WO2024007435A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2024007435A1
WO2024007435A1 PCT/CN2022/115997 CN2022115997W WO2024007435A1 WO 2024007435 A1 WO2024007435 A1 WO 2024007435A1 CN 2022115997 W CN2022115997 W CN 2022115997W WO 2024007435 A1 WO2024007435 A1 WO 2024007435A1
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WO
WIPO (PCT)
Prior art keywords
layer
signal connection
via hole
display panel
connection section
Prior art date
Application number
PCT/CN2022/115997
Other languages
English (en)
French (fr)
Inventor
张春鹏
鲜于文旭
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Publication of WO2024007435A1 publication Critical patent/WO2024007435A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display technology, and in particular to a display panel.
  • An embodiment of the present application provides a display panel for increasing the proportion of the display area of the front body of the display panel.
  • An embodiment of the present application provides a display panel, which includes:
  • the display functional layer includes a pixel driving circuit layer and a light-emitting functional layer.
  • the pixel driving circuit layer is arranged on the signal transmission layer.
  • the light-emitting functional layer is arranged on the pixel driving circuit layer away from the signal transmission layer. layer side.
  • the display panel further includes a first signal connection line, the first signal connection line is located in the display area, and the first signal connection line is used to connect all the pixel driving circuit layer and the signal transmission layer.
  • the first signal connection line includes a connected first signal connection section, a second signal connection section and a third signal connection section;
  • the display panel includes a first signal connection section. hole, a second via hole and a third via hole, the first signal connection section is arranged in the first via hole, the second signal connection section is arranged in the second via hole, and the third signal connection section is arranged in the first via hole.
  • the signal connection section is arranged in the third via hole.
  • the signal transmission layer also includes a plurality of first power supply lines, a plurality of second power supply lines, a plurality of reset signal lines, an array test pad and a plurality of fan-shaped traces; among which
  • the first signal connection section is connected to the gate drive circuit, the first power supply line, the second power supply line, the reset signal line, the array test pad or the sector line.
  • the third signal connection section is connected to the pixel driving circuit layer.
  • the display panel further includes a second signal connection line, the second signal connection line is located in the display area, and the second signal connection line is used to connect all the pixel driving circuit layer and the signal transmission layer.
  • the second signal connection line includes a connected fourth signal connection section, a fifth signal connection section and a sixth signal connection section;
  • the display panel includes a fourth signal connection section. hole, a fifth via hole and a sixth via hole, the fourth signal connection section is arranged in the fourth via hole, the fifth signal connection section is arranged in the fifth via hole, and the sixth signal connection section is arranged in the fifth via hole.
  • the signal connection section is arranged in the sixth via hole.
  • the signal transmission layer also includes a plurality of first power supply lines, a plurality of second power supply lines, a plurality of reset signal lines, an array test pad and a plurality of fan-shaped traces; among which
  • the fourth signal connection section is connected to the gate drive circuit, the first power supply line, the second power supply line, the reset signal line, the array test pad or the sector line.
  • the sixth signal connection section is connected to the pixel driving circuit layer.
  • the display panel further includes a first connection terminal and a second connection terminal;
  • the gate driving circuit includes a first thin film transistor, and the first thin film transistor includes a first thin film transistor.
  • An active layer, a first gate electrode, a second gate electrode, a first source electrode and a first drain electrode, the signal transmission layer also includes:
  • a substrate, the first active layer is disposed on the substrate;
  • a first gate insulating layer is provided on the substrate, the first gate is provided on the substrate, and the first connection terminal and the first gate are in the same layer and made of the same material;
  • a second gate insulating layer is provided on the first gate insulating layer.
  • the second gate insulating layer covers the first gate and the first connection terminal.
  • the second gate and the first connecting terminal are The second connection terminal is provided on the second gate insulating layer, and the second gate and the second connection terminal are in the same layer and made of the same material;
  • a first interlayer insulating layer is provided on the second gate insulating layer, and the first interlayer insulating layer covers the second gate and the second connection terminal, and the first via hole passes through The first interlayer insulating layer and the second gate insulating layer, the first signal connection section is connected to the first connection terminal through the first via hole, and the fourth via hole penetrates the a first interlayer insulating layer, the fourth signal connection section is connected to the second connection terminal through the fourth via hole, and the first source electrode and the first drain electrode pass through the first contact hole and the first drain electrode respectively.
  • the second contact hole is connected to the first active layer;
  • a second interlayer insulating layer is provided on the first interlayer insulating layer.
  • the second via hole penetrates the second interlayer insulating layer.
  • the second signal connection section passes through the second via hole and the second interlayer insulating layer.
  • the first signal connection section is connected, the fifth via hole penetrates the second interlayer insulating layer, and the fifth signal connection section is connected to the fourth signal connection section through the fifth via hole.
  • the display panel further includes a third connection terminal and a fourth connection terminal;
  • the pixel driving circuit layer includes:
  • a second active layer is provided on the base layer
  • An insulating layer is provided on a side of the second active layer away from the base layer, the sixth via hole penetrates the insulating layer and the base layer, and the sixth signal connection section passes through the sixth via hole and the base layer.
  • the fifth signal connection section is connected;
  • a third gate is provided on a side of the insulating layer away from the second active layer.
  • the third connection terminal is connected to the sixth signal connection section and is in the same layer and material as the third gate. ;
  • An interlayer dielectric layer is provided on a side of the third gate away from the insulating layer.
  • the third via hole penetrates the interlayer dielectric layer, the insulating layer and the base layer.
  • the third signal is connected to the second signal connection section through the third via hole;
  • the second source electrode and the second drain electrode are disposed on the interlayer dielectric layer and pass through the third contact hole and the fourth contact hole and the second contact hole respectively.
  • the active layer is connected, the fourth connection terminal and the second source are in the same layer and material, the fourth connection terminal is connected to the third signal connection section;
  • a planarization layer is provided on the interlayer dielectric layer.
  • the signal transmission layer further includes a light-shielding layer, the light-shielding layer is provided on the second interlayer insulating layer, and the light-shielding layer is connected to the second interlayer insulating layer through a via hole.
  • the first drain electrode is connected, and the orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the second active layer on the substrate.
  • the display panel further includes a seventh via hole that penetrates part of the insulation layer of the signal transmission layer;
  • the signal transmission layer also includes a connection Traces and connection pads, the connection pads are provided on a side of the substrate away from the first interlayer insulating layer, the connection traces are provided in the seventh via hole, the connection traces One end of the connection line is connected to the connection pad, and the other end of the connection line is connected to the pixel driving circuit layer.
  • the display panel further includes a driver chip, the driver chip is disposed on a side of the substrate away from the first interlayer insulating layer, and the driver chip and the Connection pad connection.
  • the pixel driving circuit layer includes a pixel driving circuit, which includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. , a second capacitor and an organic light-emitting diode; wherein the first transistor is a driving thin film transistor.
  • embodiments of the present application also provide a display panel, which includes a display area, and the display panel includes:
  • the display functional layer includes a pixel driving circuit layer and a light-emitting functional layer.
  • the pixel driving circuit layer is arranged above the signal transmission layer.
  • the light-emitting functional layer is arranged on the pixel driving circuit layer away from the signal transmission layer. layer side;
  • a driver chip is located on the side of the signal transmission layer away from the display function layer.
  • the display panel further includes a first signal connection line, the first signal connection line is located in the display area, and the first signal connection line is used to connect all the pixel driving circuit layer and the signal transmission layer.
  • the first signal connection line includes a connected first signal connection section, a second signal connection section and a third signal connection section;
  • the display panel includes a first signal connection section. hole, a second via hole and a third via hole, the first signal connection section is arranged in the first via hole, the second signal connection section is arranged in the second via hole, and the third signal connection section is arranged in the first via hole.
  • the signal connection section is arranged in the third via hole.
  • the signal transmission layer also includes a plurality of first power supply lines, a plurality of second power supply lines, a plurality of reset signal lines, an array test pad and a plurality of fan-shaped traces; among which
  • the first signal connection section is connected to the gate drive circuit, the first power supply line, the second power supply line, the reset signal line, the array test pad or the sector line.
  • the third signal connection section is connected to the pixel driving circuit layer.
  • the display panel further includes a second signal connection line, the second signal connection line is located in the display area, and the second signal connection line is used to connect all the pixel driving circuit layer and the signal transmission layer.
  • the second signal connection line includes a connected fourth signal connection section, a fifth signal connection section and a sixth signal connection section;
  • the display panel includes a fourth signal connection section. hole, a fifth via hole and a sixth via hole, the fourth signal connection section is arranged in the fourth via hole, the fifth signal connection section is arranged in the fifth via hole, and the sixth signal connection section is arranged in the fifth via hole.
  • the signal connection section is arranged in the sixth via hole.
  • the fourth signal connection section is connected to the gate drive circuit, the first power supply line, the second power supply line, and the reset signal line. lines, the array test pads or the fan-shaped traces, and the sixth signal connection section is connected to the pixel driving circuit layer.
  • An embodiment of the present application provides a display panel, which includes a display area.
  • the display panel includes a signal transmission layer and a display function layer. Among them, the signal transmission layer is located in the display area.
  • the signal transmission layer includes the gate drive circuit.
  • the display functional layer includes a pixel driving circuit layer and a light-emitting functional layer.
  • the pixel driving circuit layer is arranged on the signal transmission layer.
  • the light-emitting functional layer is arranged on the side of the pixel driving circuit layer away from the signal transmission layer.
  • the signal transmission layer for transmitting signals to the display functional layer is arranged below the display functional layer.
  • the signal transmission layer corresponds to the display area. That is to say, the embodiment of the present application will be used to drive the pixels of the display area.
  • the metal traces that provide signals from the circuit are set in the display area. Therefore, the signal transmission layer does not occupy the space of the non-display area, increasing the proportion of the display area of the display surface of the display panel, thereby realizing a narrow frame or frameless design and improving user experience.
  • Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Figure 2 is a schematic cross-sectional structural diagram of a display panel provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of the signal transmission layer provided by the embodiment of the present application.
  • Figure 4 is a schematic structural diagram of a display function layer provided by an embodiment of the present application.
  • FIG. 5 is a circuit diagram of a pixel driving circuit of the pixel driving circuit layer provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a method for manufacturing a display panel according to an embodiment of the present application.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features.
  • features defined as “first” and “second” may explicitly or implicitly include one or more of the described features.
  • “plurality” means two or more than two, unless otherwise explicitly and specifically limited.
  • An embodiment of the present application provides a display panel. Each is explained in detail below. It should be noted that the order of description of the following embodiments does not limit the preferred order of the embodiments.
  • An embodiment of the present application provides a display panel, which includes a display area.
  • the display panel includes a signal transmission layer and a display function layer.
  • the signal transmission layer is located in the display area.
  • the signal transmission layer includes the gate drive circuit.
  • the display functional layer includes a pixel driving circuit layer and a light-emitting functional layer.
  • the pixel driving circuit layer is arranged on the signal transmission layer.
  • the light-emitting functional layer is arranged on the side of the pixel driving circuit layer away from the signal transmission layer.
  • the signal transmission layer for transmitting signals to the display function layer is arranged below the display function layer.
  • the signal transmission layer corresponds to the display area, so that the signal transmission layer does not occupy the space of the non-display area and improves the display of the display panel.
  • the proportion of the display area of the screen can be adjusted to achieve a narrow bezel or bezel-less design and improve the user experience.
  • the frame area of the display panel is provided with a gate driving circuit and metal wiring.
  • the gate driving circuit and metal wiring occupy a large proportion of the front screen of the display panel, making the screen of the display panel The proportion of the display area is too small to achieve a truly narrow bezel design.
  • Embodiments of the present application provide a display panel for increasing the proportion of the display area of the display surface of the display panel, thereby achieving a narrow frame or frameless design and improving user experience.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel 100 includes a display area AA.
  • the display panel 100 includes a signal transmission layer 10 , a display function layer 20 and a first signal connection line 40 .
  • the signal transmission layer 10 is located in the display area AA.
  • the signal transmission layer 10 includes a gate driving circuit 102 .
  • the display functional layer 20 includes a pixel driving circuit layer 20a and a light-emitting functional layer 20b.
  • the pixel driving circuit layer 20a is provided above the signal transmission layer 10, and the light-emitting functional layer 20b is provided on a side of the pixel driving circuit layer 20a away from the signal transmission layer 10.
  • the first signal connection line 40 is used to connect the signal transmission layer 10 and the pixel driving circuit layer 20a.
  • the signal transmission layer 10 for transmitting signals to the display function layer 20 is arranged below the display function layer 20 so that the signal transmission layer 10 is located in the display area AA. Therefore, the signal transmission layer does not occupy the space of the non-display area. , increasing the proportion of the display area AA of the display panel 100, thereby achieving a narrow frame or frameless design, improving the taste of the display panel 100, and thus improving the user experience.
  • the first signal connection line 40 is located in the display area AA.
  • the display panel 100 further includes a second signal connection line 50 , and the second signal connection line 50 is located in the display area.
  • the second signal connection line 50 is used to connect the pixel driving circuit layer 20a and the signal transmission layer 10.
  • the first signal connection line 40 includes a first signal connection section 401, a second signal connection section 402 and a third signal connection section 403.
  • the second signal connection line 50 includes a connected fourth signal connection section 501 , a fifth signal connection section 502 and a sixth signal connection section 503 .
  • the display panel 100 includes a first via hole h1, a second via hole h2, a third via hole h3, a fourth via hole h4, a fifth via hole h5, and a sixth via hole h6.
  • the first signal connection section 401 is provided in the first via hole h1
  • the second signal connection section 402 is provided in the second via hole h2
  • the third signal connection section 403 is provided in the third via hole h3.
  • the fourth signal connection section 501 is provided in the fourth via hole h4
  • the fifth signal connection section 502 is provided in the fifth via hole h5, and the sixth signal connection section 503 is provided in the sixth via hole h6.
  • the display panel 100 further includes a first connection terminal a1, a second connection terminal a2, a third connection terminal a3 and a fourth connection terminal a4.
  • the first connection terminal a1 is connected to the first signal connection section 401
  • the fourth connection terminal a4 is connected to the third signal connection section 403
  • the second connection terminal a2 is connected to the fourth signal connection section 501
  • the third connection terminal a3 and The sixth signal connection section 503 is connected.
  • the signal transmission layer 10 also includes a plurality of first power traces 110 , a plurality of second power traces 111 , a plurality of reset signal traces 113 , array test pads 114 and a plurality of sector traces 115 .
  • the first signal connection section 401 is connected to the gate driving circuit 102, the first power supply line 110, the second power supply line 111, the reset signal line 113, the array test pad 114 or the sector line 115.
  • the third signal connection section 403 is connected to the pixel driving circuit layer 20a.
  • the output ends of the gate drive circuit 102, the first power supply line 110, the second power supply line 111, the reset signal line 113, the array test pad 114 or the sector line 115 are connected to the first connection terminal a1
  • the corresponding signal is transmitted through the first signal connection line 40
  • the fourth connection terminal a4 is connected to the corresponding transistor or metal line of the pixel driving circuit layer 20a, thereby realizing signal transmission.
  • the fourth signal connection section 501 connects the gate driving circuit 102 , the first power supply trace 110 , the second power supply trace 111 , the reset signal trace 113 , the array test pad 114 or the sector trace 115 .
  • the sixth signal connection section 503 is connected to the pixel driving circuit layer 20a. Specifically, the output ends of the gate drive circuit 102, the first power supply line 110, the second power supply line 111, the reset signal line 113, the array test pad 114 or the sector line 115 are connected to the second connection terminal a2, The corresponding signal is transmitted through the second signal connection line 50, and the third connection terminal a3 is connected to the corresponding transistor or metal line of the pixel driving circuit layer 20a, thereby realizing signal transmission.
  • the first power supply line 110, the second power supply line 111, the reset signal line 113, the array test pad 114 and the plurality of sector lines 115 are all arranged below the display function layer 20. And all correspond to the display area AA. At this time, there is no need to set up a non-display area for placing metal traces, and the frameless design of the display panel 100 is realized, a true full screen is realized, and the user experience is greatly improved.
  • the fan-shaped traces 115 may be metal traces used to lead out the data lines of the pixel driving circuit layer, but are not limited to this.
  • the gate driving circuit 102 includes a first thin film transistor structure 102a.
  • the first thin film transistor structure 102a includes a first active layer 1021, a first gate electrode 1022, a second gate electrode 1023, a first source electrode 1024 and a first drain electrode 1025.
  • the signal transmission layer 10 also includes a substrate 101, a first gate insulating layer 103, a second gate insulating layer 104, a first interlayer insulating layer 105 and a second interlayer insulating layer 106.
  • the first gate insulating layer 103 is provided on the substrate 101 .
  • the first gate electrode 1022 is disposed on the substrate 101, and the first connection terminal a1 and the first gate electrode 1022 are in the same layer and made of the same material.
  • the second gate insulating layer 104 is provided on the first gate insulating layer 103 .
  • the second gate insulating layer 104 covers the first gate 1022 and the first connection terminal a1.
  • the second gate electrode 1023 and the second connection terminal a2 are disposed on the second gate insulating layer 104.
  • the second gate electrode 1023 and the second connection terminal a2 are of the same layer and made of the same material.
  • the first interlayer insulating layer 105 is disposed on the second gate insulating layer 104, and the first interlayer insulating layer 105 covers the second gate 1023 and the second connection terminal a2.
  • the first via hole h1 penetrates the first interlayer insulating layer 105 and the second gate insulating layer 104, and the first signal connection section 401 is connected to the first connection terminal a1 through the first via hole h1.
  • the fourth via hole h4 penetrates the first interlayer insulating layer 105, and the fourth signal connection section 501 is connected to the second connection terminal a2 through the fourth via hole h4.
  • the first source electrode 1024 and the first drain electrode 1025 are connected to the first active layer 1021 through the first contact hole cnt1 and the second contact hole cnt2 respectively.
  • the second interlayer insulating layer 106 is disposed on the first interlayer insulating layer 105 , and the second via hole h2 penetrates the second interlayer insulating layer 106 .
  • the second signal connection section 402 is connected to the first signal connection section 401 through the second via hole h2.
  • the fifth via hole h5 penetrates the second interlayer insulating layer 106, and the fifth signal connection section is connected to the fourth signal connection section through the fifth via hole.
  • the thin film transistor of the gate driving circuit 102 may be a bottom gate thin film transistor, a top gate thin film transistor or a double gate thin film transistor.
  • the gate driving circuit 102 is a double gate thin film transistor.
  • a gate type thin film transistor is described as an example, but is not limited thereto.
  • the first active layer 1021 is a low temperature polysilicon active layer.
  • Low Temperature Polysilicon (Low Temperature Polysilicon) Poly-Silicon (LTPS) technology is another new technology in the field of flat panel displays, the next generation technology after amorphous silicon (a-Si).
  • Low-temperature polysilicon display panels have the advantages of faster electron mobility, smaller film circuit area, higher resolution, lower power consumption, and higher stability.
  • FIG. 4 is a schematic structural diagram of a display function layer provided by an embodiment of the present application.
  • the pixel driving circuit layer 20a includes a base layer 201, a second active layer 202, a third gate electrode 204, an insulating layer 203, a third gate electrode 204, an interlayer dielectric layer 205, a second source electrode 206, a second drain electrode 207 and Planarization layer 208.
  • the base layer 201 is disposed on a side of the second interlayer insulating layer 106 away from the first interlayer insulating layer 105 .
  • the second active layer 202 is disposed on a side of the base layer 201 away from the second interlayer insulating layer 106, and the orthographic projection of the second active layer 202 on the substrate 101 is located within the orthographic projection of the light shielding layer 108 and the substrate 101. .
  • the insulating layer 203 is disposed on a side of the second active layer 202 away from the base layer 201 .
  • the sixth via hole h6 penetrates the insulating layer 203 and the base layer 201 , and the sixth signal connection section 503 is connected to the fifth signal connection section 502 through the sixth via hole h6 .
  • the third gate 204 is disposed on a side of the insulating layer 203 away from the second active layer 202 .
  • the third connection terminal a3 is connected to the sixth signal connection section 503 and is in the same layer and material as the third gate electrode 204 .
  • the interlayer dielectric layer 205 is disposed on the side of the third gate 204 away from the insulating layer 203 .
  • the third via hole h3 penetrates the interlayer dielectric layer 205, the insulating layer 203 and the base layer 201, and the third signal connection section 403 is connected to the second signal connection section 402 through the third via hole h3.
  • the pixel driving circuit layer 20a has a third contact hole cnt3 and a fourth contact hole cnt4.
  • the third contact hole cnt3 and the fourth contact hole cnt4 penetrate the interlayer dielectric layer 205 .
  • the second source electrode 206 and the second drain electrode 207 are disposed on the interlayer dielectric layer 205 and are connected to the second active layer 202 through the third contact hole cnt3 and the fourth contact hole cnt4 respectively.
  • the fourth connection terminal a4 and the second source electrode 206 are in the same layer and made of the same material, and the fourth connection terminal a4 is connected to the third signal connection section 403 .
  • the planarization layer 208 is disposed on the interlayer dielectric layer 205 and covers the second source electrode 206 and the second drain electrode 207 .
  • the first signal connection line 40 and the second signal connection line 50 in the embodiment of the present application are formed in the process of forming the metal wiring required for the display panel 100. There is no need to introduce additional processes and reduce the cost of the display panel 100. production costs.
  • the second active layer 202 is a metal oxide active layer.
  • the material of the second active layer 202 may be selected from indium gallium zinc oxide.
  • Metal oxide semiconductors have the characteristics of large mobility, high on-state current, better switching characteristics, and better uniformity. They can be suitable for applications that require fast response and large current, such as high frequency, high resolution, and large size. Displays and organic light-emitting displays, etc.
  • the light-emitting functional layer 20b includes an anode 210, a pixel definition layer 209, a light-emitting layer 211 and a cathode 212.
  • the anode 210 is connected to the second drain electrode 207 through a via hole.
  • the pixel definition layer 209 has openings, and the openings of the pixel definition layer 209 expose the surface of the anode 210 .
  • the light emitting layer 211 is disposed within the opening of the pixel defining layer 209 .
  • the cathode 212 is disposed on the side of the light-emitting layer 211 away from the anode 210 .
  • the signal transmission layer 10 further includes a light-shielding layer 108 .
  • the light-shielding layer 108 is disposed on a side of the second interlayer insulating layer 106 away from the first interlayer insulating layer 105 , and the light-shielding layer 108 is connected to the first drain electrode 1025 through a via hole.
  • the orthographic projection of the light shielding layer 108 on the substrate 101 covers the orthographic projection of the second active layer 202 on the substrate 101 .
  • the light-shielding layer 108 can be used to reduce the electromagnetic interference of the signal transmission layer 10 to the display function layer 20, and can block the interference caused by the substrate 101.
  • the external light incident from the side improves the stability of the display panel 100 .
  • the display panel 100 further includes a seventh via hole h7 that penetrates part of the insulating layer of the signal transmission layer 10 .
  • the signal transmission layer 10 also includes connection traces 107 and connection pads 109 .
  • the connection pads 109 are provided on a side of the substrate 101 away from the first interlayer insulating layer 105 .
  • the connection trace 107 is provided in the seventh via hole h7, one end of the connection trace h7 is connected to the connection pad 109, and the other end of the connection trace 107 is connected to the pixel driving circuit layer 20a.
  • the seventh via hole h7 penetrates the first interlayer insulating layer 106 , the second gate insulating layer 104 , the first gate insulating layer 103 and the substrate 101 .
  • connection traces 107 are used to connect the data lines on the pixel driving circuit layer 20a to the connection pads 109, but are not limited thereto.
  • the display panel 100 also includes a driver chip 30 .
  • the driver chip 30 is provided with a connection pad 109 on a side away from the substrate 101 .
  • the driving chip 30 is used to drive the display panel 100 to emit light.
  • the driver chip 30 is bound to the side of the signal transmission layer 10 away from the display function layer 20 , that is, the driver chip 30 is bound to the back side.
  • the driver chip 30 is bound to the display panel by bending. Compared with the arrangement method on the back of the display panel 100 , the frame of the display panel 100 is further reduced, and the proportion of the display area AA of the display surface of the display panel 100 is increased.
  • connection pads 109 include chip connection pads and test connection pads.
  • the embodiments of the present application do not limit the arrangement of the connection pads and the test connection pads.
  • the gate driving circuit 102 corresponds to the outer edge of the display area AA.
  • the first power supply trace 110 is provided outside the gate driving circuit 102 .
  • the second power trace 111 is provided on a side close to the connection pad 109 .
  • the reset signal wiring 113 is provided inside the gate driving circuit 102 .
  • the array test pad 114 is disposed on a side of the second power trace 111 away from the connection pad 109 .
  • the fan-shaped trace 115 is provided between the second power trace 111 and the connection pad 109 for connecting the second power trace 111 and the connection pad 109 .
  • the substrate 101 includes an inorganic layer 1011, a first flexible substrate layer, a first barrier layer 1013 and a second barrier layer 1014 that are stacked in sequence.
  • the first active layer 1021 is provided on the second barrier layer 1014.
  • the connection pad 109 is provided on a side of the inorganic layer 1011 away from the first flexible substrate layer 1012 .
  • the material of the first flexible substrate layer 1012 may include PI (polyimide), PET (polyethylene naphthalate), PEN (polyethylene naphthalate), PC (polyethylene naphthalate), Carbonate), PES (polyethersulfone), PAR (aromatic fluorotoluene containing polyarylate) or PCO (polycyclic olefin).
  • the inorganic layer 1011, the first barrier layer 1013, and the second barrier layer 1014 are composed of one or a stack structure of two or more of silicon-containing nitride, silicon-containing oxide, or silicon-containing oxynitride.
  • the pixel driving circuit layer 20a includes a pixel driving circuit
  • the pixel driving circuit may include a 3T1C type pixel driving circuit, a 4T2C type pixel driving circuit, a 5T2C type pixel driving circuit, or a 6T1C type pixel driving circuit.
  • FIG. 5 is a circuit diagram of a pixel driving circuit of the pixel driving circuit layer provided by an embodiment of the present application.
  • the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, a second capacitor C2, and an organic light emitting diode OLED.
  • Each transistor is a P-type thin film transistor.
  • the first transistor T1 is a driving thin film transistor.
  • the gate of the first transistor T1 is electrically connected to one end of the first capacitor (C1) through the first node (A).
  • the source of the first transistor T1 is connected to the second power line. 111 positive voltage.
  • the drain of the first transistor T1 is electrically connected to the anode of the organic light emitting diode OLED.
  • the gate of the second transistor T2 is connected to the nth scan signal SCAN(n) corresponding to the row of the pixel driving circuit, the source of the second transistor T2 is connected to the data signal data, and the drain of the second transistor T2 is connected to the second scan signal SCAN(n).
  • Node B is electrically connected to the other end of the first capacitor C1.
  • the gate of the third transistor T3 is connected to the n+1 scan signal SCAN(n+1) corresponding to the next row of the pixel driving circuit, and the source of the third transistor T3 is electrically connected to the second node B.
  • the drain is connected to the base reference voltage Vref.
  • the gate of the fourth transistor T4 is connected to the nth scan signal SCAN(n) corresponding to the row of the pixel driving circuit.
  • the source of the fourth transistor T4 is electrically connected to the first node A.
  • the drain of the fourth transistor T4 Electrically connected to the anode of the organic light emitting diode OLED.
  • One end of the first capacitor C1 is electrically connected to the first node A, and the other end is electrically connected to the second node B.
  • One end of the second capacitor C2 is electrically connected to the first node A, and the other end is electrically connected to the second power trace 111 .
  • the anode of the organic light-emitting diode OLED is electrically connected to the drain of the first transistor T1 and the drain of the fourth transistor T4, and the cathode is electrically connected to the first power trace 110.
  • the pixel driving circuit provided by the present invention adopts a 4T2C structure. Compared with the existing pixel driving circuit, it only needs to set scanning signals to control the corresponding thin film transistors, which not only plays a compensation role, but also reduces the number of control signals and simplifies The circuit structure is simplified and the cost is reduced.
  • inventions of the present application also provide a method for manufacturing a display panel, please refer to Figure 6 .
  • the manufacturing method of the display panel includes the following steps:
  • Step B001 Provide a signal transmission layer, which is located in the display area of the display panel.
  • the step of providing the signal transmission layer includes providing a flexible substrate, and then providing the connection pad 109 on the flexible substrate.
  • the inorganic layer 1011 and the first flexible substrate layer 1012 are sequentially provided on the flexible substrate 1015.
  • the gate driving circuit 102 is disposed on the first flexible substrate layer 1012 to form a signal transmission layer.
  • the signal transmission layer further includes a plurality of first power supply traces, a plurality of second power supply traces, a plurality of reset signal traces, array test pads and a plurality of sector traces.
  • Step B002 Set a display function layer on the signal transmission layer.
  • the display function layer includes a pixel driving circuit layer and a light-emitting function layer.
  • the pixel driving circuit layer is arranged on the signal transmission layer.
  • the light-emitting functional layer is arranged on the side of the pixel driving circuit layer away from the signal transmission layer.
  • step B003 the flexible substrate 1015 is peeled off using laser peeling, mechanical peeling, dissolution peeling, or other methods to expose the connection pad.
  • Step B003 Bind the driver chip to the connection pad to complete the production of the display panel.

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Abstract

一种显示面板（100），显示面板（100）包括显示区（AA）。显示面板（100）包括信号传输层（10）和显示功能层（20）。信号传输层（10）位于显示区（AA）。信号传输层（10）包括栅极驱动电路（102）。显示功能层（20）包括像素驱动电路层（20a）和发光功能层（20b）。像素驱动电路层（20a）设置在信号传输层（10）上方。发光功能层（20b）设置在像素驱动电路层（20a）远离信号传输层（10）的一面。

Description

显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板。
 背景技术
随着电子产品的不断更新换代，大屏的电子产品越来越受到用户的青睐。目前，市场上的电子产品总会存在或大或小的四周边框，电子产品的发展趋势要求其边框应该越做越窄以致达到无边框的效果。全面屏电子产品凭借其超高的屏占比和极好的用户体验感，成为时下最热门的技术之一。但在实际生产过程中，很难满足无边框的要求，造成屏幕显示区域占机身正面的占比较小，影响用户的体验感。
 技术问题
本申请实施例提供一种显示面板，用于提高显示面板的正面机身的显示区的占比。
 技术解决方案
本申请实施例提供一种显示面板，所述显示面板包括：
信号传输层，位于所述显示区，所述信号传输层包括栅极驱动电路；
显示功能层，所述显示功能层包括像素驱动电路层和发光功能层，像素驱动电路层设置在所述信号传输层上，所述发光功能层设置在所述像素驱动电路层远离所述信号传输层的一面。
可选的，在本申请提供的一些实施例中，所述显示面板还包括第一信号连接线，所述第一信号连接线位于所述显示区，所述第一信号连接线用于连接所述像素驱动电路层和所述信号传输层。
可选的，在本申请提供的一些实施例中，所述第一信号连接线包括连接的第一信号连接段、第二信号连接段和第三信号连接段；所述显示面板包括第一过孔、第二过孔和第三过孔，所述第一信号连接段设置在所述第一过孔内，所述第二信号连接段设置在所述第二过孔内，所述第三信号连接段设置在所述第三过孔内。
可选的，在本申请提供的一些实施例中，所述信号传输层还包括多条第一电源走线、多条第二电源走线、多条复位信号走线、阵列测试焊盘和多条扇形走线；其中
所述第一信号连接段连接所述栅极驱动电路、所述第一电源走线、所述第二电源走线、所述复位信号走线、所述阵列测试焊盘或所述扇形走线，所述第三信号连接段连接所述像素驱动电路层。
可选的，在本申请提供的一些实施例中，所述显示面板还包括第二信号连接线，所述第二信号连接线位于所述显示区，所述第二信号连接线用于连接所述像素驱动电路层和所述信号传输层。
可选的，在本申请提供的一些实施例中，所述第二信号连接线包括连接的第四信号连接段、第五信号连接段和第六信号连接段；所述显示面板包括第四过孔、第五过孔和第六过孔，所述第四信号连接段设置在所述第四过孔内，所述第五信号连接段设置在所述第五过孔内，所述第六信号连接段设置在所述第六过孔内。
可选的，在本申请提供的一些实施例中，所述信号传输层还包括多条第一电源走线、多条第二电源走线、多条复位信号走线、阵列测试焊盘和多条扇形走线；其中
所述第四信号连接段连接所述栅极驱动电路、所述第一电源走线、所述第二电源走线、所述复位信号走线、所述阵列测试焊盘或所述扇形走线，所述第六信号连接段连接所述像素驱动电路层。
可选的，在本申请提供的一些实施例中，所述显示面板还包括第一连接端子和第二连接端子；所述栅极驱动电路包括第一薄膜晶体管，所述第一薄膜晶体管包括第一有源层、第一栅极、第二栅极、第一源极和第一漏极，所述信号传输层还包括：
衬底，所述第一有源层设置在所述衬底上；
第一栅极绝缘层，设置在所述衬底上，所述第一栅极设置在所述衬底上，且所述第一连接端子和所述第一栅极同层且同材料；
第二栅极绝缘层，设置在所述第一栅极绝缘层上，所述第二栅极绝缘层覆盖所述第一栅极和所述第一连接端子，所述第二栅极和所述第二连接端子设置在所述第二栅极绝缘层上，所述第二栅极和所述第二连接端子同层且同材料；
第一层间绝缘层，设置在所述第二栅极绝缘层上，且所述第一层间绝缘层覆盖所述第二栅极和所述第二连接端子，所述第一过孔贯穿所述第一层间绝缘层和所述第二栅极绝缘层，所述第一信号连接段通过所述第一过孔与所述第一连接端子连接，所述第四过孔贯穿所述第一层间绝缘层，所述第四信号连接段通过所述第四过孔与所述第二连接端子连接，所述第一源极和所述第一漏极分别通过第一接触孔和第二接触孔和所述第一有源层连接；
第二层间绝缘层，设置在所述第一层间绝缘层上，所述第二过孔贯穿所述第二层间绝缘层，所述第二信号连接段通过所述第二过孔和第一信号连接段连接，所述第五过孔贯穿所述第二层间绝缘层，所述第五信号连接段通过所述第五过孔和所述第四信号连接段连接。
可选的，在本申请提供的一些实施例中，所述显示面板还包括第三连接端子和第四连接端子；所述像素驱动电路层包括：
基底层，设置在所述第二层间绝缘层上；
第二有源层，设置在所述基底层上；
绝缘层，设置在所述第二有源层远离所述基底层的一面，所述第六过孔贯穿所述绝缘层和基底层，所述第六信号连接段通过所述第六过孔和所述第五信号连接段连接；
第三栅极，设置在所述绝缘层远离所述第二有源层的一面，所述第三连接端子和所述第六信号连接段连接且与所述第三栅极同层且同材料；
层间介质层，设置在所述第三栅极远离所述绝缘层的一面，所述第三过孔贯穿所述层间介质层、所述绝缘层和所述基底层，所述第三信号连接段通过所述第三过孔和所述第二信号连接段连接；
第二源极和第二漏极，所述第二源极和所述第二漏极设置在所述层间介质层上，并分别通过第三接触孔和第四接触孔和所述第二有源层连接，所述第四连接端子和所述第二源极同层且材料，所述第四连接端子和所述第三信号连接段连接；
平坦化层，所述平坦化层设置在所述层间介质层上。
可选的，在本申请提供的一些实施例中，所述信号传输层还包括遮光层，所述遮光层设置在所述第二层间绝缘层上，所述遮光层通过过孔与所述第一漏极连接，且所述遮光层于所述衬底上的正投影覆盖所述第二有源层于所述衬底上的正投影。
可选的，在本申请提供的一些实施例中，所述显示面板还包括第七过孔，所述第七过孔贯穿所述信号传输层的部分绝缘层；所述信号传输层还包括连接走线和连接焊盘，所述连接焊盘设置在所述衬底远离所述第一层间绝缘层的一面，所述连接走线设置在所述第七过孔内，所述连接走线的一端连接所述连接焊盘，所述连接走线的另一端连接所述像素驱动电路层。
可选的，在本申请提供的一些实施例中，所述显示面板还包括驱动芯片，所述驱动芯片设置在衬底远离所述第一层间绝缘层的一面，所述驱动芯片和所述连接焊盘连接。
可选的，在本申请提供的一些实施例中，所述像素驱动电路层包括像素驱动电路，所述像素驱动电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一电容、第二电容及有机发光二极管；其中，所述第一晶体管为驱动薄膜晶体管。
相应的，本申请实施例还提供一种显示面板，所述显示面板包括显示区，所述显示面板包括：
信号传输层，位于所述显示区，所述信号传输层包括栅极驱动电路；
显示功能层，所述显示功能层包括像素驱动电路层和发光功能层，像素驱动电路层设置在所述信号传输层上方，所述发光功能层设置在所述像素驱动电路层远离所述信号传输层的一面；
驱动芯片，所述驱动芯片位于所述信号传输层远离所述显示功能层的一侧。
可选的，在本申请提供的一些实施例中，所述显示面板还包括第一信号连接线，所述第一信号连接线位于所述显示区，所述第一信号连接线用于连接所述像素驱动电路层和所述信号传输层。
可选的，在本申请提供的一些实施例中，所述第一信号连接线包括连接的第一信号连接段、第二信号连接段和第三信号连接段；所述显示面板包括第一过孔、第二过孔和第三过孔，所述第一信号连接段设置在所述第一过孔内，所述第二信号连接段设置在所述第二过孔内，所述第三信号连接段设置在所述第三过孔内。
可选的，在本申请提供的一些实施例中，所述信号传输层还包括多条第一电源走线、多条第二电源走线、多条复位信号走线、阵列测试焊盘和多条扇形走线；其中
所述第一信号连接段连接所述栅极驱动电路、所述第一电源走线、所述第二电源走线、所述复位信号走线、所述阵列测试焊盘或所述扇形走线，所述第三信号连接段连接所述像素驱动电路层。
可选的，在本申请提供的一些实施例中，所述显示面板还包括第二信号连接线，所述第二信号连接线位于所述显示区，所述第二信号连接线用于连接所述像素驱动电路层和所述信号传输层。
可选的，在本申请提供的一些实施例中，所述第二信号连接线包括连接的第四信号连接段、第五信号连接段和第六信号连接段；所述显示面板包括第四过孔、第五过孔和第六过孔，所述第四信号连接段设置在所述第四过孔内，所述第五信号连接段设置在所述第五过孔内，所述第六信号连接段设置在所述第六过孔内。
可选的，在本申请提供的一些实施例中，所述第四信号连接段连接所述栅极驱动电路、所述第一电源走线、所述第二电源走线、所述复位信号走线、所述阵列测试焊盘或所述扇形走线，所述第六信号连接段连接所述像素驱动电路层。
 有益效果
本申请实施例提供一种显示面板，显示面板包括显示区。显示面板包括信号传输层和显示功能层。其中，信号传输层位于显示区。信号传输层包括栅极驱动电路。显示功能层包括像素驱动电路层和发光功能层。像素驱动电路层设置在信号传输层上。发光功能层设置在像素驱动电路层远离信号传输层的一面。本申请实施例将用于向显示功能层传输信号的信号传输层设置在显示功能层的下方，信号传输层对应于显示区，也就是说，本申请实施例将用于为显示区的像素驱动电路提供信号的金属走线设置在显示区内，因此，信号传输层不占用非显示区域的空间，提高显示面板的显示面的显示区的占比，从而实现窄边框或无边框的设计，提高用户体验。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板一种结构示意图；
图2为本申请实施例提供的显示面板的一种剖面结构示意图；
图3为本申请实施例提供的信号传输层的一种结构示意图；
图4为本申请实施例提供的显示功能层的一种结构示意图；
图5为本申请实施例提供的像素驱动电路层的一种像素驱动电路的电路图。
图6为本申请实施例提供的显示面板的制作方法的示意图。
 本发明的实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述，请参照附图中的图式，其中相同的组件符号代表相同的组件，以下的说明是基于所示的本申请具体实施例，其不应被视为限制本申请未在此详述的其他具体实施例。本说明书所使用的词语“实施例”意指实例、示例或例证。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
本申请实施例提供一种显示面板。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
本申请实施例提供一种显示面板，显示面板包括显示区。显示面板包括信号传输层和显示功能层。其中，信号传输层位于显示区。信号传输层包括栅极驱动电路。显示功能层包括像素驱动电路层和发光功能层。像素驱动电路层设置在信号传输层上。发光功能层设置在像素驱动电路层远离信号传输层的一面。本申请实施例将用于向显示功能层传输信号的信号传输层设置在显示功能层的下方，信号传输层对应于显示区，使得信号传输层不占用非显示区域的空间，提高显示面板的显示面的显示区的占比，从而实现窄边框或无边框的设计，提高用户体验。
下面通过具体实施例对本申请提供的显示面板进行详细的阐述。
在已知技术中，显示面板的边框区设置有栅极驱动电路及金属走线等，栅极驱动电路及金属走线占据了显示面板的正面屏幕较大的占比，使得显示面板的屏幕的显示区的占比偏小，无法实现真正的窄边框设计。
本申请实施例提供一种显示面板，用于提高显示面板的显示面的显示区的占比，从而实现窄边框或无边框的设计，提高用户体验。
请结合图1和图2，图1为本申请实施例提供的显示面板一种结构示意图。图2为本申请实施例提供的显示面板的一种剖面结构示意图。显示面板100包括显示区AA。显示面板100包括信号传输层10、显示功能层20和第一信号连接线40。其中，信号传输层10位于显示区AA。信号传输层10包括栅极驱动电路102。显示功能层20包括像素驱动电路层20a和发光功能层20b，像素驱动电路层20a设置在信号传输层10上方，发光功能层20b设置在像素驱动电路层20a远离信号传输层10的一面。第一信号连接线40用于连接信号传输层10和像素驱动电路层20a。
本申请实施例将用于向显示功能层20传输信号的信号传输层10设置在显示功能层20的下方，使得信号传输层10位于显示区AA，因此，信号传输层不占用非显示区域的空间，提高了显示面板100的显示区AA的占比，从而实现窄边框或无边框的设计，提升显示面板100的品味，从而提高用户体验。
其中，第一信号连接线40位于显示区AA。
在一些实施例中，显示面板100还包括第二信号连接线50，第二信号连接线50位于显示区。第二信号连接线50用于连接像素驱动电路层20a和信号传输层10。
具体的，第一信号连接线40包括第一信号连接段401、第二信号连接段402和第三信号连接段403。第二信号连接线50包括连接的第四信号连接段501、第五信号连接段502和第六信号连接段503。
显示面板100包括第一过孔h1、第二过孔h2、第三过孔h3、第四过孔h4、第五过孔h5和第六过孔h6。第一信号连接段401设置在第一过孔h1内，第二信号连接段402设置在第二过孔h2内，第三信号连接段403设置在第三过孔h3内。第四信号连接段501设置在第四过孔h4内，第五信号连接段502设置在第五过孔h5内，第六信号连接段503设置在第六过孔h6内。
显示面板100还包括第一连接端子a1、第二连接端子a2、第三连接端子a3和第四连接端子a4。其中，第一连接端子a1和第一信号连接段401连接，第四连接端子a4和第三信号连接段403连接，第二连接端子a2和第四信号连接段501连接，第三连接端子a3和第六信号连接段503连接。
信号传输层10还包括多条第一电源走线110、多条第二电源走线111、多条复位信号走线113、阵列测试焊盘114和多条扇形走线115。其中，第一信号连接段401连接栅极驱动电路102、第一电源走线110、第二电源走线111、复位信号走线113、阵列测试焊盘114或扇形走线115。第三信号连接段403连接像素驱动电路层20a。具体的，栅极驱动电路102、第一电源走线110、第二电源走线111、复位信号走线113、阵列测试焊盘114或扇形走线115的输出端和第一连接端子a1连接，使得相应信号通过第一信号连接线40传输，而第四连接端子a4和像素驱动电路层20a对应的晶体管或者金属走线连接，从而实现信号传输。
在一些实施例中，第四信号连接段501连接栅极驱动电路102、第一电源走线110、第二电源走线111、复位信号走线113、阵列测试焊盘114或扇形走线115。第六信号连接段503连接像素驱动电路层20a。具体的，栅极驱动电路102、第一电源走线110、第二电源走线111、复位信号走线113、阵列测试焊盘114或扇形走线115的输出端和第二连接端子a2连接，使得相应信号通过第二信号连接线50传输，而第三连接端子a3和像素驱动电路层20a对应的晶体管或者金属走线连接，从而实现信号传输。
在本申请实施例中，将第一电源走线110、第二电源走线111、复位信号走线113、阵列测试焊盘114和多条扇形走线115均设置与显示功能层20的下方，且均对应于显示区AA，此时，无需设置用于放置金属走线的非显示区域，实现了显示面板100的无边框设计，实现了真正的全面屏，大大提高了用户体验。
需要说明的是，在本申请实施例中，扇形走线115可以是用于将像素驱动电路层的数据线引出的金属走线，但不限于此。
具体的，请参阅图3，图3为本申请实施例提供的信号传输层的一种结构示意图。栅极驱动电路102包括第一薄膜晶体管结构102a。第一薄膜晶体管结构102a包括第一有源层1021、第一栅极1022、第二栅极1023、第一源极1024和第一漏极1025。信号传输层10还包括衬底101、第一栅极绝缘层103、第二栅极绝缘层104、第一层间绝缘层105和第二层间绝缘层106。
第一栅极绝缘层103设置在衬底101上。第一栅极1022设置在衬底101上，且第一连接端子a1和第一栅极1022同层且同材料。
第二栅极绝缘层104设置在第一栅极绝缘层103上。第二栅极绝缘层104覆盖第一栅极1022和第一连接端子a1。第二栅极1023和第二连接端子a2设置在第二栅极绝缘层104上，第二栅极1023和第二连接端子a2同层且同材料。
第一层间绝缘层105设置在第二栅极绝缘层104上，且第一层间绝缘层105覆盖第二栅极1023和第二连接端子a2。第一过孔h1贯穿第一层间绝缘层105和第二栅极绝缘层104，第一信号连接段401通过第一过孔h1与第一连接端子a1连接。第四过孔h4贯穿第一层间绝缘层105，第四信号连接段501通过第四过孔h4与第二连接端子a2连接。
第一源极1024和第一漏极1025分别通过第一接触孔cnt1和第二接触孔cnt2和第一有源层1021连接。
第二层间绝缘层106设置在第一层间绝缘层105上，第二过孔h2贯穿第二层间绝缘层106。第二信号连接段402通过第二过孔h2和第一信号连接段401连接。第五过孔h5贯穿第二层间绝缘层106，第五信号连接段通过所述第五过孔和所述第四信号连接段连接。
需要说明的是，在本申请实施例中，栅极驱动电路102的薄膜晶体管可以是底栅型薄膜晶体管、顶栅型薄膜晶体管或双栅型薄膜晶体管，本申请以栅极驱动电路102为双栅型薄膜晶体管为示例进行说明，但不限于此。
在一些实施例中，第一有源层1021为低温多晶硅有源层，低温多晶硅(Low Temperature Poly-Silicon，LTPS)技术是平板显示器领域中的又一新技术，继非晶硅(a-Si)之后的下一代技术。低温多晶硅型的显示面板具有电子迁移率更快、薄膜电路面积更小、分辨率更高、功耗更低、稳定性更高等优点。
请结合图2和图4，图4为本申请实施例提供的显示功能层的一种结构示意图。像素驱动电路层20a包括基底层201、第二有源层202、第三栅极204绝缘层203、第三栅极204、层间介质层205、第二源极206、第二漏极207和平坦化层208。
其中，基底层201设置在第二层间绝缘层106远离第一层间绝缘层105的一面。第二有源层202设置在基底层201远离第二层间绝缘层106的一面，且第二有源层202于衬底101上的正投影位于遮光层108与衬底101上的正投影内。
绝缘层203设置在第二有源层202远离基底层201的一面。第六过孔h6贯穿绝缘层203和基底层201，第六信号连接段503通过第六过孔h6和第五信号连接段502连接。
第三栅极204设置在绝缘层203远离第二有源层202的一面。第三连接端子a3和第六信号连接段503连接且与第三栅极204同层且同材料。
层间介质层205设置在第三栅极204远离绝缘层203的一面。第三过孔h3贯穿层间介质层205、绝缘层203和基底层201，第三信号连接段403通过第三过孔h3和第二信号连接段402连接。
像素驱动电路层20a具有第三接触孔cnt3和第四接触孔cnt4。第三接触孔cnt3和第四接触孔cnt4贯穿层间介质层205。
第二源极206和第二漏极207设置在层间介质层205上，并分别通过第三接触孔cnt3和第四接触孔cnt4和第二有源层202连接。第四连接端子a4和第二源极206同层且材料，第四连接端子a4和第三信号连接段403连接。
平坦化层208设置在所述层间介质层205上，并覆盖第二源极206和第二漏极207。
在本申请实施例中，分别对不同的膜层进行打孔，使得在形成金属层的同时不同的过孔内形成对应的连接信号段，由多个信号连接段连接组成信号连接走线。即，本申请实施例的第一信号连接线40和第二信号连接线50均在形成显示面板100所需的金属走线的过程中形成的，无需再引入额外的制程，降低了显示面板100的生产成本。
在一些实施例中，第二有源层202为金属氧化物有源层。其中，第二有源层202的材料可以选自铟镓锌氧化物。
金属氧化物半导体具有迁移率大、开态电流高、开关特性更优、均匀性更好的特点，可以适用于需要快速响应和较大电流的应用，如高频、高分辨率、大尺寸的显示器以及有机发光显示器等。
发光功能层20b包括阳极210、像素定义层209、发光层211和阴极212。其中，阳极210通过过孔与第二漏极207连接。像素定义层209具有开口，像素定义层209的开口暴露阳极210的表面。发光层211设置在像素定义层209的开口内。阴极212设置在发光层211远离阳极210的一面。
在一些实施例中，信号传输层10还包括遮光层108。遮光层108设置在第二层间绝缘层106远离第一层间绝缘层105的一面，且遮光层108通过过孔和第一漏极1025连接。遮光层108于衬底101上的正投影覆盖第二有源层202于衬底101上的正投影。在本申请实施例中，通过设置与第一漏极1025连接的遮光层108，遮光层108可以用于减小信号传输层10对显示功能层20的电磁干扰，且可以遮挡由衬底101一侧射入的外界光，提高显示面板100的稳定性。
在一些实施例中，显示面板100还包括第七过孔h7，第七过孔h7贯穿信号传输层10的部分绝缘层。信号传输层10还包括连接走线107和连接焊盘109，连接焊盘109设置在衬底101远离第一层间绝缘层105的一面。连接走线107设置在第七过孔h7内，连接走线h7的一端与连接焊盘109连接，连接走线107的另一端连接像素驱动电路层20a。
在一些实施例中，第七过孔h7贯穿第一层间绝缘层106、第二栅极绝缘层104、第一栅极绝缘层103和衬底101。
在一些实施例中，连接走线107用于将像素驱动电路层20a上的数据线接入连接焊盘109，但不限于此。
显示面板100还包括驱动芯片30。驱动芯片30设置连接焊盘109远离衬底101的一面。驱动芯片30用于驱动显示面板100发光。
在本申请实施例中，将驱动芯片30绑定于信号传输层10远离显示功能层20的一面，即将驱动芯片30绑定于背面，与现有技术通过弯折将驱动芯片绑定至显示面板的背面的设置方式相比，进一步减小了显示面板100的边框，提高了显示面板100的显示面的显示区AA的占比。
需要说明的是，在一些实施例中，连接焊盘109包括芯片连接焊盘和测试连接焊盘。本申请实施例不限定连接焊盘和测试连接焊盘的排列方式。
请继续参阅图1，栅极驱动电路102对应于显示区AA的外边缘。第一电源走线110设置在栅极驱动电路102的外侧。第二电源走线111设置在靠近连接焊盘109的一侧。复位信号走线113设置在栅极驱动电路102的内侧。阵列测试焊盘114设置在第二电源走线111远离连接焊盘109的一侧。扇形走线115设置在第二电源走线111和连接焊盘109之间，用于连接第二电源走线111和连接焊盘109。
在一些实施例中，衬底101包括依次层叠设置在的无机层1011、第一柔性衬底层、第一阻挡层1013和第二阻挡层1014。第一有源层1021设置在第二阻挡层1014上。连接焊盘109设置在无机层1011远离第一柔性衬底层1012的一面。
在一些实施例中，第一柔性衬底层1012的材料可以包括PI（聚酰亚胺）、PET（聚二甲酸乙二醇酯）、PEN（聚萘二甲酸乙二醇脂）、PC（聚碳酸酯）、PES（聚醚砜）、PAR（含有聚芳酯的芳族氟甲苯）或PCO（多环烯烃）中的至少一种。无机层1011、第一阻挡层1013和第二阻挡层1014由含硅的氮化物、含硅的氧化物或含硅的氮氧化物中的一种或两种及以上的堆栈结构组成。
在一些实施例中，像素驱动电路层20a包括像素驱动电路，像素驱动电路可以包括3T1C型像素驱动电路、4T2C型像素驱动电路、5T2C型像素驱动电路或6T1C型像素驱动电路。
请参考图5，图5为本申请实施例提供的像素驱动电路层的一种像素驱动电路的电路图。像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第一电容C1、第二电容C2、及有机发光二极管OLED。各个晶体管均为P型薄膜晶体管。第一晶体管T1为驱动薄膜晶体管，第一晶体管T1的栅极经由第一节点(A)电性连接于第一电容(C1)的一端，第一晶体管T1的源极接入第二电源走线111的正电压。第一晶体管T1的漏极电性连接于有机发光二极管OLED的阳极。第二晶体管T2的栅极接入该像素驱动电路所在行对应的第n条扫描信号SCAN(n)，第二晶体管T2的源极接入数据信号data，第二晶体管T2的漏极经由第二节点B电性连接于第一电容C1的另一端。第三晶体管T3的栅极接入该像素驱动电路所在行的下一行对应的第n+1条扫描信号SCAN(n+1)，第三晶体管T3的源极电性连接于第二节点B，漏极接入基准参考电压Vref。第四晶体管T4的栅极接入该像素驱动电路所在行对应的第n条扫描信号SCAN(n)，第四晶体管T4的源极电性连接于第一节点A，第四晶体管T4的漏极电性连接于有机发光二极管OLED的阳极。
第一电容C1的一端电性连接于第一节点A，另一端电性连接于第二节B。第二电容C2的一端电性连接于第一节点A，另一端电性连接于第二电源走线111。有机发光二极管OLED的阳极电性连接于第一晶体管T1的漏极和第四晶体管T4的漏极，阴极电性连接于第一电源走线110。
本发明提供的一种像素驱动电路采用4T2C结构，相比于现有的像素驱动电路，仅需要设置扫描信号来控制相应的薄膜晶体管，既起到了补偿作用，又减少了控制信号数量，且简化了电路结构，降低了成本。
相应的，本申请实施例还提供一种显示面板的制作方法，请参考图6。显示面板的制作方法包括以下步骤：
步骤B001，提供信号传输层，信号传输层位于显示面板的显示区。
其中，提供信号传输层的步骤包括提供一柔性衬底，然后在柔性衬底上设置连接焊盘109。
接下来，在柔性衬底1015上依次设置无机层1011、第一柔性衬底层1012。
随后，在第一柔性衬底层1012上设置栅极驱动电路102，以此形成信号传输层。
在一些实施例中，信号传输层还包括多条第一电源走线、多条第二电源走线、多条复位信号走线、阵列测试焊盘和多条扇形走线。
步骤B002，在信号传输层上设置显示功能层，显示功能层包括像素驱动电路层和发光功能层。像素驱动电路层设置在信号传输层上。发光功能层设置在像素驱动电路层远离信号传输层的一面。
步骤B003，利用激光剥离、机械剥离、溶解剥离等方法将柔性衬底1015剥离，以此裸露连接焊盘。
步骤B003，将驱动芯片绑定于连接焊盘上，以此完成显示面板的制作。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括显示区，所述显示面板包括：
    信号传输层，位于所述显示区，所述信号传输层包括栅极驱动电路；
    显示功能层，所述显示功能层包括像素驱动电路层和发光功能层，像素驱动电路层设置在所述信号传输层上方，所述发光功能层设置在所述像素驱动电路层远离所述信号传输层的一面。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括第一信号连接线，所述第一信号连接线位于所述显示区，所述第一信号连接线用于连接所述像素驱动电路层和所述信号传输层。
  3. 根据权利要求2所述的显示面板，其中，所述第一信号连接线包括连接的第一信号连接段、第二信号连接段和第三信号连接段；所述显示面板包括第一过孔、第二过孔和第三过孔，所述第一信号连接段设置在所述第一过孔内，所述第二信号连接段设置在所述第二过孔内，所述第三信号连接段设置在所述第三过孔内。
  4. 根据权利要求3所述的显示面板，其中，所述信号传输层还包括多条第一电源走线、多条第二电源走线、多条复位信号走线、阵列测试焊盘和多条扇形走线；其中
    所述第一信号连接段连接所述栅极驱动电路、所述第一电源走线、所述第二电源走线、所述复位信号走线、所述阵列测试焊盘或所述扇形走线，所述第三信号连接段连接所述像素驱动电路层。
  5. 根据权利要求3所述的显示面板，其中，所述显示面板还包括第二信号连接线，所述第二信号连接线位于所述显示区，所述第二信号连接线用于连接所述像素驱动电路层和所述信号传输层。
  6. 根据权利要求5所述的显示面板，其中，所述第二信号连接线包括连接的第四信号连接段、第五信号连接段和第六信号连接段；所述显示面板包括第四过孔、第五过孔和第六过孔，所述第四信号连接段设置在所述第四过孔内，所述第五信号连接段设置在所述第五过孔内，所述第六信号连接段设置在所述第六过孔内。
  7. 根据权利要求6所述的显示面板，其中，所述第四信号连接段连接所述栅极驱动电路、所述第一电源走线、所述第二电源走线、所述复位信号走线、所述阵列测试焊盘或所述扇形走线，所述第六信号连接段连接所述像素驱动电路层。
  8. 根据权利要求6所述的显示面板，其中，所述显示面板还包括第一连接端子和第二连接端子；所述栅极驱动电路包括第一薄膜晶体管，所述第一薄膜晶体管包括第一有源层、第一栅极、第二栅极、第一源极和第一漏极，所述信号传输层还包括：
    衬底，所述第一有源层设置在所述衬底上；
    第一栅极绝缘层，设置在所述衬底上，所述第一栅极设置在所述衬底上，且所述第一连接端子和所述第一栅极同层且同材料；
    第二栅极绝缘层，设置在所述第一栅极绝缘层上，所述第二栅极绝缘层覆盖所述第一栅极和所述第一连接端子，所述第二栅极和所述第二连接端子设置在所述第二栅极绝缘层上，所述第二栅极和所述第二连接端子同层且同材料；
    第一层间绝缘层，设置在所述第二栅极绝缘层上，且所述第一层间绝缘层覆盖所述第二栅极和所述第二连接端子，所述第一过孔贯穿所述第一层间绝缘层和所述第二栅极绝缘层，所述第一信号连接段通过所述第一过孔与所述第一连接端子连接，所述第四过孔贯穿所述第一层间绝缘层，所述第四信号连接段通过所述第四过孔与所述第二连接端子连接，所述第一源极和所述第一漏极分别通过第一接触孔和第二接触孔和所述第一有源层连接；
    第二层间绝缘层，设置在所述第一层间绝缘层上，所述第二过孔贯穿所述第二层间绝缘层，所述第二信号连接段通过所述第二过孔和第一信号连接段连接，所述第五过孔贯穿所述第二层间绝缘层，所述第五信号连接段通过所述第五过孔和所述第四信号连接段连接。
  9. 根据权利要求8所述的显示面板，其中，所述显示面板还包括第三连接端子和第四连接端子；所述像素驱动电路层包括：
    基底层，设置在所述第二层间绝缘层上；
    第二有源层，设置在所述基底层上；
    绝缘层，设置在所述第二有源层远离所述基底层的一面，所述第六过孔贯穿所述绝缘层和基底层，所述第六信号连接段通过所述第六过孔和所述第五信号连接段连接；
    第三栅极，设置在所述绝缘层远离所述第二有源层的一面，所述第三连接端子和所述第六信号连接段连接且与所述第三栅极同层且同材料；
    层间介质层，设置在所述第三栅极远离所述绝缘层的一面，所述第三过孔贯穿所述层间介质层、所述绝缘层和所述基底层，所述第三信号连接段通过所述第三过孔和所述第二信号连接段连接；
    第二源极和第二漏极，所述第二源极和所述第二漏极设置在所述层间介质层上，并分别通过第三接触孔和第四接触孔和所述第二有源层连接，所述第四连接端子和所述第二源极同层且材料，所述第四连接端子和所述第三信号连接段连接；
    平坦化层，所述平坦化层设置在所述层间介质层上。
  10. 根据权利要求9所述的显示面板，其中，所述信号传输层还包括遮光层，所述遮光层设置在所述第二层间绝缘层上，所述遮光层通过过孔与所述第一漏极连接，且所述遮光层于所述衬底上的正投影覆盖所述第二有源层于所述衬底上的正投影。
  11. 根据权利要求8所述的显示面板，其中，所述显示面板还包括第七过孔，所述第七过孔贯穿所述信号传输层的部分绝缘层；所述信号传输层还包括连接走线和连接焊盘，所述连接焊盘设置在所述衬底远离所述第一层间绝缘层的一面，所述连接走线设置在所述第七过孔内，所述连接走线的一端连接所述连接焊盘，所述连接走线的另一端连接所述像素驱动电路层。
  12. 根据权利要求11所述的显示面板，其中，所述显示面板还包括驱动芯片，所述驱动芯片设置在所述连接焊盘远离所述衬底的一面。
  13. 根据权利要求1所述的显示面板，其中，所述像素驱动电路层包括像素驱动电路，所述像素驱动电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一电容、第二电容及有机发光二极管；其中，所述第一晶体管为驱动薄膜晶体管。
  14. 一种显示面板，其中，所述显示面板包括显示区，所述显示面板包括：
    信号传输层，位于所述显示区，所述信号传输层包括栅极驱动电路；
    显示功能层，所述显示功能层包括像素驱动电路层和发光功能层，像素驱动电路层设置在所述信号传输层上方，所述发光功能层设置在所述像素驱动电路层远离所述信号传输层的一面；
    驱动芯片，所述驱动芯片位于所述信号传输层远离所述显示功能层的一侧。
  15. 根据权利要求14所述的显示面板，其中，所述显示面板还包括第一信号连接线，所述第一信号连接线位于所述显示区，所述第一信号连接线用于连接所述像素驱动电路层和所述信号传输层。
  16. 根据权利要求15所述的显示面板，其中，所述第一信号连接线包括连接的第一信号连接段、第二信号连接段和第三信号连接段；所述显示面板包括第一过孔、第二过孔和第三过孔，所述第一信号连接段设置在所述第一过孔内，所述第二信号连接段设置在所述第二过孔内，所述第三信号连接段设置在所述第三过孔内。
  17. 根据权利要求16所述的显示面板，其中，所述信号传输层还包括多条第一电源走线、多条第二电源走线、多条复位信号走线、阵列测试焊盘和多条扇形走线；其中
    所述第一信号连接段连接所述栅极驱动电路、所述第一电源走线、所述第二电源走线、所述复位信号走线、所述阵列测试焊盘或所述扇形走线，所述第三信号连接段连接所述像素驱动电路层。
  18. 根据权利要求16所述的显示面板，其中，所述显示面板还包括第二信号连接线，所述第二信号连接线位于所述显示区，所述第二信号连接线用于连接所述像素驱动电路层和所述信号传输层。
  19. 根据权利要求18所述的显示面板，其中，所述第二信号连接线包括连接的第四信号连接段、第五信号连接段和第六信号连接段；所述显示面板包括第四过孔、第五过孔和第六过孔，所述第四信号连接段设置在所述第四过孔内，所述第五信号连接段设置在所述第五过孔内，所述第六信号连接段设置在所述第六过孔内。
  20. 根据权利要求19所述的显示面板，其中，所述第四信号连接段连接所述栅极驱动电路、所述第一电源走线、所述第二电源走线、所述复位信号走线、所述阵列测试焊盘或所述扇形走线，所述第六信号连接段连接所述像素驱动电路层。
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