WO2024001105A1 - 一种通信检测方法、装置、设备、***以及存储介质 - Google Patents

一种通信检测方法、装置、设备、***以及存储介质 Download PDF

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Publication number
WO2024001105A1
WO2024001105A1 PCT/CN2022/141390 CN2022141390W WO2024001105A1 WO 2024001105 A1 WO2024001105 A1 WO 2024001105A1 CN 2022141390 W CN2022141390 W CN 2022141390W WO 2024001105 A1 WO2024001105 A1 WO 2024001105A1
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WIPO (PCT)
Prior art keywords
pin
electronic device
communication
data frame
signal level
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PCT/CN2022/141390
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English (en)
French (fr)
Inventor
郭红光
张晨松
林尚波
田晨
张加亮
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Oppo广东移动通信有限公司
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Publication of WO2024001105A1 publication Critical patent/WO2024001105A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H02J7/00034—Charger exchanging data with an electronic device, i.e. telephone, whose internal battery is under charge
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/0031—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using battery or load disconnect circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0047—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with monitoring or indicating devices or circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/46—Monitoring; Testing

Definitions

  • the present application relates to the field of charging technology, and in particular to a communication detection method, device, equipment, system and storage medium.
  • the communication connection between the electronic device and the adapter can be realized through a communication cable (also called a “charging cable” or “data cable”), and the adapter can be used to charge the electronic device.
  • a communication cable also called a “charging cable” or “data cable”
  • the adapter can be used to charge the electronic device.
  • communication timeout or current intermittent methods to detect whether charging is abnormal.
  • this method takes a long time to detect and the response speed is relatively slow, making it easy to Raise security issues.
  • embodiments of the present application provide a communication detection method, which is applied to a first electronic device.
  • the first electronic device establishes a connection with a second electronic device through a communication cable.
  • the first electronic device is used to provide the second electronic device with
  • the first electronic device at least includes a first pin and a second pin, and a first resistor is connected in series between the second pin and ground; the method includes:
  • the first electronic device stops the charging path with the second electronic device.
  • the signal level of the identification bit of the first data frame is used to indicate data frame communication. abnormal.
  • embodiments of the present application provide a communication detection method, which is applied to a second electronic device.
  • the second electronic device establishes a connection with the first electronic device through a communication cable.
  • the first electronic device is used to provide the second electronic device with a communication detection method.
  • the second electronic device at least includes a first pin and a second pin, and a first resistor is connected in series between the second pin and ground; the method includes:
  • the second electronic device stops the charging path with the first electronic device.
  • the signal level of the identification bit of the first data frame is used to indicate data frame communication. abnormal.
  • embodiments of the present application provide a communication detection device applied to a first electronic device.
  • the first electronic device at least includes a first pin and a second pin, and the second pin is connected in series with ground.
  • the communication detection device includes a communication unit, a detection unit and a control unit; wherein,
  • a communication unit configured to perform transceiver communication with the second electronic device through the first pin and the second pin;
  • the detection unit is configured to detect the signal level at the second pin during the process of sending and receiving communication; and when detecting that the signal level at the second pin changes from high level to low level, trigger the second pin.
  • the foot starts to receive the first data frame;
  • the control unit is configured to stop the charging path between the first electronic device and the second electronic device when the signal level of the identification bit of the first data frame is low level, and the signal level of the identification bit of the first data frame is used to indicate Data frame communication exception.
  • embodiments of the present application provide a communication detection device applied to a second electronic device.
  • the second electronic device at least includes a first pin and a second pin, and the second pin is connected in series with ground.
  • a first resistor the communication detection device includes a communication unit, a detection unit and a control unit; wherein,
  • a communication unit configured to perform transceiver communication with the first electronic device through the first pin and the second pin;
  • the detection unit is configured to detect the signal level at the second pin during the process of sending and receiving communication; and when detecting that the signal level at the second pin changes from high level to low level, trigger the second pin.
  • the foot starts to receive the first data frame;
  • the control unit is configured to stop the charging path between the second electronic device and the first electronic device when the signal level of the identification bit of the first data frame is low level, and the signal level of the identification bit of the first data frame is used to indicate Data frame communication exception.
  • inventions of the present application provide an electronic device.
  • the electronic device includes a communication interface, a memory, and a processor.
  • the communication interface at least includes a first pin and a second pin, and the second pin is connected to ground.
  • the first resistor is connected in series between them; among them,
  • Communication interface used to receive and send information with other external network elements
  • Memory for storing computer programs capable of running on the processor
  • a processor configured to execute the method described in the first aspect or the method described in the second aspect when running a computer program.
  • a charging system which includes:
  • the first electronic device includes at least a first pin and a second pin, and a first resistor is connected in series between the second pin of the first electronic device and ground;
  • the second electronic device includes at least a first pin and a second pin, and a second resistor is connected in series between the second pin of the second electronic device and ground;
  • the first electronic device establishes a connection with the second electronic device through a communication cable for charging the second electronic device.
  • embodiments of the present application provide a computer-readable storage medium that stores a computer program.
  • the computer program is executed by at least one processor, the method described in the first aspect is implemented. Or the method described in the second aspect.
  • Figure 1 is a schematic structural diagram of a charging system
  • Figure 2 is a schematic diagram of the communication structure between a smartphone and an adapter
  • Figure 3 is a schematic diagram of the signal waveform for communication between a smartphone and an adapter
  • Figure 4 is a schematic flow chart of a communication detection method provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a UART data frame provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of an application scenario of a communication detection method provided by an embodiment of the present application.
  • Figure 7 is a schematic flow chart of another communication detection method provided by an embodiment of the present application.
  • Figure 8 is a schematic diagram of an application scenario of another communication detection method provided by an embodiment of the present application.
  • Figure 9 is a schematic diagram of an application scenario of yet another communication detection method provided by an embodiment of the present application.
  • FIG. 10A is a schematic structural diagram of another UART data frame provided by an embodiment of the present application.
  • FIG. 10B is a schematic structural diagram of another UART data frame provided by an embodiment of the present application.
  • Figure 11 is a schematic structural diagram of a communication detection device provided by an embodiment of the present application.
  • Figure 12 is a schematic diagram of a specific hardware structure of an electronic device provided by an embodiment of the present application.
  • embodiments of the present application provide a communication detection method, which is applied to a first electronic device.
  • the first electronic device establishes a connection with a second electronic device through a communication cable.
  • the first electronic device is used for
  • the second electronic device is charged, the first electronic device at least includes a first pin and a second pin, and a first resistor is connected in series between the second pin and ground; the method includes:
  • the first electronic device stops the charging path with the second electronic device. Used to indicate data frame communication exceptions.
  • the first data frame includes at least one of the following: a start field, a data field, a parity field, a stop field, and an idle field; wherein the start field corresponds to a start bit, The data field corresponds to eight data bits, the parity field corresponds to one parity bit, the stop field corresponds to one stop bit, and the idle field corresponds to one idle bit.
  • the method further includes: if the signal levels of the consecutive preset bits received by the second pin are all low levels, determining the signal level of the identification bit of the first data frame. Level is low level.
  • the method further includes: if the signal level of the preset value bit received by the second pin is low level, determining the signal level of the identification bit of the first data frame. Level is low level.
  • the method further includes: when the signal level of the identification bit of the first data frame is low level, The second electronic device sends a first message, so that the second electronic device stops the charging path with the first electronic device according to the first message; wherein the first message is used to indicate that the first electronic device There is a reception abnormality on the second pin of an electronic device.
  • the communication cable at least includes a positive signal data line and a negative signal data line; wherein the first pin is a pin connected to the positive signal data line, and the second pin is Connect the negative signal data line to the pin.
  • embodiments of the present application provide a communication detection method, which is applied to a second electronic device.
  • the second electronic device establishes a connection with a first electronic device through a communication cable.
  • the first electronic device is used for
  • the second electronic device is charged, the second electronic device includes at least a first pin and a second pin, and a first resistor is connected in series between the second pin and ground; the method includes:
  • the second electronic device stops the charging path with the first electronic device. Used to indicate data frame communication exceptions.
  • the first data frame includes at least one of the following: a start field, a data field, a parity field, a stop field, and an idle field; wherein the start field corresponds to a start bit, The data field corresponds to eight data bits, the parity field corresponds to one parity bit, the stop field corresponds to one stop bit, and the idle field corresponds to one idle bit.
  • the method further includes: if the signal levels of the consecutive preset bits received by the second pin are all low levels, determining the signal level of the identification bit of the first data frame. Level is low level.
  • the method further includes: if the signal level of the preset value bit received by the second pin is low level, determining the signal level of the identification bit of the first data frame. Level is low level.
  • the method further includes: when the signal level of the identification bit of the first data frame is low level, The first electronic device sends a second message, so that the first electronic device stops the charging path with the second electronic device according to the second message; wherein the second message is used to indicate that the first electronic device The second pin of the second electronic device has a receiving abnormality.
  • the communication cable at least includes a positive signal data line and a negative signal data line; wherein the first pin is a pin connected to the negative signal data line, and the second pin is Connect the positive signal data line to the pin.
  • embodiments of the present application provide a communication detection device applied to a first electronic device.
  • the first electronic device at least includes a first pin and a second pin, and the second pin is connected to ground.
  • a first resistor is connected in series between them;
  • the communication detection device includes a communication unit, a detection unit and a control unit; wherein,
  • the communication unit is configured to perform transceiver communication with the second electronic device through the first pin and the second pin;
  • the detection unit is configured to detect the signal level at the second pin during the process of sending and receiving communication; and when detecting that the signal level at the second pin changes from high level to When the level is low, the second pin is triggered to start receiving the first data frame;
  • the control unit is configured to stop the charging path between the first electronic device and the second electronic device when the signal level of the identification bit of the first data frame is low, and the first data frame
  • the signal level of the flag bit is used to indicate data frame communication abnormality.
  • embodiments of the present application provide a communication detection device applied to a second electronic device.
  • the second electronic device at least includes a first pin and a second pin, and the second pin is connected to ground.
  • a first resistor is connected in series between them;
  • the communication detection device includes a communication unit, a detection unit and a control unit; wherein,
  • the communication unit is configured to perform transceiver communication with the first electronic device through the first pin and the second pin;
  • the detection unit is configured to detect the signal level at the second pin during the process of sending and receiving communication; and when detecting that the signal level at the second pin changes from high level to When the level is low, the second pin is triggered to start receiving the first data frame;
  • the control unit is configured to stop the charging path between the second electronic device and the first electronic device when the signal level of the identification bit of the first data frame is low, and the first data frame
  • the signal level of the flag bit is used to indicate data frame communication abnormality.
  • inventions of the present application provide an electronic device.
  • the electronic device includes a communication interface, a memory, and a processor.
  • the communication interface at least includes a first pin and a second pin, and the second pin
  • the first resistor is connected in series between the pin and the ground;
  • the communication interface is used to receive and send information with other external network elements
  • the memory is used to store computer programs capable of running on the processor
  • the processor is configured to execute the method described in the first aspect or the method described in the second aspect when running the computer program.
  • a charging system which includes:
  • a first electronic device the first electronic device includes at least a first pin and a second pin, and a first resistor is connected in series between the second pin of the first electronic device and ground;
  • a second electronic device the second electronic device includes at least a first pin and a second pin, and a second resistor is connected in series between the second pin of the second electronic device and ground;
  • the first electronic device establishes a connection with the second electronic device through a communication cable for charging the second electronic device.
  • the first electronic device is used to communicate with the second electronic device through the first pin and the second pin; during the process of sending and receiving communication, Detect the signal level at the second pin; when detecting that the signal level at the second pin changes from high level to low level, trigger the second pin to start receiving the first data frame ; And when the signal level of the identification bit of the first data frame is low level, the first electronic device stops the charging path with the second electronic device, and the signal of the identification bit of the first data frame The level is used to indicate data frame communication exceptions.
  • the first electronic device is further configured to send a first message to the second electronic device when the signal level of the identification bit of the first data frame is low level, so that the The second electronic device stops the charging path with the first electronic device according to the first message; wherein the first message is used to indicate that the second pin of the first electronic device has a reception abnormality.
  • the second electronic device is configured to perform transceiver communication with the first electronic device through the first pin and the second pin; during the process of transceiving communication, Detect the signal level at the second pin; when detecting that the signal level at the second pin changes from high level to low level, trigger the second pin to start receiving the first data frame ; And when the signal level of the identification bit of the first data frame is low level, the second electronic device stops the charging path with the first electronic device, and the signal of the identification bit of the first data frame The level is used to indicate data frame communication exceptions.
  • the second electronic device is further configured to send a second message to the first electronic device when the signal level of the identification bit of the first data frame is low level, so that the The first electronic device stops the charging path with the second electronic device according to the second message; wherein the second message is used to indicate that a second pin of the second electronic device has a reception abnormality.
  • embodiments of the present application provide a computer-readable storage medium that stores a computer program.
  • the computer program is executed by at least one processor, the method as described in the first aspect is implemented. , or the method described in the second aspect.
  • first ⁇ second ⁇ third involved in the embodiments of this application are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that “first ⁇ second ⁇ The third "specific order or sequence may be interchanged where permitted, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein.
  • USB Universal Serial Bus
  • QC Quick Charge
  • SCP Secure Copy Protocol
  • Super VOOC File Fast charging protocols
  • UFCS Universal Fast Charging Specification
  • UART Universal Asynchronous Receiver/Transmitter
  • UART is a universal serial data bus that can be used for asynchronous communication. As the name suggests, It refers to the transmission of data on a data line according to binary digits, from low to high bits; and the bus has two-way communication and can achieve full-duplex transmission and reception.
  • USB Universal Serial Bus
  • FIG. 1 shows a schematic structural diagram of a charging system provided by an embodiment of the present application.
  • the device 100 to be charged may be connected to the power supply device 200 via a USB cable 300 .
  • the device 100 to be charged may be an electronic device such as a smartphone or a tablet computer; the power supply device 200 may be any suitable type of charging device, such as a charger, an adapter, a mobile power supply, a rechargeable electronic device, etc.
  • the device 100 to be charged may include a first USB interface 101
  • the power supply device 200 may include a second USB interface 201 .
  • the first USB interface 101 in the device 100 to be charged can be physically connected to the second USB interface 201 in the power supply device 200 through a USB cable 300.
  • the power supply device 200 includes the second USB interface 201, in other embodiments, the USB cable can also be directly welded to the power supply device 200, thereby avoiding the need for a USB interface.
  • the power supply device 200 may convert the received alternating current signal into a direct current signal and feed the direct current signal to the device to be charged 100 .
  • the power supply device 200 may support a battery charger communication protocol, and the battery charger communication protocol may be used to negotiate voltage and/or current levels between the power supply device 200 and the device to be charged 100 .
  • the power supply device 200 when the power supply device 200 is connected and communicates with the device 100 to be charged through the USB cable 300, the power supply device 200 will charge the battery of the device 100 to be charged until the battery is fully charged.
  • the charging process of the battery from zero or low power to full power for example, can include: trickle charging (providing a small charging current to the battery at a low rate and in a constant manner), constant current charging (Fixed charging current) and constant voltage charging (Fixed charging voltage).
  • the constant current stage can include multiple stages, each stage using different currents for charging.
  • connection in the embodiment of the present application refers to the electrical connection between the two interfaces, and the corresponding pins of the two interfaces are connected one by one.
  • connection methods There are no restrictions on connection methods. For example, the connection may be insertion, docking, etc.
  • the device 100 to be charged in the embodiment of the present application can be applied to various terminal devices including batteries, including but not limited to smart phones, tablets, laptops, PDAs, and mobile Internet devices.
  • Device MID
  • wearable devices vehicle-mounted devices
  • virtual reality (VR) terminals virtual reality
  • AR augmented reality
  • self-driving self-driving
  • Wireless terminals in remote medical wireless terminals in smart grid, wireless terminals in transportation safety, wireless terminals in smart city, smart Wireless terminals in smart homes, etc.
  • the power supply device 200 in the embodiment of the present application may be a charger, an adapter, a rechargeable electronic device, a reverse charging device, etc., or even a terminal device including a battery.
  • the power supply device 200 can not only be used to charge the battery inside the electronic device, but can also use the battery as a power source to supply power to the outside, that is, reverse charging.
  • the so-called reverse charging means that an electronic device (such as a smartphone, tablet, etc.) can use the power stored in its own battery to charge another electronic device (such as another smartphone) through wired/wireless methods .
  • wired reverse charging you can connect the device that needs to be charged through a USB cable to achieve wired reverse charging.
  • Figure 2 shows a schematic structural diagram of the two parties communicating with UFCS.
  • the communication cable may include: power signal line (Vbus), ground signal line (Ground, GND), communication signal line (D+ and D-), etc.
  • Vbus can be used as the power supply port for both communicating parties
  • GND can be used as the grounding port for both communicating parties
  • D-(D Negative, DN) can be used as the transmitting port (TX) on the smartphone side
  • TX port on the adapter side receives port (RX); D+ (D Positive, DP) can be used as the receiving port (RX) on the smartphone side and the transmitting port (TX) on the adapter side.
  • Super VOOC belongs to private synchronous communication, specifically half-duplex communication. In this way, at a certain moment, both communicating parties can only send or receive data, but cannot send and receive data at the same time. During the communication process, if it is found that one of the parties fails to send or reply to the message on time, it means that there is a communication error, and the other party will cut off the fast charging channel.
  • label 1 represents the Vbus voltage signal in the communication cable
  • label 2 represents the D+ signal in the communication cable
  • label 3 represents the D- signal in the communication cable
  • label 4 represents the Ibus in the communication cable current signal.
  • the adapter sends a message to the smartphone through the D+ signal
  • the smartphone will reply to the adapter on time through the D- signal.
  • the D- signal does not reply on time
  • the Ibus current signal is disconnected at this time, and the Vbus signal will rise to the voltage value set by the adapter due to the loss of the voltage drop caused by the current on the communication cable.
  • a typical communication error is abnormal unplugging of the communication cable.
  • the charging process will only be stopped when an abnormality in the data frame is detected (that is, one of the parties does not send or reply to the message on time).
  • an abnormality in the data frame that is, one of the parties does not send or reply to the message on time.
  • the longest time in between is one communication cycle.
  • embodiments of the present application provide a communication detection method that can be applied to a first electronic device.
  • the first electronic device at least includes a first pin and a second pin, and the second pin is connected in series with ground. a first resistor; or, it can also be applied to a second electronic device.
  • the second electronic device at least includes a first pin and a second pin, and the first resistor is connected in series between the second pin and the ground.
  • the first electronic device establishes a connection with the second electronic device through a communication cable, and the first electronic device is used to charge the second electronic device; in this way, through the first pin and the second pin, it performs transceiver communication with the opposite end.
  • the first resistor since the first resistor is connected in series between the second pin and the ground, if the signal level of the identification bit of the first data frame is detected to be low level, which means that a communication abnormality occurs in the data frame, then the first resistor can be The electronic device stops the charging path with the second electronic device or the second electronic device stops the charging path with the first electronic device, thereby quickly detecting communication abnormalities; and compared with related technologies, the detection time can be greatly shortened, and The entire response time is controlled at the sub-millisecond level, thereby improving the safety of the charging process.
  • FIG. 4 shows a schematic flowchart of a communication detection method provided by an embodiment of the present application.
  • the method may include:
  • S401 Transmit and receive communication with the second electronic device through the first pin and the second pin.
  • this method can be applied to the first electronic device, and the first electronic device can establish a connection with the second electronic device through a communication cable.
  • the first electronic device serves as a power supply device and can be used to charge the second electronic device.
  • the first electronic device at least includes a first pin and a second pin, and a first resistor is connected in series between the second pin and the ground.
  • the communication cable at least includes a first data signal line and a second data signal line; wherein the first pin can be connected to the first data signal line, and the second pin Can be connected to the second data signal line.
  • the first data signal line may be a positive signal data line, and the second data signal line may be a negative signal data line; or, the first data signal line may be a negative signal data line, and the second data signal line may be a negative signal data line.
  • the positive signal data line can be represented by the D+ line
  • the negative signal data line can be represented by the D- line.
  • performing transceiver communication with the second electronic device through the first pin and the second pin may include:
  • the fourth message sent by the second electronic device is received through the second data signal line connected to the second pin.
  • both the third message and the fourth message may include at least one data frame.
  • the third message and the fourth message here may be used to set charging between the first electronic device and the second electronic device. For example, assuming that the first electronic device is a power supply device and the second electronic device is a device to be charged, then according to the third message and the fourth message, the first electronic device can provide appropriate charging power to the second electronic device so as to provide the second electronic device with appropriate charging power. Batteries in electronic devices are charged.
  • the first pin may be a transmit (TX) pin, used to send data; the second pin may be a receive (RX) pin, used to receive data.
  • TX transmit
  • RX receive
  • the method of the embodiment of the present application can be applied to the UFCS standard, and the UFCS standard is based on the UART communication structure on the physical layer. That is to say, the first electronic device and the second electronic device here can have full-duplex communication. Data can be sent and received through two signal lines, D+ and D-, so that both communicating parties can send and receive data at the same time.
  • the first data signal line may be a D+ line
  • the second data line may be a D- line
  • the first pin may be a pin connected to the positive signal data line
  • the second pin may be a pin connected to the positive signal data line.
  • the pin may be a pin connected to the negative signal data line.
  • the first pin is connected to the D+ line so that the first electronic device sends data on the D+ line
  • the second pin is connected to the D- line so that the first electronic device receives data on the D- line.
  • the second pin when no data frame is received, if the first electronic device is connected to the second electronic device normally through the communication cable, then due to the existence of the second electronic device, The second data signal line connected to the second pin can be pulled high, that is, the signal level at the second pin is high; but if a communication abnormality occurs, for example, the first electronic device communicates with the third electronic device through a communication cable. If the connection between the two electronic devices fails (the communication cable is disconnected from the first electronic device, or the communication cable is disconnected from the second electronic device), then since the second pin is grounded through the first resistor, it can be connected to the second pin.
  • the second data signal line connected to the second pin is pulled low, that is, the signal level at the second pin is low; thus, by detecting the signal level at the second pin, it can be determined whether a communication abnormality occurs in the data frame. , can shorten the detection time so that the first electronic device can respond quickly.
  • the signal level of the identification bit of the first data frame may be used to indicate a data frame communication abnormality.
  • the first data frame can be one byte.
  • the first data frame may include at least one of the following: a start field, a data field, a parity field, a stop field, and an idle field.
  • the start field corresponds to one start bit
  • the data field corresponds to eight data bits
  • the parity field corresponds to one parity bit
  • the stop field corresponds to one stop bit
  • the idle field corresponds to one idle bit.
  • the start bit is valid at low level
  • the stop bit and idle bit are both valid at high level. That is, if there is no communication abnormality, the signal level of the start bit is low level, the signal level of the stop bit is high level, and the signal level of the idle bit is also high level.
  • the data format of asynchronous communication usually consists of start bits, data bits, parity bits and stop bits.
  • the parity bit is not necessary. Therefore, for certain requirements, the data format of asynchronous communication can also be composed of start bits, data bits and stop bits.
  • the parity field corresponds to a parity bit, and the parity bit can be added or not added according to actual needs.
  • the idle field it can be regarded as a part of the first data frame or as a part outside the first data frame.
  • the idle field corresponds to an idle bit, which is from the end of the stop bit of one byte to the beginning of the start bit of the next byte, indicating that the communication line is in an idle state. Specifically, before the valid data bits are officially sent, a start bit will be sent first, then the valid data bits will be sent, and a stop bit will be sent at the end of the valid data bits.
  • the start bit to the stop bit can constitute a data frame.
  • the data frame can be an n-th byte data stream, which is a standard UART data frame.
  • the data frame may include 1 start bit, 8 data bits, 1 parity bit, 1 stop bit and 1 idle bit.
  • the start bit is valid at a low level, and the stop bit and idle bit are both valid at a high level.
  • high level can be represented by logic "1”
  • low level can be represented by logic "0”.
  • 8 data bits after the start bit, the data is received serially from the lowest bit (Least Significant Bit, LSB) to the highest bit (Most Significant Bit, MSB).
  • the signal level at the second pin is low level, it means that the start bit is recognized, and then the subsequent data starts to be received, which will be done one by one.
  • the serial data received can be stored in the storage device; if there is a parity bit, the parity bit needs to be checked to determine the correctness of the data.
  • the transmission unit when using UART for data transmission, is a data frame.
  • a complete data frame can also include a start bit added before the data, a parity bit and a stop bit added after the data.
  • the parity bit can be added or added as required. Without adding, the number of stop bits can also be configured, such as 1/1.5/2 bits, etc. Under normal circumstances, UART does not require parity bits.
  • the length of a UART frame is 10 bits.
  • the stop bit when the UART is in the idle state, it remains high; after sending a set of data, it will automatically return to the high level, which generates a 1-bit idle bit of logic "1".
  • the method may further include: if the signal level of the consecutive preset bits received by the second pin is low level, determining that the signal level of the identification bit of the first data frame is low level. flat.
  • the first electronic device stops the charging path with the second electronic device.
  • the preset number of digits can be specifically set according to the actual situation, such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, etc. This embodiment of the present application does not limit this in any way.
  • the method may further include: if the signal level of the preset value bit received by the second pin is low level, determining that the signal level of the identification bit of the first data frame is low level. flat.
  • the first electronic device stops the charging path with the second electronic device.
  • the preset values here can also be specifically set according to actual conditions, such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, etc. The embodiments of this application do not limit this in any way.
  • the first data frame does not include a parity bit
  • the signal level of the 10th bit received by the second pin is low, that is, the stop bit of the first data frame is low. level
  • the first electronic device will stop the charging path with the second electronic device.
  • the first electronic device is connected to the second electronic device through a communication cable. If the communication cable is disconnected from the first electronic device, or the communication cable is disconnected from the second electronic device, connection, then for the first electronic device, the signal level at the second pin will be pulled down to a low level by the first resistor, that is, a data frame communication abnormality occurs.
  • the method may also include: when receiving the stop bit of the first data frame, if it is detected that the signal level at the second pin is low level, determining that data occurs Frame communication abnormality.
  • the method may also include: if the signal level of the stop bit of the first data frame is low level, and it is continued to detect that the signal level at the second pin is low level, Then the data frame communication abnormality is identified as the communication cable pull-out abnormality to determine that the communication cable is disconnected from the first electronic device or the second electronic device.
  • the method may also include: when triggering the second pin to start receiving the first data frame, if it is detected that the signal level at the second pin continues If at least 10 bits are low level, the data frame communication abnormality is identified as a communication cable pull-out abnormality to determine that the communication cable is disconnected from the first electronic device or the second electronic device.
  • the second pin will always be at a low level.
  • the signal level at the second pin is detected to change from high to high. After the level changes to low level, if it is detected that the signal level at the second pin is pulled down by at least 10 bits, a frame error can be triggered at this time, so that the abnormal communication cable pullout can also be identified, that is, the communication cable
  • the communication cable is disconnected from the first electronic device, or the communication cable is disconnected from the second electronic device.
  • the charging path between the first electronic device and the second electronic device can also be suspended, and then the charging process can be restarted by reducing the charging power, reducing the current, etc., to further identify the data frame communication abnormality; or, If the triggered communication error is the data retransmission mechanism, the first data frame can also be resent. At this time, all detected signal levels are still low, and data frame communication abnormalities can also be identified, such as unplugging the communication cable. Exception occurred.
  • the method can also include:
  • a first message is sent to the second electronic device, so that the second electronic device stops the charging path with the first electronic device according to the first message; wherein, A message is used to indicate that the second pin of the first electronic device has a reception abnormality.
  • the first electronic device when the signal level of the identification bit of the first data frame is used to indicate an abnormal communication of the data frame, not only the first electronic device can actively stop the charging path with the second electronic device ; Even the first electronic device can send a first message to the second electronic device to notify the second electronic device that the second pin of the first electronic device has a receiving abnormality at this time, and then the second electronic device stops communicating with the first electronic device. Charging path for electronic equipment.
  • the UFCS standard proposes higher voltage and larger current, in order to avoid safety issues, after the communication cable is pulled out, it is hoped that the first electronic device can quickly learn this situation, and respond immediately at the protocol level to shut down the charging process.
  • a first resistor is added between the second pin of the first electronic device and the ground, so that the abnormality of pulling out the communication cable can be quickly identified; then, after the abnormality of pulling out the communication cable is identified, the first electronic device The device immediately stops outputting charging power to close the charging path between the first electronic device and the second electronic device.
  • the application scenario may include a first electronic device 601 , a second electronic device 602 and a communication cable 603 .
  • the first electronic device 601 may include a first pin TX, a second pin RX, a third pin GND and a fourth pin Vbus
  • the second electronic device 602 may include a fifth pin RX and a sixth pin.
  • the communication cable 603 may include a D+ line, a D- line, a Vbus line and a GND line.
  • a first resistor Rd- is connected between the second pin RX and the third pin GND in the first electronic device 601 .
  • the Vbus line is connected between the fourth pin Vbus in the first electronic device 601 and the eighth pin Vbus in the second electronic device 602
  • the GND line is connected between the third pin Vbus in the first electronic device 601. between the pin GND and the seventh pin GND in the second electronic device 602
  • the D+ line is connected between the first pin TX in the first electronic device 601 and the fifth pin RX in the second electronic device 602
  • the D-line is connected between the second pin RX in the first electronic device 601 and the sixth pin TX in the second electronic device 602 .
  • this technical solution only requires adding a pull-down resistor Rd- in the circuit of the first electronic device 601; thus, when the communication cable 603 is pulled out , the first electronic device 601 can quickly detect the corresponding abnormality, and respond immediately at the protocol level, turning off the charging output of the first electronic device 601 so that Vbus drops to zero.
  • the first electronic device can realize the rapid detection function of abnormal charging cable unplugging.
  • the embodiment of the present application provides a communication detection method, specifically a method for quickly detecting the unplugging of a UFCS communication cable.
  • the method is applied to a first electronic device.
  • the first electronic device establishes a connection with a second electronic device through a communication cable.
  • the first electronic device is used to charge the second electronic device.
  • the first electronic device at least includes a first pin and a third electronic device.
  • Two pins, and a first resistor is connected in series between the second pin and the ground; in this way, during the process of sending and receiving communication, the signal level at the second pin is detected; when the signal level at the second pin is detected When the level changes from high level to low level, the second pin is triggered to start receiving the first data frame; when the signal level of the identification bit of the first data frame is low level, the first electronic device stops communicating with the second electronic device In the charging path, the signal level of the identification bit of the first data frame is used to indicate data frame communication abnormality.
  • the first electronic device ie, the power supply device
  • the first resistor is connected in series between the second pin and the ground
  • the signal level at the second pin will continue to be at a low level, causing the signal level of the identification bit of the first data frame to be unable to detect a high level, thus enabling quick abnormality detection of communication cable unplugging;
  • it can shorten the detection time and control the entire response time to sub-millisecond level, which can also improve the safety of the charging process.
  • FIG. 7 shows a schematic flow chart of another communication detection method provided by an embodiment of the present application. As shown in Figure 7, the method may include:
  • S701 Perform transceiver communication with the first electronic device through the first pin and the second pin.
  • this method can be applied to a second electronic device, and the second electronic device can establish a connection with the first electronic device through a communication cable.
  • the second electronic device serves as the device to be charged, and the first electronic device can charge the second electronic device.
  • the second electronic device at least includes a first pin and a second pin, and a first resistor is connected in series between the second pin and the ground.
  • the communication cable at least includes a first data signal line and a second data signal line; wherein the first pin can be connected to the first data signal line, and the second pin Can be connected to the second data signal line.
  • the first data signal line may be a positive signal data line, and the second data signal line may be a negative signal data line; or, the first data signal line may be a negative signal data line, and the second data signal line may be a negative signal data line.
  • the positive signal data line can be represented by the D+ line
  • the negative signal data line can be represented by the D- line.
  • performing transceiver communication with the first electronic device through the first pin and the second pin may include:
  • the fourth message sent by the first electronic device is received through the second data signal line connected by the second pin.
  • the third message and the fourth message may be used to set charging between the first electronic device and the second electronic device.
  • the first electronic device is a power supply device and the second electronic device is a device to be charged
  • the first electronic device can provide appropriate charging power to the second electronic device so as to provide the second electronic device with appropriate charging power. Batteries in electronic devices are charged.
  • the first pin may be a transmitting (TX) pin, used for sending data; the second pin may be a receiving (RX) pin, used for receiving data.
  • TX transmitting
  • RX receiving
  • the method of the embodiment of the present application can be applied to the UFCS standard, and the UFCS standard is based on the UART communication structure on the physical layer. That is to say, the first electronic device and the second electronic device have full-duplex communication, and data are sent and received through the two signal lines D+ and D-, so that both communicating parties can send and receive data at the same time.
  • the first data signal line can be a D- line
  • the second data line can be a D+ line
  • the first pin can be a pin connected to the negative signal data line
  • the second pin can be It is the pin connecting the positive signal data line.
  • the first pin is connected to the D- line so that the second electronic device sends data on the D- line
  • the second pin is connected to the D+ line so that the second electronic device receives data on the D+ line.
  • S702 During the process of sending and receiving communication, detect the signal level at the second pin.
  • the second data signal line connected to the second pin can be pulled high, that is, the signal level at the second pin is high; but if the second electronic device fails to connect to the first electronic device through the communication cable , in other words, the communication cable is disconnected from the first electronic device, or the communication cable is disconnected from the second electronic device, then since the second pin is grounded through the first resistor, the third pin connected to the second pin can be The second data signal line is pulled low, that is, the signal level at the second pin is low; thus, by detecting the signal level at the second pin, it can also be determined whether a communication abnormality occurs in the data frame, which can shorten the detection time. time so that the second electronic device can respond quickly.
  • the signal level of the identification bit of the first data frame may be used to indicate a data frame communication abnormality.
  • the first data frame can be one byte.
  • the first data frame may include at least one of the following: a start field, a data field, a parity field, a stop field, and an idle field.
  • the start field corresponds to one start bit
  • the data field corresponds to eight data bits
  • the parity field corresponds to one parity bit
  • the stop field corresponds to one stop bit
  • the idle field corresponds to one idle bit.
  • the start bit is valid at low level
  • the stop bit and idle bit are both valid at high level. That is, if there is no communication abnormality, the signal level of the start bit is low level, the signal level of the stop bit is high level, and the signal level of the idle bit is also high level.
  • the data format of asynchronous communication usually consists of start bits, data bits, parity bits and stop bits.
  • the parity bit is not necessary. Therefore, for certain requirements, the data format of asynchronous communication can also be composed of start bits, data bits and stop bits.
  • the parity field corresponds to a parity bit, and the parity bit can be added or not added according to actual needs.
  • the idle field it can be regarded as a part of the first data frame or as a part outside the first data frame.
  • the idle field corresponds to an idle bit, which is from the end of the stop bit of one byte to the beginning of the start bit of the next byte, indicating that the communication line is in an idle state. Specifically, before the valid data bits are officially sent, a start bit will be sent first, then the valid data bits will be sent, and a stop bit will be sent at the end of the valid data bits.
  • the start bit to the stop bit can constitute a data frame.
  • the method may further include: if the signal level of the consecutive preset bits received by the second pin is low level, determining that the signal level of the identification bit of the first data frame is low level. flat.
  • the second electronic device stops the charging path with the first electronic device.
  • the preset number of digits can be specifically set according to the actual situation, such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, etc. This embodiment of the present application does not limit this in any way.
  • the method may further include: if the signal level of the preset value bit received by the second pin is low level, determining that the signal level of the identification bit of the first data frame is low level. flat.
  • the second electronic device stops the charging path with the first electronic device.
  • the preset values here can also be specifically set according to actual conditions, such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, etc. The embodiments of this application do not limit this in any way.
  • the second electronic device is connected to the first electronic device through a communication cable. If the communication cable is disconnected from the first electronic device, or the communication cable is disconnected from the second electronic device, connection, then for the second electronic device, the signal level at the second pin will be pulled down to a low level by the first resistor, that is, a data frame communication exception occurs.
  • the method may also include: when receiving the stop bit of the first data frame, if it is detected that the signal level at the second pin is low level, determining that data occurs Frame communication abnormality.
  • the method may also include: if the signal level of the stop bit of the first data frame is low level, and it is continued to detect that the signal level at the second pin is low level, Then the data frame communication abnormality is identified as the communication cable pull-out abnormality to determine that the communication cable is disconnected from the first electronic device or the second electronic device.
  • the method may also include: when triggering the second pin to start receiving the first data frame, if it is detected that the signal level at the second pin continues If at least 10 bits are low, the data frame communication abnormality is identified as a communication cable pull-out abnormality to determine that the communication cable is disconnected from the first electronic device or the second electronic device.
  • the second pin will always be at a low level.
  • the signal level at the second pin is detected to change from high to high. After the level changes to low level, if it is detected that the signal level at the second pin is pulled down by at least 10 bits, a frame error can be triggered at this time, so that the abnormal communication cable pullout can also be identified, that is, the communication cable
  • the communication cable is disconnected from the first electronic device, or the communication cable is disconnected from the second electronic device.
  • the method can also include:
  • a second message is sent to the first electronic device, so that the first electronic device stops the charging path with the second electronic device according to the second message; wherein, the first electronic device The second message is used to indicate that the second pin of the second electronic device has a reception abnormality.
  • the second electronic device when the signal level of the identification bit of the first data frame is used to indicate an abnormality in the communication of the data frame, not only the second electronic device can actively stop the charging path with the first electronic device ; Even the second electronic device can send a second message to the first electronic device to notify the first electronic device that the second pin of the second electronic device has a receiving abnormality at this time, and then the first electronic device stops communicating with the second electronic device. Charging path for electronic equipment.
  • a first pin can also be added between the second pin of the second electronic device and the ground. resistance, so that the abnormality of the communication cable being pulled out can be quickly identified; then, after identifying the abnormality of the communication cable being pulled out, the second electronic device immediately stops outputting the charging power to turn off the connection between the first electronic device and the second electronic device. charging path between.
  • FIG. 8 shows a schematic diagram of an application scenario of another communication detection method provided by an embodiment of the present application.
  • the application scenario may include a second electronic device 801 , a first electronic device 802 and a communication cable 803 .
  • the second electronic device 801 may include a first pin TX, a second pin RX, a third pin GND and a fourth pin Vbus
  • the first electronic device 802 may include a fifth pin RX and a sixth pin.
  • the communication cable 803 may include a D+ line, a D- line, a Vbus line and a GND line.
  • a first resistor Rd- is connected between the second pin RX and the third pin GND in the second electronic device 801 .
  • the Vbus line is connected between the fourth pin Vbus in the second electronic device 801 and the eighth pin Vbus in the first electronic device 802, and the GND line is connected between the third pin Vbus in the second electronic device 801. between the pin GND and the seventh pin GND in the first electronic device 802, and the D-line is connected between the first pin TX in the second electronic device 801 and the fifth pin RX in the first electronic device 802 , the D+ line is connected between the second pin RX in the second electronic device 801 and the sixth pin TX in the first electronic device 802 .
  • this technical solution can also only require adding a pull-down resistor Rd- in the circuit of the second electronic device 801; thus, in the communication cable 803
  • the second electronic device 801 can also quickly detect the corresponding abnormality and respond immediately at the protocol level, shutting off the charging path of the second electronic device 801 so that Vbus drops to zero.
  • the second electronic device can also realize the rapid detection function of abnormal charging cable unplugging.
  • the embodiment of the present application provides a communication detection method, specifically a method for quickly detecting the unplugging of a UFCS communication cable.
  • the method is applied to a second electronic device.
  • the second electronic device establishes a connection with the first electronic device through a communication cable.
  • the first electronic device is used to charge the second electronic device.
  • the second electronic device at least includes a first pin and a third electronic device.
  • Two pins, and a first resistor is connected in series between the second pin and the ground; in this way, during the process of sending and receiving communication, the signal level at the second pin is detected; when the signal level at the second pin is detected When the level changes from high level to low level, the second pin is triggered to start receiving the first data frame; when the signal level of the identification bit of the first data frame is low level, the second electronic device stops communicating with the first electronic device In the charging path, the signal level of the identification bit of the first data frame is used to indicate data frame communication abnormality.
  • the second electronic device such as the device to be charged
  • the first resistor is connected in series between the second pin and the ground
  • the signal level at the second pin will continue to be at a low level, causing the signal level of the identification bit of the first data frame to be unable to detect a high level, thus enabling rapid abnormality detection of communication cable unplugging.
  • it can shorten the detection time and control the entire response time to sub-millisecond level, which can also improve the safety of the charging process.
  • the first resistor Rd1 can be connected in series between the second pin RX on the side of the power supply device and ground, and between the second pin RX on the side of the device to be charged and ground. Connect the second resistor Rd2 in series.
  • embodiments of the present application provide a charging system, which may include:
  • the first electronic device includes at least a first pin and a second pin, and a first resistor is connected in series between the second pin of the first electronic device and ground;
  • the second electronic device includes at least a first pin and a second pin, and a second resistor is connected in series between the second pin of the second electronic device and ground;
  • the first electronic device establishes a connection with the second electronic device through a communication cable for charging the second electronic device.
  • the first electronic device is used to perform transceiver communication with the second electronic device through the first pin and the second pin; in the transceiver communication During the process, detect the signal level at the second pin; when detecting that the signal level at the second pin changes from high level to low level, trigger the second pin to start receiving the first data frame; and When the signal level of the identification bit of the first data frame is low level, the first electronic device stops the charging path with the second electronic device, and the signal level of the identification bit of the first data frame is used to indicate an abnormality in data frame communication.
  • the first electronic device is also configured to send the first message to the second electronic device when the signal level of the identification bit of the first data frame is low level, so that the second electronic device can respond according to the first The message stops the charging path with the first electronic device; wherein the first message is used to indicate that the second pin of the first electronic device has a reception abnormality.
  • the second electronic device is used to perform transceiver communication with the first electronic device through the first pin and the second pin; During the communication process, the signal level at the second pin is detected; when it is detected that the signal level at the second pin changes from high level to low level, the second pin is triggered to start receiving the first data frame; And when the signal level of the identification bit of the first data frame is low level, the second electronic device stops the charging path with the first electronic device, and the signal level of the identification bit of the first data frame is used to indicate abnormal communication of the data frame. .
  • the second electronic device is also configured to send a second message to the first electronic device when the signal level of the identification bit of the first data frame is low level, so that the first electronic device can respond according to the second The message stops the charging path with the second electronic device; wherein the second message is used to indicate that the second pin of the second electronic device has a reception abnormality.
  • FIG. 9 shows a schematic diagram of an application scenario of yet another communication detection method provided by an embodiment of the present application.
  • the application scenario may include a first electronic device (power supply device) 901 , a second electronic device (device to be charged) 902 and a communication cable 903 .
  • the power supply device 901 may include a first pin TX, a second pin RX, a third pin GND and a fourth pin Vbus
  • the device to be charged 902 may include a fifth pin RX, a sixth pin TX, a third pin With seven pins GND and an eighth pin Vbus
  • the communication cable 903 may include a D+ line, a D- line, a Vbus line and a GND line.
  • a first resistor Rd1 is connected between the second pin RX and the third pin GND in the power supply device 901
  • a second resistor Rd1 is connected between the fifth pin RX and the seventh pin GND in the device to be charged 902. Resistor Rd2.
  • the Vbus line is connected between the fourth pin Vbus in the power supply device 901 and the eighth pin Vbus in the device to be charged 902
  • the GND line is connected between the third pin GND in the power supply device 901 and the device to be charged.
  • the D+ line is connected between the first pin TX in the power supply device 901 and the fifth pin RX in the device to be charged 902
  • the D- line is connected between the power supply device 901 between the second pin RX in the device 902 and the sixth pin TX in the device 902 to be charged.
  • the embodiment of the present application only requires adding a pull-down resistor between the RX pin of the power supply device 901 and/or the device to be charged 902 and ground. In this way, when the communication cable is pulled out, the power supply device 901 and/or the device to be charged 902 can quickly detect the corresponding abnormality, and respond immediately at the protocol level to turn off the corresponding output power.
  • Figure 5 shows the data frame composition of a standard UART, including a 1-bit start bit, 8-bit data bits, 1-bit parity bit, 1-bit stop bit, and 1-bit idle bit.
  • the characteristic of the UART physical layer is that the stop bit and idle bit are both high level.
  • this technical solution can add a pull-down resistor Rd1 to the RX pin of the power supply equipment 901. In this way, after the communication cable is pulled out, a falling edge event will occur on the RX pin of the power supply equipment 901. Communication mechanism that triggers UART data frames.
  • the power supply device 901 can re-confirm the signal level at the RX pin. If it is found that the signal level at the RX pin is still low, then the abnormality of unplugging the communication cable can be identified. , triggering the application to immediately terminate the charging process.
  • the parity bit can be removed in the UFCS standard.
  • the UART data frame is shown in Figure 10A. If the RX pin (or D-line) of the power supply device 901 is continuously pulled low for 10 bits, it may also be recognized that the stop bit is low level. As shown in Figure 10B, the data bits at this time are all 0. , an error in the stop bit represents a UART communication error (abnormal state), which can trigger the frame error interrupt mechanism, thereby recognizing that the communication cable is pulled out abnormally, and the power supply device will immediately stop output power.
  • UART communication error abnormal state
  • the time from when the communication cable is pulled out to when the power supply device stops outputting power will be compressed to the time when the UART data frame receives one byte.
  • the baud rate is 115200bps
  • the above situation is not only applicable to the power supply device 901 (such as an adapter), but also applicable to the device to be charged 902 (such as a smart phone).
  • the technical solution of this application is not only applicable to the abnormal detection of charging unplugging on the adapter side in the UFCS standard, but is also applicable to the abnormal detection of charging unplugging on the smartphone side in the UFCS standard. It only requires the RX pin on the smartphone side. (or in other words, D+ line) can be achieved by connecting a pull-down resistor Rd2 in series with ground.
  • FIG. 11 shows a schematic structural diagram of a communication detection device provided by an embodiment of the present application.
  • the communication detection device 110 may include a communication unit 1101 , a detection unit 1102 and a control unit 1103 .
  • the communication detection device 110 is applied to a first electronic device, and the first electronic device establishes a connection with a second electronic device through a communication cable, and the first electronic device is used to charge the second electronic device,
  • the first electronic device may at least include a first pin and a second pin, and a first resistor is connected in series between the second pin and ground.
  • the communication unit 1101 is configured to perform transceiver communication with the second electronic device through the first pin and the second pin;
  • the detection unit 1102 is configured to detect the signal level at the second pin during the process of sending and receiving communication; and when detecting that the signal level at the second pin changes from high level to low level, trigger the second The pin starts receiving the first data frame;
  • the control unit 1103 is configured to stop the charging path between the first electronic device and the second electronic device when the signal level of the identification bit of the first data frame is low level, and the signal level of the identification bit of the first data frame is used for Indicates data frame communication exception.
  • the first data frame includes at least one of the following: a start field, a data field, a parity field, a stop field, and an idle field; wherein the start field corresponds to one start bit, and the data field corresponds to eight data bits, the parity field corresponds to one parity bit, the stop field corresponds to one stop bit, and the idle field corresponds to one idle bit.
  • the detection unit 1102 is also configured to determine that the signal level of the identification bit of the first data frame is low if the signal level of the consecutive preset bits received by the second pin is low. level.
  • the detection unit 1102 is further configured to determine that the signal level of the identification bit of the first data frame is low if the signal level of the preset value bit received by the second pin is low level. level.
  • control unit 1103 is further configured to send a signal to the second electronic device when the signal level of the identification bit of the first data frame is low level after triggering the second pin to start receiving the first data frame.
  • the first message is so that the second electronic device stops the charging path with the first electronic device according to the first message; wherein the first message is used to indicate that the second pin of the first electronic device has a reception abnormality.
  • the communication cable at least includes a positive signal data line and a negative signal data line; wherein the first pin is a pin connected to the positive signal data line, and the second pin is a pin connected to the negative signal data line.
  • the communication detection device 110 is applied to a second electronic device, and the second electronic device is connected to the first electronic device through a communication cable, and the first electronic device is used to charge the second electronic device.
  • the second electronic device may at least include a first pin and a second pin, and a first resistor is connected in series between the second pin and ground.
  • the communication unit 1101 is configured to perform transceiver communication with the first electronic device through the first pin and the second pin;
  • the detection unit 1102 is configured to detect the signal level at the second pin during the process of sending and receiving communication; and when detecting that the signal level at the second pin changes from high level to low level, trigger the second The pin starts receiving the first data frame;
  • the control unit 1103 is configured to stop the charging path between the second electronic device and the first electronic device when the signal level of the identification bit of the first data frame is low level, and the signal level of the identification bit of the first data frame is used to Indicates data frame communication exception.
  • the first data frame includes at least one of the following: a start field, a data field, a parity field, a stop field, and an idle field; wherein the start field corresponds to one start bit, and the data field corresponds to eight data bits, the parity field corresponds to one parity bit, the stop field corresponds to one stop bit, and the idle field corresponds to one idle bit.
  • the detection unit 1102 is also configured to determine that the signal level of the identification bit of the first data frame is low if the signal level of the consecutive preset bits received by the second pin is low. level.
  • the detection unit 1102 is further configured to determine that the signal level of the identification bit of the first data frame is low if the signal level of the preset value bit received by the second pin is low level. level.
  • control unit 1103 is further configured to send a signal to the first electronic device when the signal level of the identification bit of the first data frame is low level after triggering the second pin to start receiving the first data frame.
  • the second message is so that the first electronic device stops the charging path with the second electronic device according to the second message; wherein the second message is used to indicate that the second pin of the second electronic device has a reception abnormality.
  • the communication cable at least includes a positive signal data line and a negative signal data line; wherein the first pin is a pin connected to the negative signal data line, and the second pin is a pin connected to the positive signal data line.
  • the "unit" may be part of a circuit, part of a processor, part of a program or software, etc., and of course may also be a module, or may be non-modular.
  • each component in this embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.
  • the above integrated units can be implemented in the form of hardware or software function modules.
  • the integrated unit is implemented in the form of a software function module and is not sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of this embodiment is essentially either The part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product.
  • the computer software product is stored in a storage medium and includes a number of instructions to make a computer device (can It is a personal computer, server, or network device, etc.) or processor that executes all or part of the steps of the method described in this embodiment.
  • the aforementioned storage media include: U disk, mobile hard disk, Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk or optical disk and other media that can store program code.
  • this embodiment provides a computer-readable storage medium that stores a computer program that implements the method described in any one of the preceding embodiments when executed by at least one processor. step.
  • the electronic device 120 may include: a communication interface 1201, a memory 1202, and a processor 1203; the various components are coupled together through a bus system 1204. It can be understood that the bus system 1204 is used to implement connection communication between these components. In addition to the data bus, the bus system 1204 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, the various buses are labeled bus system 1204 in FIG. 12 .
  • the electronic device 120 may be a first electronic device.
  • the electronic device 120 is connected to a second electronic device through a communication cable for charging the second electronic device, and the communication interface 1201 is at least It may include a first pin TX and a second pin RX, and a first resistor Rd- is connected in series between the second pin RX and ground.
  • Communication interface 1201 used for receiving and sending signals during the process of sending and receiving information with other external network elements (for example, a second electronic device);
  • Memory 1202 for storing computer programs capable of running on the processor 1203;
  • Processor 1203 used to execute when running a computer program:
  • the first electronic device stops the charging path with the second electronic device.
  • the signal level of the identification bit of the first data frame is used to indicate data frame communication. abnormal.
  • the electronic device 120 may be a second electronic device.
  • the electronic device 120 is connected to the first electronic device through a communication cable.
  • the first electronic device is used to charge the electronic device, and
  • the communication interface 1201 may also include at least a first pin TX and a second pin RX, and a first resistor Rd- is connected in series between the second pin RX and ground.
  • Communication interface 1201 used for receiving and sending signals during the process of sending and receiving information with other external network elements (for example, the first electronic device);
  • Memory 1202 for storing computer programs capable of running on the processor 1203;
  • Processor 1203 used to execute when running a computer program:
  • the second electronic device stops the charging path with the first electronic device.
  • the signal level of the identification bit of the first data frame is used to indicate data frame communication. abnormal.
  • the memory 1202 in the embodiment of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories.
  • non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), electrically removable memory. Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory.
  • Volatile memory may be Random Access Memory (RAM), which is used as an external cache.
  • RAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • SDRAM double data rate synchronous dynamic random access memory
  • Double Data Rate SDRAM DDRSDRAM
  • ESDRAM enhanced synchronous dynamic random access memory
  • SLDRAM synchronous link dynamic random access memory
  • Direct Rambus RAM Direct Rambus RAM
  • the processor 1203 may be an integrated circuit chip with signal processing capabilities. During the implementation process, each step of the above method can be completed by instructions in the form of hardware integrated logic circuits or software in the processor 1203 .
  • the above-mentioned processor 1203 can be a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
  • DSP Digital Signal Processor
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • a general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.
  • the steps of the method disclosed in conjunction with the embodiments of the present application can be directly implemented by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other mature storage media in this field.
  • the storage medium is located in the memory 1202.
  • the processor 1203 reads the information in the memory 1202 and completes the steps of the above method in combination with its hardware.
  • the processing unit can be implemented in one or more Application Specific Integrated Circuits (ASIC), Digital Signal Processing (DSP), Digital Signal Processing Device (DSP Device, DSPD), programmable Logic device (Programmable Logic Device, PLD), Field-Programmable Gate Array (FPGA), general-purpose processor, controller, microcontroller, microprocessor, and other devices used to perform the functions described in this application electronic unit or combination thereof.
  • ASIC Application Specific Integrated Circuits
  • DSP Digital Signal Processing
  • DSP Device Digital Signal Processing Device
  • DSPD Digital Signal Processing Device
  • PLD programmable Logic Device
  • FPGA Field-Programmable Gate Array
  • the techniques described herein may be implemented through modules (eg, procedures, functions, etc.) that perform the functions described herein.
  • Software code may be stored in memory and executed by a processor.
  • the memory can be implemented in the processor or external to the processor.
  • the processor 1203 is further configured to perform the steps of the method described in any of the preceding embodiments when running the computer program.
  • processor when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory can be integrated in the processor. Additionally, memories described herein are intended to include, but are not limited to, these and any other suitable types of memories.
  • a first electronic device establishes a connection with a second electronic device through a communication cable, and the first electronic device is used to charge the second electronic device; wherein, the method can be applied to the first electronic device, and the first electronic device The device at least includes a first pin and a second pin, and a first resistor is connected in series between the second pin and the ground; alternatively, the method can also be applied to a second electronic device, and the second electronic device at least includes the first pin. pin and the second pin, and the first resistor is connected in series between the second pin and the ground.
  • the first pin and the second pin are used to perform transceiver communication with the opposite end; during the process of transceiver communication, the signal level at the second pin is detected; when the signal level at the second pin is detected When the high level changes to the low level, the second pin is triggered to start receiving the first data frame; when the signal level of the identification bit of the first data frame is the low level, the communication between the first electronic device and the second electronic device is stopped. In the charging path, the signal level of the identification bit of the first data frame is used to indicate a data frame communication abnormality.
  • the first resistor since the first resistor is connected in series between the second pin and the ground, if the signal level of the identification bit of the first data frame is detected to be low level, which means that a communication abnormality occurs in the data frame, then the first resistor can be The electronic device stops the charging path with the second electronic device or the second electronic device stops the charging path with the first electronic device, thereby quickly detecting communication abnormalities; and compared with related technologies, the detection time can be greatly shortened, and The entire response time is controlled at the sub-millisecond level, thereby improving the safety of the charging process.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
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  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

本申请实施例公开了一种通信检测方法、装置、设备、***以及存储介质，该方法应用于第一电子设备，第一电子设备用于为第二电子设备充电，第一电子设备至少包括第一引脚和第二引脚，且第二引脚与地之间串接第一电阻；该方法包括：通过第一引脚和第二引脚，与第二电子设备进行收发通信；在收发通信的过程中，检测第二引脚处的信号电平；在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数据帧；在第一数据帧的标识位的信号电平为低电平时，第一电子设备停止与第二电子设备的充电通路，第一数据帧的标识位的信号电平用于指示数据帧通信异常。这样，可以缩短检测时间，能够提升充电过程的安全性。

Description

一种通信检测方法、装置、设备、***以及存储介质
相关申请的交叉引用
本申请要求在2022年06月27日提交中国专利局、申请号为202210735632.7、申请名称为“一种通信检测方法、装置、设备、***以及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及充电技术领域，尤其涉及一种通信检测方法、装置、设备、***以及存储介质。
背景技术
随着通信技术的不断发展，诸如智能手机、平板电脑之类的电子设备所支持的功能越来越多，而越来越多的功能对电子设备的电池容量提出了更高的要求。尤其是在电子设备的大屏化趋势下，设备的耗电逐渐增大，电池容量也随之增大，电子设备对快速充电需求越来越强烈。
在电子设备与适配器的通信场景下，通过通信线缆(或称为“充电线”、“数据线”)可以实现电子设备与适配器的通信连接，利用适配器为电子设备充电。然而，在相关技术中，对于大功率、大电流等情况，大多数仍然采用通信超时或电流断续的方式来检测充电是否异常，但是这种方式的检测时间长，响应速度比较慢，从而容易引发安全性问题。
发明内容
本申请的技术方案是这样实现的：
第一方面，本申请实施例提供了一种通信检测方法，应用于第一电子设备，第一电子设备通过通信线缆与第二电子设备建立连接，第一电子设备用于为第二电子设备充电，第一电子设备至少包括第一引脚和第二引脚，且第二引脚与地之间串接第一电阻；该方法包括：
通过第一引脚和第二引脚，与第二电子设备进行收发通信；
在收发通信的过程中，检测第二引脚处的信号电平；
在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数据帧；
在第一数据帧的标识位的信号电平为低电平时，第一电子设备停止与第二电子设备的充电通路，所述第一数据帧的标识位的信号电平用于指示数据帧通信异常。
第二方面，本申请实施例提供了一种通信检测方法，应用于第二电子设备，第二电子设备通过通信线缆与第一电子设备建立连接，第一电子设备用于为第二电子设备充电，第二电子设备至少包括第一引脚和第二引脚，且第二引脚与地之间串接第一电阻；该方法包括：
通过第一引脚和第二引脚，与第一电子设备进行收发通信；
在收发通信的过程中，检测第二引脚处的信号电平；
在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数据帧；
在第一数据帧的标识位的信号电平为低电平时，第二电子设备停止与第一电子设备的充电通路，所述第一数据帧的标识位的信号电平用于指示数据帧通信异常。
第三方面，本申请实施例提供了一种通信检测装置，应用于第一电子设备，第一电子设备至少包括第一引脚和第二引脚，且第二引脚与地之间串接第一电阻；该通信检测装置包括通信单元、检测单元和控制单元；其中，
通信单元，配置为通过第一引脚和第二引脚，与第二电子设备进行收发通信；
检测单元，配置为在收发通信的过程中，检测第二引脚处的信号电平；以及在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数据帧；
控制单元，配置为在第一数据帧的标识位的信号电平为低电平时，第一电子设备停止与第二电子设备的充电通路，第一数据帧的标识位的信号电平用于指示数据帧通信异常。
第四方面，本申请实施例提供了一种通信检测装置，应用于第二电子设备，第二电子设备至少包括 第一引脚和第二引脚，且第二引脚与地之间串接第一电阻；该通信检测装置包括通信单元、检测单元和控制单元；其中，
通信单元，配置为通过第一引脚和第二引脚，与第一电子设备进行收发通信；
检测单元，配置为在收发通信的过程中，检测第二引脚处的信号电平；以及在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数据帧；
控制单元，配置为在第一数据帧的标识位的信号电平为低电平时，第二电子设备停止与第一电子设备的充电通路，第一数据帧的标识位的信号电平用于指示数据帧通信异常。
第五方面，本申请实施例提供了一种电子设备，该电子设备包括通信接口、存储器和处理器，通信接口至少包括第一引脚和第二引脚，且所述第二引脚与地之间串接第一电阻；其中，
通信接口，用于与其他外部网元之间进行信息的接收和发送；
存储器，用于存储能够在处理器上运行的计算机程序；
处理器，用于在运行计算机程序时，执行如第一方面所述的方法、或者第二方面所述的方法。
第六方面，本申请实施例提供了一种充电***，该充电***包括：
第一电子设备，第一电子设备至少包括第一引脚和第二引脚，且第一电子设备的第二引脚与地之间串接第一电阻；
第二电子设备，第二电子设备至少包括第一引脚和第二引脚，且第二电子设备的第二引脚与地之间串接第二电阻；
其中，第一电子设备通过通信线缆与第二电子设备建立连接，用于为第二电子设备充电。
第七方面，本申请实施例提供了一种计算机可读存储介质，该计算机可读存储介质存储有计算机程序，所述计算机程序被至少一个处理器执行时实现如第一方面所述的方法、或者第二方面所述的方法。
附图说明
图1为一种充电***的组成结构示意图；
图2为一种智能手机与适配器通信的组成结构示意图；
图3为一种智能手机与适配器通信的信号波形示意图；
图4为本申请实施例提供的一种通信检测方法的流程示意图；
图5为本申请实施例提供的一种UART数据帧的组成结构示意图；
图6为本申请实施例提供的一种通信检测方法的应用场景示意图；
图7为本申请实施例提供的另一种通信检测方法的流程示意图；
图8为本申请实施例提供的另一种通信检测方法的应用场景示意图；
图9为本申请实施例提供的又一种通信检测方法的应用场景示意图；
图10A为本申请实施例提供的另一种UART数据帧的组成结构示意图；
图10B为本申请实施例提供的又一种UART数据帧的组成结构示意图；
图11为本申请实施例提供的一种通信检测装置的组成结构示意图；
图12为本申请实施例提供的一种电子设备的具体硬件结构示意图。
具体实施方式
第一方面，本申请实施例提供了一种通信检测方法，应用于第一电子设备，所述第一电子设备通过通信线缆与第二电子设备建立连接，所述第一电子设备用于为所述第二电子设备充电，所述第一电子设备至少包括第一引脚和第二引脚，且所述第二引脚与地之间串接第一电阻；所述方法包括：
通过所述第一引脚和所述第二引脚，与所述第二电子设备进行收发通信；
在所述收发通信的过程中，检测所述第二引脚处的信号电平；
在检测到所述第二引脚处的信号电平由高电平变换为低电平时，触发所述第二引脚开始接收第一数据帧；
在所述第一数据帧的标识位的信号电平为低电平时，所述第一电子设备停止与所述第二电子设备的充电通路，所述第一数据帧的标识位的信号电平用于指示数据帧通信异常。
在一些实施例中，所述第一数据帧包括下述至少一项：起始字段、数据字段、奇偶校验字段、停止字段和空闲字段；其中，所述起始字段对应一个起始位，所述数据字段对应八个数据位，所述奇偶校验字段对应一个奇偶校验位，所述停止字段对应一个停止位，所述空闲字段对应一个空闲位。
在一些实施例中，所述方法还包括：若所述第二引脚接收到的连续预设位数的信号电平均为低电平， 则确定所述第一数据帧的标识位的信号电平为低电平。
在一些实施例中，所述方法还包括：若所述第二引脚接收到的第预设数值位的信号电平为低电平，则确定所述第一数据帧的标识位的信号电平为低电平。
在一些实施例中，在所述触发所述第二引脚开始接收第一数据帧之后，所述方法还包括：在所述第一数据帧的标识位的信号电平为低电平时，向所述第二电子设备发送第一消息，以使得所述第二电子设备根据所述第一消息停止与所述第一电子设备的充电通路；其中，所述第一消息用于指示所述第一电子设备的第二引脚存在接收异常。
在一些实施例中，所述通信线缆至少包括正信号数据线和负信号数据线；其中，所述第一引脚为连接所述正信号数据线的引脚，所述第二引脚为连接所述负信号数据线的引脚。
第二方面，本申请实施例提供了一种通信检测方法，应用于第二电子设备，所述第二电子设备通过通信线缆与第一电子设备建立连接，所述第一电子设备用于为所述第二电子设备充电，所述第二电子设备至少包括第一引脚和第二引脚，且所述第二引脚与地之间串接第一电阻；所述方法包括：
通过所述第一引脚和所述第二引脚，与所述第二电子设备进行收发通信；
在所述收发通信的过程中，检测所述第二引脚处的信号电平；
在检测到所述第二引脚处的信号电平由高电平变换为低电平时，触发所述第二引脚开始接收第一数据帧；
在所述第一数据帧的标识位的信号电平为低电平时，所述第二电子设备停止与所述第一电子设备的充电通路，所述第一数据帧的标识位的信号电平用于指示数据帧通信异常。
在一些实施例中，所述第一数据帧包括下述至少一项：起始字段、数据字段、奇偶校验字段、停止字段和空闲字段；其中，所述起始字段对应一个起始位，所述数据字段对应八个数据位，所述奇偶校验字段对应一个奇偶校验位，所述停止字段对应一个停止位，所述空闲字段对应一个空闲位。
在一些实施例中，所述方法还包括：若所述第二引脚接收到的连续预设位数的信号电平均为低电平，则确定所述第一数据帧的标识位的信号电平为低电平。
在一些实施例中，所述方法还包括：若所述第二引脚接收到的第预设数值位的信号电平为低电平，则确定所述第一数据帧的标识位的信号电平为低电平。
在一些实施例中，在所述触发所述第二引脚开始接收第一数据帧之后，所述方法还包括：在所述第一数据帧的标识位的信号电平为低电平时，向所述第一电子设备发送第二消息，以使得所述第一电子设备根据所述第二消息停止与所述第二电子设备的充电通路；其中，所述第二消息用于指示所述第二电子设备的第二引脚存在接收异常。
在一些实施例中，所述通信线缆至少包括正信号数据线和负信号数据线；其中，所述第一引脚为连接所述负信号数据线的引脚，所述第二引脚为连接所述正信号数据线的引脚。
第三方面，本申请实施例提供了一种通信检测装置，应用于第一电子设备，所述第一电子设备至少包括第一引脚和第二引脚，且所述第二引脚与地之间串接第一电阻；所述通信检测装置包括通信单元、检测单元和控制单元；其中，
所述通信单元，配置为通过所述第一引脚和所述第二引脚，与所述第二电子设备进行收发通信；
所述检测单元，配置为在所述收发通信的过程中，检测所述第二引脚处的信号电平；以及在检测到所述第二引脚处的信号电平由高电平变换为低电平时，触发所述第二引脚开始接收第一数据帧；
所述控制单元，配置为在所述第一数据帧的标识位的信号电平为低电平时，所述第一电子设备停止与所述第二电子设备的充电通路，所述第一数据帧的标识位的信号电平用于指示数据帧通信异常。
第四方面，本申请实施例提供了一种通信检测装置，应用于第二电子设备，所述第二电子设备至少包括第一引脚和第二引脚，且所述第二引脚与地之间串接第一电阻；所述通信检测装置包括通信单元、检测单元和控制单元；其中，
所述通信单元，配置为通过所述第一引脚和所述第二引脚，与所述第一电子设备进行收发通信；
所述检测单元，配置为在所述收发通信的过程中，检测所述第二引脚处的信号电平；以及在检测到所述第二引脚处的信号电平由高电平变换为低电平时，触发所述第二引脚开始接收第一数据帧；
所述控制单元，配置为在所述第一数据帧的标识位的信号电平为低电平时，所述第二电子设备停止与所述第一电子设备的充电通路，所述第一数据帧的标识位的信号电平用于指示数据帧通信异常。
第五方面，本申请实施例提供了一种电子设备，所述电子设备包括通信接口、存储器和处理器，所述通信接口至少包括第一引脚和第二引脚，且所述第二引脚与地之间串接第一电阻；其中，
所述通信接口，用于与其他外部网元之间进行信息的接收和发送；
所述存储器，用于存储能够在所述处理器上运行的计算机程序；
所述处理器，用于在运行所述计算机程序时，执行如第一方面所述的方法、或者第二方面所述的方 法。
第六方面，本申请实施例提供了一种充电***，所述充电***包括：
第一电子设备，所述第一电子设备至少包括第一引脚和第二引脚，且所述第一电子设备的第二引脚与地之间串接第一电阻；
第二电子设备，所述第二电子设备至少包括第一引脚和第二引脚，且所述第二电子设备的第二引脚与地之间串接第二电阻；
其中，所述第一电子设备通过通信线缆与所述第二电子设备建立连接，用于为所述第二电子设备充电。
在一些实施例中，所述第一电子设备，用于通过所述第一引脚和所述第二引脚，与所述第二电子设备进行收发通信；在所述收发通信的过程中，检测所述第二引脚处的信号电平；在检测到所述第二引脚处的信号电平由高电平变换为低电平时，触发所述第二引脚开始接收第一数据帧；以及在所述第一数据帧的标识位的信号电平为低电平时，所述第一电子设备停止与所述第二电子设备的充电通路，所述第一数据帧的标识位的信号电平用于指示数据帧通信异常。
在一些实施例中，所述第一电子设备，还用于在所述第一数据帧的标识位的信号电平为低电平时，向所述第二电子设备发送第一消息，以使得所述第二电子设备根据所述第一消息停止与所述第一电子设备的充电通路；其中，所述第一消息用于指示所述第一电子设备的第二引脚存在接收异常。
在一些实施例中，所述第二电子设备，用于通过所述第一引脚和所述第二引脚，与所述第一电子设备进行收发通信；在所述收发通信的过程中，检测所述第二引脚处的信号电平；在检测到所述第二引脚处的信号电平由高电平变换为低电平时，触发所述第二引脚开始接收第一数据帧；以及在所述第一数据帧的标识位的信号电平为低电平时，所述第二电子设备停止与所述第一电子设备的充电通路，所述第一数据帧的标识位的信号电平用于指示数据帧通信异常。
在一些实施例中，所述第二电子设备，还用于在所述第一数据帧的标识位的信号电平为低电平时，向所述第一电子设备发送第二消息，以使得所述第一电子设备根据所述第二消息停止与所述第二电子设备的充电通路；其中，所述第二消息用于指示所述第二电子设备的第二引脚存在接收异常。
第七方面，本申请实施例提供了一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，所述计算机程序被至少一个处理器执行时实现如第一方面所述的方法、或者第二方面所述的方法。
为了能够更加详尽地了解本申请实施例的特点与技术内容，下面结合附图对本申请实施例的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本申请实施例。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本申请实施例的目的，不是旨在限制本申请。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
还需要指出，本申请实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本申请实施例能够以除了在这里图示或描述的以外的顺序实施。
随着通信技术的不断发展，诸如智能手机、平板电脑之类的电子设备所支持的功能越来越多，而越来越多的功能对电子设备的电池容量提出了更高的要求。尤其是在电子设备的大屏化趋势下，设备的耗电逐渐增大，电池容量也随之增大，电子设备对快速充电需求越来越强烈。由此，基于通用串行总线(Universal Serial Bus，USB)通道，近些年来衍生了多种快速充电协议，如USB2.0/3.0、快充(Quick Charge，QC)2.0/3.0/4.0、文件传输协议(Secure Copy Protocol，SCP)、Super VOOC等快充协议，能够大大缩短电子设备的充电时间。
目前，业界提出了一种移动终端融合快速充电(Universal Fast Charging Specification，UFCS)标准，主要目的是解决各家厂商快充协议互不兼容的问题，得到了终端厂商、芯片企业和产业界伙伴的大力支持。
需要说明的是，UFCS标准在物理层上是基于通用异步收发器(Universal Asynchronous Receiver/Transmitter，UART)的通信结构，其中，UART是一种通用串行数据总线，可以用于异步通信，顾名思义，是指数据在一根数据线上按照二进制的数位，从低到高位一位一位的传输；而且该总线双向通信，可以实现全双工传输和接收。
尽管本申请实施例中提到了各类充电协议，以及业界快速充电标准和通信接口，但不应被理解为对本申请的限制，仅为了示例性地阐述发明实施例，基于通用串行总线(Universal Serial Bus，USB)通道架构，在电子设备与充电器的通信场连接并且利用充电器为电子设备充电的情形下，有效解决因充电过程中充电异常检测和响应速度比较慢所引发的安全性问题，才是本申请发明构思强调的重点。
下面介绍本申请适用的一种充电场景。图1示出了本申请实施例提供的一种充电***的组成结构示意图。如图1所示，待充电设备100可以经由USB线缆300连接到供电设备200。其中，待充电设备100可以是智能手机、平板电脑之类的电子设备；供电设备200可以是任何合适类型的充电装置，例如，充电器、适配器、移动电源、可充电的电子设备等。
在图1中，待充电设备100可以包括第一USB接口101，供电设备200可以包括第二USB接口201。待充电设备100中的第一USB接口101，可以通过USB线缆300物理连接到供电设备200中的第二USB接口201。虽然在该实施例中，供电设备200包括第二USB接口201，但是在其他实施例中，USB线缆也可以是直接焊接到供电设备200上，从而避免对USB接口的需求。
在一些实施例中，当接收到交流电信号(例如，220V或110V)时，供电设备200可以将接收到的交流电信号转换为直流信号，并将该直流信号馈送给待充电设备100。在一种实现方式中，供电设备200可以支持电池充电器通信协议，电池充电器通信协议可用于协商供电设备200和待充电设备100之间的电压和/或电流电平。
在具体的充电过程中，在供电设备200通过USB线缆300与待充电设备100连接并通信时，供电设备200会向待充电设备100的电池进行充电，直至电池电量充满。其中，根据电池的特性，对电池从零电量或低电量到电量充满的充电过程，例如，可以包括：涓流充电(以低速率且恒定方式对电池提供很小的充电电流)、恒流充电(充电电流固定)、恒压充电(充电电压固定)几个阶段，随着大电流充电技术的发展，恒流阶段可以包括多个阶段，每一阶段采用不同电流进行充电。
需要说明的是，本申请实施例描述的电路结构以及充电场景是为了更加清楚的说明本申请实施例的技术方案，并不构成对于本申请实施例提供的技术方案的限定。另外，本申请实施例中“连接”指的是两个接口之间实现了电气连接，且两个接口中互相对应的引脚一一连接，但本申请实施例对两个接口之间具体的连接方式并不多作限制。例如，该连接可以是***、对接等等。
还需要说明的是，本申请实施例中的待充电设备100可以是应用于各种包括电池的终端设备，包括但不限于智能手机、平板电脑、笔记本电脑、掌上电脑、移动互联网设备(Mobile Internet Device，MID)、可穿戴设备，车载设备、虚拟现实(Virtual Reality，VR)终端、增强现实(Augmented Reality，AR)终端、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程医疗(remote medical)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端等。本申请实施例中的供电设备200可以是诸如充电器、适配器、可充电的电子设备、反向充电设备等，甚至供电设备200也可以是包括电池的终端设备。此时供电设备200不仅可以用于对电子设备内部的电池进行充电，还可以将电池作为电源向外部供电，即反向充电。这里所谓的反向充电，指的是电子设备(例如智能手机、平板电脑等)可以通过有线/无线方式，利用自身电池中存储的电能，为另一个电子设备(例如另一台智能手机)充电。当采用有线方式进行反向充电时，可以通过USB线缆连接需要充电的设备，以实现有线反向充电。
下面如图2所示，以待充电设备为智能手机、供电设备为适配器为例，在智能手机与适配器的通信场景下，图2示出了一种UFCS通信双方的组成结构示意图。如图2所示，以USB线缆为例，该通信线缆可以包括：电源信号线(Vbus)、接地信号线(Ground，GND)、通信信号线(D+和D-)等。其中，在该通信线缆中，Vbus可以作为通信双方的供电端口，GND可以作为通信双方的接地端口；D-(D Negative，DN)可以作为智能手机侧的发射端口(TX)，适配器侧的接收端口(RX)；D+(D Positive，DP)可以作为智能手机侧的接收端口(RX)，适配器侧的发射端口(TX)。
进一步地，以Super VOOC快充协议为例，Super VOOC属于私有同步通信，具体是半双工通信。这样，在某一时刻，通信双方只能发送或接收数据，不能同时发送和接收数据。在通信的过程中，如果发现其中一方没有按时发送或回复消息，那么意味着通信发生错误，这时候另外一方会切断快充通路。如图3所示，标号1表示通信线缆中的Vbus电压信号，标号2表示通信线缆中的D+信号，标号3表示通信线缆中的D-信号，标号4表示通信线缆中的Ibus电流信号。在通信过程中，如果适配器通过D+信号向智能手机发送消息，那么智能手机在接收到消息之后，会通过D-信号向适配器按时回复消息。但是在D-信号没有按时回复时，这时候Ibus电流信号被断开，Vbus信号由于失去了通信线缆上电流带来的压降，将会抬升至适配器设定的电压值。在这里，典型的通信错误是通信线缆拔出异常。
对于上述的通信中断方式，只有在检测到数据帧发生异常(即发现其中一方没有按时发送或回复消息)时，才会停止充电过程。也就是说，从充电双方中一方出现充电异常，到充电停止，这中间最长的时间需要经过一个通信周期。
在UFCS标准中，目前对于通信线缆拔出的检测，大多数仍然采用通信超时或电流断续的方式实现，但是这种方式仍然存在通信线缆拔出后相当一段时间内充电双发无法获知的情况。另外，由于UFCS 标准提出了更高的电压、更大的电流，因此这种方式在安全性方面也较弱，容易引发安全性问题。并且UFCS标准对充电异常的处理还提出了更高的要求，因此在充电双方检测到充电异常时，还需要能够快速的通过通信来中断充电过程。
基于此，本申请实施例提供了一种通信检测方法，可以应用于第一电子设备，第一电子设备至少包括第一引脚和第二引脚，且第二引脚与地之间串接第一电阻；或者，也可以应用于第二电子设备，第二电子设备至少包括第一引脚和第二引脚，且第二引脚与地之间串接第一电阻。其中，第一电子设备通过通信线缆与第二电子设备建立连接，第一电子设备用于为第二电子设备充电；这样，通过第一引脚和第二引脚，与对端进行收发通信；在收发通信的过程中，检测第二引脚处的信号电平；在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数据帧；在第一数据帧的标识位的信号电平为低电平时，停止第一电子设备与第二电子设备的充电通路，第一数据帧的标识位的信号电平用于指示数据帧通信异常。如此，由于第二引脚与地之间串接有第一电阻，如果检测到第一数据帧的标识位的信号电平为低电平，意味着数据帧发生通信异常，那么可以由第一电子设备停止与第二电子设备的充电通路或者由第二电子设备停止与第一电子设备的充电通路，从而能够快速实现通信异常的检测；而且相比于相关技术，能够大大缩短检测时间，并且将整个响应时间控制在亚毫秒级，进而提升了充电过程的安全性。
下面将结合附图对本申请各实施例进行详细说明。
本申请的一实施例中，参见图4，其示出了本申请实施例提供的一种通信检测方法的流程示意图。如图4所示，该方法可以包括：
S401：通过第一引脚和第二引脚，与第二电子设备进行收发通信。
需要说明的是，在本申请实施例中，该方法可以应用于第一电子设备，第一电子设备可以通过通信线缆与第二电子设备建立连接。在这里，第一电子设备作为供电设备，可以用于为第二电子设备充电。另外，第一电子设备至少包括第一引脚和第二引脚，且第二引脚与地之间串接第一电阻。
还需要说明的是，在本申请实施例中，通信线缆至少包括有第一数据信号线和第二数据信号线；其中，第一引脚可以与第一数据信号线连接，第二引脚可以与第二数据信号线连接。
在一些实施例中，第一数据信号线可以为正信号数据线，第二数据信号线可以为负信号数据线；或者，第一数据信号线可以为负信号数据线，第二数据信号线可以为正信号数据线。其中，正信号数据线可以用D+线表示，负信号数据线可以用D-线表示。
在一些实施例中，对于S401来说，通过第一引脚和第二引脚，与第二电子设备进行收发通信，可以包括：
通过第一引脚连接的第一数据信号线，向第二电子设备发送第三消息；
通过第二引脚连接的第二数据信号线，接收第二电子设备发送的第四消息。
需要说明的是，无论是第三消息还是第四消息，均可以包括至少一个数据帧。另外，这里的第三消息和第四消息可以用于对第一电子设备与第二电子设备之间的充电进行设置。例如，假定第一电子设备为供电设备，第二电子设备为待充电设备，那么根据第三消息和第四消息可以实现第一电子设备向第二电子设备提供合适的充电功率，以便为第二电子设备中的电池进行充电。
还需要说明的是，第一引脚可以为发射(TX)引脚，用于发送数据；第二引脚可以为接收(RX)引脚，用于接收数据。另外，本申请实施例的方法可以应用于UFCS标准，而UFCS标准在物理层上基于UART通信结构。也就是说，这里的第一电子设备和第二电子设备之间可以为全双工通信，通过D+和D-两条信号线进行数据收发，能够实现通信双方同时发送和接收数据。
在一种具体的实施例中，第一数据信号线可以为D+线，第二数据线可以为D-线；此时，第一引脚可以为连接正信号数据线的引脚，第二引脚可以为连接负信号数据线的引脚。在这种情况下，第一引脚与D+线连接，使得第一电子设备在D+线上发送数据；第二引脚与D-线连接，使得第一电子设备在D-线上接收数据。
S402：在收发通信的过程中，检测第二引脚处的信号电平。
在本申请实施例中，对于第二引脚而言，在没有接收数据帧的情况下，如果第一电子设备通过通信线缆与第二电子设备连接正常，那么由于第二电子设备的存在，可以使得与第二引脚连接的第二数据信号线被拉高，即第二引脚处的信号电平为高电平；但是如果发生通信异常，例如第一电子设备通过通信线缆与第二电子设备连接故障(通信线缆与第一电子设备断开连接，或者通信线缆与第二电子设备断开连接)，那么由于第二引脚通过第一电阻接地，可以使得与第二引脚连接的第二数据信号线被拉低，即第二引脚处的信号电平为低电平；从而通过检测第二引脚处的信号电平，即可确定出数据帧是否发生通信异常，能够缩短检测时间，以便第一电子设备快速做出响应。
S403：在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数 据帧。
S404：在第一数据帧的标识位的信号电平为低电平时，第一电子设备停止与第二电子设备的充电通路。
需要说明的是，在本申请实施例中，第一数据帧的标识位的信号电平可以用于指示数据帧通信异常。在这里，第一数据帧可以为一个字节。第一数据帧可以包括下述至少一项：起始字段、数据字段、奇偶校验字段、停止字段和空闲字段。
在本申请实施例中，起始字段对应一个起始位，数据字段对应八个数据位，奇偶校验字段对应一个奇偶校验位，停止字段对应一个停止位，空闲字段对应一个空闲位。其中，在UART数据结构中，起始位是低电平有效，停止位和空闲位均是高电平有效。即若无通信异常，则起始位的信号电平为低电平，停止位的信号电平为高电平，空闲位的信号电平也为高电平。
还需要说明的是，在UART数据结构中，异步通信的数据格式通常是由起始位、数据位、奇偶校验位和停止位组成。其中，奇偶校验位不是必须具备的，因此，对于某些需求，异步通信的数据格式也可以是由起始位、数据位和停止位组成。也就是说，奇偶校验字段对应一个奇偶校验位，该奇偶校验位可以根据实际需求选择添加或不添加。另外，对于空闲字段而言，其可以看作第一数据帧的一部分，也可以看作第一数据帧之外的部分。空闲字段对应一个空闲位，该空闲位是指从一个字节的停止位结束到下一个字节的起始位开始，表示通信线路处于空闲状态。具体来讲，在有效数据位正式发送之前，首先会发送一个起始位，然后发送有效数据位，在有效数据位结束时再发送一个停止位，起始位至停止位可以构成一数据帧。另外，停止位至下一个起始位之间是不定长的空闲位，并且相关标准规定起始位为低电平(逻辑值为0)，停止位和空闲位都是高电平(逻辑值为1)，这样就能够保证起始位开始处一定会存在下降沿，由此就可以标志一个数据流传输的起始。
示例性地，参见图5，其示出了本申请实施例提供的一种UART数据帧的组成结构示意图。如图5所示，该数据帧可以为第n个字节的数据流，其是一种标准UART的数据帧组成。具体地，该数据帧可以包括1个起始位、8个数据位、1个奇偶校验位、1个停止位和1个空闲位。对于UART物理层来说，其特点是起始位为低电平有效，停止位、空闲位均为高电平有效。如图5所示，高电平可以用逻辑“1”表示，低电平可以用逻辑“0”表示。另外，对于8个数据位，在起始位之后，数据按照最低位(Least Significant Bit，LSB)向最高位(Most Significant Bit，MSB)串行接收。
也就是说，在通过第二引脚进行数据接收时，如果第二引脚处的信号电平为低电平，那么意味着识别到起始位，然后开始对后续的数据进行接收，将逐位接收到的串行数据可以存储到存储设备中；如果存在奇偶校验位，那么还需要对其奇偶校验位进行校验以判断数据的正确性。
在UFCS标准中，使用UART进行数据传输时，传输单位为数据帧。一个完整的数据帧除了包括需要传输的数据外，还可以包括添加在数据之前的起始位，添加在数据之后的奇偶校验位和停止位，其中，奇偶校验位可按需求选择添加或不添加，停止位的个数也可进行配置，例如1/1.5/2位(bit)等。一般情况下，UART不需要奇偶校验位，在发送8bit数据情况下，UART的一帧长度为10bit。另外，在停止位之后，当UART处于空闲状态时，一直保持高电平；在发送完一组数据后，会自动恢复为高电平，即产生1bit的逻辑“1”的空闲位。
这样，在检测到第二引脚处的信号电平由高电平变换为低电平，即状态由空闲(高电平)切换到起始位(低电平)时，表示准备开始发送UART数据，也就触发了第二引脚开始接收第一数据帧。对于第一数据帧来说，如果第一数据帧的标识位的信号电平为低电平，意味着发生数据帧通信异常，那么第一电子设备需要停止与第二电子设备的充电通路，避免在大功率、大电流等情况下引发安全性问题。
在一些实施例中，该方法还可以包括：若第二引脚接收到的连续预设位数的信号电平均为低电平，则确定第一数据帧的标识位的信号电平为低电平。
需要说明的是，在触发第二引脚开始接收第一数据帧之后，如果第二引脚接收到的连续预设位数(例如，连续五位、连续六位等)的信号电平均为低电平，那么可以确定第一数据帧的标识位的信号电平为低电平，这时候第一电子设备停止与第二电子设备的充电通路。其中，这里的预设位数可以根据实际情况进行具体设置，例如2、3、4、5、6、7、8、9、10、11等，本申请实施例对此不作任何限定。
在一些实施例中，该方法还可以包括：若第二引脚接收到的第预设数值位的信号电平为低电平，则确定第一数据帧的标识位的信号电平为低电平。
还需要说明的是，在触发第二引脚开始接收第一数据帧之后，如果第二引脚接收到的第预设数值位(例如，第10位、第11位等)的信号电平为低电平，那么可以确定第一数据帧的标识位的信号电平为低电平，这时候第一电子设备停止与第二电子设备的充电通路。其中，这里的预设数值也可以根据实际情况进行具体设置，例如2、3、4、5、6、7、8、9、10、11等，本申请实施例对此不作任何限定。
示例性地，在第一数据帧不包括奇偶校验位的情况下，如果第二引脚接收到的第10位的信号电平 为低电平，即第一数据帧的停止位为低电平，那么可以确定发生数据帧通信异常；或者，如果第二引脚接收到的连续第10位和第11位的信号电平均为低电平，即第一数据帧的停止位和空闲位均为低电平，那么也可以确定发生数据帧通信异常，这时候第一电子设备会停止与第二电子设备的充电通路。
可以理解地，在本申请实施例中，第一电子设备通过通信线缆与第二电子设备连接，如果通信线缆与第一电子设备断开连接，或者通信线缆与第二电子设备断开连接，那么对于第一电子设备而言，第二引脚处的信号电平会被第一电阻下拉至低电平，即发生数据帧通信异常。
在一种具体的实施例中，在UART数据结构中，如果没有发生数据帧通信异常，停止位对应的信号电平应该为高电平；那么在接收完8位数据位之后，如果此时检测到第二引脚处的信号电平为低电平，即第一数据帧的停止位的信号电平为低电平，那么可以确定发生数据帧通信异常。在一些实施例中，对于S404来说，该方法还可以包括：在接收到第一数据帧的停止位时，若检测到第二引脚处的信号电平为低电平，则确定发生数据帧通信异常。
进一步地，在一些实施例中，该方法还可以包括：若第一数据帧的停止位的信号电平为低电平，且继续检测到第二引脚处的信号电平为低电平，则将数据帧通信异常识别为通信线缆拔出异常，以确定通信线缆与第一电子设备或第二电子设备断开连接。
需要说明的是，在通信线缆拔出之后，对于第一电子设备来说，第二引脚处会出现下降沿事件，触发第一数据帧的通信机制。但是由于通信线缆拔出之后，第二引脚处会一直处于低电平，因此在停止字段处无法检测到高电平，也就触发了通信错误。由于考虑到该通信错误可能是干扰或者其他因素导致停止位处的数据错误，那么还需要在检测到该通信错误之后，继续确认第二引脚处的信号电平，如果发现第二引脚处的信号电平仍为低电平，那么可以识别出通信线缆拔出异常，即通信线缆与第一电子设备断开连接、或者通信线缆与第二电子设备断开连接，此时需立即停止第一电子设备与第二电子设备的充电通路。
在另一种具体的实施例中，对于S404来说，该方法还可以包括：在触发所述第二引脚开始接收第一数据帧时，若检测到第二引脚处的信号电平持续至少10位为低电平，则将数据帧通信异常识别为通信线缆拔出异常，以确定通信线缆与第一电子设备或第二电子设备断开连接。
还需要说明的是，在通信线缆拔出之后，对于第一电子设备来说，第二引脚处会出现下降沿事件，触发第一数据帧的通信机制。但是由于通信线缆拔出之后，第二引脚处会一直处于低电平，考虑到在UFCS标准中通常去掉了奇偶校验位，那么在检测到第二引脚处的信号电平由高电平变换为低电平之后，如果检测到第二引脚处的信号电平被拉低至少10位，这时候可以触发帧错误，从而也可以识别出通信线缆拔出异常，即通信线缆与第一电子设备断开连接、或者通信线缆与第二电子设备断开连接。
另外，还需要注意的是，在理想情况下，可以根据一个数据帧的长度来识别是否发生数据帧通信异常；但是实际应用中，通常也可以根据多于一个数据帧的长度来识别是否发生数据帧通信异常。在本申请实施例中，引发数据帧通信异常的方式有很多种可能性，例如帧错误、信号干扰、通信线缆拔出、或者通信线缆未拔出但是通信接口的阻抗异常、通信接口有异物甚至于短路等等。如此，在发生数据帧通信异常时，也可以中止第一电子设备与第二电子设备的充电通路，然后使用降低充电功率、降低电流等方式来重启充电流程，进一步识别数据帧通信异常；或者，如果触发的通信错误为数据重发机制，那么还可以将第一数据帧重新发送，这时候检测到的信号电平仍全部为低电平，也可以识别数据帧通信异常，如通信线缆拔出异常。
还可以理解地，在本申请实施例中，如果第一电子设备的接收异常，但第一电子设备的发送无异常；那么在一些实施例中，在触发第二引脚开始接收第一数据帧之后，该方法还可以包括：
在第一数据帧的标识位的信号电平为低电平时，向第二电子设备发送第一消息，以使得第二电子设备根据第一消息停止与第一电子设备的充电通路；其中，第一消息用于指示第一电子设备的第二引脚存在接收异常。
需要说明的是，在本申请实施例中，当第一数据帧的标识位的信号电平用于指示数据帧通信异常时，不仅可以由第一电子设备主动停止与第二电子设备的充电通路；甚至也可以由第一电子设备向第二电子设备发送第一消息，以通知第二电子设备此时第一电子设备的第二引脚存在接收异常，然后由第二电子设备停止与第一电子设备的充电通路。
综上可知，在本申请实施例中，由于UFCS标准提出了更高的电压、更大的电流，为了避免安全性问题，在通信线缆被拔出之后，希望第一电子设备能够快速获知这一情况，并且立即在协议层面响应，关断充电过程。具体地，第一电子设备的第二引脚与地之间添加了第一电阻，以便能够快速识别出通信线缆拔出异常；然后，在识别出通信线缆拔出异常之后，第一电子设备立即停止输出充电功率，以关断第一电子设备与第二电子设备之间的充电通路。
示例性地，参见图6，其示出了本申请实施例提供的一种通信检测方法的应用场景示意图。如图6 所示，该应用场景可以包括第一电子设备601、第二电子设备602和通信线缆603。其中，第一电子设备601可以包括第一引脚TX、第二引脚RX、第三引脚GND和第四引脚Vbus，第二电子设备602可以包括第五引脚RX、第六引脚TX、第七引脚GND和第八引脚Vbus，通信线缆603可以包括D+线、D-线、Vbus线和GND线。另外，第一电子设备601中的第二引脚RX与第三引脚GND之间连接有第一电阻Rd-。
在图6中，Vbus线连接在第一电子设备601中的第四引脚Vbus和第二电子设备602中的第八引脚Vbus之间，GND线连接在第一电子设备601中的第三引脚GND和第二电子设备602中的第七引脚GND之间，D+线连接在第一电子设备601中的第一引脚TX和第二电子设备602中的第五引脚RX之间，D-线连接在第一电子设备601中的第二引脚RX和第二电子设备602中的第六引脚TX之间。
这样，对于第一电子设备(例如供电设备)而言，该技术方案在硬件结构上可以只需要在第一电子设备601的电路中，增加一个下拉电阻Rd-；从而在通信线缆603拔出时，第一电子设备601能够快速检测到对应异常，并且立即在协议层面响应，关断第一电子设备601的充电输出，使得Vbus下降到零。也就是说，通过最小的硬件改动，与UART底层逻辑和软件进行配合，从而第一电子设备能够实现充电线缆拔出异常的快速检测功能。
本申请实施例提供了一种通信检测方法，具体是一种快速检测UFCS通信线缆拔出的方法。该方法应用于第一电子设备，第一电子设备通过通信线缆与第二电子设备建立连接，第一电子设备用于为第二电子设备充电，第一电子设备至少包括第一引脚和第二引脚，且第二引脚与地之间串接第一电阻；这样，在收发通信的过程中，检测第二引脚处的信号电平；在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数据帧；在第一数据帧的标识位的信号电平为低电平时，第一电子设备停止与第二电子设备的充电通路，第一数据帧的标识位的信号电平用于指示数据帧通信异常。如此，对于第一电子设备(即供电设备)而言，由于第二引脚与地之间串接有第一电阻，在通信线缆与第一电子设备或第二电子设备断开连接时，那么第二引脚处的信号电平将会持续处于低电平，导致第一数据帧的标识位的信号电平无法检测到高电平，从而能够快速实现通信线缆拔出的异常检测；而且相比于相关技术，能够缩短检测时间，而且还能够将整个响应时间控制在亚毫秒级，进而还能够提升充电过程的安全性。
本申请的另一实施例中，参见图7，其示出了本申请实施例提供的另一种通信检测方法的流程示意图。如图7所示，该方法可以包括：
S701：通过第一引脚和第二引脚，与第一电子设备进行收发通信。
需要说明的是，在本申请实施例中，该方法可以应用于第二电子设备，第二电子设备可以通过通信线缆与第一电子设备建立连接。在这里，第二电子设备作为待充电设备，可以由第一电子设备为第二电子设备充电。另外，第二电子设备至少包括第一引脚和第二引脚，且第二引脚与地之间串接第一电阻。
还需要说明的是，在本申请实施例中，通信线缆至少包括有第一数据信号线和第二数据信号线；其中，第一引脚可以与第一数据信号线连接，第二引脚可以与第二数据信号线连接。
在一些实施例中，第一数据信号线可以为正信号数据线，第二数据信号线可以为负信号数据线；或者，第一数据信号线可以为负信号数据线，第二数据信号线可以为正信号数据线。其中，正信号数据线可以用D+线表示，负信号数据线可以用D-线表示。
在一些实施例中，对于S701来说，通过第一引脚和第二引脚，与第一电子设备进行收发通信，可以包括：
通过第一引脚连接的第一数据信号线，向第一电子设备发送第三消息；
通过第二引脚连接的第二数据信号线，接收第一电子设备发送的第四消息。
其中，第三消息和所述第四消息可以用于对第一电子设备与第二电子设备之间的充电进行设置。例如，假定第一电子设备为供电设备，第二电子设备为待充电设备，那么根据第三消息和第四消息可以实现第一电子设备向第二电子设备提供合适的充电功率，以便为第二电子设备中的电池进行充电。
还需要说明的是，在第二电子设备中，第一引脚可以为发射(TX)引脚，用于发送数据；第二引脚可以为接收(RX)引脚，用于接收数据。另外，本申请实施例的方法可以应用于UFCS标准，而UFCS标准在物理层上基于UART通信结构。也就是说，第一电子设备和第二电子设备之间为全双工通信，通过D+和D-两条信号线进行数据收发，能够实现通信双方同时发送和接收数据。
在一种具体的实施例中，第一数据信号线可以为D-线，第二数据线可以为D+线，那么第一引脚可以为连接负信号数据线的引脚，第二引脚可以为连接正信号数据线的引脚。在这种情况下，第一引脚与D-线连接，使得第二电子设备在D-线上发送数据；第二引脚与D+线连接，使得第二电子设备在D+线上接收数据。
S702：在收发通信的过程中，检测第二引脚处的信号电平。
S703：在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数据帧。
S704：在第一数据帧的标识位的信号电平为低电平时，第二电子设备停止与第一电子设备的充电通路。
在本申请实施例中，对于第二引脚而言，在没有接收数据帧的情况下，如果第二电子设备通过通信线缆与第一电子设备连接正常，那么由于第一电子设备的存在，可以使得与第二引脚连接的第二数据信号线被拉高，即第二引脚处的信号电平为高电平；但是如果第二电子设备通过通信线缆与第一电子设备连接故障，换言之，通信线缆与第一电子设备断开连接，或者通信线缆与第二电子设备断开连接，那么由于第二引脚通过第一电阻接地，可以使得与第二引脚连接的第二数据信号线被拉低，即第二引脚处的信号电平为低电平；从而通过检测第二引脚处的信号电平，也可以确定出数据帧是否发生通信异常，能够缩短检测时间，以便第二电子设备快速做出响应。
在本申请实施例中，第一数据帧的标识位的信号电平可以用于指示数据帧通信异常。在这里，第一数据帧可以为一个字节。第一数据帧可以包括下述至少一项：起始字段、数据字段、奇偶校验字段、停止字段和空闲字段。
需要说明的是，起始字段对应一个起始位，数据字段对应八个数据位，奇偶校验字段对应一个奇偶校验位，停止字段对应一个停止位，空闲字段对应一个空闲位。其中，在UART数据结构中，起始位是低电平有效，停止位和空闲位均是高电平有效。即若无通信异常，则起始位的信号电平为低电平，停止位的信号电平为高电平，空闲位的信号电平也为高电平。
还需要说明的是，在UART数据结构中，异步通信的数据格式通常是由起始位、数据位、奇偶校验位和停止位组成。其中，奇偶校验位不是必须具备的，因此，对于某些需求，异步通信的数据格式也可以是由起始位、数据位和停止位组成。也就是说，奇偶校验字段对应一个奇偶校验位，该奇偶校验位可以根据实际需求选择添加或不添加。另外，对于空闲字段而言，其可以看作第一数据帧的一部分，也可以看作第一数据帧之外的部分。空闲字段对应一个空闲位，该空闲位是指从一个字节的停止位结束到下一个字节的起始位开始，表示通信线路处于空闲状态。具体来讲，在有效数据位正式发送之前，首先会发送一个起始位，然后发送有效数据位，在有效数据位结束时再发送一个停止位，起始位至停止位可以构成一数据帧。另外，停止位至下一个起始位之间是不定长的空闲位，并且相关标准规定起始位为低电平(逻辑值为0)，停止位和空闲位都是高电平(逻辑值为1)，这样就能够保证起始位开始处一定会存在下降沿，由此就可以标志一个数据流传输的起始。
这样，在检测到第二引脚处的信号电平由高电平变换为低电平，即状态由空闲(高电平)切换到起始位(低电平)时，表示准备开始发送UART数据，也就触发了第二引脚开始接收第一数据帧。对于第一数据帧来说，如果第一数据帧的标识位的信号电平为低电平，意味着发生数据帧通信异常，那么第二电子设备需要停止与第一电子设备的充电通路，避免在大功率、大电流等情况下引发安全性问题。
在一些实施例中，该方法还可以包括：若第二引脚接收到的连续预设位数的信号电平均为低电平，则确定第一数据帧的标识位的信号电平为低电平。
需要说明的是，在触发第二引脚开始接收第一数据帧之后，如果第二引脚接收到的连续预设位数(例如，连续五位、连续六位等)的信号电平均为低电平，那么可以确定第一数据帧的标识位的信号电平为低电平，这时候第二电子设备停止与第一电子设备的充电通路。其中，这里的预设位数可以根据实际情况进行具体设置，例如2、3、4、5、6、7、8、9、10、11等，本申请实施例对此不作任何限定。
在一些实施例中，该方法还可以包括：若第二引脚接收到的第预设数值位的信号电平为低电平，则确定第一数据帧的标识位的信号电平为低电平。
还需要说明的是，在触发第二引脚开始接收第一数据帧之后，如果第二引脚接收到的第预设数值位(例如，第10位、第11位等)的信号电平为低电平，那么可以确定第一数据帧的标识位的信号电平为低电平，这时候第二电子设备停止与第一电子设备的充电通路。其中，这里的预设数值也可以根据实际情况进行具体设置，例如2、3、4、5、6、7、8、9、10、11等，本申请实施例对此不作任何限定。
可以理解地，在本申请实施例中，第二电子设备通过通信线缆与第一电子设备连接，如果通信线缆与第一电子设备断开连接，或者通信线缆与第二电子设备断开连接，那么对于第二电子设备而言，第二引脚处的信号电平会被第一电阻下拉至低电平，即发生数据帧通信异常。
在一种具体的实施例中，在UART数据结构中，如果没有发生数据帧通信异常，停止位对应的信号电平应该为高电平；那么在接收完8位数据位之后，如果此时检测到第二引脚处的信号电平为低电平，即第一数据帧的停止位的信号电平为低电平，那么可以确定发生数据帧通信异常。在一些实施例中，对于S704来说，该方法还可以包括：在接收到第一数据帧的停止位时，若检测到第二引脚处的信号电平为低电平，则确定发生数据帧通信异常。
进一步地，在一些实施例中，该方法还可以包括：若第一数据帧的停止位的信号电平为低电平，且继续检测到第二引脚处的信号电平为低电平，则将数据帧通信异常识别为通信线缆拔出异常，以确定通信线缆与第一电子设备或第二电子设备断开连接。
需要说明的是，在通信线缆拔出之后，对于第二电子设备来说，第二引脚处会出现下降沿事件，触发第一数据帧的通信机制。但是由于通信线缆拔出之后，第二引脚处会一直处于低电平，因此在停止字段处无法检测到高电平，也就触发了通信错误。由于考虑到该通信错误可能是干扰或者其他因素导致停止位处的数据错误，那么还需要在检测到该通信错误之后，继续确认第二引脚处的信号电平，如果发现第二引脚处的信号电平仍为低电平，那么可以识别出通信线缆拔出异常，即通信线缆与第一电子设备断开连接、或者通信线缆与第二电子设备断开连接。
在另一种具体的实施例中，对于S704来说，该方法还可以包括：在触发第二引脚开始接收第一数据帧时，若检测到所述第二引脚处的信号电平持续至少10位为低电平，则将数据帧通信异常识别为通信线缆拔出异常，以确定通信线缆与第一电子设备或第二电子设备断开连接。
还需要说明的是，在通信线缆拔出之后，对于第二电子设备来说，第二引脚处会出现下降沿事件，触发第一数据帧的通信机制。但是由于通信线缆拔出之后，第二引脚处会一直处于低电平，考虑到在UFCS标准中通常去掉了奇偶校验位，那么在检测到第二引脚处的信号电平由高电平变换为低电平之后，如果检测到第二引脚处的信号电平被拉低至少10位，这时候可以触发帧错误，从而也可以识别出通信线缆拔出异常，即通信线缆与第一电子设备断开连接、或者通信线缆与第二电子设备断开连接。
还可以理解地，在本申请实施例中，如果第二电子设备的接收异常，但第二电子设备的发送无异常；那么在一些实施例中，在触发第二引脚开始接收第一数据帧之后，该方法还可以包括：
在第一数据帧的标识位的信号电平为低电平时，向第一电子设备发送第二消息，以使得第一电子设备根据第二消息停止与第二电子设备的充电通路；其中，第二消息用于指示第二电子设备的第二引脚存在接收异常。
需要说明的是，在本申请实施例中，当第一数据帧的标识位的信号电平用于指示数据帧通信异常时，不仅可以由第二电子设备主动停止与第一电子设备的充电通路；甚至也可以由第二电子设备向第一电子设备发送第二消息，以通知第一电子设备此时第二电子设备的第二引脚存在接收异常，然后由第一电子设备停止与第二电子设备的充电通路。
综上可知，在本申请实施例中，由于UFCS标准提出了更高的电压、更大的电流，为了避免安全性问题，第二电子设备的第二引脚与地之间也可以添加第一电阻，以便能够快速识别出通信线缆拔出异常；然后，在识别出通信线缆拔出异常之后，第二电子设备立即停止输出充电功率，以关断第一电子设备与第二电子设备之间的充电通路。
在一种具体的实施例中，参见图8，其示出了本申请实施例提供的另一种通信检测方法的应用场景示意图。如图8所示，该应用场景可以包括第二电子设备801、第一电子设备802和通信线缆803。其中，第二电子设备801可以包括第一引脚TX、第二引脚RX、第三引脚GND和第四引脚Vbus，第一电子设备802可以包括第五引脚RX、第六引脚TX、第七引脚GND和第八引脚Vbus，通信线缆803可以包括D+线、D-线、Vbus线和GND线。另外，第二电子设备801中的第二引脚RX与第三引脚GND之间连接有第一电阻Rd-。
在图8中，Vbus线连接在第二电子设备801中的第四引脚Vbus和第一电子设备802中的第八引脚Vbus之间，GND线连接在第二电子设备801中的第三引脚GND和第一电子设备802中的第七引脚GND之间，D-线连接在第二电子设备801中的第一引脚TX和第一电子设备802中的第五引脚RX之间，D+线连接在第二电子设备801中的第二引脚RX和第一电子设备802中的第六引脚TX之间。
这样，对于第二电子设备(例如待充电设备)而言，该技术方案在硬件结构上也可以只需要在第二电子设备801的电路中，增加一个下拉电阻Rd-；从而在通信线缆803拔出时，第二电子设备801也能够快速检测到对应异常，并且立即在协议层面响应，关断第二电子设备801的充电路径，使得Vbus下降到零。也就是说，通过最小的硬件改动，与UART底层逻辑和软件进行配合，从而第二电子设备也能够实现充电线缆拔出异常的快速检测功能。
本申请实施例提供了一种通信检测方法，具体是一种快速检测UFCS通信线缆拔出的方法。该方法应用于第二电子设备，第二电子设备通过通信线缆与第一电子设备建立连接，第一电子设备用于为第二电子设备充电，第二电子设备至少包括第一引脚和第二引脚，且第二引脚与地之间串接第一电阻；这样，在收发通信的过程中，检测第二引脚处的信号电平；在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数据帧；在第一数据帧的标识位的信号电平为低电平时，第二电子设备停止与第一电子设备的充电通路，第一数据帧的标识位的信号电平用于指示数据帧通信异常。如此，对于第二电子设备(例如待充电设备)而言，由于第二引脚与地之间串接有第一电阻，在通信线缆与第 一电子设备或第二电子设备断开连接时，那么第二引脚处的信号电平将会持续处于低电平，导致第一数据帧的标识位的信号电平无法检测到高电平，从而能够快速实现通信线缆拔出的异常检测；而且相比于相关技术，能够缩短检测时间，而且还能够将整个响应时间控制在亚毫秒级，进而还能够提升充电过程的安全性。
本申请的又一实施例中，基于前述实施例的通信检测方法，以第一电子设备为供电设备，第二电子设备为待充电设备为例，为了在供电设备侧和待充电设备侧均能够快速检测到通信线缆拔出异常，那么可以同时在供电设备侧的第二引脚RX与地之间串接第一电阻Rd1，以及在待充电设备侧的第二引脚RX与地之间串接第二电阻Rd2。
也就是说，在一些实施例中，本申请实施例提供了一种充电***，该充电***可以包括：
第一电子设备，第一电子设备至少包括第一引脚和第二引脚，且第一电子设备的第二引脚与地之间串接第一电阻；
第二电子设备，第二电子设备至少包括第一引脚和第二引脚，且第二电子设备的第二引脚与地之间串接第二电阻；
其中，第一电子设备通过通信线缆与第二电子设备建立连接，用于为第二电子设备充电。
进一步地，对于第一电子设备而言，在一种具体的实施例中，第一电子设备，用于通过第一引脚和第二引脚，与第二电子设备进行收发通信；在收发通信的过程中，检测第二引脚处的信号电平；在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数据帧；以及在第一数据帧的标识位的信号电平为低电平时，第一电子设备停止与第二电子设备的充电通路，第一数据帧的标识位的信号电平用于指示数据帧通信异常。
在一些实施例中，第一电子设备，还用于在第一数据帧的标识位的信号电平为低电平时，向第二电子设备发送第一消息，以使得第二电子设备根据第一消息停止与第一电子设备的充电通路；其中，第一消息用于指示第一电子设备的第二引脚存在接收异常。
进一步地，对于第二电子设备而言，在另一种具体的实施例中，第二电子设备，用于通过第一引脚和第二引脚，与第一电子设备进行收发通信；在收发通信的过程中，检测第二引脚处的信号电平；在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数据帧；以及在第一数据帧的标识位的信号电平为低电平时，第二电子设备停止与第一电子设备的充电通路，第一数据帧的标识位的信号电平用于指示数据帧通信异常。
在一些实施例中，第二电子设备，还用于在第一数据帧的标识位的信号电平为低电平时，向第一电子设备发送第二消息，以使得第一电子设备根据第二消息停止与第二电子设备的充电通路；其中，第二消息用于指示第二电子设备的第二引脚存在接收异常。
示例性地，参见图9，其示出了本申请实施例提供的又一种通信检测方法的应用场景示意图。如图9所示，该应用场景可以包括第一电子设备(供电设备)901、第二电子设备(待充电设备)902和通信线缆903。其中，供电设备901可以包括第一引脚TX、第二引脚RX、第三引脚GND和第四引脚Vbus，待充电设备902可以包括第五引脚RX、第六引脚TX、第七引脚GND和第八引脚Vbus，通信线缆903可以包括D+线、D-线、Vbus线和GND线。另外，供电设备901中的第二引脚RX与第三引脚GND之间连接有第一电阻Rd1，待充电设备902中的第五引脚RX与第七引脚GND之间连接有第二电阻Rd2。
在图9中，Vbus线连接在供电设备901中的第四引脚Vbus和待充电设备902中的第八引脚Vbus之间，GND线连接在供电设备901中的第三引脚GND和待充电设备902中的第七引脚GND之间，D+线连接在供电设备901中的第一引脚TX和待充电设备902中的第五引脚RX之间，D-线连接在供电设备901中的第二引脚RX和待充电设备902中的第六引脚TX之间。
可以理解地，以相关技术的图2为例，在充电过程中拔出通信线缆时，按照已有的超时检测机制，最长需要两次通信的间隔，即需要经过一个通信周期。按照UFCS标准默认参数设计，假定每1000毫秒通信一次，而通信的最小数据是5字节(Ping消息)，最快的通信波特率115200比特率(bit per second，bps)，那么在拔出通信线缆后，需要1000.434毫秒才能够做出识别。即使在最快的超时检测(通信间隔不存在)的情况下，也需要434微秒(microsecond，us)以上才能做出识别(这种情况下通信负荷过重，***已经难以正常工作)。
基于此，在硬件电路方面，本申请实施例仅需要在供电设备901和/或待充电设备902的RX引脚与地之间增加下拉电阻。这样，在通信线缆拔出时，供电设备901和/或待充电设备902能够快速检测到对应异常，并且立即在协议层面进行响应，关断相应的输出功率。
进一步地，图5示出了标准UART的数据帧组成，包括1bit的起始位，8bit的数据位，1bit的奇偶校验位，1bit的停止位，1bit的空闲位。UART物理层的特点是停止位、空闲位均为高电平。以供电设备901侧为例，本技术方案可以在供电设备901的RX引脚处增加一个下拉电阻Rd1，这样，在通信线 缆拔出后，供电设备901的RX引脚会出现下降沿事件，触发UART数据帧的通信机制。但是由于通信线缆拔出后RX引脚处的信号电平一直处于低电平，从而在停止位无法检测到高电平，触发UART通信错误。供电设备901在检测到UART通信错误后，可以去再次确认RX引脚处的信号电平，如果发现RX引脚处的信号电平仍然为低电平，那么可以识别到通信线缆拔出异常，触发应用程序立即终止充电过程。
通常情况下，在UFCS标准中可以去掉奇偶校验位，这时候的UART数据帧如图10A所示。如果供电设备901的RX引脚(或者说，D-线)被连续拉低10bit，那么也能够会识别到停止位为低电平，具体如图10B所示，这时候的数据位全部为0，停止位出错，代表UART通信错误(异常状态)，可以触发帧错误中断机制，从而识别到通信线缆拔出异常，供电设备会立即停止输出功率。
这样，在UFCS充电过程中，从通信线缆拔出出到供电设备停止输出功率，中间的时间会被压缩到UART数据帧接收完一个字节的时间，当波特率为115200bps时，这时候的识别时间＝(1+8+1)/115200＝86.8us，远远低于通信超时检测机制下的识别时间。
需要说明的是，在本申请实施例中，在任意通信帧的间隔时间下，本技术方案都可以迅速响应通信线缆拔出的异常。
还需要说明的是，在本申请实施例中，上述情况不仅适用于供电设备901(例如适配器)，同样也可以适用于待充电设备902(例如智能手机)。也就是说，本申请的技术方案不仅适用于UFCS标准中适配器侧的充电拔线异常检测，同样适用于UFCS标准中智能手机侧的充电拔线异常检测，只需要在智能手机侧的RX引脚(或者说，D+线)对地串联一颗下拉电阻Rd2即可实现。
通过上述实施例，对前述实施例的具体实现进行了详细阐述，从中可以看出，这里提出了一种快速实现UFCS通信线缆拔出的检测方案，基于最小的硬件改动，搭配UART底层逻辑和软件，实现快速的充电拔线异常检测功能；具体来说，相比于通信超时的检测方案，大大缩短UFCS充电拔线异常的检测，做到亚毫秒级的响应速度，以便将整个响应时间控制在亚毫秒级，而且对于充电***的安全性提升，均有十分重要的价值。
本申请的再一实施例中，基于前述实施例相同的发明构思，参见图11，其示出了本申请实施例提供的一种通信检测装置的组成结构示意图。如图11所示，通信检测装置110可以包括通信单元1101、检测单元1102和控制单元1103。
在一种具体的实施例中，通信检测装置110应用于第一电子设备，而且第一电子设备通过通信线缆与第二电子设备建立连接，第一电子设备用于为第二电子设备充电，第一电子设备至少可以包括第一引脚和第二引脚，第二引脚与地之间串接第一电阻。
在一些实施例中，通信单元1101，配置为通过第一引脚和第二引脚，与第二电子设备进行收发通信；
检测单元1102，配置为在收发通信的过程中，检测第二引脚处的信号电平；以及在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数据帧；
控制单元1103，配置为在第一数据帧的标识位的信号电平为低电平时，第一电子设备停止与第二电子设备的充电通路，第一数据帧的标识位的信号电平用于指示数据帧通信异常。
在一些实施例中，第一数据帧包括下述至少一项：起始字段、数据字段、奇偶校验字段、停止字段和空闲字段；其中，起始字段对应一个起始位，数据字段对应八个数据位，奇偶校验字段对应一个奇偶校验位，停止字段对应一个停止位，空闲字段对应一个空闲位。
在一些实施例中，检测单元1102，还配置为若第二引脚接收到的连续预设位数的信号电平均为低电平，则确定第一数据帧的标识位的信号电平为低电平。
在一些实施例中，检测单元1102，还配置为若第二引脚接收到的第预设数值位的信号电平为低电平，则确定第一数据帧的标识位的信号电平为低电平。
在一些实施例中，控制单元1103，还配置为在触发第二引脚开始接收第一数据帧之后，在第一数据帧的标识位的信号电平为低电平时，向第二电子设备发送第一消息，以使得第二电子设备根据第一消息停止与第一电子设备的充电通路；其中，第一消息用于指示第一电子设备的第二引脚存在接收异常。
在一些实施例中，通信线缆至少包括正信号数据线和负信号数据线；其中，第一引脚为连接正信号数据线的引脚，第二引脚为连接负信号数据线的引脚。
在另一种具体的实施例中，通信检测装置110应用于第二电子设备，而且第二电子设备通过通信线缆与第一电子设备建立连接，第一电子设备用于为第二电子设备充电，第二电子设备至少可以包括第一引脚和第二引脚，第二引脚与地之间串接第一电阻。
在一些实施例中，通信单元1101，配置为通过第一引脚和第二引脚，与第一电子设备进行收发通 信；
检测单元1102，配置为在收发通信的过程中，检测第二引脚处的信号电平；以及在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数据帧；
控制单元1103，配置为在第一数据帧的标识位的信号电平为低电平时，第二电子设备停止与第一电子设备的充电通路，第一数据帧的标识位的信号电平用于指示数据帧通信异常。
在一些实施例中，第一数据帧包括下述至少一项：起始字段、数据字段、奇偶校验字段、停止字段和空闲字段；其中，起始字段对应一个起始位，数据字段对应八个数据位，奇偶校验字段对应一个奇偶校验位，停止字段对应一个停止位，空闲字段对应一个空闲位。
在一些实施例中，检测单元1102，还配置为若第二引脚接收到的连续预设位数的信号电平均为低电平，则确定第一数据帧的标识位的信号电平为低电平。
在一些实施例中，检测单元1102，还配置为若第二引脚接收到的第预设数值位的信号电平为低电平，则确定第一数据帧的标识位的信号电平为低电平。
在一些实施例中，控制单元1103，还配置为在触发第二引脚开始接收第一数据帧之后，在第一数据帧的标识位的信号电平为低电平时，向第一电子设备发送第二消息，以使得第一电子设备根据第二消息停止与第二电子设备的充电通路；其中，第二消息用于指示第二电子设备的第二引脚存在接收异常。
在一些实施例中，通信线缆至少包括正信号数据线和负信号数据线；其中，第一引脚为连接负信号数据线的引脚，第二引脚为连接正信号数据线的引脚。
可以理解地，在本实施例中，“单元”可以是部分电路、部分处理器、部分程序或软件等等，当然也可以是模块，还可以是非模块化的。而且在本实施例中的各组成部分可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
所述集成的单元如果以软件功能模块的形式实现并非作为独立的产品进行销售或使用时，可以存储在一个计算机可读取存储介质中，基于这样的理解，本实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或processor(处理器)执行本实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
因此，本实施例提供了一种计算机可读存储介质，该计算机可读存储介质存储有计算机程序，所述计算机程序被至少一个处理器执行时实现前述实施例中任一项所述的方法的步骤。
基于上述通信检测装置110的组成以及计算机可读存储介质，参见图12，其示出了本申请实施例提供的一种电子设备的具体硬件结构示意图。如图12所示，电子设备120可以包括：通信接口1201、存储器1202和处理器1203；各个组件通过总线***1204耦合在一起。可理解，总线***1204用于实现这些组件之间的连接通信。总线***1204除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图12中将各种总线都标为总线***1204。
在一种具体的实施例中，电子设备120可以为第一电子设备，这时候的电子设备120通过通信线缆与第二电子设备连接，用于为第二电子设备充电，而且通信接口1201至少可以包括第一引脚TX和第二引脚RX，且第二引脚RX与地之间串接有第一电阻Rd-。其中，
通信接口1201，用于在与其他外部网元(例如，第二电子设备)之间进行收发信息过程中，信号的接收和发送；
存储器1202，用于存储能够在处理器1203上运行的计算机程序；
处理器1203，用于在运行计算机程序时，执行：
通过第一引脚和第二引脚，与第二电子设备进行收发通信；
在收发通信的过程中，检测第二引脚处的信号电平；
在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数据帧；
在第一数据帧的标识位的信号电平为低电平时，第一电子设备停止与第二电子设备的充电通路，所述第一数据帧的标识位的信号电平用于指示数据帧通信异常。
在另一种具体的实施例中，电子设备120可以为第二电子设备，这时候的电子设备120通过通信线缆与第一电子设备连接，第一电子设备用于为该电子设备充电，而且通信接口1201也至少可以包括第一引脚TX和第二引脚RX，且第二引脚RX与地之间串接有第一电阻Rd-。其中，
通信接口1201，用于在与其他外部网元(例如，第一电子设备)之间进行收发信息过程中，信号的接收和发送；
存储器1202，用于存储能够在处理器1203上运行的计算机程序；
处理器1203，用于在运行计算机程序时，执行：
通过第一引脚和第二引脚，与第一电子设备进行收发通信；
在收发通信的过程中，检测第二引脚处的信号电平；
在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数据帧；
在第一数据帧的标识位的信号电平为低电平时，第二电子设备停止与第一电子设备的充电通路，所述第一数据帧的标识位的信号电平用于指示数据帧通信异常。
可以理解的是，本申请实施例中的存储器1202可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDRSDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步链动态随机存取存储器(Synchronous link DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DRRAM)。本文描述的***和方法的存储器1202旨在包括但不限于这些和任意其它适合类型的存储器。
而处理器1203可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器1203中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器1203可以是通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器1202，处理器1203读取存储器1202中的信息，结合其硬件完成上述方法的步骤。
还可以理解的是，本文描述的这些实施例可以用硬件、软件、固件、中间件、微码或其组合来实现。对于硬件实现，处理单元可以实现在一个或多个专用集成电路(Application Specific Integrated Circuits，ASIC)、数字信号处理器(Digital Signal Processing，DSP)、数字信号处理设备(DSP Device，DSPD)、可编程逻辑设备(Programmable Logic Device，PLD)、现场可编程门阵列(Field-Programmable Gate Array，FPGA)、通用处理器、控制器、微控制器、微处理器、用于执行本申请所述功能的其它电子单元或其组合中。
对于软件实现，可通过执行本文所述功能的模块(例如过程、函数等)来实现本文所述的技术。软件代码可存储在存储器中并通过处理器执行。存储器可以在处理器中或在处理器外部实现。
可选地，作为另一个实施例，处理器1203还配置为在运行所述计算机程序时，执行前述实施例中任一项所述的方法的步骤。
需要说明的是，在本申请中，当处理器为通用处理器、DSP、ASIC、FPGA或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件时，存储器可以集成在处理器中。另外，本申请描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
还需要说明的是，在本申请中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
本申请所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本申请所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本申请所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新 的方法实施例或设备实施例。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
工业实用性
本申请实施例中，第一电子设备通过通信线缆与第二电子设备建立连接，第一电子设备用于为第二电子设备充电；其中，该方法可以应用于第一电子设备，第一电子设备至少包括第一引脚和第二引脚，且第二引脚与地之间串接第一电阻；或者，该方法也可以应用于第二电子设备，第二电子设备至少包括第一引脚和第二引脚，且第二引脚与地之间串接第一电阻。这样，通过第一引脚和第二引脚，与对端进行收发通信；在收发通信的过程中，检测第二引脚处的信号电平；在检测到第二引脚处的信号电平由高电平变换为低电平时，触发第二引脚开始接收第一数据帧；在第一数据帧的标识位的信号电平为低电平时，停止第一电子设备与第二电子设备的充电通路，第一数据帧的标识位的信号电平用于指示数据帧通信异常。如此，由于第二引脚与地之间串接有第一电阻，如果检测到第一数据帧的标识位的信号电平为低电平，意味着数据帧发生通信异常，那么可以由第一电子设备停止与第二电子设备的充电通路或者由第二电子设备停止与第一电子设备的充电通路，从而能够快速实现通信异常的检测；而且相比于相关技术，能够大大缩短检测时间，并且将整个响应时间控制在亚毫秒级，进而提升了充电过程的安全性。

Claims (21)

  1. 一种通信检测方法，应用于第一电子设备，所述第一电子设备通过通信线缆与第二电子设备建立连接，所述第一电子设备用于为所述第二电子设备充电，所述第一电子设备至少包括第一引脚和第二引脚，且所述第二引脚与地之间串接第一电阻；所述方法包括：
    通过所述第一引脚和所述第二引脚，与所述第二电子设备进行收发通信；
    在所述收发通信的过程中，检测所述第二引脚处的信号电平；
    在检测到所述第二引脚处的信号电平由高电平变换为低电平时，触发所述第二引脚开始接收第一数据帧；
    在所述第一数据帧的标识位的信号电平为低电平时，所述第一电子设备停止与所述第二电子设备的充电通路，所述第一数据帧的标识位的信号电平用于指示数据帧通信异常。
  2. 根据权利要求1所述的方法，其中，所述第一数据帧包括下述至少一项：起始字段、数据字段、奇偶校验字段、停止字段和空闲字段；
    其中，所述起始字段对应一个起始位，所述数据字段对应八个数据位，所述奇偶校验字段对应一个奇偶校验位，所述停止字段对应一个停止位，所述空闲字段对应一个空闲位。
  3. 根据权利要求1所述的方法，其中，所述方法还包括：
    若所述第二引脚接收到的连续预设位数的信号电平均为低电平，则确定所述第一数据帧的标识位的信号电平为低电平。
  4. 根据权利要求1所述的方法，其中，所述方法还包括：
    若所述第二引脚接收到的第预设数值位的信号电平为低电平，则确定所述第一数据帧的标识位的信号电平为低电平。
  5. 根据权利要求1所述的方法，其中，在所述触发所述第二引脚开始接收第一数据帧之后，所述方法还包括：
    在所述第一数据帧的标识位的信号电平为低电平时，向所述第二电子设备发送第一消息，以使得所述第二电子设备根据所述第一消息停止与所述第一电子设备的充电通路；其中，所述第一消息用于指示所述第一电子设备的第二引脚存在接收异常。
  6. 根据权利要求1至5中任一项所述的方法，其中，所述通信线缆至少包括正信号数据线和负信号数据线；
    其中，所述第一引脚为连接所述正信号数据线的引脚，所述第二引脚为连接所述负信号数据线的引脚。
  7. 一种通信检测方法，应用于第二电子设备，所述第二电子设备通过通信线缆与第一电子设备建立连接，所述第一电子设备用于为所述第二电子设备充电，所述第二电子设备至少包括第一引脚和第二引脚，且所述第二引脚与地之间串接第一电阻；所述方法包括：
    通过所述第一引脚和所述第二引脚，与所述第二电子设备进行收发通信；
    在所述收发通信的过程中，检测所述第二引脚处的信号电平；
    在检测到所述第二引脚处的信号电平由高电平变换为低电平时，触发所述第二引脚开始接收第一数据帧；
    在所述第一数据帧的标识位的信号电平为低电平时，所述第二电子设备停止与所述第一电子设备的充电通路，所述第一数据帧的标识位的信号电平用于指示数据帧通信异常。
  8. 根据权利要求7所述的方法，其中，所述第一数据帧包括下述至少一项：起始字段、数据字段、奇偶校验字段、停止字段和空闲字段；
    其中，所述起始字段对应一个起始位，所述数据字段对应八个数据位，所述奇偶校验字段对应一个奇偶校验位，所述停止字段对应一个停止位，所述空闲字段对应一个空闲位。
  9. 根据权利要求7所述的方法，其中，所述方法还包括：
    若所述第二引脚接收到的连续预设位数的信号电平均为低电平，则确定所述第一数据帧的标识位的信号电平为低电平。
  10. 根据权利要求7所述的方法，其中，所述方法还包括：
    若所述第二引脚接收到的第预设数值位的信号电平为低电平，则确定所述第一数据帧的标识位的信号电平为低电平。
  11. 根据权利要求7所述的方法，其中，在所述触发所述第二引脚开始接收第一数据帧之后，所述方法还包括：
    在所述第一数据帧的标识位的信号电平为低电平时，向所述第一电子设备发送第二消息，以使得所述第一电子设备根据所述第二消息停止与所述第二电子设备的充电通路；其中，所述第二消息用于指示所述第二电子设备的第二引脚存在接收异常。
  12. 根据权利要求7至11中任一项所述的方法，其中，所述通信线缆至少包括正信号数据线和负信号数据线；
    其中，所述第一引脚为连接所述负信号数据线的引脚，所述第二引脚为连接所述正信号数据线的引脚。
  13. 一种通信检测装置，应用于第一电子设备，所述第一电子设备至少包括第一引脚和第二引脚，且所述第二引脚与地之间串接第一电阻；所述通信检测装置包括通信单元、检测单元和控制单元；其中，
    所述通信单元，配置为通过所述第一引脚和所述第二引脚，与所述第二电子设备进行收发通信；
    所述检测单元，配置为在所述收发通信的过程中，检测所述第二引脚处的信号电平；以及在检测到所述第二引脚处的信号电平由高电平变换为低电平时，触发所述第二引脚开始接收第一数据帧；
    所述控制单元，配置为在所述第一数据帧的标识位的信号电平为低电平时，所述第一电子设备停止与所述第二电子设备的充电通路，所述第一数据帧的标识位的信号电平用于指示数据帧通信异常。
  14. 一种通信检测装置，应用于第二电子设备，所述第二电子设备至少包括第一引脚和第二引脚，且所述第二引脚与地之间串接第一电阻；所述通信检测装置包括通信单元、检测单元和控制单元；其中，
    所述通信单元，配置为通过所述第一引脚和所述第二引脚，与所述第一电子设备进行收发通信；
    所述检测单元，配置为在所述收发通信的过程中，检测所述第二引脚处的信号电平；以及在检测到所述第二引脚处的信号电平由高电平变换为低电平时，触发所述第二引脚开始接收第一数据帧；
    所述控制单元，配置为在所述第一数据帧的标识位的信号电平为低电平时，所述第二电子设备停止与所述第一电子设备的充电通路，所述第一数据帧的标识位的信号电平用于指示数据帧通信异常。
  15. 一种电子设备，所述电子设备包括通信接口、存储器和处理器，所述通信接口至少包括第一引脚和第二引脚，且所述第二引脚与地之间串接第一电阻；其中，
    所述通信接口，用于与其他外部网元之间进行信息的接收和发送；
    所述存储器，用于存储能够在所述处理器上运行的计算机程序；
    所述处理器，用于在运行所述计算机程序时，执行如权利要求1至6中任一项所述的方法、或者权利要求7至12中任一项所述的方法。
  16. 一种充电***，所述充电***包括：
    第一电子设备，所述第一电子设备至少包括第一引脚和第二引脚，且所述第一电子设备的第二引脚与地之间串接第一电阻；
    第二电子设备，所述第二电子设备至少包括第一引脚和第二引脚，且所述第二电子设备的第二引脚与地之间串接第二电阻；
    其中，所述第一电子设备通过通信线缆与所述第二电子设备建立连接，用于为所述第二电子设备充电。
  17. 根据权利要求16所述的充电***，其中，
    所述第一电子设备，用于通过所述第一引脚和所述第二引脚，与所述第二电子设备进行收发通信；在所述收发通信的过程中，检测所述第二引脚处的信号电平；在检测到所述第二引脚处的信号电平由高电平变换为低电平时，触发所述第二引脚开始接收第一数据帧；以及在所述第一数据帧的标识位的信号电平为低电平时，所述第一电子设备停止与所述第二电子设备的充电通路，所述第一数据帧的标识位的信号电平用于指示数据帧通信异常。
  18. 根据权利要求17所述的充电***，其中，
    所述第一电子设备，还用于在所述第一数据帧的标识位的信号电平为低电平时，向所述第二电子设备发送第一消息，以使得所述第二电子设备根据所述第一消息停止与所述第一电子设备的充电通路；其中，所述第一消息用于指示所述第一电子设备的第二引脚存在接收异常。
  19. 根据权利要求16所述的充电***，其中，
    所述第二电子设备，用于通过所述第一引脚和所述第二引脚，与所述第一电子设备进行收发通信；在所述收发通信的过程中，检测所述第二引脚处的信号电平；在检测到所述第二引脚处的信号电平由高电平变换为低电平时，触发所述第二引脚开始接收第一数据帧；以及在所述第一数据帧的标识位的信号电平为低电平时，所述第二电子设备停止与所述第一电子设备的充电通路，所述第一数据帧的标识位的信号电平用于指示数据帧通信异常。
  20. 根据权利要求19所述的充电***，其中，
    所述第二电子设备，还用于在所述第一数据帧的标识位的信号电平为低电平时，向所述第一电子设 备发送第二消息，以使得所述第一电子设备根据所述第二消息停止与所述第二电子设备的充电通路；其中，所述第二消息用于指示所述第二电子设备的第二引脚存在接收异常。
  21. 一种计算机可读存储介质，其中，所述计算机可读存储介质存储有计算机程序，所述计算机程序被至少一个处理器执行时实现如权利要求1至6中任一项所述的方法、或者权利要求7至12中任一项所述的方法。
PCT/CN2022/141390 2022-06-27 2022-12-23 一种通信检测方法、装置、设备、***以及存储介质 WO2024001105A1 (zh)

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