WO2024000791A1 - Dem structure for improving dynamic performance of dac at extremely low temperature - Google Patents

Dem structure for improving dynamic performance of dac at extremely low temperature Download PDF

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WO2024000791A1
WO2024000791A1 PCT/CN2022/116152 CN2022116152W WO2024000791A1 WO 2024000791 A1 WO2024000791 A1 WO 2024000791A1 CN 2022116152 W CN2022116152 W CN 2022116152W WO 2024000791 A1 WO2024000791 A1 WO 2024000791A1
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bit
random
signal
output
input terminal
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PCT/CN2022/116152
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French (fr)
Chinese (zh)
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卓壮
雒超
曹刚
郭国平
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中国科学技术大学
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
    • H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
    • H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
    • H03M1/0665—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching using data dependent selection of the elements, e.g. data weighted averaging
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters

Definitions

  • the present disclosure relates to the field of integrated circuit technology, and in particular to a glitch-weakened DEM (Dynamic Element Matching) structure that improves the dynamic performance of digital-to-analog converters under extremely low temperature (-269°C and below) conditions.
  • DEM Dynamic Element Matching
  • DAC Digital to analog converter, digital-to-analog converter
  • the current rudder type DAC can meet the needs of high speed and high precision due to its structural characteristics.
  • the performance of the DAC will be greatly affected.
  • the threshold voltage of lower MOS tubes becomes higher, carriers freeze, and the mismatch of tubes in the same area is greater.
  • DEM technology can be used to improve the dynamic performance of DACs under high mismatch conditions.
  • traditional DEMs have problems such as complex structure, weak randomness, high number of switches, and high power consumption. Therefore, there is an urgent need for a method that can effectively improve the DAC at extremely low temperatures.
  • DEM structure that has dynamic performance and can weaken the burrs caused by switching on and off.
  • the present disclosure provides a DEM structure that improves the dynamic performance of a DAC at extremely low temperatures, including: a signal input terminal, a random control signal module, and a random shift circuit.
  • the signal input terminal is configured to receive a three-digit binary input signal
  • the random control signal module is connected to the signal input terminal and is configured to generate a random control signal based on the three-digit binary input signal
  • the random shift circuit includes a first input terminal and a second input terminal.
  • the first input terminal is connected to the signal input terminal.
  • the second input terminal is connected to the random control signal module.
  • the random shift circuit is configured Used to decode the three-digit binary input signal into a seven-digit thermometer code according to the random control signal.
  • the random control signal module includes: a pseudo-random number generator circuit, a logic shift circuit, a three-bit adder, a multiplexer, and a four-bit subtractor.
  • the pseudo-random number generator circuit is configured to generate a pseudo-random code; the logic shift circuit is connected to the signal input end and is configured to shift the three-digit binary input signal; the three-digit adder is simultaneously connected to the pseudo-random number
  • the generator circuit is connected to the logic shift circuit and is configured to add the pseudo-random code and the shifted three-digit binary input signal to generate an adder output signal; the multiplexer is configured to According to the carry output of the three-bit adder, a three-bit output signal of all zeros or all ones is output; a four-bit subtractor is connected to the multiplexer and the three-bit adder at the same time and is configured to The adder output signal and the three-digit output signal are subtracted bit by bit to generate a random control signal.
  • the logic shift circuit includes three input signals and four output signals; one of the SEL output signals provides a clock for the pseudo-random number generator circuit.
  • the logic shift circuit is configured so that if and only when the three-digit binary input signal is all zeros or all ones, the SEL output signal changes, and the pseudo-random number generator generates a new random code.
  • the pseudo-random number generator circuit includes a plurality of D flip-flops, OR gates, NOR gates, and XOR gates;
  • the multi-input NOR gate ensures that the pseudo-random number generator circuit can work normally and avoids all zeros.
  • the XOR gate is It is constructed so that the output of the D flip-flop changes every clock cycle.
  • the pseudo-random number circuit can realize that the output does not repeat within (215-1) cycles.
  • the three-bit adder circuit adopts a serial carry adder structure, including three one-bit full adders, and uses multiple clock cycles to complete the three-bit addition operation.
  • the four-bit subtractor adopts a bit-by-bit subtraction structure and includes four one-bit subtractors.
  • the random control signal output by the four-bit subtractor will be connected to the shift of the random shift circuit through a NOT gate.
  • the signal terminal is controlled so that when the three-digit binary input signal is all zeros or all ones, the output seven-digit thermometer code is shifted.
  • the multiplexer includes three one-bit multiplexers, and the three-bit output signal is determined according to the carry signal of the three-bit adder. If the three-bit adder generates a carry signal, the multiplexer output Three high-level signals, otherwise three low-level signals are output.
  • the random shift circuit includes three rows and seven columns of multiplexer units.
  • the output control signal of the multiplexer unit in each row is controlled by the random control signal output by the four-bit subtractor.
  • the three-bit binary input The signals are individually connected to seven columns of multiplexer units in a binary weight ratio.
  • the present disclosure provides a DEM structure that improves the dynamic performance of a DAC at extremely low temperatures, which can effectively alleviate technical problems in the prior art such as the deterioration of dynamic performance caused by increased transistor mismatch in digital-to-analog converters operating at extremely low temperatures.
  • this DEM decoding structure can randomly decode the input binary code and randomly disrupt the decoding order while ensuring that the output is correct.
  • the random mismatch of the tube is compensated, which can improve the dynamic performance of the digital-to-analog converter under harsh process or environmental conditions; the DEM structure is simple, the area and power consumption are lower than that of the conventional DEM decoder, and it is more efficient in decoding.
  • thermometer decoder There will be no redundant switch switching times during the coding process, which reduces the glitches caused by high-speed switching during the working process.
  • the output result is the same as the output result of the thermometer decoder, and there will be no extra signal that is always low level. link, which also brings convenience to the design of differential output digital-to-analog converters; the number of switching times is the same as that of a traditional thermometer decoder, which is lower than that of a conventional DEM decoder, minimizing the effect of a large number of switching times on Here comes the glitch problem.
  • Figure 1 is a schematic diagram of a DEM structure for improving the dynamic performance of a DAC at extremely low temperatures according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a logic shift circuit in an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of the circuit structure of a pseudo-random number generator in an embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of a random shift circuit in an embodiment of the present disclosure.
  • Figure 5 is a schematic diagram of the DEM structure decoding results for improving the dynamic performance of the DAC at extremely low temperatures according to an embodiment of the present disclosure.
  • Figure 6 is a schematic diagram of the SFDR distribution based on traditional thermometer decoding.
  • Figure 7 is a schematic diagram of SFDR distribution for decoding based on the DEM structure of an embodiment of the present disclosure.
  • the present disclosure provides a DEM-II structure that improves the dynamic performance of a DAC at extremely low temperatures. It can maintain the minimum number of switching while completing random decoding, and can improve the dynamic performance of the DAC at extremely low temperatures.
  • a DEM structure that improves the dynamic performance of a DAC at extremely low temperatures.
  • the DEM structure includes:
  • the signal input terminal is configured to receive a three-digit binary input signal
  • a random control signal module connected to the signal input terminal and configured to generate a random control signal based on the three-digit binary input signal
  • a random shift circuit includes a first input terminal and a second input terminal.
  • the first input terminal is connected to the signal input terminal.
  • the second input terminal is connected to the random control signal module.
  • the random shift circuit is Configured for decoding the three-digit binary input signal into a seven-digit thermometer code according to the random control signal.
  • the random control signal module includes:
  • PRNG pseudo-random number generator circuit
  • a logic shift circuit connected to the signal input terminal, is configured to shift the three-digit binary input signal
  • a three-digit adder simultaneously connected to the pseudo-random number generator circuit and the logic shift circuit, is configured to add the pseudo-random code and the shifted three-digit binary input signal to generate an adder. output signal;
  • a multiplexer configured to output a three-digit output signal of all zeros or all ones according to the carry output of the three-digit adder
  • a four-bit subtractor simultaneously connected to the multiplexer and the three-bit adder, is configured to subtract the adder output signal and the three-bit output signal bit by bit to generate a random control signal.
  • the logic shift circuit includes multiple NOT gates, OR gates, and AND gates (specifically, it includes three NOT gates, two three-input AND gates, and two two-input AND gates. , three two-input OR gates), receive three input signals (three-digit binary input signals B0, B1, B2), and generate four output signals (A0, A1, A2, SEL), one of which is pseudo-random SEL output signal
  • the number generator circuit provides a clock. If and only when the three-digit binary input signal is all zeros or all ones, the SEL output signal changes, and the pseudo-random number generator generates a new random code.
  • the pseudo-random number generator circuit includes multiple D flip-flops, OR gates, NOR gates, and XOR gates, specifically 15 D flip-flops (Q 0 -Q 14 ), a two-input OR gate, a two-input XOR gate, a fifteen-input NOR gate (NOR), in which 15 D flip-flops are continuously shifted under the control of the clock, and the multi-input NOR gate ensures that the circuit It can work normally and avoid the situation of all zeros.
  • the XOR gate can make the output of the D flip-flop change after shifting in each clock cycle.
  • the pseudo-random number circuit can be implemented in (2 15 -1) cycles. The internal output does not repeat, so this circuit can be used to generate approximate random numbers.
  • the three-digit adder circuit adopts a serial carry adder structure, which is simpler than the carry-lookahead adder structure. It is mainly composed of a NOT gate, a multi-input AND gate, and a multi-input OR gate. It contains Three one-bit full adders use multiple clock cycles to complete a three-bit addition operation.
  • the serial carry adder is not as fast as the carry-lookahead adder, it takes up less resources and can implement basic addition operations.
  • the multiplexer can output a three-digit output signal of all zeros or all ones according to the carry output of the three-digit adder, and further subtract it from the output of the three-digit adder to obtain the control Random control signal for the random shift circuit.
  • the three-bit multiplexer specifically includes three one-bit multiplexers, which are composed of AND gates, NOT gates, OR gates and other gate circuits. The three-bit output signal is determined by the carry signal of the three-bit adder. If the three-bit adder When a carry signal is generated, the three-bit multiplexer outputs three high-level signals (all one signals), otherwise it outputs three low-level signals (all zero signals).
  • the four-bit subtractor is used to subtract the output signal of the three-bit adder and the three-bit output signal of the three-bit multiplexer. Similar to the three-bit adder, the subtractor adopts It is a bit-by-bit subtraction structure, which is composed of four one-bit subtractors internally.
  • a single one-bit subtractor includes an AND gate, an OR gate and an XOR gate. The output of the four-bit subtractor will be connected to the random shift circuit through a NOT gate.
  • the shift control signal terminal is such that when the input three-digit binary code is all zeros or all ones, the output seven-digit thermometer code is shifted, so that in the process of continuous switching of the switch, the last opened/closed switch When the next clock arrives, priority is still given to opening/closing, which can minimize glitches caused by a large number of switch switching times.
  • the random shift circuit includes multiple multiplexers (MUX), the input of which is a three-bit binary code (B0, B1, B2), and the output is a seven-bit binary code.
  • Thermometer code W1-W7
  • PRBS0, PRBS1 in this random shift circuit PRBS2
  • PRBS2 is determined by a three-digit binary input signal.
  • the overall layout of the random shift circuit is divided into three rows and seven columns, including three rows and seven columns of multiplexer units.
  • Each row of multiplexer units includes 7 multiplexers, and each column of multiplexers
  • the unit includes 3 multiplexers, consisting of a total of twenty-one multiplexers.
  • the output control signal of the multiplexer unit in each row is controlled by the output of the subtractor (that is, the output of the four-bit subtractor. Random control signals PRBS0, PRBS1, PRBS2 control).
  • the three three-digit binary input signals are respectively connected to the multiplexers in the first row, which are distributed and connected according to the binary weight ratio, and then connected to the multiplexer units in each column.
  • the three-digit binary Two, four, and eight connection lines are respectively connected to the first row of multiplexer units from the input signal.
  • the specific connection method is shown in Figure 4.
  • B0 connects two lines to the first row of multiplexer units.
  • the 4th and 7th multiplexers in the multiplexer unit, B1 connects four lines to the 2nd, 3rd, 5th, and 6th multiplexers in the first row of multiplexer units, and B2 connects eight lines respectively. Lines go to multiplexers 1-7 in the first row of multiplexer cells.
  • the decoding result of the DEM decoder under the condition of -269°C where latch: 5, latch: 6, and latch: 7 in the leftmost column are input Three-digit binary codes, 5, 7, 4, 6, 1, 3, 2 are the output seven-digit thermometer codes.
  • the right side is the decoding result corresponding to the continuously changing binary input code. It can be seen that with the continuous change of latch , the seven-digit output thermometer code always keeps the channel that was turned on/off in the previous clock cycle preferentially turned on/off. It can be seen that in adjacent clock cycles, the input three-digit binary code continues to switch, and the output can still maintain switching in adjacent cycles. The number of times is the smallest, which can minimize the interference to the dynamic performance of the DAC caused by frequent switching at high frequencies.
  • the present disclosure provides a DEM structure that improves the dynamic performance of DACs at extremely low temperatures. Facing the situation where the dynamic performance of conventional digital-to-analog converters is poor in extremely low temperature environments, this DEM decoding technology can decode the input binary The code is randomly decoded, and the decoding order is randomly disrupted while ensuring the correct output, and the random mismatch of the MOS tube is compensated, which can improve the dynamic performance of the digital-to-analog converter under harsh processes or environments.
  • this DEM decoder is very simple in structure, occupies less area and consumes less power than conventional DEM decoders, and does not produce redundant switching times during the decoding process.
  • the glitch phenomenon caused by high-speed switching during operation is reduced.
  • the output result is the same as the output result of the thermometer decoder, and there is no extra signal link that is always low level. This is also the digital-to-analog conversion of differential output. It brings convenience to the design work of the device.

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Abstract

A DEM structure for improving dynamic performance of a digital-to-analog converter (DAC) at an extremely low temperature, comprising: a signal input terminal, configured to receive three-bit binary input signals (B0, B1, B2); a random control signal module, connected to the signal input terminal and configured to generate random control signals (PRBS0, PRBS1, PRBS2) according to the three-bit binary input signals (B0, B1, B2); and a random shift circuit, comprising a first input terminal and a second input terminal, the first input terminal being connected to the signal input terminal, the second input terminal being connected to the random control signal module, and the random shift circuit being configured to decode the three-bit binary input signals (B0, B1, B2) into seven-bit thermometer codes (W1-W7) according to the random control signals. The DEM structure can alleviate the technical problems in the prior art of dynamic performance deterioration and the like caused by aggravation of transistor mismatch when a DAC operates at an extremely low temperature.

Description

极低温下提升DAC动态性能的DEM结构DEM structure to improve DAC dynamic performance at extremely low temperatures 技术领域Technical field
本公开涉及集成电路技术领域，尤其涉及一种极低温(-269℃及以下)条件下提升数模转换器动态性能的毛刺削弱型DEM(DynamicElement Matching，动态元件匹配)结构。The present disclosure relates to the field of integrated circuit technology, and in particular to a glitch-weakened DEM (Dynamic Element Matching) structure that improves the dynamic performance of digital-to-analog converters under extremely low temperature (-269°C and below) conditions.
背景技术Background technique
DAC(Digital to analog converter，数模转换器)能够将离散的数字信号转化为连续的模拟信号，随着深空探测、量子计算等技术的不断发展，需要高速高精度的数模转换器在极低温下正常工作，电流舵型DAC因其结构上的特点，能够满足高速高精度的需求，但是由于极低温下工艺造成的失配加剧，会导致DAC的性能受到极大的影响，因为极低温下MOS管的阈值电压变得更高，载流子产生冻结，并且同等面积下管子的失配更大，这些问题使得低温DAC想达到与常温DAC同样的性能十分困难，必须提出新的结构来解决低温下MOS管的失配问题。DAC (Digital to analog converter, digital-to-analog converter) can convert discrete digital signals into continuous analog signals. With the continuous development of deep space exploration, quantum computing and other technologies, high-speed and high-precision digital-to-analog converters are required. Working normally at low temperatures, the current rudder type DAC can meet the needs of high speed and high precision due to its structural characteristics. However, due to the increased mismatch caused by the process at extremely low temperatures, the performance of the DAC will be greatly affected. Because of the extremely low temperature The threshold voltage of lower MOS tubes becomes higher, carriers freeze, and the mismatch of tubes in the same area is greater. These problems make it very difficult for low-temperature DACs to achieve the same performance as normal-temperature DACs, and new structures must be proposed. Solve the mismatch problem of MOS tubes at low temperatures.
DEM技术可用于提升高失配情况下的DAC动态性能，但是传统的DEM存在结构复杂、随机性弱、开关次数多、功耗大等问题，因此亟需一种能够在极低温下有效提升DAC动态性能，且能够削弱因开关通断产生的毛刺的DEM结构。DEM technology can be used to improve the dynamic performance of DACs under high mismatch conditions. However, traditional DEMs have problems such as complex structure, weak randomness, high number of switches, and high power consumption. Therefore, there is an urgent need for a method that can effectively improve the DAC at extremely low temperatures. DEM structure that has dynamic performance and can weaken the burrs caused by switching on and off.
发明内容Contents of the invention
本公开提供一种极低温下提升DAC动态性能的DEM结构，包括：信号输入端，随机控制信号模块，随机移位电路。The present disclosure provides a DEM structure that improves the dynamic performance of a DAC at extremely low temperatures, including: a signal input terminal, a random control signal module, and a random shift circuit.
信号输入端被配置用于接收三位二进制输入信号；随机控制信号模块与信号输入端相连，被配置用于根据三位二进制输入信号生成随机控制信号；The signal input terminal is configured to receive a three-digit binary input signal; the random control signal module is connected to the signal input terminal and is configured to generate a random control signal based on the three-digit binary input signal;
随机移位电路包括第一输入端和第二输入端，所述第一输入端与信号输入端相连，所述第二输入端与所述随机控制信号模块相连，所述随机移位电路被配置用于根据所述随机控制信号将所述三位二进制输入信号译码为七位温度计码。The random shift circuit includes a first input terminal and a second input terminal. The first input terminal is connected to the signal input terminal. The second input terminal is connected to the random control signal module. The random shift circuit is configured Used to decode the three-digit binary input signal into a seven-digit thermometer code according to the random control signal.
根据本公开实施例，所述随机控制信号模块，包括：伪随机数发生器电路，逻辑移位电路，三位加法器，多路复用器，四位减法器。According to an embodiment of the present disclosure, the random control signal module includes: a pseudo-random number generator circuit, a logic shift circuit, a three-bit adder, a multiplexer, and a four-bit subtractor.
伪随机数发生器电路被配置用于产生伪随机码；逻辑移位电路与信号输入端相连，被配置用于将三位二进制输入信号进行移位；三位加法器同时与所述伪随机数发生器电路和所述逻辑移位电路相连，被配置用于将伪随机码与所述移位后的三位二进制输入信号进行相加生 成加法器输出信号；多路复用器被配置用于根据所述三位加法器的进位输出，输出全零或者全一的三位输出信号；四位减法器同时与所述多路复用器和所述三位加法器相连，被配置用于将所述加法器输出信号和所述三位输出信号进行逐位相减，生成随机控制信号。The pseudo-random number generator circuit is configured to generate a pseudo-random code; the logic shift circuit is connected to the signal input end and is configured to shift the three-digit binary input signal; the three-digit adder is simultaneously connected to the pseudo-random number The generator circuit is connected to the logic shift circuit and is configured to add the pseudo-random code and the shifted three-digit binary input signal to generate an adder output signal; the multiplexer is configured to According to the carry output of the three-bit adder, a three-bit output signal of all zeros or all ones is output; a four-bit subtractor is connected to the multiplexer and the three-bit adder at the same time and is configured to The adder output signal and the three-digit output signal are subtracted bit by bit to generate a random control signal.
根据本公开实施例，逻辑移位电路包括三路输入信号，四路输出信号；其中一路SEL输出信号为伪随机数发生器电路提供时钟。According to the embodiment of the present disclosure, the logic shift circuit includes three input signals and four output signals; one of the SEL output signals provides a clock for the pseudo-random number generator circuit.
根据本公开实施例，所述逻辑移位电路被构造成当且仅当三位二进制输入信号为全零或者全1时，SEL输出信号发生变化，伪随机数发生器产生新的随机码。According to an embodiment of the present disclosure, the logic shift circuit is configured so that if and only when the three-digit binary input signal is all zeros or all ones, the SEL output signal changes, and the pseudo-random number generator generates a new random code.
根据本公开实施例，所述伪随机数发生器电路包括多个D触发器、或门、或非门、异或门；According to an embodiment of the present disclosure, the pseudo-random number generator circuit includes a plurality of D flip-flops, OR gates, NOR gates, and XOR gates;
其中D触发器为15个，15个D触发器在时钟的控制下不断移位，多输入的或非门保证伪随机数发生器电路能正常工作且避免出现全零的情况，异或门被构造成能够使得每个时钟周期下D触发器的输出移位后会有所变化。Among them, there are 15 D flip-flops, and the 15 D flip-flops are continuously shifted under the control of the clock. The multi-input NOR gate ensures that the pseudo-random number generator circuit can work normally and avoids all zeros. The XOR gate is It is constructed so that the output of the D flip-flop changes every clock cycle.
根据本公开实施例，伪随机数电路能够实现在(215-1)个周期内输出不重复。According to the embodiment of the present disclosure, the pseudo-random number circuit can realize that the output does not repeat within (215-1) cycles.
根据本公开实施例，三位加法器电路采用串行进位加法器结构，包括三个一位全加器，利用多个时钟周期完成三位的加法运算。According to an embodiment of the present disclosure, the three-bit adder circuit adopts a serial carry adder structure, including three one-bit full adders, and uses multiple clock cycles to complete the three-bit addition operation.
根据本公开实施例，四位减法器采用的是逐位相减结构，包括四个一位减法器，所述四位减法器输出的随机控制信号将经过非门连接到随机移位电路的移位控制信号端，使得当三位二进制输入信号为全零或全一时，输出的七位温度计码产生移位。According to the embodiment of the present disclosure, the four-bit subtractor adopts a bit-by-bit subtraction structure and includes four one-bit subtractors. The random control signal output by the four-bit subtractor will be connected to the shift of the random shift circuit through a NOT gate. The signal terminal is controlled so that when the three-digit binary input signal is all zeros or all ones, the output seven-digit thermometer code is shifted.
根据本公开实施例，多路复用器包括三个一位复用器，三位输出信号根据三位加法器的进位信号决定，若三位加法器产生进位信号，则多路复用器输出三路高电平信号，否则输出三路低电平信号。According to an embodiment of the present disclosure, the multiplexer includes three one-bit multiplexers, and the three-bit output signal is determined according to the carry signal of the three-bit adder. If the three-bit adder generates a carry signal, the multiplexer output Three high-level signals, otherwise three low-level signals are output.
根据本公开实施例，随机移位电路包括三行七列多路复用器单元，每一行的多路复用器单元输出控制信号由四位减法器输出的随机控制信号控制，三位二进制输入信号按照二进制的权重比例分别连接至七列多路复用器单元。According to an embodiment of the present disclosure, the random shift circuit includes three rows and seven columns of multiplexer units. The output control signal of the multiplexer unit in each row is controlled by the random control signal output by the four-bit subtractor. The three-bit binary input The signals are individually connected to seven columns of multiplexer units in a binary weight ratio.
本公开提供的一种极低温下提升DAC动态性能的DEM结构，能够有效缓解现有技术中数模转换器工作在极低温下因晶体管失配加剧带来的动态性能恶化等技术问题。面向极低温环境下常规数模转换器动态性能较差的情况，该DEM译码结构能够对输入的二进码进行随机译码，在保证输出正确的情况下随机打乱译码次序，对MOS管的随机失配进行了补偿，可在工艺或环境较为恶劣的情况下提升数模转换器的动态性能；DEM结构简洁，所占面积与功耗均低于常规DEM译码器，而且在译码过程中不会产生多余的开关切换次数，降低了工作过程中因高速切换开关导致的毛刺现象，此外输出结果与温度计译码器输出结果相同，不 会多产生一路恒为低电平的信号链路，这也为差分输出的数模转换器的设计工作带来便利；开关次数与传统的温度计译码器相同，低于常规的DEM译码器，最大程度上削弱了因大量开关次数带来的毛刺问题。The present disclosure provides a DEM structure that improves the dynamic performance of a DAC at extremely low temperatures, which can effectively alleviate technical problems in the prior art such as the deterioration of dynamic performance caused by increased transistor mismatch in digital-to-analog converters operating at extremely low temperatures. Faced with the poor dynamic performance of conventional digital-to-analog converters in extremely low temperature environments, this DEM decoding structure can randomly decode the input binary code and randomly disrupt the decoding order while ensuring that the output is correct. The random mismatch of the tube is compensated, which can improve the dynamic performance of the digital-to-analog converter under harsh process or environmental conditions; the DEM structure is simple, the area and power consumption are lower than that of the conventional DEM decoder, and it is more efficient in decoding. There will be no redundant switch switching times during the coding process, which reduces the glitches caused by high-speed switching during the working process. In addition, the output result is the same as the output result of the thermometer decoder, and there will be no extra signal that is always low level. link, which also brings convenience to the design of differential output digital-to-analog converters; the number of switching times is the same as that of a traditional thermometer decoder, which is lower than that of a conventional DEM decoder, minimizing the effect of a large number of switching times on Here comes the glitch problem.
附图说明Description of drawings
图1为本公开实施例的极低温下提升DAC动态性能的DEM结构示意图。Figure 1 is a schematic diagram of a DEM structure for improving the dynamic performance of a DAC at extremely low temperatures according to an embodiment of the present disclosure.
图2为本公开实施例中逻辑移位电路结构示意图。FIG. 2 is a schematic structural diagram of a logic shift circuit in an embodiment of the present disclosure.
图3为本公开实施例中伪随机数发生器电路结构示意图。FIG. 3 is a schematic diagram of the circuit structure of a pseudo-random number generator in an embodiment of the present disclosure.
图4为本公开实施例中随机移位电路结构示意图。Figure 4 is a schematic structural diagram of a random shift circuit in an embodiment of the present disclosure.
图5为本公开实施例的极低温下提升DAC动态性能的DEM结构译码结果示意图。Figure 5 is a schematic diagram of the DEM structure decoding results for improving the dynamic performance of the DAC at extremely low temperatures according to an embodiment of the present disclosure.
图6为基于传统温度计进行译码的SFDR分布示意图。Figure 6 is a schematic diagram of the SFDR distribution based on traditional thermometer decoding.
图7为基于本公开实施例的DEM结构进行译码的SFDR分布示意图。Figure 7 is a schematic diagram of SFDR distribution for decoding based on the DEM structure of an embodiment of the present disclosure.
具体实施方式Detailed ways
本公开提供了一种极低温下提升DAC动态性能的DEM二结构，在完成随机译码的同时可保持最小切换次数，能够提高极低温下DAC的动态性能。The present disclosure provides a DEM-II structure that improves the dynamic performance of a DAC at extremely low temperatures. It can maintain the minimum number of switching while completing random decoding, and can improve the dynamic performance of the DAC at extremely low temperatures.
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。In order to make the purpose, technical solutions and advantages of the present disclosure more clear, the present disclosure will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.
在本公开实施例中，提供一种极低温下提升DAC动态性能的DEM结构，如图1所示，所述DEM结构，包括：In an embodiment of the present disclosure, a DEM structure is provided that improves the dynamic performance of a DAC at extremely low temperatures. As shown in Figure 1, the DEM structure includes:
信号输入端，被配置用于接收三位二进制输入信号；The signal input terminal is configured to receive a three-digit binary input signal;
随机控制信号模块，与信号输入端相连，被配置用于根据三位二进制输入信号生成随机控制信号；以及a random control signal module connected to the signal input terminal and configured to generate a random control signal based on the three-digit binary input signal; and
随机移位电路，包括第一输入端和第二输入端，所述第一输入端与信号输入端相连，所述第二输入端与所述随机控制信号模块相连，所述随机移位电路被配置用于根据所述随机控制信号将所述三位二进制输入信号译码为七位温度计码。A random shift circuit includes a first input terminal and a second input terminal. The first input terminal is connected to the signal input terminal. The second input terminal is connected to the random control signal module. The random shift circuit is Configured for decoding the three-digit binary input signal into a seven-digit thermometer code according to the random control signal.
进一步地，所述随机控制信号模块，包括：Further, the random control signal module includes:
伪随机数发生器电路(PRNG)，被配置用于产生伪随机码；a pseudo-random number generator circuit (PRNG) configured to generate pseudo-random codes;
逻辑移位电路(LOGIC)，与信号输入端相连，被配置用于将三位二进制输入信号进行移位；A logic shift circuit (LOGIC), connected to the signal input terminal, is configured to shift the three-digit binary input signal;
三位加法器，同时与所述伪随机数发生器电路和所述逻辑移位电路相连，被配置用于将 伪随机码与所述移位后的三位二进制输入信号进行相加生成加法器输出信号；A three-digit adder, simultaneously connected to the pseudo-random number generator circuit and the logic shift circuit, is configured to add the pseudo-random code and the shifted three-digit binary input signal to generate an adder. output signal;
多路复用器(MUX)，被配置用于根据所述三位加法器的进位输出，输出全零或者全一的三位输出信号；以及A multiplexer (MUX) configured to output a three-digit output signal of all zeros or all ones according to the carry output of the three-digit adder; and
四位减法器，同时与所述多路复用器和所述三位加法器相连，被配置用于将所述加法器输出信号和所述三位输出信号进行逐位相减，生成随机控制信号。A four-bit subtractor, simultaneously connected to the multiplexer and the three-bit adder, is configured to subtract the adder output signal and the three-bit output signal bit by bit to generate a random control signal. .
在本公开实施例中，如图2所示，逻辑移位电路包括多个非门、或门、与门构成(具体包括三个非门、两个三输入与门、两个二输入与门、三个二输入或门)，接收三路输入信号(三位二进制输入信号B0、B1、B2)，生成四路输出信号(A0、A1、A2、SEL)，其中一路SEL输出信号为伪随机数发生器电路提供时钟，当且仅当三位二进制输入信号为全零或者全一时，SEL输出信号发生变化，伪随机数发生器产生新的随机码。In the embodiment of the present disclosure, as shown in Figure 2, the logic shift circuit includes multiple NOT gates, OR gates, and AND gates (specifically, it includes three NOT gates, two three-input AND gates, and two two-input AND gates. , three two-input OR gates), receive three input signals (three-digit binary input signals B0, B1, B2), and generate four output signals (A0, A1, A2, SEL), one of which is pseudo-random SEL output signal The number generator circuit provides a clock. If and only when the three-digit binary input signal is all zeros or all ones, the SEL output signal changes, and the pseudo-random number generator generates a new random code.
在本公开实施例中，如图3所示，伪随机数发生器电路包括多个D触发器、或门、或非门、异或门，具体为15个D触发器(Q 0-Q 14)、一个两输入或门、一个两输入异或门、一个十五输入或非门(NOR)，其中15个D触发器在时钟的控制下不断移位，多输入的或非门保证该电路能正常工作，避免出现全零的情况，异或门能够使得每个时钟周期下D触发器的输出移位后会有所变化，该伪随机数电路能够实现在(2 15-1)个周期内输出不重复，因此可利用该电路产生近似的随机数。 In the embodiment of the present disclosure, as shown in Figure 3, the pseudo-random number generator circuit includes multiple D flip-flops, OR gates, NOR gates, and XOR gates, specifically 15 D flip-flops (Q 0 -Q 14 ), a two-input OR gate, a two-input XOR gate, a fifteen-input NOR gate (NOR), in which 15 D flip-flops are continuously shifted under the control of the clock, and the multi-input NOR gate ensures that the circuit It can work normally and avoid the situation of all zeros. The XOR gate can make the output of the D flip-flop change after shifting in each clock cycle. The pseudo-random number circuit can be implemented in (2 15 -1) cycles. The internal output does not repeat, so this circuit can be used to generate approximate random numbers.
在本公开实施例中，三位加法器电路采用串行进位加法器结构，相比于超前进位加法器结构更加简单，主要由非门、多输入与门、多输入或门构成，内部包含三个一位全加器，利用多个时钟周期完成三位的加法运算，串行进位加法器虽然运行速度不如超前进位加法器，但是占用资源更少，能够实现基本的相加操作。In the embodiment of the present disclosure, the three-digit adder circuit adopts a serial carry adder structure, which is simpler than the carry-lookahead adder structure. It is mainly composed of a NOT gate, a multi-input AND gate, and a multi-input OR gate. It contains Three one-bit full adders use multiple clock cycles to complete a three-bit addition operation. Although the serial carry adder is not as fast as the carry-lookahead adder, it takes up less resources and can implement basic addition operations.
在本公开实施例中，多路复用器能够实现根据三位加法器的进位输出，来输出全零或者全一的三位输出信号，进一步与三位加法器的输出相减，得出控制随机移位电路的随机控制信号。三位多路复用器具体包括三个一位复用器，由与门、非门、或门等门电路构成，三位输出信号根据三位加法器的进位信号决定，若三位加法器产生进位信号，则三位多路复用器输出三路高电平信号(全一信号)，否则输出三路低电平信号(全零信号)。In the embodiment of the present disclosure, the multiplexer can output a three-digit output signal of all zeros or all ones according to the carry output of the three-digit adder, and further subtract it from the output of the three-digit adder to obtain the control Random control signal for the random shift circuit. The three-bit multiplexer specifically includes three one-bit multiplexers, which are composed of AND gates, NOT gates, OR gates and other gate circuits. The three-bit output signal is determined by the carry signal of the three-bit adder. If the three-bit adder When a carry signal is generated, the three-bit multiplexer outputs three high-level signals (all one signals), otherwise it outputs three low-level signals (all zero signals).
在本公开实施例中，四位减法器用来实现将三位加法器的输出信号与三位多路复用器的三位输出信号进行相减的操作，与三位加法器类似，减法器采用的是逐位相减结构，内部由四个一位减法器构成，单个的一位减法器包括与门、或门以及异或门，四位减法器的输出将经过非门连接到随机移位电路的移位控制信号端，使得当输入的三位二进制码为全零或全一时，输出的七位温度计码产生移位，这样能够使得在开关不断切换的过程中，上一次打开/关闭的开关在下一个时钟到来的时候依旧优先打开/关闭，可以实现最小化因大量开关切换次数 带来的毛刺现象。In the embodiment of the present disclosure, the four-bit subtractor is used to subtract the output signal of the three-bit adder and the three-bit output signal of the three-bit multiplexer. Similar to the three-bit adder, the subtractor adopts It is a bit-by-bit subtraction structure, which is composed of four one-bit subtractors internally. A single one-bit subtractor includes an AND gate, an OR gate and an XOR gate. The output of the four-bit subtractor will be connected to the random shift circuit through a NOT gate. The shift control signal terminal is such that when the input three-digit binary code is all zeros or all ones, the output seven-digit thermometer code is shifted, so that in the process of continuous switching of the switch, the last opened/closed switch When the next clock arrives, priority is still given to opening/closing, which can minimize glitches caused by a large number of switch switching times.
在本公开实施例中，如图4所示，随机移位电路包括多个多路复用器(MUX)构成，其输入为三位二进制码(B0、B1、B2)，输出为七位的温度计码(W1-W7)，其功能是实现二进制码到温度计码的译码，与传统二进制码转温度计码的译码电路不同的是，此随机移位电路中的随机控制信号(PRBS0、PRBS1、PRBS2)是由三位二进制输入信号确定的。随机移位电路的整体布局分为三行七列，包括三行七列多路复用器单元，每行多路复用器单元包括7个多路复用器，每列多路复用器单元包括3个多路复用器，共计二十一个多路复用器组成，每一行的多路复用器单元的输出控制信号由减法器的输出控制(即由四位减法器输出的随机控制信号PRBS0、PRBS1、PRBS2控制)。三路三位二进制输入信号分别连接至第一行的多路复用器，其按照二进制的权重比例进行分配连接，进而连接每一列多路复用器单元，如图4所示，三位二进制输入信号中分别连出二、四、八条连接线至第一行多路复用器单元，具体连接方式图图4所示为，B0分别连接两条线至第一行多路复用器单元中的第4和第7个多路复用器，B1分别连接四条线至第一行多路复用器单元中的第2、3、5、6个多路复用器，B2分别连接八条线至第一行多路复用器单元中的第1-7个多路复用器。In the embodiment of the present disclosure, as shown in Figure 4, the random shift circuit includes multiple multiplexers (MUX), the input of which is a three-bit binary code (B0, B1, B2), and the output is a seven-bit binary code. Thermometer code (W1-W7), its function is to realize the decoding from binary code to thermometer code. Different from the traditional decoding circuit from binary code to thermometer code, the random control signal (PRBS0, PRBS1) in this random shift circuit , PRBS2) is determined by a three-digit binary input signal. The overall layout of the random shift circuit is divided into three rows and seven columns, including three rows and seven columns of multiplexer units. Each row of multiplexer units includes 7 multiplexers, and each column of multiplexers The unit includes 3 multiplexers, consisting of a total of twenty-one multiplexers. The output control signal of the multiplexer unit in each row is controlled by the output of the subtractor (that is, the output of the four-bit subtractor. Random control signals PRBS0, PRBS1, PRBS2 control). The three three-digit binary input signals are respectively connected to the multiplexers in the first row, which are distributed and connected according to the binary weight ratio, and then connected to the multiplexer units in each column. As shown in Figure 4, the three-digit binary Two, four, and eight connection lines are respectively connected to the first row of multiplexer units from the input signal. The specific connection method is shown in Figure 4. B0 connects two lines to the first row of multiplexer units. The 4th and 7th multiplexers in the multiplexer unit, B1 connects four lines to the 2nd, 3rd, 5th, and 6th multiplexers in the first row of multiplexer units, and B2 connects eight lines respectively. Lines go to multiplexers 1-7 in the first row of multiplexer cells.
在本公开实施例中，如图5所示为该DEM译码器在-269℃条件下的译码结果，其中最左侧栏中的latch：5，latch：6，latch：7为输入的三位二进制码，5、7、4、6、1、3、2为输出的七位温度计码，右侧为连续变化的二进制输入码对应的译码结果，可以看出随着latch的不断变化，七位输出温度计码始终保持上一个时钟周期开启/关闭的通道优先开启/关闭，可以看出相邻的时钟周期内，输入三位二进制码不断发生切换，输出仍可保持相邻周期开关切换次数最小，这样能够最小化高频情况下开关切换频繁对DAC动态性能带来的干扰。In the embodiment of the present disclosure, as shown in Figure 5, the decoding result of the DEM decoder under the condition of -269°C, where latch: 5, latch: 6, and latch: 7 in the leftmost column are input Three-digit binary codes, 5, 7, 4, 6, 1, 3, 2 are the output seven-digit thermometer codes. The right side is the decoding result corresponding to the continuously changing binary input code. It can be seen that with the continuous change of latch , the seven-digit output thermometer code always keeps the channel that was turned on/off in the previous clock cycle preferentially turned on/off. It can be seen that in adjacent clock cycles, the input three-digit binary code continues to switch, and the output can still maintain switching in adjacent cycles. The number of times is the smallest, which can minimize the interference to the dynamic performance of the DAC caused by frequent switching at high frequencies.
在本公开实施例中，结合图6和图7所示，可以看出在电流源失配为10％的情况下，传统温度计译码的SFDR分布中最差约为44.15dB，而应用了本公告开的DEM结构译码器后，在电流源失配很大的情况下，SFDR分布更加集中，最差情况约53.65dB，对比两种译码器的结果，采用新型DEM译码器的DAC在极端情况下，SFDR指标相对于传统温度计译码的DAC有较大提升。In the embodiment of the present disclosure, as shown in Figure 6 and Figure 7, it can be seen that when the current source mismatch is 10%, the worst SFDR distribution decoded by a traditional thermometer is about 44.15dB, and this application After the announcement of the DEM structure decoder, when the current source mismatch is large, the SFDR distribution is more concentrated, with the worst case being about 53.65dB. Comparing the results of the two decoders, the DAC using the new DEM decoder In extreme cases, the SFDR index is greatly improved compared to the traditional thermometer decoding DAC.
至此，已经结合附图对本公开实施例进行了详细描述。需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进行详细说明。此外，上述对各元件和方法的定义并不仅限于实施例中提到的各种具体结构、形状或方式，本领域普通技术人员可对其进行简单地更改或替换。So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that implementation methods not shown or described in the drawings or the text of the specification are all forms known to those of ordinary skill in the technical field and have not been described in detail. In addition, the above definitions of each element and method are not limited to the various specific structures, shapes or methods mentioned in the embodiments, which can be simply modified or replaced by those of ordinary skill in the art.
依据以上描述，本领域技术人员应当对本公开极低温下提升DAC动态性能的DEM结构有了清楚的认识。Based on the above description, those skilled in the art should have a clear understanding of the DEM structure of the present disclosure for improving the dynamic performance of the DAC at extremely low temperatures.
综上所述，本公开提供了一种极低温下提升DAC动态性能的DEM结构，面向极低温环境下常规数模转换器动态性能较差的情况，该DEM译码技术能够对输入的二进码进行随机译码，在保证输出正确的情况下随机打乱译码次序，对MOS管的随机失配进行了补偿，可在工艺或环境较为恶劣的情况下提升数模转换器的动态性能。与传统的DEM译码器相比，该DEM译码器结构上十分简单，所占面积与功耗均低于常规DEM译码器，而且在译码过程中不会产生多余的开关切换次数，降低了工作过程中因高速切换开关导致的毛刺现象，此外输出结果与温度计译码器输出结果相同，不会多产生一路恒为低电平的信号链路，这也为差分输出的数模转换器的设计工作带来便利。In summary, the present disclosure provides a DEM structure that improves the dynamic performance of DACs at extremely low temperatures. Facing the situation where the dynamic performance of conventional digital-to-analog converters is poor in extremely low temperature environments, this DEM decoding technology can decode the input binary The code is randomly decoded, and the decoding order is randomly disrupted while ensuring the correct output, and the random mismatch of the MOS tube is compensated, which can improve the dynamic performance of the digital-to-analog converter under harsh processes or environments. Compared with traditional DEM decoders, this DEM decoder is very simple in structure, occupies less area and consumes less power than conventional DEM decoders, and does not produce redundant switching times during the decoding process. The glitch phenomenon caused by high-speed switching during operation is reduced. In addition, the output result is the same as the output result of the thermometer decoder, and there is no extra signal link that is always low level. This is also the digital-to-analog conversion of differential output. It brings convenience to the design work of the device.
以上所述本公开的具体实施方式，并不构成对本公开保护范围的限定。任何根据本公开的技术构思所作出的各种其他相应的改变与变形，均应包含在本公开权利要求的保护范围内。The above-mentioned specific embodiments of the present disclosure do not constitute a limitation on the scope of the present disclosure. Any other corresponding changes and deformations made based on the technical concept of the present disclosure shall be included in the protection scope of the claims of the present disclosure.

Claims (10)

  1. 一种极低温下提升DAC动态性能的DEM结构，包括：A DEM structure that improves the dynamic performance of DAC at extremely low temperatures, including:
    信号输入端，被配置用于接收三位二进制输入信号；The signal input terminal is configured to receive a three-digit binary input signal;
    随机控制信号模块，与信号输入端相连，被配置用于根据三位二进制输入信号生成随机控制信号；以及a random control signal module connected to the signal input terminal and configured to generate a random control signal based on the three-digit binary input signal; and
    随机移位电路，包括第一输入端和第二输入端，所述第一输入端与信号输入端相连，所述第二输入端与所述随机控制信号模块相连，所述随机移位电路被配置用于根据所述随机控制信号将所述三位二进制输入信号译码为七位温度计码。A random shift circuit includes a first input terminal and a second input terminal. The first input terminal is connected to the signal input terminal. The second input terminal is connected to the random control signal module. The random shift circuit is Configured for decoding the three-digit binary input signal into a seven-digit thermometer code according to the random control signal.
  2. 根据权利要求1所述的DEM结构，所述随机控制信号模块，包括：According to the DEM structure of claim 1, the random control signal module includes:
    伪随机数发生器电路，被配置被配置用于产生伪随机码；a pseudo-random number generator circuit configured to generate pseudo-random codes;
    逻辑移位电路，与信号输入端相连，被配置用于将三位二进制输入信号进行移位；a logic shift circuit connected to the signal input terminal and configured to shift the three-digit binary input signal;
    三位加法器，同时与所述伪随机数发生器电路和所述逻辑移位电路相连，被配置用于将伪随机码与所述移位后的三位二进制输入信号进行相加生成加法器输出信号；A three-digit adder, simultaneously connected to the pseudo-random number generator circuit and the logic shift circuit, is configured to add the pseudo-random code and the shifted three-digit binary input signal to generate an adder. output signal;
    多路复用器，被配置用于根据所述三位加法器的进位输出，输出全零或者全一的三位输出信号；以及A multiplexer configured to output a three-digit output signal of all zeros or all ones according to the carry output of the three-digit adder; and
    四位减法器，同时与所述多路复用器和所述三位加法器相连，被配置用于将所述加法器输出信号和所述三位输出信号进行逐位相减，生成随机控制信号。A four-bit subtractor, simultaneously connected to the multiplexer and the three-bit adder, is configured to subtract the adder output signal and the three-bit output signal bit by bit to generate a random control signal. .
  3. 根据权利要求2所述的DEM结构，所述逻辑移位电路包括三路输入信号，四路输出信号；其中一路SEL输出信号为伪随机数发生器电路提供时钟。According to the DEM structure of claim 2, the logic shift circuit includes three input signals and four output signals; one of the SEL output signals provides a clock for the pseudo-random number generator circuit.
  4. 根据权利要求3所述的DEM结构，所述逻辑移位电路被构造成当且仅当三位二进制输入信号为全零或者全1时，SEL输出信号发生变化，伪随机数发生器产生新的随机码。According to the DEM structure of claim 3, the logic shift circuit is configured so that when and only when the three-digit binary input signal is all zeros or all ones, the SEL output signal changes, and the pseudo-random number generator generates a new random code.
  5. 根据权利要求2所述的DEM结构，所述伪随机数发生器电路包括多个D触发器、或门、或非门、异或门；According to the DEM structure of claim 2, the pseudo-random number generator circuit includes a plurality of D flip-flops, OR gates, NOR gates, and XOR gates;
    其中D触发器为15个，15个D触发器在时钟的控制下不断移位，多输入的或非门保证伪随机数发生器电路能正常工作且避免出现全零的情况，异或门被构造成能够使得每个时钟周期下D触发器的输出移位后会有所变化。Among them, there are 15 D flip-flops, and the 15 D flip-flops are continuously shifted under the control of the clock. The multi-input NOR gate ensures that the pseudo-random number generator circuit can work normally and avoids all zeros. The XOR gate is It is constructed so that the output of the D flip-flop changes every clock cycle.
  6. 根据权利要求5所述的DEM结构，该伪随机数电路能够实现在(2 15-1)个周期内输出不重复。 According to the DEM structure of claim 5, the pseudo-random number circuit can realize that the output does not repeat within (2 15 -1) cycles.
  7. 根据权利要求2所述的DEM结构，所述三位加法器电路采用串行进位加法器结构，包括三个一位全加器，利用多个时钟周期完成三位的加法运算。According to the DEM structure of claim 2, the three-bit adder circuit adopts a serial carry adder structure, including three one-bit full adders, and uses multiple clock cycles to complete the three-bit addition operation.
  8. 根据权利要求2所述的DEM结构，所述四位减法器采用的是逐位相减结构，包括四个一位减法器，所述四位减法器输出的随机控制信号将经过非门连接到随机移位电路的移位控制信号端，使得当三位二进制输入信号为全零或全一时，输出的七位温度计码产生移位。According to the DEM structure of claim 2, the four-bit subtractor adopts a bit-by-bit subtraction structure and includes four one-bit subtractors. The random control signal output by the four-bit subtractor will be connected to the random control signal through a NOT gate. The shift control signal terminal of the shift circuit makes the output seven-bit thermometer code shift when the three-digit binary input signal is all zeros or all ones.
  9. 根据权利要求2所述的DEM结构，所述多路复用器包括三个一位复用器，三位输出信号根据三位加法器的进位信号决定，若三位加法器产生进位信号，则多路复用器输出三路高电平信号，否则输出三路低电平信号。According to the DEM structure of claim 2, the multiplexer includes three one-bit multiplexers, and the three-bit output signal is determined according to the carry signal of the three-bit adder. If the three-bit adder generates a carry signal, then The multiplexer outputs three high-level signals, otherwise it outputs three low-level signals.
  10. 根据权利要求1所述的DEM结构，所述随机移位电路包括三行七列多路复用器单元，每一行的多路复用器单元输出控制信号由四位减法器输出的随机控制信号控制，三位二进制输入信号按照二进制的权重比例分别连接至七列多路复用器单元。The DEM structure according to claim 1, the random shift circuit includes three rows and seven columns of multiplexer units, and the multiplexer unit of each row outputs a control signal which is a random control signal output by a four-bit subtractor. For control, the three-digit binary input signals are connected to the seven-column multiplexer units respectively according to the binary weight ratio.
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