CN115133928A - DEM structure for improving dynamic performance of DAC at extremely low temperature - Google Patents
DEM structure for improving dynamic performance of DAC at extremely low temperature Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
- H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
- H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
- H03M1/0665—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching using data dependent selection of the elements, e.g. data weighted averaging
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
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Abstract
The utility model provides a promote DEM structure of DAC dynamic behavior under extremely low temperature, include: a signal input for receiving a three-bit binary input signal; the random control signal module is connected with the signal input end and used for generating a random control signal according to the three-bit binary input signal; and the random shift circuit comprises a first input end and a second input end, the first input end is connected with a signal input end, the second input end is connected with the random control signal module, and the random shift circuit is used for decoding the three-bit binary input signal into a seven-bit thermometer code according to the random control signal. The DEM structure can relieve the technical problems of dynamic performance deterioration and the like caused by transistor mismatching aggravation when a digital-to-analog converter works at an extremely low temperature in the prior art.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a Dynamic Element Matching (DEM) structure for improving dynamic performance of a digital-to-analog converter at very low temperature (-269 ℃ and below).
Background
A DAC (Digital to analog converter) can convert discrete Digital signals into continuous analog signals, and with the continuous development of deep space detection, quantum computation and other technologies, the DAC with high speed and high precision needs to work normally at extremely low temperature, and the current steering DAC can meet the requirements of high speed and high precision due to the structural characteristics of the DAC, but because the mismatch caused by the process at extremely low temperature is intensified, the performance of the DAC is greatly affected, because the threshold voltage of the MOS transistor at extremely low temperature becomes higher, carriers are frozen, and the mismatch of the transistor in the same area is larger, these problems make it very difficult for the low-temperature DAC to achieve the same performance as that of the normal-temperature DAC, and a new structure must be provided to solve the mismatch problem of the MOS transistor at low temperature.
The DEM technology can be used for improving the dynamic performance of the DAC under the condition of high mismatch, but the traditional DEM has the problems of complex structure, weak randomness, multiple switching times, high power consumption and the like, so that the DEM structure capable of effectively improving the dynamic performance of the DAC at extremely low temperature and weakening burrs generated due to on-off of a switch is urgently needed.
Disclosure of Invention
Technical problem to be solved
Based on the above problem, the present disclosure provides a DEM structure for improving dynamic performance of a DAC at an extremely low temperature, so as to alleviate technical problems such as dynamic performance deterioration caused by transistor mismatch aggravation when a digital-to-analog converter works at the extremely low temperature in the prior art.
(II) technical scheme
The utility model provides a promote DEM structure of DAC dynamic behavior under extremely low temperature, include: the circuit comprises a signal input end, a random control signal module and a random shift circuit.
The signal input end is used for receiving a three-bit binary input signal; the random control signal module is connected with the signal input end and used for generating a random control signal according to the three-bit binary input signal;
the random shift circuit comprises a first input end and a second input end, the first input end is connected with a signal input end, the second input end is connected with the random control signal module, and the random shift circuit is used for decoding the three-bit binary input signal into a seven-bit thermometer code according to the random control signal.
According to an embodiment of the present disclosure, the random control signal module includes: the circuit comprises a pseudo-random number generator circuit, a logic shift circuit, a three-bit adder, a multiplexer and a four-bit subtracter.
The pseudo-random number generator circuit is used for generating pseudo-random codes; the logic shift circuit is connected with the signal input end and is used for shifting the three-bit binary input signal; the three-bit adder is simultaneously connected with the pseudo-random number generator circuit and the logic shift circuit and is used for adding a pseudo-random code and the shifted three-bit binary input signal to generate an adder output signal; the multiplexer is used for outputting a three-bit output signal of all zeros or all ones according to the carry output of the three-bit adder; and the four-bit subtracter is simultaneously connected with the multiplexer and the three-bit adder and is used for carrying out bit-by-bit subtraction on the output signal of the adder and the output signal of the three-bit adder to generate a random control signal.
According to the embodiment of the disclosure, the logic shift circuit comprises three input signals and four output signals; one of the SEL output signals clocks a pseudo-random number generator circuit.
According to an embodiment of the disclosure, the logic shift circuit is configured such that if and only if the three-bit binary input signal is all zeros or all 1's, the SEL output signal changes and the pseudo-random number generator generates a new random code.
According to an embodiment of the present disclosure, the pseudo-random number generator circuit includes a plurality of D flip-flops, or gates, nor gates, and xor gates;
the number of the D triggers is 15, the 15D triggers continuously shift under the control of a clock, the multi-input NOR gate ensures that the pseudo-random number generator circuit can normally work and avoids the condition of all zeros, and the XOR gate is constructed to enable the output of the D triggers to be changed after shifting in each clock cycle.
According to the disclosed embodiment, the pseudo-random number circuit can be realized in (2) 15 -1) the output does not repeat within one cycle.
According to the embodiment of the disclosure, the three-bit adder circuit adopts a serial carry adder structure, comprises three one-bit full adders and completes the addition operation of three bits by using a plurality of clock cycles.
According to the embodiment of the disclosure, the four-bit subtracter adopts a bit-by-bit subtraction structure, and comprises four one-bit subtracters, and the random control signal output by the four-bit subtracter is connected to the shift control signal end of the random shift circuit through the not gate, so that when the three-bit binary input signal is all zero or all one, the output seven-bit thermometer code is shifted.
According to the embodiment of the disclosure, the multiplexer includes three one-bit multiplexers, the three-bit output signals are determined according to the carry signals of the three-bit adder, if the three-bit adder generates the carry signals, the multiplexer outputs three paths of high level signals, otherwise, three paths of low level signals are output.
According to the embodiment of the disclosure, the random shift circuit comprises three rows and seven columns of multiplexer units, the output control signal of the multiplexer unit of each row is controlled by the random control signal output by the four-bit subtracter, and the three-bit binary input signals are respectively connected to the seven columns of multiplexer units according to the binary weight proportion.
(III) advantageous effects
According to the technical scheme, the DEM structure for improving the dynamic performance of the DAC at the extremely low temperature has at least one or one part of the following beneficial effects:
(1) the DEM decoding structure can randomly decode input binary codes, randomly disorder decoding sequence under the condition of ensuring correct output, compensate random mismatch of MOS (metal oxide semiconductor) tubes and improve the dynamic performance of the digital-to-analog converter under the condition of severe process or environment;
(2) the structure is simple, the occupied area and the power consumption are lower than those of a conventional DEM decoder, redundant switch switching times cannot be generated in the decoding process, the burr phenomenon caused by high-speed switch switching in the working process is reduced, in addition, the output result is the same as that of a thermometer decoder, one more signal link which is constant in low level cannot be generated, and the convenience is brought to the design work of a differential output digital-to-analog converter;
(3) the switching times are the same as those of a traditional thermometer decoder and lower than that of a conventional DEM decoder, and the problem of burrs caused by a large number of switching times is weakened to the greatest extent.
Drawings
Fig. 1 is a schematic structural diagram of a DEM for improving dynamic performance of a DAC at an extremely low temperature according to an embodiment of the present disclosure.
Fig. 2 is a schematic diagram of a logic shift circuit according to an embodiment of the disclosure.
FIG. 3 is a schematic diagram of a pseudo-random number generator circuit according to an embodiment of the disclosure.
Fig. 4 is a schematic diagram of a random shift circuit according to an embodiment of the disclosure.
Fig. 5 is a schematic diagram of a decoding result of the DEM structure for improving dynamic performance of the DAC at an extremely low temperature according to the embodiment of the present disclosure.
FIG. 6 is a diagram of SFDR distribution for decoding based on a conventional thermometer.
Fig. 7 is a schematic SFDR distribution diagram for decoding based on the DEM structure of the embodiment of the present disclosure.
Detailed Description
The utility model provides a dynamic performance of DAC DEM structure is promoted at extremely low temperature, can keep minimum switching number of times when accomplishing random decoding, can improve the dynamic performance of DAC at extremely low temperature.
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
In an embodiment of the present disclosure, a DEM structure for improving dynamic performance of a DAC at an extremely low temperature is provided, as shown in fig. 1, the DEM structure includes:
a signal input for receiving a three-bit binary input signal;
the random control signal module is connected with the signal input end and used for generating a random control signal according to the three-bit binary input signal; and
and the random shift circuit comprises a first input end and a second input end, the first input end is connected with a signal input end, the second input end is connected with the random control signal module, and the random shift circuit is used for decoding the three-bit binary input signal into a seven-bit thermometer code according to the random control signal.
Further, the random control signal module includes:
a pseudo-random number generator circuit (PRNG) for generating a pseudo-random code;
a LOGIC shift circuit (LOGIC) connected to the signal input terminal for shifting the three-bit binary input signal;
a three-bit adder, connected to the pseudo-random number generator circuit and the logic shift circuit, for adding the pseudo-random code and the shifted three-bit binary input signal to generate an adder output signal;
a Multiplexer (MUX) for outputting a three-bit output signal of all zeros or all ones according to a carry output of the three-bit adder; and
and the four-bit subtracter is simultaneously connected with the multiplexer and the three-bit adder and is used for carrying out bit-by-bit subtraction on the output signal of the adder and the output signal of the three-bit adder to generate a random control signal.
In the embodiment of the disclosure, as shown in fig. 2, the logic shift circuit includes a plurality of not gates, or gates, and gates (specifically, three not gates, two three-input and gates, two-input and gates, and three two-input or gates), receives three input signals (three-bit binary input signals B0, B1, and B2), and generates four output signals (a0, a1, a2, SEL), wherein one SEL output signal clocks the pseudo random number generator circuit, and when and only when the three-bit binary input signal is all zeros or all ones, the SEL output signal changes, and the pseudo random number generator generates a new random code.
In the disclosed embodiment, as shown in fig. 3, the pseudo random number generator circuit includes a plurality of D flip-flops, or gates, nor gates, and xor gates, and specifically, 15D flip-flops (Q) 0 -Q 14 ) A two-input OR gate, a two-input XOR gate,A fifteen-input NOR gate (NOR), wherein 15D flip-flops are shifted continuously under the control of a clock, the multi-input NOR gate ensures that the circuit can work normally and avoids the condition of all zeros, the XOR gate can enable the output of the D flip-flops to be changed after the shift at each clock cycle, and the pseudo-random number circuit can be realized at (2) 15 -1) the output does not repeat within one cycle, so that an approximate random number can be generated using this circuit.
In the embodiment of the disclosure, the three-bit adder circuit adopts a serial carry adder structure, which is simpler than a carry look-ahead adder structure, and mainly comprises a not gate, a multi-input and gate, and a multi-input or gate, and the inside of the three-bit adder circuit includes three one-bit full adders, and three-bit addition operation is completed by using a plurality of clock cycles, although the running speed of the serial carry adder is lower than that of the carry look-ahead adder circuit, the serial carry adder circuit occupies less resources, and can realize basic addition operation.
In the embodiment of the disclosure, the multiplexer can output all-zero or all-one three-bit output signals according to the carry output of the three-bit adder, and further subtract the output of the three-bit adder to obtain the random control signal for controlling the random shift circuit. The three-bit multiplexer specifically comprises three one-bit multiplexers, each one-bit multiplexer is composed of gate circuits such as an AND gate, a NOT gate and an OR gate, the three-bit output signals are determined according to carry signals of the three-bit adder, if the three-bit adder generates the carry signals, the three-bit multiplexer outputs three paths of high level signals (all one signals), and otherwise, three paths of low level signals (all zero signals) are output.
In the embodiment of the disclosure, a four-bit subtracter is used to implement the operation of subtracting the output signal of the three-bit adder from the three-bit output signal of the three-bit multiplexer, and similar to the three-bit adder, the subtracter adopts a bit-by-bit subtraction structure, and the inside of the subtracter is composed of four one-bit subtracters, a single one-bit subtracter includes an and gate, an or gate and an xor gate, and the output of the four-bit subtracter is connected to the shift control signal terminal of the random shift circuit through a not gate, so that when the input three-bit binary code is all zero or all one, the output seven-bit thermometer code generates shift, which can enable the switch that was turned on/off last time to be turned on/off preferentially when the next clock comes during the process of switching the switch continuously, and can minimize the glitch phenomenon caused by a large number of switching times of the switch.
In the embodiment of the present disclosure, as shown in fig. 4, the random shift circuit includes a plurality of Multiplexers (MUXs), the input of which is three-bit binary code (B0, B1, B2), the output of which is seven-bit thermometer code (W1-W7), the function of which is to decode binary code to thermometer code, unlike the conventional circuit for decoding binary code to thermometer code, the random control signals (PRBS0, PRBS1, PRBS2) in the random shift circuit are determined by three-bit binary input signals. The overall layout of the random shift circuit is divided into three rows and seven columns, and comprises three rows and seven columns of multiplexer units, each row of multiplexer units comprises 7 multiplexers, each column of multiplexer units comprises 3 multiplexers, and the total number of the multiplexers is twenty-one, and the output control signals of the multiplexer units in each row are controlled by the output of the subtracter (namely controlled by random control signals PRBS0, PRBS1 and PRBS2 output by the four-bit subtracter). As shown in fig. 4, two, four, and eight connection lines are respectively connected to the three-bit binary input signals and further connected to the multiplexer units in each row, and as shown in fig. 4, B0 respectively connects two lines to the 4 th and 7 th multiplexers in the first row of multiplexer units, B1 respectively connects four lines to the 2 nd, 3 rd, 5 th, and 6 th multiplexers in the first row of multiplexer units, and B2 respectively connects eight lines to the 1 st to 7 th multiplexers in the first row of multiplexer units.
In the disclosed embodiment, FIG. 5 shows the decoding result of the DEM decoder at-269 ℃, where the latch in the leftmost column: 5, latch: 6, latch: 7 is the input three-bit binary code, 5, 7, 4, 6, 1, 3 and 2 are the seven-bit thermometer code output, and the right side is the decoding result corresponding to the binary input code which changes continuously, so that the seven-bit output thermometer code always keeps the channel which is turned on/off in the previous clock cycle to be turned on/off preferentially along with the continuous change of latch, and the input three-bit binary code is switched continuously in the adjacent clock cycles, and the output can still keep the switching frequency of the switch in the adjacent cycles to be minimum, thereby minimizing the interference of the switch switching frequency on the DAC dynamic performance under the high-frequency condition.
In the embodiment of the present disclosure, as shown in fig. 6 and 7, it can be seen that, under the condition that the mismatch of the current source is 10%, the worst SFDR distribution of the conventional thermometer decoding is about 44.15dB, and after the DEM structure decoder disclosed in this disclosure is applied, under the condition that the mismatch of the current source is large, the SFDR distribution is more concentrated, and the worst case is about 53.65dB, compared with the results of the two decoders, the SFDR index of the DAC adopting the novel DEM decoder is greatly improved in an extreme case compared with that of the DAC of the conventional thermometer decoding.
So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. Further, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by those of ordinary skill in the art.
From the above description, those skilled in the art should have clear understanding of the DEM structure for improving the dynamic performance of the DAC at very low temperature according to the present disclosure.
In summary, the present disclosure provides a DEM structure for improving dynamic performance of a DAC at an extremely low temperature, which is oriented to the situation that a conventional DAC has poor dynamic performance in an extremely low temperature environment, and the DEM decoding technology can randomly decode input binary codes, randomly disorder decoding order under the situation that correct output is ensured, compensate for random mismatch of MOS transistors, and improve dynamic performance of the DAC under the situation that a process or an environment is severe. Compared with the traditional DEM decoder, the DEM decoder is quite simple in structure, occupied area and power consumption are lower than those of a conventional DEM decoder, redundant switch switching times cannot be generated in the decoding process, the burr phenomenon caused by high-speed switch in the working process is reduced, in addition, the output result is the same as the output result of the thermometer decoder, one path of signal link which is constant at a low level cannot be generated, and convenience is brought to the design work of a digital-to-analog converter for differential output.
It should be noted that, unless otherwise specified herein, the inclusion of "a" or "an" element is not limited to inclusion of a single such element, but may include one or more such elements.
In addition, unless otherwise specified, the terms "first," "second," and the like, herein, are used merely to distinguish one element from another having the same name, and do not denote any order, hierarchy, order of execution, or order of manufacture. A "first" element and a "second" element may be present together in the same component or separately in different components. The presence of an element having a higher ordinal number does not necessarily indicate the presence of another element having a lower ordinal number.
In this context, the so-called characteristic formazan "or" (iii) unless otherwise indicated o r) or "and/or" (and/or) characteristic b, means that a is present alone, b is present alone, or a and b are present together; by the features A and (and) or "and" feature B, it is meant that A and B are present simultaneously; the terms "comprising," "including," "having," "containing," and "containing" are intended to be inclusive and not limiting.
Moreover, the terms "upper," "lower," "left," "right," "front," "rear," or "between," and the like, as used herein, are used merely to describe relative positions of various elements and are to be construed to include translational, rotational, or mirror-image situations. Further, in this document, unless specifically stated otherwise, "an element on" or the like does not necessarily mean that the element contacts another element.
In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (10)
1. A DEM structure for improving dynamic performance of a DAC at extremely low temperature comprises:
a signal input for receiving a three-bit binary input signal;
the random control signal module is connected with the signal input end and used for generating a random control signal according to the three-bit binary input signal; and
and the random shift circuit comprises a first input end and a second input end, the first input end is connected with a signal input end, the second input end is connected with the random control signal module, and the random shift circuit is used for decoding the three-bit binary input signal into a seven-bit thermometer code according to the random control signal.
2. DEM architecture as in claim 1, said random control signal module comprising:
a pseudo-random number generator circuit for generating a pseudo-random code;
the logic shift circuit is connected with the signal input end and is used for shifting the three-bit binary input signal;
a three-bit adder, connected to both the pseudo-random number generator circuit and the logic shift circuit, for adding the pseudo-random code to the shifted three-bit binary input signal to generate an adder output signal;
the multiplexer is used for outputting a three-bit output signal of all zeros or all ones according to the carry output of the three-bit adder; and
and the four-bit subtracter is simultaneously connected with the multiplexer and the three-bit adder and is used for carrying out bit-by-bit subtraction on the output signal of the adder and the output signal of the three-bit adder to generate a random control signal.
3. DEM architecture as in claim 2, said logic shifting circuitry comprising a three-way input signal, a four-way output signal; one of the SEL output signals clocks a pseudo-random number generator circuit.
4. DEM structure according to claim 3, said logic shift circuit being configured such that if and only if the three-bit binary input signal is all zeros or all 1, the SEL output signal changes and the pseudo-random number generator generates a new random code.
5. DEM architecture as in claim 2, said pseudo-random number generator circuit comprising a plurality of D flip-flops, or gates, nor gates, exclusive or gates;
the number of the D triggers is 15, the 15D triggers continuously shift under the control of a clock, the multi-input NOR gate ensures that the pseudo-random number generator circuit can normally work and avoids the condition of all zeros, and the XOR gate is constructed to enable the output of the D triggers to be changed after shifting in each clock cycle.
6. DEM structure according to claim 5, the pseudo random number circuit being able to be implemented at (2) 15 -1) the output does not repeat within one cycle.
7. DEM architecture as in claim 2, said three-bit adder circuit employing a serial carry adder architecture comprising three one-bit full adders for performing three-bit addition operations using multiple clock cycles.
8. DEM structure according to claim 2, wherein said four-bit subtracter is a bit-by-bit subtraction structure, and comprises four one-bit subtracters, and the random control signal output by said four-bit subtracter is connected to the shift control signal terminal of the random shift circuit via the not gate, so that when the three-bit binary input signal is all zero or all one, the output seven-bit thermometer code is shifted.
9. DEM architecture as in claim 2, said multiplexer comprising three one-bit multiplexers, the three-bit output signals being determined in accordance with the carry signal of the three-bit adder, the multiplexer outputting three high level signals if the three-bit adder produces the carry signal, and outputting three low level signals otherwise.
10. DEM structure according to claim 1, said random shift circuit comprising three rows and seven columns of multiplexer units, the multiplexer units output control signals of each row being controlled by the random control signal output by the four-bit subtractor, the three-bit binary input signals being respectively connected to the seven columns of multiplexer units according to a binary weight ratio.
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| CN202210776955.0A CN115133928A (en) | 2022-06-30 | 2022-06-30 | DEM structure for improving dynamic performance of DAC at extremely low temperature |
| PCT/CN2022/116152 WO2024000791A1 (en) | 2022-06-30 | 2022-08-31 | Dem structure for improving dynamic performance of dac at extremely low temperature |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024000791A1 (en) * | 2022-06-30 | 2024-01-04 | 中国科学技术大学 | Dem structure for improving dynamic performance of dac at extremely low temperature |
| CN118041360A (en) * | 2024-04-15 | 2024-05-14 | 南京朗立微集成电路有限公司 | Method and equipment for reducing high-precision DAC output interference pulse |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104113343B (en) * | 2014-02-28 | 2017-09-29 | 西安电子科技大学 | One kind packet pseudorandom rotating thermometer decoding circuit |
| CN104852733B (en) * | 2015-05-15 | 2018-04-20 | 清华大学 | Dynamic element matching encoder |
| CN109672446B (en) * | 2019-01-18 | 2021-08-06 | 西安电子科技大学 | Sectional pseudo data weighted average DEM circuit |
| KR20210056544A (en) * | 2019-11-11 | 2021-05-20 | 삼성전자주식회사 | Digital-to-analog converter and electronic system including the same |
| CN111256849B (en) * | 2020-02-24 | 2021-11-23 | 苏州迅芯微电子有限公司 | Thermometer decoding structure applied to high-speed DAC circuit |
| CN115133928A (en) * | 2022-06-30 | 2022-09-30 | 中国科学技术大学 | DEM structure for improving dynamic performance of DAC at extremely low temperature |
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2022
- 2022-06-30 CN CN202210776955.0A patent/CN115133928A/en active Pending
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024000791A1 (en) * | 2022-06-30 | 2024-01-04 | 中国科学技术大学 | Dem structure for improving dynamic performance of dac at extremely low temperature |
| CN118041360A (en) * | 2024-04-15 | 2024-05-14 | 南京朗立微集成电路有限公司 | Method and equipment for reducing high-precision DAC output interference pulse |
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