WO2023279516A1 - 微凸块及其形成方法、芯片互连结构及方法 - Google Patents

微凸块及其形成方法、芯片互连结构及方法 Download PDF

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WO2023279516A1
WO2023279516A1 PCT/CN2021/117234 CN2021117234W WO2023279516A1 WO 2023279516 A1 WO2023279516 A1 WO 2023279516A1 CN 2021117234 W CN2021117234 W CN 2021117234W WO 2023279516 A1 WO2023279516 A1 WO 2023279516A1
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chip
silicon substrate
layer
micro
bump
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PCT/CN2021/117234
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English (en)
French (fr)
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范增焰
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长鑫存储技术有限公司
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Priority to US17/650,844 priority Critical patent/US20230005869A1/en
Publication of WO2023279516A1 publication Critical patent/WO2023279516A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Definitions

  • Embodiments of the present application relate to, but are not limited to, a microbump, a method for forming the same, and a chip interconnection structure and method.
  • copper Pillar bumps In the semiconductor packaging process, a flip-chip bonding process is usually used to bond chips to substrates or chips to chips.
  • copper Pillar bumps Copper Pillar bump
  • Copper Pillar bump technology is a technology that makes solder bumps on the surface of the chip to make the chip have better electrical conductivity, thermal conductivity and anti-electromigration capabilities.
  • the use of copper pillar bumps for packaging can not only shorten the length of the connecting circuit, reduce the area and volume of chip packaging, realize miniaturization, but also improve the performance of the chip packaging module.
  • An embodiment of the present application provides a micro-bump forming method, including: providing a chip, the chip at least including a silicon substrate and a through-silicon via through the silicon substrate; forming a conductive layer in the through-silicon via, Wherein, the conductive layer has a first preset size in a first direction, the first direction being the thickness direction of the silicon substrate; a connection layer is formed on the surface of the conductive layer in the through-silicon via ; Wherein, the connection layer has a second preset size in the first direction; the sum of the first preset size and the second preset size is equal to the TSV in the first direction an upward initial dimension; processing the silicon substrate, exposing the connection layer, and forming a micro-bump corresponding to the TSV.
  • An embodiment of the present application provides a micro-bump, the micro-bump is formed by the above micro-bump forming method; the micro-bump is located in the through silicon via structure of the chip, and the micro-bump is at least used to realize The interconnection between two chips.
  • An embodiment of the present application provides a chip interconnection method, including: providing at least two chips; the chips include through-silicon vias with openings along the first surface of the chip and a dielectric layer located on the second surface of the chip; A metal interconnection line connected to the TSV is formed in the dielectric layer; the first surface and the second surface are two opposite surfaces of the chip along the thickness direction of the chip; In the corresponding position of the said TSV of the chip, the micro-bump on the first surface of the chip is formed by the above-mentioned method of forming the micro-bump; the exposed surface of the metal interconnection in the chip is implanted Balls, forming bonding bumps on the second side of the chip; connecting the micro-bumps on the first side of the first chip in the at least two chips to the second side of the second chip in the at least two chips aligning and bonding the welding bumps, so as to realize the interconnection between the at least two chips through the micro bumps.
  • the embodiment of the present application also provides a chip interconnection structure, including: at least two chips; the chips include through-silicon vias opening along the first surface of the chip and a dielectric layer located on the second surface of the chip; A metal interconnection line connected to the through-silicon via is formed in the dielectric layer; the first surface and the second surface are two opposite surfaces of the chip along the thickness direction of the chip; The micro-bump on the first surface of the chip, wherein the micro-bump is connected to the through-silicon via; the micro-bump is formed by the above-mentioned method for forming the micro-bump; the bonding on the second surface of the chip Bumps; wherein, the bonding bumps are connected to the metal interconnection; the micro bumps on the first surface of the first chip in the at least two chips are connected to the second chip in the at least two chips.
  • the solder bumps on the second side of the chip are electrically connected.
  • FIG. 1 is a schematic cross-sectional structure diagram of a chip packaged by TSV technology in the related art
  • FIG. 2 is an optional schematic flow chart of a microbump forming method provided in an embodiment of the present application
  • 3a-3k are flowcharts of forming micro-bumps provided by the embodiment of the present application.
  • FIG. 4 is an optional structural schematic diagram of a chip and a micro-bump provided by an embodiment of the present application
  • FIG. 5 is a schematic flowchart of an optional chip interconnection method provided in the embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an optional chip interconnection structure provided by an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a cross-sectional structure of a chip packaged using TSV technology in the related art.
  • Wiring 102 metal interconnection 102 is used to lead out the signal of chip first side;
  • the second side of chip (B side as shown in Figure 1) is formed with copper post bump 103, and copper post bump 103 is made of copper
  • the post 1031 and the tin block 1032 for soldering are formed in two parts, and the position of the copper post bump 103 corresponds to the position of the TSV 104 in the chip. It can be seen from FIG. 1 that the dimension D1 of the copper stud bump in the related art is larger than the dimension D2 of the TSV.
  • the distance between adjacent bumps is also getting smaller and smaller, but the size of the copper pillar bumps formed in the related art is relatively large, and it is impossible to achieve a bump pitch of less than 20 microns. Therefore, it cannot meet
  • the current chip stacking technology requires small pitch and small size micro-bumps.
  • an embodiment of the present application provides a method for forming micro-bumps.
  • the chip transmits signals from the front of the chip to the back of the chip through Through Silicon Via (TSV) technology, and the direct stacking between chips needs to be interconnected through micro-bumps.
  • FIG. 2 is an optional schematic flow chart of the microbump forming method provided in the embodiment of the present application. As shown in FIG. 2, the method includes the following steps:
  • Step S201 providing a chip, the chip at least including a silicon substrate and through-silicon vias penetrating through the silicon substrate.
  • the chip at least includes a silicon substrate.
  • Through-silicon vias are formed inside the chip and pass through the silicon substrate of the chip.
  • the inside of the through-silicon via is filled with conductive materials to transmit signals from the front of the chip to the back of the chip.
  • the silicon substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; under the condition of ignoring the flatness of the top surface and the bottom surface of the silicon substrate, the vertical silicon substrate top surface and the bottom surface are defined
  • the direction, that is, the thickness direction of the silicon substrate is the first direction.
  • any direction is defined as the second direction.
  • the first direction is perpendicular to the second direction.
  • the first direction is defined as the X-axis direction
  • the second direction is defined as the Y-axis direction.
  • Step S202 forming a conductive layer in the TSV.
  • the conductive layer has a first predetermined dimension in a first direction, and the first direction is a thickness direction of the silicon substrate.
  • the conductive material of the conductive layer may be metal copper or metal tungsten.
  • an insulating layer, a barrier layer and a seed layer may be formed in the TSV.
  • the material of the insulating layer may be SiO 2 ;
  • the material of the barrier layer may be metal tantalum or tantalum nitride;
  • the material of the seed layer may be metal tungsten, cobalt, copper, aluminum or any combination thereof.
  • Step S203 forming a connection layer on the surface of the conductive layer in the TSV.
  • connection layer has a second preset size in the first direction; the sum of the first preset size and the second preset size is equal to the TSV in the first direction the initial size of .
  • connection layer is used to form subsequent micro-bumps.
  • Step S204 processing the silicon substrate, exposing the connection layer, and forming micro-bumps corresponding to the TSVs.
  • processing the silicon substrate refers to etching the silicon substrate or thinning the silicon substrate to expose the connection layer.
  • etching the silicon substrate may be etching the silicon substrate by using a dry etching process, and the dry etching process may be a plasma etching process, a reactive ion etching process or an ion milling process.
  • processing the silicon substrate to expose the connection layer includes two meanings: one is to process the silicon substrate to completely expose the connection layer; the other is to process the silicon substrate to expose the connection layer. out part of the connection layer.
  • forming micro-bumps corresponding to TSVs means on the one hand that the position of the formed micro-bumps corresponds to the TSVs, that is, the position of each TSV corresponds to the formation of a micro-bump; On the other hand, since the micro-bumps in the embodiment of the present application are formed inside the TSVs, the size of the formed micro-bumps is smaller than or equal to the size of the TSVs.
  • connection layer for forming the micro-bump is formed in the TSV, by removing the silicon substrate and exposing the connection layer, the micro-bump corresponding to the TSV can be formed. Blocks, in this way, can realize the preparation of micro-bumps with small size and small pitch.
  • FIGS. 3a-3k are schematic flow charts of forming micro-bumps provided by the embodiment of the present application. Next, please refer to FIGS.
  • step S201 is performed to provide a chip, the chip at least including a silicon substrate and through-silicon vias penetrating the silicon substrate.
  • the chip includes a silicon substrate and through-silicon vias opening along the first surface of the silicon substrate, and the chip further includes a dielectric layer located on the second surface of the silicon substrate, so A metal interconnection line connected to the TSV is formed in the dielectric layer.
  • the through-silicon via and the metal interconnection are jointly used to transmit signals from the first side of the silicon substrate (ie, the first side of the chip) to the second side of the silicon substrate (ie, the first side of the chip). second surface), or, transmit the signal on the second surface of the silicon substrate (that is, the second surface of the chip) to the first surface of the silicon substrate (that is, the first surface of the chip).
  • the first surface of the silicon substrate and the second surface of the silicon substrate are two opposite surfaces of the silicon substrate along a first direction.
  • the first direction is the thickness direction of the silicon substrate.
  • the chip further includes a pad on the second surface of the silicon substrate; the first end of the pad is connected to the internal circuit of the chip, and the second end of the pad is connected to the The metal interconnection in the dielectric layer; the metal interconnection is also used to lead out the signal of the second surface of the silicon substrate (ie, the second surface of the chip).
  • the metal interconnection in the dielectric layer is formed by:
  • a dielectric material is deposited on the second surface of the silicon substrate to form the dielectric layer.
  • the dielectric material may be SiO 2 or other insulating materials.
  • the process of depositing the dielectric material on the second surface of the silicon substrate may include chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD) or atomic layer deposition (Atomic Layer Deposition, ALD).
  • a patterned second photoresist layer is formed on the surface of the medium layer.
  • the dielectric layer is etched through the second photoresist layer to form interconnection holes in the dielectric layer.
  • the conductive material includes tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.
  • FIG. 3a is a schematic cross-sectional structure diagram of forming a dielectric layer and a metal interconnection line provided by the embodiment of the present application.
  • a dielectric layer 301 , and a metal interconnection line 3011 is formed in the dielectric layer 301 .
  • the chip also includes a welding pad 302 located on the second side of the silicon substrate, the first end of the welding pad 302 is connected to the internal circuit 303 in the chip, and the second end of the welding pad 302 is connected to the metal interconnection line in the dielectric layer 301 3011 connection.
  • the provision of the chip may be achieved through the following steps:
  • Step S2011 providing the silicon substrate.
  • Step S2012 taking the first surface of the silicon substrate as an etching starting point, etching the silicon substrate to form the through-silicon via through the silicon substrate.
  • the formation of the through-silicon via through the silicon substrate may be formed by the following steps:
  • a first photoresist layer is formed on the surface of the silicon substrate.
  • the first photoresist layer can be formed on the first surface of the silicon substrate by any suitable deposition process.
  • the first photoresist layer is patterned to form a window, and the window exposes the first surface of the silicon substrate.
  • the first photoresist layer may be patterned through steps such as exposure and development to form the window.
  • a first photoresist layer 304 is formed on the first surface of the silicon substrate 300 (surface D in FIG. 3b), and the first photoresist layer 304 is patterned to form a window 3041, and the window 3041 exposes the first side of the silicon substrate. It should be noted that, in FIG. 3 b , only one window is exemplarily shown in the first photoresist layer, and in an actual process, at least two windows may be formed in the first photoresist layer.
  • the size of the formed TSVs in the Y-axis direction is less than 15 microns, and the distance between two adjacent TSVs is less than 20 microns.
  • the silicon substrate is etched through the window to form through-silicon holes penetrating through the silicon substrate.
  • the silicon substrate 300 is etched through the window 3041 to form a through-silicon via 305 penetrating the silicon substrate 300 .
  • a through-silicon via 305 penetrating the silicon substrate 300 .
  • only one TSV is exemplarily shown in FIG. 3 c , but in an actual process, at least two TSVs are formed in the chip.
  • the method for forming the micro-bump further includes: removing the first photoresist layer.
  • the first photoresist layer may be removed by a wet etching process or a dry etching process. As shown in FIG. 3 d , the first photoresist layer is removed, exposing the D surface of the silicon substrate 300 .
  • step S202 is performed to form a conductive layer in the TSV.
  • the method for forming the micro-bump before forming a conductive layer in the through-silicon via, the method for forming the micro-bump further includes the following steps:
  • An insulating material is deposited on the inner wall of the TSV to form an insulating layer.
  • the insulating material may be silicon oxide or silicon oxynitride, and the insulating layer is used to protect the silicon substrate from being damaged.
  • the insulating layer may be formed by any suitable deposition process.
  • the silicon substrate may also be oxidized by in-situ oxidation under high temperature and high pressure conditions to form an insulating layer located on the inner wall of the TSV.
  • the insulating layer 306 is formed on the inner wall of the TSV 305 and the first surface (D surface) of the silicon substrate 300 .
  • a barrier material is deposited on the surface of the insulating layer to form a barrier layer.
  • the barrier material may be metal tantalum or tantalum nitride, and the barrier layer is used to prevent the diffusion of the conductive material subsequently filled in the TSV.
  • the barrier layer may be formed by any suitable deposition process.
  • a seed material is deposited on the surface of the barrier layer to form a seed layer.
  • the material of the seed layer may be any conductive material, for example, tungsten, cobalt, copper, aluminum or any combination thereof.
  • the seed layer is used for the subsequent formation of a conductive layer in the through-silicon via to provide a connection function.
  • a barrier layer 307 is formed on the surface of the insulating layer 306 , and a seed layer 308 is formed on the surface of the barrier layer 307 .
  • the forming a conductive layer in the TSV may include the following steps:
  • Step S2021 using an electrochemical deposition process to electroplate a conductive material on the surface of the seed layer in the TSV to form the conductive layer.
  • the conductive material includes: tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide or any combination thereof, and the conductive material and the seed material may be the same or different. In the embodiment of the present application, both the conductive material and the seed material forming the conductive layer are metallic copper.
  • an electro-chemical deposition process is used to electroplate conductive materials in the TSVs to form a conductive layer 309 .
  • the conductive layer 309 has a first preset size D3 in the X-axis direction, and the first preset size D3 is smaller than the initial size D4 of the TSV in the X-axis direction, that is, in the embodiment of the present application, the conductive layer 309 is not filled. Filled with TSVs.
  • step S203 is performed to form a connection layer on the surface of the conductive layer in the TSV.
  • forming a connection layer on the surface of the conductive layer in the TSV includes the following steps:
  • Step S2031 depositing solder material on the surface of the conductive layer and the seed layer in the TSV to form the connection layer.
  • the soldering material includes nickel-gold (Ni/Au) conductive material or solder paste (Solder).
  • the connection layer may be formed by any suitable deposition process.
  • solder material is deposited on the surfaces of the conductive layer 309 and the seed layer 308 in the TSVs to form a connection layer 310 .
  • the connecting layer 310 has a second predetermined dimension D5 in the X-axis direction, and the sum of the second predetermined dimension D5 and the first predetermined dimension D3 is equal to the initial dimension D4 of the TSV in the X-axis direction.
  • the forming method of the micro-bump also includes:
  • connection layer After the connection layer is formed, chemical mechanical polishing is performed on the first surface of the silicon substrate to remove the insulating layer, the barrier layer and the seed layer on the first surface of the silicon substrate.
  • the first surface (D surface) of the silicon substrate 300 is chemically mechanically polished to process the insulating layer, barrier layer and seed layer on the first surface of the silicon substrate 300, exposing the silicon substrate 300. first side.
  • step S204 is performed to process the silicon substrate to expose the connection layer and form micro-bumps corresponding to the TSVs.
  • the processing of the silicon substrate to expose the connection layer and form the micro-bumps corresponding to the TSVs may include the following steps:
  • Step S2041 taking the first surface of the silicon substrate as the starting point of etching, removing the silicon substrate with the second predetermined size, and retaining the insulating layer and the barrier layer on the sidewall of the connection layer and the seed layer, exposing the connection layer with the second predetermined size, forming micro-bumps corresponding to the through-silicon vias.
  • a dry etching process is used to etch and remove the silicon substrate with the second predetermined dimension D5, and retain the insulating layer on the side wall of the connection layer 310.
  • the layer 306 , the barrier layer 307 and the seed layer expose the connection layer 310 having a second predetermined dimension D5 to form micro-bumps corresponding to the TSVs.
  • the formed micro-bump not only includes the connecting layer, but also includes a barrier layer and an insulating layer located on the sidewall of the connecting layer.
  • the size of the formed micro-bumps in the Y-axis direction is equal to the size of the TSVs in the Y-axis direction.
  • the insulating layer and the barrier layer can prevent the solder material of the connection layer from overflowing to a certain extent, and avoid bridging between the connection layers.
  • the processing of the silicon substrate to expose the connection layer and form the micro-bumps corresponding to the TSVs may include the following steps:
  • Step S2042 taking the first surface of the silicon substrate as the starting point of etching, removing the silicon substrate with the second predetermined size and the insulating layer, the barrier layer and the sidewall of the connecting layer
  • the seed layer exposes the connection layer having the second predetermined size to form a micro-bump corresponding to the TSV.
  • a dry etching process is used to etch and remove the silicon substrate with the second predetermined dimension D5, and etch and remove the sidewall of the connection layer 310
  • the insulating layer, the barrier layer and the seed layer expose the connection layer 310 having a second predetermined dimension D5, forming a micro-bump corresponding to the TSV.
  • the formed micro-bump only includes the connecting layer, but does not include the barrier layer and the insulating layer located on the sidewall of the connecting layer.
  • the size of the formed micro-bump is equal to the size of the conductive layer in the Y-axis direction, and the size of the micro-bump in the Y-axis direction is smaller than the size of the TSV in the Y-axis direction.
  • micro-bumps with small size and small spacing can be prepared.
  • the silicon substrate with the second predetermined size and the insulating layer, barrier layer and seed layer located on the sidewall of the connection layer can be etched and removed at the same time, and the silicon liner with the second predetermined size can also be removed sequentially. Bottom and insulating layer, barrier layer and seed layer on the sidewall of the connecting layer.
  • the embodiment of the present application provides a new method for preparing micro bumps, which can realize the preparation of micro bumps with small size and small pitch, and meet the requirements of three-dimensional (Three Dimension, 3D) interconnection of bumps with appropriate pitch in the future.
  • the size of the bumps can be controlled below 15 microns, for example, the size of the bumps can be 7 microns; the pitch of the bumps can be controlled below 20 microns, for example, the pitch of the bumps can be 10 microns. Microns.
  • the filling part is passed first, and the remaining part is filled with Ni/Au Micro Bump or Solder, and the excess silicon is etched to expose the Micro Bump.
  • the formed micro-bump pitch (Bump pitch) and bump size (Bump size) can be reduced to varying degrees.
  • An embodiment of the present application provides a micro-bump, which is formed by the method for forming a micro-bump provided in the above-mentioned embodiment, the micro-bump is located in a through-silicon via structure of a chip, and the micro-bump At least for implementing the interconnection between two chips.
  • the micro bumps are also used to realize the interconnection between the chip and the substrate.
  • FIG. 4 is an optional structural schematic diagram of a chip and a micro-bump provided by the embodiment of the present application.
  • the chip includes a silicon substrate 400 and a dielectric layer 401 located on the surface of the silicon substrate 400, so A TSV 4001 is formed in the silicon substrate, the TSV 4011 corresponds to the micro-bump 50, and the dimension D6 of the micro-bump 50 in the Y-axis direction is smaller than the dimension D7 of the TSV 4001 in the Y-axis direction .
  • the chip includes at least two TSVs, and a micro-bump is formed corresponding to each TSV. piece.
  • the size of the micro-bumps in the Y-axis direction is less than 15 microns, and the distance between two adjacent micro-bumps is less than 20 microns.
  • a metal interconnection 4011 connected to the TSV 4001 is also formed in the dielectric layer 401, and the TSV 4001 and the metal interconnection 4011 are used to connect the silicon substrate
  • the signal of the first side of the bottom 400 i.e. the first side of the chip
  • the silicon substrate is the second side (i.e. the chip)
  • the signal on the second side of the silicon substrate is transmitted to the first side of the silicon substrate (ie, the first side of the chip).
  • the first surface of the silicon substrate and the second surface of the silicon substrate are two opposite surfaces of the silicon substrate along the X-axis direction.
  • micro-bumps provided by the embodiments of the present application have small pitches and small sizes, and can meet the 3D interconnection requirements of fine pitch bumps in the future.
  • micro-bumps provided in the embodiments of the present application are similar to the micro-bumps in the above-mentioned embodiments.
  • technical features that are not fully disclosed in the embodiments of the present application please refer to the above-mentioned embodiments for understanding, and details will not be repeated here.
  • FIG. 5 is an optional flowchart of the chip interconnection method provided in the embodiment of the present application. As shown in FIG. 5 , the method includes the following steps:
  • Step S501 providing at least two chips; the chips include through-silicon vias opening along the first surface of the chip and a dielectric layer located on the second surface of the chip; Metal interconnection lines connected by holes; the first surface and the second surface are two opposite surfaces of the chip along the thickness direction of the chip.
  • the chip is a chip to be packaged.
  • the chip includes a silicon substrate and a dielectric layer, and the silicon through hole is formed in the silicon substrate and penetrates through the silicon substrate.
  • a metal interconnection line is formed in the dielectric layer, and the metal interconnection line is connected to the through-silicon hole, and the through-silicon hole and the metal interconnection line are jointly used to connect the signal on the first surface of the chip transferred to the second side of the chip.
  • Step S502 forming micro-bumps on the first surface of the chip at corresponding positions of the TSVs of the chip.
  • micro-bumps are formed by the method for forming the micro-bumps provided in the above-mentioned embodiments.
  • the micro-bumps are formed by the method for forming the micro-bumps provided in the above-mentioned embodiments.
  • the chip includes at least two through-silicon vias, and a micro-bump is formed at a corresponding position of each through-silicon via.
  • Step S503 performing ball planting on the exposed surface of the metal interconnection in the chip to form a bonding bump on the second surface of the chip.
  • the metal interconnection is also used to lead out signals on the second side of the chip.
  • the bonding bumps are also used to implement chip-to-chip or chip-to-substrate stacking.
  • the size of the bonding bump is larger than that of the micro bump.
  • Step S504 aligning and bonding the micro-bumps on the first surface of the first chip among the at least two chips with the welding bumps on the second surface of the second chip among the at least two chips, In order to realize the interconnection between the at least two chips through the micro-bumps.
  • the interconnection between chips is back-to-face soldering, that is, the first surface of the first chip of the at least two chips is in contact with the second surface of the second chip of the at least two chips.
  • Chip-to-chip interconnection is achieved through alignment and bonding between microbumps and solder bumps.
  • the chip interconnection method provided by the embodiment of the present application can meet the requirements of future 3D interconnection because the micro-bumps formed on the first surface of the chip can realize small size and small pitch.
  • the embodiment of the present application also provides a chip interconnection structure, the chip interconnection structure includes at least two chips, micro bumps on the first surface of each chip, and bonding bumps on the second surface of each chip.
  • Figure 6 is a schematic structural diagram of an optional chip interconnection structure provided by the implementation of the present application. As shown in Figure 6, in the embodiment of the present application, the chip interconnection structure 60 includes two stacked 601, 602, each Microbumps 71 on the first side of a chip and bonding bumps 72 on the second side of each chip.
  • each chip in the chip interconnection structure is the same, and the internal structure of the chip is introduced below by taking chip 601 as an example.
  • the chip 601 includes TSVs 6011, 6012 opening along the first surface of the chip (such as the E surface shown in FIG. 6 ) and the second surface of the chip (the F surface shown in FIG. ) dielectric layer 6013; metal interconnection lines 6014 connected to each TSV 6011, 6012 are formed in the dielectric layer 6013.
  • the first surface (E surface) and the second surface (F surface) are two opposite surfaces of the chip 601 along the X-axis direction.
  • the micro-bumps of each chip are connected to through-silicon vias, and the micro-bumps are formed by the method for forming the micro-bumps provided in the above-mentioned embodiments.
  • the bonding bumps of each chip are connected with the metal interconnection lines.
  • the micro-bumps on the first surface of the first chip among the at least two chips are electrically connected to the welding bumps on the second surface of the second chip among the at least two chips.
  • TSVs and two micro-bumps are only shown in Figure 6 of the embodiment of the present application. In the actual process, there are multiple TSVs in the chip, and each TSV position will form a micro-bump.
  • the chip interconnection structure provided by the embodiment of the present application is similar to the chip interconnection method in the above-mentioned embodiments.
  • the technical features not disclosed in detail in the embodiments of the present application please refer to the above-mentioned embodiments for understanding, and details will not be repeated here.
  • the chip interconnection structure provided by the embodiment of the present application can meet the requirements of future 3D interconnection because the micro-bumps formed on the first surface of the chip can realize small size and small pitch.
  • the disclosed devices and methods can be implemented in non-target ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the various components shown or discussed are coupled with each other, or directly coupled.
  • the units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units; Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

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Abstract

本申请实施例提供一种微凸块及其形成方法、芯片互连结构及方法，其中，微凸块的形成方法包括：提供芯片，所述芯片至少包括硅衬底和贯穿所述硅衬底的硅通孔；在所述硅通孔中形成导电层，其中，所述导电层在第一方向上具有第一预设尺寸，所述第一方向为所述硅衬底的厚度方向；在所述硅通孔中的所述导电层的表面形成连接层；其中，所述连接层在所述第一方向上具有第二预设尺寸；所述第一预设尺寸与所述第二预设尺寸之和等于所述硅通孔在所述第一方向上的初始尺寸；处理所述硅衬底，暴露出所述连接层，形成与所述硅通孔对应的微凸块。

Description

微凸块及其形成方法、芯片互连结构及方法
相关申请的交叉引用
本申请基于申请号为202110756416.6、申请日为2021年7月5日、发明名称为“微凸块及其形成方法、芯片互连结构及方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及但不限于一种微凸块及其形成方法、芯片互连结构及方法。
背景技术
在半导体封装工艺中，通常利用倒装芯片接合工艺将芯片与基板或者芯片与芯片进行接合。相关技术中，通常采用铜柱凸块(Copper Pillar bump)来实现芯片与基板之间或者芯片与芯片之间的结合。铜柱凸块技术是在芯片的表面制作焊接凸块，使芯片具备较佳的导电、导热和抗电子迁移能力的一种技术。采用铜柱凸块进行封装，不仅可以缩短连接电路的长度，减小芯片封装面积和体积，实现微型化，而且还可以提高芯片封装模组的性能。
然而，随着芯片集成度的不断增加，相邻凸块之间的间距也越来越小，相关技术中的铜柱凸块技术，由于自身工艺的局限性，不能实现小间距和小尺寸的要求。
发明内容
本申请实施例提供一种微凸块的形成方法，包括：提供芯片，所述芯片至少包括硅衬底和贯穿所述硅衬底的硅通孔；在所述硅通孔中形成导电层，其中，所述导电层在第一方向上具有第一预设尺寸，所述第一方向为所述硅衬底的厚度方向；在所述硅通孔中的所述导电层的表面形成连接层；其中，所述连接层在所述第一方向上具有第二预设尺寸；所述第一预设尺寸与所述第二预设尺寸之和等于所述硅通孔在所述第一方向上的初始尺寸；处理所述硅衬底，暴露出所述连接层，形成与所述硅通孔对应的微凸块。
本申请实施例提供一种微凸块，所述微凸块通过上述微凸块的形成方法形成；所 述微凸块位于芯片的硅通孔结构中，且所述微凸块至少用于实现两个芯片之间的互连。
本申请实施例提供一种芯片互连方法，包括：提供至少两个芯片；所述芯片包括沿所述芯片第一面进行开口的硅通孔和位于所述芯片第二面的介质层；所述介质层中形成有与所述硅通孔连接的金属互连线；所述第一面和所述第二面为所述芯片沿所述芯片厚度方向上的相对的两个面；在所述芯片的所述硅通孔的对应位置，通过上述微凸块的形成方法形成位于所述芯片第一面的微凸块；在所述芯片中的所述金属互连线的暴露面进行植球，形成位于所述芯片第二面的键合凸块；将所述至少两个芯片中第一芯片第一面的所述微凸块与所述至少两个芯片中第二芯片第二面的所述焊接凸块进行对准和键合，以实现通过所述微凸块实现所述至少两个芯片之间的互连。
本申请实施例还提供一种芯片互连结构，包括：至少两个芯片；所述芯片包括沿所述芯片第一面进行开口的硅通孔和位于所述芯片第二面的介质层；所述介质层中形成有与所述硅通孔连接的金属互连线；所述第一面和所述第二面为所述芯片沿所述芯片厚度方向上的相对的两个面；位于所述芯片第一面的微凸块，其中，所述微凸块与所述硅通孔连接；所述微凸块通过上述微凸块的形成方法形成；位于所述芯片第二面的键合凸块；其中，所述键合凸块与所述金属互连线连接；所述至少两个芯片中第一芯片第一面的所述微凸块与所述至少两个芯片中的第二芯片第二面的所述焊接凸块电连接。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为相关技术中采用TSV技术进行封装的芯片的剖面结构示意图；
图2为本申请实施例提供的微凸块形成方法的一种可选的流程示意图；
图3a～3k为本申请实施例提供的形成微凸块的流程图；
图4为本申请实施例提供的芯片和微凸块的一种可选的结构示意图；
图5为本申请实施例提供的芯片互连方法的一种可选的流程示意图；
图6为本申请实施例提供的芯片互连结构的一种可选的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对发明的具体技术方案做进一步详细描述。以下实施例用于说明本申请，但不用来限制本申请的范围。
在后续的描述中，使用用于表示元件的诸如“模块”或“单元”的后缀仅为了有利于本申请的说明，其本身没有特定的意义。因此，“模块”或“单元”可以混合地使用。
在说明本申请实施例的微凸块(Micro bump)之前，首先，对相关技术中的铜柱凸块进行介绍。
相关技术中，通常采用铜柱凸块来实现芯片与基板之间或者芯片与芯片之间的结合。图1为相关技术中采用TSV技术进行封装的芯片的剖面结构示意图，如图1所示，芯片的第一面(如图1中示出的A面)形成有位于介质层101中的金属互连线102，金属互连线102用于引出芯片第一面的信号；芯片的第二面(如图1中示出的B面)形成有铜柱凸块103，铜柱凸块103由铜柱1031和用于焊接的锡块1032两部分形成，且铜柱凸块103的位置与芯片中的硅通孔104的位置对应。从图1中可以看出，相关技术中的铜柱凸块的尺寸D1大于硅通孔的尺寸D2。
随着芯片集成度不断增加，相邻凸块之间的间距也越来越小，而相关技术中形成的铜柱凸块的尺寸较大，无法实现凸块间距小于20微米，因此，不能满足当前芯片堆叠技术中对于小间距和小尺寸的微凸块的要求。
基于相关技术中存在的上述问题，本申请实施例提供一种微凸块的形成方法。通常芯片通过硅通孔(Through Silicon Via，TSV)技术将信号从芯片的正面传输到芯片的背面，而芯片与芯片之间的直接堆叠需要通过微凸块互连。图2为本申请实施例提供的微凸块形成方法的一种可选的流程示意图，如图2所示，所述方法包括以下步骤：
步骤S201、提供芯片，所述芯片至少包括硅衬底和贯穿所述硅衬底的硅通孔。
芯片的内部形成有各种有源器件和电路，用于实现各种功能各样的功能。本申请实施例中，芯片至少包括硅衬底。
硅通孔是形成在芯片内部，且贯穿芯片硅衬底的通孔，硅通孔内部填充导电材料，用于实现将芯片正面的信号传输至芯片的背面。
所述硅衬底可以包括处于正面的顶表面以及处于与正面相对的背面的底表面；在忽略硅衬底顶表面和底表面的平整度的情况下，定义垂直硅衬底顶表面和底表面的方 向，即硅衬底的厚度方向为第一方向。在硅衬底顶表面和底表面内(即硅衬底所在的平面)，定义任意一个方向为第二方向。这里，所述第一方向垂直于所述第二方向。本申请实施例中，定义所述第一方向为X轴方向，定义所述第二方向为Y轴方向。
步骤S202、在所述硅通孔中形成导电层。
其中，所述导电层在第一方向上具有第一预设尺寸，所述第一方向为所述硅衬底的厚度方向。
在一些实施例中，导电层的导电材料可以是金属铜或者金属钨。
在其它实施例中，在所述硅通孔中形成所述导电层之前，可以先在所述硅通孔中形成绝缘层、阻挡层和种子层。其中，绝缘层的材料可以是SiO 2；阻挡层的材料可以是金属钽或者氮化钽；所述种子层材料可以是金属钨、钴、铜、铝或其任何组合。
步骤S203、在所述硅通孔中的所述导电层的表面形成连接层。
其中，所述连接层在所述第一方向上具有第二预设尺寸；所述第一预设尺寸与所述第二预设尺寸之和等于所述硅通孔在所述第一方向上的初始尺寸。
本申请实施例中，所述连接层用于形成后续的微凸块。
步骤S204、处理所述硅衬底，暴露出所述连接层，形成与所述硅通孔对应的微凸块。
本申请实施例中，处理硅衬底是指刻蚀硅衬底或者对硅衬底进行减薄处理，以暴露出连接层。这里，刻蚀硅衬底可以是采用干法刻蚀工艺刻蚀硅衬底，所述干法刻蚀工艺可以是等离子体刻蚀工艺，反应离子刻蚀工艺或者离子铣工艺。
需要说明的是，本申请实施例中，处理硅衬底，暴露出所述连接层包含两种含义：一是处理硅衬底，完全暴露出所述连接层；二是处理硅衬底，暴露出部分所述连接层。
本申请实施例中，形成与硅通孔对应的微凸块，一方面是指形成的微凸块的位置与硅通孔对应，即每个硅通孔的位置都会对应形成一个微凸块；另一方面由于本申请实施例中的微凸块形成于硅通孔内部，因此，形成的微凸块的尺寸小于或者等于硅通孔的尺寸。
本申请实施例提供的微凸块的形成方法，由于形成微凸块的连接层形成于硅通孔中，通过去除硅衬底，暴露出连接层，即可形成与硅通孔对应的微凸块，如此，可以实现制备具有小尺寸和小间距的微凸块。
图3a～3k为本申请实施例提供的形成微凸块的流程示意图，接下来请参考图3a～3k对本申请实施例提供的微凸块的形成方法进一步地详细说明。
首先，可以参考图3a～3d，执行步骤S201、提供芯片，所述芯片至少包括硅衬底和贯穿所述硅衬底的硅通孔。
本申请实施例中，所述芯片包括硅衬底和沿所述硅衬底的第一面进行开口的硅通孔，所述芯片还包括位于所述硅衬底第二面的介质层，所述介质层中形成有与所述硅通孔连接的金属互连线。所述硅通孔和所述金属互连线共同用于将所述硅衬底的第一面(即芯片的第一面)的信号传输至所述硅衬底的第二面(即芯片的第二面)，或者，将所述硅衬底第二面(即芯片的第二面)的信号传输至硅衬底的第一面(即芯片的第一面)。所述硅衬底的第一面和所述硅衬底的第二面为所述硅衬底沿第一方向上相对的两个面。所述第一方向为硅衬底的厚度方向。
在一些实施例中，所述芯片还包括位于所述硅衬底第二面的焊垫；所述焊垫的第一端连接所述芯片的内部电路，所述焊垫的第二端连接所述介质层中的金属互连线；所述金属互连线还用于引出所述硅衬底的第二面(即芯片的第二面)的信号。
在一些实施例中，位于所述介质层中的所述金属互连线通过以下方式形成：
在所述硅衬底的第二面沉积介质材料，形成所述介质层。
这里，所述介质材料可以是SiO 2或者其它绝缘材料。在硅衬底的第二面沉积介质材料的工艺可以包括化学气相沉积(Chemical Vapor Deposition，CVD)、物理气相沉积(Physical Vapor Deposition，PVD)或者原子层沉积(Atomic Layer Deposition，ALD)。
在所述介质层的表面形成图形化的第二光阻层。
通过所述第二光阻层，刻蚀所述介质层，形成位于所述介质层中的互连孔。
在所述互连孔中填充导电材料，形成位于所述介质层中的所述金属互连线。
在一些实施例中，所述导电材料包括钨(W)、钴(Co)、铜(Cu)、铝(Al)、多晶硅、掺杂硅、硅化物或其任何组合。
在一些实施例中，在芯片的形成过程，首先形成介质层和金属互连线，然后形成硅通孔。图3a为本申请实施例提供的形成介质层和金属互连线的剖面结构示意图，如图3a所示，在硅衬底300的第二面(如图3a中示出的C面)形成有介质层301，介质层301中形成有金属互连线3011。芯片还包括位于所述硅衬底第二面的焊垫302，焊垫302的第一端与芯片中的内部电路303连接，焊垫302的第二端与介质层301中的金属互连线3011连接。
在一些实施例中，所述提供芯片，可以通过以下步骤实现：
步骤S2011、提供所述硅衬底。
步骤S2012、以所述硅衬底的第一面为刻蚀起点，刻蚀所述硅衬底，形成贯穿所述硅衬底的所述硅通孔。
在一些实施例中，所述形成贯穿所述硅衬底的硅通孔，可以通过以下步骤形成：
在所述硅衬底的表面形成第一光阻层。
这里，可以通过任意一种合适的沉积工艺在硅衬底的第一面形成第一光阻层。
图形化所述第一光阻层，形成窗口，所述窗口暴露出所述硅衬底的第一面。
在一些实施例中，可以通过曝光、显影等步骤来图形化第一光阻层，形成所述窗口。
如图3b所示，在硅衬底300的第一面(如图3b中的D面)形成第一光阻层304，图形化第一光阻层304形成窗口3041，所述窗口3041暴露出硅衬底的第一面。值得注意的是，图3b中仅仅示例性地示出了在第一光阻层中形成一个窗口，在实际工艺中，第一光阻层中可以形成至少两个窗口。
本申请实施例中，形成的硅通孔在Y轴方向上的尺寸小于15微米，且相邻两个硅通孔之间的间距小于20微米。
通过所述窗口，刻蚀所述硅衬底，形成贯穿所述硅衬底的硅通孔。
如图3c所示，通过所述窗口3041刻蚀硅衬底300，形成了贯穿硅衬底300的硅通孔305。需要说明的是，图3c中仅仅示例性地示出了一个硅通孔，在实际工艺中，所述芯片中形成有至少两个硅通孔。
在一些实施例中，在通过所述第一光阻层中的窗口形成所述硅通孔后，所述微凸块的形成方法还包括：去除所述第一光阻层。
本申请实施例中，可以通过湿法刻蚀工艺或者干法刻蚀工艺去除所述第一光阻层。如图3d所示，去除了第一光阻层，暴露出了所述硅衬底300的D面。
接下来，可以参考图3e～3g，执行步骤S202、在所述硅通孔中形成导电层。
在一些实施例中，在所述硅通孔中形成导电层之前，所述微凸块的形成方法还包括以下步骤：
在所述硅通孔的内壁沉积绝缘材料，形成绝缘层。
本申请实施例中，所述绝缘材料可以是氧化硅或者氮氧化硅，所述绝缘层用于保护硅衬底不被破坏。这里，可以通过任意一种合适的沉积工艺形成所述绝缘层。
在一些实施例中，也可以在高温、高压条件下，通过原位氧化的方式，氧化所述硅衬底，形成位于所述硅通孔内壁的绝缘层。
如图3e所示，在硅通孔305的内壁和硅衬底300的第一面(D面)均形成了所述绝缘层306。
在所述绝缘层的表面沉积阻挡材料，形成阻挡层。
本申请实施例中，所述阻挡材料可以是金属钽或者氮化钽，所述阻挡层用于防止后续填充在硅通孔中的导电材料的扩散。这里，可以通过任意一种合适的沉积工艺形成所述阻挡层。
在所述阻挡层的表面沉积种子材料，形成种子层。
本申请实施例中，所述种子层材料可以是任意一种导电材料，例如，钨、钴、铜、铝或其任何组合。所述种子层用于为后续在硅通孔中形成导电层，提供衔接作用。
如图3f所示，在绝缘层306的表面形成了阻挡层307，并且在阻挡层307的表面形成了种子层308。
在一些实施例中，所述在所述硅通孔中形成导电层，可以包括以下步骤：
步骤S2021、采用电化学沉积工艺，在所述硅通孔中的所述种子层的表面电镀导电材料，形成所述导电层。
在一些实施例中，所述导电材料包括：钨、钴、铜、铝、多晶硅、掺杂硅、硅化物或其任何组合，所述导电材料与所述种子材料可以相同，也可以不同。本申请实施例中，形成所述导电层的导电材料和种子材料均为金属铜。
如图3g所示，采用电化学沉积工艺，在硅通孔中电镀导电材料，形成导电层309。所述导电层309在X轴方向上具有第一预设尺寸D3，第一预设尺寸D3小于硅通孔在X轴方向上的初始尺寸D4，即本申请实施例中，导电层309未填充满硅通孔。
接下来，可以参考图3h和3i，执行步骤S203、在所述硅通孔中的所述导电层的表面形成连接层。
在一些实施例中，所述在所述硅通孔中的所述导电层的表面形成连接层，包括以下步骤：
步骤S2031、在所述硅通孔中的所述导电层和所述种子层的表面沉积焊接材料，形成所述连接层。
本申请实施例中，所述焊接材料包括镍金(Ni/Au)导电材料或者焊锡膏(Solder)。这里，可以通过任意一种合适的沉积工艺形成所述连接层。
如图3h所示，在硅通孔中的导电层309和种子层308的表面沉积焊接材料，形成连接层310。所述连接层310在X轴方向上具有第二预设尺寸D5，第二预设尺寸 D5与第一预设尺寸D3之和等于硅通孔在X轴方向上的初始尺寸D4。
在一些实施例中，在硅通孔中形成绝缘层，阻挡层和种子层时，在所述硅衬底的第一面同时也形成有所述绝缘层、所述阻挡层和所述种子层，所述微凸块的形成方法还包括：
在形成所述连接层之后，对所述硅衬底的第一面进行化学机械抛光处理，以去除所述硅衬底第一面的所述绝缘层、所述阻挡层和所述种子层。
如图3i所示，对硅衬底300第一面(D面)进行化学机械抛光处理，去处理硅衬底300第一面的绝缘层、阻挡层和种子层，暴露出硅衬底300的第一面。
接下来，可以参考图3j和3k，执行步骤S204、处理所述硅衬底，暴露出所述连接层，形成与所述硅通孔对应的微凸块。
在一些实施例中，所述处理所述硅衬底，暴露出所述连接层，形成与所述硅通孔对应的微凸块，可以包括以下步骤：
步骤S2041、以所述硅衬底的第一面为刻蚀起点，去除具有所述第二预设尺寸的硅衬底，保留位于所述连接层侧壁的所述绝缘层、所述阻挡层和所述种子层，暴露出具有所述第二预设尺寸的连接层，形成与所述硅通孔对应的微凸块。
如图3j所示，以硅衬底300的D面为刻蚀起点，采用干法刻蚀工艺刻蚀去除具有第二预设尺寸D5的硅衬底，并保留位于连接层310侧壁的绝缘层306、阻挡层307和种子层，暴露出具有第二预设尺寸D5的连接层310，形成与所述硅通孔对应的微凸块。
本申请实施例中，所形成的微凸块不仅包括连接层，还包括位于连接层侧壁的阻挡层和绝缘层。所形成的微凸块在Y轴方向上尺寸与硅通孔在Y轴方向的尺寸相等。绝缘层和阻挡层可以在一定程度上防止连接层的焊接材料外溢，避免连接层之间的桥接。
在一些实施例中，所述处理所述硅衬底，暴露出所述连接层，形成与所述硅通孔对应的微凸块，可以包括以下步骤：
步骤S2042、以所述硅衬底的第一面为刻蚀起点，去除具有所述第二预设尺寸的硅衬底和位于所述连接层侧壁的所述绝缘层、所述阻挡层和所述种子层，暴露出具有所述第二预设尺寸的连接层，形成与所述硅通孔对应的微凸块。
如图3k所示，以硅衬底300的D面为刻蚀起点，采用干法刻蚀工艺刻蚀去除具有第二预设尺寸D5的硅衬底，并刻蚀去除位于连接层310侧壁的绝缘层、阻挡层和 种子层，暴露出具有第二预设尺寸D5的连接层310，形成与所述硅通孔对应的微凸块。
本申请实施例中，所形成的微凸块仅包括连接层，而不包括位于连接层侧壁的阻挡层和绝缘层。所形成的微凸块在Y轴方向上尺寸与导电层在Y轴方向的尺寸相等，且微凸块在Y轴方向上的尺寸小于硅通孔在Y轴方向上的尺寸。本申请实施例中，通过去除连接层侧壁的绝缘层和阻挡层，可以制备得到具有小尺寸和小间距的微凸块。
在一些实施例中，可以同时刻蚀去除具有第二预设尺寸的硅衬底和位于连接层侧壁的绝缘层、阻挡层和种子层，也可以依次去除具有第二预设尺寸的硅衬底和位于连接层侧壁的绝缘层、阻挡层和种子层。
本申请实施例提供了一种制备微凸块的新方法，可以实现制备得到具有小尺寸和小间距的Micro bump，应对未来合适间距凸块的三维(Three Dimension，3D)互连的需求。通过本申请实施例所形成的微凸块，凸块尺寸可以控制在15微米以下，例如，凸块尺寸可以是7微米；凸块间距可以控制在20微米以下，例如，凸块间距可以是10微米。
本申请实施例，在硅通孔的后端封装工艺(TSV Via last)实现过程中先填充部分通过，余下部分填充Ni/Au Micro Bump或Solder，刻蚀多余硅，裸露Micro Bump。通过本申请实施例提供的微凸块的形成方法，所形成的微凸块间距(Bump pitch)与凸块尺寸(Bump size)均可以做到不同程度的缩小。
本申请实施例提供一种微凸块，所述微凸块通过上述实施例提供的微凸块的形成方法形成，所述微凸块位于芯片的硅通孔结构中，且所述微凸块至少用于实现两个芯片之间的互连。
在其它实施例中，所述微凸块还用于实现芯片与基板之间的互连。
图4为本申请实施例提供的芯片和微凸块的一种可选的结构示意图，如图4所示，所述芯片包括硅衬底400和位于硅衬底400表面的介质层401，所述硅衬底中形成有硅通孔4001，所述硅通孔4011与微凸块50对应，所述微凸块50在Y轴方向的尺寸D6小于硅通孔4001在Y轴方向的尺寸D7。
值得注意的是，图4中仅仅示出了一个硅通孔和一个微凸块，在实际制作过程中，芯片至少包括两个硅通孔，且对应于每一硅通孔都会形成一个微凸块。
本申请实施例中，所述微凸块在Y轴方向的尺寸小于15微米，且相邻两个微凸块之间的间距小于20微米。
在一些实施例中，所述介质层401中还形成有与硅通孔4001相连的金属互连线4011，所述硅通孔4001和所述金属互连线4011共同用于将所述硅衬底400的第一面(即芯片的第一面)的信号传输至所述硅衬底400的第二面(即芯片的第二面)，或者，将硅衬底是第二面(即芯片的第二面)的信号传输至硅衬底的第一面(即芯片的第一面)。所述硅衬底的第一面和所述硅衬底的第二面为所述硅衬底沿X轴方向上相对的两个面。
本申请实施例提供的微凸块，具有小间距和小尺寸，可以应对未来fine pitch bump的3D互连需求。
本申请实施例提供的微凸块与上述实施例中的微凸块的形成方法类似，对于本申请实施例未详尽披露的技术特征，请参考上述实施例进行理解，这里，不再赘述。
本申请实施例提供一种芯片互连方法，图5为本申请实施例提供的芯片互连方法的一种可选的流程示意图，如图5所示，所述方法包括以下步骤：
步骤S501、提供至少两个芯片；所述芯片包括沿所述芯片第一面进行开口的硅通孔和位于所述芯片第二面的介质层；所述介质层中形成有与所述硅通孔连接的金属互连线；所述第一面和所述第二面为所述芯片沿所述芯片厚度方向上的相对的两个面。
本申请实施例中，所述芯片为待封装的芯片。芯片包括硅衬底和介质层，所述硅通孔形成于所述硅衬底中，并贯穿所述硅衬底。所述介质层中形成有金属互连线，所述金属互连线与所述硅通孔连接，所述硅通孔和所述金属互连线共同用于将所述芯片第一面的信号传输至所述芯片的第二面。
步骤S502、在所述芯片的所述硅通孔的对应位置，形成位于所述芯片第一面的微凸块。
所述微凸块通过上述实施例提供的微凸块的形成方法形成，对于本申请实施例未详尽披露的技术特征，请参照上述实施例进行理解。
本申请实施例中，所述芯片包括至少两个硅通孔，每一硅通孔的对应位置均会形成一个微凸块。
步骤S503、在所述芯片中的所述金属互连线的暴露面进行植球，形成位于所述芯片第二面的键合凸块。
在一些实施例中，所述金属互连线还用于引出芯片第二面的信号。所述键合凸块也用于实现芯片与芯片或者芯片与基板之间的堆叠。这里，所述键合凸块的尺寸大于微凸块的尺寸。
步骤S504、将所述至少两个芯片中第一芯片第一面的所述微凸块与所述至少两个芯片中第二芯片第二面的所述焊接凸块进行对准和键合，以实现通过所述微凸块实现所述至少两个芯片之间的互连。
本申请实施例中，芯片与芯片之间的互连是背对面焊接的方式，即至少两个芯片中的第一芯片的第一面与至少两个芯片中第二芯片的第二面相接触。通过微凸块和焊接凸块之间的对准和键合，实现芯片与芯片之间的互连。
本申请实施例提供的芯片互连方法，由于在芯片第一面形成的微凸块可以实现小尺寸和小间距，如此，能够满足未来3D互连的需求。
本申请实施例还提供一种芯片互连结构，所述芯片互连结构包括至少两个芯片、位于每一芯片第一面的微凸块和位于每一芯片第二面的键合凸块。图6为本申请实施提供的芯片互连结构一种可选的结构示意图，如图6所示，本申请实施例中，所述芯片互连结构60包括两个堆叠的601、602、位于每一芯片第一面的微凸块71和位于每一芯片第二面的键合凸块72。
本申请实施例中，所述芯片互连结构中的每一个芯片的结构都是相同的，下面，以芯片601为例对芯片的内部结构进行介绍。
请继续参见图6，芯片601包括沿芯片第一面(如图6中示出的E面)进行开口的硅通孔6011、6012和位于芯片第二面(如图6中示出的F面)的介质层6013；所述介质层6013中形成有与每一硅通孔6011、6012连接的金属互连线6014。其中，第一面(E面)和第二面(F面)为芯片601沿X轴方向上的相对的两个面。
本申请实施例中，每一芯片的所述微凸块与硅通孔连接，所述微凸块通过上述实施例提供的微凸块的形成方法形成。且每一芯片的键合凸块与所述金属互连线连接。所述至少两个芯片中第一芯片第一面的所述微凸块与所述至少两个芯片中的第二芯片第二面的所述焊接凸块电连接。
需要说明的是，本申请实施例图6中只是示例性示出了两个硅通孔和两个微凸块，在实际工艺中，芯片中存在多个硅通孔，每一硅通孔的位置都会形成一个微凸块。
本申请实施例提供的芯片互连结构与上述实施例中的芯片互连方法类似，对于本申请实施例未详尽披露的技术特征，请参照上述实施例进行理解，这里不再赘述。
本申请实施例提供的芯片互连结构，由于在芯片第一面形成的微凸块可以实现小尺寸和小间距，如此，能够满足未来3D互连的需求。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过 非目标的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个***，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
本申请所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本申请的一些实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (17)

  1. 一种微凸块的形成方法，包括：
    提供芯片，所述芯片至少包括硅衬底和贯穿所述硅衬底的硅通孔；
    在所述硅通孔中形成导电层，其中，所述导电层在第一方向上具有第一预设尺寸，所述第一方向为所述硅衬底的厚度方向；
    在所述硅通孔中的所述导电层的表面形成连接层；其中，所述连接层在所述第一方向上具有第二预设尺寸；所述第一预设尺寸与所述第二预设尺寸之和等于所述硅通孔在所述第一方向上的初始尺寸；
    处理所述硅衬底，暴露出所述连接层，形成与所述硅通孔对应的微凸块。
  2. 根据权利要求1所述的方法，其中，在形成所述导电层之前，所述方法还包括：
    在所述硅通孔的内壁沉积绝缘材料，形成绝缘层；
    在所述绝缘层的表面沉积阻挡材料，形成阻挡层；
    在所述阻挡层的表面沉积种子材料，形成种子层。
  3. 根据权利要求2所述的方法，其中，所述在所述硅通孔中形成导电层，包括：
    采用电化学沉积工艺，在所述硅通孔中的所述种子层的表面电镀导电材料，形成所述导电层；
    其中，所述导电材料与所述种子材料相同。
  4. 根据权利要求2所述的方法，其中，所述在所述硅通孔中的所述导电层的表面形成连接层，包括：
    在所述硅通孔中的所述导电层和所述种子层的表面沉积焊接材料，形成所述连接层；
    其中，所述焊接材料包括镍金导电材料或者焊锡膏。
  5. 根据权利要求2至4任一项所述的方法，其中，所述硅衬底的第一面形成有所述绝缘层、所述阻挡层和所述种子层；所述方法还包括：
    在形成所述连接层之后，对所述硅衬底的第一面进行化学机械抛光处理，以去除所述硅衬底第一面的所述绝缘层、所述阻挡层和所述种子层。
  6. 根据权利要求5所述的方法，其中，所述处理所述硅衬底，暴露出所述连接层，形成与所述硅通孔对应的微凸块，包括：
    以所述硅衬底的第一面为刻蚀起点，去除具有所述第二预设尺寸的硅衬底，保留位于所述连接层侧壁的所述绝缘层、所述阻挡层和所述种子层，暴露出具有所述第二预设尺寸的连接层，形成与所述硅通孔对应的微凸块。
  7. 根据权利要求5所述的方法，其中，所述处理所述硅衬底，暴露出所述连接层，形成与所述硅通孔对应的微凸块，包括：
    以所述硅衬底的第一面为刻蚀起点，去除具有所述第二预设尺寸的硅衬底和位于所述连接层侧壁的所述绝缘层、所述阻挡层和所述种子层，暴露出具有所述第二预设尺寸的连接层，形成与所述硅通孔对应的微凸块。
  8. 根据权利要求1所述的方法，其中，所述提供芯片，包括：
    提供所述硅衬底；
    以所述硅衬底的第一面为刻蚀起点，刻蚀所述硅衬底，形成贯穿所述硅衬底的所述硅通孔；
    其中，所述硅通孔在第二方向上的尺寸小于15微米，且相邻两个硅通孔之间的间距小于20微米；所述第二方向垂直于所述第一方向。
  9. 根据权利要求8所述的方法，其中，所述形成贯穿所述硅衬底的硅通孔，包括：
    在所述硅衬底的第一面形成第一光阻层；
    图形化所述第一光阻层，形成窗口，所述窗口暴露出所述硅衬底的第一面；
    通过所述窗口，刻蚀所述硅衬底，形成贯穿所述硅衬底的硅通孔。
  10. 根据权利要求5所述的方法，其中，所述芯片还包括：
    位于所述硅衬底的第二面的介质层；所述介质层中形成有与所述硅通孔连接的金属互连线；其中，所述硅衬底的第一面和所述硅衬底的第二面为所述硅衬底沿所述第一方向上相对的两个面；
    所述硅通孔和所述金属互连线共同用于将所述硅衬底的第一面的信号传输至所述硅衬底的第二面。
  11. 根据权利要求10所述的方法，其中，位于所述介质层中的所述金属互连线通过以下方式形成：
    在所述硅衬底的第二面沉积介质材料，形成所述介质层；
    在所述介质层的表面形成图形化的第二光阻层；
    通过所述第二光阻层，刻蚀所述介质层，形成位于所述介质层中的互连孔；
    在所述互连孔中填充导电材料，形成位于所述介质层中的所述金属互连线。
  12. 根据权利要求10所述的方法，其中，所述芯片还包括位于所述硅衬底第二面的焊垫；
    所述焊垫的第一端连接所述芯片的内部电路，所述焊垫的第二端连接所述介质层中的金属互连线；所述金属互连线还用于引出所述硅衬底的第二面的信号。
  13. 一种微凸块，所述微凸块通过上述权利要求1至12任一项提供的微凸块的形成方法形成；
    所述微凸块位于芯片的硅通孔结构中，且所述微凸块至少用于实现两个芯片之间的互连。
  14. 根据权利要求13所述的微凸块，其中，所述芯片包括贯穿所述芯片硅衬底的硅通孔；
    所述硅通孔与所述微凸块对应，且所述微凸块在垂直于第一方向上的尺寸小于所述硅通孔在垂直于所述的第一方向上的尺寸；
    其中，所述第一方向为所述硅衬底的厚度方向。
  15. 根据权利要求14所述的微凸块，其中，所述微凸块在第二方向上的尺寸小于15微米，且相邻两个微凸块之间的间距小于20微米，其中，所述第二方向垂直于所述第一方向。
  16. 一种芯片互连方法，包括：
    提供至少两个芯片；所述芯片包括沿所述芯片第一面进行开口的硅通孔和位于所述芯片第二面的介质层；所述介质层中形成有与所述硅通孔连接的金属互连线；所述第一面和所述第二面为所述芯片沿所述芯片厚度方向上的相对的两个面；
    在所述芯片的所述硅通孔的对应位置，通过上述权利要求1至12任一项所述的方法形成位于所述芯片第一面的微凸块；
    在所述芯片中的所述金属互连线的暴露面进行植球，形成位于所述芯片第二面的键合凸块；
    将所述至少两个芯片中第一芯片第一面的所述微凸块与所述至少两个芯片中第二芯片第二面的所述焊接凸块进行对准和键合，以实现通过所述微凸块实现所述至少两个芯片之间的互连。
  17. 一种芯片互连结构，包括：至少两个芯片；
    所述芯片包括沿所述芯片第一面进行开口的硅通孔和位于所述芯片第二面的介 质层；所述介质层中形成有与所述硅通孔连接的金属互连线；所述第一面和所述第二面为所述芯片沿所述芯片厚度方向上的相对的两个面；
    位于所述芯片第一面的微凸块，其中，所述微凸块与所述硅通孔连接；所述微凸块通过上述权利要求1至12任一项提供的微凸块的形成方法形成；
    位于所述芯片第二面的键合凸块；其中，所述键合凸块与所述金属互连线连接；
    所述至少两个芯片中第一芯片第一面的所述微凸块与所述至少两个芯片中的第二芯片第二面的所述焊接凸块电连接。
PCT/CN2021/117234 2021-07-05 2021-09-08 微凸块及其形成方法、芯片互连结构及方法 WO2023279516A1 (zh)

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