WO2023279259A1 - 一种高压发光二极管 - Google Patents

一种高压发光二极管 Download PDF

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Publication number
WO2023279259A1
WO2023279259A1 PCT/CN2021/104777 CN2021104777W WO2023279259A1 WO 2023279259 A1 WO2023279259 A1 WO 2023279259A1 CN 2021104777 W CN2021104777 W CN 2021104777W WO 2023279259 A1 WO2023279259 A1 WO 2023279259A1
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WO
WIPO (PCT)
Prior art keywords
isolation groove
emitting diode
mesa
light
side wall
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PCT/CN2021/104777
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English (en)
French (fr)
Inventor
熊伟平
吴志伟
高迪
郭桓邵
彭钰仁
Original Assignee
泉州三安半导体科技有限公司
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Application filed by 泉州三安半导体科技有限公司 filed Critical 泉州三安半导体科技有限公司
Priority to CN202180005886.7A priority Critical patent/CN114586184A/zh
Priority to PCT/CN2021/104777 priority patent/WO2023279259A1/zh
Publication of WO2023279259A1 publication Critical patent/WO2023279259A1/zh
Priority to US18/405,316 priority patent/US20240145441A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the invention relates to the field of semiconductor devices, in particular to a high-voltage light-emitting diode.
  • adjacent chiplets are electrically connected to each other through interconnect structures.
  • the interconnect structure when the interconnect structure is evaporated, the evaporation vapor is laterally deposited on the sidewalls of the mesa on both sides of the isolation groove between adjacent sub-chips.
  • the inclination angle of the side wall of the mesa is large, the evaporation is difficult, the evaporation thickness is insufficient, and the interconnection structure is prone to cracks.
  • the diode is burned; or there will be a problem that the interconnection bar is directly disconnected, and the light-emitting diode cannot emit light normally.
  • the object of the present invention is to provide a high-voltage light-emitting diode.
  • the present invention provides a high-voltage light-emitting diode, which includes a substrate and an LED chip unit formed on the substrate, and the LED chip unit includes a plurality of sub-chips separated by isolation grooves.
  • the adjacent sub-chips are conductively connected through a bridge structure; the isolation groove extends in a first direction, and the isolation groove includes a first isolation groove and a second isolation groove, wherein the width of the first isolation groove is larger than the width of the first isolation groove.
  • the width of the second isolation groove, the side wall of the first isolation groove extending in the second direction intersecting with the first direction is the first side wall, extending in the first direction and connecting with the first
  • the side wall connected by one side wall is the second side wall, the area where the first side wall is connected to the second side wall is formed as an arc-shaped area, and the bridging structure is formed on the surface of the isolation groove and the side wall on, and cover the arc-shaped area.
  • the LED chip unit includes a semiconductor light-emitting sequence layer formed on the substrate, and the semiconductor light-emitting sequence layer includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially formed on the substrate , the thickness of the light-emitting sequence layer is between 6 ⁇ m and 8 ⁇ m.
  • the angle between the sidewall of the isolation groove and the surface of the substrate is between 60° and 90°.
  • part of the first semiconductor layer in the semiconductor light-emitting sequence layer forms a first mesa
  • the second semiconductor layer in the semiconductor light-emitting sequence layer forms a second mesa
  • all adjacent The first mesas and the second mesas of the sub-chips are adjacent, and the bridging structure is formed on the first and second mesas of the adjacent sub-chips.
  • the angle between the side wall of the second mesa and the surface of the first mesa is between 50° and 70°.
  • the isolation trench is formed between the first mesa and the second mesa of adjacent sub-chips, wherein the first isolation trench is located at an end of the isolation trench.
  • the width of the first isolation trench ranges from 10 ⁇ m to 50 ⁇ m.
  • the width of the second isolation trench ranges from 3 ⁇ m to 10 ⁇ m.
  • the bridging structure includes a conductive metal layer, and the conductive metal layer has a thickness ranging from 0.1 ⁇ m to 2 ⁇ m.
  • the thickness of the bridging structure formed on the sidewall of the isolation groove is d1
  • the thickness of the bridging structure formed above the first mesa and the second mesa is d2, d1:d2 Between 6:10 ⁇ 10:10.
  • the isolation trench is filled with an insulating dielectric layer, and the bridging structure is formed above the insulating dielectric layer.
  • the high-voltage light-emitting diodes are red light-emitting diodes.
  • an electrode structure is also included, and the electrode structure is arranged above the sub-chip at the starting end and the sub-chip at the end of the LED chip unit.
  • the high-voltage light-emitting diode provided by the present invention has at least the following beneficial technical effects:
  • the isolation groove between adjacent sub-chips includes a first isolation groove and a second isolation groove, the first isolation groove and the second isolation groove are continuous structures, and the width of the first isolation groove is larger than The width of the second isolation slot.
  • An arc-shaped area is formed at a position where the first isolation groove is connected with the second isolation groove.
  • the bridge structure of the adjacent sub-chip covers the arc-shaped area, which increases the adhesion of the bridge structure and makes it cover the arc-shaped area, thereby ensuring the stability of the bridge structure and making it less prone to defects such as cracks or breaks , improve the reliability of the device.
  • the above-mentioned isolation groove structure is especially in the case where the thickness of the epitaxial layer is relatively large (for example, a red light LED chip unit of 6 ⁇ m to 8 ⁇ m), and the inclination angle of the side wall of the mesa of the epitaxial layer is relatively large (for example, 60° to 90°), the isolation groove of the present invention Structures in particular can enhance the stability of bridging structures.
  • the thickness of the bridge structure can be controlled to be thin (for example, 0.1 ⁇ m ⁇ 2 ⁇ m). Therefore, on the one hand, the flatness of each plane of the device can be ensured, which facilitates the subsequent manufacturing process; on the other hand, the manufacturing cost of the device can be effectively reduced.
  • the above-mentioned first wide isolation groove is formed adjacent to the dicing lines of adjacent LED chip units.
  • the formation of the first isolation trench adjacent to the scribe line can form the above-mentioned first isolation trench without losing or losing a very small light-emitting area, so as to ensure the light-emitting area of the chip.
  • Fig. 1a shows a schematic structural diagram of a traditional high-voltage LED chip unit.
  • Fig. 1b is a cross-sectional scanning view of the isolation groove of the LED chip shown in Fig. 1a.
  • FIG. 2 shows a schematic structural diagram of an LED chip unit of a high-voltage light-emitting diode provided in Embodiment 1 of the present invention.
  • Fig. 3a is shown as a sectional view along the line L-L in Fig. 2 .
  • Fig. 3b is a partially enlarged schematic diagram of area A in Fig. 3a.
  • FIG. 4 is a schematic perspective view of the LED chip unit shown in FIG. 2 .
  • FIG. 5 is a schematic diagram of forming a bridge structure in the LED chip unit shown in FIG. 2 .
  • FIG. 6 shows a schematic structural diagram of an LED chip unit of a high-voltage light-emitting diode provided in Embodiment 2 of the present invention.
  • FIG. 7 is a schematic diagram of forming a bridge structure in the LED chip unit shown in FIG. 6 .
  • a traditional high-voltage light-emitting diode 001 is shown, which exemplarily shows that the high-voltage light-emitting diode 001 includes a substrate 100 and two sub-chips formed on the substrate: a first sub-chip 011 and a second sub-chip 012 , the two sub-chips are separated from each other by the isolation groove 013, and the two sides of the isolation groove are mesa I and mesa II of the two sub-chips.
  • the interconnection bars 014 are formed on the surfaces and sidewalls of the mesa I and the mesa II on both sides of the isolation trench to realize the electrical connection of the two sub-chips.
  • the thickness of the interconnection bar is significantly smaller than the thickness of the interconnection bar above mesa I and mesa II.
  • the thickness of the interconnection bar on the side wall of the isolation trench is the same as the thickness of the interconnection bar above mesa I and mesa II. The ratio is between 2:10 ⁇ 4:10.
  • the insufficient evaporation thickness of the interconnection strips on the side wall makes the interconnection strips very prone to cracks, resulting in an increase in the interconnection resistance between each sub-chip, and it is easy to burn the high-voltage diode under high current; or the interconnection strips are directly disconnected, and the high-voltage The LEDs are not functioning properly and will not glow properly.
  • the method of increasing the thickness of the interconnection structure is usually adopted.
  • the increase in the thickness of the interconnection structure will make the surface of the light-emitting diode uneven on the one hand, which will bring difficulties to the subsequent process; on the other hand, it will increase the thickness of the interconnection structure. manufacturing cost.
  • the present invention provides a high-voltage light-emitting diode, which can effectively improve the problem of poor coverage of the interconnection structure between adjacent sub-chips on the sidewalls of the mesas of the sub-chips.
  • This embodiment provides a high-voltage light-emitting diode, which includes a substrate and an LED chip unit formed on the substrate.
  • a substrate 110 of a high-voltage light-emitting diode and an LED chip unit 100 formed on the substrate are exemplarily shown, and two sub-chips 101 and 100 of the LED chip unit are exemplarily shown. 102.
  • several LED chip units 100 may be formed on the substrate 110, and each chip unit 100 may include several sub-chips.
  • each LED chip unit 100 includes a semiconductor light-emitting sequence layer 120 formed on a substrate 110.
  • the semiconductor light-emitting sequence layer 120 is a multi-layer structure, for example, at least including a first semiconductor layer 1201, The active layer 1202 and the second semiconductor layer 1203 .
  • the semiconductor light-emitting sequence layer 120 is obtained by MOCVD or other growth methods, and is a semiconductor material that can provide conventional radiation such as ultraviolet, blue, green, yellow, red, infrared light, etc., specifically, it can be 200nm ⁇ 950nm materials, such as common nitrides, specifically gallium nitride-based semiconductor epitaxial stacks, gallium nitride-based epitaxial stacks are often doped with elements such as aluminum and indium, and mainly provide radiation in the 200-550nm band; or common AlGaInP-based or AlGaAs-based semiconductor barrier stacks mainly provide radiation in the 550-950nm band.
  • the first semiconductor layer 1201 and the second semiconductor layer 1203 can be doped by n-type or p-type respectively so as to provide at least electrons or holes respectively.
  • the n-type semiconductor layer may be doped with an n-type dopant such as Si, Ge or Sn
  • the p-type semiconductor layer may be doped with a p-type dopant such as Mg, Zn, Ca, Sr or Ba.
  • the first semiconductor layer 1201, the active layer 1202, and the second semiconductor layer 1203 may specifically be made of aluminum gallium indium nitride, gallium nitride, aluminum gallium nitrogen, aluminum indium phosphide, aluminum gallium indium phosphide, or gallium arsenide or aluminum gallium arsenide.
  • the first semiconductor layer 1201 and the second semiconductor layer 1203 include a covering layer that provides electrons or holes, and may also include other material layers such as current spreading layers, window layers, or ohmic contact layers, etc., depending on the doping concentration or component content. Make settings for different layers.
  • the active layer 1202 is a region for recombination of electrons and holes to provide light radiation. Different materials can be selected according to different emission wavelengths.
  • the active layer 1202 can be a periodic structure of single quantum well or multiple quantum wells. By adjusting the composition ratio of the semiconductor material in the active layer 1202, it is desired to radiate light of different wavelengths.
  • the semiconductor light-emitting sequence layer 120 is formed of an AlGaInP-based material, and the thickness of the semiconductor light-emitting sequence layer 120 is 6 ⁇ m ⁇ 8 ⁇ m.
  • the above-mentioned semiconductor light-emitting sequence layer 120 may also be formed of a GaN-based material, and the thickness of the GaN-based semiconductor light-emitting sequence layer is between 4 ⁇ m and 6 ⁇ m; in another optional embodiment, the above-mentioned semiconductor light-emitting sequence layer
  • the sequence layer 120 can also be formed of a GaAs-based material, and the thickness of the GaAs-based semiconductor light-emitting sequence layer is between 6 ⁇ m and 8 ⁇ m.
  • an isolation groove 103 is formed between two adjacent sub-chips 101 and 102, and the isolation groove 103 extends through the above-mentioned semiconductor light emitting sequence layer 120 in the first direction, or further penetrates part of the substrate 110, so as to Two adjacent chiplets are separated.
  • the above-mentioned first direction may be the Y direction shown in FIG. 2 .
  • An insulating dielectric layer 130 is formed in the isolation trench to further realize the insulating interval between two adjacent sub-chips.
  • the semiconductor light-emitting epitaxial layer forms a mesa structure. As shown in FIGS.
  • the first semiconductor layer 1201 forms first mesas 1011 and 1021 .
  • the first mesa can be formed by etching the second semiconductor layer, the active layer and part of the first semiconductor layer of the semiconductor light emitting epitaxial layer.
  • the semiconductor light emitting sequence layer 120 other than the first mesa forms the second mesas 1012 and 1022 .
  • the isolation trench 103 is formed between the first mesa 1011 of the first chiplet 101 and the second mesa 1022 of the second chiplet 102 .
  • the sidewall of the second mesa may be formed as an inclined sidewall, specifically, for example, the angle between the sidewall of the second mesa and the surface of the first mesa is between 50°-70°.
  • the sidewall of the isolation trench 103 and the surface of the substrate 110 have an inclination angle ⁇ , that is, the sidewall of the first mesa 1011 of the first chiplet 101 and the side of the second mesa 1022 of the second chiplet 102
  • the wall and the surface of the substrate 110 have an inclination angle ⁇ .
  • the inclination angle ⁇ is approximately 60°-90°.
  • the isolation groove 1031 and the narrower second isolation groove 1032, the first isolation groove and the second isolation groove are continuous structures.
  • the width of the first isolation groove is between 10 ⁇ m ⁇ 50 ⁇ m
  • the width of the second isolation groove is between 3 ⁇ m ⁇ 10 ⁇ m.
  • the first isolation groove 1031 is located at the end of the isolation groove 103, and the first isolation groove 1031 is close to the dicing line between adjacent LED chip units (not detailed icon).
  • the probe when the chip is picked up in the subsequent die-bonding process, the probe will not touch the interconnection bar, and will not cause damage to the interconnection bar, thereby ensuring the reliability of the chip;
  • the above-mentioned first isolation trench is formed without losing or losing a very small light-emitting area, so as to ensure the light-emitting area of the chip.
  • the side wall extending and connecting the first isolation groove 1031 in the first direction is defined as the first side wall 1031-1 of the first isolation groove 1031; extending in the second direction
  • the side wall connected to the first side wall 1031 - 1 is the second side wall 1031 - 2 of the first isolation groove 1031 .
  • the first direction may be the X direction described in FIG. 2
  • the second direction is the Y direction perpendicular to the X direction.
  • the X and Y directions in FIG. 2 are merely exemplary first and second directions, and the first and second directions may be two directions that intersect but are not perpendicular.
  • the area where the first side wall 1031-1 is connected to the second side wall 1031-2 is formed as an arc-shaped area 1033, the area where the first side wall is connected to the second groove 1032, and the second side wall is formed in the first isolation groove.
  • the end portion can also be formed as an arc structure.
  • This structure makes the first trench take on a trumpet shape as a whole, so that the arc region 1033 can be completely exposed, and when the bridging structure is evaporated on the side wall of the first isolation groove, the evaporation gas can completely contact the arc region. 1033, thus improving the coverage uniformity and integrity of the bridge structure in the arc region, and improving the reliability of the bridge structure.
  • a bridging structure 104 is formed between the first sub-chip 101 and the second sub-chip 102 , and the bridging structure may be a metal conductive material, such as Au, Ag and other metals with good conductivity.
  • the bridging structures are conductively connected to the first semiconductor layer 1021 of the first chiplet 101 and the second semiconductor layer 1023 of the second chiplet 102 respectively, thereby realizing the series connection of the first chiplet and the second chiplet.
  • the bridge structure 104 is formed at the position where the first isolation groove 1031 and the second isolation groove 1032 are connected, and the bridge structure 104 covers the arc region 1033 of the first isolation groove 1031 .
  • the arc-shaped area 1033 increases the contact area between the bridge structure and the mesa of the sub-chip, so that the bridge structure 104 can cover the arc-shaped area 1033 well, and the stability of the bridge structure is increased without defects such as breakage or cracks. Due to the increased adhesion and uniformity of the bridge structure in the arc-shaped region, the difference between the thickness d1 of the bridge structure on the side wall of the isolation groove and the thickness d2 of the bridge structure above the mesa as shown in Figure 3b can be reduced, For example, as shown in FIG.
  • the ratio d1:d2 of the thickness d1 of the bridging structure on the sidewall of the isolation groove to the thickness d2 of the bridging structure above the mesa in this embodiment is between 6:10 and 10:10, thus it can be On the premise of ensuring the reliability of the bridge structure, the bridge structure can be made thinner. In addition, due to the enhanced adhesion between the bridge structure and the arc-shaped region 1033, the bridge structure can be made thinner. For example, in this embodiment, the thickness of the bridge structure can be controlled between 0.1 ⁇ m and 2 ⁇ m, thereby ensuring The manufacturing cost of the device is reduced under the premise of improving the device yield.
  • the LED chip unit further includes an electrode structure, specifically, including a second electrode 180 formed on the second mesa of the first sub-chip 101 and a first electrode 180 formed on the first mesa of the second sub-chip 102 .
  • electrode 190 is electrically connected to the first semiconductor layer
  • the second electrode 180 is electrically connected to the second semiconductor layer.
  • a transparent conductive layer 150 is further formed between the second electrode 180 and the second semiconductor layer 1203 , the transparent conductive layer may be an indium tin oxide layer, and may be used for current spreading.
  • a current blocking layer 170 is further formed at a position directly below the second electrode 180 .
  • An insulating protection layer 160 is also formed on the outermost side of the LED chip unit, for example, the insulating protection layer may be SiO 2 , Si 3 N 4 and the like.
  • Figure 4 shows the position of the electrode structure when there are two sub-chips. It should be understood that in an LED chip unit with more than two sub-chips, the electrode structures are respectively located on the starting sub-chip and the end sub-chip in the LED chip unit. .
  • This embodiment also provides a high-voltage light-emitting diode, which also includes a substrate and an LED chip unit formed on the substrate.
  • a high-voltage light-emitting diode which also includes a substrate and an LED chip unit formed on the substrate.
  • the first isolation groove 1031 of the isolation groove 103 is located away from the end of the isolation groove, that is, located in the middle area of the isolation groove.
  • the position of the first isolation groove can be selected according to actual needs.
  • the side wall connecting the first isolation groove 1031 to the second isolation groove 1032 is the first side wall
  • the side wall connected to the first side wall and away from the second isolation groove 1032 is the second side wall
  • the first side wall and the second isolation groove 1032 are connected to each other.
  • the junction of the side walls forms an arcuate area 1033 .
  • a bridging structure 104 is formed between the first sub-chip 101 and the second sub-chip 102 , and the bridging structure may be a metal conductive material, such as Au, Ag and other metals with good conductivity.
  • the bridging structures are conductively connected to the first semiconductor layer 1021 of the first chiplet 101 and the second semiconductor layer 1023 of the second chiplet 102 respectively, thereby realizing the series connection of the first chiplet and the second chiplet.
  • the bridge structure 104 is formed at the position where the first isolation groove 1031 and the second isolation groove 1032 are connected, and the bridge structure 104 covers the arc region 1033 of the first isolation groove 1031 .
  • the arc-shaped area 1033 increases the contact area between the bridge structure and the mesa of the sub-chip, so that the bridge structure 104 can cover the arc-shaped area 1033 well, and the stability of the bridge structure is increased without defects such as breakage or cracks.
  • the bridge structure can be made thinner.
  • the thickness of the bridge structure can be controlled between 0.1 ⁇ m and 2 ⁇ m, thereby ensuring The manufacturing cost of the device is reduced under the premise of improving the device yield.
  • the isolation trench of the present invention is especially suitable for high-voltage light-emitting diodes with a large thickness of semiconductor light-emitting epitaxial layer (such as 6 ⁇ m to 8 ⁇ m) and a large angle between the side wall of the isolation trench and the surface of the substrate (such as 60° to 90°). Applicable, the coverage area of the bridging structure on the side wall of the isolation groove can be increased, and the stability of the bridging structure can be improved.
  • the high-voltage light-emitting diode provided by the present invention has at least the following beneficial technical effects:
  • the isolation groove between adjacent sub-chips includes a first isolation groove and a second isolation groove, the first isolation groove and the second isolation groove are continuous structures, and the width of the first isolation groove is larger than The width of the second isolation slot.
  • An arc-shaped area is formed at a position where the first isolation groove is connected with the second isolation groove.
  • the bridge structure of the adjacent sub-chip covers the arc-shaped area, which increases the adhesion of the bridge structure and makes it cover the arc-shaped area, thereby ensuring the stability of the bridge structure and making it less prone to defects such as cracks or breaks , improve the reliability of the device.
  • the above-mentioned isolation groove structure is particularly suitable for the case where the thickness of the epitaxial layer is relatively large (for example, a red LED chip unit of 6 ⁇ m to 8 ⁇ m) and the sidewall inclination angle of the isolation groove is relatively large (for example, 60° to 90°), the isolation groove of the present invention Structures in particular can enhance the stability of bridging structures.
  • the thickness of the bridge structure can be controlled to be thin (for example, 0.1 ⁇ m ⁇ 2 ⁇ m). Therefore, on the one hand, the flatness of each plane of the device can be ensured, which facilitates the subsequent manufacturing process; on the other hand, the manufacturing cost of the device can be effectively reduced.
  • the above-mentioned wide first isolation groove can be formed adjacent to the dicing lines of adjacent LED chip units.
  • the formation of the first isolation groove adjacent to the dicing line can form the above-mentioned first isolation groove without losing or losing a very small light-emitting area, so as to ensure the light-emitting area of the chip.

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Abstract

本发明提供一种高压发光二极管，其中相邻的子芯片之间的隔离槽包括第一隔离槽和第二隔离槽，第一隔离槽的宽度大于第二隔离槽的宽度。隔离槽在第一方向上延伸，第一隔离槽在与所述第一方向相交的第二方向上延伸的侧壁为第一侧壁，在第一方向上延伸并且与第一侧壁连接的侧壁为第二侧壁，第一侧壁与第二侧壁相连的区域形成为弧形区域。相邻子芯片的桥接结构覆盖该弧形区域，增加了桥接结构的粘附性，使其包覆该弧形区域，由此可以保证桥接结构的稳定性，使其不易出现裂缝或者断裂等缺陷，提高器件的可靠性。上述隔离槽结构尤其在外延层厚度较大、外延层台面侧壁倾斜角较大的情况下，本发明的隔离槽结构尤其能够增强桥接结构的稳定性。

Description

一种高压发光二极管 技术领域
本发明涉及半导体器件领域，具体地，涉及一种高压发光二极管。
 背景技术
在高压发光二极管中，相邻的子芯片通过互连结构相互电连接。现有技术中，在互连结构蒸镀时，蒸镀蒸汽侧向沉积至相邻子芯片之间的隔离槽两侧的台面侧壁上。然而，当台面侧壁倾斜角较大时，蒸镀难度大，蒸镀厚度不足，互连结构容易产生裂缝，这就导致高压芯片各子芯片之间互连电阻大，大电流下容易使得发光二极管烧毁；或者会出现互连条直接断开的问题，发光二极管不能正常发光。
为了解决上述问题，有必要提供一种能够增加互连结构的稳定性及器件的可靠性的高压发光二极管。
 技术解决方案
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种高压发光二极管。通过改进发光二极管的LED芯片单元中相邻子芯片之间的隔离槽的结构，增加相邻子芯片之间的桥接结构在沟槽位置处的粘附性，使得桥接结构不易裂缝或者断裂，提高器件的稳定性。
为实现上述目的及其它相关目的，本发明提供了一种高压发光二极管，包括基板以及形成在所述基板上的LED芯片单元，所述LED芯片单元包括多个由隔离槽间隔的子芯片，相邻的所述子芯片通过桥接结构导电连接；所述隔离槽在第一方向上延伸，并且所述隔离槽包括第一隔离槽和第二隔离槽，其中所述第一隔离槽的宽度大于所述第二隔离槽的宽度，所述第一隔离槽在与所述第一方向相交的第二方向上延伸的侧壁为第一侧壁，在所述第一方向上延伸并且与所述第一侧壁连接的侧壁为第二侧壁，所述第一侧壁与所述第二侧壁相连的区域形成为弧形区域，所述桥接结构形成在所述隔离槽的表面及侧壁上，并且覆盖所述弧形区域。
可选地，所述LED芯片单元包括形成在所述基板上的半导体发光序列层，所述半导体发光序列层包括依次形成在所述基板上的第一半导体层、有源层及第二半导体层，所述发光序列层的厚度介于6 μm~8 μm。
可选地，所述隔离槽的侧壁与所述基板的表面之间的夹角介于60°~ 90°。
可选地，每一个所述子芯片中，所述半导体发光序列层中的部分第一半导体层形成第一台面，所述半导体发光序列层的第二半导体层形成第二台面，相邻的所述子芯片的第一台面和第二台面相邻，所述桥接结构形成在相邻的所述子芯片的第一台面和第二台面上。
可选地，所述第二台面的侧壁与第一台面的表面之间的夹角介于50°~ 70°。
可选地，所述隔离沟槽形成在相邻的所述子芯片的第一台面和第二台面之间，其中，所述第一隔离槽位于所述隔离槽的端部。
可选地，所述第一隔离沟槽的宽度介于10 μm~50μm。
可选地，所述第二隔离沟槽的宽度介于3μm ~10μm。
可选地，所述桥接结构包括金属导电层，所述金属导电层的厚度介于0.1 μm~2μm。
可选地，形成在所述隔离槽侧壁上的所述桥接结构的厚度为d1，形成在所述第一台面和所述第二台面上方的所述桥接结构的厚度为d2，d1∶d2介于6∶10~ 10∶10。
可选地，所述隔离沟槽中填充有绝缘介质层，所述桥接结构形成在所述绝缘介质层上方。
可选地，所述高压发光二极管为红光二极管。
可选地，还包括电极结构，所述电极结构设置在所述LED芯片单元的起始端的子芯片和最末端的子芯片的上方。
 有益效果
如上所述，本发明提供的高压发光二极管，至少具备如下有益技术效果：
本发明的高压发光二极管中，相邻的子芯片之间的隔离槽包括第一隔离槽和第二隔离槽，第一隔离槽和第二隔离槽为连续结构，并且第一隔离槽的宽度大于第二隔离槽的宽度。第一隔离槽与第二隔离槽连接的位置处形成弧形区域。相邻子芯片的桥接结构覆盖该弧形区域，增加了桥接结构的粘附性，使其包覆该弧形区域，由此可以保证桥接结构的稳定性，使其不易出现裂缝或者断裂等缺陷，提高器件的可靠性。上述隔离槽结构尤其在外延层厚度较大（例如6μm~8μm的红光LED芯片单元）、外延层台面侧壁倾斜角较大（例如60°~90°）的情况下，本发明的隔离槽结构尤其能够增强桥接结构的稳定性。
另外，由于弧形区域增加了桥接结构的粘附性及稳定性，因此可以控制桥接结构的厚度较薄（例如0.1 μm~2μm）。由此，一方面能够保证器件各个平面的平整度，便于后续制程；另一方面也可以有效降低器件的制造成本。
本发明中，上述较宽的第一隔离槽紧邻相邻LED芯片单元的切割道形成，一方面在后续固晶过程中拾取芯片时，探针不会碰到互联条，不会对互联条造成破坏，保证芯片的可靠性；另一方面，第一隔离槽紧邻切割道形成可以在不损失或者损失极小的发光面积的情况下形成上述第一隔离沟槽，保证芯片的出光面积。
 附图说明
图1a显示为传统高压LED芯片单元的结构示意图。
图1b显示为图1a所示的LED芯片的隔离槽的断面扫描图。
图2显示为本发明实施例一提供的高压发光二极管的LED芯片单元的结构示意图。
图3a显示为沿图2中线L-L的剖面图。
图3b显示为图3a中区域A的局部放大示意图。
图4显示为图2所示的LED芯片单元的立体示意图。
图5显示为在图2所示的LED芯片单元中形成桥接结构的示意图。
[根据细则91更正 26.10.2021]　
图6显示为本发明实施例二提供的高压发光二极管的LED芯片单元的结构示意图。
[根据细则91更正 26.10.2021]　
图7显示为在图6所示的LED芯片单元中形成桥接结构的示意图。
附图标记：
001高压发光二极管；011第一子芯片；012第二子芯片；013隔离槽；014互连条；100高压发光二极管；110基板；100 LED芯片单元；101第一子芯片；1011第一台面；1012第二台面；102第二子芯片；103隔离槽；1031第一隔离槽；1031-1第一侧壁；1031-2第二侧壁；1032第二隔离槽；1033弧形区域；104桥接结构；120半导体发光序列层；1201第一半导体层；1202有源层；1203第二半导体层；130绝缘介质层；150透明导电层；160绝缘保护层；170电流阻挡层；180第二电极；190第一电极。
 本发明的实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其它优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，虽图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的形态、数量、位置关系及比例可在实现本方技术方案的前提下随意改变，且其组件布局形态也可能更为复杂。
在高压发光二极管中，相邻的子芯片通过互连结构相互电连接。如图1a所示，示出了传统的高压发光二极管001，其中示例性示出该高压发光二极管001包括基板100以及形成在基板上的两个子芯片：第一子芯片011和第二子芯片012，两个子芯片通过隔离槽013相互间隔，隔离槽两侧为两个子芯片的台面I和台面II。互连条014形成在隔离槽两侧的台面I和台面II的表面及侧壁，实现两个子芯片的电连接。然而，如图1b所示，台面I和台面II与基板010之间的侧壁与基板的表面之间具有倾斜角α 1和α 2，并且倾斜角α 1和α 2均比较大，例如图1b所示的86.9° 及73.8°。当蒸镀蒸汽侧向沉积至隔离槽013两侧的台面I和台面II的侧壁时，上述大角度的倾斜角会使得蒸镀难度大，蒸镀厚度不足如图1b所示，在隔离槽的侧壁上，互连条厚度明显小于台面I和台面II上方的互连条的厚度，通常，隔离槽侧壁上的互连条的厚度与台面I和台面II上方的互连条的厚度比介于2：10~ 4:10。侧壁上的互连条蒸镀厚度不足使得互联条极易产生裂缝，导致每个子芯片之间的互连电阻变大，大电流下容易使得高压二极管烧毁；或者使得互联条直接断开，高压发光二极管无法正常工作，无法正常发光。为了解决上述问题，通常也会采用增加互连结构的厚度的方法，然而，互连结构厚度的增加，一方面会使得发光二极管的各表面高低不平，为后续制程带来困难；另一方会增加制造成本。
为了解决上述问题，本发明提供一种高压发光二极管，有效改善相邻子芯片之间的互连结构在子芯片的台面的侧壁覆盖不佳的问题。
实施例一
本实施例提供一种高压发光二极管，其包括基板以及形成在所述基板上的LED芯片单元。如图2所示，在本实施例中，示例性示出了高压发光二极管的基板110以及形成自基板上的一个LED芯片单元100，并且示例性示出了LED芯片单元的两个子芯片101和102，应该理解的是，基板110上可以形成若干个LED芯片单元100，每一个芯片单元100可以包括若干个子芯片。
如图3a所示，每一个LED芯片单元100均包括形成在基板110上的半导体发光序列层120，具体地，该半导体发光序列层120为多层结构，例如，至少包括第一半导体层1201、有源层1202及第二半导体层1203。
本实施例中，半导体发光序列层120通过MOCVD或其它的生长方式获得，为能够提供常规的如紫外、蓝、绿、黄、红、红外光等辐射的半导体材料，具体的可以是200nm ~950nm的材料，如常见的氮化物，具体的如氮化镓基半导体外延叠层，氮化镓基外延叠层常见有掺杂铝、铟等元素，主要提供200~550nm波段的辐射；或者常见的铝镓铟磷基或铝镓砷基半导体垒晶叠层，主要提供550~950nm波段的辐射。其中，第一半导体层1201和第二半导体层1203可分别通过n型掺杂或P型掺杂以实现至少分别提供电子或空穴。n型半导体层可以掺杂有诸如Si、Ge或者Sn的n型掺杂物，P型半导体层可以掺杂有诸如Mg、Zn、Ca、Sr或者Ba的P型掺杂物。第一半导体层1201、有源层1202及第二半导体层1203具体可以是铝镓铟氮、氮化镓、铝镓氮、铝铟磷、铝镓铟磷或砷化镓或铝镓砷等材料制作形成。第一半导体层1201和第二半导体层1203中包括提供电子或空穴的覆盖层，还可以包括其它材料层如电流扩展层、窗口层或欧姆接触层等，根据掺杂浓度或组分含量不同进行设置为不同的多层。有源层1202为提供电子和空穴复合提供光辐射的区域，根据发光波长的不同可选择不同的材料，有源层1202可以是单量子阱或多量子阱的周期性结构。通过调整有源层1202中半导体材料的组成比，以期望辐射出不同波长的光。
在本实施例中，优选半导体发光序列层120为AlGaInP基材料形成，该半导体发光序列层120的厚度为6 μm~8 μm。
在可选实施例中，上述半导体发光序列层120也可以由GaN基材料形成，该GaN基半导体发光序列层的厚度介于4 μm~6 μm；在另一可选实施例中，上述半导体发光序列层120还可以由GaAs基材料形成，该GaAs基半导体发光序列层的厚度介于6 μm~8 μm。
参照图2至图4，相邻的两个子芯片101及102之间形成隔离槽103，该隔离槽103在第一方向上延伸贯穿上述半导体发光序列层120，或者进一步贯穿部分基板110，以将相邻的两个子芯片分隔。上述第一方向可以是图2所示的Y方向。在隔离槽中形成有绝缘介质层130，进一步实现相邻的两个子芯片的绝缘间隔。另外，在每一个子芯片中，上述半导体发光外延层均形成台面结构。如图2和3所示，在第一子芯片101和第二子芯片102中，第一半导体层1201形成第一台面1011和1021。可以通过刻蚀半导体发光外延层的第二半导体层、有源层及部分第一半导体层形成该第一台面。该第一台面之外的半导体发光序列层120形成第二台面1012及1022。隔离槽103形成在第一子芯片101的第一台面1011和第二子芯片102的第二台面1022之间。在可选实施例中，第二台面的侧壁可以形成为倾斜侧壁，具体地，例如，第二台面的侧壁与第一台面的表面之间的夹角介于50°~ 70°。如图3a所示，隔离槽103的侧壁与基板110的表面具有一倾斜角α，即第一子芯片101的第一台面1011的侧壁和第二子芯片102的第二台面1022的侧壁与基板110的表面具有一倾斜角α。在可选实施例中该倾斜角α大约为60°~90°。
为了保证能够良好覆盖如此大角度倾斜的侧壁的桥接结构，如图2至图4所示，本实施例中，隔离槽103具有一加宽部，即，隔离槽103包括较宽的第一隔离槽1031和较窄的第二隔离槽1032，第一隔离槽和第二隔离槽为连续结构。在可选实施例中，第一隔离槽的宽度介于10 μm~50 μm，第二隔离槽的宽度介于3 μm~10 μm。如图2和图4所示，在本实施例中，第一隔离槽1031位于隔离槽103的端部，并且该第一隔离槽1031靠近相邻的LED芯片单元之间的切割道（未详细图示）。这样一方面在后续固晶过程中拾取芯片时，探针不会碰到互联条，不会对互联条造成破坏，保证芯片的可靠性；另一方面，第一隔离槽紧邻切割道形成可以在不损失或者损失极小的发光面积的情况下形成上述第一隔离沟槽，保证芯片的出光面积。
如图2所示，在本实施例中，定义第一隔离槽1031在与第一方向上延伸连接的侧壁为第一隔离槽1031的第一侧壁1031-1；在第二方向上延伸并且与该第一侧壁1031-1连接的侧壁为第一隔离槽1031的第二侧壁1031-2。其中，第一方向可以是图2中所述的X方向，第二方向为与X方向垂直的Y方向。应该可以理解的是，图2中X和Y方向仅仅是示例性的第一方向和第二方向，第一方向和第二方向可以是相交但是不垂直的两个方向。第一侧壁1031-1与第二侧壁1031-2相连的区域形成为弧形区域1033，第一侧壁和第二沟槽1032相连的区域，以及第二侧壁在第一隔离槽的端部同样也可以形成为弧形结构。该结构使得第一沟槽整体上呈现喇叭口形状，使得弧形区域1033能够完全暴露出来，后续在第一隔离槽侧壁上迎面蒸镀桥接结构时，能够使得蒸镀气体完全接触弧形区域1033，由此提高桥接结构在弧形区域的覆盖均匀性及完整性，提高桥接结构的可靠性。
如图5所示，在第一子芯片101和第二子芯片102之间形成桥接结构104，该桥接结构可以是金属导电材料，例如Au、Ag等导电性良好的金属。桥接结构分别与第一子芯片101的第一半导体层1021和第二子芯片102的第二半导体层1023导电连接，由此实现第一子芯片和第二子芯片的串联。形成上述桥接结构104时，采用侧面蒸镀工艺进行蒸镀，即相对第一隔离槽的第一侧壁进行迎面蒸镀。如图5所示，桥接结构104形成在第一隔离槽1031和第二隔离槽1032相连接的位置处，并且桥接结构104覆盖第一隔离槽1031的弧形区域1033。弧形区域1033增加了桥接结构与子芯片的台面的接触面积，使得桥接结构104能够很好地覆盖弧形区域1033，桥接结构稳定性增加，不会出现断裂或者裂缝等缺陷。由于弧形区域的桥接结构的粘附性及均匀性增加，因此可以缩小如图3b所示的隔离槽侧壁上的桥接结构的厚度d1及台面上方的桥接结构的厚度d2之间的差异，例如，如图3b所示，本实施例中隔离槽侧壁上的桥接结构的厚度d1与台面上方的桥接结构的厚度d2的比d1：d2介于6:10~ 10:10，由此可以做到在保证桥接结构的可靠性的前提下将桥接结构做到更薄。另外，由于桥接结构与弧形区域1033的粘附性增强，可以使得桥接结构做得更薄，例如本实施例中，桥接结构的厚度可以控制在0.1 μm~2μm之间，由此能够在保证器件良率的前提下降低器件的制造成本。
再次参照图4，LED芯片单元还包括电极结构，具体地，包括形成在第一子芯片101的第二台面上的第二电极180和形成在第二子芯片102的第一台面上的第一电极190。第一电极190与第一半导体层电连接，第二电极180与第二半导体层电连接。可选地，第二电极180与第二半导体层1203之间还形成有透明导电层150，该透明导电层可以是氧化铟锡层，可以用作电流扩展的作用。另外，在透明导电层150和第二半导体层1203之间，第二电极180正下方的位置处还形成有电流阻挡层170。LED芯片单元的最外侧还形成有绝缘保护层160，例如该绝缘保护层可以是SiO 2、Si 3N 4等。图4示出了两个子芯片时电极结构所在的位置，应该理解的是，在多于两个子芯片的LED芯片单元中，电极结构分别位于LED芯片单元中的起始子芯片和末端子芯片上。
实施例二
本实施例同样提供一种高压发光二极管，其同样包括基板以及形成在所述基板上的LED芯片单元。与实施例一提供的高压发光二极管的相同之处不再赘述，不同之处在于：
本实施例中，如图6所示，隔离槽103的第一隔离槽1031位于远离隔离槽端部的位置，即位于隔离槽的中间区域。本实施例中，第一隔离槽的位置可以根据实际需要选择。第一隔离槽1031与第二隔离槽1032连接的侧壁为第一侧壁，与第一侧壁连接且远离第二隔离槽1032的侧壁为第二侧壁，第一侧壁和第二侧壁的连接处形成弧形区域1033。
如图7所示，在第一子芯片101和第二子芯片102之间形成桥接结构104，该桥接结构可以是金属导电材料，例如Au、Ag等导电性良好的金属。桥接结构分别与第一子芯片101的第一半导体层1021和第二子芯片102的第二半导体层1023导电连接，由此实现第一子芯片和第二子芯片的串联。形成上述桥接结构104时，采用侧面蒸镀工艺进行蒸镀，即对第一隔离槽的第一侧壁进行迎面蒸镀。如图5所示，桥接结构104形成在第一隔离槽1031和第二隔离槽1032相连接的位置处，并且桥接结构104覆盖第一隔离槽1031的弧形区域1033。弧形区域1033增加了桥接结构与子芯片的台面的接触面积，使得桥接结构104能够很好地覆盖弧形区域1033，桥接结构稳定性增加，不会出现断裂或者裂缝等缺陷。另外，由于桥接结构与弧形区域1033的粘附性增强，可以使得桥接结构做得更薄，例如本实施例中，桥接结构的厚度可以控制在0.1 μm~2μm之间，由此能够在保证器件良率的前提下降低器件的制造成本。
本发明的隔离沟槽对于半导体发光外延层厚度较大（例如6 μm~8 μm）、隔离槽侧壁与基板表面之间的夹角较大（例如60°~90°）的高压发光二极管尤其适用，可以增大桥接结构在隔离槽侧壁上的覆盖面积，提高桥接结构的稳定性。
如上所述，本发明提供的高压发光二极管，至少具备如下有益技术效果：
本发明的高压发光二极管中，相邻的子芯片之间的隔离槽包括第一隔离槽和第二隔离槽，第一隔离槽和第二隔离槽为连续结构，并且第一隔离槽的宽度大于第二隔离槽的宽度。第一隔离槽与第二隔离槽连接的位置处形成弧形区域。相邻子芯片的桥接结构覆盖该弧形区域，增加了桥接结构的粘附性，使其包覆该弧形区域，由此可以保证桥接结构的稳定性，使其不易出现裂缝或者断裂等缺陷，提高器件的可靠性。上述隔离槽结构尤其在外延层厚度较大（例如6μm~8μm的红光LED芯片单元）、隔离槽的侧壁倾斜角较大（例如60°~90°）的情况下，本发明的隔离槽结构尤其能够增强桥接结构的稳定性。
另外，由于弧形区域增加了桥接结构的粘附性及稳定性，因此可以控制桥接结构的厚度较薄（例如0.1 μm~2μm）。由此，一方面能够保证器件各个平面的平整度，便于后续制程；另一方面也可以有效降低器件的制造成本。
本发明中，上述较宽的第一隔离槽可以紧邻相邻LED芯片单元的切割道形成，一方面在后续固晶过程中拾取芯片时，探针不会碰到互联条，不会对互联条造成破坏，保证芯片的可靠性；另一方面，第一隔离槽紧邻切割道形成可以在不损失或者损失极小的发光面积的情况下形成上述第一隔离沟槽，保证芯片的出光面积。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (13)

  1. 一种高压发光二极管，包括基板以及形成在所述基板上的LED芯片单元，所述LED芯片单元包括多个由隔离槽间隔的子芯片，相邻的所述子芯片通过桥接结构导电连接；其特征在于，
    所述隔离槽在第一方向上延伸，并且所述隔离槽包括第一隔离槽和第二隔离槽，其中所述第一隔离槽的宽度大于所述第二隔离槽的宽度，所述第一隔离槽在与所述第一方向相交的第二方向上延伸的侧壁为第一侧壁，在所述第一方向上延伸并且与所述第一侧壁连接的侧壁为第二侧壁，所述第一侧壁与所述第二侧壁相连的区域为弧形区域，所述桥接结构形成在所述隔离槽的表面及侧壁上，并且覆盖所述弧形区域。
  2. 根据权利要求1所述的高压发光二极管，其特征在于，所述LED芯片单元包括形成在所述基板上的半导体发光序列层，所述半导体发光序列层包括依次形成在所述基板上的第一半导体层、有源层及第二半导体层，所述发光序列层的厚度介于6μm~8μm。
  3. 根据权利要求1所述的高压发光二极管，其特征在于，所述隔离槽的侧壁与所述基板的表面之间的夹角介于60°~90°。
  4. 根据权利要求1所述的高压发光二极管，其特征在于，每一个所述子芯片中，所述半导体发光序列层中的部分第一半导体层形成第一台面，所述半导体发光序列层的第二半导体层形成第二台面，相邻的所述子芯片的第一台面和第二台面相邻，所述桥接结构形成在相邻的所述子芯片的第一台面和第二台面上。
  5. 根据权利要求4所述的高压发光二极管，其特征在于，所述第一台面和所述第二台面的侧壁与所述第一台面的表面之间的夹角介于50°~ 70°。
  6. 根据权利要求4所述的高压发光二极管，其特征在于，所述隔离槽形成在相邻的所述子芯片的第一台面和第二台面之间，其中所述第一隔离槽位于所述隔离槽的端部。
  7. 根据权利要求1所述的高压发光二极管，其特征在于，所述第一隔离沟槽的宽度介于10 μm~50μm。
  8. 根据权利要求1所述的高压发光二极管，其特征在于，所述第二隔离沟槽的宽度介于3μm~10μm。
  9. 根据权利要求1所述的高压发光二极管，其特征在于，所述桥接结构包括金属导电层，所述金属导电层的厚度介于0.1 μm~2μm。
  10. 根据权利要求4所述的高压发光二极管，其特征在于，形成在所述隔离槽侧壁上的所述桥接结构的厚度为d1，形成在所述第一台面和所述第二台面上方的所述桥接结构的厚度为d2，d1∶d2介于6∶10~ 10∶10。
  11. 根据权利要求1所述的高压发光二极管，其特征在于，所述隔离沟槽中填充有绝缘介质层，所述桥接结构形成在所述绝缘介质层上方。
  12. 根据权利要求1所述的高压发光二极管，其特征在于，所述高压发光二极管为红光二极管。
  13. 根据权利要求1所述的高压发光二极管，其特征在于，还包括电极结构，所述电极结构设置在所述LED芯片单元的起始端的子芯片和最末端的子芯片的上方。
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