WO2023246160A1 - 电路板、电路板组件 - Google Patents

电路板、电路板组件 Download PDF

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Publication number
WO2023246160A1
WO2023246160A1 PCT/CN2023/079007 CN2023079007W WO2023246160A1 WO 2023246160 A1 WO2023246160 A1 WO 2023246160A1 CN 2023079007 W CN2023079007 W CN 2023079007W WO 2023246160 A1 WO2023246160 A1 WO 2023246160A1
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WO
WIPO (PCT)
Prior art keywords
array
offset
hole
holes
circuit board
Prior art date
Application number
PCT/CN2023/079007
Other languages
English (en)
French (fr)
Inventor
张红艳
Original Assignee
中兴通讯股份有限公司
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Filing date
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Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2023246160A1 publication Critical patent/WO2023246160A1/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components

Definitions

  • the present disclosure relates to, but is not limited to, the field of circuit board technology.
  • connection points for connecting to other structures.
  • some connection points may have to be arranged in an array.
  • the pads on the circuit board used to connect to the ball grid array (BGA, Ball Grid Array) package chip must be arranged in an array corresponding to the ball grid array. Therefore, the vias (BGA vias) connected to the above pads (connection points) should also be arranged in the same array (but the entire array can be offset relative to the array of pads).
  • the positions of the above vias are fixed, so the spacing between adjacent vias is also fixed. Therefore, the number of leads that can be arranged between adjacent vias is limited, resulting in a reduction in the density of the circuit board and an increase in the number of layers. Increased costs.
  • the present disclosure provides a circuit board and a circuit board assembly.
  • the present disclosure provides a circuit board, including a plurality of array connection points arranged in a connection point array, and a plurality of array holes arranged in a hole array, at least part of the array connection points and at least one of the array holes.
  • a standard array and a virtual array with the same structure are defined in the circuit board, and the corresponding structural directions in the standard array and the virtual array are parallel to each other; each array connection point is located in its corresponding position in the standard array standard points; the hole array includes a plurality of standard array holes and at least one offset array hole; each of the standard array holes is located at its corresponding virtual point in the virtual array; each of the offset array holes The first side is adjacent to the first lead, and the offset array hole is offset by a first predetermined distance to the second side relative to its corresponding virtual point in the virtual array, and the second side is the opposite side to the first side. .
  • the present disclosure provides a circuit board assembly, which includes: any circuit board provided by the present disclosure; electronic devices provided on the circuit board, at least part of the electronic devices are electrically connected to the array connection points.
  • Figure 1 is a schematic diagram of the positional relationship between array connection points and points in a circuit board provided by the present disclosure
  • Figure 2 is a schematic diagram of the positional relationship between array connection points and points in another circuit board provided by the present disclosure
  • Figure 3 is a schematic diagram of the positional relationship between array holes and leads in a circuit board provided by the present disclosure
  • Figure 4 is a schematic diagram of the positional relationship between array holes and leads in another circuit board provided by the present disclosure
  • Figure 5 is a partial cross-sectional structural diagram of the back drilling as an offset array hole in a circuit board provided by the present disclosure
  • Figure 6 is a schematic diagram of the positional relationship between the array connection points and the array holes in the circuit board of Figure 1;
  • Figure 7 is a schematic diagram of the positional relationship between the array connection points and the array holes in the circuit board of Figure 2;
  • Figure 8 is a schematic diagram of the size relationship between array holes and leads in a circuit board provided by the present disclosure.
  • Figure 9 is a block diagram of a circuit board assembly provided by the present disclosure.
  • plan and/or cross-sectional illustrations are schematic illustrations of the disclosure. Accordingly, example illustrations may be modified based on manufacturing techniques and/or tolerances.
  • the present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of configurations based on manufacturing processes. Accordingly, the regions illustrated in the figures are of a schematic nature and the shapes of the regions shown in the figures are illustrative of the specific shapes of regions of the element and are not intended to be limiting.
  • the present disclosure provides a circuit board.
  • a circuit board (PCB, Print Circuit Board) is also called a “printed circuit board”, “circuit board”, etc. It can include multiple layers, each layer is provided with some leads, and the leads can be electrically connected to other layers through holes. Thus, when electronic components are disposed on the circuit board, each electronic component can be electrically connected in a desired relationship through the leads.
  • the circuit board of the present disclosure includes a plurality of arrays arranged in an array of connection points.
  • a standard array and a virtual array with the same structure are defined in the circuit board, and the standard array and the virtual array
  • the corresponding structural directions in the standard array are parallel to each other; each array connection point 1 is located at its corresponding standard point 21 in the standard array;
  • the hole array includes a plurality of standard array holes 31 and at least one offset array hole 32; each standard array
  • the hole 31 is located at its corresponding virtual point 23 in the virtual array;
  • the first side of each offset array hole 32 is adjacent to the first lead 41, and the offset array hole 32 is relative to its corresponding virtual point 23 in the virtual array. Offset by a first predetermined distance to a second side, the second side being an opposite side to the first side.
  • the circuit board of the present disclosure includes a plurality of array connection points 1 arranged in a connection point array and a plurality of array holes arranged in a hole array.
  • the array connection point 1 is a structure used for electrical connection with other structures (such as electronic devices), and is usually located on the surface of the circuit board.
  • the array connection point 1 may be a pad provided on the surface of the circuit board.
  • Array holes are hole structures in circuit boards (such as blind holes, through holes, etc.). Conductive materials are formed in the holes to achieve signal transmission between different layer structures.
  • a standard array and a virtual array are also defined in the circuit board.
  • the standard array is a complete array composed of multiple standard points 21; in the plane position, each array connection point 1 is arranged on the standard point 21 of the standard array, that is, the connection point array is a standard array At least part of it.
  • connection point 1 must be located at the standard point 21, it does not mean that there must be an array connection point 1 at every standard point 21. That is, the connection point array may not be the standard array. All points of the standard array are "full”, and some positions of the standard array may be "vacant”, which is set according to the form of other structures connected to the array connection point 1 as needed.
  • the virtual array is a complete array composed of multiple virtual points 23, and its structure is the same as the standard array, that is, the number, spacing, relative position, etc. of the points in the virtual array and the standard array are the same; and, the standard array
  • the corresponding structural directions in the array and the virtual array are parallel to each other. For example, when both have "rows", the "row directions" of the two are parallel to each other.
  • the virtual array and the standard array overlap each other; you can also refer to Figure 1. 2.
  • the virtual array is "translated (without rotation)" by a certain distance relative to the standard array as a whole.
  • each array hole corresponds to a virtual point 23 of the virtual array, and is "substantially" located at the virtual point 23 .
  • the array holes are divided into two types, standard array holes 31 and offset array holes 32. 3 and 4, the standard array hole 31 is located at its corresponding virtual point 23; and the first side of the offset array hole 32 is provided with an adjacent first lead 41 (ie, the offset array hole 32 There are no other leads, holes or other structures between the first lead 41 and the first lead 41), and the offset array hole 32 is not exactly located at its corresponding virtual point 23, but is located at a second point away from the first lead 41 relative to the virtual point 23. The side is offset by a first predetermined distance.
  • the description that the standard array hole 31 is located at the virtual point 23 does not mean that the standard array hole 31 and the virtual point 23 "absolutely" coincide, but as long as the purpose is to hope that the standard array hole 31 is located at the virtual point 23, then Small positional offsets (such as offsets that are significantly smaller than the first predetermined distance) are allowed.
  • the above first predetermined distance should be very small, for example, no more than one-fifth of the distance between adjacent virtual points 23 .
  • each offset array hole 32 has a respective first lead 41 and a first side, that is, different offset array holes 32 may be directed to different first leads 41 to different second sides. Offset; for a lead, some of the array holes adjacent to it may be the first leads 41 but offset array holes 32, while the other part of the array holes adjacent to it may not be the first leads but standard arrays. Hole 31.
  • each array hole must correspond to the virtual point 23 (located at the virtual point 23 or offset from the virtual point 23 by a first predetermined distance), but this does not mean that each virtual point 23 has a corresponding array.
  • the holes, that is, the hole array may not "fill up” all the points in the virtual array, and some positions in the virtual array may be "vacant".
  • the array holes are "wholly” arranged in the same hole array as the connection point array (but the positions do not necessarily coincide with each other), but some of the offset array holes 32 adjacent to the first lead 41 are The relative virtual point 23 is slightly away from the first lead 41 , thereby increasing the distance from the first lead 41 .
  • the standard point 21 corresponds to the virtual point 23 one-to-one, but the array connection point 1 does not correspond to the standard point 21 one-to-one, and the array hole does not correspond to the virtual point. 23 correspond one to one, so there is no necessary correspondence between the array connection point 1 and the array hole, that is, the number and relative position of the two can be different.
  • the array connection points 1 are electrically connected to one or more array holes to transmit signals to each other.
  • each array connection point 1 corresponds to and is electrically connected to an array hole.
  • the array connection point 1 may not be electrically connected to the array hole corresponding to the position, but to other array holes around the array hole corresponding to the position.
  • Array connection point 1 can also be electrically connected to the array hole on the lower left side of it.
  • some array connection points 1 may not be electrically connected to the array holes, or one array connection point 1 may be electrically connected to multiple array holes, or one array hole may be electrically connected to multiple array connection points 1. Or some of the array holes are not electrically connected to the array connection point 1, etc.
  • connection points may also be other connection points besides the array connection point 1 and other holes than the array holes, which will not be described in detail here.
  • the array connection points 1 are arranged into a connection point array, and the array holes are arranged into a hole array, and the hole array is "wholly" in the same form as the connection point array, so that the electrical connection between the array holes and the array connection points 1 can be realized ;
  • the offset array holes 32 in the hole array adjacent to the first lead 41 are slightly offset in the direction away from the first lead 41, so that the distance between them and the first lead 41 increases, causing the adjacent array holes to
  • the number of leads that can be set between them increases, which increases the density of the circuit board, reduces the number of layers required for the circuit board, and reduces its manufacturing cost.
  • the hole array includes multiple rows and multiple columns; each first lead 41 is provided between two adjacent columns of array holes.
  • each array hole can be arranged in multiple rows and columns, and the first leads 41 of all offset array holes 32 are in adjacent "two columns" extending between array holes.
  • the standard array is a matrix, and the rows and columns of the matrix are perpendicular to each other.
  • the above rows and columns can be perpendicular to each other, so that the standard array is in a "matrix” form.
  • the virtual array is also in a "matrix” form.
  • array connection point 1 is a pad for connection to a ball grid array.
  • the array connection point 1 is a pad used to connect to a ball grid array (BGA, Ball Grid Array) packaged chip, that is, each pad is used to connect to one pin in the BGA of the BGA packaged chip.
  • the pins are connected to the solder balls, and the corresponding array holes are "BGA vias", which are used to transmit signals from the BGA package chip.
  • At least some of the virtual points 23 corresponding to the array holes are the positions of the pads, and the first predetermined distance is less than the sum of the pad radius and the array hole radius; at least some of the array holes are coincident with the pads. Electrical connection.
  • the virtual point 23 corresponding to the array hole can be the location of its electrically connected pad (also the array connection point 1 and the standard point 21), that is, the virtual array and the standard point 21 are located.
  • the arrays overlap, that is, the POFV (Plated over Filled Via) design is used.
  • the standard array hole 31 is located at its corresponding pad and can be directly electrically connected to the pad; while the offset array hole 32 is offset by a first predetermined distance relative to the virtual point 23 (that is, the pad), but Since the first predetermined distance is smaller than the sum of the radius of the pad and the radius of the array hole, the offset array hole 32 still at least partially overlaps with the pad after offset and can be directly electrically connected.
  • At least some of the virtual points 23 corresponding to the array holes are offset by a second predetermined distance relative to the position of the pad, and the second predetermined distance is greater than the sum of the pad radius and the array hole radius; at least some of the array holes It is electrically connected to the pad through connecting leads 43 .
  • Two predetermined distances, and the second predetermined distance is greater than the sum of the pad radius and the array hole radius, so the pad (also the array connection point 1 and the standard point 21) does not directly coincide with the array hole, but needs to be connected through the connecting lead 43 Electrical connection (as before, the connection relationship between the pad and the array hole is not limited to the form of Figure 7).
  • the positional shift of the offset array hole 32 is equivalent to a change in the position of one end of the connecting lead 43. Therefore, the length and angle of the connecting lead 43 connected to the offset array hole 32 are different from those connected to the standard array hole 31.
  • the lengths and angles of the leads 43 will be slightly different (some connecting leads 43 are shorter in length, and some are longer in length), but because the above differences are very small, they will not have a substantial impact on the corresponding signal transmission.
  • the array connection point 1 is not limited to the form of the above pad.
  • the array connection point 1 can also be used to connect to an array of pins in other electronic devices.
  • At least a portion of the offset array holes 32 are back drilled.
  • the offset array holes 32 may be back-drilled (ie, holes with a back-drilling process on the back). Referring to FIG. 5 , the hole diameter will increase during the back-drilling process, resulting in the same position. , compared with other holes, the distance between the back drilling and adjacent leads will be smaller, and it is easier to exceed the process capability or cause defects, so the back drilling can be used as the offset array hole 32.
  • the hole array includes at least one offset hole group; each offset hole group includes two adjacent offset array holes 32, wherein the first side of any offset array hole 32 is aligned with the other offset hole group.
  • the offset array holes 32 are adjacent; the two offset array holes 32 in each pair of adjacent offset array holes are back drilled holes.
  • both of them can be offset array holes 32 (viewed as as an offset hole group), and are respectively offset in opposite directions (that is, the first sides of the two offset array holes 32 are opposite, and the second sides are opposite).
  • the distance between them must be smaller, so both of them can be offset from the array holes 32 to maximize the distance between them.
  • offset array holes 32 can be back-drilled holes does not mean that all back-drilled holes must be offset array holes. That is, for each back-drilled hole, whether it is an offset array hole can be selected as needed.
  • the holes that can be used as the offset array holes 32 are not limited to the form of back drilling.
  • blind holes, deep V holes, other via holes, etc. can also be used as the offset array holes 32 .
  • the relationship between the back drilling and the offset array holes 32 is not limited to the above specific examples.
  • only one of them can be an offset array hole 32, or neither of them can be an offset array hole 32; for another example, it can also be done between two adjacent back-drilled holes.
  • the array holes with leads between them when only one is a back-drilled hole (i.e., a single-side back-drilled hole), the back-drilled hole is used as the offset array hole 32; for another example, it can also be a back-drilled hole other than a back-drilled hole.
  • the other array holes serve as offset array holes 32.
  • At least part of the first leads 41 are differential lines.
  • the first leads 41 corresponding to the offset array holes 32 may be differential lines for transmitting differential signals (the holes electrically connected thereto are high-speed signal holes).
  • Differential signals are usually high-frequency signals and are more likely to interfere with other structures, so the distance from other structures should be larger; moreover, differential lines must be "paired", and a pair of differential lines is best located adjacent to each other.
  • the array holes are used to increase the density of the circuit board and reduce the number of layers and costs. Therefore, the wiring space of differential lines is often more compact, and it is necessary to increase the wiring space in some ways.
  • the first lead 41 is not limited to the above form.
  • the array holes may also include offset array holes 32; for another example, other leads (such as ground lines GND, etc.) may also be used as the first lead. 41.
  • At least a portion of the second side of the offset array aperture 32 is adjacent a second lead 42 that extends perpendicular to a direction from the first side toward the second side, and the second lead 42 is in A bent structure 421 is formed adjacent to the offset array hole 32 and protrudes in a direction away from the offset array hole 32 .
  • adjacent leads may also be provided on the second side of the offset array hole 32 , and the overall extension direction of the second leads 42 is perpendicular to the direction from the first side to the second side (such as column direction).
  • the offset array holes 32 are offset to the second side (eg, offset along the row direction), the distance between the offset array holes 32 and the second leads 42 is smaller than the standard array holes 31 (eg, the standard array holes 31 in the same row). will become smaller.
  • the second lead 42 can be in a part corresponding to the offset array hole 32 The position is bent toward the side away from the offset array hole 32 (that is, a bent structure 421 is formed).
  • each offset array hole 32 has a corresponding second lead 42 , and each lead may simultaneously serve as the second lead 42 of multiple offset array holes 32 , and the first side of the offset array hole 32 has different
  • the direction may be different. Therefore, referring to FIG. 3 , the specific bending direction of the bending structure 421 may be different.
  • the hole array includes at least one offset hole group; each offset hole group includes two adjacent offset array holes 32, wherein the first side of any offset array hole 32 is aligned with the other offset hole group.
  • the shifting array holes 32 are adjacent to each other.
  • some adjacent array holes with leads between them can be offset array holes 32 at the same time (such as back drilling at the same time), and are offset in a direction away from each other ( That is, the first sides of two adjacent offset array holes 32 are opposite and the second sides are opposite).
  • a lead is provided between at least part of the adjacent offset array holes 32, and the lead is simultaneously the first lead 41 of the two offset array holes 32; and/or, at least part of the adjacent offset array holes 32 are connected.
  • Two leads are provided between the shift array holes 32 , and the two leads are respectively the first leads 41 of the two offset array holes 32 .
  • the specific forms of the leads and array holes are not limited to the above specific forms.
  • only some of the array holes may be offset array holes 32 (for example, only back drilling is the offset array hole 32), or None of the array holes may be offset array holes; for another example, referring to FIG. 4 , when the offset array holes 32 have adjacent leads, the leads may not be bent (that is, not the second leads), etc.
  • the first predetermined distance by which the offset array holes 32 are offset can be selected according to the drilling capability size range (the distance range between the holes and adjacent leads that can ensure that no defects will occur after drilling).
  • the two adjacent array holes are offset array holes 32 (so the two leads are both first leads 41), and each offset array hole
  • the second side of the hole is the bent structure 421 of the two second leads 42 and a standard array hole 31 (taking the offset array hole 32 on the left side in FIG. 8 as an example)
  • D is the spacing between adjacent virtual points 23 along the row direction
  • d is the first predetermined distance of the offset array hole 32 along the row direction
  • w is the line width of the lead
  • s is the line width of two adjacent virtual points.
  • the spacing of the leads along the row direction d1 is the spacing between the standard array hole 31 and the adjacent leads along the row direction
  • Rp is the radius of the array hole
  • d2 is the spacing between the offset array holes 32 and the adjacent leads along the row direction.
  • the distance D between different virtual points 23 must be the same. From the perspective of signal uniformity, the specific sizes of all other identical parameters should also be as equal as possible (such as the offset array hole 32 and the first The value of the distance d2 between the first lead 41 and the second lead 42 should be the same). Therefore, the values of parameters with the same sign in the above formula (1) and formula (2) are equal, so subtracting the formula (1) from the above formula (2), we can get the offset in the case of referring to Figure 8
  • d1 and d2 should be within the drilling capacity (primary drilling capacity, secondary drilling capacity) size range of the standard array hole 31 (such as non-back drilling) and the offset array hole 32 (such as back drilling) respectively. selection (otherwise defects may occur), and after selecting d1 and d2, the first predetermined distance d for the offset of the offset array holes 32 can be obtained according to the above formula.
  • the various dimensions are not limited to the above specific examples.
  • the distance d2 between the offset array hole 32 and the leads on both sides may be different.
  • each figure The leads in may actually be in the inner layer of the circuit board (for example, refer to Figure 5), so they are not directly visible when viewed from above (but they are shown in the figure); for another example, the leads in each drawing may be reference Figure 3 is connected to the array hole and implements signal transmission with the array connection point 1, or the lead can just "pass" the area of the array hole without connecting the array hole.
  • the circuit board can include two layers.
  • the upper layer realizes the wires out of the outer two circles of the BGA matrix, and the lower layer
  • One layer realizes the outlet of the inner two turns of the BGA, and the leads of the outer two turns are back-drilled at the lead layers of the high-speed lines of the inner two turns.
  • the lead channel can be enlarged and more leads can be passed through the offset of the array holes.
  • the spacing between the array holes in the first and second rows is 1mm, and one lead is passed through; the spacing between the array holes in the second and third rows is 1mm, and two leads are passed through; the arrays in the third and fourth rows are The spacing between the holes is 1.2mm, and three leads are passed through; the spacing between the fourth and fifth row array holes is 0.8mm, and one lead is passed through.
  • the offset array holes in the fourth row are shifted downward by 0.2mm, causing the spacing between the array holes in the third and fourth rows to increase to 1.2mm, and the spacing between the array holes in the fourth and fifth rows to shrink to 0.8mm.
  • the lead channel can be enlarged and more leads can be passed through the offset of the array holes.
  • the spacing between the holes in each row of the two columns on the left is 0.8mm.
  • the spacing between the array holes in the first and second rows is 0.8mm, and one lead is passed through;
  • the array holes in the second and third rows are The spacing between the array holes in the third row and the fourth row is 0.76mm, and one lead wire is passed through it;
  • the spacing between the array holes in the third and fourth rows is 0.96mm, and two leads are passed through;
  • the spacing between the array holes in the fourth and fifth rows is 0.76mm, and one lead wire is passed through lead;
  • the spacing between the array holes in the fifth and sixth rows is 0.76mm, and one lead is passed through;
  • the spacing between the array holes in the sixth and seventh rows is 0.76mm, and one lead is passed through; starting from the third row Set the offset array holes to adjust the spacing; therefore, whether it is the left two columns or the right columns of array holes, the hole spacing from the second row to the seventh row is 4mm. It can be seen that the ratio of leads passing through the right side of the same distance is One more one on the left.
  • the present disclosure provides a circuit board assembly, which includes: any circuit board according to the embodiment of the present disclosure; electronic devices provided on the circuit board, at least some of the electronic devices are electrically connected to the array connection points .
  • Corresponding electronic devices can be disposed on the above circuit board to form a circuit board assembly (or a circuit board with relatively complete functions); at least some of the electronic devices are electrically connected to the array connection points of the circuit board.
  • the electronic device may include a BGA package chip, and the BGA package chip is connected to the circuit board through an array of connection points (pads).
  • the BGA package chip is connected to the circuit board through an array of connection points (pads).

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  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

本公开提供了一种电路板，其包括多个排成连接点阵列的阵列连接点，以及多个排成孔阵列的阵列孔，至少部分所述阵列连接点与至少一个所述阵列孔电连接；所述电路板中定义有结构相同的标准阵列和虚拟阵列，且所述标准阵列与虚拟阵列中相对应的结构方向相互平行；每个所述阵列连接点均位于标准阵列中其对应的标准点位；孔阵列包括多个标准阵列孔和至少一个偏移阵列孔；每个所述标准阵列孔位于虚拟阵列中其对应的虚拟点位；每个所述偏移阵列孔的第一侧与第一引线相邻，且所述偏移阵列孔相对虚拟阵列中其对应的虚拟点位向第二侧偏移第一预定距离，所述第二侧为第一侧的相对侧。

Description

电路板、电路板组件
相关申请的交叉引用
本申请要求2022年6月21日提交给中国专利局的第202210705661.9号专利申请的优先权，其全部内容通过引用合并于此。
技术领域
本公开涉及但不限于电路板技术领域。
背景技术
电路板(PCB，Print Circuit Board)中设有用于与其它结构连接的连接点，在一些情况下，部分连接点可能必须排成阵列形式。例如，电路板上用于与球栅阵列(BGA，Ball Grid Array)封装芯片连接的焊盘就必须排成与球栅阵列对应的阵列。由此，与以上焊盘(连接点)相连的过孔(BGA过孔)也应排成相同形式阵列(但该阵列整体可相对焊盘的阵列偏移)。
也就是说，以上过孔的位置是固定的，故相邻过孔间的间距也固定，由此相邻过孔间能布置的引线数量受限，导致电路板的密度降低，层数增多，成本提高。
发明内容
本公开提供一种电路板、电路板组件。
第一方面，本公开提供一种电路板，包括多个排成连接点阵列的阵列连接点，以及多个排成孔阵列的阵列孔，至少部分所述阵列连接点与至少一个所述阵列孔电连接；所述电路板中定义有结构相同的标准阵列和虚拟阵列，且所述标准阵列与虚拟阵列中相对应的结构方向相互平行；每个所述阵列连接点均位于标准阵列中其对应的标准点位；孔阵列包括多个标准阵列孔和至少一个偏移阵列孔；每个所述标准阵列孔位于虚拟阵列中其对应的虚拟点位；每个所述偏移阵列孔的 第一侧与第一引线相邻，且所述偏移阵列孔相对虚拟阵列中其对应的虚拟点位向第二侧偏移第一预定距离，所述第二侧为第一侧的相对侧。
第二方面，本公开提供一种电路板组件，其包括：本公开提供的任意一种电路板；设于所述电路板上的电子器件，至少部分所述电子器件与阵列连接点电连接。
附图说明
图1为本公开提供的一种电路板中阵列连接点和点位的位置关系示意图；
图2为本公开提供的另一种电路板中阵列连接点和点位的位置关系示意图；
图3为本公开提供的一种电路板中阵列孔和引线的位置关系示意图；
图4为本公开提供的另一种电路板中阵列孔和引线的位置关系示意图；
图5为本公开提供的一种电路板中作为偏移阵列孔的背钻孔处的局部剖面结构示意图；
图6为图1的电路板中阵列连接点和阵列孔的位置关系示意图；
图7为图2的电路板中阵列连接点和阵列孔的位置关系示意图；
图8为本公开提供的一种电路板中阵列孔和引线的尺寸关系示意图；
图9为本公开提供的一种电路板组件的组成框图；
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开实施方式提供的电路板、电路板组件进行详细描述。
在下文中将参考附图更充分地描述本公开，但是所示的实施方式可以以不同形式来体现，且本公开不应当被解释为限于以下阐述的实施方式。反之，提供这些实施方式的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。
本公开实施方式的附图用来提供对本公开实施方式的进一步理解，并且构成说明书的一部分，与详细实施方式一起用于解释本公开，并不构成对本公开的限制。通过参考附图对详细实施方式进行描述，以上和其它特征和优点对本领域技术人员将变得更加显而易见。
本公开可借助本公开的理想示意图而参考平面图和/或截面图进行描述。因此，可根据制造技术和/或容限来修改示例图示。
在不冲突的情况下，本公开各实施方式及实施方式中的各特征可相互组合。
本公开所使用的术语仅用于描述特定实施方式，且不意欲限制本公开。如本公开所使用的术语“和/或”包括一个或多个相关列举条目的任何和所有组合。如本公开所使用的单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。如本公开所使用的术语“包括”、“由……制成”，指定存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件和/或其群组。
除非另外限定，否则本公开所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本公开明确如此限定。
本公开不限于附图中所示的实施方式，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了元件的区的具体形状，但并不是旨在限制性的。
第一方面，本公开提供一种电路板。
电路板(PCB，Print Circuit Board)也称“印刷电路板”、“线路板”等，其可包括多层，每层设有一些引线，而引线可通过孔电连接至其它层的结构。由此，当在电路板上设置电子器件时，可通过引线使各电子器件以所需关系电连接。
参照图1至图8，本公开的电路板包括多个排成连接点阵列的阵 列连接点1，以及多个排成孔阵列的阵列孔，至少部分阵列连接点1与至少一个阵列孔电连接；电路板中定义有结构相同的标准阵列和虚拟阵列，且标准阵列与虚拟阵列中相对应的结构方向相互平行；每个阵列连接点1均位于标准阵列中其对应的标准点位21；孔阵列包括多个标准阵列孔31和至少一个偏移阵列孔32；每个标准阵列孔31位于虚拟阵列中其对应的虚拟点位23；每个偏移阵列孔32的第一侧与第一引线41相邻，且偏移阵列孔32相对虚拟阵列中其对应的虚拟点位23向第二侧偏移第一预定距离，第二侧为第一侧的相对侧。
本公开的电路板包括多个排成连接点阵列的阵列连接点1和多个排成孔阵列的阵列孔。
阵列连接点1是用于与其它结构(如电子器件)电连接的结构，通常位于电路板的表层。例如，阵列连接点1可为设于电路板表面的焊盘。
而阵列孔是电路板中的孔结构(如盲孔、通孔等)，孔中形成有导电材料，以实现不同层结构间的信号传输。
参照图1、图2，电路板中还定义有标准阵列和虚拟阵列。
其中，标准阵列是由多个标准点位21构成的完整的阵列；在平面位置上，每个阵列连接点1都排在标准阵列的标准点位21上，即，连接点阵列是标准阵列的至少一部分。
应当理解，参照图1、图2，阵列连接点1虽然必然位于标准点位21，但不代表每个标准点位21处都必然有阵列连接点1，即，连接点阵列可未将标准阵列的所有点位都“排满”，标准阵列可有部分位置是“空缺”的，具体根据需要与阵列连接点1相连的其它结构的形式设定。
其中，虚拟阵列是由多个虚拟点位23构成的完整的阵列，且其结构与标准阵列相同，即虚拟阵列、标准阵列中点位的个数、间距、相对位置等都相同；而且，标准阵列与虚拟阵列中相对应的结构方向相互平行，例如，当二者均有“行”时，则二者的“行方向”相互平行。
由此，可参照图1，虚拟阵列与标准阵列相互重合；也可参照图 2，虚拟阵列相对标准阵列整体“平移(无旋转)”一定距离。
本公开中，每个阵列孔对应虚拟阵列的一个虚拟点位23，且“基本”位于该虚拟点位23处。具体的，阵列孔分为两种类型，标准阵列孔31和偏移阵列孔32。其中，参照图3、图4，标准阵列孔31就位于其对应的虚拟点位23处；而偏移阵列孔32的第一侧设有相邻的第一引线41(即偏移阵列孔32与第一引线41间没有其它的引线、孔等结构)，且偏移阵列孔32不是正好位于其对应的虚拟点位23，而是相对该虚拟点位23向远离第一引线41的第二侧偏移第一预定距离。
应当理解，标准阵列孔31位于虚拟点位23的描述，并不代表标准阵列孔31与虚拟点位23“绝对”重合，而只要目的是希望标准阵列孔31设于虚拟点位23处，则很小的位置偏移(比如明显小于第一预定距离的偏移)是被允许的。
应当理解，相对相邻虚拟点位23原有的间距，以上第一预定距离应当很小，例如是不超过相邻虚拟点位23的间距的五分之一。
应当理解，参照图3，每个偏移阵列孔32都具有各自的第一引线41和第一侧，即，不同的偏移阵列孔32可能针对不同的第一引线41向不同的第二侧偏移；而对一条引线，部分与其相邻的阵列孔可以其为第一引线41而是偏移阵列孔32，而另一部分与其相邻的阵列孔可不以其为第一引线而是标准阵列孔31。
应当理解，每个阵列孔必然对应虚拟点位23(位于该虚拟点位23或相对虚拟点位23偏移第一预定距离)，但这并不代表每个虚拟点位23都有对应的阵列孔，即孔阵列可未将虚拟阵列的所有点位都“排满”，虚拟阵列可有部分位置是“空缺”的。
也就是说，本公开中，阵列孔“整体上”排成与连接点阵列的相同(但位置不一定重合)的孔阵列，但其中部分与第一引线41相邻的偏移阵列孔32则相对虚拟点位23稍微远离第一引线41，从而增大与第一引线41之间的间距。
应当理解，标准点位21与虚拟点位23一一对应，但由于阵列连接点1不是与标准点位21一一对应，且阵列孔也不是与虚拟点位 23一一对应，故阵列连接点1与阵列孔之间也无必然的对应关系，即二者的数量、所处的相对位置均可不同。
其中，至少部分阵列连接点1与一个或多个阵列孔电连接，以相互传输信号。
即，多个阵列连接点1中，有至少部分阵列连接点1需要与阵列孔电连接。
如前，由于阵列连接点1与阵列孔之间并不一定是一一对应的，故二者之间的对应(电连接)关系也是多样的。
例如，可参照图6、图7，作为本公开的一种方式，每个阵列连接点1均对应且电连接一个阵列孔。再如，阵列连接点1也可不是与位置上对应的阵列孔电连接，而是与位置上对应的阵列孔周围的其它阵列孔电连接，如参照图7，其中标出“编号1”的阵列连接点1，也可与其左下方的阵列孔电连接。再如，也可有部分阵列连接点1不与阵列孔电连接，或者是一个阵列连接点1可与多个阵列孔电连接，或者是一个阵列孔可与多个阵列连接点1电连接，或是部分阵列孔不与阵列连接点1电连接等。
由此可见，阵列孔与阵列连接点1间的电连接方式可根据需要设定，在此不再详细描述。
应当理解，在电路板中，也可有除阵列连接点1外的其它连接点，以及除阵列孔外的其它孔，在此不再详细描述。
本公开中，阵列连接点1排成连接点阵列，阵列孔排成孔阵列，且孔阵列“整体上”是与连接点阵列形式相同的，从而可实现阵列孔与阵列连接点1的电连接；同时，孔阵列中与第一引41线相邻的偏移阵列孔32向远离第一引线41的方向稍微偏移，从而其与第一引线41间的距离增大，使相邻阵列孔间可设置的引线数量增多，提高了电路板的密度，减少了电路板所需的层数，降低其制造成本。
在一些实施方式中，孔阵列包括多行、多列；每条第一引线41设于相邻两列阵列孔之间。
参照图1至图4，作为本公开的一种方式，各阵列孔可以排成多行、多列，而所有偏移阵列孔32的第一引线41都是在相邻“两列” 阵列孔之间延伸的。
应当理解，以上行、列仅表示两个相互交叉的相对方向，其既不代表二者必须相互垂直，也与电路板的朝向、放置位置等没有必然关系(例如，不一定各附图中的纵向就是列方向)。
在一些实施方式中，标准阵列为矩阵，矩阵的行、列相互垂直。
作为本公开的一种方式，进一步的，参照图1、图2，以上行、列可以是相互垂直的，从而标准阵列是“矩阵”形式，当然，虚拟阵列相应也为“矩阵”形式。
在一些实施方式中，阵列连接点1为用于与球栅阵列连接的焊盘。
作为本公开的一种方式，阵列连接点1是用于与球栅阵列(BGA，Ball Grid Array)封装芯片连接的焊盘，即每个焊盘用于与BGA封装芯片的BGA中的一个引脚锡球相连，相应的阵列孔也就是“BGA过孔”，用于传输BGA封装芯片的信号。
在一些实施方式中，至少部分阵列孔对应的虚拟点位23为焊盘的位置，第一预定距离小于焊盘半径与阵列孔半径之和；至少部分阵列孔与和其位置有重合的焊盘电连接。
参照图6，作为本公开的一种方式，阵列孔对应的虚拟点位23可就是其电连接的焊盘(也是阵列连接点1和标准点位21)所在的位置，即，虚拟阵列与标准阵列重合，也就是采用孔上盘(POFV,Plated over Filled Via)设计。
由此，标准阵列孔31就设于其对应的焊盘处，可直接与焊盘电连接；而偏移阵列孔32相对虚拟点位23(也就是焊盘)偏移第一预定距离，但由于第一预定距离小于焊盘半径与阵列孔半径之和，故偏移阵列孔32在偏移后仍然与焊盘至少有部分重合，可直接电连接。
或者，在另一些实施方式中，至少部分阵列孔对应的虚拟点位23相对焊盘的位置偏移第二预定距离，第二预定距离大于焊盘半径与阵列孔半径之和；至少部分阵列孔通过连接引线43与焊盘电连接。
参照图7，作为本公开的另一种方式，阵列孔对应的虚拟点位23与焊盘之间可有第二预定距离，即虚拟阵列相对标准阵列移动第 二预定距离，且该第二预定距离大于焊盘半径与阵列孔半径之和，从而焊盘(也是阵列连接点1和标准点位21)与阵列孔并无直接重合，而是要通过连接引线43电连接(如前，此时焊盘与阵列孔的连接关系不限于图7的形式)。
参照图7，此时偏移阵列孔32的位置偏移就相当于连接引线43的一端位置改变，故偏移阵列孔32连接的连接引线43的长度、角度，与标准阵列孔31连接的连接引线43的长度、角度会稍有不同(有的连接引线43长度缩短，有的连接引线43长度增长)，但因为以上差别非常小，故对相应的信号传输不会产生实质的影响。
应当理解，阵列连接点1不限于以上焊盘的形式。例如，阵列连接点1也可用于与其它电子器件中呈阵列的引脚相连。
在一些实施方式中，至少部分偏移阵列孔32为背钻孔。
作为本公开的一种方式，偏移阵列孔32可为背钻孔(即背面进行了背钻工艺的孔)，参照图5，在背钻工艺中孔径会增大，从而导致在位置相同时，相对于其它的孔，背钻孔与相邻引线间的距离会更小，更容易超出工艺能力或引起不良，因此可用背钻孔作为偏移阵列孔32。
在一些实施方式中，孔阵列包括至少一个偏移孔组；每个偏移孔组包括两个相邻的偏移阵列孔32，其中任意一个偏移阵列孔32的第一侧与另一个偏移阵列孔32相邻；每对相邻偏移阵列孔中的两个偏移阵列孔32均为背钻孔。
作为本公开的一种方式，可以是在两个相邻且之间有引线的阵列孔均为背钻孔(即双侧背钻孔)时，使二者均为偏移阵列孔32(视为一个偏移孔组)，并向相反的方向分别偏移(即两个偏移阵列孔32的第一侧相对，而第二侧相反)。当两个相邻的阵列孔都是背钻孔时，二者的间距必然更小，故二者可都是偏移阵列孔32以尽量增大间距。
应当理解，偏移阵列孔32可为背钻孔并不代表所有的背钻孔都必须为偏移阵列孔，即，对每个背钻孔，其是否为偏移阵列孔可根据需要选择。
应当理解，可作为偏移阵列孔32的孔也不限于背钻孔的形式，例如，盲孔、深V孔、其它过孔等也均可作为偏移阵列孔32。
应当理解，背钻孔与偏移阵列孔32的关系不限于以上具体例子。例如，对相邻且之间有引线的两个背钻孔，可以是其中只有一个是偏移阵列孔32，或都不是偏移阵列孔32；再如，也可以是在两个相邻且之间有引线的阵列孔中，当只有一个为背钻孔(即单侧背钻孔)时，该背钻孔作为偏移阵列孔32；再如，也可以是以除背钻孔外的其它阵列孔作为偏移阵列孔32。
在一些实施方式中，至少部分第一引线41为差分线。
作为本公开的一种方式，偏移阵列孔32对应的第一引线41可以是用于传输差分信号的差分线(与其电连接的孔为高速信号孔)。差分信号通常是高频信号，更容易与其它结构产生干扰，故与其它结构的间距应更大；而且，差分线必然是“成对”的，而一对差分线最好是设于相邻的阵列孔间(双线模式)以提高电路板的密度并降低其层数和成本，故差分线的布线空间往往更紧凑，更需要通过一些方式增大布线空间。
应当理解，第一引线41并不限于以上形式。例如，相邻阵列孔间仅设有一条差分线(单线模式)时，阵列孔中也可包括偏移阵列孔32；再如，其它的引线(如接地线GND等)也可作为第一引线41。
在一些实施方式中，至少部分偏移阵列孔32的第二侧与第二引线42相邻，第二引线42的延伸方向垂直于从第一侧指向第二侧的方向，第二引线42在与偏移阵列孔32相邻处构成向远离偏移阵列孔32的方向凸出的弯折结构421。
参照图3，偏移阵列孔32的第二侧，也可设有相邻的引线(第二引线42)，第二引线42整体的延伸方向垂直于从第一侧指向第二侧的方向(如为列方向)。
由于偏移阵列孔32向第二侧偏移(如沿行方向偏移)，故相对标准阵列孔31(如同列的标准阵列孔31)，偏移阵列孔32与第二引线42间的距离会变小，为使偏移阵列孔32与第二引线42间的距离符合要求，故参照图3，第二引线42可在对应偏移阵列孔32的局部 位置向远离偏移阵列孔32一侧弯折(即形成弯折结构421)。
应当理解，每个偏移阵列孔32具有对应的第二引线42，而每条引线可能同时作为多个偏移阵列孔32的第二引线42，且不同偏移阵列孔32的第一侧的方向可能不同，故参照图3，弯折结构421的具体弯折方向可有不同。
在一些实施方式中，孔阵列包括至少一个偏移孔组；每个偏移孔组包括两个相邻的偏移阵列孔32，其中任意一个偏移阵列孔32的第一侧与另一个偏移阵列孔32相邻。
作为本公开的一种方式，参照图3，可以是部分相邻且之间有引线的阵列孔同时为偏移阵列孔32(如同时为背钻孔)，并向相互远离的方向偏移(即两个相邻偏移阵列孔32的第一侧相对，第二侧相反)。
在一些实施方式中，至少部分相邻的偏移阵列孔32间设有一条引线，该引线同时为该两个偏移阵列孔32的第一引线41；和/或，至少部分相邻的偏移阵列孔32间设有两条引线，该两条引线分别为该两个偏移阵列孔32的第一引线41。
作为本公开的一种方式，参照图4，当两个相邻偏移阵列孔32相互远离的偏移时，可以是二者之间只有一条引线，其同时作为二者的第一引线41；也可以是参照图3，二者之间有两条引线，分别作为二者的第一引线41。
应当理解，引线、阵列孔的具体形式均不限于以上的具体形式。例如，参照图3，与偏移阵列孔32第一侧相邻的引线也可为三条或更多；再如，参照图4，两个相邻阵列孔中可只有一个是偏移阵列孔32；再如，参照图3、图4，两列阵列孔间引线的数量相同时，其中可只有部分阵列孔是偏移阵列孔32(如只有背钻孔才是偏移阵列孔32)，或者阵列孔可都不是偏移阵列孔；再如，参照图4，偏移阵列孔32有相邻引线时，引线也可不弯折(即不是第二引线)等。
应当理解，偏移阵列孔32偏移的第一预定距离可根据钻孔能力尺寸范围(可保证钻孔后不会产生不良的情况下，孔与相邻引线间的距离范围)选择。
例如，对参照图8，当两列阵列孔间设有两条引线，两个相邻阵列孔均为偏移阵列孔32(故两条引线均为第一引线41)，而每个偏离阵列孔的第二侧依次为两条第二引线42的弯折结构421和一个标准阵列孔31时(以图8中左侧的偏移阵列孔32为例)，该偏移阵列孔32的第二侧处应满足以下公式(1)：
D＝2w+s+d1+d2+2Rp+d    (1)；
而该偏移阵列孔32的第一侧处应满足以下公式(2)：
D＝2w+s+2d2+2Rp-2d    (2)；
其中，参照图8，D为相邻虚拟点位23沿行方向的间距，d为偏移阵列孔32沿行方向偏移的第一预定距离，w为引线的线宽，s为两相邻引线沿行方向的间距，d1为标准阵列孔31与相邻引线沿行方向的间距，Rp为阵列孔的半径，d2为偏移阵列孔32与相邻引线沿行方向的间距。
可见，由于是阵列，故不同虚拟点位23间的距离D必然是相同的，而从信号均匀的角度考虑，其它所有相同的参数的具体尺寸也应尽量相等(如偏移阵列孔32与第一引线41、第二引线42间的距离d2的值应相同)。由此，以上公式(1)、公式(2)中相同符号的参数的值是相等的，故用以上公式(2)减去公式(1)，即可得参照图8的情况下，偏移阵列孔32偏移的第一预定距离d根据以下公式(3)计算：
d＝(d2-d1)/3    (3)。
其中，d1、d2应分别在标准阵列孔31(如非背钻孔)、偏移阵列孔32(如背钻孔)的钻孔能力(一次钻孔能力、二次钻孔能力)尺寸范围内选择(否则可能产生不良)，而在选定d1、d2后，即可根据以上公式求出偏移阵列孔32偏移的第一预定距离d。
应当理解，各种尺寸不限于以上具体例子，例如，当偏移阵列孔32第二侧有引线但引线不弯折时，则偏移阵列孔32与两侧引线间的距离d2就可不同。
应当理解，本公开的各附图中只是示意性的表示各结构的相对位置关系，而不是对其具***置、连接方式等的限定。例如，各附图 中的引线，实际可能处于电路板的内层中(例如参照图5)，故在俯视情况下不直接可见(但图中将其示出)；再如，各附图中的引线可以是参照图3与阵列孔相连，而与阵列连接点1实现信号传输，或引线也可只是“经过”阵列孔的区域，而不连接阵列孔。
示例1：
当电路板的阵列连接点对应间距1mm的BGA矩阵时，BGA矩阵最外4圈需要出线，故电路板可包括两层，靠上的一层实现BGA矩阵靠外两圈的出线，靠下的一层实现BGA靠内两圈的出线，靠外两圈的引线在靠内两圈的高速线的引线层处被背钻掉。
示例2：
当电路板的阵列连接点对应间距1mm的BGA矩阵时，通过偏移阵列孔的偏移，可增大引线通道，穿更多的引线。例如，第一行与第二行阵列孔之间间距为1mm，穿1根引线；第二行与第三行阵列孔之间间距为1mm，穿2根引线；第三行与第四行阵列孔之间间距为1.2mm，穿3根引线；第四行与第五行阵列孔之间间距为0.8mm，穿一根引线。其中第4行中的偏移阵列孔向下偏移0.2mm，造成第三行与第四行阵列孔之间间距加大为1.2mm，而第四行与第五行阵列孔之间间距缩小为0.8mm。
示例3：
当电路板的阵列连接点对应间距0.8mm的BGA矩阵时，通过偏移阵列孔的偏移，可增大引线通道，穿更多的引线。例如，左侧两列每行孔间距为0.8mm，右侧阵列孔中，第一行与第二行阵列孔之间间距为0.8mm，穿1根引线；第二行与第三行阵列孔之间间距为0.76mm，穿1根引线；第三行与第四行阵列孔之间间距为0.96mm，穿2根引线；第四行与第五行阵列孔之间间距为0.76mm，穿1根引线；第五行与第六行阵列孔之间间距为0.76mm，穿1根引线；第六行与第七行阵列孔之间间距为0.76mm，穿1根引线；其中从第3行开始设置偏移阵列孔以调整间距；由此，无论是左边两列还是右边各列阵列孔，从第二行到第七行孔间距为4mm，可以看出同样的距离右侧穿过的引线比左侧多一根。
第二方面，参照图9，本公开提供一种电路板组件，其包括：本公开实施方式的任意一种电路板；设于电路板上的电子器件，至少部分电子器件与阵列连接点电连接。
可在以上电路板上设置相应的电子器件，以形成电路板组件(或者说是具有相对完整功能的电路板)；其中，至少部分电子器件是与电路板的阵列连接点电连接的。
例如，电子器件可包括BGA封装芯片，而BGA封装芯片即通过阵列连接点(焊盘)连接在电路板上。
本公开已经公开了示例实施方式，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则可单独使用与特定实施方式相结合描述的特征、特性和/或元素，或可与其它实施方式相结合描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本公开的范围的情况下，可进行各种形式和细节上的改变。

Claims (15)

  1. 一种电路板，包括多个排成连接点阵列的阵列连接点，以及多个排成孔阵列的阵列孔，至少部分所述阵列连接点与至少一个所述阵列孔电连接；
    所述电路板中定义有结构相同的标准阵列和虚拟阵列，且所述标准阵列与虚拟阵列中相对应的结构方向相互平行；
    每个所述阵列连接点均位于所述标准阵列中其对应的标准点位；
    孔阵列包括多个标准阵列孔和至少一个偏移阵列孔；每个所述标准阵列孔位于所述虚拟阵列中其对应的虚拟点位；每个所述偏移阵列孔的第一侧与第一引线相邻，且所述偏移阵列孔相对所述虚拟阵列中其对应的虚拟点位向第二侧偏移第一预定距离，所述第二侧为第一侧的相对侧。
  2. 根据权利要求1所述的电路板，其中，
    所述孔阵列包括多行、多列；
    每条所述第一引线设于相邻两列阵列孔之间。
  3. 根据权利要求1所述的电路板，其中，
    所述标准阵列为矩阵，所述矩阵的行、列相互垂直。
  4. 根据权利要求1所述的电路板，其中，
    至少部分所述偏移阵列孔的第二侧与第二引线相邻，所述第二引线的延伸方向垂直于从第一侧指向第二侧的方向，所述第二引线在与偏移阵列孔相邻处构成向远离偏移阵列孔的方向凸出的弯折结构。
  5. 根据权利要求1所述的电路板，其中，所述孔阵列包括至少一个偏移孔组；
    每个所述偏移孔组包括两个相邻的偏移阵列孔，其中任意一个偏移阵列孔的第一侧与另一个偏移阵列孔相邻。
  6. 根据权利要求5所述的电路板，其中，
    至少部分相邻的所述偏移阵列孔间设有一条引线，该引线同时为该两个偏移阵列孔的第一引线。
  7. 根据权利要求5所述的电路板，其中，
    至少部分相邻的所述偏移阵列孔间设有两条引线，该两条引线分别为该两个偏移阵列孔的第一引线。
  8. 根据权利要求5所述的电路板，其中，
    至少部分相邻的所述偏移阵列孔间设有一条引线，该引线同时为该两个偏移阵列孔的第一引线；
    并且，
    至少部分相邻的所述偏移阵列孔间设有两条引线，该两条引线分别为该两个偏移阵列孔的第一引线。
  9. 根据权利要求1所述的电路板，其中，
    至少部分所述第一引线为差分线。
  10. 根据权利要求1所述的电路板，其中，
    至少部分所述偏移阵列孔为背钻孔。
  11. 根据权利要求10所述的电路板，其中，所述孔阵列包括至少一个偏移孔组；
    每个所述偏移孔组包括两个相邻的偏移阵列孔，其中任意一个偏移阵列孔的第一侧与另一个偏移阵列孔相邻；
    每对相邻偏移阵列孔中的两个偏移阵列孔均为背钻孔。
  12. 根据权利要求1所述的电路板，其中，
    所述阵列连接点为用于与球栅阵列连接的焊盘。
  13. 根据权利要求12所述的电路板，其中，
    至少部分所述阵列孔对应的虚拟点位为焊盘的位置，所述第一预定距离小于焊盘半径与阵列孔半径之和；至少部分所述阵列孔与和其位置有重合的焊盘电连接。
  14. 根据权利要求12所述的电路板，其中，
    至少部分所述阵列孔对应的虚拟点位相对焊盘的位置偏移第二预定距离，所述第二预定距离大于焊盘半径与阵列孔半径之和；至少部分所述阵列孔通过连接引线与焊盘电连接。
  15. 一种电路板组件，其包括：
    权利要求1至14中任意一项所述的电路板；
    设于所述电路板上的电子器件，至少部分所述电子器件与阵列连接点电连接。
PCT/CN2023/079007 2022-06-21 2023-03-01 电路板、电路板组件 WO2023246160A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020084312A1 (en) * 2000-12-29 2002-07-04 Shier Daniel E. Design and assembly methodology for reducing bridging in bonding electronic components to pads connected to vias
US20030183419A1 (en) * 2001-04-27 2003-10-02 Lsi Logic Corporation Ball assignment for ball grid array package
CN102111957A (zh) * 2009-12-28 2011-06-29 丛林网络公司 用于增加每pcb层的布线通道数目的bga印迹图案
CN203228481U (zh) * 2013-05-03 2013-10-09 深圳市沃特沃德科技有限公司 一种smt印刷模板的结构
CN110874518A (zh) * 2018-08-13 2020-03-10 日本麦可罗尼克斯股份有限公司 布线基板的设计辅助装置、导孔配置方法以及记录介质

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020084312A1 (en) * 2000-12-29 2002-07-04 Shier Daniel E. Design and assembly methodology for reducing bridging in bonding electronic components to pads connected to vias
US20030183419A1 (en) * 2001-04-27 2003-10-02 Lsi Logic Corporation Ball assignment for ball grid array package
CN102111957A (zh) * 2009-12-28 2011-06-29 丛林网络公司 用于增加每pcb层的布线通道数目的bga印迹图案
CN203228481U (zh) * 2013-05-03 2013-10-09 深圳市沃特沃德科技有限公司 一种smt印刷模板的结构
CN110874518A (zh) * 2018-08-13 2020-03-10 日本麦可罗尼克斯股份有限公司 布线基板的设计辅助装置、导孔配置方法以及记录介质

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