WO2023240796A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023240796A1
WO2023240796A1 PCT/CN2022/114847 CN2022114847W WO2023240796A1 WO 2023240796 A1 WO2023240796 A1 WO 2023240796A1 CN 2022114847 W CN2022114847 W CN 2022114847W WO 2023240796 A1 WO2023240796 A1 WO 2023240796A1
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Prior art keywords
signal
wiring
display panel
groups
trace
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PCT/CN2022/114847
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English (en)
French (fr)
Inventor
张兵
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昆山国显光电有限公司
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Publication of WO2023240796A1 publication Critical patent/WO2023240796A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present application belongs to the technical field of electronic products, and particularly relates to a display panel and a display device.
  • Embodiments of the present application provide a display panel and a display device that reduce capacitance interference between adjacent signal wiring groups and reduce capacitance differences between signal wiring groups, thereby ensuring the display effect of the display panel.
  • embodiments of the present application provide a plurality of signal traces. At least in part of the plurality of signal traces, two of the signal traces extend side by side to form a signal trace group; between adjacent signal trace groups The minimum distance is greater than the maximum distance between two signal traces in the same signal trace group; and/or, at least one of the signal trace groups includes a bent section.
  • the distance between two signal traces in the same signal trace group is equal everywhere.
  • At least one of the signal trace groups includes connected bent segments and straight segments, and the sum of the lengths of the bent segments and straight segments of each of the signal traces is equal.
  • At least one of the bent sections of the signal wiring group is arranged in a serpentine wiring arrangement.
  • the minimum distance between the straight sections of two adjacent groups of signal wiring groups is greater than the minimum distance between the bent sections of two adjacent groups of signal wiring groups.
  • the minimum distance between the linear segments of two adjacent groups of signal traces is greater than or equal to twice the trace width of a single linear segment; preferably, the minimum distance between the two adjacent groups of signal traces is greater than or equal to twice the trace width of a single linear segment.
  • the minimum distance between the linear segments of the signal trace group is equal to three times the trace width of a single linear segment; preferably, the trace width of a single linear segment is 2 ⁇ m to 3 ⁇ m; preferably, The minimum distance between the straight segments of the two adjacent groups of signal wiring groups is 6 ⁇ m to 9 ⁇ m.
  • the display panel includes a fan-out area.
  • the fan-out area includes a middle wiring area and an edge wiring area.
  • the edge wiring area is located in the middle wiring area perpendicular to the wiring area. Both sides in the extension direction; in the middle wiring area, the wiring length of the bent section of each signal wiring group is greater than the wiring length of the straight section; in the edge wiring area, The wiring length of the bending section of each signal wiring group is smaller than the wiring length of the straight section.
  • the present application also includes a substrate, a first metal layer and a second metal layer stacked along the thickness direction of the display panel.
  • the second metal layer includes a plurality of conductive blocks, the signal traces and
  • the first metal layer is arranged on the same layer; along the thickness direction of the display panel, the orthographic projection of the conductive block on the substrate and the orthographic projection of the signal trace on the substrate at least partially overlap, In the overlapping area of the single conductive block and the orthographic projection of the signal trace on the substrate, the trace lengths of each of the signal trace groups are equal.
  • an external circuit and a pixel driving circuit are further included.
  • the external circuit is electrically connected to the pixel driving circuit; and each of the signal lines is electrically connected to a different external circuit.
  • Another aspect of the embodiment of the present application provides a display device, including: the display panel in any of the above embodiments.
  • the display panel provided by the embodiment of the present application includes multiple signal traces. At least part of the multiple signal traces, two signal traces extend side by side to form a signal trace group. Since each signal trace The materials used are the same, that is, the impedance is the same. According to the calculation rules of capacitance, the greater the distance, the smaller the capacitance. The minimum distance between adjacent signal trace groups is set to be greater than the two signal traces in the same signal trace group.
  • the capacitance between adjacent signal trace groups can be smaller than the capacitance between two signal traces in the same signal trace group, thereby reducing capacitive interference between adjacent signal trace groups and reducing
  • the capacitance difference between small signal traces ensures the display effect of the display panel.
  • at least one set of signal trace groups includes a bending section, the overlapping area between the two signal traces of the signal trace group can be increased, and the capacitance generated by the bending section is relatively increased, which can be achieved by adjusting the bending section.
  • the wiring length of the bent section adjusts the capacitance difference between each signal wiring group, and the use of bent sections can also shorten the extension length of the signal wiring group and save wiring space.
  • Figure 1 is a circuit diagram of an external circuit
  • Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Figure 3 is a partial enlarged view of an embodiment at B in Figure 2;
  • Figure 4 is a schematic structural diagram of a bending section provided by an embodiment of the present application.
  • Figure 5 is a partial enlarged view of an embodiment at C in Figure 2;
  • Figure 6 is a partial enlarged view of another embodiment at C in Figure 2;
  • Figure 7 is a film structure diagram of an embodiment at D-D in Figure 6.
  • 1-control chip 2-signal wiring; 21-bent section; 22-straight line section; 3-conductive block; M1-first metal layer; M2-second metal layer; A1-middle wiring area; A2- Edge routing area; Y-first direction; X-second direction.
  • transistors made of low-temperature polysilicon or oxides will have threshold voltage Vth drift during use. For example, factors such as illumination in the oxide semiconductor, source-drain electrode voltage stress, etc. may cause the threshold voltage Vth to drift. Voltage drift causes the current through the light-emitting element to be inconsistent with the required current, and the display uniformity of the display panel cannot be satisfied.
  • an external circuit can be used to compensate the threshold voltage of the driving transistor of the pixel driving circuit, as shown in Figure 1.
  • Figure 1 is a circuit diagram of an external circuit. Each external circuit is connected to a different signal line Date/Sense respectively. During compensation, the capacitor Cdata needs to be charged through the signal line Date/Sense first so that the capacitor Cdata reaches the VDD+Vth voltage. Since VDD is a constant, it can be measured Vth, and finally perform voltage compensation on the driving transistor of the pixel driving circuit based on the measured Vth.
  • the embodiments of the present application provide a display panel and a display device. Each embodiment of the display panel and the display device will be described below with reference to FIGS. 2 to 7 .
  • Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present application
  • Figure 3 is a partial enlarged view of an embodiment at B in Figure 2
  • Figure 4 is an implementation of the present application.
  • the example provides a schematic structural diagram of the bending section
  • Figure 5 is a partial enlarged view of an embodiment at C in Figure 2.
  • a display panel provided by an embodiment of the present application includes a plurality of signal traces 2. At least part of the plurality of signal traces 2, two signal traces 2 extend side by side to form a signal trace group; between adjacent signal trace groups The minimum distance b between two signal traces 2 is greater than the maximum distance a between two signal traces 2 in the same signal trace group; and/or, at least one signal trace group includes a bending section 21 .
  • the display panel provided by the embodiment of the present application includes signal traces 2.
  • Two signal traces 2 extend side by side to form a signal trace group. Since the materials used in each signal trace 2 are the same, that is, the impedances are the same, according to the calculation rules of capacitance , the larger the distance, the smaller the capacitance.
  • the minimum distance b between adjacent signal trace groups is set to be greater than the maximum distance a between two signal traces 2 in the same signal trace group, the adjacent signal traces 2 can be The capacitance between signal trace groups is smaller than the capacitance between two signal traces 2 in the same signal trace group, which reduces the capacitive interference between adjacent signal trace groups and reduces the capacitance difference between signal traces 2. This ensures the display effect of the display panel.
  • the bending section 21 can increase the overlapping area between the two signal traces 2 of the signal trace group, and the capacitance generated by the bending section 21 is relatively small. Increase, the capacitance difference between the signal wiring groups can be adjusted by adjusting the wiring length of the bending section 21, and the use of the bending section 21 can also shorten the extension length of the signal wiring group and save wiring space.
  • two signal traces 2 extend side by side to form a signal trace group, that is, part of the signal traces 2 may not form a signal trace group, and part may form a signal trace group.
  • the signal wiring group can be set with a bending section or without a bending section.
  • the display panel includes a fan-out area.
  • the fan-out area includes a middle wiring area A1 and an edge wiring area A2.
  • the edge wiring area A2 is located in the middle wiring area A1 in a direction perpendicular to the wiring extension direction.
  • the signal traces 2 located in the edge trace area A2 can all form a signal trace group, or can partially form a signal trace group, and the minimum distance b between adjacent signal trace groups should be greater than the same signal trace group.
  • the maximum distance a between two signal traces 2 in the trace group to reduce the capacitance interference between adjacent signal trace groups can be determined based on the capacitance difference of the signal trace 2 located in the edge trace area A2 choose.
  • the ones located in the middle wiring area A1 can be extended side by side to form a signal wiring group, and at least one set of signal wiring groups includes a bending section 21.
  • the bending section 21 can increase the capacitance between the signal wirings and can be adjusted by bending.
  • the wiring length of segment 21 adjusts the capacitance difference between each signal wiring group, and can also shorten the extension length of the signal wiring group in the middle wiring area A1, saving wiring space.
  • the minimum distance b between adjacent signal trace groups is greater than the maximum distance a between two signal traces 2 in the same signal trace group, and at least one signal trace group includes a bending section.
  • the setting method of 21 can be applied to signal trace 2 at the same time, or can be applied to signal trace 2 alone, such as signal trace 2 located in different locations, as long as the capacitance difference between signal traces 2 can be reduced to ensure The display effect of the display panel is sufficient, and there are no special restrictions.
  • the display panel also includes a control chip 1.
  • Each signal trace 2 is electrically connected to the control chip 1.
  • the control chip 1 can provide signals for external circuits through the signal traces 2, and the signal traces 2 can correspond to the external circuit.
  • the control chip 1 is a fan-out line.
  • the control chip 1 can also provide signal control for the internal compensation circuit or pixel drive circuit of the display panel. That is, the signal line 2 can also be the fan-out line or other lines for the internal compensation circuit or pixel drive circuit.
  • the embodiment of the present application is aimed at improving the wiring method of the signal trace 2, and there is no special limitation on the application scenarios of the signal trace 2.
  • the distance between two signal traces 2 in the same signal trace group is equal everywhere. Since the materials used in each signal trace 2 are the same, that is, the impedance is the same, by making the distance equal everywhere, This can realize that the capacitance between the two signal traces 2 in the same signal trace group is equal everywhere, and improve the capacitance consistency of the two signal traces 2 in the same signal trace group.
  • the signal wiring group includes connected bent sections 21 and straight sections 22.
  • the curved sections 21 and straight sections 22 of each signal wiring group are The sum of the line lengths are all equal.
  • the sum of the wiring lengths of the bending section 21 and the straight section 22 of each signal wiring group is equal to ensure that each signal wiring 2 of each signal wiring group has the same impedance, without Because the proportions of the wiring lengths of the curved sections 21 and the straight sections 22 of each signal wiring group are different, the impedances are different, which makes it easy to adjust the capacitance of each signal wiring group under the condition that the impedance is the same.
  • Capacitance C k ⁇ S/d; where k is the dielectric constant of the medium between the traces, S is the facing area of the two traces, and d is the distance between the two traces.
  • the facing area S between the two signal traces 2 can be effectively increased, thereby increasing the capacitance C.
  • the bending sections 21 of each signal wiring group can be arranged in a serpentine shape, and the different bending sections 21 formed by the bending in the serpentine shape are arranged relative to each other, that is, two more bending sections are added.
  • the facing area S between the signal traces 2 can generate additional capacitance and increase the capacitance generated by the bending section 21 .
  • the bent section 21 extends along the first direction Y, as shown in FIG. 3 , which can better utilize the wiring space.
  • the bending section 21 extends along the second direction X, and the second direction X intersects the first direction Y.
  • the second direction X can be perpendicular to the first direction Y, and is not particularly limited.
  • the serpentine trace can be formed by straight lines, and the bending angle of each straight line at the bend is a right angle, as shown in Figure 2.
  • the serpentine trace can also be a curve segment, that is, the bend section 21 can be a curve that is bent multiple times. Formation is not particularly limited.
  • the bending section 21 of each signal wiring group can also be a polyline segment formed by bending multiple straight lines, similar to a "Z" type wiring or other irregular polyline segments, according to The required wiring length of the bending segment 21 can be determined by selecting the number of bends and the bending angle of the bending line segment.
  • the minimum distance between the straight segments 22 of two adjacent signal trace groups is greater than the minimum distance between the bent segments 21 of two adjacent signal trace groups, that is, by increasing The distance d between the two traces is used to reduce the capacitance of the signal trace group in the straight section 22 and facilitate adjustment of the capacitance difference between the signal trace groups.
  • the angle between the extending direction of the straight segments 22 and the first direction Y is an acute angle, that is, each straight segment 22 is distributed in an inclined line, so that each straight segment 22 is directed toward the location of the control chip 1 The position is closed and electrically connected to the control chip 1.
  • the display panel includes a fan-out area.
  • the fan-out area includes a middle wiring area A1 and an edge wiring area A2.
  • the edge wiring area A2 is located in the middle wiring area A1 in a direction perpendicular to the wiring extension direction. On both sides of The trace length of segment 21 is smaller than the trace length of straight segment 22 .
  • the signal wiring group in the edge wiring area A2 needs to extend from both sides to the middle in order to facilitate connection with the control chip 1, while the signal wiring group in the middle wiring area A1
  • the inclination angle of the wiring group is relatively small or extends directly vertically along the first direction Y in order to make the wiring length of the signal wiring group in the middle wiring area A1 equal to the length of the signal wiring group in the edge wiring area A2.
  • the wiring length of the bending section 21 of each signal wiring group is greater than or equal to the wiring length of the straight section 22; to reduce the risk caused by the middle wiring area A1 , the impedance difference caused by the wiring length of the edge wiring area A2, thereby reducing the capacitance difference between the middle wiring area A1 and the edge wiring area A2.
  • the signal wiring group in the edge wiring area A2 includes a bending section 21. The wiring length of the bending section 21 of each signal wiring group is shorter than the wiring length of the straight section 22, so as to reduce the wiring length in the middle wiring area A1. , the capacitance difference of A2 in the edge wiring area.
  • the wiring length of the bent section 21 of each signal wiring group is greater than the wiring length of the straight section 22; in the edge wiring area A2, the curved section of each signal wiring group is longer than the wiring length of the straight section 22.
  • the trace length of 21 is smaller than the trace length of straight segment 22, that is, in the middle trace area A1, the capacitance of the bent segment 21 plays a major role, and in the edge trace area A2, the capacitance of the straight segment 22 plays a major role.
  • the middle wiring area A1 uses a single wiring to form a serpentine wiring to reduce the length of the wiring in its extension direction, this structure will not generate additional capacitance in the bending section 21, resulting in the intermediate wiring
  • the capacitance of the traces in the line area A1 is smaller than the capacitance of the traces in the edge trace area A2, resulting in a capacitance difference.
  • the embodiment of the present application forms a signal wiring group by extending two signal wirings 2 side by side.
  • the signal wiring group includes a bending section 21 to generate additional capacitance. , that is, increasing the capacitance of the middle wiring area A1.
  • the stacking area is increased, thereby increasing the capacitance of the bending section 21 and saving wiring space.
  • the capacitance of the signal wiring group in the straight line segment 22 can also be reduced by increasing the minimum distance between the straight segments 22 of two adjacent signal wiring groups, that is, increasing the distance d between the two wiring groups.
  • the method of increasing the capacitance of the bent section 21 and the method of reducing the capacitance of the straight section 22 are combined to reduce the capacitance difference between the signal wiring groups in the middle wiring area A1 and the edge wiring area A2.
  • the display panel also includes an external circuit and a pixel driving circuit, and the external circuit and the pixel driving circuit are electrically connected; each signal line 2 is electrically connected to a different external circuit respectively.
  • the capacitance range between each signal trace 2 is 25pf ⁇ 35pf, and when the charging time is 1ms, the voltage range of Cdata is 1.709V ⁇ 1.870 V, the measured difference range of Vth is -100mV ⁇ 100mV. When the charging time is 18ms, the voltage range of Cdata is 2.764V ⁇ 2.846V, and the measured difference range of Vth is -50mV ⁇ 50mV.
  • the capacitance range between the signal traces 2 is 28.5pf ⁇ 31.5pf.
  • the voltage range of Cdata is 1.762V ⁇ 1.810V, and the measured difference in Vth The range is -25mV ⁇ 25mV.
  • the voltage range of Cdata is 2.788V ⁇ 2.813V, and the measured Vth difference range is -15mV ⁇ 15mV.
  • the use of the signal traces 2 in the embodiment of the present application can effectively reduce the capacitance range between the signal traces 2, and whether it is when the charging time is 1ms or when the charging time is 18ms, the capacitance range is relatively good.
  • the voltage range of Cdata and the measured difference range of Vth in the embodiment of the present application are significantly reduced, which improves the accuracy of the voltage compensation value of the driving transistor of each pixel driving circuit by each external circuit. , thereby improving the display effect of the display panel.
  • the minimum distance between the straight segments 22 of two adjacent signal trace groups is greater than or equal to twice the trace width of a single straight segment 22 to ensure that the straight segments 22 of two adjacent signal trace groups are The capacitance value between them is significantly reduced, which meets the need to balance the capacitance difference between the signal wiring group located in the middle wiring area A1 and the edge wiring area A2; in this embodiment, specifically, when the same signal wiring When the minimum distance between two signal traces 2 in the group is equal to the width of a single signal trace 2, the minimum distance between the straight line segments 22 of two adjacent signal trace groups can be equal to the width of a single straight line segment 22. Three times the line width, that is, a space for one signal line 2 is reserved between the straight segments 22 of two adjacent signal line groups to facilitate installation.
  • the trace width of a single straight line segment 22 is 2 ⁇ m to 3 ⁇ m, and the minimum distance between the straight segments 22 of two adjacent signal line groups is 6 ⁇ m to 9 ⁇ m.
  • the size of the capacitance is adjusted by adjusting the minimum distance between the straight segments 22 of two adjacent groups of signal traces.
  • the trace width of a single straight line segment 22 and the minimum distance between the straight line segments 22 of two adjacent signal trace groups are not limited to the above numerical range, and can be selected according to the need to reduce the capacitance difference of the signal traces 2 .
  • capacitance may also occur between the signal traces 2 and other conductive layers of the adjacent display panel.
  • Figure 6 is a partial enlarged view of another embodiment at C in Figure 2;
  • Figure 7 is a film structure diagram of an embodiment at D-D in Figure 6.
  • the display panel also includes a substrate, a first metal layer M1 and a second metal layer M2 that are stacked along the thickness direction of the display panel.
  • the second metal layer M2 includes a plurality of conductive blocks 3.
  • the signal traces 2 are the same as the first metal layer M1.
  • each signal trace 2 and the first metal layer M1 are arranged on the same layer; that is, the vertical distance between each signal trace 2 and the second metal layer M2 is equal, and the distance between each signal trace 2 is The trace width and unit impedance are equal. Therefore, the parameter that affects the capacitance between each signal trace 2 and the conductive block 3 of the second metal layer M2 is only the length of the overlapping portion of the signal trace 2 and the single conductive block 3. In this embodiment, by limiting the overlapping area of the orthographic projection of the single conductive block 3 and the signal trace 2 on the substrate along the thickness direction of the display panel, the trace lengths of each signal trace group are equal to ensure that the trace lengths of each signal trace group are equal.
  • each conductive block 3 may be a polygon such as a triangle or a trapezoid, or a shape including a curved edge such as an ellipse or a circle.
  • the second metal layer M2 may specifically be a wiring layer for VDD positive voltage wiring and VSS negative voltage wiring.
  • An embodiment of the present application also provides a display device, including: the display panel in any of the above embodiments.
  • the display device provided by the embodiment of the present application can be applied to mobile phones or any electronic product with a display function, including but not limited to the following categories: televisions, notebook computers, desktop monitors, tablet computers, digital cameras, smart phones Rings, smart glasses, vehicle-mounted displays, medical equipment, industrial control equipment, touch interactive terminals, etc.
  • the embodiments of this application do not specifically limit this.

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Abstract

本申请公开了一种显示面板及显示装置，显示面板包括：多条信号走线，至少部分多条信号走线中，两条信号走线并排延伸形成信号走线组；相邻信号走线组之间的最小距离大于同一信号走线组内两条信号走线之间的最大距离，和/或，至少一组信号走线组包括弯折段。降低相邻信号走线组之间的电容干扰，减小信号走线之间的电容差异，进而保证显示面板的显示效果，且采用弯折段还可以缩短信号走线组的延伸长度，节省布线空间。

Description

显示面板及显示装置
本申请要求于2022年06年15日提交中国专利局、申请号202210674469.8、申请名称为“显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于电子产品技术领域，尤其涉及一种显示面板及显示装置。
背景技术
目前LTPS(Low Temperature Poly-Silicon，低温多晶硅)领域的中小尺寸面板普遍采用7T1C像素电路进行阈值电压内部补偿，使用的薄膜晶体管数量较多，不利于向更高的PPI方向发展。另外对于屏下的应用，需要较高的透光性能摄像头，传统的7T1C电路，透光性能差，不能实现主副屏的同质显示；而采用外部补偿方式，可以减小面板内的薄膜晶体管数量，可以实现高PPI和屏下应用。
但受到现有的外部补偿电路的布线方式限制，检测到的阈值电压不准确，导致显示画面出现问题。
因此，亟需一种新的显示面板及显示装置。
发明内容
本申请实施例提供了一种显示面板及显示装置，降低相邻信号走线组之间的电容干扰，减小信号走线之间的电容差异，进而保证显示面板的显示效果。
本申请实施例一方面提供了多条信号走线，至少部分所述多条信号走线中，两条所述信号走线并排延伸形成信号走线组；相邻所述信号走线组之间的最小距离大于同一所述信号走线组内两条信号走线之间的最大距离； 和/或，至少一组所述信号走线组包括弯折段。
根据本申请的一个方面，同一所述信号走线组内两条所述信号走线之间的距离处处相等。
根据本申请的一个方面，至少一组所述信号走线组包括相接的弯折段和直线段，各所述信号走线的弯折段和直线段的走线长度之和均相等。
根据本申请的一个方面，至少一组所述信号走线组的弯折段呈蛇形走线设置。
根据本申请的一个方面，相邻两组所述信号走线组的所述直线段之间的最小距离大于相邻两组所述信号走线组的所述弯折段之间的最小距离。
根据本申请的一个方面，相邻两组所述信号走线组的所述直线段之间的最小距离大于或者等于单根所述直线段走线宽度的两倍；优选的，相邻两组所述信号走线组的所述直线段之间的最小距离等于单根所述直线段走线宽度的三倍；优选的，单根所述直线段走线宽度为2μm～3μm；优选的，所述相邻两组所述信号走线组的所述直线段之间的最小距离为6μm～9μm。
根据本申请的一个方面，所述显示面板包括扇出区，所述扇出区包括中间走线区和边缘走线区，所述边缘走线区位于所述中间走线区在垂直于走线延伸方向上的两侧；在所述中间走线区，各所述信号走线组的所述弯折段的走线长度大于所述直线段的走线长度；在所述边缘走线区，各所述信号走线组的所述弯折段的走线长度小于所述直线段的走线长度。
根据本申请的一个方面，还包括沿所述显示面板的厚度方向层叠设置的基板、第一金属层和第二金属层，所述第二金属层包括多个导电块，所述信号走线和所述第一金属层同层设置；沿所述显示面板的厚度方向上，所述导电块在所述基板上的正投影和所述信号走线在所述基板上的正投影至少部分重叠，在单个所述导电块和所述信号走线在所述基板上正投影的重叠区域内，各所述信号走线组的走线长度相等。
根据本申请的一个方面，还包括外部电路和像素驱动电路，所述外部电路和所述像素驱动电路电连接；各所述信号走线分别和不同的所述外部电路电连接。
本申请实施例另一方面提供了一种显示装置，包括：上述任一实施例 中的显示面板。
与现有技术相比，本申请实施例所提供的显示面板包括多条信号走线，至少部分多条信号走线中，两条信号走线并排延伸形成信号走线组，由于各信号走线所采用的材料相同，即阻抗相同，根据电容的计算规则，距离越大，则电容越小，在相邻信号走线组之间的最小距离设置为大于同一信号走线组内两条信号走线之间的最大距离时，能够使相邻信号走线组之间电容小于同一信号走线组内两条信号走线之间的电容，降低相邻信号走线组之间的电容干扰，减小信号走线之间的电容差异，进而保证显示面板的显示效果。而在至少一组信号走线组包括弯折段时，能够增大信号走线组的两条信号走线之间的交叠面积，弯折段所产生的电容相对增大，可以通过调整弯折段的走线长度调整各信号走线组之间的电容差异，且采用弯折段还可以缩短信号走线组的延伸长度，节省布线空间。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单地介绍，显而易见地，下面所描述的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是一种外部电路的电路图；
图2是本申请一种实施例提供的显示面板的结构示意图；
图3是图2中B处一种实施例的局部放大图；
图4是本申请一种实施例提供的弯折段的结构示意图；
图5是图2中C处一种实施例的局部放大图；
图6是图2中C处另一种实施例的局部放大图；
图7是图6中D-D处一种实施例的膜层结构图。
附图中：
1-控制芯片；2-信号走线；21-弯折段；22-直线段；3-导电块；M1-第一金属层；M2-第二金属层；A1-中间走线区；A2-边缘走线区；Y-第一方向；X-第二方向。
具体实施方式
下面将详细描述本申请的各个方面的特征和示例性实施例，为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及具体实施例，对本申请进行进一步详细描述。应理解，此处所描述的具体实施例仅被配置为解释本申请，并不被配置为限定本申请。对于本领域技术人员来说，本申请可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本申请的示例来提供对本申请更好的理解。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
应当理解，在描述部件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将部件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
在不脱离本申请的精神或范围的情况下，在本申请中能进行各种修改和变化，这对于本领域技术人员来说是显而易见的。因而，本申请意在覆盖落入所对应权利要求(要求保护的技术方案)及其等同物范围内的本申请的修改和变化。需要说明的是，本申请实施例所提供的实施方式，在不矛盾的情况下可以相互组合。
在相关技术中，使用低温多晶硅或者氧化物制作的晶体管在使用的过程中均会发生阈值电压Vth漂移的现象，例如氧化物半导体中的照光、源 漏电极电压应力作用等因素，都可能导致阈值电压漂移，导致通过发光元件的电流与所需的电流不一致，显示面板的显示均匀度也得不到满足。
为解决上述问题，可以采用外部电路对像素驱动电路的驱动晶体管进行阈值电压补偿，如图1所示，图1是一种外部电路的电路图。各个外部电路分别和不同的信号线Date/Sense连接，补偿时，首先需要通过信号线Date/Sense对电容Cdata进行充电，以使电容Cdata达到VDD+Vth电压，由于VDD为常数，因而可以测得Vth，最后根据测得的Vth对像素驱动电路的驱动晶体管进行电压补偿。经由申请人研究发现，受到现有的信号线Date/Sense和控制芯片连接时的布线形式限制，现有技术中的各信号线Date/Sense之间的电容差异较大，进而导致各信号线Date/Sense对电容Cdata进行充电时，在相同的充电时间内，不同的外部电路中电容Cdata所达到VDD+Vth电压的值存在差异，进而导致所测得的Vth值不准确，各个外部电路对各像素驱动电路的驱动晶体管的电压补偿值也存在较大差异，导致显示画面出现问题。
本申请实施例提供了一种显示面板及显示装置，以下将结合附图2至图7对显示面板及显示装置的各实施例进行说明。
请参阅图2至图5，图2是本申请一种实施例提供的显示面板的结构示意图；图3是图2中B处一种实施例的局部放大图；图4是本申请一种实施例提供的弯折段的结构示意图；图5是图2中C处一种实施例的局部放大图。
本申请实施例提供的一种显示面板，包括多条信号走线2，至少部分多条信号走线2中，两条信号走线2并排延伸形成信号走线组；相邻信号走线组之间的最小距离b大于同一信号走线组内两条信号走线2之间的最大距离a；和/或，至少一组信号走线组包括弯折段21。
本申请实施例所提供的显示面板包括信号走线2，两条信号走线2并排延伸形成信号走线组，由于各信号走线2所采用的材料相同，即阻抗相同，根据电容的计算规则，距离越大，则电容越小，在相邻信号走线组之间的最小距离b设置为大于同一信号走线组内两条信号走线2之间的最大距离a时，能够使相邻信号走线组之间电容小于同一信号走线组内两条信 号走线2之间的电容，降低相邻信号走线组之间的电容干扰，减小信号走线2之间的电容差异，进而保证显示面板的显示效果。而在至少一组信号走线组包括弯折段21时，弯折段21能够增大信号走线组的两条信号走线2之间的交叠面积，弯折段21所产生的电容相对增大，可以通过调整弯折段21的走线长度调整各信号走线组之间的电容差异，且采用弯折段21还可以缩短信号走线组的延伸长度，节省布线空间。
需要说明的是，至少部分多条信号走线2中，两条信号走线2并排延伸形成信号走线组，即信号走线2部分可以不形成信号走线组，部分形成信号走线组。信号走线组可以设置弯折段，也可以不设置弯折段。
在本申请的部分实施例中，显示面板包括扇出区，扇出区包括中间走线区A1和边缘走线区A2，边缘走线区A2位于中间走线区A1在垂直于走线延伸方向上的两侧，位于边缘走线区A2的信号走线2可以全部形成信号走线组，也可以部分形成信号走线组，且使相邻信号走线组之间的最小距离b大于同一信号走线组内两条信号走线2之间的最大距离a，以降低相邻信号走线组之间的电容干扰，具体可以根据位于边缘走线区A2的信号走线2的电容差异大小进行选择。
而位于中间走线区A1的可以并排延伸形成信号走线组，且至少一组信号走线组包括弯折段21，弯折段21能够增大信号走线间的电容，可以通过调整弯折段21的走线长度调整各信号走线组之间的电容差异，也可以缩短信号走线组在中间走线区A1的延伸长度，节省布线空间。
本实施例中相邻信号走线组之间的最小距离b大于同一信号走线组内两条信号走线2之间的最大距离a的设置方式以及至少一组信号走线组包括弯折段21的设置方式两者可以同时应用于信号走线2，也可以单独应用于信号走线2，例如位于不同位置的信号走线2，只要能够减小信号走线2之间的电容差异，保证显示面板的显示效果即可，并无特殊限定。
可选的，显示面板还包括控制芯片1，各信号走线2分别和控制芯片1电连接，控制芯片1可以通过信号走线2为外部电路提供信号，信号走线2可以为外部电路所对应的控制芯片1的扇出线，控制芯片1也可以为显示面板的内部补偿电路或者像素驱动电路提供信号控制，即信号走线2 也可以为内部补偿电路或者像素驱动电路的扇出线或者其他走线，本申请实施例是针对于信号走线2的布线方式的改进，对于信号走线2的应用场景并无特殊限定。
在一些可选的实施例中，同一信号走线组内两条信号走线2之间的距离处处相等，由于各信号走线2所采用的材料相同，即阻抗相同，通过使距离处处相等，即可实现同一信号走线组内两条信号走线2之间的电容处处相等，提高同一信号走线组内两条信号走线2的电容一致性。
请参阅图3和图5，在一些可选的实施例中，信号走线组包括相接的弯折段21和直线段22，各信号走线组的弯折段21和直线段22的走线长度之和均相等。
可以理解的是，各信号走线组的弯折段21和直线段22的走线长度之和均相等，以保证各信号走线组的各条信号走线2具有相同的阻抗，而不会因为各信号走线组的弯折段21和直线段22的走线长度的占比不同而导致阻抗不同，便于在阻抗相同的条件下调整各信号走线组的电容。
具体的，电容的计算规则如下：
电容C＝k×S/d；其中，k为走线间介质的介电常数，S为两走线的正对面积，d为两走线间的距离。
通过同一信号走线组内的两条信号走线2的弯折段21至少弯折两次，能够有效增大两条信号走线2之间的正对面积S，进而增大电容C。
可选的，各信号走线组的弯折段21可以呈蛇形走线设置，呈蛇形的弯折段21由于弯折所形成的不同弯折段之间相对设置，即增大两条信号走线2之间的正对面积S，进而能够产生额外的电容，增大弯折段21所产生的电容。
在一些可选的实施例中，弯折段21沿第一方向Y延伸，如图3所示，能够更好的利用走线空间。可选的，弯折段21沿第二方向X延伸，第二方向X和第一方向Y相交，如图4所示，第二方向X可以和第一方向Y相垂直，并无特殊限定。
蛇形走线具体可以由直线形成，各直线在弯折处的弯折角为直角，如图2所示，蛇形走线也可以为曲线段，即弯折段21可以由弯曲多次的曲 线形成，并无特殊限定。
除了上述蛇形走线的形式，各信号走线组的弯折段21还可以采用由多段直线弯折所形成的折线段，类似于“Z”型走线或者其他无规律的折线段，根据弯折段21所需的走线长度可以选择折线段的弯折次数以及弯折角度。
在一些可选的实施例中，相邻两组信号走线组的直线段22之间的最小距离大于相邻两组信号走线组的弯折段21之间的最小距离，即通过增大两走线间的距离d以减小信号走线组在直线段22的电容，便于调整各信号走线组之间的电容差异。在本实施例中，可选的，直线段22的延伸方向和第一方向Y之间的夹角呈锐角，即各直线段22呈倾斜线分布，以便于各直线段22向控制芯片1所在位置收拢，和控制芯片1电连接。
在一些可选的实施例中，显示面板包括扇出区，扇出区包括中间走线区A1和边缘走线区A2，边缘走线区A2位于中间走线区A1在垂直于走线延伸方向上的两侧；在中间走线区A1，各信号走线组的弯折段21的走线长度大于直线段22的走线长度；在边缘走线区A2，各信号走线组的弯折段21的走线长度小于直线段22的走线长度。
需要说明的是，受到控制芯片1设置位置的限制，边缘走线区A2的信号走线组需要由两侧倾斜向至中间延伸，以便于和控制芯片1连接，而中间走线区A1的信号走线组的倾斜角度相对较小或者直接沿第一方向Y竖直延伸，是为了使中间走线区A1的信号走线组的走线长度等于边缘走线区A2的信号走线组的走线长度，在本实施例中，在中间走线区A1中，各信号走线组的弯折段21的走线长度大于或者等于直线段22的走线长度；以降低因中间走线区A1、边缘走线区A2的走线长度而导致的阻抗差异，进而降低中间走线区A1、边缘走线区A2的电容差异。进一步的，边缘走线区A2中的信号走线组包括弯折段21，各信号走线组的弯折段21的走线长度小于直线段22的走线长度，以降低中间走线区A1、边缘走线区A2的电容差异。
进一步的，通常在中间走线区A1，各信号走线组的弯折段21的走线长度大于直线段22的走线长度；在边缘走线区A2，各信号走线组的弯折 段21的走线长度小于直线段22的走线长度，即在中间走线区A1，弯折段21的电容占主要影响地位，在边缘走线区A2，直线段22的电容占主要影响地位，在现有技术中由于中间走线区A1采用单根走线形成蛇形走线以减小走线在其延伸方向上的长度，该结构在弯折段21不会产生额外电容，导致中间走线区A1的走线的电容小于边缘走线区A2的走线的电容，造成电容差异。
为了降低中间走线区A1和边缘走线区A2的电容差异，本申请实施例通过使两条信号走线2并排延伸形成信号走线组，信号走线组包括弯折段21以产生额外电容，即增大中间走线区A1的电容。具体的，由于各信号走线2所采用材料相同，即各信号走线2的单位阻抗相同，且各信号走线2的弯折段21和直线段22的走线长度之和均相等，根据上述的电容的计算规则：电容C＝k×S/d，通过将弯折段21设置为蛇形走线的布线形式，能够增大弯折段21的两条信号走线2之间的交叠面积，进而增大弯折段21的电容，且节省布线空间。
同时，还可以通过增加相邻两组信号走线组的直线段22之间的最小距离，即增大两走线间的距离d能够减小信号走线组在直线段22的电容，通过增大弯折段21电容的方式和减小直线段22的电容的方式相结合，以降低中间走线区A1和边缘走线区A2的信号走线组之间的电容差异。
可选的，显示面板还包括外部电路和像素驱动电路，外部电路和像素驱动电路电连接；各信号走线2分别和不同的外部电路电连接。
即上述的布线形式应用于外部电路后，由于各信号走线2之间的电容差异减小，通过各信号走线2对电容Cdata进行充电时，在相同的充电时间内，不同的外部电路中电容Cdata所达到VDD+Vth电压的值的差异减小，提高了所测得的Vth值的准确性，各个外部电路对各像素驱动电路的驱动晶体管的电压补偿值的差异也随之减小，进而提高了显示面板的显示效果。
经过申请人实验测得，在采用现有信号走线2布线形式时，各信号走线2之间的电容范围为25pf～35pf，在充电时间为1ms时，Cdata的电压范围为1.709V～1.870V，所测得的Vth的差值范围为-100mV～100mV，在充 电时间为18ms时，Cdata的电压范围为2.764V～2.846V，所测得的Vth的差值范围为-50mV～50mV。
而本申请实施例中的各信号走线2之间的电容范围为28.5pf～31.5pf，在充电时间为1ms时，Cdata的电压范围为1.762V～1.810V，所测得的Vth的差值范围为-25mV～25mV，在充电时间为18ms时，Cdata的电压范围为2.788V～2.813V，所测得的Vth的差值范围为-15mV～15mV。
通过对比上述数据，可以得到采用本申请实施例中信号走线2能够有效减小各信号走线2之间的电容范围，且不论是在充电时间为1ms时还是在充电时间为18ms时，相比于现有技术，本申请实施例中的Cdata的电压范围、所测得的Vth的差值范围均明显减小，提高了各个外部电路对各像素驱动电路的驱动晶体管的电压补偿值准确性，进而提高了显示面板的显示效果。
可选的，相邻两组信号走线组的直线段22之间的最小距离大于或者等于单根直线段22走线宽度的两倍，以保证相邻两组信号走线组的直线段22之间的电容值明显降低，满足平衡位于中间走线区A1和位于边缘走线区A2的信号走线组之间的电容差异的需求；在本实施例中，具体的，当同一信号走线组内的两条信号走线2之间的最小距离等于单根信号走线2的宽度时，相邻两组信号走线组的直线段22之间的最小距离可以等于单根直线段22走线宽度的三倍，即在相邻两组信号走线组的直线段22之间预留一根信号走线2的空间，便于设置。
可选的，单根直线段22走线宽度为2μm～3μm，相邻两组信号走线组的直线段22之间的最小距离为6μm～9μm。通过调整相邻两组信号走线组的直线段22之间的最小距离以调整电容的大小。当然，单根直线段22走线宽度和相邻两组信号走线组的直线段22之间的最小距离并不局限于上述数值范围，可以根据降低信号走线2的电容差异的需求进行选择。
需要说明的是，除了各信号走线2之间可以产生电容外，信号走线2和相邻的显示面板的其他导电层之间也会产生电容。
请参阅图6和图7，图6是图2中C处另一种实施例的局部放大图；图7是图6中D-D处一种实施例的膜层结构图。显示面板还包括沿显示面 板的厚度方向层叠设置的基板、第一金属层M1和第二金属层M2，第二金属层M2包括多个导电块3，信号走线2和第一金属层M1同层设置；沿显示面板的厚度方向上，导电块3在基板上的正投影和信号走线2在基板上的正投影至少部分重叠，在单个导电块3和信号走线2在基板上正投影的重叠区域内，各信号走线组的走线长度相等。
需要说明的是，由于各信号走线2和第一金属层M1同层设置；即各信号走线2和第二金属层M2之间的垂直距离均相等，且各信号走线2之间的走线宽度以及单位阻抗均相等，因而，影响各信号走线2和第二金属层M2的导电块3之间电容的参数仅为信号走线2和单个导电块3的交叠部分的长度，在本实施例中，通过限定沿显示面板的厚度方向上，在单个导电块3和信号走线2在基板上正投影的重叠区域内，各信号走线组的走线长度相等，以保证各信号走线组和导电块3的正对电容相等，进而降低了各信号走线组在沿显示面板的厚度方向上和导电块3之间的电容差异。可选的，各导电块3的形状可以为三角形、梯形等多边形或者椭圆形、圆形等包括曲边的形状。第二金属层M2具体可以为VDD正性电压走线、VSS负性电压走线的走线层。
本申请实施例还提供了一种显示装置，包括：上述任一实施例中的显示面板。
本申请实施例提供的显示装置可以应用于手机，也可以为任何具有显示功能的电子产品，包括但不限于以下类别：电视机、笔记本电脑、桌上型显示器、平板电脑、数码相机、智能手环、智能眼镜、车载显示器、医疗设备、工控设备、触摸交互终端等，本申请实施例对此不作特殊限定。
以上，仅为本申请的具体实施方式，所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的***、模块和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。应理解，本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。
还需要说明的是，本申请中提及的示例性实施例，基于一系列的步骤或者装置描述一些方法或***。但是，本申请不局限于上述步骤的顺序， 也就是说，可以按照实施例中提及的顺序执行步骤，也可以不同于实施例中的顺序，或者若干步骤同时执行。

Claims (10)

  1. 一种显示面板，包括：多条信号走线，至少部分所述多条信号走线中，两条所述信号走线并排延伸形成信号走线组；
    相邻所述信号走线组之间的最小距离大于同一所述信号走线组内两条信号走线之间的最大距离；和/或，
    至少一组所述信号走线组包括弯折段。
  2. 根据权利要求1所述的显示面板，其中，同一所述信号走线组内两条所述信号走线之间的距离处处相等。
  3. 根据权利要求1所述的显示面板，其中，至少一组所述信号走线组包括相接的所述弯折段和直线段，各所述信号走线组的弯折段和直线段的走线长度之和均相等。
  4. 根据权利要求3所述的显示面板，其中，至少一组所述信号走线组的弯折段呈蛇形走线设置。
  5. 根据权利要求3所述的显示面板，其中，相邻两组所述信号走线组的所述直线段之间的最小距离大于相邻两组所述信号走线组的所述弯折段之间的最小距离。
  6. 根据权利要求3所述的显示面板，其中，相邻两组所述信号走线组的所述直线段之间的最小距离大于或者等于单根所述直线段走线宽度的两倍；
    优选的，相邻两组所述信号走线组的所述直线段之间的最小距离等于单根所述直线段走线宽度的三倍；
    优选的，单根所述直线段走线宽度为2μm～3μm；
    优选的，所述相邻两组所述信号走线组的所述直线段之间的最小距离为6μm～9μm。
  7. 根据权利要求4所述的显示面板，其中，所述显示面板包括扇出区，所述扇出区包括中间走线区和边缘走线区，所述边缘走线区位于所述中间走线区在垂直于走线延伸方向上的两侧；
    在所述中间走线区，各所述信号走线组的所述弯折段的走线长度大于或者等于所述直线段的走线长度；
    在所述边缘走线区，各所述信号走线组的所述弯折段的走线长度小于所述直线段的走线长度。
  8. 根据权利要求1所述的显示面板，其中，还包括沿所述显示面板的厚度方向层叠设置的基板、第一金属层和第二金属层，所述第二金属层包括多个导电块，所述信号走线和所述第一金属层同层设置；
    沿所述显示面板的厚度方向上，所述导电块在所述基板上的正投影和所述信号走线在所述基板上的正投影至少部分重叠，在单个所述导电块和所述信号走线在所述基板上正投影的重叠区域内，各所述信号走线组的走线长度相等。
  9. 根据权利要求1所述的显示面板，其中，还包括外部电路和像素驱动电路，所述外部电路和所述像素驱动电路电连接；
    各所述信号走线分别和不同的所述外部电路电连接。
  10. 一种显示装置，其中，包括：权利要求1至9任一项所述的显示面板。
PCT/CN2022/114847 2022-06-15 2022-08-25 显示面板及显示装置 WO2023240796A1 (zh)

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009122318A (ja) * 2007-11-14 2009-06-04 Hitachi Displays Ltd 表示装置
CN101893962A (zh) * 2010-07-08 2010-11-24 友达光电股份有限公司 触控显示器及其触控显示基板
CN104969283A (zh) * 2013-02-26 2015-10-07 夏普株式会社 显示装置
CN107357105A (zh) * 2017-09-05 2017-11-17 京东方科技集团股份有限公司 一种阵列基板、显示面板、显示装置
CN109643525A (zh) * 2017-05-23 2019-04-16 京东方科技集团股份有限公司 具有多条第一接线和多条第二接线的显示面板和显示装置
CN111696461A (zh) * 2020-06-30 2020-09-22 武汉天马微电子有限公司 一种显示面板和显示装置
CN111812898A (zh) * 2019-04-01 2020-10-23 三星显示有限公司 显示装置、光掩模和显示装置的制造方法
CN114446997A (zh) * 2022-01-17 2022-05-06 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置
CN114937673A (zh) * 2022-06-15 2022-08-23 昆山国显光电有限公司 显示面板及显示装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009122318A (ja) * 2007-11-14 2009-06-04 Hitachi Displays Ltd 表示装置
CN101893962A (zh) * 2010-07-08 2010-11-24 友达光电股份有限公司 触控显示器及其触控显示基板
CN104969283A (zh) * 2013-02-26 2015-10-07 夏普株式会社 显示装置
CN109643525A (zh) * 2017-05-23 2019-04-16 京东方科技集团股份有限公司 具有多条第一接线和多条第二接线的显示面板和显示装置
CN107357105A (zh) * 2017-09-05 2017-11-17 京东方科技集团股份有限公司 一种阵列基板、显示面板、显示装置
CN111812898A (zh) * 2019-04-01 2020-10-23 三星显示有限公司 显示装置、光掩模和显示装置的制造方法
CN111696461A (zh) * 2020-06-30 2020-09-22 武汉天马微电子有限公司 一种显示面板和显示装置
CN114446997A (zh) * 2022-01-17 2022-05-06 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置
CN114937673A (zh) * 2022-06-15 2022-08-23 昆山国显光电有限公司 显示面板及显示装置

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