WO2023226083A1 - 像素驱动电路、像素驱动方法和显示面板 - Google Patents

像素驱动电路、像素驱动方法和显示面板 Download PDF

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Publication number
WO2023226083A1
WO2023226083A1 PCT/CN2022/097381 CN2022097381W WO2023226083A1 WO 2023226083 A1 WO2023226083 A1 WO 2023226083A1 CN 2022097381 W CN2022097381 W CN 2022097381W WO 2023226083 A1 WO2023226083 A1 WO 2023226083A1
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Prior art keywords
thin film
film transistor
signal
node
potential
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PCT/CN2022/097381
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English (en)
French (fr)
Inventor
刘斌
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惠州华星光电显示有限公司
Tcl华星光电技术有限公司
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Publication of WO2023226083A1 publication Critical patent/WO2023226083A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/046—Dealing with screen burn-in prevention or compensation of the effects thereof

Definitions

  • the present application belongs to the field of display technology, and in particular relates to a pixel driving circuit, a pixel driving method and a display panel.
  • mini LEDs Mini LEDs
  • micro LEDs Micro LEDs
  • organic light-emitting diodes OLEDs
  • the traditional passive matrix driving method (Passive Matrix, PM) requires very large transient currents and has high requirements on power supply and power consumption.
  • the active matrix driving method (Active Matrix, AM) uses thin film transistor (TFT) switches and capacitor progressive scanning to light up LEDs, which can effectively avoid the problem of large transient current.
  • the threshold voltage of the driving thin film transistor will shift, thereby causing the attenuation of the current of the light-emitting device.
  • Embodiments of the present application provide a pixel driving circuit, a pixel driving method and a display panel to solve the problem that in the existing AM driving method, due to long-term operation, the threshold voltage of the driving thin film transistor will shift, thereby causing the current attenuation of the light-emitting device. The problem.
  • embodiments of the present application provide a pixel driving circuit, including a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, and a seventh thin film transistor.
  • a first capacitor, a second capacitor and a light-emitting device the first thin film transistor is used as a driving thin film transistor of the light-emitting device;
  • the gate of the first thin film transistor is electrically connected to the first node, and the drain is electrically connected to the second node;
  • the gate of the second thin film transistor is connected to the first scan signal, the source is connected to the data signal, and the drain is electrically connected to the first node;
  • the gate of the third thin film transistor is connected to the light emitting control signal, and the drain is electrically connected to the source of the first thin film transistor;
  • the gate of the fourth thin film transistor is connected to the light emitting control signal, the source is electrically connected to the second node, and the drain is connected to the common ground voltage;
  • the gate of the fifth thin film transistor is connected to the second scan signal, the source is connected to the first node, and the drain is electrically connected to the drain of the third thin film transistor;
  • the gate of the sixth thin film transistor is connected to the third scan signal, the source is connected to the power supply voltage, and the drain is electrically connected to the first node;
  • the gate of the seventh thin film transistor is connected to the fourth scan signal, the source is connected to the reference signal, and the drain is electrically connected to the second node;
  • One end of the first capacitor is electrically connected to the first node, and the other end is electrically connected to the second node;
  • One end of the second capacitor is electrically connected to the first node, and the other end is electrically connected to the drain of the second thin film transistor;
  • the anode of the light-emitting device is connected to the power supply voltage, and the cathode is electrically connected to the source of the third thin film transistor.
  • embodiments of the present application further provide a pixel driving method, which is applied to a pixel driving circuit.
  • the pixel driving circuit includes: a first thin film transistor, with a gate electrically connected to the first node and a drain electrically connected to the second node.
  • the second thin film transistor is connected to the first scanning signal, the source is connected to the data signal, and the drain is electrically connected to the first node;
  • the third thin film transistor is connected to the light-emitting control signal, and the drain is electrically connected to the first node;
  • the source of the fourth thin film transistor is electrically connected to the source of the first thin film transistor;
  • the gate of the fourth thin film transistor is connected to the light-emitting control signal, the source is electrically connected to the second node, and the drain is connected to the common ground voltage;
  • the gate of the fifth thin film transistor is connected to the light-emitting control signal.
  • the electrode of the sixth thin film transistor is connected to the second scanning signal, the source is connected to the first node, and the drain is electrically connected to the drain of the third thin film transistor; the gate of the sixth thin film transistor is connected to the third scanning signal, and the source is connected to The power supply voltage is input, the drain is electrically connected to the first node; the seventh thin film transistor, the gate is connected to the fourth scanning signal, the source is connected to the reference signal, and the drain is electrically connected to the second node; the first capacitor , one end is connected to the first node, and the other end is connected to the second node; a second capacitor, one end is connected to the first node, and the other end is connected to the drain of the second thin film transistor; and a light-emitting device, the anode is connected power supply voltage, the cathode is connected to the source of the third thin film transistor, and the light emitting device is driven by the first thin film transistor;
  • the pixel driving method includes:
  • the first scanning signal, the third scanning signal and the fourth scanning signal are controlled to be high potential, and the second scanning signal, the light emitting control signal and the data signal are all low.
  • the potential is such that the first node potential is the power supply voltage and the second node potential is the reference signal;
  • the first scan signal, the second scan signal and the fourth scan signal are all controlled to be at high potential, and the third scan signal, the luminescence control signal and the data signal are all at high potential. is a low potential, so that the first node potential is the sum of the reference signal and the threshold voltage, and the second node potential is the reference signal;
  • the first scanning signal, the fourth scanning signal and the data signal are all controlled to be at a high potential
  • the second scanning signal, the third scanning signal and the light emission control signal are all at a high level.
  • the light-emitting control signal is controlled to be at a high potential, and the first scanning signal, the second scanning signal, the third scanning signal, the fourth scanning signal and the data signal are all at a low potential.
  • the potential of the second node is the ground voltage
  • the potential of the first node is the sum of the difference between the high potential and the low potential of the data signal and the threshold voltage and the ground voltage.
  • embodiments of the present application further provide a display panel, including the pixel driving circuit as described in any one of the above.
  • a 7T2C pixel driving circuit is used to control the scanning signal, luminescence signal and data signal respectively in the initialization stage, threshold voltage extraction stage, data writing stage and light emitting stage.
  • the threshold voltage of the driving thin film transistor in each pixel can be compensated, thereby eliminating the influence of the threshold voltage of the driving thin film transistor on the current flowing through the light-emitting device, and improving the display uniformity of the display panel.
  • the impact of at least part of the communication signal line voltage drop on the display panel can be eliminated.
  • FIG. 1 is a schematic side structural view of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a pixel driving circuit in the display panel shown in FIG. 1 .
  • FIG. 3 is a timing diagram of a pixel driving circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic path diagram of the initialization stage of the pixel driving circuit provided by the embodiment of the present application under the driving timing sequence shown in FIG. 3 .
  • FIG. 5 is a schematic path diagram of the threshold voltage extraction stage of the pixel driving circuit provided by the embodiment of the present application under the driving timing shown in FIG. 3 .
  • FIG. 6 is a schematic path diagram of the data writing stage of the pixel driving circuit provided by the embodiment of the present application under the driving timing shown in FIG. 3 .
  • FIG. 7 is a schematic path diagram of the light emitting stage of the pixel driving circuit provided by the embodiment of the present application under the driving timing sequence shown in FIG. 3 .
  • FIG. 8 is a schematic flowchart of a pixel driving method provided by an embodiment of the present application.
  • embodiments of the present application provide a pixel driving circuit, a pixel driving method and a The display panel will be described below with reference to the accompanying drawings.
  • FIG. 1 is a schematic side structural view of a display panel provided by an embodiment of the present application.
  • the embodiment of the present application provides a display panel 1.
  • the display panel 1 may include a pixel layer 20, a light-emitting layer, a driving circuit layer and an array substrate stacked in sequence.
  • the driving circuit layer is arranged on the array substrate.
  • the pixel layer 20 may include a plurality of pixels arranged in an array, and the light-emitting layer is provided with a light-emitting device D corresponding to each pixel.
  • the driving circuit layer may include a plurality of pixel driving circuits 10, each pixel is configured with a pixel driving circuit 10, and the pixel driving circuit 10 is used to drive the light-emitting device D of the corresponding pixel to emit light.
  • the light-emitting device D may be an organic light-emitting diode.
  • Organic light-emitting diode also known as organic electric laser display and organic light-emitting semiconductor, refers to the phenomenon that organic semiconductor materials and light-emitting materials cause light emission through carrier injection and recombination under the driving of electric field.
  • the light-emitting device D may also be a mini-light-emitting diode, or the light-emitting device D may be a micro-light-emitting diode.
  • the embodiment of this application takes the light-emitting device D as an organic light-emitting diode as an example for description.
  • the traditional passive matrix driving method requires a very large transient current and has high requirements on power supply and power consumption.
  • the active matrix driving method uses thin film transistor switches and capacitor progressive scanning to light up the LED, which can effectively avoid the problem of large transient current.
  • ID represents the current flowing through the driving thin film transistor and the light-emitting device D
  • K is the intrinsic conductivity factor of the driving thin film transistor
  • Vgs represents the voltage difference between the gate and source of the driving thin film transistor
  • Vth represents the driving thin film transistor. threshold voltage. It can be seen that the size of ID is related to the threshold voltage Vth of the driving thin film transistor. Due to long-term operation, the threshold voltage of the driving thin film transistor that drives the light-emitting device D to emit light will shift, thereby causing an attenuation of the current of the light-emitting device. In addition, the voltage drop of the signal lines in the display panel will also cause current differences between the light-emitting devices of the display panel, causing macroscopically visible moiré or unevenness.
  • the embodiment of the present application improves the pixel driving circuit 10.
  • the pixel driving circuit 10 will be described below with reference to the accompanying drawings.
  • FIG. 2 is a schematic structural diagram of the pixel driving circuit in the display panel shown in FIG. 1.
  • the pixel driving circuit 10 in the embodiment of the present application includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, and a seventh thin film transistor.
  • the first thin film transistor T1 may be used as a driving thin film transistor of the light emitting device D.
  • the second thin film transistor T2 is a data writing thin film transistor.
  • the third thin film transistor T3 and the fourth thin film transistor T4 may be used to emit light.
  • the fifth thin film transistor T5 and the sixth thin film transistor T6 may be used in the detection stage of the threshold voltage Vth of the first thin film transistor T1.
  • the seventh thin film transistor T7 can be used for charge clearing of the second node S.
  • the first capacitor C1 may be a storage capacitor, and the second capacitor C2 may be used to write data voltage.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6 and the seventh thin film transistor T7 are all oxide semiconductor thin film transistors.
  • low-temperature polysilicon thin film transistors or amorphous silicon thin film transistors that is, the types of thin film transistors T1 to T7 can all be indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), low temperature polysilicon (Low Temperature Poly-silicon, LTPS) or amorphous silicon (A-Si) type.
  • IGZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Poly-silicon
  • A-Si amorphous silicon
  • different types of thin film transistors can also be used for the thin film transistors T1 to T7 respectively, and there are many combination methods, which will not be described again here.
  • LTPS type thin film transistors can be divided into two structures: N-type and P-type.
  • the N-type TFT uses a lightly doped drain (Lightly Doped Drain, LDD) to reduce the leakage current of the component. Therefore, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6 and the seventh thin film transistor T7 may all be N-type TFTs. .
  • LDD Lightly Doped Drain
  • the gate of the first thin film transistor T1 is electrically connected to the first node G, and the drain is electrically connected to the second node S.
  • the gate of the second thin film transistor T2 is connected to the first scan signal SCAN1, the source is connected to the data signal DATA, and the drain is electrically connected to the first node G.
  • the gate of the third thin film transistor T3 is connected to the light emission control signal EM, and the drain is electrically connected to the source of the first thin film transistor T1.
  • the gate of the fourth thin film transistor T4 is connected to the light emission control signal EM, the source is electrically connected to the second node S, and the drain is connected to the common ground voltage VSS.
  • the gate of the fifth thin film transistor T5 is connected to the second scan signal SCAN2, the source is connected to the first node G, and the drain is electrically connected to the drain of the third thin film transistor T3.
  • the gate of the sixth thin film transistor T6 is connected to the third scanning signal SCAN3, the source is connected to the power supply voltage VDD, and the drain is electrically connected to the first node G.
  • the gate of the seventh thin film transistor T7 is connected to the fourth scanning signal SCAN4, the source is connected to the reference signal Ref, and the drain is electrically connected to the second node S.
  • One end of the first capacitor C1 is electrically connected to the first node G, and the other end is electrically connected to the second node S.
  • One end of the second capacitor C2 is electrically connected to the first node G, and the other end is electrically connected to the drain of the second thin film transistor T2.
  • the second capacitor C2 is directly connected to the data signal DATA.
  • the data signal DATA When the data signal DATA is at a high potential, the data signal can be written through coupling without affecting the data storage of the threshold voltage. For example, it can prevent the loss of the stored threshold voltage information.
  • the anode of the light-emitting device D is connected to the power supply voltage VDD, and the cathode is electrically connected to the source of the third thin film transistor T3.
  • the light-emitting device D is set at the power supply voltage VDD, and the voltage value of the scanning signal can be reduced by using the light-emitting device D to divide the voltage, thereby reducing the power consumption of the pixel driving circuit 10 .
  • the embodiment of the present application uses a 7T2C pixel drive circuit 10 to control the scanning signal, light-emitting signal and data signal at different potentials in the initialization stage, threshold voltage extraction stage, data writing stage and light-emitting stage, so that each pixel can be controlled.
  • the threshold voltage of the driving thin film transistor is compensated, thereby eliminating the influence of the threshold voltage of the driving thin film transistor on the current flowing through the light emitting device D, and improving the display uniformity of the display panel 1 .
  • the impact of at least part of the communication signal line voltage drop on the display panel 1 can be eliminated.
  • Figure 3 is a timing diagram of a pixel driving circuit provided by an embodiment of the present application.
  • the combination of the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, the fourth scan signal SCAN4, the light emission control signal EM and the data signal DATA successively corresponds to an initialization phase ST1, a threshold voltage extraction phase ST2, and a A data writing phase ST3 and a lighting phase ST4.
  • FIG. 4 is a schematic diagram of the initialization phase of the pixel driving circuit provided by the embodiment of the present application under the driving timing sequence shown in FIG. 3 .
  • the first scan signal SCAN1, the third scan signal SCAN3 and the fourth scan signal SCAN4 are all high potential
  • the second scan signal SCAN2 the light emission control signal EM and the data signal DATA are all low potential.
  • the potential of the first node G is the power supply voltage VDD
  • the potential of the second node S is the reference signal Ref.
  • the first scan signal SCAN1, the third scan signal SCAN3 and the fourth scan signal SCAN4 turn on the high potential of the second thin film transistor T2, the sixth thin film transistor T6 and the seventh thin film transistor T7 respectively.
  • the second scan signal SCAN2, the light emission control signal EM, and the data signal DATA are all at low potential, that is, the fifth thin film transistor T5, the third thin film transistor T3, and the fourth thin film transistor T4 are all turned off.
  • FIG. 5 is a schematic diagram of the path of the threshold voltage extraction stage of the pixel driving circuit provided by the embodiment of the present application under the driving timing sequence shown in FIG. 3 .
  • the first scan signal SCAN1, the second scan signal SCAN2 and the fourth scan signal SCAN4 are all at high potential
  • the third scan signal SCAN3, the light emission control signal EM and the data signal DATA are at low potential.
  • the potential of the first node G is the sum of the reference signal Ref and the threshold voltage Vth, that is, the potential of the first node G is Ref+Vth.
  • the potential of the second node S is the reference signal Ref.
  • the third scan signal SCAN3 is at a low potential to turn off the sixth thin film transistor T6, and the first scan signal SCAN1, the second scan signal SCAN2 and the fourth scan signal SCAN4 are all at a high potential to turn on the second thin film transistor T6.
  • the thin film transistor T2, the fifth thin film transistor T5, and the seventh thin film transistor T7 form a diode structure.
  • the light emission control signal EM and the data signal DATA are both at low potential, that is, the third thin film transistor T3 and the fourth thin film transistor T4 are both turned off.
  • the potential of the first node G changes from the power supply voltage VDD to the sum of the reference signal Ref and the threshold voltage Vth, Ref+Vth, and the potential of the second node S remains the reference signal Ref.
  • FIG. 6 is a schematic diagram of the data writing stage of the pixel driving circuit provided by an embodiment of the present application under the driving timing sequence shown in FIG. 3 .
  • the second scan signal SCAN2, the third scan signal SCAN3 and the light emission control signal EM are all at low potential
  • the first scan signal SCAN1 and the fourth scan signal SCAN4 are at high potential
  • the data signal DATA is at high potential.
  • the potential of the first node G is the difference between the high potential DATA_H and the low potential DATA_L of the data signal and the sum of the reference signal Ref and the threshold voltage Vth DATA_H-DATA_L+Ref+Vth.
  • the potential of the second node S is the reference signal Ref. It can be understood that during the data writing stage ST3, the second scan signal SCAN2 changes from high potential to low potential, and the fifth thin film transistor T5 is turned off.
  • the first scan signal SCAN1 and the fourth scan signal SCAN4 are at high potential, the second thin film transistor T2 and the seventh thin film transistor T7 are turned on, and the data signal DATA changes from the low potential DATA_L to the high potential DATA_H, so the potential of the first node G becomes DATA_H-DATA_L+Ref+Vth, the potential of the second node S is still the reference signal Ref.
  • FIG. 7 is a schematic path diagram of the light-emitting stage of the pixel driving circuit provided by the embodiment of the present application under the driving timing sequence shown in FIG. 3 .
  • the light-emitting control signal EM is at a high potential, and only the third thin film transistor T3 and the fourth thin film transistor T4 are turned on.
  • the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, the fourth scan signal SCAN4 and the data signal DATA are all low potential, that is, the second thin film transistor T2, the fifth thin film transistor T5, the sixth thin film transistor T6 and the seventh thin film transistor T7 are both turned off.
  • the potential of the second node S is the ground voltage VSS.
  • the potential of the first node G is the difference between the high potential DATA_H and the low potential DATA_L of the data signal and the difference between the threshold voltage Vth and the ground voltage VSS. and DATA_H-DATA_L+Vth+VSS. It can be understood that in the light-emitting stage ST4, only the high-potential light-emitting control signal EM turns on the third thin film transistor T3 and the fourth thin film transistor T4, the other thin film transistors are turned off, and the potential of the second node S changes from the reference signal Ref to the ground voltage VSS.
  • the compensation of Vth further eliminates the influence of the threshold voltage shift of the first thin film transistor T1 on the current flowing through the light-emitting device D.
  • the potential flowing through the first node G and the second node S becomes Vgs, that is, the current flowing through the first node G and the second node S has nothing to do with the ground voltage VSS, thereby realizing the compensation for the voltage drop and eliminating the The influence of the voltage drop of the communication signal line on the display panel 1 is eliminated, thereby improving the display uniformity of the display panel 1 .
  • the detection method of the threshold voltage is a diode connection, but it does not have rectification characteristics like a diode.
  • the characteristics it has are just like when a diode is forward-conducted, that is, It exhibits small signal characteristics like a small resistor.
  • the detection method of the threshold voltage is usually the source follow method.
  • first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, the fourth scan signal SCAN4, the light emission control signal EM and the data signal DATA are all generated by an external timing controller.
  • FIG. 8 is a schematic flowchart of a pixel driving method provided by an embodiment of the present application.
  • the pixel driving method is applied to the pixel driving circuit 10.
  • Pixel driving methods include:
  • the combination of the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, the fourth scan signal SCAN4, the light emission control signal EM and the data signal DATA successively corresponds to an initialization stage ST1 and a threshold voltage.
  • the first scan signal SCAN1, the third scan signal SCAN3 and the fourth scan signal SCAN4 are all high potential
  • the second scan signal SCAN2 the light emission control signal EM and the data signal DATA are all low potential.
  • the potential of the first node G is the power supply voltage VDD
  • the potential of the second node S is the reference signal Ref. It can be understood that at this stage, the first scan signal SCAN1, the third scan signal SCAN3 and the fourth scan signal SCAN4 turn on the high potential of the second thin film transistor T2, the sixth thin film transistor T6 and the seventh thin film transistor T7 respectively.
  • the second scan signal SCAN2, the light emission control signal EM, and the data signal DATA are all at low potential, that is, the fifth thin film transistor T5, the third thin film transistor T3, and the fourth thin film transistor T4 are all turned off.
  • the first scan signal SCAN1, the second scan signal SCAN2 and the fourth scan signal SCAN4 are all at high potential, and the third scan signal SCAN3, the light emission control signal EM and the data signal DATA are at low potential.
  • the potential of the first node G is the sum of the reference signal Ref and the threshold voltage Vth, that is, the potential of the first node G is Ref+Vth.
  • the potential of the second node S is the reference signal Ref.
  • the third scan signal SCAN3 is at a low potential to turn off the sixth thin film transistor T6, and the first scan signal SCAN1, the second scan signal SCAN2 and the fourth scan signal SCAN4 are all at a high potential to turn on the second thin film transistor T6.
  • the thin film transistor T2, the fifth thin film transistor T5, and the seventh thin film transistor T7 form a diode structure.
  • the light emission control signal EM and the data signal DATA are both at low potential, that is, the third thin film transistor T3 and the fourth thin film transistor T4 are both turned off.
  • the potential of the first node G changes from the power supply voltage VDD to the sum of the reference signal Ref and the threshold voltage Vth, Ref+Vth, and the potential of the second node S remains the reference signal Ref.
  • the second scan signal SCAN2, the third scan signal SCAN3 and the light emission control signal EM are all at low potential, the first scan signal SCAN1 and the fourth scan signal SCAN4 are at high potential, and the data signal DATA is at high potential.
  • the potential of the first node G is the difference between the high potential DATA_H and the low potential DATA_L of the data signal and the sum of the reference signal Ref and the threshold voltage Vth DATA_H-DATA_L+Ref+Vth.
  • the potential of the second node S is the reference signal Ref. It can be understood that during the data writing stage ST3, the second scan signal SCAN2 changes from high potential to low potential, and the fifth thin film transistor T5 is turned off.
  • the first scan signal SCAN1 and the fourth scan signal SCAN4 are at high potential, the second thin film transistor T2 and the seventh thin film transistor T7 are turned on, and the data signal DATA changes from the low potential DATA_L to the high potential DATA_H, so the potential of the first node G becomes DATA_H-DATA_L+Ref+Vth, the potential of the second node S is still the reference signal Ref.
  • the light-emitting control signal is controlled to be at a high potential, and the first scanning signal, the second scanning signal, the third scanning signal, the fourth scanning signal and the data signal are all at a low potential, so that the potential of the second node is grounded.
  • Voltage, the potential of the first node is the difference between the high potential and the low potential of the data signal and the sum of the threshold voltage and the ground voltage.
  • the light-emitting control signal EM is at a high potential, and only the third thin film transistor T3 and the fourth thin film transistor T4 are turned on.
  • the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, the fourth scan signal SCAN4 and the data signal DATA are all low potential, that is, the second thin film transistor T2, the fifth thin film transistor T5, the sixth thin film transistor T6 and the seventh thin film transistor T7 are both turned off.
  • the potential of the second node S is the ground voltage VSS.
  • the potential of the first node G is the difference between the high potential DATA_H and the low potential DATA_L of the data signal and the difference between the threshold voltage Vth and the ground voltage VSS.
  • the potential of the first node G is Vgs+VSS. That is to say, the current flowing through the light-emitting device D in the light-emitting stage ST4 has nothing to do with the threshold voltage Vth of the first thin film transistor T1, thus realizing the threshold voltage.
  • the compensation of Vth further eliminates the influence of the threshold voltage shift of the first thin film transistor T1 on the current flowing through the light-emitting device D.
  • the potential flowing through the first node G and the second node S becomes Vgs, that is, the current flowing through the first node G and the second node S has nothing to do with the ground voltage VSS, thereby realizing the compensation for the voltage drop and eliminating the The influence of the voltage drop of the communication signal line on the display panel 1 is eliminated, thereby improving the display uniformity of the display panel 1 .
  • a 7T2C pixel driving circuit 10 is used to control the scanning signal, light emission respectively in the initialization stage, threshold voltage extraction stage, data writing stage and light emitting stage.
  • the signal and the data signal are at different potentials, so that the threshold voltage of the driving thin film transistor in each pixel can be compensated, thereby eliminating the influence of the threshold voltage of the driving thin film transistor on the current flowing through the light-emitting device D, and improving the display uniformity of the display panel 1 .
  • the impact of at least part of the communication signal line voltage drop on the display panel 1 can be eliminated.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more features.

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Abstract

一种像素驱动电路（10）、像素驱动方法和显示面板。像素驱动电路（10）包括第一薄膜晶体管（T1）、第二薄膜晶体管（T2）、第三薄膜晶体管（T3）、第四薄膜晶体管（T4）、第五薄膜晶体管（T5）、第六薄膜晶体管（T6）、第七薄膜晶体管（T7）、第一电容（C1）、第二电容（C2）和发光器件（D），第一薄膜晶体管（T1）用作发光器件（D）的驱动薄膜晶体管。可以对每一像素中驱动薄膜晶体管的阈值电压进行补偿。

Description

像素驱动电路、像素驱动方法和显示面板 技术领域
本申请属于显示技术领域，尤其涉及一种像素驱动电路、像素驱动方法和显示面板。
 背景技术
近年来，迷你发光二极管（Mini LED）、微发光二极管（Micro LED）和有机发光二极管（Organic Light-Emitting Diode，OLED）因为高色域、高对比度等特性逐渐成为人们研究的对象。
随着面板尺寸的增大，传统的无源矩阵驱动方式（Passive Matrix，PM）需要非常大的瞬态电流，对电源及功耗都有很高的要求。有源式矩阵驱动方式（Active Matrix，AM）通过薄膜晶体管（Thin Film Transistor，TFT）开关和电容逐行扫描进行LED点亮，可以有效避免大瞬态电流的问题。
 技术问题
然而，AM驱动方式中，由于长时间工作，驱动薄膜晶体管会发生阈值电压的偏移，从而引起发光器件电流的衰减。
 技术解决方案
本申请实施例提供一种像素驱动电路、像素驱动方法和显示面板，以解决现有的AM驱动方式中，由于长时间工作，驱动薄膜晶体管会发生阈值电压的偏移，从而引起发光器件电流衰减的问题。
第一方面，本申请实施例提供一种像素驱动电路，包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第一电容、第二电容和发光器件，所述第一薄膜晶体管用作所述发光器件的驱动薄膜晶体管；
所述第一薄膜晶体管的栅极电性连接第一节点，漏极电性连接第二节点；
所述第二薄膜晶体管的栅极接入第一扫描信号，源极接入数据信号，漏极电性连接所述第一节点；
所述第三薄膜晶体管的栅极接入发光控制信号，漏极电性连接所述第一薄膜晶体管的源极；
所述第四薄膜晶体管的栅极接入发光控制信号，源极电性连接所述第二节点，漏极接入公共接地电压；
所述第五薄膜晶体管的栅极接入第二扫描信号，源极接入所述第一节点，漏极电性连接所述第三薄膜晶体管的漏极；
所述第六薄膜晶体管的栅极接入第三扫描信号，源极接入电源电压，漏极电性连接第一节点；
所述第七薄膜晶体管的栅极接入第四扫描信号，源极接入参考信号，漏极电性连接所述第二节点；
所述第一电容的一端电性连接所述第一节点，另一端电性连接所述第二节点；
所述第二电容的一端电性连接所述第一节点，另一端电性连接所述第二薄膜晶体管的漏极；
所述发光器件的阳极接入电源电压，阴极与所述第三薄膜晶体管的源极电性连接。
第二方面，本申请实施例还提供一种像素驱动方法，应用于像素驱动电路，所述像素驱动电路包括：第一薄膜晶体管，栅极电性连接第一节点，漏极电性连接第二节点；第二薄膜晶体管，栅极接入第一扫描信号，源极接入数据信号，漏极电性连接所述第一节点；第三薄膜晶体管，栅极接入发光控制信号，漏极电性连接所述第一薄膜晶体管的源极；第四薄膜晶体管，栅极接入发光控制信号，源极电性连接所述第二节点，漏极接入公共接地电压；第五薄膜晶体管，栅极接入第二扫描信号，源极接入所述第一节点，漏极电性连接所述第三薄膜晶体管的漏极；第六薄膜晶体管，栅极接入第三扫描信号，源极接入电源电压，漏极电性连接所述第一节点；第七薄膜晶体管，栅极接入第四扫描信号，源极接入参考信号，漏极电性连接所述第二节点；第一电容，一端连接所述第一节点，另一端连接所述第二节点；第二电容，一端连接所述第一节点，另一端连接所述第二薄膜晶体管的漏极；以及发光器件，阳极接入电源电压，阴极与所述第三薄膜晶体管的源极连接，所述发光器件被所述第一薄膜晶体管驱动；
所述像素驱动方法包括：
进入初始化阶段，控制所述第一扫描信号、所述第三扫描信号和所述第四扫描信号均为高电位，所述第二扫描信号、所述发光控制信号和所述数据信号均为低电位，以使所述第一节点电位为电源电压，所述第二节点电位为参考信号；
进入阈值电压提取阶段，控制所述第一扫描信号、所述第二扫描信号以及所述第四扫描信号均为高电位，所述第三扫描信号、所述发光控制信号和所述数据信号均为低电位，以使所述第一节点电位为参考信号与阈值电压的和，所述第二节点电位为参考信号；
进入数据写入阶段，控制所述第一扫描信号、所述第四扫描信号和所述数据信号均为高电位，所述第二扫描信号、所述第三扫描信号和所述发光控制信号均为低电位，以使所述第一节点电位为数据信号高电位与低电位的差值以及参考信号和阈值电压的和，所述第二节点的电位为参考信号；
进入发光阶段，控制所述发光控制信号为高电位，所述第一扫描信号、所述第二扫描信号、所述第三扫描信号、所述第四扫描信号和所述数据信号均为低电位，以使所述第二节点的电位为接地电压，所述第一节点的电位为数据信号高电位与低电位的差值以及阈值电压和接地电压的和。
第三方面，本申请实施例还提供一种显示面板，包括如上任一项所述的像素驱动电路。
 有益效果
本申请实施例的像素驱动电路、像素驱动方法和显示面板中，采用7T2C的像素驱动电路，对初始化阶段、阈值电压提取阶段、数据写入阶段以及发光阶段分别控制扫描信号、发光信号和数据信号在不同的电位，从而可以对每一像素中驱动薄膜晶体管的阈值电压进行补偿，进而消除驱动薄膜晶体管的阈值电压对流经发光器件电流的影响，提高显示面板的显示均匀性。此外，在发光阶段还能至少消除部分通讯信号线电压降对显示面板的影响。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单的介绍。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对本领域技术人员来说，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
为了更完整地理解本申请及其有益效果，下面将结合附图来进行说明。其中，在下面的描述中相同的附图标号表示相同部分。
图1为本申请实施例提供的显示面板的侧面结构示意图。
图2为图1所示的显示面板中像素驱动电路的结构示意图。
图3为本申请实施例提供的像素驱动电路的时序图。
图4为本申请实施例提供的像素驱动电路在图3所示的驱动时序下的初始化阶段的通路示意图。
图5为本申请实施例提供的像素驱动电路在图3所示的驱动时序下的阈值电压提取阶段的通路示意图。
图6为本申请实施例提供的像素驱动电路在图3所示的驱动时序下的数据写入阶段的通路示意图。
图7为本申请实施例提供的像素驱动电路在图3所示的驱动时序下的发光阶段的通路示意图。
图8为本申请实施例提供的像素驱动方法的流程示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
为了解决现有的AM驱动方式中，由于长时间工作，驱动薄膜晶体管会发生阈值电压的偏移，从而引起发光器件电流的衰减问题，本申请实施例提供一种像素驱动电路、像素驱动方法和显示面板，以下将结合附图进行说明。
示例性的，请参阅图1，图1为本申请实施例提供的显示面板的侧面结构示意图。本申请实施例提供一种显示面板1，显示面板1可以包括依次叠设的像素层20、发光层、驱动电路层和阵列基板。驱动电路层设置于阵列基板上。像素层20可以包括多个呈阵列排布的像素，发光层对应每一像素设置有发光器件D。驱动电路层可以包括多个像素驱动电路10，对每一像素均配置有像素驱动电路10，像素驱动电路10用于驱动对应像素的发光器件D的发光。发光器件D可以是有机发光二极管，有机发光二极管又称为有机电激光显示、有机发光半导体，是指有机半导体材料和发光材料在电场驱动下，通过载流子注入和复合导致发光的现象。发光器件D也可以是迷你发光二极管，发光器件D还可以是微发光二极管，本申请实施例以发光器件D为有机发光二极管为例进行说明。
随着显示面板1尺寸的增大，传统的无源矩阵驱动方式需要非常大的瞬态电流，对电源及功耗都有很高的要求。有源式矩阵驱动方式通过薄膜晶体管开关和电容逐行扫描进行LED点亮，可以有效避免大瞬态电流的问题。然而，现有技术中，像素驱动电路通常为2T1C的结构，即两个薄膜晶体管加一个电容的结构。根据计算流经驱动薄膜晶体管及发光器件D电流的公式为：I_D=K×(Vgs-Vth)。其中，ID代表流经驱动薄膜晶体管及发光器件D的电流，K为驱动薄膜晶体管的本征导因子，Vgs表示驱动薄膜晶体管的栅极与源极之间的电压差，Vth表示驱动薄膜晶体管的阈值电压。可见，ID的大小与驱动薄膜晶体管的阈值电压Vth有关。由于长时间工作，驱动发光器件D发光的驱动薄膜晶体管会发生阈值电压的偏移，从而引起发光器件电流的衰减。此外，显示面板内信号线的电压降同样会造成显示面板的发光器件间电流差异，宏观上产生肉眼可见的云纹或称不均匀。
为了解决上述问题，本申请实施例对像素驱动电路10进行了改进，以下将结合附图对像素驱动电路10进行说明。
示例性的，请结合图1并参阅图2，图2为图1所示的显示面板中像素驱动电路的结构示意图。本申请实施例的像素驱动电路10包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第一电容C1、第二电容C2和发光器件D。第一薄膜晶体管T1可以用作发光器件D的驱动薄膜晶体管。第二薄膜晶体管T2为数据写入薄膜晶体管。第三薄膜晶体管T3和第四薄膜晶体管T4可以用于发光。第五薄膜晶体管T5和第六薄膜晶体管T6可以用于第一薄膜晶体管T1的阈值电压Vth的侦测阶段。第七薄膜晶体管T7可以用于第二节点S电荷清空。第一电容C1可以为存储电容，第二电容C2可以用于将数据电压写入。其中，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7均为氧化物半导体薄膜晶体管、低温多晶硅薄膜晶体管或者非晶硅薄膜晶体管，也即薄膜晶体管T1至T7的类型均可以为铟镓锌氧化物（Indium Gallium Zinc Oxide，IGZO）、低温多晶硅（Low Temperature Poly-silicon，LTPS）或者非晶硅（A-Si）类型。当然，也可以对薄膜晶体管T1至T7分别采用不同类型的薄膜晶体管，组合方式有多种，这里不再赘述。例如，对于LTPS类型的薄膜晶体管，其可以分为N型和P型两种结构，其中的N型TFT会利用低掺杂型漏极（Lightly Doped Drain，LDD）来降低元件的漏电流。因此，对于第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7可以均为N型TFT。
第一薄膜晶体管T1的栅极电性连接第一节点G，漏极电性连接第二节点S。
第二薄膜晶体管T2的栅极接入第一扫描信号SCAN1，源极接入数据信号DATA，漏极电性连接第一节点G。
第三薄膜晶体管T3的栅极接入发光控制信号EM，漏极电性连接第一薄膜晶体管T1的源极。
第四薄膜晶体管T4的栅极接入发光控制信号EM，源极电性连接第二节点S，漏极接入公共接地电压VSS。
第五薄膜晶体管T5的栅极接入第二扫描信号SCAN2，源极接入第一节点G，漏极电性连接第三薄膜晶体管T3的漏极。
第六薄膜晶体管T6的栅极接入第三扫描信号SCAN3，源极接入电源电压VDD，漏极电性连接第一节点G。
第七薄膜晶体管T7的栅极接入第四扫描信号SCAN4，源极接入参考信号Ref，漏极电性连接第二节点S。
第一电容C1的一端电性连接第一节点G，另一端电性连接第二节点S。
第二电容C2的一端电性连接第一节点G，另一端电性连接第二薄膜晶体管T2的漏极。将第二电容C2直接连接数据信号DATA，在数据信号DATA高电位时可以通过耦合的方式写入数据信号，并且不会影响阈值电压的数据存储，比如可以防止丢失已经存储的阈值电压信息。
发光器件D的阳极接入电源电压VDD，阴极与第三薄膜晶体管T3的源极电性连接。将发光器件D设置在电源电压VDD处，利用发光器件D分压可以降低扫描信号电压值，从而降低像素驱动电路10的功耗。
本申请实施例采用7T2C的像素驱动电路10，对初始化阶段、阈值电压提取阶段、数据写入阶段以及发光阶段分别控制扫描信号、发光信号和数据信号在不同的电位，从而可以对每一像素中驱动薄膜晶体管的阈值电压进行补偿，进而消除驱动薄膜晶体管的阈值电压对流经发光器件D电流的影响，提高显示面板1的显示均匀性。此外，在发光阶段还能至少消除部分通讯信号线电压降对显示面板1的影响。
示例性的，请结合图1和图2并参阅图3，图3为本申请实施例提供的像素驱动电路的时序图。第一扫描信号SCAN1、第二扫描信号SCAN2、第三扫描信号SCAN3、第四扫描信号SCAN4、发光控制信号EM以及数据信号DATA相组合先后对应于一初始化阶段ST1、一阈值电压提取阶段ST2、一数据写入阶段ST3以及一发光阶段ST4。
请结合图1至图3并参阅图4，图4为本申请实施例提供的像素驱动电路在图3所示的驱动时序下的初始化阶段的通路示意图。在初始化阶段ST1，第一扫描信号SCAN1、第三扫描信号SCAN3和第四扫描信号SCAN4均为高电位，第二扫描信号SCAN2、发光控制信号EM以及数据信号DATA均为低电位。第一节点G电位为电源电压VDD，第二节点S电位为参考信号Ref。可以理解的是，在这个阶段，第一扫描信号SCAN1、第三扫描信号SCAN3和第四扫描信号SCAN4高电位分别打开第二薄膜晶体管T2、第六薄膜晶体管T6和第七薄膜晶体管T7。第二扫描信号SCAN2、发光控制信号EM以及数据信号DATA均为低电位，也即第五薄膜晶体管T5、第三薄膜晶体管T3以及第四薄膜晶体管T4均关断。
请结合图1至图3并参阅图5，图5为本申请实施例提供的像素驱动电路在图3所示的驱动时序下的阈值电压提取阶段的通路示意图。在阈值电压提取阶段ST2，第一扫描信号SCAN1、第二扫描信号SCAN2以及第四扫描信号SCAN4均为高电位，第三扫描信号SCAN3、发光控制信号EM和数据信号DATA为低电位。第一节点G电位为参考信号Ref与阈值电压Vth的和，也即第一节点G的电位为Ref+Vth。第二节点S电位为参考信号Ref。可以理解的是，在ST2这个阶段，第三扫描信号SCAN3为低电位关断第六薄膜晶体管T6，第一扫描信号SCAN1、第二扫描信号SCAN2以及第四扫描信号SCAN4均为高电位打开第二薄膜晶体管T2、第五薄膜晶体管T5和第七薄膜晶体管T7，从而形成二极管（diode）结构。发光控制信号EM以及数据信号DATA均为低电位，也即第三薄膜晶体管T3以及第四薄膜晶体管T4均关断。第一节点G的电位由电源电压VDD变为参考信号Ref与阈值电压Vth的和Ref+Vth，第二节点S的电位仍为参考信号Ref。
请结合图1至图3并参阅图6，图6为本申请实施例提供的像素驱动电路在图3所示的驱动时序下的数据写入阶段的通路示意图。在数据写入阶段ST3，第二扫描信号SCAN2、第三扫描信号SCAN3和发光控制信号EM均为低电位，第一扫描信号SCAN1和第四扫描信号SCAN4为高电位，数据信号DATA为高电位，第一节点G电位为数据信号高电位DATA_H与低电位DATA_L的差值以及参考信号Ref和阈值电压Vth的和DATA_H-DATA_L+Ref+Vth，第二节点S的电位为参考信号Ref。可以理解的是，在数据写入阶段ST3，第二扫描信号SCAN2由高电位变为低电位，第五薄膜晶体管T5关断。第一扫描信号SCAN1和第四扫描信号SCAN4为高电位，第二薄膜晶体管T2和第七薄膜晶体管T7打开，数据信号DATA由低电位DATA_L变为高电位DATA_H，由此第一节点G电位变为DATA_H-DATA_L+Ref+Vth，第二节点S的电位仍为参考信号Ref。
请结合图1至图3并参阅图7，图7为本申请实施例提供的像素驱动电路在图3所示的驱动时序下的发光阶段的通路示意图。在发光阶段ST4，发光控制信号EM为高电位，仅第三薄膜晶体管T3和第四薄膜晶体管T4打开。第一扫描信号SCAN1、第二扫描信号SCAN2、第三扫描信号SCAN3、第四扫描信号SCAN4和数据信号DATA均为低电位，也即第二薄膜晶体管T2、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7均关断，第二节点S的电位为接地电压VSS，第一节点G的电位为数据信号高电位DATA_H与低电位DATA_L的差值以及阈值电压Vth和接地电压VSS的和DATA_H-DATA_L+Vth+VSS。可以理解的是，发光阶段ST4仅发光控制信号EM高电位打开第三薄膜晶体管T3和第四薄膜晶体管T4，其他薄膜晶体管均关断，第二节点S的电位由参考信号Ref变为接地电压VSS，第一节点G的电位由DATA_H-DATA_L+Ref+Vth变为DATA_H-DATA_L+Vth+VSS。由于Vgs-Vth=DATA_H-DATA_L，Vgs是指第一薄膜晶体管T1栅极和源极的电压差。因此在发光阶段ST4，第一节点G的电位为Vgs+VSS，也即是说，发光阶段ST4流经发光器件D的电流与第一薄膜晶体管T1的阈值电压Vth无关，从而实现了对阈值电压Vth的补偿，进而消除了第一薄膜晶体管T1的阈值电压偏移对流经发光器件D的电流的影响。此外，流经第一节点G和第二节点S的电位变为Vgs，也即流经第一节点G和第二节点S的电流与接地电压VSS无关，从而实现了对电压降的补偿，消除了由于通讯信号线电压降对显示面板1的影响，进而可以提高显示面板1的显示均匀性。
需要说明的是，本申请实施例中，对于阈值电压的探测方式为二极管接法（diode connect），但是并不是像二极管一样具有整流特性，它具有的特性只是二极管正向导通时候的样子，就表现出一个小电阻似的小信号特性。而现有技术中，对于阈值电压的探测方式通常为源极追踪法（source follow）。
需要说明的是，第一扫描信号SCAN1、第二扫描信号SCAN2、第三扫描信号SCAN3、第四扫描信号SCAN4、发光控制信号EM和数据信号DATA均通过外部时序控制器产生。
为了更清楚的说明本申请实施例像素驱动电路10的作用方法，以下将从像素驱动方法的角度进行说明。
请结合图1至图7并参阅图8，图8为本申请实施例提供的像素驱动方法的流程示意图。像素驱动方法应用于像素驱动电路10中，像素驱动电路10可以参照上述说明，这里不再赘述。像素驱动方法包括：
101、进入初始化阶段，控制第一扫描信号、第三扫描信号和第四扫描信号均为高电位，第二扫描信号、发光控制信号和数据信号均为低电位，以使第一节点电位为电源电压，第二节点电位为参考信号。
需要说明的是，第一扫描信号SCAN1、第二扫描信号SCAN2、第三扫描信号SCAN3、第四扫描信号SCAN4、发光控制信号EM以及数据信号DATA相组合先后对应于一初始化阶段ST1、一阈值电压提取阶段ST2、一数据写入阶段ST3以及一发光阶段ST4。
在初始化阶段ST1，第一扫描信号SCAN1、第三扫描信号SCAN3和第四扫描信号SCAN4均为高电位，第二扫描信号SCAN2、发光控制信号EM以及数据信号DATA均为低电位。第一节点G电位为电源电压VDD，第二节点S电位为参考信号Ref。可以理解的是，在这个阶段，第一扫描信号SCAN1、第三扫描信号SCAN3和第四扫描信号SCAN4高电位分别打开第二薄膜晶体管T2、第六薄膜晶体管T6和第七薄膜晶体管T7。第二扫描信号SCAN2、发光控制信号EM以及数据信号DATA均为低电位，也即第五薄膜晶体管T5、第三薄膜晶体管T3以及第四薄膜晶体管T4均关断。
102、进入阈值电压提取阶段，控制第一扫描信号、第二扫描信号以及第四扫描信号均为高电位，第三扫描信号、发光控制信号和数据信号均为低电位，以使第一节点电位为参考信号与阈值电压的和，第二节点电位为参考信号。
在阈值电压提取阶段ST2，第一扫描信号SCAN1、第二扫描信号SCAN2以及第四扫描信号SCAN4均为高电位，第三扫描信号SCAN3、发光控制信号EM和数据信号DATA为低电位。第一节点G电位为参考信号Ref与阈值电压Vth的和，也即第一节点G的电位为Ref+Vth。第二节点S电位为参考信号Ref。可以理解的是，在ST2这个阶段，第三扫描信号SCAN3为低电位关断第六薄膜晶体管T6，第一扫描信号SCAN1、第二扫描信号SCAN2以及第四扫描信号SCAN4均为高电位打开第二薄膜晶体管T2、第五薄膜晶体管T5和第七薄膜晶体管T7，从而形成二极管（diode）结构。发光控制信号EM以及数据信号DATA均为低电位，也即第三薄膜晶体管T3以及第四薄膜晶体管T4均关断。第一节点G的电位由电源电压VDD变为参考信号Ref与阈值电压Vth的和Ref+Vth，第二节点S的电位仍为参考信号Ref。
103、进入数据写入阶段，控制第一扫描信号、第四扫描信号和数据信号均为高电位，第二扫描信号、第三扫描信号和发光控制信号均为低电位，以使第一节点电位为数据信号高电位与低电位的差值以及参考信号和阈值电压的和，第二节点的电位为参考信号。
在数据写入阶段ST3，第二扫描信号SCAN2、第三扫描信号SCAN3和发光控制信号EM均为低电位，第一扫描信号SCAN1和第四扫描信号SCAN4为高电位，数据信号DATA为高电位，第一节点G电位为数据信号高电位DATA_H与低电位DATA_L的差值以及参考信号Ref和阈值电压Vth的和DATA_H-DATA_L+Ref+Vth，第二节点S的电位为参考信号Ref。可以理解的是，在数据写入阶段ST3，第二扫描信号SCAN2由高电位变为低电位，第五薄膜晶体管T5关断。第一扫描信号SCAN1和第四扫描信号SCAN4为高电位，第二薄膜晶体管T2和第七薄膜晶体管T7打开，数据信号DATA由低电位DATA_L变为高电位DATA_H，由此第一节点G电位变为DATA_H-DATA_L+Ref+Vth，第二节点S的电位仍为参考信号Ref。
104、进入发光阶段，控制发光控制信号为高电位，第一扫描信号、第二扫描信号、第三扫描信号、第四扫描信号和数据信号均为低电位，以使第二节点的电位为接地电压，第一节点的电位为数据信号高电位与低电位的差值以及阈值电压和接地电压的和。
在发光阶段ST4，发光控制信号EM为高电位，仅第三薄膜晶体管T3和第四薄膜晶体管T4打开。第一扫描信号SCAN1、第二扫描信号SCAN2、第三扫描信号SCAN3、第四扫描信号SCAN4和数据信号DATA均为低电位，也即第二薄膜晶体管T2、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7均关断，第二节点S的电位为接地电压VSS，第一节点G的电位为数据信号高电位DATA_H与低电位DATA_L的差值以及阈值电压Vth和接地电压VSS的和DATA_H-DATA_L+Vth+VSS。可以理解的是，发光阶段ST4仅发光控制信号EM高电位打开第三薄膜晶体管T3和第四薄膜晶体管T4，其他薄膜晶体管均关断，第二节点S的电位由参考信号Ref变为接地电压VSS，第一节点G的电位由DATA_H-DATA_L+Ref+Vth变为DATA_H-DATA_L+Vth+VSS。由于Vgs-Vth=DATA_H-DATA_L，Vgs是指第一薄膜晶体管T1栅极和源极的电压差。因此在发光阶段ST4，第一节点G的电位为Vgs+VSS，也即是说，发光阶段ST4流经发光器件D的电流与第一薄膜晶体管T1的阈值电压Vth无关，从而实现了对阈值电压Vth的补偿，进而消除了第一薄膜晶体管T1的阈值电压偏移对流经发光器件D的电流的影响。此外，流经第一节点G和第二节点S的电位变为Vgs，也即流经第一节点G和第二节点S的电流与接地电压VSS无关，从而实现了对电压降的补偿，消除了由于通讯信号线电压降对显示面板1的影响，进而可以提高显示面板1的显示均匀性。
本申请实施例提供的像素驱动电路10、像素驱动方法和显示面板1中，采用7T2C的像素驱动电路10，对初始化阶段、阈值电压提取阶段、数据写入阶段以及发光阶段分别控制扫描信号、发光信号和数据信号在不同的电位，从而可以对每一像素中驱动薄膜晶体管的阈值电压进行补偿，进而消除驱动薄膜晶体管的阈值电压对流经发光器件D电流的影响，提高显示面板1的显示均匀性。此外，在发光阶段还能至少消除部分通讯信号线电压降对显示面板1的影响。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个特征。
以上对本申请实施例所提供的像素驱动电路、像素驱动方法和显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种像素驱动电路，其中，包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第一电容、第二电容和发光器件，所述第一薄膜晶体管用作所述发光器件的驱动薄膜晶体管；
    所述第一薄膜晶体管的栅极电性连接第一节点，漏极电性连接第二节点；
    所述第二薄膜晶体管的栅极接入第一扫描信号，源极接入数据信号，漏极电性连接所述第一节点；
    所述第三薄膜晶体管的栅极接入发光控制信号，漏极电性连接所述第一薄膜晶体管的源极；
    所述第四薄膜晶体管的栅极接入发光控制信号，源极电性连接所述第二节点，漏极接入公共接地电压；
    所述第五薄膜晶体管的栅极接入第二扫描信号，源极接入所述第一节点，漏极电性连接所述第三薄膜晶体管的漏极；
    所述第六薄膜晶体管的栅极接入第三扫描信号，源极接入电源电压，漏极电性连接第一节点；
    所述第七薄膜晶体管的栅极接入第四扫描信号，源极接入参考信号，漏极电性连接所述第二节点；
    所述第一电容的一端电性连接所述第一节点，另一端电性连接所述第二节点；
    所述第二电容的一端电性连接所述第一节点，另一端电性连接所述第二薄膜晶体管的漏极；
    所述发光器件的阳极接入电源电压，阴极与所述第三薄膜晶体管的源极电性连接。
  2. 根据权利要求1所述的像素驱动电路，其中，所述第一扫描信号、所述第二扫描信号、所述第三扫描信号、所述第四扫描信号、所述发光控制信号以及所述数据信号相组合先后对应于一初始化阶段、一阈值电压提取阶段、一数据写入阶段以及一发光阶段。
  3. 根据权利要求2所述的像素驱动电路，其中，在所述初始化阶段，所述第一扫描信号、所述第三扫描信号和所述第四扫描信号均为高电位，所述第二扫描信号、所述发光控制信号和所述数据信号均为低电位，所述第一节点电位为电源电压，所述第二节点电位为参考信号。
  4. 根据权利要求2所述的像素驱动电路，其中，在所述阈值电压提取阶段，所述第一扫描信号、所述第二扫描信号以及所述第四扫描信号均为高电位，所述第三扫描信号、所述发光控制信号和所述数据信号均为低电位，所述第一节点电位为参考信号与阈值电压的和，所述第二节点电位为参考信号。
  5. 根据权利要求2所述的像素驱动电路，其中，在所述数据写入阶段，所述第一扫描信号、所述第四扫描信号和所述数据信号均为高电位，所述第二扫描信号、所述第三扫描信号和所述发光控制信号均为低电位，所述第一节点电位为数据信号高电位与低电位的差值以及参考信号和阈值电压的和，所述第二节点的电位为参考信号。
  6. 根据权利要求2所述的像素驱动电路，其中，在所述发光阶段，所述发光控制信号为高电位，所述第一扫描信号、所述第二扫描信号、所述第三扫描信号、所述第四扫描信号和所述数据信号均为低电位，所述第二节点的电位为接地电压，所述第一节点的电位为数据信号高电位与低电位的差值以及阈值电压和接地电压的和。
  7. 根据权利要求6所述的像素驱动电路，其中，在所述发光阶段，流经所述第一节点和所述第二节点的电流与接地电压无关。
  8. 根据权利要求7所述的像素驱动电路，其中，在所述发光阶段，流经所述发光器件的电流与所述第一薄膜晶体管的阈值电压无关。
  9. 根据权利要求1所述的像素驱动电路，其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管和所述第七薄膜晶体管均为氧化物半导体薄膜晶体管、低温多晶硅薄膜晶体管或者非晶硅薄膜晶体管。
  10. 根据权利要求9所述的像素驱动电路，其中，所述发光器件为有机发光二极管。
  11. 根据权利要求1所述的像素驱动电路，其中，所述第一扫描信号、所述第二扫描信号、所述第三扫描信号、所述第四扫描信号、所述发光控制信号和所述数据信号均通过外部时序控制器产生。
  12. 一种像素驱动方法，其中，应用于像素驱动电路，所述像素驱动电路包括：第一薄膜晶体管，栅极电性连接第一节点，漏极电性连接第二节点；第二薄膜晶体管，栅极接入第一扫描信号，源极接入数据信号，漏极电性连接所述第一节点；第三薄膜晶体管，栅极接入发光控制信号，漏极电性连接所述第一薄膜晶体管的源极；第四薄膜晶体管，栅极接入发光控制信号，源极电性连接所述第二节点，漏极接入公共接地电压；第五薄膜晶体管，栅极接入第二扫描信号，源极接入所述第一节点，漏极电性连接所述第三薄膜晶体管的漏极；第六薄膜晶体管，栅极接入第三扫描信号，源极接入电源电压，漏极电性连接所述第一节点；第七薄膜晶体管，栅极接入第四扫描信号，源极接入参考信号，漏极电性连接所述第二节点；第一电容，一端连接所述第一节点，另一端连接所述第二节点；第二电容，一端连接所述第一节点，另一端连接所述第二薄膜晶体管的漏极；以及发光器件，阳极接入电源电压，阴极与所述第三薄膜晶体管的源极连接，所述发光器件被所述第一薄膜晶体管驱动；
    所述像素驱动方法包括：
    进入初始化阶段，控制所述第一扫描信号、所述第三扫描信号和所述第四扫描信号均为高电位，所述第二扫描信号、所述发光控制信号和所述数据信号均为低电位，以使所述第一节点电位为电源电压，所述第二节点电位为参考信号；
    进入阈值电压提取阶段，控制所述第一扫描信号、所述第二扫描信号以及所述第四扫描信号均为高电位，所述第三扫描信号、所述发光控制信号和所述数据信号均为低电位，以使所述第一节点电位为参考信号与阈值电压的和，所述第二节点电位为参考信号；
    进入数据写入阶段，控制所述第一扫描信号、所述第四扫描信号和所述数据信号均为高电位，所述第二扫描信号、所述第三扫描信号和所述发光控制信号均为低电位，以使所述第一节点电位为数据信号高电位与低电位的差值以及参考信号和阈值电压的和，所述第二节点的电位为参考信号；
    进入发光阶段，控制所述发光控制信号为高电位，所述第一扫描信号、所述第二扫描信号、所述第三扫描信号、所述第四扫描信号和所述数据信号均为低电位，以使所述第二节点的电位为接地电压，所述第一节点的电位为数据信号高电位与低电位的差值以及阈值电压和接地电压的和。
  13. 根据权利要求12所述的像素驱动方法，其中，在所述发光阶段，流经所述第一节点和所述第二节点的电流与接地电压无关。
  14. 根据权利要求13所述的像素驱动方法，其中，在所述发光阶段，流经所述发光器件的电流与所述第一薄膜晶体管的阈值电压无关。
  15. 一种显示面板，其中，包括像素驱动电路，包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第一电容、第二电容和发光器件，所述第一薄膜晶体管用作所述发光器件的驱动薄膜晶体管；
    所述第一薄膜晶体管的栅极电性连接第一节点，漏极电性连接第二节点；
    所述第二薄膜晶体管的栅极接入第一扫描信号，源极接入数据信号，漏极电性连接所述第一节点；
    所述第三薄膜晶体管的栅极接入发光控制信号，漏极电性连接所述第一薄膜晶体管的源极；
    所述第四薄膜晶体管的栅极接入发光控制信号，源极电性连接所述第二节点，漏极接入公共接地电压；
    所述第五薄膜晶体管的栅极接入第二扫描信号，源极接入所述第一节点，漏极电性连接所述第三薄膜晶体管的漏极；
    所述第六薄膜晶体管的栅极接入第三扫描信号，源极接入电源电压，漏极电性连接第一节点；
    所述第七薄膜晶体管的栅极接入第四扫描信号，源极接入参考信号，漏极电性连接所述第二节点；
    所述第一电容的一端电性连接所述第一节点，另一端电性连接所述第二节点；
    所述第二电容的一端电性连接所述第一节点，另一端电性连接所述第二薄膜晶体管的漏极；
    所述发光器件的阳极接入电源电压，阴极与所述第三薄膜晶体管的源极电性连接。
  16. 根据权利要求15所述的显示面板，其中，所述第一扫描信号、所述第二扫描信号、所述第三扫描信号、所述第四扫描信号、所述发光控制信号以及所述数据信号相组合先后对应于一初始化阶段、一阈值电压提取阶段、一数据写入阶段以及一发光阶段。
  17. 根据权利要求16所述的显示面板，其中，在所述初始化阶段，所述第一扫描信号、所述第三扫描信号和所述第四扫描信号均为高电位，所述第二扫描信号、所述发光控制信号和所述数据信号均为低电位，所述第一节点电位为电源电压，所述第二节点电位为参考信号。
  18. 根据权利要求16所述的显示面板，其中，在所述阈值电压提取阶段，所述第一扫描信号、所述第二扫描信号以及所述第四扫描信号均为高电位，所述第三扫描信号、所述发光控制信号和所述数据信号均为低电位，所述第一节点电位为参考信号与阈值电压的和，所述第二节点电位为参考信号。
  19. 根据权利要求16所述的显示面板，其中，在所述数据写入阶段，所述第一扫描信号、所述第四扫描信号和所述数据信号均为高电位，所述第二扫描信号、所述第三扫描信号和所述发光控制信号均为低电位，所述第一节点电位为数据信号高电位与低电位的差值以及参考信号和阈值电压的和，所述第二节点的电位为参考信号。
  20. 根据权利要求16所述的显示面板，其中，在所述发光阶段，所述发光控制信号为高电位，所述第一扫描信号、所述第二扫描信号、所述第三扫描信号、所述第四扫描信号和所述数据信号均为低电位，所述第二节点的电位为接地电压，所述第一节点的电位为数据信号高电位与低电位的差值以及阈值电压和接地电压的和。
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