WO2023221086A1 - 显示基板 - Google Patents

显示基板 Download PDF

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Publication number
WO2023221086A1
WO2023221086A1 PCT/CN2022/094081 CN2022094081W WO2023221086A1 WO 2023221086 A1 WO2023221086 A1 WO 2023221086A1 CN 2022094081 W CN2022094081 W CN 2022094081W WO 2023221086 A1 WO2023221086 A1 WO 2023221086A1
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WO
WIPO (PCT)
Prior art keywords
power signal
layer
signal bus
electrode
display substrate
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PCT/CN2022/094081
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English (en)
French (fr)
Inventor
丁录科
李永谦
袁粲
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001321.6A priority Critical patent/CN117441128A/zh
Priority to PCT/CN2022/094081 priority patent/WO2023221086A1/zh
Publication of WO2023221086A1 publication Critical patent/WO2023221086A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

Definitions

  • Embodiments of the present disclosure relate to a display substrate.
  • organic light-emitting diode (OLED) display panels have the characteristics of self-illumination, high contrast, low energy consumption, wide viewing angle, fast response speed, can be used in flexible panels, wide operating temperature range, simple manufacturing, etc., and have broad application prospects. Prospects.
  • At least one embodiment of the present disclosure provides a display substrate, which has a display area and a peripheral area at least partially surrounding the display area, and includes a base substrate, a plurality of sub-pixels, a first power signal line, a second power signal lines, a first power signal bus and a second power signal bus, a plurality of sub-pixels are arranged on the substrate and located in the display area, the first power signal line and the second power signal line are arranged on the substrate on and at least partially located in the display area, wherein the first power signal line is configured to transmit a first power signal to at least part of the plurality of sub-pixels, and the second power signal line is configured to transmit a first power signal to the plurality of sub-pixels.
  • At least part of the sub-pixels transmits a second power signal different from the first power signal;
  • the first power signal bus and the second power signal bus are provided on the substrate and located in the peripheral area, wherein the The first power signal line is electrically connected to the first power signal bus, the second power signal line is electrically connected to the second power signal bus, and the second power signal bus includes a A first portion of the signal bus is located close to the display area and a second portion is disposed on a side of the first power signal bus away from the display area to at least partially surround the first power signal bus.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: a light-shielding layer disposed on the base substrate, wherein each of the plurality of sub-pixels includes a light-emitting device and a pixel driving circuit that drives the light-emitting device.
  • the pixel driving circuit is disposed on a side of the light-shielding layer away from the base substrate, and the first power signal bus is disposed on the same layer as the light-shielding layer.
  • the pixel driving circuit includes a thin film transistor
  • the thin film transistor includes a gate electrode disposed on a side of the light shielding layer away from the base substrate and a gate electrode located on the side of the light shielding layer away from the base substrate.
  • the gate electrode is away from the source and drain electrodes on one side of the base substrate, and the first part is arranged in the same layer as the source and drain electrodes.
  • the second part is provided in the same layer as the gate electrode.
  • the second power signal bus further includes a third part and a fourth part that are electrically connected to the first part and the second part, and the third part and The fourth part is located on opposite sides of the first power signal bus, and the first part, the second part, the third part and the fourth part together surround the first power signal bus .
  • the third part and the fourth part are arranged on the same layer as the first part and are integrally connected with the first part.
  • the structures of the third part and the fourth part are symmetrical.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: a first power connection line, which is arranged on the same layer as the first power signal bus and electrically connects the first power signal bus and the first power signal line. .
  • the first power signal line is arranged on the same layer as the source and drain electrodes, and is electrically connected to the first power connection line through a transfer via hole.
  • the second power signal line and the source and drain electrode are arranged in the same layer.
  • the second power signal line extends from the display area to the peripheral area and is electrically connected to the first part.
  • the potential of the first power signal is higher than the potential of the second power signal.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a planarization layer and a first electrode layer; the planarization layer is disposed on a side of the source and drain electrodes away from the base substrate, including disposed on the periphery. a first via hole in the area exposing the first part and a second via hole arranged in the display area exposing the source and drain electrodes, and the first electrode layer is arranged on the planarization layer away from the base substrate
  • One side of the side includes a first electrode provided in the display area and a connection electrode provided in the peripheral area, the first electrode is electrically connected to the source and drain electrode through the second via hole, and the connection The electrode is electrically connected to the first part through the first via hole.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: a pixel definition layer disposed on a side of the first electrode layer away from the base substrate, including a connection opening disposed in the peripheral area and a The sub-pixel opening of the display area exposes the connection electrode, and the sub-pixel opening exposes the first electrode.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a luminescent material layer and a second electrode layer; the luminescent material layer is at least partially disposed in the sub-pixel opening, and the second electrode layer is disposed away from the luminescent material layer.
  • One side of the base substrate extends from the display area to the peripheral area, and is electrically connected to the connection electrode through the connection opening.
  • the second electrode layer terminates at a side of the first power signal bus close to the display area and is spaced from the first power signal bus.
  • the first part at least partially overlaps the first power connection line in a direction perpendicular to the base substrate, and the first part is included in A first hollow portion overlapping the first power connection line in a direction perpendicular to the base substrate.
  • the first part further includes a second hollow part that does not overlap with the first power connection line in a direction perpendicular to the base substrate.
  • At least one of the third part and the fourth part is at least at least connected to the first power connection line.
  • the first power connection line includes a first wiring portion extending along a first direction and a second wiring portion extending along a second direction.
  • the direction is different from the second direction, and in a direction perpendicular to the base substrate, the first wiring portion at least partially overlaps the first portion and overlaps with the first hollow portion, and the The second wiring portion overlaps with at least one of the third portion and the fourth portion, and overlaps with the third hollow portion.
  • Figure 1 is a pixel circuit diagram of a display substrate provided by at least one embodiment of the present disclosure
  • 2A-2C are signal timing diagrams of a driving method for a pixel circuit provided by at least one embodiment of the present disclosure
  • Figure 3 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • Figure 4 is a partial plan view of the display substrate in Figure 3 in the dotted frame area;
  • Figure 5 is a partially enlarged plan view of the display substrate in the dotted frame area in Figure 4;
  • FIG. 6 is a partial cross-sectional schematic diagram of a sub-pixel of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 7-13B are partial schematic plan views of each functional layer of the display substrate provided by at least one embodiment of the present disclosure, and a partial schematic plan view of each functional layer being stacked in sequence.
  • the display substrate usually includes a display area and a peripheral area surrounding the display area.
  • the display area has a plurality of sub-pixels for display. At least some of the plurality of sub-pixels include a light-emitting device and a pixel driving circuit that drives the light-emitting device to emit light.
  • the peripheral area includes structures such as a control circuit that provides control signals to the pixel drive circuit and a power bus.
  • the pixel driving circuit is usually implemented as 3T1C (three thin film transistors and one storage capacitor), 7T1C (seven thin film transistors and one storage capacitor), 8T1C (eight thin film transistors and one storage capacitor) Or structures such as 8T2C (eight thin film transistors and two storage capacitors) to achieve the effect of driving light-emitting devices.
  • 3T1C three thin film transistors and one storage capacitor
  • 7T1C even thin film transistors and one storage capacitor
  • 8T1C epitinc
  • structures such as 8T2C (eight thin film transistors and two storage capacitors) to achieve the effect of driving light-emitting devices.
  • a pixel driving circuit with a 3T1C structure is used as an example for introduction below, but the embodiments of the present disclosure do not limit the specific structure of the pixel driving circuit.
  • the pixel driving circuit of the 3T1C structure includes a driving sub-circuit for driving the light-emitting device to emit light and a detection sub-circuit for detecting the electrical characteristics of the sub-pixel to achieve external compensation.
  • FIG. 1 shows a schematic diagram of a 3T1C pixel driving circuit provided by at least one embodiment of the present disclosure.
  • the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor Cst.
  • the first transistor T1 is, for example, a driving transistor
  • the second transistor T2 is, for example, a data writing transistor.
  • the first source-drain electrode of the second transistor T2 is electrically connected to the first capacitor electrode Ca of the storage capacitor Cst and the gate electrode of the first transistor T1.
  • the second source-drain electrode of the second transistor T2 is configured to receive the data signal DT.
  • the transistor T2 is configured to write the data signal DT into the gate of the first transistor T1 and the storage capacitor Cst in response to the first control signal G1; the first source-drain electrode of the first transistor T1 and the second capacitance electrode Cb of the storage capacitor Cst.
  • the second source-drain electrode of the first transistor T1 is configured to receive the first power supply voltage V1 (for example, receiving a high power supply voltage through the power supply signal line VDD), and the first The transistor T1 is configured to control the current for driving the light-emitting device under the control of the voltage of the gate of the first transistor T1; the first source-drain electrode of the third transistor T3 and the first source-drain electrode of the first transistor T1 and the storage capacitor
  • the second capacitance electrode Cb of Cst is electrically connected, the second source-drain electrode of the third transistor T3 is configured to be connected to the detection line SEN to be connected to the external detection circuit, and the third transistor T3 is configured to detect the associated signal in response to the second control signal G2
  • the electrical characteristics of the sub-pixel are used to achieve external compensation; the electrical characteristics include, for example, the threshold voltage and/or carrier mobility of the first transistor T1, or the threshold voltage and driving current of
  • the storage capacitor Cst shown in FIG. 1 also includes a third capacitor electrode Cc.
  • the third capacitor electrode Cc is located on a side of the first capacitor electrode Ca away from the second capacitor electrode Cb and is electrically connected to the second capacitor electrode Cb to form
  • the structure of the parallel capacitor increases the capacitance value of the storage capacitor Cst.
  • the second electrode of the light emitting device EM is electrically connected to the power supply signal line VSS to receive the low power supply voltage.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or other switching devices with the same characteristics.
  • the source and drain of the transistor used here can be symmetrical in structure, so there can be no structural difference between the source and drain.
  • one of the electrodes is the first source-drain electrode and the other electrode is the second source-drain electrode.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages) );
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages) voltage).
  • the transistor in FIG. 1 is an N-type transistor as an example. However, this description is not intended to limit the present disclosure.
  • Figure 1 shows the signal timing diagram of the pixel driving circuit during the display process
  • Figure 2B and Figure 2C shows the signal timing diagram of the pixel driving circuit during the detection process.
  • the display process of each frame image includes data writing and resetting phase 1 and lighting phase 2.
  • Figure 2A shows the timing waveforms of each signal in each stage.
  • a working process of the 3T1C pixel driving circuit includes: in the data writing and reset phase 1, the first control signal G1 and the second control signal G2 are both turn-on signals, the second transistor T2 and the third transistor T3 are turned on, and the data
  • the signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2, the first switch K1 is closed, and the analog-to-digital converter writes to the first electrode (such as the anode) of the light-emitting device EM through the detection line SEN and the third transistor T3.
  • the first transistor T1 is turned on and generates a driving current to charge the first electrode of the light-emitting device to the operating voltage; in the light-emitting phase 2, the first control signal G1 and the second control signal G2 are both off signals, due to the storage capacitor Cst Due to the bootstrap effect, the voltage across the storage capacitor Cst remains unchanged, the first transistor T1 works in a saturated state with unchanged current, and drives the light-emitting device to emit light.
  • FIG. 2B shows a signal timing diagram of the pixel driving circuit when detecting the threshold voltage.
  • a working process of the 3T1C pixel driving circuit includes: the first control signal G1 and the second control signal G2 are both turn-on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal DT is transmitted to The gate of the first transistor T1; the analog-to-digital converter writes a reset signal to the first electrode (node S) of the light-emitting device EM through the detection line SEN and the third transistor T3.
  • the first transistor T1 is turned on and charges the node S.
  • the digital-to-analog converter samples the voltage on the detection line SEN to obtain the threshold voltage of the first transistor T1. This process may be performed, for example, when the display device is turned off.
  • FIG. 2C shows a signal timing diagram of the pixel driving circuit when detecting carrier mobility.
  • a working process of the 3T1C pixel driving circuit includes: in the first stage, the first control signal G1 and the second control signal G2 are both turn-on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal DT passes through the third transistor.
  • the second transistor T2 transmits to the gate of the first transistor T1; the analog-to-digital converter writes a reset signal to the first electrode (node S) of the light-emitting device EM through the detection line SEN and the third transistor T3; in the second stage, the first The control signal G1 is a turn-off signal, the second control signal G1 is a turn-on signal, the second transistor T2 is turned off, the third transistor T3 is turned on, and the detection line SEN is floated; due to the bootstrap effect of the storage capacitor Cst, the storage capacitor Cst The voltage at both ends remains unchanged.
  • the first transistor T1 works in a saturated state with unchanged current and drives the light-emitting device to emit light.
  • the digital-to-analog converter samples the voltage on the detection line SEN, and combines the size and duration of the light-emitting current to calculate Get the carrier mobility in the first transistor T1. For example, this process can be performed during the blanking phase between display phases.
  • the electrical characteristics of the first transistor T1 can be obtained and the corresponding compensation algorithm can be implemented.
  • the peripheral area of the display substrate includes a power bus that provides power signals to the power signal line VDD and the power signal line VSS respectively. Since the power signal line VDD is used to transmit high-level signals, the high-level signals are easily transmitted to and from the display substrate. Other signals produce crosstalk, so the layout of the power bus needs to be optimized.
  • At least one embodiment of the present disclosure provides a display substrate, which has a display area and a peripheral area at least partially surrounding the display area, and includes a base substrate, a plurality of sub-pixels, a first power signal line, a second power signal line, a first power signal bus and a second power signal bus; a plurality of sub-pixels are disposed on the base substrate and located in the display area, the first power signal line and the second power signal line are disposed on the base substrate and at least partially located in the display area, The first power signal line is configured to transmit a first power signal to at least part of the plurality of sub-pixels, and the second power signal line is configured to transmit a second power signal different from the first power signal to at least part of the plurality of sub-pixels; A power signal bus and a second power signal bus are provided on the substrate and located in the peripheral area.
  • the first power signal line is electrically connected to the first power signal bus
  • the second power signal line is electrically connected to the second power signal bus.
  • the two power signal buses include a first portion disposed on a side of the first power signal bus close to the display area and a second portion disposed on a side of the first power signal bus away from the display area to at least partially surround the first power signal bus.
  • the second power signal bus at least partially surrounds the first power signal bus, thereby achieving the effect of shielding the first power signal bus from electromagnetic interference, so that the first power signal bus
  • the bus signal transmission is more accurate and the display effect of the display substrate is improved.
  • FIG. 3 shows a schematic plan view of the display substrate.
  • Figure 4 shows an enlarged schematic view of the display substrate in the dotted box area in Figure 3.
  • Figure 5 shows a schematic diagram of Figure 4 The enlarged schematic diagram of the display substrate in the dotted box area in FIG. 6 shows a partial cross-sectional schematic diagram of the sub-pixels of the display substrate.
  • the display substrate has a display area AA and a peripheral area NA at least partially surrounding the display area AA.
  • the display substrate also includes a substrate substrate 101, a plurality of sub-pixels SP, a first power signal line VDD, a second power signal line VSS, a first power signal bus VDB and a second power signal bus VSB, etc. structure.
  • a plurality of sub-pixels SP are provided on the base substrate 101 and located in the display area AA to achieve display effects.
  • the first power signal line VDD and the second power signal line VSS are provided on the base substrate 101 and are at least partially located in the display area AA.
  • the first power signal line VDD is configured to transmit a first power signal to at least part of the plurality of sub-pixels SP
  • the second power signal line VSS is configured to transmit a second power signal different from the first power signal to at least part of the plurality of sub-pixels SP. power signal.
  • the potential of the first power signal is higher than the potential of the second power signal, that is, the first power signal line VDD is used to transmit the high power voltage, and the second power signal line VSS is used to transmit the low power Voltage.
  • the second power signal bus VSB may be connected to ground.
  • the first power signal bus VDB and the second power signal bus VSB are disposed on the substrate 101 and located in the peripheral area NA.
  • the first power signal line VDD is electrically connected to the first power signal bus VDB to receive the signal from the first power signal bus VDB. Get the first power signal.
  • the first power signal line VDD may extend from the display area AA to the peripheral area NA to be electrically connected to the first power signal bus VDB.
  • the second power signal line VSS is electrically connected to the second power signal bus VSV to obtain the second power signal from the second power signal bus VSB.
  • the second power signal line VSS may extend from the display area AA to the peripheral area NA to be electrically connected with the second power signal bus VSV.
  • the second power signal bus VSB includes a first part VSB1 disposed on the side of the first power signal bus VDB close to the display area AA (the lower side in the figure) and a first part VSB1 disposed on the first power signal bus VDB.
  • the bus VDB is away from the second portion VSB2 on one side of the display area AA (the upper side in the figure), so that the second power signal bus VSB at least partially surrounds the first power signal bus VDB.
  • the second power signal bus VSB can at least achieve the function of shielding the first power signal bus VDB from electromagnetic interference on the opposite sides of the first power signal bus VDB (the upper and lower sides in the figure), so that the first power signal bus VDB's signal transmission is more accurate and improves the display effect of the display substrate.
  • the display substrate further includes a light-shielding layer SH, which is disposed on the base substrate 101 .
  • each of the plurality of sub-pixels includes a light-emitting device EM and a light-emitting device driving the light-emitting device.
  • the pixel driving circuit is provided on the side of the light shielding layer SH away from the base substrate 101 .
  • the pixel driving circuit includes structures such as thin film transistors (shown as driving transistors in FIG. 6) and storage capacitors.
  • the thin film transistor includes an active layer Ta disposed on a side of the light shielding layer SH away from the base substrate 101, a gate Tg disposed on a side of the active layer Ta away from the base substrate 101, and a gate electrode Tg disposed on a side far away from the base substrate.
  • the source and drain electrodes Td and Ts on the 101 side are electrically connected to the active layer Ta through via holes respectively.
  • the light-shielding layer SH at least partially overlaps the active layer Ta, thereby achieving the effect of shielding the active layer Ta from the outside world. Light irradiates the active layer Ta and affects the normal operation of the thin film transistor.
  • the storage capacitor includes a first capacitor electrode Ca, a second capacitor electrode Cb, and a third capacitor electrode Cc.
  • the first capacitor electrode Ca and the second capacitor electrode Cb overlap with each other to form the first capacitor C1
  • the first capacitor electrode Ca and the third capacitor electrode Cc overlap with each other to form the first capacitor C2
  • the first capacitor C1 and the first capacitor C2 are connected in parallel, thereby increasing the storage capacitance. of capacitance.
  • the first capacitor electrode Ca is placed in the same layer as the active layer Ta
  • the second capacitor electrode Cb is placed in the same layer as the source and drain electrodes Td and Ts
  • the third capacitor electrode Cc is placed in the same layer as the light shielding layer SH.
  • “same layer arrangement” means that two or more functional layers or structural layers are formed on the same layer and with the same material in the hierarchical structure of the display substrate, that is, during the preparation process, the The two functional layers or structural layers can be formed from the same material layer, and the required patterns and structures can be formed through the same patterning process, thereby simplifying the preparation process of the display substrate.
  • the first power signal bus VDB is provided on the same layer as the light-shielding layer SH.
  • the first part VSB1 of the second power signal bus VSB is arranged in the same layer as the source and drain electrodes Td and Ts.
  • the second part VSB2 of the second power signal bus VSB is arranged on the same layer as the gate Tg, which can further simplify the preparation process of the display substrate, avoid the display substrate from having too many structural layers, and make the display substrate thinner; in addition, , the first part VSB1 and the second part VSB2 of the first power signal bus VDB and the second power signal bus VSB are respectively made of different metal layers, which can increase the distance between the first power signal bus VDB and the second power signal bus VSB. , so it can avoid short circuit and other undesirable phenomena caused by too close signal lines.
  • the second power signal bus VSB also includes a third part VSB3 and a fourth part VSB4 that are electrically connected to the first part VSB1 and the second part VSB3.
  • the third part VSB3 and the fourth part Part VSB4 is located on the opposite sides of the first power signal bus VDS, such as the left and right sides in Figure 4.
  • the first part VSB1, the second part VSB, the third part VSB3 and the fourth part VSB4 together surround the first power supply Signal bus VDB.
  • the first part VSB1, the second part VSB, the third part VSB3 and the fourth part VSB4 completely surround the first power signal bus VDB to fully achieve the function of preventing signal crosstalk for the first power signal bus VDB. .
  • the third part VSB3 and the fourth part VSB4 can be arranged on the same layer as the first part VSB1 and integrally connected with the first part VSB, and the third part VSB3 and the fourth part VSB4 pass through
  • the via hole is electrically connected to the second part VSB2, so that the first part VSB1, the second part VSB, the third part VSB3 and the fourth part VSB4 of the second power signal bus VSB form a whole for transmitting the same low power signal, and The voltage drop of the second power signal bus VSB can be reduced.
  • the structures of the third part VSB3 and the fourth part VSB4 are symmetrical, that is, have substantially the same shape, size, layout, etc., so that signals on the left and right sides of the display substrate can be maintained
  • the transmission performance is basically consistent, improving the display uniformity of the display substrate.
  • the display substrate further includes a first power connection line DL.
  • the first power connection line DL can be arranged on the same layer as the first power signal bus VDB, that is, on the same layer as the light-shielding layer SH. Layer arrangement, the first power connection line DL is used to electrically connect the first power signal bus VDB and the first power signal line VDD.
  • the first power connection line DL may be arranged on the same layer as the first power signal bus VDB and connected integrally.
  • the first power signal line VDD may be arranged in the same layer as the source and drain electrodes Td and Ts, and be electrically connected to the first power connection line DL through the transfer via V.
  • the second power signal line VSS is arranged in the same layer as the source and drain electrodes Td and Ts, and is integrally connected to the first part VSB1 of the second power signal bus VSB.
  • the second power signal line VSS extends from the display area AA to the peripheral area NA and is electrically connected to the first part VSB1 of the second power signal bus VSB, for example, integrally connected.
  • the first part VSB1 of the second power signal bus VSB at least partially overlaps the first power connection line DL, and the first part VSB1 includes a first hollow portion H1 that overlaps the first power connection line DL in a direction perpendicular to the base substrate 101.
  • This can reduce the overlapping area of the first power connection line DL and the first portion VSB1, thereby preventing the second power connection line DL from overlapping.
  • a power connection line DL and the first part VSB1 form parasitic capacitance and other structures that affect the normal transmission of electrical signals.
  • the first part VSB1 of the second power signal bus VSB also includes a second hollow that does not overlap with the first power connection line DL in a direction perpendicular to the base substrate 101 Part H2.
  • the provision of the second hollow part H2 can increase the regional transparency, reduce the etching difference in different regions of the first part VSB1 arranged in a large area, and improve the etching uniformity of the first part VSB1 arranged in a large area.
  • At least one of the third portion VSB3 and the fourth portion VSB4 of the second power signal bus VSB (eg, Both the third part VSB3 and the fourth part VSB4) at least partially overlap the first power connection line DL
  • at least one of the third part VSB3 and the fourth part VSB4 (for example, the third part VSB3 and the fourth part VSB4 or) includes a third hollow portion H3 that overlaps the first power connection line DL in a direction perpendicular to the base substrate 101, thereby reducing the size of the first power connection line DL and the third portion VSB3 and the fourth portion VSB4. of overlapping area.
  • the third part VSB3 and the fourth part VSB4 may also include a hollow part (not shown in the figure) that does not overlap with the first power connection line DL in a direction perpendicular to the base substrate 101 , to improve the etching uniformity of the third part VSB3 and the fourth part VSB4.
  • the first power connection line DL may include a first wiring portion DL1 extending along a first direction (vertical direction in the figure) and a first wiring portion DL1 extending along a second direction (the vertical direction in the figure). (horizontal direction) of the second wiring portion DL2 extending, the first direction is different from the second direction, for example, the first direction is perpendicular to the second direction.
  • the first wiring part DL1 includes a plurality of first wirings, and the plurality of first wirings are parallel to each other;
  • the second wiring part DL2 includes two second wirings arranged oppositely, the The two second traces are arranged on the same straight line.
  • part of the first wiring is directly connected to the first power signal bus VDB
  • part of the first wiring is connected to the second wiring, and is electrically connected to the first power signal bus VDB through the second wiring.
  • the first wiring portion DL1 at least partially overlaps the first portion VSB1 of the second power signal bus VSB and overlaps with the first hollow portion H1, and the second wiring portion DL2 It overlaps with at least one of the third part VSB3 and the fourth part VSB4 (for example, both the third part VSB3 and the fourth part VSB4) of the second power signal bus VSB, and overlaps with the third hollow part H3.
  • the display substrate further includes a planarization layer PLN and a first electrode layer.
  • the planarization layer PLN is disposed on the side of the source and drain electrodes Td and Ts away from the base substrate 101 to planarize the pixel driving circuit and provide a flat surface to facilitate the placement of the first electrode layer.
  • the planarization layer PLN includes a first via V1 disposed in the peripheral area NA exposing the first part VSB1 of the second power signal bus VSB and a second via hole V1 disposed in the display area AA exposing the source and drain electrode Ts. Via V2.
  • the first electrode layer is disposed on a side of the planarization layer PLN away from the base substrate 101 .
  • the first electrode layer includes a first electrode E1 disposed in the display area AA. and a connection electrode EL provided in the peripheral area NA.
  • the first electrode E1 is electrically connected to the source and drain electrode Ts through the second via hole V2.
  • the connection electrode EL is electrically connected to the first part VSB1 of the second power signal bus VSB through the first via hole V1. connect.
  • the first electrode E1 may serve as an anode of the light emitting device EM.
  • the display substrate further includes a pixel defining layer PDL, and the pixel defining layer PDL is disposed on the side of the first electrode layer away from the base substrate 101 .
  • the pixel The defining layer PDL includes a connection opening PDL1 provided in the peripheral area NA and a sub-pixel opening PDL2 provided in the display area AA.
  • the connection opening PDL1 exposes the connection electrode EL
  • the sub-pixel opening PDL2 exposes the first electrode E1, thereby defining the light emitting device EM. Effective luminous area.
  • the display substrate further includes a luminescent material layer E2 and a second electrode layer E3.
  • the luminescent material layer E2 is at least partially disposed in the sub-pixel opening PDL2 so as to be driven by the first electrode E1 exposed by the sub-pixel opening PDL2 to emit light.
  • the second electrode layer E3 is provided on the side of the luminescent material layer E2 away from the base substrate 101 .
  • the second electrode layer E3 may serve as the cathode of the light emitting device EM.
  • the second electrode layer E3 may be an electrode layer formed over the entire surface, that is, it is continuously provided in a sheet shape on the base substrate, and extends from the display area AA to the peripheral area NA, and passes through the connection opening.
  • PLN1 is electrically connected to the connection electrode EL, so that the second electrode layer E3 can be electrically connected to the first part VSB1 of the second power signal bus VSB to receive the low power signal.
  • the second electrode layer E3 terminates at a side of the first power signal bus VDS close to the display area AA.
  • the termination boundary line of the second electrode layer E3 is E3D, represented by
  • the second electrode layer E3 is separated from the first power signal bus VDB, that is, the boundary line E3D is separated from the first power signal bus VDB.
  • the separation distance is greater than 1.0 micrometer, such as 1.20 micrometer, 1.30 micrometer, or 1.35 micrometer. , 1.40 micron, 1.45 micron or 1.50 micron, etc. This can reduce the risk of short circuit between the second electrode layer E3 and the first power signal bus VDB, and improve the production yield of the display substrate.
  • the display substrate may also include structures such as a barrier layer and a buffer layer (not shown in the figure) disposed on the base substrate 101 to prevent impurities from entering the base substrate 101 from the base substrate 101 in each functional layer.
  • the display substrate may further include an insulating layer 102 provided on the light shielding layer SH, a gate insulating layer GI provided on the active layer Ta, an interlayer insulating layer IDL provided on the gate electrode Tg, Structures such as a passivation layer PVX provided on the source and drain electrodes Td and Ts and an encapsulation layer (not shown in the figure) provided on the second electrode layer.
  • the passivation layer PVX has a via hole PVX1 penetrating the second via hole V2 of the planarization layer PLN, so that the first electrode E1 is electrically connected to the source and drain electrode Ts through the second via hole V2 and the via hole PVX1.
  • the passivation layer PVX also includes a via PVX2 penetrating the first via V1 (see FIG. 11A, detailed later), thereby connecting the electrode EL to the second power signal bus through the first via V1 and the via PVX2.
  • the first part of the VSB, VSB1 is electrically connected.
  • the encapsulation layer may be a composite encapsulation layer, including a stack of multiple inorganic encapsulation layers and organic encapsulation layers, such as a three-layer stack structure of inorganic encapsulation layer/organic encapsulation layer/inorganic encapsulation layer, to achieve better encapsulation effect.
  • the display substrate may also include structures such as a cover plate (such as a glass transparent cover plate) disposed on the encapsulation layer. The embodiments of the present disclosure do not specifically limit other structures on the display substrate.
  • the base substrate 101 may be a rigid substrate such as glass or quartz or a flexible substrate such as polyimide (PI).
  • the materials of the active layer Ta and the first capacitor electrode Ca include but are not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials Materials (hexathiophene, polythiophene, etc.).
  • the semiconductor material of the first capacitor electrode Ca is conductive to have good electrical conductivity.
  • the light shielding layer SH, the third capacitor electrode Cc and the first power signal bus VDD can be made of copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), titanium (Ti), tungsten (W) and other metal materials. Or alloy materials.
  • the gate Tg and the second part VSB2 of the second power signal bus VSB can be made of metals such as copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), titanium (Ti), tungsten (W), etc. materials or alloy materials.
  • the gate Tg and the second part VSB2 of the second power signal bus VSB may be a single-layer or multi-layer structure, such as a laminate structure of molybdenum-titanium alloy and copper.
  • the source and drain electrodes Td and Ts, the second capacitor electrode Cb and the first part VSB1, the third part VSB3 and the fourth part VSB4 of the second power signal bus VSB may be made of copper (Cu), aluminum (Al), molybdenum (Mo).
  • magnesium (Mg), titanium (Ti), tungsten (W) and other metal materials or alloy materials can also be formed into a single-layer or multi-layer structure, such as a laminated structure of molybdenum-titanium alloy and copper.
  • the insulating layer 102, the gate insulating layer GI, the interlayer insulating layer IDL, the passivation layer PVX and the inorganic encapsulation layer may be inorganic insulating layers, such as silicon oxide (SiOx), silicon nitride (SiNy) or silicon oxynitride (SiNy). SiOxNy) and other inorganic insulating materials.
  • the planarization layer PLN, the pixel definition layer PDL and the organic encapsulation layer can be organic insulating layers.
  • polyimide (PI) acrylate
  • epoxy resin polymethyl methacrylate
  • PMMA polymethyl methacrylate
  • the first electrode E1 and the connecting electrode EL can use materials with high work functions, such as transparent metal oxides, such as ITO, IZO, etc.
  • the first electrode E1 can also include a metal layer such as Ag, thereby forming a transparent metal oxide Multilayer structure of physical/metallic layers.
  • the light-emitting material layer E2 may include an organic light-emitting material, so that the light-emitting device EM is formed as an organic light-emitting device (OLED); or, in other embodiments, the light-emitting material layer E2 may also include quantum dot light-emitting materials, so that the light-emitting device EM Formed into quantum dot devices (QLEDs).
  • the second electrode layer E3 may be made of metal materials such as magnesium (Mg), lithium (Li), aluminum (Al), silver (Ag), or alloy materials. The embodiments of the present disclosure do not limit the materials of each functional layer.
  • FIGS. 7 to 13B show partial plan views of each functional layer of the display substrate and partial plan views of each functional layer being stacked in sequence.
  • each functional layer of the display substrate and its relative positional relationship will be introduced by taking the structure shown in FIGS. 7-13B as an example.
  • Figure 7 shows a partial plan view of the first conductive layer where the light shielding layer SH is located.
  • the first conductive layer includes the light shielding layer SH, the first power signal bus VDB, and the first power signal connection line DL. and other structures.
  • a sputtering process can be used to form the material of the first conductive layer on the base substrate 101, and the material of the first conductive layer can be patterned through a photolithography process to obtain the light-shielding layer SH, the first conductive layer SH, and the first conductive layer SH. Patterns of the power signal bus VDB, the first power signal connection line DL and other structures.
  • the photolithography process may include processes such as photoresist coating, exposure, development, and etching.
  • processes such as photoresist coating, exposure, development, and etching.
  • an insulating layer 102 may be formed on the first conductive layer.
  • a deposition process may be used to form the material of the insulating layer 102 .
  • the material of the insulating layer 102 may include one or more of SiNx, SiOx or SiOxNy. kind, the thickness can be 150nm-500nm, such as 200nm, 300nm or 400nm, etc.
  • a sputtering process may be used to form a semiconductor oxide on the insulating layer 102, such as an amorphous oxide such as IGZO, ZnON, ITZO, etc. to form a semiconductor material layer, and the semiconductor material layer may be patterned through a photolithography process. , forming the pattern of the active layer Ta and the first capacitor electrode Ca.
  • the pattern of the first capacitor electrode Ca and part of the pattern of the active layer Ta can be subsequently subjected to conductive processing, such as doping processing, to have good conductivity. sex.
  • a deposition process can be used to form the material of the gate insulating layer GI, and then a sputtering process can be used to form the material of the second conductive layer on the material of the gate insulating layer GI.
  • the deposition thickness of the material of the second conductive layer can be It is 200nm-1000nm, such as 400nm, 600nm or 800nm, etc., and the gate Tg and the second part VSB2 of the second power signal bus VSB are formed through a photolithography process, as shown in Figure 8A.
  • the photoresist pattern used in the above photolithography process does not need to be stripped.
  • the photoresist pattern can be used as a mask to etch the material of the gate insulating layer GI using a dry etching process to form the pattern of the gate insulating layer GI. , and use gases such as NH 3 , N 2 or H 2 to conduct conductive treatment on the exposed semiconductor material layer, so that the processed semiconductor material layer has good conductivity.
  • FIG. 8B shows a partial plan view of the second conductive layer and the first conductive layer stack.
  • the second part VSB2 of the second power signal bus VSB is located away from the display area of the first power signal bus VDB. AA side.
  • FIG. 9A shows a partial plan view of the interlayer insulating layer IDL.
  • the interlayer insulating layer IDL includes a third portion VSB3 (and a fourth portion VSB4) for electrically connecting the second power signal bus VSB. ) and the via hole VS1 of the second part VSB2 and the via hole VS2 used to electrically connect the source and drain electrodes Ts/Td and the active layer Ta.
  • a deposition process may be used to deposit the material of the interlayer insulating layer IDL on the second conductive layer, and the via hole VS1 and the via hole VS2 may be obtained through a dry etching process.
  • the material of the interlayer insulating layer IDL may be a single-layer or multi-layer structure formed of SiNx or SiOx.
  • FIG. 9B shows a partial plan view of the interlayer insulating layer IDL, the second conductive layer, and the first conductive layer stack.
  • the via VS1 exposes the second part VSB2 of the second power signal bus VSB,
  • the via VS2 exposes the active layer Ta.
  • a sputtering process can be used to form the material of the third conductive layer on the interlayer insulating layer IDL.
  • the deposition thickness of the material of the third conductive layer can be 200nm-1000nm, and the source leakage current can be formed through a photolithography process.
  • the poles Ts/Td, the first power signal line VDD, the second power signal line VSS, and the first part VSB1 and the third part VSB3 (and the fourth part VSB4) of the second power signal bus VSB are shown in FIG. 10A .
  • the first part VSB1 has a first hollow part H1 and a second hollow part H2
  • the third part VSB3 (and the fourth part VSB4) has a third hollow part H3.
  • FIG. 10B shows a partial plan view of the third conductive layer, the interlayer insulating layer IDL, the second conductive layer, and the first conductive layer stack.
  • the third part VSB3 of the second power signal bus VSB (and the fourth part VSB4) is electrically connected to the second part VSB2 through the via hole VS1
  • the source and drain electrodes Ts/Td are electrically connected to the active layer Ta through the via hole VS2, which is not specifically shown in the figure.
  • Figure 6 Please refer to Figure 6.
  • FIG. 11A shows a partial plan view of the passivation layer PVX and the planarization layer PLN.
  • a deposition process can be used to form the material of the passivation layer PVX, such as SiO 2 , on the third conductive layer, and a photolithography process can be used to form a pattern of the passivation layer PVX.
  • the passivation layer PVX includes a layer located in the display area AA.
  • the via hole PVX1 exposing the source and drain electrode Ts and the via hole PXV2 located in the peripheral area NA exposing the first part VSB1.
  • a material such as polyimide, such as polyimide can be used to form the planarization layer PLN on the passivation layer PVX by coating.
  • the water and organic solvent in the material are then baked at 230 degrees to form a thickness of about 2.0 ⁇ m to 3.5 ⁇ m.
  • the planarization layer PLN is then exposed and developed to form a first via hole V1 located in the peripheral area NA and penetrating the via hole PXV2, and a second via hole V2 located in the display area AA and penetrating the via hole PVX1.
  • FIG. 11B shows a partial plan view of the passivation layer PVX, the planarization layer PLN, the third conductive layer, the interlayer insulating layer IDL, the second conductive layer, and the first conductive layer stack.
  • the first via hole V1 and the via hole PXV2 expose the first part VSB1.
  • the second via hole V2 and the via hole PVX1 expose the source and drain electrode Ts, which are not shown in Figure 11B, please refer to Figure 6 .
  • FIG. 12A shows a partial plan view of the first electrode layer.
  • the first electrode layer includes a first electrode E1 located in the display area AA and a connection electrode EL located in the peripheral area NA.
  • a sputtering process can be used to form the material of the first electrode layer on the planarization layer PLN.
  • the thickness of the material is about 100nm-600nm, such as 200nm, 300nm, 400nm or 500nm, etc.
  • the third electrode layer is obtained through a photolithography process.
  • An electrode E1 and a pattern connecting the electrode EL is obtained through a photolithography process.
  • FIG. 12B shows a partial plan view of the first electrode layer, the passivation layer PVX, the planarization layer PLN, the third conductive layer, the interlayer insulating layer IDL, the second conductive layer, and the first conductive layer stack, as shown in FIG.
  • the connection electrode EL is electrically connected to the first part VSB1 through the via holes of the passivation layer PVX and the planarization layer PLN in the peripheral area NA.
  • the first electrode E1 is electrically connected to the source and drain electrode Ts through the via holes of the passivation layer PVX and the planarization layer PLN in the display area AA, which is not specifically shown in FIG. 12B and may be referred to FIG. 6 .
  • FIG. 13A shows a partial plan view of the pixel defining layer PLN, and the shaded portion in the figure is the portion where the material of the pixel defining layer PLN has been removed.
  • the pixel defining layer PLN includes a sub-pixel opening region PDL3 having a sub-pixel opening PDL2 for a plurality of sub-pixels, and the sub-pixel opening PDL2 exposes the first electrode E1, refer to FIG. 6 .
  • the pixel definition layer PLN also includes a connection opening PDL1, which exposes the connection electrode EL, so that the subsequently formed second electrode layer E2 is electrically connected to the connection electrode EL through the connection opening PDL1, and then to the first part of the second power signal bus VSB VSB1 electrical connection.
  • a coating process can be used to form the material of the pixel defining layer PLN.
  • the patterns of the pixel defining layer PLN such as the connection opening PDL1 and the sub-pixel opening PDL2 are formed, and then after 230 degrees The water and organic solvent in the pixel definition layer PLN are removed by baking, and finally a pixel definition layer PLN with a thickness of 1.8 ⁇ m-2.0 ⁇ m is formed.
  • FIG. 13B shows a portion of the pixel definition layer PLN and the first electrode layer, the passivation layer PVX, the planarization layer PLN, the third conductive layer, the interlayer insulating layer IDL, the second conductive layer, and the first conductive layer.
  • the connection opening PDL1 exposes the connection electrode EL, so that the subsequently formed second electrode layer E2 is electrically connected to the connection electrode EL through the connection opening PDL1.
  • the display substrate also has a luminescent material layer E2 (for example, formed by inkjet printing), a second electrode layer E3 (for example, formed by sputtering), an encapsulation layer and other structures.
  • a luminescent material layer E2 for example, formed by inkjet printing
  • a second electrode layer E3 for example, formed by sputtering
  • an encapsulation layer and other structures.
  • the formation method and specific structure can be found in The related technology and the description of Figure 6 will not be described again here.
  • the second power signal line VSS and the first power signal line VDD in the display area AA are arranged in the same layer as the source and drain electrodes Ts and Td, and the first power signal line VDD is connected to The first power signal bus VDB; the first power signal bus VDB is arranged on the same layer as the light-shielding layer SH, and different parts of the second power signal bus VSB are arranged on the same layer as the gate electrode Tg and the source-drain electrode Ts/Td respectively, which can increase the height.
  • the distance between the power signal lines and the first power signal bus VDB being far away from the second electrode layer E3 can prevent the first power signal bus VDB from being short-circuited with the second electrode layer E3 and improve the yield of the display substrate;
  • the second power signal bus VSB Different parts of are respectively arranged on the side close to the display area AA and the side far away from the display area AA to at least partially surround the first power signal bus VDB, which can provide electromagnetic shielding for the first power signal bus VDB;
  • the second electrode The layer E3 passes through the connection opening in the pixel definition layer PDL, and uses the connection electrode EL provided in the same layer as the first electrode E1 to be electrically connected to the second power signal bus VSB, which is beneficial to the second electrode layer E3 and the second power signal bus VSB.
  • the intersection of the first power connection line DL and the second power signal bus VSB that is electrically connected to the first power signal bus VDB adopts a trench design, that is, the second power signal bus VSB has a first hollow portion and a third hollow part, which can avoid the formation of parasitic capacitance; the large-area second power signal bus VSB also has a second hollow part, which can increase the transparent area and reduce the etching difference, thereby ensuring the yield of the display substrate and Improve display effect.
  • the display substrate provided by the embodiments of the present disclosure can achieve narrow borders and larger screens while having better display effects and manufacturing yields.

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Abstract

一种显示基板，该显示基板具有显示区域(AA)和周边区域(NA)，且包括衬底基板(101)以及位于衬底基板(101)上的多个子像素(SP)、第一电源信号线(VDD)、第二电源信号线(VSS)、第一电源信号总线(VDB)和第二电源信号总线(VSB)，多个子像素(SP)位于显示区域(AA)，第一电源信号线(VDD)和第二电源信号线(VSS)至少部分位于显示区域(AA)，第一电源信号线(VDD)配置为向至少部分子像素(SP)传输第一电源信号，第二电源信号线(VSS)配置为向至少部分子像素(SP)传输第二电源信号；第一电源信号总线(VDB)和第二电源信号总线(VSB)位于周边区域(NA)，第一电源信号线(VDD)与第一电源信号总线(VDB)电连接，第二电源信号线(VSS)与第二电源信号总线(VSB)电连接，第二电源信号总线(VSB)包括设置在第一电源信号总线(VDB)靠近显示区域(AA)一侧的第一部分(VSB1)以及设置在第一电源信号总线(VDB)远离显示区域(AA)一侧的第二部分(VSB2)，以至少部分围绕第一电源信号总线(VDB)。该显示基板具有更好的显示效果。

Description

显示基板 技术领域
本公开的实施例涉及一种显示基板。
背景技术
在显示领域，有机发光二极管(OLED)显示面板具有自发光、对比度高、能耗低、视角广、响应速度快、可用于挠曲性面板、使用温度范围广、制造简单等特点，具有广阔的发展前景。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板具有显示区域以及至少部分围绕所述显示区域的周边区域，且包括衬底基板、多个子像素、第一电源信号线、第二电源信号线、第一电源信号总线和第二电源信号总线，多个子像素设置在所述衬底基板上且位于所述显示区域，第一电源信号线和第二电源信号线设置在所述衬底基板上且至少部分位于所述显示区域，其中，所述第一电源信号线配置为向所述多个子像素中的至少部分传输第一电源信号，所述第二电源信号线配置为向所述多个子像素中的至少部分传输不同于所述第一电源信号的第二电源信号；第一电源信号总线和第二电源信号总线设置在所述衬底基板上且位于所述周边区域，其中，所述第一电源信号线与所述第一电源信号总线电连接，所述第二电源信号线与所述第二电源信号总线电连接，所述第二电源信号总线包括设置在所述第一电源信号总线靠近所述显示区域一侧的第一部分以及设置在所述第一电源信号总线远离所述显示区域一侧的第二部分，以至少部分围绕所述第一电源信号总线。
例如，本公开至少一实施例提供的显示基板还包括：遮光层，设置在所述衬底基板上，其中，所述多个子像素的每个包括发光器件以及驱动所述发光器件的像素驱动电路，所述像素驱动电路设置在所述遮光层的远离所述衬底基板的一侧，所述第一电源信号总线与所述遮光层同层设置。
例如，本公开至少一实施例提供的显示基板中，所述像素驱动电路包括薄膜晶体管，所述薄膜晶体管包括设置在所述遮光层的远离所述衬底基板一侧的栅极和位于所述栅极远离所述衬底基板一侧的源漏电极，所述第一部分与所述源漏电极同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第二部分与所述栅极同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第二电源信号总线还包括电连接所述第一部分和所述第二部分的第三部分和第四部分，所述第三部分和所述第四部分位于所述第一电源信号总线的相对两侧，所述第一部分、所述第二部分、所述第三部分和所述第四部分一起共同围绕所述第一电源信号总线。
例如，本公开至少一实施例提供的显示基板中，所述第三部分和所述第四部分与所述第一部分同层设置，且与所述第一部分一体连接。
例如，本公开至少一实施例提供的显示基板中，所述第三部分和所述第四部分的结构对称。
例如，本公开至少一实施例提供的显示基板还包括：第一电源连接线，与所述第一电源信号总线同层设置，电连接所述第一电源信号总线与所述第一电源信号线。
例如，本公开至少一实施例提供的显示基板中，所述第一电源信号线与所述源漏电极同层设置，并通过转接过孔与所述第一电源连接线电连接。
例如，本公开至少一实施例提供的显示基板中，所述第二电源信号线与所述源漏电极同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第二电源信号线从所述显示区域延伸至所述周边区域并与所述第一部分电连接。
例如，本公开至少一实施例提供的显示基板中，所述第一电源信号的电位高于所述第二电源信号的电位。
例如，本公开至少一实施例提供的显示基板还包括平坦化层以及第一电极层；平坦化层设置在所述源漏电极的远离所述衬底基板的一侧，包括设置在所述周边区域的暴露所述第一部分的第一过孔以及设置在所述显示区域的暴露所述源漏电极的第二过孔，第一电极层设置在所述 平坦化层的远离所述衬底基板的一侧，包括设置在所述显示区域的第一电极以及设置在所述周边区域的连接电极，所述第一电极通过所述第二过孔与所述源漏电极电连接，所述连接电极通过所述第一过孔与所述第一部分电连接。
例如，本公开至少一实施例提供的显示基板还包括：像素界定层，设置在所述第一电极层的远离所述衬底基板一侧，包括设置在所述周边区域的连接开口以及设置在所述显示区域的子像素开口，所述连接开口暴露所述连接电极，所述子像素开口暴露所述第一电极。
例如，本公开至少一实施例提供的显示基板还包括发光材料层以及第二电极层；发光材料层至少部分设置在所述子像素开口中，第二电极层设置在所述发光材料层的远离所述衬底基板的一侧，并从所述显示区域延伸至所述周边区域，且通过所述连接开口与所述连接电极电连接。
例如，本公开至少一实施例提供的显示基板中，所述第二电极层终止于所述第一电源信号总线的靠近所述显示区域的一侧，且与所述第一电源信号总线具有间隔。
例如，本公开至少一实施例提供的显示基板中，在垂直于所述衬底基板的方向上，所述第一部分与所述第一电源连接线至少部分交叠，且所述第一部分包括在垂直于所述衬底基板的方向上与所述第一电源连接线交叠的第一镂空部分。
例如，本公开至少一实施例提供的显示基板中，所述第一部分还包括在垂直于所述衬底基板的方向上与所述第一电源连接线不交叠的第二镂空部分。
例如，本公开至少一实施例提供的显示基板中，在垂直于所述衬底基板的方向上，所述第三部分和所述第四部分中的至少一个与所述第一电源连接线至少部分交叠，且所述第三部分和所述第四部分中的至少一个包括在垂直于所述衬底基板的方向上与所述第一电源连接线交叠的第三镂空部分。
例如，本公开至少一实施例提供的显示基板中，所述第一电源连接线包括沿第一方向延伸的第一走线部分以及沿第二方向延伸的第二走线部分，所述第一方向不同于所述第二方向，在垂直于所述衬底基板的方向上，所述第一走线部分与所述第一部分至少部分交叠且与所述第一 镂空部分交叠，所述第二走线部分与所述第三部分和所述第四部分中的至少一个交叠，且与所述第三镂空部分交叠。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一实施例提供的显示基板的像素电路图；
图2A-图2C为本公开至少一实施例提供的像素电路的驱动方法的信号时序图；
图3为本公开至少一实施例提供的显示基板的平面示意图；
图4为图3中的显示基板在虚线框区域的部分平面示意图；
图5为图4中的显示基板在虚线框区域的部分平面放大示意图；
图6为本公开至少一实施例提供的显示基板的子像素的部分截面示意图；以及
图7-图13B为本公开至少一实施例提供的显示基板的各个功能层的部分平面示意图以及各个功能层依次叠层的部分平面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、 “左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
显示基板通常包括显示区域以及围绕显示区域的周边区域，显示区域具有多个子像素，用于显示。多个子像素中的至少部分子像素包括发光器件和驱动发光器件发光的像素驱动电路。周边区域包括向像素驱动电路提供控制信号的控制电路以及电源总线等结构。
在显示装置大屏化以及窄边框的发展趋势下，显示基板的周边区域的上述控制电路以及电源总线等结构的排布空间需要尽可能的小，此时，电路排布过于紧凑容易信号串扰等问题，因此，如何合理利用有限的排布空间布局上述电路结构是优化显示基板结构的重要方向。
在显示基板的多个子像素中，像素驱动电路通常实现为3T1C(三个薄膜晶体管和一个存储电容)、7T1C(七个薄膜晶体管和一个存储电容)、8T1C(八个薄膜晶体管和一个存储电容)或者8T2C(八个薄膜晶体管和两个存储电容)等结构，以实现驱动发光器件的效果。例如，下面以3T1C结构的像素驱动电路为例进行介绍，但是本公开的实施例对于像素驱动电路的具体结构不做限制。
例如，该3T1C结构的像素驱动电路包括用于驱动发光器件发光的驱动子电路和用于检测该子像素电特性以实现外部补偿的检测子电路。例如，图1示出了本公开至少一实施例提供的一种3T1C像素驱动电路的示意图。
参照图1，该像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容Cst。第一晶体管T1例如为驱动晶体管，第二晶体管T2例如为数据写入晶体管。第二晶体管T2的第一源漏电极与存储电容Cst的第一电容电极Ca和第一晶体管T1的栅极电连接，第二晶体管T2的第二源漏电极配置为接收数据信号DT，第二晶体管T2配置为响应于第一控制信号G1将该数据信号DT写入第一晶体管T1的栅极和存储电容Cst；第一晶体管T1的第一源漏电极与存储电容Cst的第二电容电极Cb电连接，并配置为与发光器件EM的第一电极电连接，第一晶体管T1的第二源漏电极配置为接收第一电源电压V1(例如通过电源信号线VDD接受高电源电压)，第一晶体管T1配置为在第一晶体管T1的栅极的电压的控制下控制用于驱动发光器件的电流；第三晶体管T3的第一源漏电极与第一晶体管T1的第一源漏电极以及存储电容Cst的第二电容电极Cb电连接，第三晶体管T3的第二源 漏电极配置为与检测线SEN连接以连到外部检测电路，第三晶体管T3配置为响应于第二控制信号G2检测所属的子像素的电特性以实现外部补偿；该电特性例如包括第一晶体管T1的阈值电压和/或载流子迁移率，或者发光器件EM的阈值电压、驱动电流等。该外部检测电路例如为包括数模转换器(DAC)和模数转换器(ADC)等的常规电路，本公开的实施例对此不作赘述。
例如，图1所示的存储电容Cst还包括第三电容电极Cc，该第三电容电极Cc位于第一电容电极Ca远离第二电容电极Cb的一侧且与第二电容电极Cb电连接从而形成并联电容的结构，增大存储电容Cst的电容值。例如，发光器件EM的第二电极与电源信号线VSS电连接，以接收低电源电压。
本公开的实施例中采用的晶体管均可以为薄膜晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两个电极，直接描述了其中一个电极为第一源漏电极，另一个电极为第二源漏电极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。需要说明的是，在下面的描述中均以图1中的晶体管为N型晶体管为例进行说明，然而该描述不作为对本公开的限制。
下面结合图2A-图2C所示的信号时序图对图1所示的像素驱动电路的工作原理进行说明，其中图2A示出了该像素驱动电路在显示过程的信号时序图，图2B和图2C示出了该像素驱动电路在检测过程的信号时序图。
例如，如图2A所示，每一帧图像的显示过程包括数据写入和复位阶段1以及发光阶段2。图2A示出了每个阶段中各个信号的时序波形。该3T1C像素驱动电路的一种工作过程包括：在数据写入和复位阶段1，第一控制信号G1和第二控制信号G2均为开启信号，第二晶体管T2和第三晶体管T3导通，数据信号DT经第二晶体管T2传输至第一晶体管T1的栅极，第一开关K1关闭，模数转换器通过检测线SEN及第三晶体管T3向发光器件EM 的第一电极(例如阳极)写入复位信号，第一晶体管T1导通并产生驱动电流将发光器件的第一电极充电至工作电压；在发光阶段2，第一控制信号G1和第二控制信号G2均为关闭信号，由于存储电容Cst的自举效应，存储电容Cst两端的电压保持不变，第一晶体管T1工作在饱和状态且电流不变，并驱动发光器件发光。
例如，图2B示出了该像素驱动电路在进行阈值电压的检测时的信号时序图。该3T1C像素驱动电路的一种工作过程包括：第一控制信号G1和第二控制信号G2均为开启信号，第二晶体管T2和第三晶体管T3导通，数据信号DT经第二晶体管T2传输至第一晶体管T1的栅极；模数转换器通过检测线SEN及第三晶体管T3向发光器件EM的第一电极(节点S)写入复位信号，第一晶体管T1导通并对节点S进行充电直至第一晶体管T1截止，数模转换器对检测线SEN上的电压取样即可得到第一晶体管T1的阈值电压。该过程例如可以在显示装置关机时进行。
例如，图2C示出了该像素驱动电路在进行载流子迁移率的检测时的信号时序图。该3T1C像素驱动电路的一种工作过程包括：在第一阶段，第一控制信号G1和第二控制信号G2均为开启信号，第二晶体管T2和第三晶体管T3导通，数据信号DT经第二晶体管T2传输至第一晶体管T1的栅极；模数转换器通过检测线SEN及第三晶体管T3向发光器件EM的第一电极(节点S)写入复位信号；在第二阶段，第一控制信号G1为关闭信号，第二控制信号G1为开启信号，第二晶体管T2关断，第三晶体管T3导通，并将检测线SEN浮置；由于存储电容Cst的自举效应，存储电容Cst两端的电压保持不变，第一晶体管T1工作在饱和状态且电流不变并驱动发光器件发光，然后数模转换器对检测线SEN上的电压取样，并结合发光电流的大小和持续时间可以计算出第一晶体管T1中的载流子迁移率。例如，该过程可以在显示阶段之间的消隐阶段进行。
通过上述检测可以得到第一晶体管T1的电特性并实现相应的补偿算法。
例如，显示基板的周边区域包括分别为电源信号线VDD以及电源信号线VSS提供电源信号的电源总线，由于电源信号线VDD用于传输高电平信号，该高电平信号容易与显示基板上传输的其他信号产生串扰，因此需要对电源总线的排布进行优化设计。
本公开至少一实施例提供一种显示基板，该显示基板具有显示区域以及至少部分围绕显示区域的周边区域，且包括衬底基板、多个子像素、第一电源信号线、第二电源信号线、第一电源信号总线和第二电源信号总线；多个子像素设置在衬底基板上且位于显示区域，第一电源信号线和第二电源信号线设置在衬底基板上且至少部分位于显示区域，第一电源信号线配置为向多个子像素中的至少部分传输第一电源信号，第二电源信号线配置为向多个子像素中的至少部分传输不同于第一电源信号的第二电源信号；第一电源信号总线和第二电源信号总线设置在衬底基板上且位于周边区域，第一电源信号线与第一电源信号总线电连接，第二电源信号线与第二电源信号总线电连接，第二电源信号总线包括设置在第一电源信号总线靠近显示区域一侧的第一部分以及设置在第一电源信号总线远离显示区域一侧的第二部分，以至少部分围绕第一电源信号总线。
在本公开实施例提供的上述显示基板中，在周边区域，第二电源信号总线至少部分围绕第一电源信号总线，从而可以达到为第一电源信号总线屏蔽电磁干扰的作用，使第一电源信号总线的信号传输更准确，提高显示基板的显示效果。
下面，通过几个具体的实施例来详细介绍本公开实施例提供的显示基板。
本公开至少一实施例提供一种显示基板，图3示出了该显示基板的平面示意图，图4示出了图3中的显示基板在虚线框区域的放大示意图，图5示出了图4中的显示基板在虚线框区域的放大示意图，图6示出了显示基板的子像素的部分截面示意图。
如图3所示，该显示基板具有显示区域AA以及至少部分围绕显示区域AA的周边区域NA。结合图3-图6，该显示基板还包括衬底基板101、多个子像素SP、第一电源信号线VDD、第二电源信号线VSS、第一电源信号总线VDB和第二电源信号总线VSB等结构。
多个子像素SP设置在衬底基板101上且位于显示区域AA，用于实现显示效果。第一电源信号线VDD和第二电源信号线VSS设置在衬底基板101上且至少部分位于显示区域AA。第一电源信号线VDD配置为向多个子像素SP中的至少部分传输第一电源信号，第二电源信号线VSS配置为向多个子像素SP中的至少部分传输不同于第一电源信号 的第二电源信号。
例如，在一些实施例中，第一电源信号的电位高于第二电源信号的电位，也即，第一电源信号线VDD用于传输高电源电压，第二电源信号线VSS用于传输低电源电压。例如，在一些实施例中，第二电源信号总线VSB可以接地。
第一电源信号总线VDB和第二电源信号总线VSB设置在衬底基板101上且位于周边区域NA，第一电源信号线VDD与第一电源信号总线VDB电连接，以从第一电源信号总线VDB获取第一电源信号。例如，在一些实施例中，第一电源信号线VDD可以从显示区域AA延伸至周边区域NA，以与第一电源信号总线VDB电连接。第二电源信号线VSS与第二电源信号总线VSV电连接，以从第二电源信号总线VSB获取第二电源信号。例如，在一些实施例中，第二电源信号线VSS可以从显示区域AA延伸至周边区域NA，以与第二电源信号总线VSV电连接。
例如，如图4和图5所示，第二电源信号总线VSB包括设置在第一电源信号总线VDB靠近显示区域AA一侧(图中的下侧)的第一部分VSB1以及设置在第一电源信号总线VDB远离显示区域AA一侧(图中的上侧)的第二部分VSB2，以使得第二电源信号总线VSB至少部分围绕第一电源信号总线VDB。由此，第二电源信号总线VSB至少可以达到在第一电源信号总线VDB的相对两侧(图中的上下两侧)为第一电源信号总线VDB屏蔽电磁干扰的作用，使第一电源信号总线VDB的信号传输更准确，提高显示基板的显示效果。
例如，在一些实施例中，如图6所示，显示基板还包括遮光层SH，遮光层SH设置在衬底基板101上，例如，多个子像素的每个包括发光器件EM以及驱动发光器件的像素驱动电路，像素驱动电路设置在遮光层SH的远离衬底基板101的一侧。例如，像素驱动电路包括薄膜晶体管(图6中示出为驱动晶体管)和存储电容等结构。薄膜晶体管包括设置在遮光层SH的远离衬底基板101一侧的有源层Ta、设置在有源层Ta的远离衬底基板101一侧的栅极Tg和设置在栅极Tg远离衬底基板101一侧的源漏电极Td和Ts，源漏电极Td和Ts分别通过过孔与有源层Ta电连接。
例如，在垂直于衬底基板101的方向上，也即图6中的竖直方向上， 遮光层SH与有源层Ta至少部分交叠，从而达到为有源层Ta遮光的效果，避免外界光照射到有源层Ta而影响薄膜晶体管的正常工作。
例如，如图6所示，存储电容包括第一电容电极Ca、第二电容电极Cb以及第三电容电极Cc，在垂直于衬底基板101的方向上，第一电容电极Ca和第二电容电极Cb彼此交叠以构成第一电容C1，第一电容电极Ca和第三电容电极Cc彼此交叠以构成第一电容C2，第一电容C1和第一电容C2并联，由此可以增大存储电容的电容量。
例如，如图6所示，第一电容电极Ca与有源层Ta同层设置，第二电容电极Cb与源漏电极Td和Ts同层设置，第三电容电极Cc与遮光层SH同层设置，以简化显示基板的制备工艺，并避免显示基板具有过多的功能层而增加显示基板的厚度，由此利于显示基板的薄型化设计。
需要注意的是，在本公开的实施例中，“同层设置”为两个或多个功能层或结构层在显示基板的层级结构中同层且同材料形成，即在制备工艺中，该两个功能层或结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构，由此可简化显示基板的制备工艺。
例如，在一些实施例中，第一电源信号总线VDB与遮光层SH同层设置。例如，第二电源信号总线VSB的第一部分VSB1与源漏电极Td和Ts同层设置。例如，第二电源信号总线VSB的第二部分VSB2与栅极Tg同层设置，由此可进一步简化显示基板的制备工艺，并避免显示基板具有过多的结构层，使显示基板薄型化；另外，第一电源信号总线VDB、第二电源信号总线VSB的第一部分VSB1和第二部分VSB2分别采用不同的金属层的制作，可以增大第一电源信号总线VDB与第二电源信号总线VSB的距离，因此可以避免信号线过近产生短路等不良现象。
例如，在一些实施例中，如图4所示，第二电源信号总线VSB还包括电连接第一部分VSB1和第二部分VSB3的第三部分VSB3和第四部分VSB4，第三部分VSB3和第四部分VSB4位于第一电源信号总线VDS的相对两侧，例如图4中的左右两侧，此时，第一部分VSB1、第二部分VSB、第三部分VSB3和第四部分VSB4一起共同围绕第一电源信号总线VDB。例如，如图4所示，第一部分VSB1、第二部分VSB、 第三部分VSB3和第四部分VSB4完全围绕第一电源信号总线VDB，以充分为第一电源信号总线VDB实现防信号串扰的作用。
例如，在一些实施例中，如图4所示，第三部分VSB3和第四部分VSB4可以与第一部分VSB1同层设置，且与第一部分VSB一体连接，第三部分VSB3和第四部分VSB4通过过孔与第二部分VSB2电连接，从而第二电源信号总线VSB的第一部分VSB1、第二部分VSB、第三部分VSB3和第四部分VSB4形成一个整体，用于传输相同的低电源信号，并且可以降低第二电源信号总线VSB的压降。
例如，在一些实施例中，如图4所示，第三部分VSB3和第四部分VSB4的结构对称，也即具有基本相同的形状、尺寸以及布局等，从而可以保持显示基板左右两侧的信号传输性能基本一致，提高显示基板的显示均匀性。
例如，在一些实施例中，如图5所示，显示基板还包括第一电源连接线DL，第一电源连接线DL可以与第一电源信号总线VDB同层设置，也即与遮光层SH同层设置，第一电源连接线DL用于电连接第一电源信号总线VDB与第一电源信号线VDD。
例如，在一些实施例中，第一电源连接线DL可以与第一电源信号总线VDB同层设置且一体连接。
例如，在一些实施例中，如图5所示，第一电源信号线VDD可以与源漏电极Td和Ts同层设置，并通过转接过孔V与第一电源连接线DL电连接。例如，在一些实施例中，第二电源信号线VSS与源漏电极Td和Ts同层设置，且与第二电源信号总线VSB的第一部分VSB1一体连接。
例如，如图5所示，第二电源信号线VSS从显示区域AA延伸至周边区域NA并与第二电源信号总线VSB的第一部分VSB1电连接，例如一体连接。
例如，在一些实施例中，如图5所示，在垂直于衬底基板101的方向上，第二电源信号总线VSB的第一部分VSB1与第一电源连接线DL至少部分交叠，且第一部分VSB1包括在垂直于衬底基板101的方向上与第一电源连接线DL交叠的第一镂空部分H1，由此可以减小第一电源连接线DL与第一部分VSB1的交叠面积，避免第一电源连接线DL 与第一部分VSB1形成寄生电容等结构影响电信号的正常传输。
例如，在一些实施例中，如图5所示，第二电源信号总线VSB的第一部分VSB1还包括在垂直于衬底基板101的方向上与第一电源连接线DL不交叠的第二镂空部分H2。第二镂空部分H2的设置可以增加区域透明度，并减小大面积设置的第一部分VSB1在不同区域的刻蚀差异，提高大面积设置的第一部分VSB1的刻蚀均匀性。
例如，在一些实施例中，如图4和图5所示，在垂直于衬底基板101的方向上，第二电源信号总线VSB的第三部分VSB3和第四部分VSB4中的至少一个(例如第三部分VSB3和第四部分VSB4二者)与第一电源连接线DL至少部分交叠，且第三部分VSB3和第四部分VSB4中的至少一个(例如第三部分VSB3和第四部分VSB4二者)包括在垂直于衬底基板101的方向上与第一电源连接线DL交叠的第三镂空部分H3，由此可以减小第一电源连接线DL与第三部分VSB3和第四部分VSB4的交叠面积。
例如，在其他实施例中，第三部分VSB3和第四部分VSB4还可以包括在垂直于衬底基板101的方向上与第一电源连接线DL不交叠的镂空部(图中未示出)，以提高第三部分VSB3和第四部分VSB4的刻蚀均匀性。
例如，在一些实施例中，如图5所示，第一电源连接线DL可以包括沿第一方向(图中的竖直方向)延伸的第一走线部分DL1以及沿第二方向(图中的水平方向)延伸的第二走线部分DL2，第一方向不同于第二方向，例如，第一方向垂直于第二方向。例如，结合图4和图5，第一走线部分DL1包括多条第一走线，多条第一走线相互平行；第二走线部分DL2包括相对设置的两条第二走线，该两条第二走线设置在同一直线上。例如，部分第一走线直接与第一电源信号总线VDB连接，部分第一走线与第二走线连接，并通过第二走线与第一电源信号总线VDB电连接。
例如，在垂直于衬底基板101的方向上，第一走线部分DL1与第二电源信号总线VSB的第一部分VSB1至少部分交叠且与第一镂空部分H1交叠，第二走线部分DL2与第二电源信号总线VSB的第三部分VSB3和第四部分VSB4中的至少一个(例如第三部分VSB3和第四部 分VSB4二者)交叠，且与第三镂空部分H3交叠。
例如，在一些实施例中，如图6所示，显示基板还包括平坦化层PLN以及第一电极层。平坦化层PLN设置在源漏电极Td和Ts的远离衬底基板101的一侧，从而平坦化像素驱动电路，提供平坦的表面，以利于第一电极层的设置。结合图4和图6，平坦化层PLN包括设置在周边区域NA的暴露第二电源信号总线VSB的第一部分VSB1的第一过孔V1以及设置在显示区域AA的暴露源漏电极Ts的第二过孔V2。
例如，如图6所示，第一电极层设置在平坦化层PLN的远离衬底基板101的一侧，结合图5和图6，第一电极层包括设置在显示区域AA的第一电极E1以及设置在周边区域NA的连接电极EL，第一电极E1通过第二过孔V2与源漏电极Ts电连接，连接电极EL通过第一过孔V1与第二电源信号总线VSB的第一部分VSB1电连接。例如，第一电极E1可以作为发光器件EM的阳极。
例如，在一些实施例中，如图6所示，显示基板还包括像素界定层PDL，像素界定层PDL设置在第一电极层的远离衬底基板101一侧，结合图5和图6，像素界定层PDL包括设置在周边区域NA的连接开口PDL1以及设置在显示区域AA的子像素开口PDL2，连接开口PDL1暴露连接电极EL，子像素开口PDL2暴露第一电极E1，从而限定出发光器件EM的有效发光区域。
例如，在一些实施例中，如图6所示，显示基板还包括发光材料层E2以及第二电极层E3。发光材料层E2至少部分设置在子像素开口PDL2中，从而可以被子像素开口PDL2暴露的第一电极E1驱动而发光。第二电极层E3设置在发光材料层E2的远离衬底基板101的一侧。例如，第二电极层E3可以作为发光器件EM的阴极。例如，在一些实施例中，第二电极层E3可以为整面形成的电极层，也即在衬底基板上连续设置为片状，并从显示区域AA延伸至周边区域NA，且通过连接开口PLN1与连接电极EL电连接，从而第二电极层E3可以与第二电源信号总线VSB的第一部分VSB1电连接，以接收低电源信号。
例如，在一些实施例中，如图5所示，第二电极层E3终止于第一电源信号总线VDS的靠近显示区域AA的一侧，例如第二电极层E3的终止边界线为E3D，由此，第二电极层E3与第一电源信号总线VDB 具有间隔，也即边界线为E3D与第一电源信号总线VDB具有间隔，例如间隔距离大于1.0微米，例如为1.20微米、1.30微米、1.35微米、1.40微米、1.45微米或者1.50微米等。由此可以降低第二电极层E3与第一电源信号总线VDB发生短路的风险，提高显示基板的制备良率。
例如，在一些实施例中，显示基板还可以包括设置在衬底基板101上的阻挡层和缓冲层(图中未示出)等结构，以防止杂质从衬底基板101进入到衬底基板101上的各个功能层中。例如，如图6所示，显示基板还可以包括设置在遮光层SH上的绝缘层102、设置在有源层Ta上的栅绝缘层GI、设置在栅极Tg上的层间绝缘层IDL、设置在源漏电极Td和Ts上的钝化层PVX以及设置在第二电极层上的封装层(图中未示出)等结构。
例如，钝化层PVX具有与平坦化层PLN的第二过孔V2贯穿的过孔PVX1，从而第一电极E1通过第二过孔V2和过孔PVX1与源漏电极Ts电连接。例如，钝化层PVX还包括与第一过孔V1贯穿的过孔PVX2(参见图11A，稍后详述)，从而连接电极EL通过第一过孔V1以及过孔PVX2与第二电源信号总线VSB的第一部分VSB1电连接。
例如，封装层可以为复合封装层，包括多个无机封装层与有机封装层的叠层，例如无机封装层/有机封装层/无机封装层的三层叠层结构，以具有更好封装效果。例如，显示基板还可以包括设置在封装层上的盖板(例如玻璃透明盖板)等结构，本公开的实施例对显示基板上的其他结构不做具体限定。
例如，本公开的实施例中，衬底基板101可以采用玻璃、石英等刚性基板或者聚酰亚胺(PI)等柔性基板。有源层Ta以及第一电容电极Ca的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。在制备过过程中，第一电容电极Ca的半导体材料被导体化，以具有良好的导电性。遮光层SH、第三电容电极Cc以及第一电源信号总线VDD可以采用铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钛(Ti)、钨(W)等金属材料或者合金材料。例如，栅极Tg以及第二电源信号总线VSB的第二部分VSB2可以采用铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钛(Ti)、钨(W)等金属材料或 者合金材料。例如，栅极Tg以及第二电源信号总线VSB的第二部分VSB2可以为单层或者多层结构，例如钼钛合金与铜的叠层结构等。例如，源漏电极Td和Ts、第二电容电极Cb以及第二电源信号总线VSB的第一部分VSB1、第三部分VSB3和第四部分VSB4可以采用铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钛(Ti)、钨(W)等金属材料或者合金材料，例如也可以形成为单层或者多层结构，例如钼钛合金与铜的叠层结构等。
例如，绝缘层102、栅绝缘层GI、层间绝缘层IDL、钝化层PVX以及无机封装层可以为无机绝缘层，例如采用氧化硅(SiOx)、氮化硅(SiNy)或者氮氧化硅(SiOxNy)等无机绝缘材料制作。例如，平坦化层PLN、像素界定层PDL以及有机封装层可以为有机绝缘层，例如可以采用聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等有机绝缘材料制作。
例如，第一电极E1以及连接电极EL可以采用具有高功函数的材料，例如透明金属氧化物，例如ITO、IZO等，例如，第一电极E1还可以包括Ag等金属层，从而形成透明金属氧化物/金属层的多层结构。例如，发光材料层E2可以包括有机发光材料，从而发光器件EM形成为有机发光器件(OLED)；或者，在另一些实施例中，发光材料层E2也可以包括量子点发光材料，从而发光器件EM形成为量子点器件(QLED)。例如，第二电极层E3可以采用镁(Mg)、锂(Li)、铝(Al)、银(Ag)等金属材料或者合金材料等。本公开的实施例对各个功能层的材料不做限制。
例如，图7-图13B示出了显示基板的各个功能层的部分平面示意图以及各个功能层依次叠层的部分平面示意图。下面，以图7-图13B示出的结构为例对显示基板的各个功能层及其相对位置关系进行介绍。
例如，图7示出了遮光层SH所在的第一导电层的部分平面示意图，如图7所示，第一导电层包括遮光层SH、第一电源信号总线VDB、第一电源信号连接线DL等结构。
例如，在制备过程中，可以采用溅射工艺在衬底基板101上形成第一导电层的材料，并经过光刻工艺对第一导电层的材料进行图案化，以得到遮光层SH、第一电源信号总线VDB、第一电源信号连接线DL等 结构的图案。
例如，光刻工艺可以包括光刻胶的涂覆、曝光、显影以及刻蚀等工艺，具体可以参见相关技术，在此不再赘述。
例如，参考图6，第一导电层上可以形成绝缘层102，在制备过程中，可以采用沉积工艺形成绝缘层102的材料，绝缘层102的材料可以包括SiNx、SiOx或SiOxNy的一种或多种，厚度可以为150nm-500nm，例如200nm、300nm或者400nm等。
例如，在制备过程中，可以采用溅射工艺在绝缘层102上形成半导体氧化物，例如IGZO、ZnON、ITZO等非晶氧化物形成半导体材料层，并经过光刻工艺对半导体材料层进行图案化，形成有源层Ta以及第一电容电极Ca的图案，例如，后续可以对第一电容电极Ca的图案以及部分有源层Ta的图案进行导体化处理，例如掺杂处理，以具有良好的导电性。
例如，在制备过程中，可以采用沉积工艺形成栅绝缘层GI的材料，再用溅射工艺在栅绝缘层GI的材料上形成第二导电层的材料，第二导电层的材料的沉积厚度可以为200nm-1000nm，例如400nm、600nm或者800nm等，并经过光刻工艺形成栅极Tg以及第二电源信号总线VSB的第二部分VSB2，如图8A所示。例如，上述光刻工艺中使用的光刻胶图案可以不剥离，该光刻胶图案可以作为掩模，采用干刻蚀工艺对栅绝缘层GI的材料进行刻蚀以形成栅绝缘层GI的图形，并采用NH 3、N 2或H 2等气体对露在外面的半导体材料层进行导体化处理，以使被处理的半导体材料层具有良好的导电性。
例如，图8B示出了第二导电层与第一导电层叠层的部分平面示意图，如图8B所示，第二电源信号总线VSB的第二部分VSB2位于第一电源信号总线VDB的远离显示区域AA的一侧。
例如，图9A示出了层间绝缘层IDL的部分平面示意图，如图9所示，层间绝缘层IDL包括用于电连接第二电源信号总线VSB的第三部分VSB3(以及第四部分VSB4)与第二部分VSB2的过孔VS1以及用于电连接源漏电极Ts/Td与有源层Ta的过孔VS2。
例如，在制备过程中，可以采用沉积工艺在第二导电层上沉积层间绝缘层IDL的材料，并通过干刻工艺得到过孔VS1以及过孔VS2。例 如，层间绝缘层IDL的材料可以为SiNx或SiOx形成的单层或多层结构。
例如，图9B示出了层间绝缘层IDL与第二导电层、第一导电层叠层的部分平面示意图，如图9B所示，过孔VS1暴露第二电源信号总线VSB的第二部分VSB2，过孔VS2暴露有源层Ta。
例如，在制备过程中，可以采用溅射工艺在层间绝缘层IDL上形成第三导电层的材料，第三导电层的材料的沉积厚度可以为200nm-1000nm，并经过光刻工艺形成源漏电极Ts/Td以及第一电源信号线VDD、第二电源信号线VSS、第二电源信号总线VSB的第一部分VSB1、第三部分VSB3(以及第四部分VSB4)，如图10A所示。例如，第一部分VSB1具有第一镂空部分H1以及第二镂空部分H2，第三部分VSB3(以及第四部分VSB4)具有第三镂空部分H3。
例如，图10B示出了第三导电层与层间绝缘层IDL、第二导电层、第一导电层叠层的部分平面示意图，如图10B所示，第二电源信号总线VSB的第三部分VSB3(以及第四部分VSB4)通过过孔VS1与第二部分VSB2电连接，源漏电极Ts/Td通过过孔VS2与有源层Ta电连接，图中未具体示出，可参考图6。
例如，图11A示出了钝化层PVX和平坦化层PLN的部分平面示意图。在制备过程中，可以采用沉积工艺在第三导电层上形成钝化层PVX的材料，例如SiO 2，并经过光刻工艺形成钝化层PVX的图案，钝化层PVX包括位于显示区域AA的暴露源漏电极Ts的过孔PVX1以及位于周边区域NA的暴露第一部分VSB1的过孔PXV2。
例如，可以采用涂覆的方式在钝化层PVX形成平坦化层PLN的材料，例如聚酰亚胺，经230度后烘去除材料中的水和有机溶剂，形成厚度为约2.0μm～3.5μm的平坦化层PLN，之后通过曝光和显影形成位于周边区域NA并与过孔PXV2贯穿的第一过孔V1和位于显示区域AA并与过孔PVX1贯穿的第二过孔V2。
例如，图11B示出了钝化层PVX和平坦化层PLN与第三导电层、层间绝缘层IDL、第二导电层、第一导电层叠层的部分平面示意图，如图11B所示，在周边区域NA，第一过孔V1和过孔PXV2暴露第一部分VSB1。在显示区域AA，第二过孔V2和过孔PVX1暴露源漏电极 Ts，图11B中未示出，可参考图6。
例如，图12A示出了第一电极层的部分平面示意图。如图12A所示，第一电极层包括位于显示区域AA的第一电极E1以及位于周边区域NA的连接电极EL。在制备过程中，可以采用溅射工艺在平坦化层PLN上形成第一电极层的材料，材料的厚度为约100nm-600nm，例如200nm、300nm、400nm或者500nm等，并经过光刻工艺得到第一电极E1以及连接电极EL的图案。
例如，图12B示出了第一电极层与钝化层PVX、平坦化层PLN、第三导电层、层间绝缘层IDL、第二导电层、第一导电层叠层的部分平面示意图，如图12B所示，连接电极EL通过钝化层PVX和平坦化层PLN在周边区域NA的过孔与第一部分VSB1电连接。第一电极E1通过钝化层PVX和平坦化层PLN在显示区域AA的过孔与源漏电极Ts电连接，图12B中未具体示出，可以参考图6。
例如，图13A示出了像素界定层PLN的部分平面示意图，图中的阴影部分为像素界定层PLN的材料被去除的部分。例如，像素界定层PLN包括子像素开口区域PDL3，子像素开口区域PDL3具有用于多个子像素的子像素开口PDL2，子像素开口PDL2暴露第一电极E1，参考图6。像素界定层PLN还包括连接开口PDL1,连接开口PDL1暴露连接电极EL，以便于后续形成的第二电极层E2通过连接开口PDL1与连接电极EL电连接，进而与第二电源信号总线VSB的第一部分VSB1电连接。
例如，在制备过程中，可以采用涂覆工艺形成像素界定层PLN的材料，经过前烘、曝光、显影等形成连接开口PDL1、子像素开口PDL2等像素界定层PLN的图形，然后经230度后烘去除像素界定层PLN中的水和有机溶剂，最终形成厚度为1.8μm-2.0μm的像素界定层PLN。
例如，图13B示出了像素界定层PLN与第一电极层、钝化层PVX、平坦化层PLN、第三导电层、层间绝缘层IDL、第二导电层、第一导电层叠层的部分平面示意图，如图13B所示，连接开口PDL1暴露连接电极EL，以便于后续形成的第二电极层E2通过连接开口PDL1与连接电极EL电连接。
例如，显示基板上还具有发光材料层E2(例如通过喷墨打印的方 式形成)、第二电极层E3(例如采用溅射的方式形成)、封装层等结构，其形成方式以及具体结构可以参见相关技术以及图6的描述等，在此不再赘述。
在本公开的实施例中，显示区域AA中的第二电源信号线VSS和第一电源信号线VDD均与源漏电极Ts和Td同层设置，第一电源信号线VDD通过过孔转接至第一电源信号总线VDB；第一电源信号总线VDB与遮光层SH同层设置，第二电源信号总线VSB的不同部分分别与栅极Tg和源漏电极Ts/Td同层设置，可以增大高低电源信号线的距离，同时第一电源信号总线VDB远离第二电极层E3，可以防止第一电源信号总线VDB与第二电极层E3发生短路，提高显示基板的良率；第二电源信号总线VSB的的不同部分分别布局在靠近显示区域AA的一侧和远离显示区域AA的一侧，以至少部分环绕第一电源信号总线VDB，可以为第一电源信号总线VDB提供电磁屏蔽作用；第二电极层E3通过像素界定层PDL中的连接开口，并利用与第一电极E1同层设置的连接电极EL与第二电源信号总线VSB电连接，有利于第二电极层E3与第二电源信号总线VSB的搭接；另外，与第一电源信号总线VDB电连接的第一电源连接线DL与第二电源信号总线VSB交叠处采用挖槽设计，也即第二电源信号总线VSB具有第一镂空部分以及第三镂空部分，可以避免形成寄生电容；大面积设置的第二电源信号总线VSB还具有第二镂空部分，可以增加透明区域以及减小刻蚀差异，由此可保证显示基板的良率并提升显示效果。
综上，本公开实施例提供的显示基板可以在实现窄边框、大屏化的同时，具有更好的显示效果以及制备良率。
还有以下几点需要说明：
(1)本公开实施例的附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以 相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (20)

  1. 一种显示基板，具有显示区域以及至少部分围绕所述显示区域的周边区域，且包括：
    衬底基板，
    多个子像素，设置在所述衬底基板上且位于所述显示区域，
    第一电源信号线和第二电源信号线，设置在所述衬底基板上且至少部分位于所述显示区域，其中，所述第一电源信号线配置为向所述多个子像素中的至少部分传输第一电源信号，所述第二电源信号线配置为向所述多个子像素中的至少部分传输不同于所述第一电源信号的第二电源信号；
    第一电源信号总线和第二电源信号总线，设置在所述衬底基板上且位于所述周边区域，其中，所述第一电源信号线与所述第一电源信号总线电连接，所述第二电源信号线与所述第二电源信号总线电连接，
    所述第二电源信号总线包括设置在所述第一电源信号总线靠近所述显示区域一侧的第一部分以及设置在所述第一电源信号总线远离所述显示区域一侧的第二部分，以至少部分围绕所述第一电源信号总线。
  2. 根据权利要求1所述显示基板，还包括：
    遮光层，设置在所述衬底基板上，
    其中，所述多个子像素的每个包括发光器件以及驱动所述发光器件的像素驱动电路，所述像素驱动电路设置在所述遮光层的远离所述衬底基板的一侧，
    所述第一电源信号总线与所述遮光层同层设置。
  3. 根据权利要求2所述显示基板，其中，所述像素驱动电路包括薄膜晶体管，所述薄膜晶体管包括设置在所述遮光层的远离所述衬底基板一侧的栅极和位于所述栅极远离所述衬底基板一侧的源漏电极，
    所述第一部分与所述源漏电极同层设置。
  4. 根据权利要求3所述显示基板，其中，所述第二部分与所述栅极同层设置。
  5. 根据权利要求1-4任一所述显示基板，其中，所述第二电源信 号总线还包括电连接所述第一部分和所述第二部分的第三部分和第四部分，所述第三部分和所述第四部分位于所述第一电源信号总线的相对两侧，
    所述第一部分、所述第二部分、所述第三部分和所述第四部分一起共同围绕所述第一电源信号总线。
  6. 根据权利要求5所述显示基板，其中，所述第三部分和所述第四部分与所述第一部分同层设置，且与所述第一部分一体连接。
  7. 根据权利要求5或6所述显示基板，其中，所述第三部分和所述第四部分的结构对称。
  8. 根据权利要求3所述显示基板，还包括：
    第一电源连接线，与所述第一电源信号总线同层设置，电连接所述第一电源信号总线与所述第一电源信号线。
  9. 根据权利要求8所述显示基板，其中，所述第一电源信号线与所述源漏电极同层设置，并通过转接过孔与所述第一电源连接线电连接。
  10. 根据权利要求3所述显示基板，其中，所述第二电源信号线与所述源漏电极同层设置。
  11. 根据权利要求10所述显示基板，其中，所述第二电源信号线从所述显示区域延伸至所述周边区域并与所述第一部分电连接。
  12. 根据权利要求1-11任一所述显示基板，其中，所述第一电源信号的电位高于所述第二电源信号的电位。
  13. 根据权利要求3或4所述显示基板，还包括：
    平坦化层，设置在所述源漏电极的远离所述衬底基板的一侧，包括设置在所述周边区域的暴露所述第一部分的第一过孔以及设置在所述显示区域的暴露所述源漏电极的第二过孔，
    第一电极层，设置在所述平坦化层的远离所述衬底基板的一侧，包括设置在所述显示区域的第一电极以及设置在所述周边区域的连接电极，所述第一电极通过所述第二过孔与所述源漏电极电连接，所述连接电极通过所述第一过孔与所述第一部分电连接。
  14. 根据权利要求13所述显示基板，还包括：
    像素界定层，设置在所述第一电极层的远离所述衬底基板一侧，包 括设置在所述周边区域的连接开口以及设置在所述显示区域的子像素开口，所述连接开口暴露所述连接电极，所述子像素开口暴露所述第一电极。
  15. 根据权利要求14所述显示基板，还包括：
    发光材料层，至少部分设置在所述子像素开口中，
    第二电极层，设置在所述发光材料层的远离所述衬底基板的一侧，并从所述显示区域延伸至所述周边区域，且通过所述连接开口与所述连接电极电连接。
  16. 根据权利要求15所述显示基板，其中，所述第二电极层终止于所述第一电源信号总线的靠近所述显示区域的一侧，且与所述第一电源信号总线具有间隔。
  17. 根据权利要求8或9所述显示基板，其中，在垂直于所述衬底基板的方向上，所述第一部分与所述第一电源连接线至少部分交叠，且所述第一部分包括在垂直于所述衬底基板的方向上与所述第一电源连接线交叠的第一镂空部分。
  18. 根据权利要求17所述显示基板，其中，所述第一部分还包括在垂直于所述衬底基板的方向上与所述第一电源连接线不交叠的第二镂空部分。
  19. 根据权利要求17或18所述显示基板，其中，在垂直于所述衬底基板的方向上，所述第三部分和所述第四部分中的至少一个与所述第一电源连接线至少部分交叠，且所述第三部分和所述第四部分中的至少一个包括在垂直于所述衬底基板的方向上与所述第一电源连接线交叠的第三镂空部分。
  20. 根据权利要求19所述显示基板，其中，所述第一电源连接线包括沿第一方向延伸的第一走线部分以及沿第二方向延伸的第二走线部分，所述第一方向不同于所述第二方向，
    在垂直于所述衬底基板的方向上，所述第一走线部分与所述第一部分至少部分交叠且与所述第一镂空部分交叠，所述第二走线部分与所述第三部分和所述第四部分中的至少一个交叠，且与所述第三镂空部分交叠。
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