WO2021169568A1 - 显示母板及其制备方法、显示基板和显示装置 - Google Patents

显示母板及其制备方法、显示基板和显示装置 Download PDF

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Publication number
WO2021169568A1
WO2021169568A1 PCT/CN2020/140685 CN2020140685W WO2021169568A1 WO 2021169568 A1 WO2021169568 A1 WO 2021169568A1 CN 2020140685 W CN2020140685 W CN 2020140685W WO 2021169568 A1 WO2021169568 A1 WO 2021169568A1
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Prior art keywords
layer
insulating layer
cutting
display
planarization
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PCT/CN2020/140685
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English (en)
French (fr)
Inventor
韩林宏
张毅
赵广洲
张祎杨
杨玉清
刘庭良
于鹏飞
周洋
马群
李锡平
秦世开
黄炜赟
龙跃
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/414,332 priority Critical patent/US12004376B2/en
Publication of WO2021169568A1 publication Critical patent/WO2021169568A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/851—Division of substrate

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, in particular to a display motherboard and a preparation method thereof, a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • FIG. 1 is a schematic diagram of the arrangement of a plurality of display substrates on a display mother board.
  • a plurality of display substrate areas 300 on the display mother board 100 are arranged periodically and regularly, and the cutting area 400 is located at the periphery of each display substrate area 300.
  • the display substrate area 300 includes at least a display area 301 and a binding area 302.
  • the display area 301 includes a plurality of pixels arranged in a matrix.
  • the binding area 302 includes a driving circuit 303.
  • the binding area 302 is arranged on one side of the display area 301.
  • the cutting area 400 includes a circular cutting line 401 surrounding the display substrate area 300 and a plurality of cutting marks (Mark) 402.
  • the cutting equipment When cutting, the cutting equipment first recognizes the cutting mark, and then cuts according to the cutting mark, but there is a problem that the cutting mark cannot be recognized in production.
  • the present disclosure provides a display motherboard, the display motherboard includes a plurality of display substrate areas and a cutting area located at the periphery of each of the display substrate areas; the display motherboard further includes:
  • the driving structure layer includes a first source/drain metal layer
  • the marking structure layer includes a cutting marking layer
  • the cutting marking layer is provided in the same layer as the first source/drain metal layer.
  • the drive structure layer further includes: a first insulating layer disposed on the substrate, an active layer disposed on the first insulating layer, and a second insulating layer covering the active layer. Layer, a first gate metal layer arranged on the second insulating layer, a third insulating layer covering the first gate metal layer, a second gate metal layer arranged on the third insulating layer, covering all The fourth insulating layer of the second gate metal layer, the first source and drain metal layer is disposed on the fourth insulating layer; the identification structure layer further includes; a first insulating layer and a second insulating layer stacked on a substrate The second insulating layer, the third insulating layer and the fourth insulating layer, and the cutting marking layer is arranged on the fourth insulating layer.
  • the display motherboard further includes a fifth insulating layer; in the display substrate area, the fifth insulating layer is disposed on the drive structure layer, and in the cutting area, the The fifth insulating layer is disposed on the identification structure layer, and the planarization layer is disposed on the fifth insulating layer.
  • the planarization layer includes a second planarization layer provided on the fifth insulating layer and a pixel definition layer provided on the second planarization layer; on the display substrate In the region, an anode is also arranged between the second planarization layer and the pixel definition layer.
  • the driving structure layer includes a second source/drain metal layer
  • the marking structure layer includes a cutting marking layer
  • the cutting marking layer is provided in the same layer as the second source/drain metal layer.
  • the drive structure layer further includes: a first insulating layer disposed on the substrate, an active layer disposed on the first insulating layer, and a second insulating layer covering the active layer. Layer, a first gate metal layer arranged on the second insulating layer, a third insulating layer covering the first gate metal layer, a second gate metal layer arranged on the third insulating layer, covering all The fourth insulating layer of the second gate metal layer, the first source-drain metal layer disposed on the fourth insulating layer, covering the fifth insulating layer and the first planarization layer of the first source-drain metal layer, The second source and drain metal layer is disposed on the first planarization layer; the identification structure layer further includes: a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer stacked on a substrate. An insulating layer, a fifth insulating layer, and a first planarization layer, and the cutting mark layer is disposed on the
  • the planarization layer includes a second planarization layer covering the driving structure layer and the identification structure layer, and a pixel definition layer provided on the second planarization layer; in the display In the substrate area, an anode is further arranged between the second planarization layer and the pixel definition layer.
  • the display motherboard further includes a protective film; in the display substrate area, an encapsulation layer is provided on the planarization layer, and the protective film is provided on the encapsulation layer; In the cutting area, the protective film is disposed on the planarization layer.
  • the cutting mark layer of the cutting area includes a plurality of cutting marks, and the cutting marks include four rectangular patterns arranged in a square shape.
  • the present disclosure also provides a display substrate, which is formed by cutting the aforementioned display mother board along the cutting area.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • the present disclosure also provides a method for preparing a display motherboard, the display motherboard including a plurality of display substrate regions and a cutting region located at the periphery of each of the display substrate regions, and the manufacturing method includes:
  • the marking structure layer includes a cutting marking layer
  • a planarization layer is formed on the driving structure layer and the identification structure layer, and the planarization layer covers the identification structure layer.
  • the driving structure layer includes a first source-drain metal layer
  • the marking structure layer includes a cutting marking layer
  • the driving structure layer and the marking structure layer are formed in a plurality of display substrate areas and cutting areas, respectively, include:
  • first insulating layer Forming a first insulating layer on a substrate, forming an active layer on the first insulating layer, forming a second insulating layer covering the active layer, and forming a first gate metal layer on the second insulating layer, A third insulating layer covering the first gate metal layer is formed, a second gate metal layer is formed on the third insulating layer, and a fourth insulating layer covering the second gate metal layer is formed.
  • the first source-drain metal layer and the cutting mark layer are formed on the insulating layer through the same patterning process; the active layer, the first gate metal layer, the second gate metal layer and the first source-drain metal layer are arranged on the The substrate area is displayed, and the cutting marking layer is arranged in the cutting area.
  • forming a planarization layer on the driving structure layer and the marking structure layer includes:
  • a second planarization layer and a pixel definition layer are sequentially formed on the fifth insulating layer, and an anode is also formed between the second planarization layer and the pixel definition layer in the display substrate area.
  • the driving structure layer includes a second source-drain metal layer
  • the marking structure layer includes a cutting marking layer
  • the driving structure layer and the marking structure layer are formed in a plurality of display substrate areas and cutting areas, respectively, include:
  • first insulating layer Forming a first insulating layer on a substrate, forming an active layer on the first insulating layer, forming a second insulating layer covering the active layer, and forming a first gate metal layer on the second insulating layer, A third insulating layer covering the first gate metal layer is formed, a second gate metal layer is formed on the third insulating layer, and a fourth insulating layer covering the second gate metal layer is formed.
  • a first source-drain metal layer is formed on the insulating layer, a fifth insulating layer covering the first source-drain metal layer is formed, a first planarization layer is formed on the fifth insulating layer, and a first planarization layer is formed on the first planarization layer.
  • the second source-drain metal layer and the cutting identification layer are formed by the same patterning process; the active layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer and the second source-drain metal
  • the layer is arranged in the display substrate area, and the cutting mark layer is arranged in the cutting area.
  • forming a planarization layer on the driving structure layer and the marking structure layer includes:
  • a second planarization layer and a pixel definition layer are sequentially formed on the first planarization layer, and an anode is also formed between the second planarization layer and the pixel definition layer in the display substrate area.
  • the preparation method further includes:
  • the display mother board is cut to form a plurality of display substrates.
  • the preparation method further includes:
  • a cover plate is formed on the encapsulation layer; or a touch layer and a cover plate are sequentially formed on the encapsulation layer.
  • FIG. 1 is a schematic diagram of the arrangement of multiple display substrates on a display motherboard
  • FIG. 2 is a schematic diagram of the structure of a display motherboard of the present disclosure
  • FIG. 3 is a schematic diagram showing the pattern of the driving structure layer and the cutting mark layer formed by the mother board structure according to the present disclosure
  • FIG. 4 is a schematic diagram showing a flattened layer pattern formed on a motherboard structure according to the present disclosure
  • FIG. 5 is a schematic diagram showing the anode pattern formed on the mother board structure according to the present disclosure.
  • FIG. 6 is a schematic diagram of a display mother board structure after forming a pixel definition layer pattern in the present disclosure
  • FIG. 7 is a schematic diagram showing the protective film attached to the motherboard structure of the present disclosure.
  • FIG. 8 is a schematic diagram of the structure of a binding area of the present disclosure.
  • Fig. 9 is a schematic structural diagram of a cutting mark of the present disclosure.
  • FIG. 10 is a schematic structural diagram of another display motherboard of the present disclosure.
  • FIG. 11 is a schematic diagram of another display mother board structure of the present disclosure after forming the driving structure layer and cutting the marking layer pattern;
  • FIG. 12 is a schematic diagram of another display motherboard structure of the present disclosure after a planarization layer pattern is formed
  • FIG. 13 is a schematic structural diagram of another display motherboard of the present disclosure.
  • FIG. 14 is a schematic structural diagram of another display motherboard of the present disclosure.
  • 19B drain electrode
  • 20 fin electrode
  • 21 planearization layer
  • 21A the first planarization layer
  • 22 anode
  • 23 pixel definition layer
  • 101 thin film transistor
  • 102 storage capacitor
  • 103 connection electrode
  • 300 display substrate area
  • 301 display area
  • 302 binding area
  • 303 drive circuit
  • 400 cutting area
  • 401 cutting line
  • connection should be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between two components.
  • connection should be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • it may be the drain electrode of the first electrode and the source electrode of the second electrode, or it may be the source electrode of the first electrode and the drain electrode of the second electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged.
  • electrical connection includes the case where constituent elements are connected together by elements having a certain electrical function.
  • An element having a certain electrical function is not particularly limited as long as it can transmit and receive electrical signals between connected constituent elements.
  • elements having a certain electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, it also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore, also includes a state where an angle of 85° or more and 95° or less is included.
  • film and “layer” can be interchanged.
  • the “conductive layer” can be replaced by the “conductive film.”
  • the “insulating film” can sometimes be replaced with an “insulating layer.”
  • a preparation process of the display mother board includes: first preparing a flexible base on a rigid substrate, and preparing a corresponding film structure on the flexible base to form the display mother board.
  • the display mother board is peeled from the rigid substrate by a lift off process, and then a back film is attached to the back of the flexible base (the surface away from the film structure) to protect the flexibility Base.
  • a back film is attached to the back of the flexible base (the surface away from the film structure) to protect the flexibility Base.
  • the back film is attached with a roller, the softer flexible substrate is deformed under the pressure of the roller, and air bubbles are generated in the position where the deformation is larger due to the squeezing effect.
  • the present disclosure provides a display motherboard.
  • the display motherboard On a plane parallel to the display motherboard, the display motherboard includes a plurality of display substrate areas and a cutting area located at the periphery of each display substrate area;
  • the display motherboard On the plane of the board, the display motherboard includes:
  • the driving structure layer includes a first source/drain metal layer
  • the marking structure layer includes a cutting marking layer
  • the cutting marking layer is provided in the same layer as the first source/drain metal layer.
  • the driving structure layer further includes: a first insulating layer disposed on a substrate, an active layer disposed on the first insulating layer, and a second insulating layer covering the active layer. Layer, a first gate metal layer arranged on the second insulating layer, a third insulating layer covering the first gate metal layer, a second gate metal layer arranged on the third insulating layer, covering all The fourth insulating layer of the second gate metal layer, the first source and drain metal layer is disposed on the fourth insulating layer; the identification structure layer further includes; a first insulating layer and a second insulating layer stacked on a substrate The second insulating layer, the third insulating layer and the fourth insulating layer, and the cutting marking layer is arranged on the fourth insulating layer.
  • the display motherboard further includes a fifth insulating layer; in the display substrate area, the fifth insulating layer is disposed on the driving structure layer, and in the cutting area, the The fifth insulating layer is disposed on the identification structure layer, and the planarization layer is disposed on the fifth insulating layer.
  • the planarization layer includes a second planarization layer provided on the fifth insulating layer and a pixel definition layer provided on the second planarization layer; on the display substrate In the region, an anode is also arranged between the second planarization layer and the pixel definition layer.
  • the driving structure layer includes a second source/drain metal layer
  • the marking structure layer includes a cutting marking layer
  • the cutting marking layer is provided in the same layer as the second source/drain metal layer.
  • the driving structure layer further includes: a first insulating layer disposed on a substrate, an active layer disposed on the first insulating layer, and a second insulating layer covering the active layer. Layer, a first gate metal layer arranged on the second insulating layer, a third insulating layer covering the first gate metal layer, a second gate metal layer arranged on the third insulating layer, covering all The fourth insulating layer of the second gate metal layer, the first source-drain metal layer disposed on the fourth insulating layer, covering the fifth insulating layer and the first planarization layer of the first source-drain metal layer, The second source and drain metal layer is disposed on the first planarization layer; the identification structure layer further includes: a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer stacked on a substrate. An insulating layer, a fifth insulating layer, and a first planarization layer, and the cutting mark layer is disposed on the
  • the planarization layer includes a second planarization layer covering the driving structure layer and the identification structure layer, and a pixel definition layer provided on the second planarization layer; In the substrate area, an anode is further arranged between the second planarization layer and the pixel definition layer.
  • the display motherboard further includes a protective film; in the display substrate area, an encapsulation layer is provided on the planarization layer, and the protective film is provided on the encapsulation layer; In the cutting area, the protective film is disposed on the planarization layer.
  • the cutting mark layer of the cutting area includes a plurality of cutting marks, and the cutting marks include four rectangular patterns arranged in a square shape.
  • the present disclosure provides a display mother board.
  • the overall rigidity of the film layer in the cutting area is effectively improved, the deformation caused by the roller pressure is reduced, and air bubbles in the cutting area are avoided, thereby avoiding There is a situation where the cutting mark cannot be recognized due to the bubble concealing the cutting mark.
  • FIG. 2 is a schematic structural diagram of a display motherboard of the present disclosure, and illustrates the cross-sectional structure of a single source and drain metal layer (single SD or 1SD) structure showing the substrate area and the cutting area.
  • the display motherboard includes a display substrate area 300 and a cutting area 400, and the cutting area 400 is an area other than the display substrate area 300 on the display motherboard. As shown in FIG.
  • the display substrate area 300 in the plane direction perpendicular to the display mother board, includes a driving structure layer disposed on the base 10 and a light emitting structure layer disposed on the driving structure layer, and the cutting area 400 includes The composite insulating layer on the composite insulating layer, the cutting marking layer provided on the composite insulating layer, and the insulating layer covering the cutting marking layer.
  • the driving structure layer of the display substrate area 300 includes a plurality of thin film transistors and storage capacitors forming a pixel driving circuit. In FIG. 2, only one driving thin film transistor 101 and a storage capacitor 102 are taken as an example for illustration.
  • the driving structure layer includes a first insulating layer 11 disposed on the substrate 10, a driving thin film transistor 101 and a storage capacitor 102 disposed on the first insulating layer 11, and a fifth insulating layer 20 and a fifth insulating layer covering the driving thin film transistor 101 and the storage capacitor 102.
  • the light-emitting structure layer includes an anode 22, a pixel definition layer 23, an organic light-emitting layer 24, a cathode 25, and an encapsulation layer 26.
  • the composite insulating layer of the cutting area 400 includes a first insulating layer 11, a second insulating layer 13, a third insulating layer 16 and a fourth insulating layer 18 sequentially stacked on the substrate 10.
  • the cutting marking layer includes being arranged on the composite insulating layer
  • the insulating layer of the cutting area 400 includes a fifth insulating layer 20 covering the cutting marking layer, a second planarization layer 21, and a pixel definition layer 23 covering the second planarization layer 21.
  • the second planarization layer 21 and the pixel definition layer 23 of the cutting area 400 are completely retained, and the surface away from the substrate 10 is flat, which effectively improves the overall rigidity of the film in the cutting area.
  • the "patterning process” referred to in the present disclosure includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping treatments.
  • the deposition can be any one or more of sputtering, evaporation and chemical vapor deposition
  • the coating can be any one or more of spraying and spin coating
  • the etching can be any of dry etching and wet etching.
  • “Thin film” refers to a layer of film made by depositing or coating a certain material on a substrate.
  • the "film” does not require a patterning process during the entire production process, the “film” can also be referred to as a "layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are formed at the same time through the same patterning process.
  • the flexible substrate 10 includes a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on the glass carrier 1.
  • the material of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film materials.
  • the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), which is used to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers.
  • the material of the semiconductor layer can be Use amorphous silicon (a-si).
  • the preparation process may include: first coating a layer of polyimide on a glass carrier, and curing to form a film Then a first flexible (PI1) layer is formed; then a barrier film is deposited on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then an amorphous layer is deposited on the first barrier layer Silicon film to form an amorphous silicon (a-si) layer covering the first barrier layer; then another layer of polyimide is coated on the amorphous silicon layer and cured into a film to form a second flexible (PI2) layer; Then, a barrier film is deposited on the second flexible layer to form a second barrier (Barrier 2) layer covering the second flexible layer to complete the preparation of the flexible substrate.
  • the driving structure layer is provided in the display substrate area 300
  • the cutting marking layer is provided in the cutting area 400
  • the driving structure layer includes a driving thin film transistor 101 and a storage capacitor 102 constituting a pixel driving circuit.
  • the preparation process of the driving structure layer and the cutting mark layer may include:
  • a first insulating film and an active layer film are sequentially deposited on the substrate 10, and the active layer film is patterned through a patterning process to form a first insulating layer 11 covering the entire substrate 10 and an active layer provided on the first insulating layer 11.
  • the layer 12 is patterned, and the active layer 12 is formed in the display substrate area 300.
  • the cutting area 400 includes the first insulating layer 11 disposed on the substrate 10.
  • a second insulating film and a first metal film are sequentially deposited, and the first metal film is patterned through a patterning process to form a second insulating layer 13 covering the entire substrate 10 and a first gate metal disposed on the second insulating layer 13
  • the layer pattern, the first gate metal layer pattern is formed in the display substrate area 300, and includes at least the gate electrode 14, the first capacitor electrode 15, the first gate line (not shown) and the second gate line (not shown).
  • the cutting area 400 includes the first insulating layer 11 and the second insulating layer 13 stacked on the substrate 10.
  • a third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned through a patterning process to form a third insulating layer 16 covering the entire substrate 10 and a second gate metal disposed on the third insulating layer 16
  • the second gate metal layer pattern is formed on the display substrate area 300 and includes at least the second capacitor electrode 17.
  • the position of the second capacitor electrode 17 corresponds to the position of the first capacitor electrode 15.
  • the cutting area 400 includes the first insulating layer 11, the second insulating layer 13, and the third insulating layer 16 stacked on the substrate 10.
  • a fourth insulating film is deposited, and the fourth insulating film is patterned through a patterning process to form a pattern of the fourth insulating layer 18 covering the entire substrate 10.
  • the fourth insulating layer 18 is provided with two first vias and two second vias.
  • a via hole is formed in the display substrate area 300, and its position corresponds to the positions of the two ends of the active layer 12.
  • the fourth insulating layer 18, the third insulating layer 16 and the second insulating layer 13 in the first via hole are etched away , The surface of the active layer 12 is exposed.
  • the cutting area 400 includes the first insulating layer 11, the second insulating layer 13, the third insulating layer 16, and the fourth insulating layer 18 stacked on the substrate 10.
  • the display substrate area 300 includes at least a source electrode 19A, a drain electrode 19B, a data line (not shown), and a power line (not shown).
  • the source electrode 19A and the drain electrode 19B are respectively connected to the active layer 12 through a first via hole ;
  • the cutting marking layer is formed in the cutting area 400 and includes at least two marking blocks 40 spaced apart.
  • the cutting area 400 includes a composite insulating layer disposed on the substrate 10 and a cutting mark layer disposed on the composite insulating layer.
  • the composite insulating layer includes a first insulating layer 11, a second insulating layer 13, and The third insulating layer 16 and the fourth insulating layer 18, and the cutting marking layer includes marking blocks 40.
  • the cutting area 400 includes a composite insulating layer disposed on the substrate 10, a cutting marking layer disposed on the composite insulating layer, and a fifth insulating layer 20 covering the cutting marking layer.
  • the composite insulating layer includes a laminated first layer.
  • the fifth insulating layer 20 may not be formed.
  • the driving structure layer and the cutting identification layer pattern are prepared on the substrate 10, as shown in FIG. 3.
  • the active layer 12, the gate electrode 14, the source electrode 19A and the drain electrode 19B constitute the thin film transistor 101
  • the first capacitor electrode 15 and the second capacitor electrode 17 constitute the storage capacitor 102
  • the first source and drain metal layer and the cutting mark layer are arranged in the same layer , And formed by the same patterning process.
  • the first insulating film, the second insulating film, the third insulating film, the fourth insulating film, and the fifth insulating film may be silicon oxide (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiON), and may be single Layer structure, or may be a multilayer composite structure.
  • the first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second and third insulating layers are called gate insulating (GI) layers
  • the fourth insulating layer is called a layer
  • the fifth insulation layer is called the passivation (PVX) layer.
  • the first metal film, the second metal film, and the third metal film can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo), or can be made of metal alloy materials,
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo)
  • metal alloy materials For example, aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), the alloy material can be a single-layer structure or a multilayer composite structure, such as a composite structure composed of a Mo layer, a Cu layer, and a Mo layer.
  • the active layer film can use amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si) , Hexathiophene or polythiophene materials, that is, the present disclosure is suitable for thin film transistors manufactured based on oxide technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polysilicon
  • Hexathiophene or polythiophene materials that is, the present disclosure is suitable for thin film transistors manufactured based on oxide technology, silicon technology or organic technology.
  • the second planarization layer 21 of the cutting area 400 corresponding to the position of the cutting identification layer is retained, the second planarization layer 21 of the cutting area 400 has a flat surface, and the thickness of the second planarization layer 21 of the cutting area 400 The thickness of the second planarization layer 21 of the display substrate region 300 is the same.
  • the cutting area 400 includes a composite insulating layer disposed on the substrate 10, a cutting marking layer disposed on the composite insulating layer, a fifth insulating layer 20 covering the cutting marking layer, and a third insulating layer covering the fifth insulating layer 20. Two planarization layer 21.
  • the transparent conductive film can be indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the cutting area 400 includes a composite insulating layer disposed on the substrate 10, a cutting marking layer disposed on the composite insulating layer, a fifth insulating layer 20 covering the cutting marking layer, and a third insulating layer covering the fifth insulating layer 20.
  • Two planarization layer 21 Two planarization layer 21.
  • the pixel definition layer 23 is provided with pixel openings, and the pixel openings are formed in the display In the substrate area 300, the pixel defining film in the pixel opening is developed, exposing the surface of the anode 22, as shown in FIG. 6.
  • the pixel definition layer can use polyimide, acrylic or polyethylene terephthalate. In this process, the pixel definition film at the pixel opening position is developed, and the pixel definition film corresponding to the cutting mark layer position in the cutting area 400 is retained.
  • the pixel definition layer 23 of the cutting area 400 has a flat surface, and the pixels in the cutting area 400
  • the thickness of the definition layer 23 is the same as the thickness of the pixel definition layer 23 of the display substrate area 300.
  • the cutting area 400 includes a composite insulating layer disposed on the substrate 10, a cutting marking layer disposed on the composite insulating layer, a fifth insulating layer 20 covering the cutting marking layer, and a second insulating layer covering the fifth insulating layer 20.
  • the second planarization layer 21 and the pixel definition layer 23 covering the second planarization layer 21.
  • the second planarization layer 21 and the pixel definition layer 23 of the cutting area 400 constitute a planarization layer covering the identification structure layer.
  • the organic light-emitting layer 24, the cathode 25 and the encapsulation layer 26 are sequentially formed in the display substrate area 300, and then the display mother board is peeled off from the glass carrier 1 through a peeling process, and the roller bonding method is used to A layer of back film 2 is attached to the back of the display motherboard (the surface of the substrate 10 away from the film layer) to complete the preparation of the display motherboard, as shown in FIG. 2. Finally, the cutting device cuts the display mother board according to the cutting mark to form a plurality of display substrates.
  • the organic light emitting layer may include a stacked hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer.
  • the cathode may be magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu). )
  • the encapsulation layer can adopt, for example, a laminated structure including an inorganic material layer, an organic material layer, and an inorganic material layer ,
  • the encapsulation layer only covers the area of the display substrate.
  • the display substrate area may further include a touch layer or a touch panel disposed on the encapsulation layer and a protective layer (OC) covering the touch layer or the touch panel.
  • the display substrate area may further include a protective film (Temporary Protective Film, TPF for short) 27.
  • a protective film 27 is attached to the display motherboard through an attachment process.
  • the protective film 27 is attached to the encapsulation layer, and in the cutting area 400, the protective film 27 is attached to the pixel defining layer 23, and the protective film 27 is in direct contact with the pixel defining layer 23, as shown in FIG. . Placing a protective film on the display mother board can protect the film structure of the display substrate.
  • the display mother board is peeled from the glass carrier 1 through a peeling process, and a layer of backing film 2 is attached to the back of the display mother board using a roller bonding method to complete the preparation of the display mother board.
  • the cutting device cuts the display mother board according to the cutting mark to form a plurality of display substrates.
  • the protective film is first removed, and then a touch layer and a cover plate are sequentially arranged on the packaging layer to form a touch display panel; or a cover plate is directly arranged on the packaging layer to form a display panel.
  • the display substrate area includes a display area and a binding area.
  • the display area includes a plurality of pixels arranged in a matrix and is configured to realize image display. Pixels.
  • FIG. 8 is a schematic diagram of the structure of a binding area of the present disclosure.
  • the binding area is an area protruding from the display area. After the display motherboard is divided into multiple display substrate areas, the binding area will be bent to the back of the display area. In an exemplary embodiment, the binding area is set on one side of the display area.
  • the binding area includes a first sector (fanout A), a binding Area (bending), second sector (fanout B), panel test (cell test) area, integrated circuit (IC) area, external pin bonding (OLB) area and flexible circuit board (FPC) area.
  • the binding area length (the length from the first sector to the flexible circuit board area) L is 9 mm to 10 mm, such as 9.601 mm.
  • Fig. 9 is a schematic structural diagram of a cutting mark of the present disclosure.
  • the cutting mark includes 4 rectangular patterns, and the 4 rectangular patterns are arranged in a Tian shape, that is, arranged in a 2*2 matrix.
  • the four rectangular patterns arranged in the Tian shape can minimize the influence of bubble contour or impurity contour on the shape of the cutting mark, improve the accuracy of the cutting device's judgment on the shape of the cutting mark, and avoid the situation that the cutting device cannot recognize the cutting mark.
  • the display motherboard may include:
  • the first insulating layer 11 disposed on the substrate 10;
  • the active layer 12 is disposed on the first insulating layer 11, and the active layer 12 is disposed on the display substrate area 300;
  • the second gate metal layer provided on the third insulating layer 16 is provided on the display substrate area 300, and includes at least the second capacitor electrode 17;
  • the fourth insulating layer 18 covering the second gate metal layer is provided with two first via holes exposing the active layer 12, and the two first via holes are provided in the display substrate area 300;
  • the first source-drain metal layer and the cutting mark layer are provided on the fourth insulating layer 18.
  • the first source-drain metal layer is provided in the display substrate area 300 and includes at least a source electrode 19A and a drain electrode 19B, a source electrode 19A and a drain electrode 19B Are respectively connected to the active layer 12 through the first via;
  • the cutting identification layer is arranged in the cutting area 400 and includes at least two identification blocks 40 arranged at intervals; the first source and drain metal layer and the cutting identification layer are arranged in the same layer, and pass through the same Sub-patterning process formation;
  • the fifth insulating layer 20 and the second planarization layer 21 covering the first source-drain metal layer are provided with a second via hole exposing the drain electrode 19B, and the second via hole is provided in the display substrate area 300; the cutting area 400 The surface of the second planarization layer 21 away from the substrate 10 is flat;
  • the anode 22 provided on the second planarization layer 21, the anode 22 is provided in the display substrate area 300, and is connected to the drain electrode 19B through the second via hole;
  • the pixel definition layer 23 covering the anode 22 is provided with pixel openings exposing the anode 22, and the pixel openings are formed in the display substrate area 300; the surface of the pixel definition layer 23 in the cut area away from the substrate 10 is flat;
  • the organic light-emitting layer 24 is arranged in the 300-pixel opening of the display substrate area, and the organic light-emitting layer 24 is connected to the anode 22;
  • a cathode 25 on the organic light-emitting layer 24 is provided, and the cathode 25 is connected to the organic light-emitting layer 24;
  • the encapsulation layer 26 disposed on the display substrate area 300;
  • the protective film 27 covering the foregoing structure is disposed on the encapsulation layer in the display substrate area 300, and in the cutting area 400, the protective film 27 is disposed on the pixel defining layer 23, and the protective film 27 is in direct contact with the pixel defining layer 23.
  • the display motherboard provided by the present disclosure retains a complete planarization layer and a pixel definition layer in the cutting area, and the cutting identification layer and the display substrate in the cutting area
  • the first source and drain metal layer of the area is the same layer, which effectively improves the overall rigidity of the film layer in the cutting area, reduces the deformation caused by the pressure of the roller, and avoids the generation of bubbles in the cutting area, thereby avoiding the cutting caused by the bubble blocking the cutting mark Identify unrecognized situations.
  • both the planarization layer and the pixel definition layer in the cutting area are provided with grooves exposing the fifth insulating layer. Due to the large height difference in the position of the groove, the deformation space of the cutting marking layer is relatively large. Therefore, when the roller presses the base in the laminating process, the cutting marking layer will produce greater deformation, and then form more bubble.
  • the height difference of the area is filled, which not only increases the overall rigidity of the film layer in the cutting area, but also eliminates the deformation space of the cutting mark layer.
  • the thicker planarization layer and the pixel definition layer above the cutting mark layer can support the cut mark layer to resist the deformation of the substrate, effectively reduce the deformation of the cut mark layer, and avoid the generation of bubbles Therefore, the interference and influence of the air bubbles on the recognition of the cutting mark is reduced, and the situation that the cutting mark of the cutting area cannot be recognized is avoided.
  • the cutting marking layer is arranged in the same layer as the first gate metal layer in the display substrate area, that is, the cutting marking layer is arranged between the second insulating layer and the third insulating layer. Since only the first insulating layer and the second insulating layer are spaced between the cutting marking layer and the substrate, the thickness and rigidity of the two insulating layers are small. When the softer flexible substrate undergoes greater deformation, the cutting marking layer will also be relatively thin. Large deformation, and more bubbles are formed.
  • the cutting marking layer is set to be the same layer as the first source/drain metal layer in the display substrate area, that is, the cutting marking layer is set on the first source/drain metal layer.
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer are spaced between the cutting mark layer and the substrate, a total of four insulating layers are added, and the film layer between the cutting mark layer and the base is added.
  • the thickness and stiffness In this way, even if the flexible substrate undergoes large deformation, the four insulating layers with large thickness and rigidity can resist partial deformation of the substrate, which reduces the deformation of the cutting marking layer to a certain extent and reduces the number of bubbles.
  • the preparation process of the present disclosure can be realized by using mature preparation equipment, with little process improvement, high compatibility, simple process realization, easy implementation, high production efficiency, low production cost, and high yield.
  • the solution of the present disclosure avoids the situation that the cutting mark of the cutting area cannot be recognized, ensures the accuracy and reliability of the cutting process, and has a good application prospect.
  • FIG. 10 is a schematic structural diagram of another display motherboard of the present disclosure, illustrating the cross-sectional structure of the dual source-drain metal layer (dual SD or 2SD) structure of the display substrate area and the cutting area.
  • the display mother board includes a display substrate area 300 and a cutting area 400.
  • the display substrate area 300 includes a driving structure layer disposed on the base 10 and a light emitting structure layer disposed on the driving structure layer.
  • the cutting area 400 includes A composite insulating layer on the substrate 10, a cutting marking layer provided on the composite insulating layer, and an insulating layer covering the cutting marking layer.
  • the driving structure layer of the display substrate area 300 includes a plurality of thin film transistors and storage capacitors forming a pixel driving circuit. In FIG.
  • the driving structure layer includes a first insulating layer 11 disposed on the substrate 10, a thin film transistor 101 and a storage capacitor 102 disposed on the first insulating layer 11, a fifth insulating layer 20 and a first insulating layer 20 covering the thin film transistor 101 and the storage capacitor 102.
  • the planarization layer 21A, the second metal conductive layer provided on the first planarization layer 21A, and the second planarization layer 21 covering the second metal conductive layer, the second metal conductive layer including the drain electrode of the thin film transistor 101 Connect the electrode 103.
  • the light-emitting structure layer includes an anode 22, a pixel definition layer 23, an organic light-emitting layer 24, a cathode 25, and an encapsulation layer 26.
  • the composite insulating layer of the cutting area 400 includes a first insulating layer 11, a second insulating layer 13, a third insulating layer 16, a fourth insulating layer 18, a fifth insulating layer 20, and a first planarization layer which are sequentially stacked on the substrate 10.
  • Layer 21A, the cutting marking layer includes marking blocks 40 arranged on the composite insulating layer, and the insulating layer includes a second planarization layer 21 covering the cutting marking layer and a pixel definition layer 23 covering the second planarization layer 21.
  • the second planarization layer 21 and the pixel definition layer 23 of the cutting area 400 constitute a planarization layer covering the identification structure layer. As shown in FIG. 10, the second planarization layer 21 and the pixel definition layer 23 of the cutting area 400 are completely retained, and the surface away from the substrate 10 is flat, which effectively improves the overall rigidity of the film in the cutting area.
  • the preparation process of the present disclosure may include:
  • the substrate 10 is formed on the glass carrier 1, and the preparation process is the same as the aforementioned process (1).
  • the insulating layer 16, the second gate metal layer, the fourth insulating layer 18, and the first source/drain metal layer are processed in a similar manner to the foregoing process, except that the third metal film is patterned only on the display substrate.
  • the area 300 forms a first source-drain metal layer pattern, and the cutting area 400 does not form a cutting mark layer.
  • a fifth insulating layer 20 and a first planarization layer 21A covering the first source and drain metal layer are formed, and a third via hole is opened on the fifth insulating layer 20 and the first planarization layer 21A, and the third via hole is formed in
  • the display substrate area 300 exposes the surface of the drain electrode 19B.
  • a fourth metal film is deposited, and the fourth metal film is patterned through a patterning process to form a second metal conductive layer and a cutting mark layer on the first planarization layer 21A.
  • the second metal conductive layer is formed in the display substrate area 300, the cutting marking layer is formed in the cutting area 400, and the cutting marking layer includes at least two marking blocks 40 spaced apart.
  • the first source-drain metal layer includes at least a source electrode 19A, a drain electrode 19B, and a data line
  • the second metal conductive layer includes a connection electrode 103 connected to the drain electrode 19B through a third via hole.
  • the cutting area 400 includes a composite insulating layer disposed on the substrate 10 and a cutting mark layer disposed on the composite insulating layer.
  • the composite insulating layer includes a first insulating layer 11, a second insulating layer 13, and The third insulating layer 16, the fourth insulating layer 18, the fifth insulating layer 20 and the first planarization layer 21A, and the cutting marking layer includes the marking block 40.
  • the second metal conductive layer may further include any one or more of a power line (VDD), a low voltage line (VSS), a compensation line, and an auxiliary cathode.
  • the driving structure layer and the cutting mark layer pattern are prepared on the substrate 10, as shown in FIG. 11.
  • the active layer 12, the gate electrode 14, the source electrode 19A and the drain electrode 19B constitute the thin film transistor 101
  • the first capacitor electrode 15 and the second capacitor electrode 17 constitute the storage capacitor 102
  • the first source-drain metal layer includes at least the source electrode 19A and the drain electrode.
  • the second metal conductive layer includes at least the connecting electrode 103
  • the second metal conductive layer and the cutting mark layer are arranged in the same layer, and are formed by the same patterning process.
  • the second flattening layer 21 is provided with a fourth via hole.
  • the fourth via hole is formed in the display substrate area 300, and the flat film in the fourth via hole is developed to expose the surface of the connection electrode 103, as shown in FIG. 12.
  • the cutting area 400 includes a composite insulating layer disposed on the substrate 10, a cutting marking layer disposed on the composite insulating layer, and a second planarization layer 21 covering the cutting marking layer.
  • the anode 22, the pixel defining layer 23, the organic light-emitting layer 24, the cathode 25 and the encapsulation layer 26 are sequentially formed on the substrate forming the aforementioned pattern.
  • the preparation process is the same as the aforementioned processes (4) to (6), and subsequent attachment
  • the protective film, peeling from the glass carrier, attaching the back film, and cutting process are the same as the foregoing processes, and will not be repeated here.
  • the display motherboard may include:
  • the first insulating layer 11 disposed on the substrate 10;
  • the active layer 12 is disposed on the first insulating layer 11, and the active layer 12 is disposed on the display substrate area 300;
  • the fourth insulating layer 18 covering the second gate metal layer is provided with two first via holes exposing the active layer 12, and the two first via holes are provided in the display substrate area 300;
  • the first source-drain metal layer is provided on the fourth insulating layer 18.
  • the first source-drain metal layer is provided in the display substrate area 300 and includes at least a source electrode 19A and a drain electrode 19B.
  • the source electrode 19A and the drain electrode 19B pass through the first The via is connected to the active layer 12;
  • the fifth insulating layer 20 and the first planarization layer 21A covering the first source/drain metal layer are provided with a third via hole exposing the drain electrode 19B, and the third via hole is provided in the display substrate area 300;
  • the second metal conductive layer and the cutting mark layer are arranged on the first planarization layer 21A; the second metal conductive layer is arranged on the display substrate area 300 and includes at least the connecting electrode 103, which passes through the third via hole and the drain electrode 19B Connection;
  • the cutting identification layer is provided in the cutting area 400, and includes at least two identification blocks 40 spaced apart; the second metal conductive layer and the cutting identification layer are set in the same layer, and are formed by the same patterning process;
  • the second planarization layer 21 covering the second metal conductive layer is provided with a fourth via hole exposing the connection electrode 103, the fourth via hole is provided in the display substrate area 300; the second planarization layer 21 in the cutting area 400 The surface away from the base 10 is flat;
  • the anode 22 provided on the second planarization layer 21, the anode 22 is formed in the display substrate area 300, and is connected to the connection electrode 103 through the fourth via hole;
  • the pixel definition layer 23 covering the anode 22 is provided with pixel openings exposing the anode 22, and the pixel openings are formed in the display substrate area 300; the surface of the pixel definition layer 23 of the cutting area 400 away from the substrate 10 is flush;
  • the organic light-emitting layer 24 is arranged in the 300-pixel opening of the display substrate area, and the organic light-emitting layer 24 is connected to the anode 22;
  • the encapsulation layer 26 is provided in the display substrate area 300.
  • the cutting marking layer is set to be the same layer as the second metal conductive layer of the display substrate area, that is, the cutting marking layer is arranged on the first planarization layer, the cutting marking layer and the base are separated by a first insulating layer and a second insulating layer.
  • the deformation reduces the number of bubbles and avoids the unrecognizable cutting mark in the cutting area to the greatest extent.
  • FIG. 13 is a schematic structural diagram of another display motherboard of the present disclosure, which is an extension of the structure shown in FIG. 2 described above.
  • the difference from the aforementioned display motherboard shown in FIG. 2 is that after the drive structure layer and the cutting mark layer are formed in the display substrate area 300 and the cutting area 400, respectively, the second planarization layer 21 is directly formed on the drive structure layer and the cut mark layer. , Which means that the motherboard is not provided with the fifth insulating layer.
  • FIG. 14 is a schematic structural diagram of another display motherboard of the present disclosure, which is an extension of the structure shown in FIG. 10. The difference from the display motherboard shown in FIG. 10 is that after the first source/drain metal layer is formed, the first planarization layer 21A covering the first source/drain metal layer is directly formed, that is, the display motherboard is not provided with a fifth insulating layer .
  • the OLED may be a top emission structure, or may be a bottom emission structure.
  • the driving thin film transistor may be a top gate structure, or may be a bottom gate structure, may be a single gate structure, or may be a double gate structure.
  • other electrodes or leads may be provided in the driving structure layer and the light-emitting structure layer, which are not specifically limited in the present disclosure.
  • the present disclosure also provides a method for preparing the display motherboard.
  • the display mother board includes a plurality of display substrate areas and a cutting area located at the periphery of each display substrate area, and the preparation method includes:
  • a driving structure layer and a marking structure layer are formed in a plurality of display substrate areas and cutting areas, respectively; the marking structure layer includes a cutting marking layer;
  • a planarization layer is formed on the driving structure layer and the identification structure layer, and the planarization layer covers the identification structure layer.
  • the driving structure layer includes a first source-drain metal layer
  • the marking structure layer includes a cutting marking layer
  • step S1 includes:
  • first insulating layer Forming a first insulating layer on a substrate, forming an active layer on the first insulating layer, forming a second insulating layer covering the active layer, and forming a first gate metal layer on the second insulating layer, A third insulating layer covering the first gate metal layer is formed, a second gate metal layer is formed on the third insulating layer, and a fourth insulating layer covering the second gate metal layer is formed.
  • the first source-drain metal layer and the cutting mark layer are formed on the insulating layer through the same patterning process; the active layer, the first gate metal layer, the second gate metal layer and the first source-drain metal layer are arranged on the The substrate area is displayed, and the cutting marking layer is arranged in the cutting area.
  • step S2 includes:
  • a second planarization layer and a pixel definition layer are sequentially formed on the fifth insulating layer, and an anode is also formed between the second planarization layer and the pixel definition layer in the display substrate area.
  • the driving structure layer includes a second source/drain metal layer
  • the marking structure layer includes a cutting marking layer
  • step S1 includes:
  • first insulating layer Forming a first insulating layer on a substrate, forming an active layer on the first insulating layer, forming a second insulating layer covering the active layer, and forming a first gate metal layer on the second insulating layer, A third insulating layer covering the first gate metal layer is formed, a second gate metal layer is formed on the third insulating layer, and a fourth insulating layer covering the second gate metal layer is formed.
  • a first source-drain metal layer is formed on the insulating layer, a fifth insulating layer covering the first source-drain metal layer is formed, a first planarization layer is formed on the fifth insulating layer, and a first planarization layer is formed on the first planarization layer.
  • the second source-drain metal layer and the cutting identification layer are formed by the same patterning process; the active layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer and the second source-drain metal
  • the layer is arranged in the display substrate area, and the cutting mark layer is arranged in the cutting area.
  • step S2 includes:
  • a second planarization layer and a pixel definition layer are sequentially formed on the first planarization layer, and an anode is also formed between the second planarization layer and the pixel definition layer in the display substrate area.
  • the manufacturing method further includes:
  • the display mother board is cut to form a plurality of display substrates.
  • the preparation method after cutting the display mother board, the preparation method further includes:
  • a cover plate is formed on the encapsulation layer; or a touch layer and a cover plate are sequentially formed on the encapsulation layer.
  • the present disclosure provides a method for preparing a display motherboard.
  • a complete planarization layer and a pixel definition layer in a cutting area and the cutting identification layer in the cutting area is the same layer as the first source/drain metal layer in the display substrate area, it is effective Improve the overall rigidity of the film in the cutting area, reduce the deformation caused by the pressure of the roller, avoid the formation of bubbles in the cutting area, avoid the situation where the cutting mark cannot be recognized due to the bubble blocking the cutting mark, and ensure the accuracy of the cutting process And reliability.
  • the preparation process of the present disclosure can be realized with mature preparation equipment, with less process improvement, high compatibility, simple process realization, easy implementation, high production efficiency, low production cost, high yield, and good application prospects.
  • the present disclosure also provides a display substrate, which is formed by cutting the aforementioned display mother board along the cutting area.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • the display device can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator, or any other product or component with a display function.

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Abstract

一种显示母板及其制备方法、显示基板和显示装置。所述显示母板包括多个显示基板区域和位于每个所述显示基板区域周边的切割区域；所述显示母板包括：设置在每个显示基板区域的驱动结构层，以及设置在每个切割区域的标识结构层；所述标识结构层包括切割标识层；设置在所述驱动结构层和标识结构层上的平坦化层，所述平坦化层覆盖所述标识结构层。

Description

显示母板及其制备方法、显示基板和显示装置
本申请要求于2020年2月27日提交中国专利局、申请号为202010123204.X、发明名称为“显示母板及其制备方法、显示基板和显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开涉及但不限于显示技术领域，尤指一种显示母板及其制备方法、显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、较低耗电、极高反应速度的优点。随着显示技术的不断发展，OLED技术越来越多的应用于柔性显示装置中。
一种制备柔性OLED显示装置的过程中，先制备显示母板，然后对显示母板进行切割，从而使显示母板被分隔成多个显示基板，分开的显示基板均可以用于形成单个OLED显示装置。图1为显示母板上包括多个显示基板的排布示意图。如图1所示，显示母板100上的多个显示基板区域300呈周期性规则排布，切割区域400位于每个显示基板区域300的周边。显示基板区域300至少包括显示区域301和绑定区域302，显示区域301包括矩阵排列的多个像素，绑定区域302包括驱动电路303，绑定区域302设置在显示区域301的一侧。切割区域400包括环绕显示基板区域300的环形的切割线401和多个切割标识(Mark)402。
在进行切割时，切割设备先识别切割标识，然后按照切割标识进行切割，但在生产中存在切割标识无法识别的问题。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种显示母板，所述显示母板包括多个显示基板区域和位于每个所述显示基板区域周边的切割区域；所述显示母板还包括：
设置在每个显示基板区域的驱动结构层，以及设置在每个切割区域的标识结构层；所述标识结构层包括切割标识层；
设置在所述驱动结构层和标识结构层上的平坦化层，所述平坦化层覆盖所述标识结构层。
在一些可能的实现方式中，所述驱动结构层包括第一源漏金属层，所述标识结构层包括切割标识层，所述切割标识层与所述第一源漏金属层同层设置。
在一些可能的实现方式中，所述驱动结构层还包括：设置在基底上的第一绝缘层，设置在所述第一绝缘层上的有源层，覆盖所述有源层的第二绝缘层，设置在所述第二绝缘层上的第一栅金属层，覆盖所述第一栅金属层的第三绝缘层，设置在所述第三绝缘层上的第二栅金属层，覆盖所述第二栅金属层的第四绝缘层，所述第一源漏金属层设置在所述第四绝缘层上；所述标识结构层还包括；在基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层，所述切割标识层设置在所述第四绝缘层上。
在一些可能的实现方式中，所述显示母板还包括第五绝缘层；在所述显示基板区域，所述第五绝缘层设置在所述驱动结构层上，在所述切割区域，所述第五绝缘层设置在所述标识结构层上，所述平坦化层设置在所述第五绝缘层上。
在一些可能的实现方式中，所述平坦化层包括设置在所述第五绝缘层上的第二平坦化层和设置在所述第二平坦化层上的像素定义层；在所述显示基板区域，所述第二平坦化层与像素定义层之间还设置有阳极。
在一些可能的实现方式中，所述驱动结构层包括第二源漏金属层，所述标识结构层包括切割标识层，所述切割标识层与所述第二源漏金属层同层设置。
在一些可能的实现方式中，所述驱动结构层还包括：设置在基底上的第一绝缘层，设置在所述第一绝缘层上的有源层，覆盖所述有源层的第二绝缘层，设置在所述第二绝缘层上的第一栅金属层，覆盖所述第一栅金属层的第三绝缘层，设置在所述第三绝缘层上的第二栅金属层，覆盖所述第二栅金属层的第四绝缘层，设置在所述第四绝缘层上的第一源漏金属层，覆盖所述第一源漏金属层的第五绝缘层和第一平坦化层，所述第二源漏金属层设置在所述第一平坦化层上；所述标识结构层还包括：在基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层和第一平坦化层，所述切割标识层设置在所述第一平坦化层上。
在一些可能的实现方式中，所述平坦化层包括覆盖所述驱动结构层和标识结构层的第二平坦化层和设置在所述第二平坦化层上的像素定义层；在所述显示基板区域，所述第二平坦化层与像素定义层之间还设置有阳极。
在一些可能的实现方式中，所述显示母板还包括保护膜；在所述显示基板区域，所述平坦化层上设置有封装层，所述保护膜设置在所述封装层上；在所述切割区域，所述保护膜设置在所述平坦化层上。
在一些可能的实现方式中，所述切割区域的切割标识层包括多个切割标识，所述切割标识包括田字形排列的4个矩形图案。
本公开还提供了一种显示基板，由前述显示母板沿着所述切割区域切割而形成。
本公开还提供了一种显示装置，包括前述的显示基板。
本公开还提供了一种显示母板的制备方法，所述显示母板包括多个显示基板区域和位于每个所述显示基板区域周边的切割区域，所述制备方法包括：
在多个显示基板区域和切割区域分别形成驱动结构层和标识结构层；所述标识结构层包括切割标识层；
在所述驱动结构层和标识结构层上形成平坦化层，所述平坦化层覆盖所述标识结构层。
在一些可能的实现方式中，所述驱动结构层包括第一源漏金属层，所述标识结构层包括切割标识层，在多个显示基板区域和切割区域分别形成驱动 结构层和标识结构层，包括：
在基底上形成第一绝缘层，在所述第一绝缘层上形成有源层，形成覆盖所述有源层的第二绝缘层，在所述第二绝缘层上形成第一栅金属层，形成覆盖所述第一栅金属层的第三绝缘层，在所述第三绝缘层上形成第二栅金属层，形成覆盖所述第二栅金属层的第四绝缘层，在所述第四绝缘层上通过同一次构图工艺形成所述第一源漏金属层和切割标识层；所述有源层、第一栅金属层、第二栅金属层和第一源漏金属层设置在所述显示基板区域，所述切割标识层设置在所述切割区域。
在一些可能的实现方式中，在所述驱动结构层和标识结构层上形成平坦化层，包括：
在所述驱动结构层和标识结构层上形成第五绝缘层；
在所述第五绝缘层上依次形成第二平坦化层和像素定义层，在所述显示基板区域，所述第二平坦化层与像素定义层之间还形成有阳极。
在一些可能的实现方式中，所述驱动结构层包括第二源漏金属层，所述标识结构层包括切割标识层，在多个显示基板区域和切割区域分别形成驱动结构层和标识结构层，包括：
在基底上形成第一绝缘层，在所述第一绝缘层上形成有源层，形成覆盖所述有源层的第二绝缘层，在所述第二绝缘层上形成第一栅金属层，形成覆盖所述第一栅金属层的第三绝缘层，在所述第三绝缘层上形成第二栅金属层，形成覆盖所述第二栅金属层的第四绝缘层，在所述第四绝缘层上形成第一源漏金属层，形成覆盖所述第一源漏金属层的第五绝缘层，在所述第五绝缘层上形成第一平坦化层，在所述第一平坦化层上通过同一次构图工艺形成所述第二源漏金属层和切割标识层；所述有源层、第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层设置在所述显示基板区域，所述切割标识层设置在所述切割区域。
在一些可能的实现方式中，在所述驱动结构层和标识结构层上形成平坦化层，包括：
在所述第一平坦化层上依次形成第二平坦化层和像素定义层，在所述显 示基板区域，所述第二平坦化层与像素定义层之间还形成有阳极。
在一些可能的实现方式中，所述制备方法还包括：
依次形成有机发光层、阴极和封装层；
在所述封装层上贴附保护膜，在所述切割区域，所述保护膜与所述像素定义层接触；
采用滚轮贴合方式在所述基底远离所述平坦化层一侧的表面贴附背膜；
对所述显示母板进行切割，形成多个显示基板。
在一些可能的实现方式中，对所述显示母板进行切割之后，所述制备方法还包括：
去除所述保护膜；
在所述封装层上形成盖板；或者在所述封装层上依次形成触控层和盖板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为显示母板上包括多个显示基板的排布示意图；
图2为本公开一种显示母板的结构示意图；
图3为本公开一种显示母板结构形成驱动结构层和切割标识层图案后的示意图；
图4为本公开一种显示母板结构形成平坦化层图案后的示意图；
图5为本公开一种显示母板结构形成阳极图案后的示意图；
图6为本公开一种显示母板结构形成像素定义层图案后的示意图；
图7为本公开一种显示母板结构贴附保护膜后的示意图；
图8为本公开一种绑定区域的结构示意图；
图9为本公开一种切割标识的结构示意图；
图10为本公开另一种显示母板的结构示意图；
图11为本公开另一种显示母板结构形成驱动结构层和切割标识层图案后的示意图；
图12为本公开另一种显示母板结构形成平坦化层图案后的示意图；
图13为本公开又一种显示母板的结构示意图；
图14为本公开又一种显示母板的结构示意图。
附图标记说明:
1—玻璃载板；        2—背膜；            10—基底；
11—第一绝缘层；     12—有源层；         13—第二绝缘层；
14—栅电极；         15—第一电容电极；   16—第三绝缘层；
17—第二电容电极；   18—第四绝缘层；     19A—源电极；
19B—漏电极；        20—第五绝缘层；     21—平坦化层；
21A—第一平坦化层；  22—阳极；           23—像素定义层；
24—有机发光层；     25—阴极；           26—封装层；
27—保护膜；         40—标识块；         100—显示母板；
101—薄膜晶体管；    102—存储电容；      103—连接电极；
300—显示基板区域；  301—显示区域；      302—绑定区域；
303—驱动电路；      400—切割区域；      401—切割线；
402—切割标识。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此， 本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的实施方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的实施方式不局限于附图所示的形状或数值。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，可以是第一极为漏电极、第二极为源电极，或者可以是第一极为源电极、第二极为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
经研究发现，生产中存在切割区域的切割标识无法识别的问题，是由于制备过程中切割区域出现气泡，气泡遮挡切割标识造成的。当不规则形状的多个气泡位于切割标识所在区域时，气泡的轮廓线影响了切割设备对切割标识外形判断的准确度，进而导致出现切割设备不能识别切割标识的情形。经进一步研究发现，切割区域出现的气泡主要是在贴合背膜工艺中产生的。显示母板的一种制备过程包括：先在刚性衬底上制备柔性基底，在柔性基底制备相应膜层结构形成显示母板。所有膜层制备完成后，通过剥离(Lift Off)工艺将显示母板从刚性衬底上剥离，然后在柔性基底背部(远离膜层结构一侧的表面)贴附一层背膜，以保护柔性基底。在用滚轮贴附背膜时，较软的柔性基底在滚轮压力下发生形变，形变较大的位置由于挤压作用而产生气泡。
本公开提供了一种显示母板，在平行于显示母板的平面上，所述显示母板包括多个显示基板区域和位于每个所述显示基板区域周边的切割区域；在垂直于显示母板的平面上，所述显示母板包括：
设置在每个显示基板区域的驱动结构层，以及设置在每个切割区域的标识结构层；所述标识结构层包括切割标识层；
设置在所述驱动结构层和标识结构层上的平坦化层，所述平坦化层覆盖所述标识结构层。
在一示例性实施方式中，所述驱动结构层包括第一源漏金属层，所述标识结构层包括切割标识层，所述切割标识层与所述第一源漏金属层同层设置。
在一示例性实施方式中，所述驱动结构层还包括：设置在基底上的第一绝缘层，设置在所述第一绝缘层上的有源层，覆盖所述有源层的第二绝缘层，设置在所述第二绝缘层上的第一栅金属层，覆盖所述第一栅金属层的第三绝缘层，设置在所述第三绝缘层上的第二栅金属层，覆盖所述第二栅金属层的第四绝缘层，所述第一源漏金属层设置在所述第四绝缘层上；所述标识结构层还包括；在基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层，所述切割标识层设置在所述第四绝缘层上。
在一示例性实施方式中，所述显示母板还包括第五绝缘层；在所述显示基板区域，所述第五绝缘层设置在所述驱动结构层上，在所述切割区域，所述第五绝缘层设置在所述标识结构层上，所述平坦化层设置在所述第五绝缘层上。
在一示例性实施方式中，所述平坦化层包括设置在所述第五绝缘层上的第二平坦化层和设置在所述第二平坦化层上的像素定义层；在所述显示基板区域，所述第二平坦化层与像素定义层之间还设置有阳极。
在一示例性实施方式中，所述驱动结构层包括第二源漏金属层，所述标识结构层包括切割标识层，所述切割标识层与所述第二源漏金属层同层设置。
在一示例性实施方式中，所述驱动结构层还包括：设置在基底上的第一绝缘层，设置在所述第一绝缘层上的有源层，覆盖所述有源层的第二绝缘层，设置在所述第二绝缘层上的第一栅金属层，覆盖所述第一栅金属层的第三绝缘层，设置在所述第三绝缘层上的第二栅金属层，覆盖所述第二栅金属层的第四绝缘层，设置在所述第四绝缘层上的第一源漏金属层，覆盖所述第一源漏金属层的第五绝缘层和第一平坦化层，所述第二源漏金属层设置在所述第一平坦化层上；所述标识结构层还包括：在基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层和第一平坦化层，所述切割标识层设置在所述第一平坦化层上。
在一示例性实施方式中，所述平坦化层包括覆盖所述驱动结构层和标识 结构层的第二平坦化层和设置在所述第二平坦化层上的像素定义层；在所述显示基板区域，所述第二平坦化层与像素定义层之间还设置有阳极。
在一示例性实施方式中，所述显示母板还包括保护膜；在所述显示基板区域，所述平坦化层上设置有封装层，所述保护膜设置在所述封装层上；在所述切割区域，所述保护膜设置在所述平坦化层上。
在一示例性实施方式中，所述切割区域的切割标识层包括多个切割标识，所述切割标识包括田字形排列的4个矩形图案。
本公开提供了一种显示母板，通过在切割区域保留完整的平坦化层，有效提高了切割区域膜层的整体刚度，减小了因滚轮压力产生的形变，避免切割区域产生气泡，从而避免出现因气泡遮挡切割标识导致的切割标识无法识别的情况。
图2为本公开一种显示母板的结构示意图，示意了单源漏金属层(单SD或1SD)结构显示基板区域和切割区域的剖面结构。在平行于显示母板的平面方向，显示母板包括显示基板区域300和切割区域400，切割区域400为显示母板上显示基板区域300以外的其它区域。如图2所示，在垂直于显示母板的平面方向，显示基板区域300包括设置在基底10上的驱动结构层和设置在驱动结构层上的发光结构层，切割区域400包括设置在基底10上的复合绝缘层、设置在复合绝缘层上的切割标识层和覆盖切割标识层的绝缘层。显示基板区域300的驱动结构层包括形成像素驱动电路的多个薄膜晶体管和存储电容，图2中仅以一个驱动薄膜晶体管101和存储电容102为例进行示意。驱动结构层包括设置在基底10上的第一绝缘层11、设置在第一绝缘层11上的驱动薄膜晶体管101和存储电容102以及覆盖驱动薄膜晶体管101和存储电容102的第五绝缘层20和第二平坦化层21。发光结构层包括阳极22、像素定义层23、有机发光层24、阴极25以及封装层26。切割区域400的复合绝缘层包括在基底10上依次叠设的第一绝缘层11、第二绝缘层13、第三绝缘层16和第四绝缘层18，切割标识层包括设置在复合绝缘层上的标识块40，切割区域400的绝缘层包括覆盖切割标识层的第五绝缘层20、第二平坦化层21和覆盖第二平坦化层21的像素定义层23。如图2所示，切割区域400的第二平坦化层21和像素定义层23被完整保留，远离基底10一侧的表面为平 齐状，有效提高了切割区域膜层的整体刚度。
下面通过显示母板的制备过程的示例说明显示母板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程中该“薄膜”需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。
(1)在玻璃载板1上制备柔性基底10。柔性基底10包括在玻璃载板1上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)，用于提高基底的抗水氧能力，第一、第二无机材料层也称之为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在一示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成柔性基底的制备。
(2)在基底10上制备驱动结构层和切割标识层图案。驱动结构层设置在显示基板区域300，切割标识层设置在切割区域400，驱动结构层包括构成像素驱动电路的驱动薄膜晶体管101和存储电容102。在一示例性实施方式中，驱动结构层和切割标识层的制备过程可以包括：
在基底10上依次沉积第一绝缘薄膜和有源层薄膜，通过构图工艺对有源层薄膜进行构图，形成覆盖整个基底10的第一绝缘层11以及设置在第一绝缘层11上的有源层12图案，有源层12形成在显示基板区域300。本次构图工艺后，切割区域400包括设置在基底10上的第一绝缘层11。
随后，依次沉积第二绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成覆盖整个基底10的第二绝缘层13以及设置在第二绝缘层13上的第一栅金属层图案，第一栅金属层图案形成在显示基板区域300，至少包括栅电极14、第一电容电极15、第一栅线(未示出)和第二栅线(未示出)。本次构图工艺后，切割区域400包括在基底10叠设的第一绝缘层11和第二绝缘层13。
随后，依次沉积第三绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成覆盖整个基底10的第三绝缘层16以及设置在第三绝缘层16上的第二栅金属层图案，第二栅金属层图案形成在显示基板区域300，至少包括第二电容电极17，第二电容电极17的位置与第一电容电极15的位置相对应。本次构图工艺后，切割区域400包括在基底10叠设的第一绝缘层11、第二绝缘层13和第三绝缘层16。
随后，沉积第四绝缘薄膜，通过构图工艺对第四绝缘薄膜进行构图，形成覆盖整个基底10的第四绝缘层18图案，第四绝缘层18上开设有两个第一过孔，两个第一过孔形成在显示基板区域300，其位置与有源层12两端的位置相对应，第一过孔内的第四绝缘层18、第三绝缘层16和第二绝缘层13被刻蚀掉，暴露出有源层12的表面。本次构图工艺后，切割区域400包括在基底10叠设的第一绝缘层11、第二绝缘层13、第三绝缘层16和第四绝缘层18。
随后，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在第四绝缘层18上形成第一源漏金属层和切割标识层图案，第一源漏金属层(SD1)形成在显示基板区域300，至少包括源电极19A、漏电极19B、数据线(未示出)和电源线(未示出)，源电极19A和漏电极19B分别通过第一过孔与有源层12连接；切割标识层形成在切割区域400，包括至少二个间隔设置的标识块40。本次构图工艺后，切割区域400包括设置在基底10上的 复合绝缘层和设置在复合绝缘层上的切割标识层，复合绝缘层包括叠设的第一绝缘层11、第二绝缘层13、第三绝缘层16和第四绝缘层18，切割标识层包括标识块40。
随后，沉积第五绝缘薄膜，形成覆盖整个基底10的第五绝缘层20图案。本次构图工艺后，切割区域400包括设置在基底10上的复合绝缘层、设置在复合绝缘层上的切割标识层和覆盖切割标识层的第五绝缘层20，复合绝缘层包括叠设的第一绝缘层11、第二绝缘层13、第三绝缘层16和第四绝缘层18，切割标识层包括标识块40。在一示例性实施方式中，根据实际需要，可以不形成第五绝缘层20。
至此，在基底10上制备完成驱动结构层和切割标识层图案，如图3所示。有源层12、栅电极14、源电极19A和漏电极19B组成薄膜晶体管101，第一电容电极15与第二电容电极17组成存储电容102，第一源漏金属层和切割标识层同层设置，且通过同一次构图工艺形成。
第一绝缘薄膜、第二绝缘薄膜、第三绝缘薄膜、第四绝缘薄膜和第五绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)或氮氧化硅(SiON)，可以是单层结构，或者可以是多层复合结构。第一绝缘层称之为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称之为栅绝缘(GI)层，第四绝缘层称之为层间绝缘(ILD)层，第五绝缘层称之为钝化(PVX)层。第一金属薄膜、第二金属薄膜和第三金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)或钼(Mo)，或者可以采用由金属组成的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，合金材料可以是单层结构，或者可以是多层复合结构，如Mo层、Cu层和Mo层组成的复合结构。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或者聚噻吩材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或者有机物技术制造的薄膜晶体管。
(3)在形成前述图案的基底上涂覆平坦薄膜，通过构图工艺对第五绝缘层20进行构图，形成覆盖整个基底10的第二平坦化(PLN)层21，第五绝缘层20和第二平坦化层21上开设有第二过孔，第二过孔形成在显示基板区 域300，第二过孔内的第二平坦化层21和第五绝缘层20被去掉，暴露出漏电极19B的表面，如图4所示。本次工艺中，切割区域400对应切割标识层位置的第二平坦化层21被保留，切割区域400的第二平坦化层21具有平坦的表面，切割区域400的第二平坦化层21的厚度与显示基板区域300的第二平坦化层21的厚度相同。本次构图工艺后，切割区域400包括设置在基底10上的复合绝缘层、设置在复合绝缘层上的切割标识层、覆盖切割标识层的第五绝缘层20和覆盖第五绝缘层20的第二平坦化层21。
(4)在形成前述图案的基底上沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，在第二平坦化层21上形成阳极22图案，阳极22形成在显示基板区域300，阳极22通过第二过孔与薄膜晶体管101的漏电极连接，如图5所示。透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)。本次构图工艺后，切割区域400包括设置在基底10上的复合绝缘层、设置在复合绝缘层上的切割标识层、覆盖切割标识层的第五绝缘层20和覆盖第五绝缘层20的第二平坦化层21。
(5)在形成前述图案的基底上涂覆像素定义薄膜，通过掩膜、曝光、显影工艺，形成像素定义层(PDL)23图案，像素定义层23上开设有像素开口，像素开口形成在显示基板区域300，像素开口内的像素定义薄膜被显影掉，暴露出阳极22的表面，如图6所示。像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯。本次工艺中，像素开口位置的像素定义薄膜被显影掉，切割区域400对应切割标识层位置的像素定义薄膜被保留，因而切割区域400的像素定义层23具有平坦的表面，切割区域400的像素定义层23的厚度与显示基板区域300的像素定义层23的厚度相同。本次构图工艺后，切割区域400包括设置在基底10上的复合绝缘层、设置在复合绝缘层上的切割标识层、覆盖切割标识层的第五绝缘层20、覆盖第五绝缘层20的第二平坦化层21和覆盖第二平坦化层21的像素定义层23。切割区域400的第二平坦化层21和像素定义层23组成覆盖标识结构层的平坦化层。
(6)在后续工艺中，先在显示基板区域300依次形成有机发光层24、阴极25和封装层26，随后通过剥离工艺将显示母板从玻璃载板1上剥离，采用滚轮贴合方式在显示母板背面(基底10远离膜层的一侧表面)贴附一层 背膜2，完成显示母板的制备，如图2所示。最后，切割设备按照切割标识对显示母板进行切割，形成多个显示基板。
有机发光层可以包括叠设的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层，阴极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)金属材料的任意一种，或采用上述金属中任意一种或多种制成的合金，封装层可以采用例如包括无机材料层、有机材料层和无机材料层的叠层结构，封装层仅覆盖显示基板区域。在一示例性实施方式中，显示基板区域还可以包括设置在封装层上的触控层或触控面板以及覆盖触控层或触控面板的保护层(OC)。
在一示例性实施方式中，显示基板区域还可以包括保护膜(Temporary Protect Film，简称TPF)27，在制备完成封装层26后，通过贴附工艺在显示母板上贴附一层保护膜27，在显示基板区域300，保护膜27贴设在封装层上，在切割区域400，保护膜27贴设在像素定义层23上，保护膜27与像素定义层23直接接触，如图7所示。在显示母板上贴设保护膜能够保护显示基板的膜层结构。在贴附保护膜27后，通过剥离工艺将显示母板从玻璃载板1上剥离，采用滚轮贴合方式在显示母板背面贴附一层背膜2，完成显示母板的制备。随后，切割设备按照切割标识对显示母板进行切割，形成多个显示基板。完成切割后，先去除该保护膜，然后在封装层上依次设置触控层和盖板，形成触控显示面板；或者在封装层上直接设置盖板，形成显示面板。
显示基板区域包括显示区域和绑定区域，显示区域包括矩阵排列的多个像素，设置为实现图像显示，绑定区域包括驱动电路，设置为从外部集成电路接收控制信号并发送给显示区域的多个像素。图8为本公开一种绑定区域的结构示意图。绑定区域是从显示区域突出来的一个区域，显示母板被分隔成多个显示基板区域后，绑定区域将被弯折到显示区域的背面。在一示例性实施方式中，绑定区域设置在显示区域的一侧，如图8所示，绑定区域包括沿着远离显示区域的方向依次设置的第一扇区(fanout A)、绑定区(bending)、第二扇区(fanout B)、面板测试(cell test)区、集成电路(IC)区、外引脚绑定(OLB)区和柔性电路板(FPC)区。在一示例中，绑定区域长度(第一扇区到柔性电路板区的长度)L为9mm到10mm，如9.601mm。
本公开提出了一种切割标识结构。图9为本公开一种切割标识的结构示意图。如图9所示，切割标识包括4个矩形图案，4个矩形图案按照田字形排列，即按照2*2的矩阵方式排列。通过田字形排列的4个矩形图案，可以最大限度地减少气泡轮廓或杂质轮廓对切割标识外形的影响，提高切割设备对切割标识外形判断的准确度，避免切割设备不能识别切割标识的情形。
如图2至图7所示，显示母板可以包括：
基底10；
设置在基底10上的第一绝缘层11；
设置在第一绝缘层11上的有源层12，有源层12设置在显示基板区域300；
覆盖有源层12的第二绝缘层13；
设置在第二绝缘层13上的第一栅金属层，第一栅金属层设置在显示基板区域300，至少包括栅电极14和第一电容电极15；
覆盖第一栅金属层的第三绝缘层16；
设置在第三绝缘层16的第二栅金属层，第二栅金属层设置在显示基板区域300，至少包括第二电容电极17；
覆盖第二栅金属层的第四绝缘层18，其上开设有暴露出有源层12的两个第一过孔，两个第一过孔设置在显示基板区域300；
设置在第四绝缘层18上的第一源漏金属层和切割标识层，第一源漏金属层设置在显示基板区域300，至少包括源电极19A和漏电极19B，源电极19A和漏电极19B分别通过第一过孔与有源层12连接；切割标识层设置在切割区域400，至少包括二个间隔设置的标识块40；第一源漏金属层和切割标识层同层设置，且通过同一次构图工艺形成；
覆盖第一源漏金属层的第五绝缘层20和第二平坦化层21，其上开设有暴露出漏电极19B的第二过孔，第二过孔设置在显示基板区域300；切割区域400的第二平坦化层21远离基底10的表面为平齐状；
设置在第二平坦化层21上的阳极22，阳极22设置在显示基板区域300，通过第二过孔与漏电极19B连接；
覆盖阳极22的像素定义层23，其上开设有暴露出阳极22的像素开口，像素开口形成在显示基板区域300；切割区域的像素定义层23远离基底10的表面为平齐状；
设置在显示基板区域300像素开口内的有机发光层24，有机发光层24与阳极22连接；
设置有机发光层24上的阴极25，阴极25与有机发光层24连接；
设置在显示基板区域300的封装层26；
覆盖前述结构的保护膜27，在显示基板区域300，保护膜27设置在封装层上，在切割区域400，保护膜27设置在像素定义层23上，保护膜27与像素定义层23直接接触。
通过以上描述的显示母板的结构和制备流程可以看出，本公开所提供的显示母板，通过在切割区域保留完整的平坦化层和像素定义层，且切割区域的切割标识层与显示基板区域的第一源漏金属层同层，有效提高了切割区域膜层的整体刚度，减小了因滚轮压力产生的形变，避免了切割区域产生气泡，从而避免出现因气泡遮挡切割标识导致的切割标识无法识别的情况。
一种传统结构中，为了减少后续切割工艺的切割厚度和难度，切割区域的平坦化层和像素定义层均开设有暴露出第五绝缘层的凹槽。由于凹槽所在位置有较大的高度差，切割标识层变形空间较大，因而在贴合背膜工艺中当滚轮压设基底时，切割标识层会产生较大的变形，进而形成较多的气泡。本公开中，通过在切割区域保留完整的平坦化层和像素定义层，填补了该区域的高度差，不仅增加了切割区域膜层的整体刚度，而且消除了切割标识层的变形空间。贴合背膜工艺中滚轮压设基底时，切割标识层上方较厚的平坦化层和像素定义层能够支撑切割标识层抵抗基底的变形，有效减小了切割标识层的变形，避免了气泡产生，因而降低了气泡对识别切割标识的干扰和影响，避免出现切割区域的切割标识无法识别的情况。
一种传统结构中，切割标识层设置成与显示基板区域的第一栅金属层同层，即切割标识层设置在第二绝缘层与第三绝缘层之间。由于切割标识层与基底之间仅间隔第一绝缘层和第二绝缘层，两个绝缘层的厚度和刚度较小， 当较软的柔性基底发生较大形变时，切割标识层也会发生较大变形，进而形成较多的气泡。本公开中，通过将切割标识层由第一栅金属层变为第一源漏金属层，切割标识层设置成与显示基板区域的第一源漏金属层同层，即切割标识层设置在第四绝缘层上，切割标识层与基底之间间隔有第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层一共四个绝缘层，增加了切割标识层与基底之间膜层的厚度和刚度。这样，即使柔性基底发生较大形变，较大厚度和刚度的四个绝缘层可以抵抗基底的部分变形，在一定程度上减小了切割标识层的变形，减少了气泡数量。
此外，本公开的制备工艺可以利用成熟的制备设备实现，对工艺改进较小，兼容性高，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。总之，本公开的方案避免了切割区域的切割标识无法识别的情况，保证了切割工艺的准确性和可靠性，具有良好的应用前景。
图10为本公开另一种显示母板的结构示意图，示意了双源漏金属层(双SD或2SD)结构显示基板区域和切割区域的剖面结构。如图10所示，显示母板包括显示基板区域300和切割区域400，显示基板区域300包括设置在基底10上的驱动结构层和设置在驱动结构层上的发光结构层，切割区域400包括设置在基底10上的复合绝缘层、设置在复合绝缘层上的切割标识层和覆盖切割标识层的绝缘层。显示基板区域300的驱动结构层包括形成像素驱动电路的多个薄膜晶体管和存储电容，图8中仅以一个驱动薄膜晶体管101和存储电容102为例进行示意。驱动结构层包括设置在基底10上的第一绝缘层11、设置在第一绝缘层11上的薄膜晶体管101和存储电容102、覆盖薄膜晶体管101和存储电容102的第五绝缘层20和第一平坦化层21A、设置在第一平坦化层21A上的第二金属导电层以及覆盖第二金属导电层的第二平坦化层21，第二金属导电层包括与薄膜晶体管101的漏电极连接的连接电极103。发光结构层包括阳极22、像素定义层23、有机发光层24、阴极25以及封装层26。切割区域400的复合绝缘层包括在基底10上依次叠设的第一绝缘层11、第二绝缘层13、第三绝缘层16、第四绝缘层18、第五绝缘层20和第一平坦化层21A，切割标识层包括设置在复合绝缘层上的标识块40，绝缘层包括覆盖切割标识层的第二平坦化层21和覆盖第二平坦化层21的像素定义层 23。切割区域400的第二平坦化层21和像素定义层23组成覆盖标识结构层的平坦化层。如图10所示，切割区域400的第二平坦化层21和像素定义层23被完整保留，远离基底10一侧的表面为平齐状，有效提高了切割区域膜层的整体刚度。
本公开的制备过程可包括：
(11)在玻璃载板1上形成基底10，制备过程与前述的工艺(1)相同。
(12)在基底10上制备驱动结构层和切割标识层图案，包括：在基底10上依次形成第一绝缘层11、有源层12、第二绝缘层13、第一栅金属层、第三绝缘层16、第二栅金属层、第四绝缘层18和第一源漏金属层，处理过程与前述处理过程类似，所不同的是，在对第三金属薄膜进行构图中，只在显示基板区域300形成第一源漏金属层图案，切割区域400不形成切割标识层。
随后，形成覆盖第一源漏金属层的第五绝缘层20和第一平坦化层21A，第五绝缘层20和第一平坦化层21A上开设有第三过孔，第三过孔形成在显示基板区域300，暴露出漏电极19B的表面。随后，沉积第四金属薄膜，通过构图工艺对第四金属薄膜进行构图，在第一平坦化层21A上形成第二金属导电层和切割标识层。第二金属导电层形成在显示基板区域300，切割标识层形成在切割区域400，切割标识层包括至少二个间隔设置的标识块40。第一源漏金属层至少包括源电极19A、漏电极19B和数据线，第二金属导电层包括通过第三过孔与漏电极19B连接的连接电极103。本次构图工艺后，切割区域400包括设置在基底10上的复合绝缘层和设置在复合绝缘层上的切割标识层，复合绝缘层包括叠设的第一绝缘层11、第二绝缘层13、第三绝缘层16、第四绝缘层18、第五绝缘层20和第一平坦化层21A，切割标识层包括标识块40。在一示例性实施方式中，根据实际需要，第二金属导电层还可以包括电源线(VDD)、低压线(VSS)、补偿线和辅助阴极中的任意一种或多种。
至此，在基底10上制备完成驱动结构层和切割标识层图案，如图11所示。有源层12、栅电极14、源电极19A和漏电极19B组成薄膜晶体管101，第一电容电极15与第二电容电极17组成存储电容102，第一源漏金属层至 少包括源电极19A和漏电极19B，第二金属导电层至少包括连接电极103，第二金属导电层和切割标识层同层设置，且通过同一次构图工艺形成。
(13)在形成前述图案的基底上涂覆平坦薄膜，通过掩膜、曝光和显影工艺，形成覆盖整个基底10的第二平坦化层21，第二平坦化层21上开设有第四过孔，第四过孔形成在显示基板区域300，第四过孔内的平坦薄膜被显影掉，暴露出连接电极103的表面，如图12所示。本次工艺中，第四过孔位置的平坦薄膜被显影掉，切割区域400对应切割标识层位置的第二平坦化层21被保留，因而切割区域400的第二平坦化层21具有平坦的表面，且切割区域400的第二平坦化层21的厚度与显示基板区域的第二平坦化层21的厚度相同。本次构图工艺后，切割区域400包括设置在基底10上的复合绝缘层、设置在复合绝缘层上的切割标识层和覆盖切割标识层的第二平坦化层21。
(14)在形成前述图案的基底上依次形成阳极22、像素定义层23、有机发光层24、阴极25和封装层26，制备过程与前述的工艺(4)至(6)相同，后续贴附保护膜、从玻璃载板上剥离、贴附背膜、切割过程与前述工艺相同，这里不再赘述。
如图10至图12所示，显示母板可包括：
基底10；
设置在基底10上的第一绝缘层11；
设置在第一绝缘层11上的有源层12，有源层12设置在显示基板区域300；
覆盖有源层12的第二绝缘层13；
设置在第二绝缘层13上的第一栅金属层，第一栅金属层设置在显示基板区域300，至少包括栅电极14和第一电容电极15；
覆盖第一栅金属层的第三绝缘层16；
设置在第三绝缘层16上的第二栅金属层，第二栅金属层设置在显示基板区域300，至少包括第二电容电极17；
覆盖第二栅金属层的第四绝缘层18，其上开设有暴露出有源层12的两个第一过孔，两个第一过孔设置在显示基板区域300；
设置在第四绝缘层18上的第一源漏金属层，第一源漏金属层设置在显示基板区域300，至少包括源电极19A和漏电极19B，源电极19A和漏电极19B分别通过第一过孔与有源层12连接；
覆盖第一源漏金属层的第五绝缘层20和第一平坦化层21A，其上开设有暴露出漏电极19B的第三过孔，第三过孔设置在显示基板区域300；
设置在第一平坦化层21A上的第二金属导电层和切割标识层；第二金属导电层设置在显示基板区域300，至少包括连接电极103，连接电极103通过第三过孔与漏电极19B连接；切割标识层设置在切割区域400，至少包括二个间隔设置的标识块40；第二金属导电层和切割标识层同层设置，且通过同一次构图工艺形成；
覆盖第二金属导电层的第二平坦化层21，其上开设有暴露出连接电极103的第四过孔，第四过孔设置在显示基板区域300；切割区域400的第二平坦化层21远离基底10的表面为平齐状；
设置在第二平坦化层21上的阳极22，阳极22形成在显示基板区域300，通过第四过孔与连接电极103连接；
覆盖阳极22的像素定义层23，其上开设有暴露出阳极22的像素开口，像素开口形成在显示基板区域300；切割区域400的像素定义层23远离基底10的表面为平齐状；
设置在显示基板区域300像素开口内的有机发光层24，有机发光层24与阳极22连接；
设置在有机发光层24上的阴极25，阴极25与有机发光层24连接；
设置在显示基板区域300的封装层26。
由于将切割标识层设置成与显示基板区域的第二金属导电层同层，即切割标识层设置在第一平坦化层上，切割标识层与基底之间间隔有第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层和第一平坦化层一共六个绝缘层，增加了切割标识层与基底之间膜层的厚度和刚度，可以减小切割标识层的变形，减少气泡数量，最大限度地避免了切割区域的切割标识无法 识别。
图13为本公开又一种显示母板的结构示意图，是前述图2所示结构一种扩展。与前述图2所示显示母板不同的是，在显示基板区域300和切割区域400分别形成驱动结构层和切割标识层后，直接在驱动结构层和切割标识层上形成第二平坦化层21，即显示母板不设置第五绝缘层。
图14为本公开又一种显示母板的结构示意图，是前述图10所示结构一种扩展。与前述图10所示显示母板不同的是，在形成第一源漏金属层后，直接形成覆盖第一源漏金属层的第一平坦化层21A，即显示母板不设置第五绝缘层。
本公开所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，OLED可以是顶发射结构，或者可以是底发射结构。又如，驱动薄膜晶体管可以是顶栅结构，或者可以是底栅结构，可以是单栅结构，或者可以是双栅结构。再如，驱动结构层和发光结构层中还可以设置其它电极或引线，本公开在此不做具体的限定。
本公开还提供了一种显示母板的制备方法。所述显示母板包括多个显示基板区域和位于每个所述显示基板区域周边的切割区域，制备方法包括：
S1、在多个显示基板区域和切割区域分别形成驱动结构层和标识结构层；所述标识结构层包括切割标识层；
S2、在所述驱动结构层和标识结构层上形成平坦化层，所述平坦化层覆盖所述标识结构层。
在示例性实施方式中，所述驱动结构层包括第一源漏金属层，所述标识结构层包括切割标识层，步骤S1包括：
在基底上形成第一绝缘层，在所述第一绝缘层上形成有源层，形成覆盖所述有源层的第二绝缘层，在所述第二绝缘层上形成第一栅金属层，形成覆盖所述第一栅金属层的第三绝缘层，在所述第三绝缘层上形成第二栅金属层，形成覆盖所述第二栅金属层的第四绝缘层，在所述第四绝缘层上通过同一次构图工艺形成所述第一源漏金属层和切割标识层；所述有源层、第一栅金属 层、第二栅金属层和第一源漏金属层设置在所述显示基板区域，所述切割标识层设置在所述切割区域。
在示例性实施方式中，步骤S2包括：
在所述驱动结构层和标识结构层上形成第五绝缘层；
在所述第五绝缘层上依次形成第二平坦化层和像素定义层，在所述显示基板区域，所述第二平坦化层与像素定义层之间还形成有阳极。
在示例性实施方式中，所述驱动结构层包括第二源漏金属层，所述标识结构层包括切割标识层，步骤S1包括：
在基底上形成第一绝缘层，在所述第一绝缘层上形成有源层，形成覆盖所述有源层的第二绝缘层，在所述第二绝缘层上形成第一栅金属层，形成覆盖所述第一栅金属层的第三绝缘层，在所述第三绝缘层上形成第二栅金属层，形成覆盖所述第二栅金属层的第四绝缘层，在所述第四绝缘层上形成第一源漏金属层，形成覆盖所述第一源漏金属层的第五绝缘层，在所述第五绝缘层上形成第一平坦化层，在所述第一平坦化层上通过同一次构图工艺形成所述第二源漏金属层和切割标识层；所述有源层、第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层设置在所述显示基板区域，所述切割标识层设置在所述切割区域。
在示例性实施方式中，步骤S2包括：
在所述第一平坦化层上依次形成第二平坦化层和像素定义层，在所述显示基板区域，所述第二平坦化层与像素定义层之间还形成有阳极。
在示例性实施方式中，在所述平坦化层上形成像素定义层之后，所述制备方法还包括：
形成有机发光层、阴极和封装层；
在所述封装层上贴附保护膜，在所述切割区域，所述保护膜与所述像素定义层接触；
采用滚轮贴合方式在所述基底远离所述平坦化层一侧的表面贴附背膜；
对所述显示母板进行切割，形成多个显示基板。
在示例性实施方式中，对所述显示母板进行切割之后，所述制备方法还包括：
去除所述保护膜；
在所述封装层上形成盖板；或者在所述封装层上依次形成触控层和盖板。
本公开提供了一种显示母板的制备方法，通过在切割区域保留完整的平坦化层和像素定义层，且切割区域的切割标识层与显示基板区域的第一源漏金属层同层，有效提高了切割区域膜层的整体刚度，减小了因滚轮压力产生的形变，避免了切割区域产生气泡，避免出现因气泡遮挡切割标识导致的切割标识无法识别的情况，保证了切割工艺的准确性和可靠性。此外，本公开的制备工艺可以利用成熟的制备设备实现，工艺改进较小、兼容性高，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高，具有良好的应用前景。
本公开还提供了一种显示基板，显示基板由前述显示母板沿着所述切割区域切割而形成。
本公开还提供了一种显示装置，包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪，或任何其它具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本申请的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (19)

  1. 一种显示母板，包括多个显示基板区域和位于每个所述显示基板区域周边的切割区域；所述显示母板还包括：
    设置在每个显示基板区域的驱动结构层，以及设置在每个切割区域的标识结构层；所述标识结构层包括切割标识层；
    设置在所述驱动结构层和标识结构层上的平坦化层，所述平坦化层覆盖所述标识结构层。
  2. 根据权利要求1所述的显示母板，其中，所述驱动结构层包括第一源漏金属层，所述标识结构层包括切割标识层，所述切割标识层与所述第一源漏金属层同层设置。
  3. 根据权利要求2所述的显示母板，其中，所述驱动结构层还包括：设置在基底上的第一绝缘层，设置在所述第一绝缘层上的有源层，覆盖所述有源层的第二绝缘层，设置在所述第二绝缘层上的第一栅金属层，覆盖所述第一栅金属层的第三绝缘层，设置在所述第三绝缘层上的第二栅金属层，覆盖所述第二栅金属层的第四绝缘层，所述第一源漏金属层设置在所述第四绝缘层上；所述标识结构层还包括；在基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层，所述切割标识层设置在所述第四绝缘层上。
  4. 根据权利要求3所述的显示母板，所述显示母板还包括第五绝缘层；在所述显示基板区域，所述第五绝缘层设置在所述驱动结构层上，在所述切割区域，所述第五绝缘层设置在所述标识结构层上，所述平坦化层设置在所述第五绝缘层上。
  5. 根据权利要求4所述的显示母板，其中，所述平坦化层包括设置在所述第五绝缘层上的第二平坦化层和设置在所述第二平坦化层上的像素定义层；在所述显示基板区域，所述第二平坦化层与像素定义层之间还设置有阳极。
  6. 根据权利要求1所述的显示母板，其中，所述驱动结构层包括第二源漏金属层，所述标识结构层包括切割标识层，所述切割标识层与所述第二源漏金属层同层设置。
  7. 根据权利要求6所述的显示母板，其中，所述驱动结构层还包括：设置在基底上的第一绝缘层，设置在所述第一绝缘层上的有源层，覆盖所述有源层的第二绝缘层，设置在所述第二绝缘层上的第一栅金属层，覆盖所述第一栅金属层的第三绝缘层，设置在所述第三绝缘层上的第二栅金属层，覆盖所述第二栅金属层的第四绝缘层，设置在所述第四绝缘层上的第一源漏金属层，覆盖所述第一源漏金属层的第五绝缘层和第一平坦化层，所述第二源漏金属层设置在所述第一平坦化层上；所述标识结构层还包括：在基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层和第一平坦化层，所述切割标识层设置在所述第一平坦化层上。
  8. 根据权利要求7所述的显示母板，其中，所述平坦化层包括覆盖所述驱动结构层和标识结构层的第二平坦化层和设置在所述第二平坦化层上的像素定义层；在所述显示基板区域，所述第二平坦化层与像素定义层之间还设置有阳极。
  9. 根据权利要求1至8中任一项所述的显示母板，还包括保护膜；在所述显示基板区域，所述平坦化层上设置有封装层，所述保护膜设置在所述封装层上；在所述切割区域，所述保护膜设置在所述平坦化层上。
  10. 根据权利要求1至中8任一项所述的显示母板，其中，所述切割区域的切割标识层包括多个切割标识，每个所述切割标识包括田字形排列的4个间隔的矩形图案。
  11. 一种显示基板，由如权利要求1至10中任一项所述的显示母板沿着所述切割区域切割而形成。
  12. 一种显示装置，包括如权利要求11所述的显示基板。
  13. 一种显示母板的制备方法，所述显示母板包括多个显示基板区域和位于每个所述显示基板区域周边的切割区域，所述制备方法包括：
    在多个显示基板区域和切割区域分别形成驱动结构层和标识结构层；所述标识结构层包括切割标识层；
    在所述驱动结构层和标识结构层上形成平坦化层，所述平坦化层覆盖所述标识结构层。
  14. 根据权利要求13所述的制备方法，其中，所述驱动结构层包括第一源漏金属层，所述标识结构层包括切割标识层，在多个显示基板区域和切割区域分别形成驱动结构层和标识结构层，包括：
    在基底上形成第一绝缘层，在所述第一绝缘层上形成有源层，形成覆盖所述有源层的第二绝缘层，在所述第二绝缘层上形成第一栅金属层，形成覆盖所述第一栅金属层的第三绝缘层，在所述第三绝缘层上形成第二栅金属层，形成覆盖所述第二栅金属层的第四绝缘层，在所述第四绝缘层上通过同一次构图工艺形成所述第一源漏金属层和切割标识层；所述有源层、第一栅金属层、第二栅金属层和第一源漏金属层设置在所述显示基板区域，所述切割标识层设置在所述切割区域。
  15. 根据权利要求14所述的制备方法，其中，在所述驱动结构层和标识结构层上形成平坦化层，包括：
    在所述驱动结构层和标识结构层上形成第五绝缘层；
    在所述第五绝缘层上依次形成第二平坦化层和像素定义层，在所述显示基板区域，所述第二平坦化层与像素定义层之间还形成有阳极。
  16. 根据权利要求13所述的制备方法，其中，所述驱动结构层包括第二源漏金属层，所述标识结构层包括切割标识层，在多个显示基板区域和切割区域分别形成驱动结构层和标识结构层，包括：
    在基底上形成第一绝缘层，在所述第一绝缘层上形成有源层，形成覆盖所述有源层的第二绝缘层，在所述第二绝缘层上形成第一栅金属层，形成覆盖所述第一栅金属层的第三绝缘层，在所述第三绝缘层上形成第二栅金属层，形成覆盖所述第二栅金属层的第四绝缘层，在所述第四绝缘层上形成第一源漏金属层，形成覆盖所述第一源漏金属层的第五绝缘层，在所述第五绝缘层上形成第一平坦化层，在所述第一平坦化层上通过同一次构图工艺形成所述第二源漏金属层和切割标识层；所述有源层、第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层设置在所述显示基板区域，所述切割标识层设置在所述切割区域。
  17. 根据权利要求16所述的制备方法，其中，在所述驱动结构层和标识 结构层上形成平坦化层，包括：
    在所述第一平坦化层上依次形成第二平坦化层和像素定义层，在所述显示基板区域，所述第二平坦化层与像素定义层之间还形成有阳极。
  18. 根据权利要求13至17中任一项所述的制备方法，所述制备方法还包括：
    依次形成有机发光层、阴极和封装层；
    在所述封装层上贴附保护膜，在所述切割区域，所述保护膜与所述像素定义层接触；
    采用滚轮贴合方式在所述基底远离所述平坦化层一侧的表面贴附背膜；
    对所述显示母板进行切割，形成多个显示基板。
  19. 根据权利要求18所述的制备方法，其中，对所述显示母板进行切割之后，所述制备方法还包括：
    去除所述保护膜；
    在所述封装层上形成盖板；或者在所述封装层上依次形成触控层和盖板。
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