WO2023201475A1 - 一种表面声波滤波器 - Google Patents

一种表面声波滤波器 Download PDF

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Publication number
WO2023201475A1
WO2023201475A1 PCT/CN2022/087453 CN2022087453W WO2023201475A1 WO 2023201475 A1 WO2023201475 A1 WO 2023201475A1 CN 2022087453 W CN2022087453 W CN 2022087453W WO 2023201475 A1 WO2023201475 A1 WO 2023201475A1
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Prior art keywords
electrode
filter
piezoelectric layer
substrate
layer
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PCT/CN2022/087453
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English (en)
French (fr)
Inventor
黎子兰
王乐知
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广东致能科技有限公司
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Priority to PCT/CN2022/087453 priority Critical patent/WO2023201475A1/zh
Publication of WO2023201475A1 publication Critical patent/WO2023201475A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/125—Driving means, e.g. electrodes, coils
    • H03H9/145—Driving means, e.g. electrodes, coils for networks using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/25—Constructional features of resonators using surface acoustic waves

Definitions

  • the present invention relates to a semiconductor device, and in particular to a surface acoustic wave filter.
  • filters there are many types of filters, including dielectric filters, LC filters, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, etc.
  • SAW surface acoustic wave
  • BAW bulk acoustic wave
  • surface acoustic wave filters have many advantages such as light weight, small size, high reliability, good consistency, flexible design, and can be manufactured using microelectronic processing technology, suitable for mass production. They have been widely used in mobile communications, radio and television, Non-destructive testing, identification and positioning, navigation and telemetry and many other fields.
  • SAW filters are horizontal structure devices and have many limitations. For example, limited by the inherent on-chip area, it is difficult to achieve larger-scale integration. Horizontal devices are not conducive to heat dissipation and affect the overall performance of the device.
  • the present invention proposes a surface acoustic wave filter, including: a piezoelectric layer configured to convert mechanical energy and electrical energy to each other; wherein the piezoelectric layer includes a first vertical interface , a first electrode and a second electrode are disposed on the first vertical interface, the first electrode forms ohmic contact with the piezoelectric layer and is configured to receive an electrical signal; the second electrode and the piezoelectric layer The layer forms an ohmic contact and is configured to output an electrical signal; wherein the first electrode and the second electrode are interdigitated electrodes.
  • the piezoelectric layer material is at least one of AlN, lithium tantalate, ZnO, and PZT.
  • the method further includes a substrate, which includes a vertical interface, and the piezoelectric layer is epitaxially grown through the vertical interface.
  • the substrate is a Si substrate, and its vertical interface is the Si (111) plane; the substrate is an Al2O3 sapphire substrate, and its vertical interface is the (0001) plane of Al2O3; and the substrate is a SiC substrate, Its vertical interface is the (0001) or (000-1) plane of SiC; or, where the substrate is a GaN intrinsic substrate, its vertical interface is the (0001) plane or (000-1) plane of the GaN intrinsic substrate .
  • a thermally conductive layer is further included, wherein the substrate is between the piezoelectric layer and the thermally conductive layer.
  • the substrate undergoes a thinning process; or the thickness of the substrate is 0-3000nm.
  • a buffer layer is included between the vertical interface of the substrate and the piezoelectric layer.
  • the piezoelectric layer is disposed above the buffer layer.
  • the first electrode and the second electrode are attached to the first vertical interface of the piezoelectric layer and are self-supporting on the first vertical interface.
  • the first vertical interface includes a first acoustic wave reflector and a second acoustic wave reflector outside the first electrode and the second electrode respectively.
  • the method further includes a housing that encapsulates at least the first vertical interface of the piezoelectric layer.
  • the piezoelectric layer includes a first gap outside the first vertical interface.
  • the piezoelectric layer includes a second gap outside the second vertical interface relative to the first vertical interface.
  • a third gap is included above or below the piezoelectric layer.
  • the first electrode and the second electrode are electrically interconnected above the piezoelectric layer or below the piezoelectric layer.
  • the first electrode and the second electrode are electrically interconnected above and below the piezoelectric layer respectively.
  • the first electrode and the second electrode are electrically interconnected respectively on the left and right of the first vertical interface of the piezoelectric layer.
  • This application also relates to a filter network, including: a plurality of filters as mentioned above; wherein the above filters are integrated on a single chip.
  • the aforementioned filters share the same substrate or support layer.
  • the plurality of filters as described above form a ladder configuration, a lattice configuration, or a ladder-lattice configuration.
  • the present application also relates to a semiconductor device, including: a filter as mentioned above or a filter network as mentioned above; and one or more transistors; wherein the filter as mentioned above or one or more filter networks as mentioned above and a or multiple transistors integrated on a single chip.
  • the one or more filters according to any one of claims 1-17 or one or more filter networks according to any one of claims 18-20 and one or more transistors share same substrate or support layer.
  • the one or more transistors include HEMT or HHMT.
  • the HEMT or HHMT includes a vertically arranged channel layer and a channel providing layer.
  • FIGS. 1A to 1B are schematic structural diagrams of a surface acoustic wave filter according to an embodiment of the present invention.
  • FIGS. 2A to 2T are schematic diagrams of the preparation steps of a surface acoustic wave filter according to an embodiment of the present invention.
  • 3A to 3B are schematic structural diagrams of a surface acoustic wave filter according to another embodiment of the present invention.
  • Figure 4 is a schematic structural diagram of a surface acoustic wave filter with a reflector according to an embodiment of the present invention
  • Figures 5A to 5C are schematic structural diagrams of a surface acoustic wave filter with a housing according to an embodiment of the present invention
  • Figure 6A is a schematic diagram of a piezoelectric layer structure according to another embodiment of the present invention.
  • Figures 6B to 6D are schematic diagrams of a surface acoustic wave filter structure according to another embodiment of the present invention.
  • Figure 7A is a schematic structural diagram of a surface acoustic wave filter according to another embodiment of the present invention.
  • Figure 7B is a schematic structural diagram of a surface acoustic wave filter according to another embodiment of the present invention.
  • FIGS. 8A to 8B are schematic diagrams of the preparation steps of a surface acoustic wave filter according to an embodiment of the present invention.
  • 9A to 9C are schematic diagrams of surface acoustic wave filter network topology configuration.
  • spatially relative terms may be used herein to describe the relationship of one element or feature to another element or feature(s) as illustrated in the drawings.
  • the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the drawings.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it can be directly connected or coupled to the other element or intervening elements may be present.
  • the present invention proposes a surface acoustic wave filter with a vertical structure.
  • the sound wave propagates in the vertical direction. That is to say, the lattice direction having the piezoelectric effect in the piezoelectric material of the filter of the present invention is vertical, rather than horizontal as in the prior art. Therefore, in the filter of the present invention, the first electrode and the second electrode that are in contact with the piezoelectric material and provide input electrical signals and output electrical signals are also arranged longitudinally along the piezoelectric material, for example, they are arranged on the same side of the piezoelectric material, In the prior art, the first electrode and the second electrode are generally arranged above the piezoelectric material.
  • FIGS. 1A-1B are schematic structural diagrams of a surface acoustic wave filter according to an embodiment of the present invention.
  • the filter 10 includes two areas with different heights on the substrate 101, forming a step-like structure.
  • a vertical interface 121 is formed between the two areas.
  • the filter 100 further includes a piezoelectric layer 105 beyond the vertical interface 121 .
  • Piezoelectric layer 105 is configured to convert mechanical energy and electrical energy to and from each other.
  • the height of piezoelectric layer 105 may be higher than the height of vertical interface 121 .
  • the piezoelectric layer 105 includes a first vertical interface 122 on which a first electrode 107 and a second electrode 109 are disposed.
  • the first electrode 107 forms an ohmic contact with the piezoelectric layer 105 and is configured to receive an electrical signal.
  • the second electrode 109 forms an ohmic contact with the piezoelectric layer 105 and is configured to output an electrical signal.
  • the first electrode 107 and the second electrode 109 are interdigitated electrodes.
  • the interdigital electrode includes two oppositely intersecting parts, wherein each part includes an interdigital part 171 and a connecting part 172 .
  • the two portions of the interdigital portions 171 are alternately arranged in parallel, and the interdigital portions of each portion are uniformly electrically connected to the connecting portion 172 .
  • the first electrode 107 and the second electrode 109 are IDT electrodes.
  • the filter described herein may include more than two electrodes, such as a ground electrode (not shown).
  • the piezoelectric layer 105 converts the electrical energy from the first electrode 108 into mechanical energy at the first vertical surface in contact with the first electrode 107; the mechanical energy is transmitted to the second vertical interface through the first vertical interface.
  • the mechanical energy is converted into electrical energy again.
  • the material of the piezoelectric layer can be III-IV group ultra-wide bandgap materials, such as GaN, AlN, etc.; it can also be other piezoelectric materials, such as LiTaO 3 , LiNbO 3 , SiO 2 , etc.
  • the piezoelectric layer material is at least one of AlN, lithium tantalate, ZnO, and PZT.
  • the piezoelectric layer material may be a combination of the above materials. Those skilled in the art should understand that the piezoelectric material of the present invention is not limited thereto.
  • the material of the substrate 101 may be Si, SiC, intrinsic GaN, sapphire Al 2 O 3 , etc.
  • a Si substrate which is lower in cost and more mature in technology than other materials, is selected as an example to illustrate the technical solution of the present invention.
  • the piezoelectric material of the present invention is not limited thereto.
  • the substrate is not a necessary structure of the device of the present application. The substrate can be removed through existing technologies, and the structure of the device of the present application can be transferred to other substrates or integrated with other devices.
  • filter 100 also includes a buffer layer 104.
  • the buffer layer 104 is formed on the nucleation layer on the surface of the substrate, or can also be formed directly on the substrate.
  • the piezoelectric layer 105 is formed on the buffer layer 104 .
  • nucleation or buffer layers are not necessary.
  • the material of the nucleation layer may be AlN, which covers the vertical interface 121 of the Si substrate 101 to avoid direct contact between Si in the Si substrate 101 and the piezoelectric layer 105 .
  • the buffer layer 104 can reduce the impact of lattice differences, reduce the impact of differences in lattice constants and thermal expansion coefficients between the substrate 101 and the piezoelectric layer 105, and effectively avoid nitride epitaxy. cracks in the layer and reduce defects in the crystal lattice.
  • the material of the buffer layer may be one or more of AlN, GaN, AlGaN, InGaN, AlInN and AlGaInN.
  • a spacer layer 102 and a spacer layer 103 are included above the substrate 101 .
  • the spacer layer 102 and the spacer layer 103 isolate the filter 100 from the substrate 101, which can reduce the impact of the substrate 101 on the performance of the device, so that the device's ability to increase withstand voltage and reduce dark current is significantly improved.
  • the material of the spacer layer 102 and the spacer layer 103 may be insulating materials such as SiN and SiO 2 .
  • spacer layer 102 and spacer layer 103 are not necessary features.
  • FIG. 1A and FIG. 1B are schematic diagrams of the preparation steps of a surface acoustic wave filter according to an embodiment of the present invention.
  • this embodiment takes the manufacturing process of the filter as shown in FIG. 1A and FIG. 1B as an example.
  • the manufacturing method of a semiconductor device in this embodiment includes: in step 2001, forming a vertical interface 221 on the substrate 201, as shown in FIG. 2A. Thus, two regions with different heights are formed on the substrate 201 .
  • the substrate 201 may be a Si substrate.
  • other substrates such as intrinsic GaN, Al 2 O 3 (sapphire), SiC, etc., can also achieve similar structures.
  • a protective layer is grown on the substrate and patterned to cover only the exposed vertical interfaces of the substrate, as shown in Figure 2B.
  • SiN is grown on the substrate 201 using techniques such as LPCVD to form the protective layer 231 .
  • the protective layer 231 covers the entire substrate 201. Further, through vertical orientation etching technology, SiN on the substrate other than the vertical surface 221 is removed, leaving only SiN on the sidewalls.
  • an insulating layer is formed over the substrate 201, as shown in Figure 2C.
  • An insulating layer is grown on the substrate.
  • the insulating layer 202 may be formed on the entire substrate 201 by crystal growth.
  • the insulating layers 202 and 203 are formed by depositing an insulating material and then thinning it out to obtain an insulating layer with a desired thickness. Due to the existence of the protective layer 231, there is no growth of the insulating layer at the vertical interface.
  • step 2004, the protective layer is removed, as shown in Figure 2D.
  • the SiN on the sidewall is removed through selective etching technology, so that the vertical interface 221 of the substrate 201 is exposed, but at the same time, the spacer layers 202 and 203 of the substrate 201 are retained.
  • a spacer layer is first formed on a substrate with a vertical interface, and then the insulating layer is patterned to expose the vertical interface of the substrate.
  • a nucleation layer is formed on the exposed vertical surface of substrate 201, as shown in Figure 2E.
  • the nucleation layer 204 is generally chosen to be introduced. As known to those skilled in the art, GaN can be nucleated and grown directly on Al 2 O 3 (sapphire), SiC or intrinsic GaN. Since crystal quality control is difficult, the nucleation layer 204 is often introduced during the process. In some cases, it may not be necessary to include step 205 to introduce a nucleation layer 204 such as low temperature GaN or AlN.
  • the wafer can be taken out after growing AlN, and through anisotropic etching, only the AlN nucleation layer on the vertical plane is retained and the AlN in other places is removed, for example, using vertical downward ion bombardment. Dry etching. Since the ion bombardment of AlN on the vertical surface is weak and the bombardment of AlN on other surfaces is strong, the goal of retaining only the AlN on the vertical surface can be achieved.
  • a piezoelectric layer 205 is formed on the nucleation layer 204.
  • the piezoelectric layer 205 is formed on the nucleation layer 204 by epitaxial growth.
  • the step may include forming a buffer layer on the nucleation layer.
  • the buffer layer is not necessary. In essence, the properties of the buffer layer and the piezoelectric layer are very close, and may even be the same material (such as AlN).
  • the basic structure is a piezoelectric layer, and there can be a buffer layer between the piezoelectric layer and the nucleation layer.
  • a support layer 214 is formed over the current device structure.
  • the support layer 214 is deposited by LPCVD to form the support layer 214 covering the piezoelectric layer 205 .
  • the support layer to the right of the piezoelectric layer is patterned.
  • the support layer 214 on the right side of the piezoelectric layer 205 is etched, leaving only a small part of the structure of the right support layer 214 to support the electrode structure formed next.
  • one interdigital portion of the interdigital electrode is formed.
  • a metal layer is deposited by LPCVD and then patterned to form one interdigitated portion 203 of the interdigitated electrode.
  • the support layer is again deposited.
  • the support layer is again deposited in the manner previously described.
  • step 2012 as shown in Figure 2M, another interdigitated portion of the interdigitated electrode is formed.
  • An interdigital portion of the interdigital electrode is formed again in the aforementioned manner.
  • step 2013, as shown in FIGS. 2N to 2P, the interdigital portions of other interdigital electrodes are formed. All the interdigital portions of the interdigital electrode are formed again in the aforementioned manner.
  • a deposition channel is formed.
  • the support layer is etched to form two vertical deposition channels 217 .
  • One end of the interdigitated portion is exposed in the deposition channel 217 .
  • a connection portion of the first electrode is formed.
  • a metal layer is deposited in the deposition channel 217 by LPCVD, and the interdigital portions are electrically connected to form the connection portion of the first electrode. Among them, the interdigitated portion and the connecting portion form the first electrode 207 .
  • a channel support layer is formed.
  • channel support layer 218 is deposited by LPCVD.
  • a connection portion of the second electrode is formed.
  • a metal layer is deposited in the deposition channel 217 by LPCVD, and the interdigital portions are electrically connected to form the connection portion of the second electrode. Among them, the interdigitated portion and the connecting portion form the second electrode 209 .
  • the connection portions are provided on both sides of the piezoelectric layer rather than on the front side of the piezoelectric layer. The position of the connecting part can be set as shown in Figure 2T or as shown in Figure 1B, which can be selected according to actual needs.
  • after step 2017, further including: removing the support layer 214 and the channel support layer 218.
  • the first electrode and the second electrode are attached to and self-supporting on the first vertical interface of the piezoelectric layer 205 .
  • the vertical structure SAW filter of the present invention occupies less chip area, is more conducive to achieving higher integration, reduces costs, and is also conducive to integration with other structures. Furthermore, the vertical structure SAW filter of the present invention has better heat dissipation capabilities, has a more precise and mature process in the isolation structure, and can significantly reduce the cost of the device.
  • FIGS. 3A-3B are schematic structural diagrams of a surface acoustic wave filter according to another embodiment of the present invention.
  • the filter includes a similar structure to that of Figures 1A and 1B.
  • the first electrode 307 and the second electrode 309 are arranged from up and down to left and right (see Figure 1B and Figure 3B).
  • Vertically arranged electrodes require a sufficiently high piezoelectric layer, but forming a high piezoelectric layer requires complicated processes.
  • Horizontally arranged electrodes can save process processes and are more conducive to heat dissipation.
  • the first electrode can also be used as an output electrode and the second electrode can be used as an input electrode.
  • substrate 301 may include a thermally conductive layer underneath. In this way, the substrate 301 will be located between the piezoelectric layer 305 and the thermally conductive layer.
  • the thermal conductive layer can be made of highly thermally conductive materials such as metal or graphene.
  • substrate 301 undergoes a thinning process. After thinning, the thickness of the substrate 301 is between 0-3000 nm, thereby providing better heat dissipation capability.
  • FIG. 4 is a schematic structural diagram of a surface acoustic wave filter with a reflector according to an embodiment of the present invention.
  • this filter adds a reflector outside each of the two electrodes, which are a first reflector 431 and a second reflector 432 respectively.
  • the mechanical energy propagating in the device will inevitably escape to the periphery of the device, especially at both ends.
  • the addition of the first reflector 431 and the second reflector 432 can effectively reduce the escape of mechanical energy.
  • the device additionally includes a shell layer 530 , which encapsulates at least the first vertical interface of the piezoelectric layer 505 .
  • the filter includes a bottom layer 534 and a shell layer 530 and first and second gaps 511 and 512 formed therebetween.
  • the piezoelectric layer 505 includes a first gap 511 outside the first vertical interface, and the piezoelectric layer 505 includes a second gap 512 outside the first vertical interface relative to the second vertical interface 544 .
  • the piezoelectric layer 505, the first electrode 507 and the second electrode 909 can be formed between the substrate 501 and the shell layer 530 and in contact with both, or between the bottom layer 534 and the shell layer 530 and in contact with both.
  • . 5B and 5C are schematic diagrams of a filter according to another embodiment of the present invention, which is similar to the filter of FIG. 5A , except that the substrate 501 is replaced by the bottom layer 534 .
  • the difference between FIG. 5B and FIG. 5C is whether the piezoelectric layer 505, the first electrode 507 and the second electrode 909 are only in contact with the bottom layer 910 and not in contact with the protective layer 930.
  • a third gap 513 is included above the piezoelectric layer 505 .
  • third void 513 may be formed under piezoelectric layer 505 .
  • bottom layer 534 may be a substrate or a thinned substrate.
  • a thermally conductive layer 532 may be included outside the thinned substrate.
  • the bottom layer can also be directly a support layer formed of a highly thermally conductive material after removing the substrate, thereby providing better heat dissipation capability.
  • the cavities provided on both sides of the piezoelectric layer 505 are poor conductors of sound waves.
  • the mechanical wave formed by the piezoelectric layer 505 can propagate only between the electrode 507 and the electrode 509 as much as possible.
  • there is no clutter interference such as other spurious waves the filtering effect is better, and the quality factor is higher.
  • a sacrificial layer covering the piezoelectric layer and the electrode may be formed first, and then a shell layer covering the sacrificial layer may be formed outside the sacrificial layer. Then, holes are opened in the shell layer, and the sacrificial layer is removed by selective etching to form the above-mentioned shell structure with gaps.
  • FIG. 6A is a schematic diagram of a piezoelectric layer structure according to another embodiment of the present invention.
  • the buffer layer 604 is formed on the vertical interface of the substrate 601.
  • Piezoelectric layer 605 is formed on the vertical interface of the buffer layer.
  • the difference from the structure of FIG. 1A is that in the embodiment of FIG. 6A , the piezoelectric layer 605 grows along the horizontal direction.
  • the formed piezoelectric layer has higher lattice consistency and more stable device performance.
  • FIG. 6B to 6C are schematic diagrams of a surface acoustic wave filter structure according to another embodiment of the present invention.
  • a first interdigital electrode 607 and a second interdigital electrode 609 are formed, wherein the first interdigital electrode 607 is below the second interdigital electrode 609.
  • the first interdigital electrode 607 and the second interdigital electrode 609 are attached to and self-supporting on the vertical interface of the piezoelectric layer 605 .
  • the first interdigital electrode 607 and the second interdigital electrode 609 can be formed on the vertical interface of the piezoelectric layer 605 through a support layer similar to the embodiment shown in FIG.
  • the width of the first interdigital electrode 607 and the second interdigital electrode 609 may be slightly wider than the width of the vertical interface of the piezoelectric layer 605 .
  • the first interdigital electrode 607 and the second interdigital electrode 609 may extend a small amount onto both sides of the piezoelectric layer 605 adjacent to the vertical interface. Further, the first interdigital electrode 607 and the second interdigital electrode 609 may form electrical interconnections below and above the piezoelectric layer 605, respectively.
  • Figure 6D is a schematic diagram of a surface acoustic wave filter structure according to another embodiment of the present invention.
  • the difference from the embodiment shown in FIGS. 6B and 6C is that a housing 630 is included in this embodiment.
  • the first interdigital electrodes 607 may each extend downwardly through the substrate 601 and out of the substrate 601 to form electrical interconnections beneath the piezoelectric layer 605 .
  • the second interdigital electrodes 609 may each extend upwardly through the top portion of the housing 630 and beyond the housing 630 to form electrical interconnections above the piezoelectric layer 630 . Since the electrical interconnections of the filter are respectively formed below and above the piezoelectric layer 605, interference can be further reduced and the performance of the device can be improved.
  • FIG. 7A is a schematic structural diagram of a surface acoustic wave filter according to another embodiment of the present invention. Structures similar to those in the previous embodiments will not be described again.
  • the viewing angle in this embodiment is the angle from the other side of the vertical interface of the surface acoustic wave filter including the interdigital electrodes. This is more conducive to illustrating the integration of two surface acoustic wave filters.
  • the surface acoustic wave filter includes a substrate 701 and a piezoelectric layer 705 grown through a vertical interface of the substrate 701 . Piezoelectric layer 705 is separated to form two independent piezoelectric layers 7051 and 7052.
  • the first group of first interdigital electrodes 707 and the second interdigital electrodes 709 are located on the vertical interface of the piezoelectric layer 7051; the second group of first interdigital electrodes 706 and second interdigital electrodes 708 are located on the vertical interface of the piezoelectric layer 7051.
  • the first set of interdigitated electrodes and the second set of interdigitated electrodes may have different spacing to respond to different frequencies.
  • the first and second sets of interdigital electrodes extend above housing 730 and below substrate 701, respectively, thereby forming electrical interconnections above and below piezoelectric layers 7051 and 7052, respectively.
  • two surface acoustic wave filters can be integrated on the same substrate.
  • FIG. 7B is a schematic structural diagram of a surface acoustic wave filter according to another embodiment of the present invention. Structures similar to those in the previous embodiments will not be described again. The difference between this embodiment and the embodiment shown in FIG. 7A is that the piezoelectric layers 7051 and 7052 are respectively grown from two vertical interfaces of the substrate 701 instead of being separated from the same piezoelectric layer.
  • filters of the same or different frequencies can be integrated on a single chip in the same manner, and these filters share the same substrate or support layer.
  • the filter banks formed by these filters can form filter networks of different configurations.
  • connection portion of the filter in the embodiment of Figures 7A and 7B is formed outside the interdigitated portions and is not in contact with the piezoelectric layer.
  • the surface of the piezoelectric layer only includes the interdigitated portions, and the overall structure is more uniform.
  • FIG. 8A to 8B are schematic diagrams of electrical connections of a surface acoustic wave filter according to an embodiment of the present invention. Among them, FIG. 8A shows that the filters are connected in parallel, and FIG. 8B shows that the filters are connected in series. In some embodiments, for the filter shown in FIG. 8A and FIG. 8B , two or more devices may be arranged in the same shell layer, or may be arranged in different shell layers.
  • the first electrode and the second electrode can be led out from above or below respectively.
  • the first electrode and the second electrode may also be electrically interconnected above the piezoelectric layer or below the piezoelectric layer at the same time. Such interconnection methods are also within the scope of the present invention.
  • FIGS. 9A to 9C are schematic diagrams of surface acoustic wave filter network topology configuration.
  • Figure 9A is a ladder topology configuration, which is an unbalanced topology.
  • Figure 9B is a lattice topological configuration, a balanced topology.
  • Figure 9C is a trapezoidal-lattice topological configuration.
  • Different topologies have their own advantages and disadvantages.
  • the shunt element is adjusted to a lower frequency than the voltage divider.
  • the out-of-band rejection is determined by the number of components and the electrostatic capacitance divider.
  • the most suitable topology can be selected for the required suppression function.
  • the filter bank of the present invention can implement filter networks configured in trapezoidal, lattice and ladder-lattice topologies on the same chip.
  • the surface acoustic wave filter described according to the aforementioned embodiments can form a filter network such as that of FIGS. 9A to 9C , forming a ladder configuration, a lattice configuration, or a ladder-lattice configuration. configuration.
  • a filter network includes multiple filters as described above; and these can be filter integrated on a single chip. For example, these filters can share the same substrate or support layer.
  • the surface acoustic wave filter described according to the aforementioned embodiments can form a semiconductor device, which includes one or more filters as described above or one or more filters as described above. a filter network; and one or more transistors; wherein the one or more filters as described above or the one or more filter networks as described above and the one or more transistors are integrated on a single chip. These filters as described above or one or more filter networks as described above and one or more transistors share the same substrate or support layer.
  • one or more transistors may include a HEMT or HHMT.
  • the HEMT or HHMT includes a vertically disposed channel layer and a channel providing layer.
  • multiple filters of the same or different frequencies of the present invention can be integrated on a single chip with other semiconductor components such as transistors (such as HEMTs). These filters, transistors and other semiconductor components share the same substrate or support layer and can form highly integrated semiconductor devices.

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Abstract

一种表面声波滤波器，包括：压电层（105），经配置以将机械能和电能相互转换；其中，压电层（105）包括第一垂直界面（122），第一电极（107）和第二电极（109）设置在第一垂直界面（122）上，第一电极（107）与压电层（105）形成欧姆接触，经配置以接收电信号；第二电极（109）与压电层（105）形成欧姆接触，经配置以输出电信号；其中，第一电极（107）与第二电极（109）为叉指电极。还提供了一种滤波器网络和一种半导体器件。

Description

一种表面声波滤波器 技术领域
本发明涉及一种半导体器件，特别地涉及一种表面声波滤波器。
背景技术
滤波器的种类很多，包括介质滤波器、LC滤波器、表面声波(SAW)滤波器、体声波(BAW)滤波器等。其中，表面声波滤波器具有重量轻，体积小，可靠性高，一致性好，设计灵活以及可以采用微电子加工技术制造，适合批量生产等诸多优点，已被广泛应用于移动通讯、广播电视、无损检测、识别定位、导航和遥测等众多领域。
现有SAW滤波器为水平结构器件，有着很多局限。例如，受限于固有片上面积，难以做到更大规模的集成。水平器件不利于散热，影响器件整体性能。
发明内容
针对现有技术中存在的技术问题，本发明提出了一种表面声波滤波器，包括：压电层，其经配置以将机械能和电能相互转换；其中，所述压电层包括第一垂直界面，第一电极和第二电极设置在所述第一垂直界面上，所述第一电极与所述压电层形成欧姆接触，经配置以接收电信号；所述第二电极与所述压电层形成欧姆接触，经配置以输出电信号；其中，所述第一电极与所述第二电极为叉指电极。
可选的，其中压电层材料为AlN、钽酸锂、ZnO、PZT中的至少一者。
可选的，进一步包括衬底，其包括垂直界面，所述压电层经所述垂直界面外延生长形成。
可选的，其中衬底是Si衬底，其垂直界面是Si(111)面；其中衬底是 Al2O3蓝宝石衬底，其垂直界面是Al2O3的(0001)面；其中衬底是SiC衬底，其垂直界面是SiC的(0001)或(000-1)面；或者，其中衬底是GaN本征衬底，其垂直界面是GaN本征衬底的(0001)面或(000-1)面。
可选的，进一步包括导热层，其中所述衬底在所述压电层与所述导热层之间。
可选的，其中所述衬底经过减薄处理；或者所述衬底的厚度为0-3000nm。
可选的，其中所述衬底的所述垂直界面与所述压电层之间包括缓冲层。
可选的，其中所述压电层设置在所述缓冲层的上方。
可选的，其中所述第一电极和所述第二电极附接在所述压电层的所述第一垂直界面并自支撑于所述第一垂直界面上。
可选的，其中所述第一垂直界面上所述第一电极与所述第二电极之外分别包括第一声波反射器和第二声波反射器。
可选的，进一步包括外壳，其至少囊封所述压电层的所述第一垂直界面。
可选的，其中所述压电层的所述第一垂直界面之外包括第一空隙。
可选的，其中所述压电层的与所述第一垂直界面相对第二垂直界面之外包括第二空隙。
可选的，其中所述压电层的上方或下方包括第三空隙。
可选的，其中所述第一电极和所述第二电极在所述压电层上方或所述压电层的下方实现电互联。
可选的，其中所述第一电极和所述第二电极分别在所述压电层上方和下方实现电互联。
可选的，其中所述第一电极和所述第二电极分别在所述压电层的所述第一垂直界面的左方和右方实现电互联。
本申请还涉及一种滤波器网络，包括：多个如前述的滤波器；其中前述的滤波器集成在单片上。
可选的，其中前述的滤波器共享同一衬底或支撑层。
可选的，其中所述多个如前述的滤波器形成梯形配置、晶格配置、或梯形-晶格配置。
本申请还涉及一种半导体器件，包括：如前述的滤波器或者如前述的滤波器网络；以及一个或多个晶体管；其中如前述的滤波器或者一个或多个如前述的滤波器网络以及一个或多个晶体管集成在单片上。
可选的，其中所述一个或多个如权利要求1-17任一所述的滤波器或者一个或多个如权利要求18-20任一所述的滤波器网络以及一个或多个晶体管共享同一衬底或支撑层。
可选的，其中所述一个或多个晶体管包括HEMT或者HHMT。
可选的，其中所述HEMT或者HHMT包括垂直设置的沟道层和沟道提供层。
附图说明
下面，将结合附图对本发明的优选实施方式进行进一步详细的说明，其中：
图1A～1B是根据本发明一个实施例的表面声波滤波器的结构示意图；
图2A～图2T是根据本发明一个实施例的表面声波滤波器的制备步骤示意图；
图3A～3B是根据本发明另一个实施例的表面声波滤波器的结构示意图；
图4是根据本发明一个实施例的具有反射器的表面声波滤波器的结构示意图；
图5A～5C是根据本发明一个实施例的具有外壳的表面声波滤波器的结构示意图；
图6A是根据本发明另一个实施例的压电层结构的示意图；
图6B～6D是根据本发明另一个实施例的表面声波滤波器结构的示意图；
图7A是根据本发明另一个实施例的表面声波滤波器的结构示意图；
图7B是根据本发明另一个实施例的表面声波滤波器的结构示意图；
图8A～图8B是根据本发明一个实施例的表面声波滤波器的制备步骤示意图；
图9A～图9C是表面声波滤波器网络拓扑配置的示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
此外，为了易于描述，诸如「在……之下」、「在……下方」、「在……上方」、「上部」、「下部」、「左侧」、「右侧」及其类似术语的空间相对术语可在本文中用于描述一个元件或特征与另一(或多个)元件或特征的如图式中所说明的关系。除图式中所描绘的定向以外，空间相对术语意欲涵盖装置在使用或操作中的不同定向。设备可以其他方式定向(旋转90度或处于其他定向)，且本文中所使用的空间相对描述词可同样相应地进行解译。应理解，当元件被称为「连接至」或「耦接至」另一元件时，该元件可直接连接至或耦接至另一元件，或可存在介入元件。
在以下的详细描述中，可以参看作为本申请一部分用来说明本申请的特定实施例的各个说明书附图。在附图中，相似的附图标记在不同图式中描述大体上类似的组件。本申请的各个特定实施例在以下进行了足够详细的描述，使得具备本领域相关知识和技术的普通技术人员能够实施本申请的技术方案。应当理解，还可以利用其它实施例或者对本申请的实施例进行结构、逻辑或者电性 的改变。
本发明提出了一种具有垂直结构的表面声波滤波器。与现有技术不同，在本发明滤波器的压电材料中，声波是以垂直方向传播的。也就是说，在本发明滤波器的压电材料中具有压电效应的晶格方向是垂直的，而不是如现有技术中是水平的。由此，在本发明滤波器中与压电材料接触，提供输入电信号和输出电信号的第一电极和第二电极也是沿压电材料纵向布置的，例如设置在压电材料的同一侧面，而现有技术中，第一电极和第二电极一般都布置在压电材料的上方。
图1A～1B是根据本发明一个实施例的表面声波滤波器的结构示意图。如图所示，滤波器10包括衬底101上具有不同高度的两个区域，形成台阶状的结构。由此，在两个区域中间形成了垂直界面121。滤波器100进一步包括垂直界面121之外的压电层105。压电层105经配置以将机械能和电能相互转换。在一些实施例中，压电层105的高度可以高于垂直界面121的高度。压电层105包括第一垂直界面122，第一电极107和第二电极109设置在第一垂直界面122上，第一电极107与压电层105形成欧姆接触，经配置以接收电信号。第二电极109与压电层105形成欧姆接触，经配置以输出电信号。在一些实施例中，第一电极107与第二电极109为叉指电极。叉指电极包括相对交叉的两个部分，其中每个部分包括叉指部171和连接部172。两个部分的叉指部171交替平行排列，每个部分的叉指部统一电连接至连接部172。在一些实施例中，第一电极107与第二电极109为IDT电极。在一些实施例中，本申请所述滤波器可以包括两个以上电极，例如一个接地电极(未示出)。
对于图1所示的垂直结构SAW滤波器，压电层105在与第一电极107接触的第一垂直面将来自第一电极108电能转化为机械能；该机械能经第一垂直界面传输至第二电极109处；在第二电极109处再次将机械能转化为电能。SAW的频率可以大致参考以下公式:F＝V/λ，V是SAW的速率(velocity)，大 概3100m/s,λ是电极之间间距。由公式可知，滤波器谐振频率与电极之间的间距成反比。通过调整电极的间距，能够实现不同通带频率范围的滤波器。
根据本发明一个实施例，压电层的材料可以为III-IV族超宽禁带材料，如GaN、AlN等；也可以是其他压电材料，例如LiTaO 3，LiNbO 3，SiO 2等。在本文的一些实施例中，压电层材料为AlN、钽酸锂、ZnO、PZT中的至少一者。在一些实施例中，压电层材料可以是上述材料的组合。本领域技术人员应当理解，本发明的压电材料并不限于此。
根据本发明一个实施例，衬底101的材料可以是Si、SiC、本征GaN或蓝宝石Al 2O 3等。在一些实施例中，选择相较其他材料成本较低，工艺更为成熟的Si衬底作为实例来说明本发明的技术方案。本领域技术人员应当理解，本发明的压电材料并不限于此。如本领域技术人员所知，衬底不是本申请器件的必要结构，可以通过现有技术去除衬底，将本申请器件结构转移至其他基底或与其他器件集成。
在一些实施例中，滤波器100还包括缓冲层104。缓冲层104形成在衬底表面的成核层上，也可以直接形成在衬底上。压电层105生在缓冲层104之上。目前也存在一些特殊的工艺能够直接在Si衬底的垂直界面上生成宽禁带材料而不必使用成核层或缓冲层。因此，在一些实施例中，成核层或缓冲层不是必要的。
在一些实施例中，成核层的材料可以是AlN，其覆盖Si衬底101的垂直界面121，以避免Si衬底101中的Si与压电层105直接接触。在一些实施例中，缓冲层104能够减少晶格差异带来的影响，减小衬底101与压电层105之间的晶格常数和热膨胀系数等差异带来的影响，有效避免氮化物外延层出现龟裂等情况，减少晶格中的缺陷。缓冲层的材料可以是AlN、GaN、AlGaN、InGaN、AlInN和AlGaInN中一种或多种。
根据本发明的一个实施例，衬底101上方包括间隔层102和间隔层103。 间隔层102和间隔层103将滤波器100与衬底101隔离，能够减少衬底101对于器件性能的影响，使得器件提高耐压和减小暗电流的能力都有明显提升。在一些实施例中，间隔层102和间隔层103的材料可以为SiN、SiO 2等绝缘材料。在一些实施例中，间隔层102和间隔层103不是必要机构。
图2A～图2T是根据本发明一个实施例的表面声波滤波器的制备步骤示意图。为了更好地说明本发明的方案，该实施例以如图1A和图1B所示滤波器的制程为实例。
本实施例的半导体器件的制造方法包括：在步骤2001，在衬底201上形成垂直界面221，如图2A所示。由此，衬底201上形成高低不同的两个区域。衬底201可以为Si衬底。如本领域技术人员所理解，其他衬底如本征GaN、Al 2O 3(蓝宝石)、SiC等，也可以实现类似结构。
在步骤2002，在衬底上生长保护层并图形化为仅覆盖曝露的衬底的垂直界面，如图2B所示。在一些实施例中，在衬底201上使用LPCVD等技术生长SiN，形成保护层231。保护层231覆盖整个衬底201。进一步地，通过垂直取向蚀刻技术，去除垂直表面221以外的衬底上的SiN，仅保留在侧壁的SiN。
在步骤2003，在衬底201上方形成绝缘层，如图2C所示。在衬底上生长绝缘层。在一些实施例中，可以通过晶体生长的方式在整个衬底上201形成绝缘层202。或者，通过沉积绝缘材料然后再减薄，得到所需厚度的绝缘层，形成绝缘层202和203。由于保护层231的存在，垂直界面没有绝缘层的生长。
在步骤2004，去除保护层，如图2D所示。在一些实施例中，通过选择性蚀刻技术，去除侧壁上SiN，使得衬底201的垂直界面221曝露，但同时保留了衬底201的间隔层202和203。
本领域技术人员应当理解，还存在其他技术以在衬底上形成类似结构，并同时曝露衬底的垂直界面。例如，先在具有垂直界面的衬底上形成间隔层，然后图形化该绝缘层露出衬底的垂直界面。
在步骤2005，在衬底201曝露的垂直表面上形成成核层，如图2E所示。
对于Si衬底，一般选择引入成核层204。如本领域技术人员所知，GaN可以直接在Al 2O 3(蓝宝石)、SiC或本征GaN上成核生长。由于晶体质量控制较难，也经常在工艺过程中引入成核层204。在某些情况下，可以不必包括步骤205以引入例如低温GaN或者AlN的成核层204。
因为AlN选区生长能力较弱，所以在间隔层上也可能有一定的生长，这对半导体器件有不利的影响。在一些实施例中，可以在生长AlN后取出晶圆，通过具有各项异性的蚀刻，仅保留垂直面上的AlN成核层而把其他地方的AlN去除，例如，利用垂直向下离子轰击的干法蚀刻。由于垂直表面上的AlN受到的离子轰击较弱而其他面上的AlN受到的轰击较强，这样就可以实现仅保留垂直面上的AlN的目标。
在步骤2006，如图2F所示，在成核层204上形成压电层205。例如，在成核层204上通过外延生长形成压电层205。在一些实施例中，在此之前可以包括，在成核层上形成缓冲层。如前所述，在本发明的半导体器件的结构中，缓冲层并不是必需的。在本质上看，缓冲层和压电层的性质非常接近，甚至可以是同一种材料(如AlN)。或者说，基本的结构是压电层，而在压电层和成核层之间可以有缓冲层。
在步骤2007，如图2G所示，在当前器件结构上方形成支撑层214。在一些实施例中，通过LPCVD沉积支撑层214，形成包覆在压电层205外的支撑层214。
在步骤2008，如图2H所示，图形化压电层右侧的支撑层。在一些实施例中，刻蚀压电层205右侧的支撑层214，仅保留右侧支撑层214少部分结构，以支撑接下来形成的电极结构。
在步骤2009，如图2I所示，形成叉指电极的一个叉指部。在一些实施例中，通过LPCVD沉积金属层，然后图形化该金属层，形成叉指电极的一个叉 指部203。
在步骤2010，如图2J和2K所示，再次沉积支撑层。通过前述方式再次沉积支撑层。
在步骤2011，如图2L所示，图形化支撑层。通过前述方式再次图形化支撑层。此次保留比前次更高的支撑层，高出叉指部的部分为两叉指部之间的距离。
在步骤2012，如图2M所示，形成叉指电极的另一个叉指部。通过前述方式再次形成叉指电极的一个叉指部。
在步骤2013，如图2N～2P所示，形成其他叉指电极的叉指部。通过前述方式再次形成叉指电极的全部叉指部。
在步骤2014，如图2Q所示，形成沉积通道。蚀刻支撑层，形成两条垂直方向的沉积通道217。其中，叉指部的一端曝露在沉积通道217中。
在步骤2015，如图2R所示，形成第一电极的连接部。在一些实施例中，通过LPCVD在沉积通道217中沉积金属层，将叉指部电连接，形成第一电极的连接部。其中，叉指部和连接部形成第一电极207。
在步骤2016，如图2S所示，形成通道支撑层。在一些实施例中，通过LPCVD沉积通道支撑层218。
在步骤2017，如图2T所示，形成第二电极的连接部。在一些实施例中，通过LPCVD在沉积通道217中沉积金属层，将叉指部电连接，形成第二电极的连接部。其中，叉指部和连接部形成第二电极209。需要注意的是，图2T中结构和图1B中结构略有不同，连接部设置在压电层的两侧，而不是压电层正面。其中，连接部的位置可以如图2T所示设置，也可以如图1B所示设置，可视实际需要而选择。在一些实施例中，在步骤2017后，进一步包括：去除支撑层214和通道支撑层218。在一些实施例中，第一电极和第二电极附接在压电层205的第一垂直界面并自支撑于第一垂直界面上。
相较传统的水平结构SAW滤波器，本发明的垂直结构SAW滤波器占用更少的芯片面积，更有利于实现更高的集成度，降低成本，还有利于与其他结构集成。进一步地，本发明的垂直结构SAW滤波器具有更为优良的散热能力，在隔离结构上工艺更加精确和成熟，能够大幅度降低器件的成本。
图3A～3B是根据本发明另一个实施例的表面声波滤波器的结构示意图。如图所示，滤波器包括与图1A和图1B类似结构。与之前的实施例不同，第一电极307和第二电极309由上下排布变成左右排布(如图1B和图3B)。纵向排布的电极需要压电层足够高，但形成高的压电层需要繁复的工艺制程，横向排布的电极可以节省工艺制程，也更利于散热。在一些实施例中，第一电极也可以用作输出电极，第二电极可以用作输入电极。
在一些实施例中，衬底301的下方可以包括导热层。这样，衬底301将位于在压电层305与导热层之间。导热层可以为金属或者石墨烯等高导热材料。在一些实施例中，衬底301经过减薄处理。经过减薄后，衬底301的厚度为0-3000nm之间，从而能够提供更佳的散热能力。
图4是根据本发明一个实施例的具有反射器的表面声波滤波器的结构示意图。相较前述结构，该滤波器在两个电极外侧各增加了一个反射器，分别为第一反射器431和第二反射器432。在器件中传播的机械能，不可避免的会外逸至器件***，尤其是两端。增设第一反射器431和第二反射器432可以有效减少机械能的外逸。
图5A～5C是根据本发明一个实施例的具有外壳的表面声波滤波器的结构示意图。与之前实施例中类似的结构不再赘述。如图所示，器件额外包括一壳层530，壳层530至少囊封压电层505的第一垂直界面。如图5B和5C所示，滤波器包括底层534和壳层530以及在两者之间形成的第一空隙511和第二空隙512。其中，压电层505的第一垂直界面之外包括第一空隙511，压电层505与第一垂直界面相对第二垂直界面544之外包括第二空隙512。
其中，压电层505、第一电极507和第二电极909可以形成在衬底501和壳层530之间并与两者接触，或者形成在底层534和壳层530之间并与两者接触。图5B和图5C是根据本发明另一个实施例滤波器的示意图，其与图5A的滤波器类似，区别在于：衬底501被替换为底层534。图5B和图5C之间的区别在于，压电层505、第一电极507和第二电极909是否仅与底层910接触，而与保护层930不接触。其中，图5C所示的滤波器，压电层505的上方包括第三空隙513。在一些实施例中，第三空隙513可以形成于压电层505下方。
在一些实施例中，底层534可以是衬底或者经过减薄的衬底。在经过减薄的衬底之外可以包括导热层532。在另一些实施例中，底层也可以直接为去除衬底后由高导热材料形成的支撑层，从而提供更好的散热能力。
在本实施例中，压电层505两侧设置的空腔是声波的不良导体。在滤波器工作时，压电层505形成的机械波能够尽量仅在电极507和电极509之间传播。相较传统结构，没有其他寄生波等杂波干扰，滤波效果更好，品质因数更高。
在一些实施例中，形成前述的壳层结构，可以先形成包覆压电层和电极的牺牲层，再在牺牲层外形成包覆牺牲层的壳层。然后在壳层上开孔，通过选择蚀刻的方式，去除牺牲层以形成上述带空隙的壳层结构。本领域技术人员清楚，除本实施例所记载的方法以为，现有技术中还存在其他方法以在压电层的两侧形成空腔，以形成声波反射的结构。这样的方法也同样包括在本发明的范围之中。
图6A是根据本发明另一个实施例的压电层结构的示意图。在本实施例中，在衬底601的垂直界面上形成了缓冲层604。压电层605形成于缓冲层的垂直界面上。与图1A结构的区别在于，在图6A的实施例中，压电层605是沿水平方向生长的，所形成的压电层的晶格一致性更高，器件性能更稳定。
图6B～6C是根据本发明另一个实施例的表面声波滤波器结构的示意图。在图6A所示的压电层结构的基础上，形成了第一叉指电极607和第二叉指电 极609，其中第一叉指电极607在第二叉指电极609的下方。如图所示，第一叉指电极607和所述第二叉指电极609附接在压电层605的垂直界面上并自支撑于该垂直界面上。在一些实施例中，第一叉指电极607和第二叉指电极609能够以与图2所示的实施例类似，通过支撑层形成在压电层605的垂直界面上，然而通过去除支撑层而附接并自支撑于该垂直界面上。在本实施例中，如图所示，第一叉指电极607和第二叉指电极609的宽度可以略宽于压电层605的垂直界面的宽度。在一些情况下，第一叉指电极607和第二叉指电极609可以少量延伸到压电层605与该垂直界面相邻的两个侧面上。进一步地，第一叉指电极607和第二叉指电极609可以分别在压电层605的下方和上方形成电互联。
图6D是根据本发明另一个实施例的表面声波滤波器结构的示意图。与图6B和6C所示的实施例的区别在于，在本实施例中包括了外壳630。第一叉指电极607可以分别向下延伸穿过衬底601并延伸到衬底601之外，在压电层605的下方形成电互联。第二叉指电极609可以分别向上延伸穿过外壳630的顶层部分并延伸到外壳630之外，在压电层630的上方形成电互联。由于滤波器的电互联分别形成在压电层605的下方和上方，能够进一步减少干扰，提高器件的性能。
图7A是根据本发明另一个实施例的表面声波滤波器的结构示意图。与之前实施例中类似的结构不再赘述。在本实施例中的视角为从表面声波滤波器包括叉指电极的垂直界面的另一面的角度。这样更有利于说明两个表面声波滤波器的集成。在本实施例中，表面声波滤波器包括衬底701、经由衬底701的垂直界面生长的压电层705。压电层705被分开形成两个独立的压电层7051和7052。第一组第一叉指电极707和第二叉指电极709，其位于压电层7051的垂直界面上；第二组第一叉指电极706和第二叉指电极708，其位于压电层7052的垂直界面上；从而形成两个独立的表面声波滤波器。第一组叉指电极和第二组叉指电极可以具有不同的间距，从而能够响应于不同的频率。第一组叉指电 极和第二组叉指电极分别延伸至外壳730之上和衬底701之下，从而在压电层7051和7052的上方和下方分别形成电互联。由此，可以将两个表面声波滤波器集成在同一衬底上。
图7B是根据本发明另一个实施例的表面声波滤波器的结构示意图。与之前实施例中类似的结构不再赘述。本实施例与图7A所示的实施例的区别在于，压电层7051和7052是分别从衬底701的两个垂直界面上分别生长形成的，而不是同一压电层经分离形成的。
本领域技术人员理解，以同样的方式可以将多个相同或不同频率的滤波器集成在单片上，这些滤波器共享同一衬底或支撑层。在一些实施例中，这些滤波器形成的滤波器组能够形成不同配置的滤波器网络。
另一个方面，图7A和7B的实施例中滤波器的连接部形成在叉指部之外并且不与压电层相接触。这样形成的电极，压电层表面仅包括叉指部，整体结构更均匀。
图8A～图8B是根据本发明一个实施例的表面声波滤波器的电连接方式示意图。其中，图8A示出滤波器之间通过并联方式连接，图8B示出滤波器之间通过串联方式连接。在一些实施例中，图8A和图8B中所示滤波器，可以将两个以上器件设置在同一壳层内，也可以设置在不同的壳层内。
如以上实施例所示，第一电极和第二电极可以分别由上方或下方引出。在一些实施例中，其中第一电极和所述第二电极也可以同时在所述压电层上方或所述压电层的下方实现电互联。这样的互联方式也同样在本发明的范围之中。
图9A～图9C是表面声波滤波器网络拓扑配置的示意图。图9A是一种梯形拓扑配置，是一种非平衡拓扑结构。图9B是一种晶格形拓扑配置，一种平衡拓扑结构。图9C是一种梯形-晶格形拓扑配置。不同的拓扑结构各有优缺点，为了获得所需带宽，分流元件被调整到比分压元件更低的频率，带外抑制由元件数量和静电容分压器决定。针对所需的抑制功能，可以选择最为合适的拓扑 结构。如本领域技术人员所理解的，本发明的滤波器组可以在同一芯片上实现梯形、晶格形以及梯形-晶格形拓扑配置的滤波器网络。
如本领域技术人员所理解的，根据如前所述的实施例所说明的表面声波滤波器能够形成例如图9A～图9C的滤波器网络，形成梯形配置、晶格配置、或梯形-晶格配置。这样的滤波器网络包括多个如前述的滤波器；并且这些可以滤波器集成在单片上。例如这些滤波器可以共享同一衬底或支撑层。
如本领域技术人员所理解的，根据如前所述的实施例所说明的表面声波滤波器能够形成一种半导体器件，其包括一个或多个如前述的滤波器或者一个或多个如前述的滤波器网络；以及一个或多个晶体管；其中所述一个或多个如前述的滤波器或者一个或多个如前述的滤波器网络以及一个或多个晶体管集成在单片上。这些如前述的滤波器或者一个或多个如前述的滤波器网络以及一个或多个晶体管共享同一衬底或支撑层。在一些实施例中，一个或多个晶体管可以包括HEMT或者HHMT。在一些实施例中，其中所述HEMT或者HHMT包括垂直设置的沟道层和沟道提供层。
如本领域技术人员理解，本发明多个相同或不同频率的滤波器能够与其他晶体管(如HEMT)等半导体元件集成在单片上。这些滤波器、晶体管等半导体元件共享同一衬底或支撑层，能够形成高度集成化的半导体器件。
上述实施例仅供说明本发明之用，而并非是对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明范围的情况下，还可以做出各种变化和变型，因此，所有等同的技术方案也应属于本发明公开的范畴。

Claims (24)

  1. 一种表面声波滤波器，包括：
    压电层，其经配置以将机械能和电能相互转换；
    其中，所述压电层包括第一垂直界面，第一电极和第二电极设置在所述第一垂直界面上，所述第一电极与所述压电层形成欧姆接触，经配置以接收电信号；所述第二电极与所述压电层形成欧姆接触，经配置以输出电信号；其中，所述第一电极与所述第二电极为叉指电极。
  2. 根据权利要求1所述的滤波器，其中压电层材料为AlN、钽酸锂、ZnO、PZT中的至少一者。
  3. 根据权利要求1所述的滤波器，进一步包括衬底，其包括垂直界面，所述压电层经所述垂直界面外延生长形成。
  4. 根据权利要求3所述的滤波器，其中衬底是Si衬底，其垂直界面是Si(111)面；其中衬底是Al 2O 3蓝宝石衬底，其垂直界面是Al 2O 3的(0001)面；其中衬底是SiC衬底，其垂直界面是SiC的(0001)或(000-1)面；或者，其中衬底是GaN本征衬底，其垂直界面是GaN本征衬底的(0001)面或(000-1)面。
  5. 根据权利要求3所述的滤波器，进一步包括导热层，其中所述衬底在所述压电层与所述导热层之间。
  6. 根据权利要求3所述的滤波器，其中所述衬底经过减薄处理；或者所述衬底的厚度为0-3000nm。
  7. 根据权利要求3所述的滤波器，其中所述衬底的所述垂直界面与所述压电层之间包括缓冲层。
  8. 根据权利要求7所述的滤波器，其中所述压电层设置在所述缓冲层的上方。
  9. 根据权利要求1所述的滤波器，其中所述第一电极和所述第二电极附接在所述压电层的所述第一垂直界面并自支撑于所述第一垂直界面上。
  10. 根据权利要求1所述的滤波器，其中所述第一垂直界面上所述第一电极与所述第二电极之外分别包括第一声波反射器和第二声波反射器。
  11. 根据权利要求1所述的滤波器，进一步包括外壳，其至少囊封所述压电层的所述第一垂直界面。
  12. 根据权利要求11所述的滤波器，其中所述压电层的所述第一垂直界面之外包括第一空隙。
  13. 根据权利要求11所述的滤波器，其中所述压电层的与所述第一垂直界面相对第二垂直界面之外包括第二空隙。
  14. 根据权利要求11所述的滤波器，其中所述压电层的上方或下方包括第三空隙。
  15. 根据权利要求1所述的滤波器，其中所述第一电极和所述第二电极在所述压电层上方或所述压电层的下方实现电互联。
  16. 根据权利要求1所述的滤波器，其中所述第一电极和所述第二电极分别在所述压电层上方和下方实现电互联。
  17. 根据权利要求1所述的滤波器，其中所述第一电极和所述第二电极分别在所述压电层的所述第一垂直界面的左方和右方实现电互联。
  18. 一种滤波器网络，包括：
    多个如权利要求1-17任一所述的滤波器；其中所述多个如权利要求1-17任一所述的滤波器集成在单片上。
  19. 根据权利要求18所述的滤波器网络，其中所述多个如权利要求1-17任一所述的滤波器共享同一衬底或支撑层。
  20. 根据权利要求18所述的滤波器网络，其中所述多个如权利要求1-17任一所述的滤波器形成梯形配置、晶格配置、或梯形-晶格配置。
  21. 一种半导体器件，包括：
    一个或多个如权利要求1-17任一所述的滤波器或者一个或多个如权利要求18-20任一所述的滤波器网络；以及
    一个或多个晶体管；
    其中所述一个或多个如权利要求1-17任一所述的滤波器或者一个或多个如权利要求18-20任一所述的滤波器网络以及一个或多个晶体管集成在单片上。
  22. 根据权利要求21所述的半导体器件，其中所述一个或多个如权利要求1-17任一所述的滤波器或者一个或多个如权利要求18-20任一所述的滤波器网络以及一个或多个晶体管共享同一衬底或支撑层。
  23. 根据权利要求21所述的半导体器件，其中所述一个或多个晶体管包括HEMT或者HHMT。
  24. 根据权利要求21所述的半导体器件，其中所述HEMT或者HHMT包括垂直设置的沟道层和沟道提供层。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4564782A (en) * 1983-09-02 1986-01-14 Murata Manufacturing Co., Ltd. Ceramic filter using multiple thin piezoelectric layers
JP2005303893A (ja) * 2004-04-15 2005-10-27 Seiko Epson Corp 共振子型ｓａｗフィルタ
JP2014236430A (ja) * 2013-06-04 2014-12-15 京セラ株式会社 圧電振動素子ならびにそれを用いた圧電振動装置および携帯端末
CN113328723A (zh) * 2021-06-16 2021-08-31 中国科学院上海微***与信息技术研究所 一种弹性波谐振器及其制备方法
CN215871344U (zh) * 2021-07-01 2022-02-18 开元通信技术（厦门）有限公司 一种声波器件以及一种滤波装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4564782A (en) * 1983-09-02 1986-01-14 Murata Manufacturing Co., Ltd. Ceramic filter using multiple thin piezoelectric layers
JP2005303893A (ja) * 2004-04-15 2005-10-27 Seiko Epson Corp 共振子型ｓａｗフィルタ
JP2014236430A (ja) * 2013-06-04 2014-12-15 京セラ株式会社 圧電振動素子ならびにそれを用いた圧電振動装置および携帯端末
CN113328723A (zh) * 2021-06-16 2021-08-31 中国科学院上海微***与信息技术研究所 一种弹性波谐振器及其制备方法
CN215871344U (zh) * 2021-07-01 2022-02-18 开元通信技术（厦门）有限公司 一种声波器件以及一种滤波装置

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