WO2023197123A1 - 电子源芯片及其制作方法、电子设备 - Google Patents

电子源芯片及其制作方法、电子设备 Download PDF

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Publication number
WO2023197123A1
WO2023197123A1 PCT/CN2022/086191 CN2022086191W WO2023197123A1 WO 2023197123 A1 WO2023197123 A1 WO 2023197123A1 CN 2022086191 W CN2022086191 W CN 2022086191W WO 2023197123 A1 WO2023197123 A1 WO 2023197123A1
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WIPO (PCT)
Prior art keywords
tip
substrate
electron source
driving circuit
metal
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PCT/CN2022/086191
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English (en)
French (fr)
Inventor
肖祥
何正宇
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华为技术有限公司
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Priority to PCT/CN2022/086191 priority Critical patent/WO2023197123A1/zh
Publication of WO2023197123A1 publication Critical patent/WO2023197123A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J19/00—Details of vacuum tubes of the types covered by group H01J21/00

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to an electron source chip, a manufacturing method thereof, and electronic equipment.
  • the electron source chip is a device that generates and emits electrons.
  • the electron source chip includes a tip unit and a driving circuit unit.
  • the tip unit controls the voltage applied to the electrode of the tip unit through the driving circuit unit, so that the tip unit emits electrons to meet the needs of various application scenarios, such as vacuum tube devices, Scientific instruments, medical devices, aerospace equipment, materials characterization and semiconductor equipment, etc.
  • This application provides an electron source chip, a manufacturing method thereof, and electronic equipment, which are used to solve the problem that the current electron source chip is not compatible with high voltage and can be used in high-voltage scenarios, and to improve the reliability and stability of the electron source chip.
  • this application provides an electron source chip.
  • the electron source chip includes a driving circuit unit and a tip unit.
  • the driving circuit unit includes a first substrate, a driving circuit provided on one side of the first substrate, and connection contacts provided on the driving circuit.
  • the tip unit includes a second substrate and a tip structure disposed on the second substrate.
  • the driving circuit unit is stacked on the tip unit, and the driving circuit in the driving circuit unit faces the tip unit, and the connection contacts on the driving circuit are electrically connected to the tip structure.
  • the driving circuit unit and the tip unit of the electron source chip use different substrates, that is, the first substrate and the second substrate are respectively used.
  • the drive circuit unit is stacked on the tip structure, and the connection contact of the drive circuit is electrically connected to the tip structure, so that the drive circuit can apply a voltage to the tip structure, causing the tip structure to generate an electric field, so that the tip structure emits electrons.
  • the drive circuit and the needle tip structure are respectively arranged on different substrates. Good electrical isolation can be achieved between the drive circuit and the needle tip structure to avoid the high voltage of the needle tip structure from affecting the drive circuit.
  • the driving circuit and the tip structure are respectively set on different substrates, and the driving circuit can be manufactured separately, so that the driving circuit can choose more circuit structures to meet the needs of more scenarios, such as selecting a high-voltage device that can drive higher voltages. circuit etc.
  • connection contacts of the drive circuit are arranged on a side of the drive circuit away from the first substrate, and the connection contacts of the drive circuit are in contact with the tip structure.
  • the first substrate of the driving circuit is equivalent to covering the driving circuit, which can protect the driving circuit and prevent the electrons emitted from the tip structure from rebounding after collision with the external structure and causing bombardment to the driving circuit. and charging effect, so as to avoid affecting the normal work and operation of the drive circuit.
  • the above-mentioned electron source chip may further include a first dielectric layer.
  • the first dielectric layer is located between the tip structure and the drive circuit, except for the area where the connection contacts of the drive circuit are in contact with the tip structure. In this way, electrical isolation between the drive circuit and the tip structure can be achieved to prevent the tip high voltage from affecting the operation of the drive circuit, thereby further enabling the electron source chip to be used in scenarios where high voltage electrons are emitted.
  • the tip structure may include a tip metal layer and a first metal electrode located on a side of the tip metal layer away from the second substrate, and the tip metal layer has a metal tip protruding in a tip shape.
  • the first metal electrode has a hollow structure, and the hollow structure of the first metal electrode is located above the metal needle tip.
  • the connection contact of the driving circuit can be in contact with the tip metal layer to achieve electrical connection, so that the driving circuit applies a voltage to the tip metal layer, causing a voltage difference to be formed between the tip metal layer and the first metal electrode, thereby generating an electric field.
  • the metal tip on the tip metal layer emits electrons outward under the action of the electric field.
  • the above-mentioned needle tip structure may also include a second dielectric layer.
  • the second dielectric layer is located between the tip metal layer and the first metal electrode, in an area far away from the metal tip. In this way, electrical isolation between the tip metal layer and the first metal electrode can be achieved through the second dielectric layer.
  • the tip structure may further include a second metal electrode and a third dielectric layer; the second metal electrode is located on a side of the first metal electrode away from the second substrate.
  • the second metal electrode has a hollow structure, and the hollow structure of the second metal electrode is located above the metal needle tip.
  • the third dielectric layer is located between the second metal electrode and the first metal electrode, in a region of the hollow structure away from the second metal electrode.
  • the second metal electrode has a flat structure. After the first metal electrode is provided with a flat structure, it can be processed more easily, and the first metal electrode is not easily damaged, thereby improving the structural stability and reliability of the electron source chip.
  • the first metal electrode has a flat structure.
  • the second metal electrode After the second metal electrode is provided with a flat structure, it can be processed more easily, and the second metal electrode is not easily damaged, thereby improving the structural stability and reliability of the electron source chip.
  • the above electron source chip may also include an intermediate metal layer.
  • the intermediate metal layer is located between the tip structure and the second substrate.
  • the intermediate metal layer can increase the adhesion between adjacent hierarchical structures (such as the tip metal layer and the second substrate) to improve the stability of each hierarchical structure in the electron source chip.
  • a plurality of tip structures are provided on the second substrate, and each tip structure is connected to a driving circuit.
  • the electron source chip can emit multiple electron beams to meet the application scenarios of multiple electron beams, and each tip structure can be controlled by an independent drive circuit, making the electron source chip more flexible in emitting electrons.
  • the above electron source chip may further include a fourth dielectric layer.
  • the fourth dielectric layer is located between the tip structure and the second substrate. In this way, the second substrate and the tip structure can be completely isolated through the fourth dielectric layer to avoid electrical connection between multiple tip structures through the substrate, thereby improving the performance and reliability of the electron source chip.
  • isolation grooves are provided between adjacent needle tip structures. In this way, electrical isolation between different tip structures can be achieved.
  • the present application provides an electronic device.
  • the electronic device includes a circuit board and the electron source device in any possible implementation solution of the first aspect.
  • the electron source device is arranged on the circuit board and is electrically connected to the circuit board.
  • this application provides a method for manufacturing an electron source chip.
  • the manufacturing method includes: manufacturing one or more driving circuits on one side of the third substrate, and the connection contacts of the driving circuits are located on the side of the driving circuit away from the third substrate.
  • a tip structure is made, and the connection contacts of the driving circuit are connected to the tip structure.
  • the fourth substrate is bonded on a side of the tip structure away from the third substrate.
  • the third substrate is thinned, and the tip structure is exposed through a photolithography process and an etching process.
  • fabricating the tip structure on the side of the third substrate where the driving circuit is fabricated may include etching to obtain one or more tapered grooves on the side of the third substrate where the driving circuit is fabricated.
  • a first dielectric layer is formed on the surface of the third substrate and the tapered groove, and the connection contacts of the driving circuit are exposed.
  • a tip metal layer is formed on the connection contact point between the first dielectric layer and the driving circuit, and the tip metal layer is connected to the connection contact point of the driving circuit.
  • fabricating the tip structure on the side of the third substrate where the drive circuit is fabricated may also include: forming isolation grooves on the tip metal layer between adjacent tapered grooves.
  • the manufacturing method may further include: forming a second dielectric layer and a first metal electrode on the exposed tip structure, so that the second dielectric layer is located between the tip metal layer and the first metal electrode.
  • the manufacturing method may further include: forming a third dielectric layer and a second metal electrode on a side of the first metal electrode away from the second dielectric layer, so that the third dielectric layer is located between the first metal electrode and the second metal electrode. between electrodes.
  • the driving circuit is processed first and then the needle tip is processed during the manufacturing process, which can avoid damaging the needle tip during the processing and improve the yield and reliability of the electron source chip.
  • the connection between the drive circuit and the tip structure does not require the through silicon via (TSV) process, making the manufacturing process simpler.
  • the tip structure (i.e., the tip metal layer and the metal tip on it) is realized using a molding process, that is, a groove is first dug on the substrate (i.e., the third substrate) to form a tapered groove, and then the tapered groove is formed in the tapered groove.
  • Backfill metal backfill metal can use physical vapor deposition (PVD) or chemical vapor deposition (chemical vapor deposition, CVD) and other processes.
  • refractory metals such as molybdenum (Mo), tungsten (W), etc.
  • Mo molybdenum
  • W tungsten
  • any of the manufacturing methods and electronic devices of the electron source chip provided above can be implemented by the corresponding electron source chip provided above, or related to the corresponding electron source chip provided above. Therefore, the beneficial effects it can achieve can be referred to the beneficial effects in the electron source chip provided above, and will not be described again here.
  • Figure 1 is a schematic structural diagram of an active driving electron source chip in the prior art
  • Figure 2A is a schematic structural diagram of an electronic device
  • Figure 2B is a schematic structural diagram of a vacuum tube device
  • Figure 3A is a side structural cross-sectional view of the electron source chip provided by the embodiment of the present application.
  • Figure 3B is a top view of the electron source chip shown in Figure 3A;
  • Figure 4 is a second cross-sectional view of the side structure of the electron source chip provided by the embodiment of the present application.
  • Figure 5A is a side structural cross-sectional view three of the electron source chip provided by the embodiment of the present application.
  • Figure 5B is a top view of the electron source chip shown in Figure 5A;
  • Figure 6 is a side structural cross-sectional view 4 of the electron source chip provided by the embodiment of the present application.
  • Figure 7 is a cross-sectional view 5 of the side structure of the electron source chip provided by the embodiment of the present application.
  • Figure 8 is a cross-sectional view 6 of the side structure of the electron source chip provided by the embodiment of the present application.
  • Figure 9 is a cross-sectional view of the side structure of the electron source chip provided by the embodiment of the present application.
  • Figure 10 is a flow chart of a method for manufacturing an electron source chip provided by an embodiment of the present application.
  • Figure 11 is a schematic diagram of the structure formed by executing S1001 in Figure 10;
  • Figure 12 is a schematic diagram of the structure after etching to form a tapered groove on the structure shown in Figure 11;
  • Figure 13 is a schematic diagram of the structure after depositing the first dielectric layer on the structure shown in Figure 12;
  • Figure 14 is a schematic diagram of the structure after depositing a tip metal layer on the structure shown in Figure 13;
  • Figure 15 is a schematic diagram of the structure after depositing the tip metal layer and the metal layer on the structure shown in Figure 13;
  • Figure 16 is a schematic diagram 2 of the structure after depositing the tip metal layer and the metal layer on the structure shown in Figure 13;
  • Figure 17 is a schematic structural diagram after etching and forming isolation trenches on the structure shown in Figure 14;
  • Figure 18 is a schematic structural diagram after bonding the fourth substrate to the structure shown in Figure 17;
  • Figure 19 is a schematic structural diagram after thinning the third substrate on the structure shown in Figure 18;
  • Figure 20 is a schematic diagram of the structure after etching and exposing the tip structure on the structure shown in Figure 19;
  • Figure 21 is a schematic structural diagram after forming a second dielectric layer and a first metal electrode on the structure shown in Figure 20;
  • FIG. 22 is a schematic structural diagram after forming a third dielectric layer and a second metal electrode on the structure shown in FIG. 21 .
  • At least one refers to one or more, and “plurality” refers to two or more.
  • And/or describes the association of associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural.
  • At least one of the following or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items).
  • At least one of a, b or c can represent: a, b, c, a-b, a-c, b-c or a-b-c, where a, b and c can be single or multiple.
  • the character "/" generally indicates that the related objects are in an "or” relationship.
  • words such as “first” and “second” do not limit the number and execution order.
  • connection should be understood in a broad sense.
  • connection can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection or a detachable connection. Can be connected indirectly through intermediaries.
  • electrical connection may be a direct electrical connection or an indirect electrical connection through an intermediary.
  • Embodiments of the present application provide an electronic device, which may be vacuum tube devices, scientific instruments, medical equipment, aerospace equipment, material characterization and semiconductor equipment, etc.
  • the embodiments of the present application do not place special restrictions on the specific forms of the above-mentioned electronic devices.
  • the electronic device 01 may include a printed circuit board (PCB) and an electron source chip 10 disposed on the PCB.
  • the above-mentioned electron source chip 10 may be a chip with the function of generating and emitting electrons.
  • the vacuum tube device is an electronic device that generates current conduction in an airtight closed container and uses the effect of the electric field on the electron flow in the vacuum to obtain signal amplification or oscillation.
  • the vacuum tube device includes an electron source chip 10 , a signal input interface 20 , a signal processing chip 30 , a signal output interface 40 and an electron collection chip 50 .
  • the signal processing chip 30 can receive the electrons emitted by the electron source chip 10 and the radio frequency signal input by the signal input interface 20, so that energy exchange occurs between the radio frequency signal and the electrons, thereby amplifying the radio frequency signal, and then through the signal output interface 40 output enhanced RF signal.
  • the electrons processed by the signal processing chip 30 can also be recovered by the electron collection chip.
  • the above-mentioned electron source chip 10 includes a driving circuit unit 100 and a tip unit 200 .
  • the driving circuit unit 100 is used to control the voltage applied to the electrodes of the tip unit 200, so that the tip unit 200 emits electrons.
  • the driving circuit unit 100 includes a first substrate 101 , a driving circuit 102 provided on one side of the first substrate 101 , and a connection contact 103 provided on the driving circuit 102 .
  • the tip unit 200 includes a second substrate 201 and a tip structure 202 disposed on the second substrate 201 .
  • the driving circuit unit 100 is stacked on the tip unit 200, and the driving circuit 102 in the driving circuit unit 100 faces the tip unit 200.
  • the connection contacts 103 on the driving circuit 102 are electrically connected to the tip structure 202. In this way, when the driving circuit 102 and the tip structure 202 are electrically connected, the driving circuit 102 can apply a voltage to the tip structure 202 to generate an electric field in the tip structure 202, so that the tip structure 202 emits electrons.
  • the driving circuit 102 and the tip structure 202 are respectively provided on different substrates.
  • the driving circuit unit 100 can be fabricated first, and then the tip unit 200 can be fabricated.
  • the driving circuit 102 can be directly manufactured on a substrate, so that the manufacturing of the driving circuit 102 is not affected by the manufacturing process of the tip structure 202. Therefore, the driving circuit 102 can choose more complex circuit structures. To meet the needs of more scenarios, for example, you can choose high-voltage circuits that can drive higher voltages.
  • the above-mentioned driving circuit 102 may be a complementary metal oxide semiconductor (CMOS) circuit based on a silicon substrate, or may be other special process circuits, such as III-V compound semiconductor circuits and IV main group circuits.
  • Element semiconductor circuit CMOS
  • III-V compound semiconductor circuits refer to compound semiconductor circuits composed of main group III elements and main group V elements in the periodic table of elements, such as gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP )wait.
  • Group IV element semiconductor circuits may specifically include silicon carbide (SiC), diamond (diamond) and other circuit structures.
  • the material of the first substrate 101 may be silicon (Si), silicon carbide (SiC), glass (glass) and other materials.
  • the thickness of the first substrate 101 may be between 1 micron (um) and 50 micron.
  • the material of the second substrate 201 may be silicon (Si), silicon carbide (SiC), sapphire (sapphire), quartz (quartz), spinel (spinel), glass (glass), Alumina and other materials.
  • the thickness of the second substrate 201 may be between 500 microns and 675 microns.
  • connection contacts 103 on the drive circuit 102 may be disposed on a side of the drive circuit 102 away from the first substrate 101 , with the connection contacts 103 on the drive circuit 102 facing the tip structure 202 , and making the connection contacts of the drive circuit 102 The point 103 is in contact with the tip structure 202, thereby realizing the electrical connection between the driving circuit 102 and the tip structure 202. In this way, space can be saved more and the size of the electron source chip can be made smaller.
  • the first substrate 101 of the driving circuit 102 is equivalent to covering the driving circuit 102 .
  • the first substrate 101 in the drive circuit unit 100 covers the drive circuit 102, which can protect the drive circuit 102 and prevent the electrons emitted from the tip structure 202 from rebounding after collision with the external structure, causing bombardment to the drive circuit 102. and charging effect, so as to avoid affecting the normal work and operation of the driving circuit 102.
  • the above-mentioned electron source chip 10 may also include a first dielectric layer 301.
  • the first dielectric layer 301 is located between the tip structure 202 and the driving circuit 102 , except for the area where the connecting contact 103 contacts the tip structure 202 .
  • the first dielectric layer 301 can be a hierarchical structure composed of any material such as silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (AL 2 O 3 ), etc. It can also be a composite dielectric material layer composed of the above materials.
  • the thickness of the first dielectric layer 301 may be between 100 nanometers and 5 micrometers.
  • the first dielectric layer is made of insulating material, which can be used to achieve electrical isolation between the driving circuit 102 and the tip structure 202 to prevent the tip high voltage from affecting the operation of the driving circuit 102, thereby further enabling the electron source chip to be used in high-voltage applications. A scene where voltage emits electrons.
  • the connection contacts of the driving circuit 102 also need to be in contact with the tip structure 202. Therefore, when making the first dielectric layer 301, a contact hole can be formed at the position of the connection contact 103 of the driving circuit 102, and the tip structure 202 can form a contact boss made of the same material as the tip structure 202 at the position of the contact hole. The contact boss is inserted into the contact hole of the first dielectric layer 301, so that the tip structure 202 comes into contact with the connection contact 103 of the driving circuit 102 to achieve electrical connection.
  • connection contact 103 on the driving circuit 102 and the tip structure 202 can also be achieved by means of micro-bumps, as shown in Figure 4, such as by providing a micro-bump.
  • the adapter board 104 and the tip structure 202 can be electrically connected to the connection contacts 103 of the drive circuit 102 through the micro-protrusions on the adapter board 104 .
  • the tip structure 202 should have at least two electrodes.
  • the above-mentioned tip structure 202 includes a tip metal layer 2021 and a first metal electrode 2022 located on the side of the tip metal layer 2021 away from the second substrate 201 .
  • the needle tip metal layer 2021 has a metal needle tip 2026 protruding in the shape of a needle tip.
  • the first metal electrode 2022 has a hollow structure, and the hollow structure of the first metal electrode 2022 is located above the metal needle tip 2026 .
  • the tip metal layer 2021 and the first metal electrode 2022 above the tip metal layer 2021 are two electrodes of the tip structure 202 respectively.
  • the connection contact 103 of the driving circuit 102 can be in contact with the tip metal layer 2021 to achieve electrical connection, so that the driving circuit 102 applies a voltage on the tip metal layer 2021 .
  • the first metal electrode 2022 can also be grounded, or the first metal electrode 2022 can be electrically connected to the driving circuit 102 through through silicon via (TSV) technology, so that the driving circuit 102 is also connected to the first metal electrode 2022 Apply voltage.
  • TSV silicon via
  • a voltage difference can be formed between the tip metal layer 2021 and the first metal electrode 2022 to generate an electric field.
  • the metal tip 2026 on the tip metal layer 2021 emits electrons outward under the action of the electric field.
  • the tip metal layer 2021 may have a hierarchical structure composed of any one of metal materials such as molybdenum (Mo), tungsten (W), chromium (Cr), and nickel (Ni), or may be made of the above metals.
  • a composite metal layer composed of multiple materials in the material.
  • the thickness of the tip metal layer 2021 may be between 50 nanometers and 1 micron.
  • the first metal electrode 2022 may be made of one metal material including tungsten (W), chromium (Cr), niobium (Nb), molybdenum (Mo), platinum (Pt), etc., or may be multiple types of the above metal materials. Material composed of composite metal. The thickness of the first metal electrode 2022 may be between 50 nanometers and 500 nanometers.
  • the shape of the first metal electrode 2022 can be similar to the outer contour of the metal tip 2026 on the tip metal layer 2021, that is, having a bent structure as shown in FIG. 3A, so that the electrons emitted by the metal tip 2026 can be converged.
  • the function makes the electron beam emitted by the metal needle tip 2026 more concentrated and has better performance.
  • the hollow structure of the first metal electrode 2022 can be in various shapes such as circles, triangles, quadrilaterals, hexagons, etc. The present application does not specifically limit the shape of the hollow structure of the first metal electrode 2022 . .
  • the above-mentioned tip structure 202 may also include a second dielectric layer 2023 , which is located between the tip metal layer 2021 and the first metal electrode 2022 , in a region far away from the metal tip 2026 .
  • the second dielectric layer 2023 can be a hierarchical structure composed of any material such as silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (AL 2 O 3 ), etc. It can also be a composite dielectric material layer composed of the above materials.
  • the thickness of the second dielectric layer 2023 may be between 100 nanometers and 5 micrometers. In this way, the electrical isolation between the tip metal layer 2021 and the first metal electrode 2022 can be achieved through the second dielectric layer 2023 .
  • the gap between the tip metal layer 2021 and the first metal electrode 2022 is not filled with any material near the tip.
  • the metal tip 2026 on the tip metal layer 2021 can be in a vacuum. environment, thereby causing the metal tip 2026 to emit electrons under the action of the electric field.
  • the tip structure 202 in the electron source chip may also include a second metal electrode 2024 and a third dielectric layer 2025 .
  • the second metal electrode 2024 is disposed on the side of the first metal electrode 2022 away from the second dielectric layer 2023 .
  • the second metal electrode 2024 is also a hollow structure, and the hollow structure of the second metal electrode 2024 is also located above the metal needle tip 2026 .
  • the electrons emitted by the metal tip 2026 can be processed again, that is, by changing the spatial electric field distribution to change the movement trajectory of the electrons, or blocking discrete electrons, thereby producing a convergence effect on the emitted electrons, so as to Improve the concentration of electron beams, thereby improving the electrical performance of the electron source chip.
  • the second metal electrode 2024 may be made of the same metal material as the first metal electrode 2022 , or may be different.
  • the structure of the second metal electrode 2024 may be similar to the structure of the first metal electrode 2022, which will not be described again here.
  • the third dielectric layer 2025 is located between the second metal electrode 2024 and the first metal electrode 2022 in a region away from the hollow structure of the second metal electrode 2024 .
  • the material of the third dielectric layer 2025 can be referred to the second dielectric layer 2023, which will not be described again here. In this way, the electrical isolation between the second metal electrode 2024 and the first metal electrode 2022 can be achieved through the third dielectric layer 2025.
  • both the first metal electrode 2022 and the second metal electrode 2024 may be configured as a flat structure. After the first metal electrode 2022 and the second metal electrode 2024 are arranged into a flat structure, processing can be easier, and the first metal electrode 2022 and the second metal electrode 2024 are not easily damaged, thereby improving the structural stability of the electron source chip. and reliability.
  • the electron source chip 10 may further include an intermediate metal layer 203 .
  • the intermediate metal layer 203 is located between the tip structure 202 and the second substrate 201 , that is, the intermediate metal layer 203 is located between the tip metal layer 2021 of the tip structure 202 and the second substrate 201 .
  • the intermediate metal layer 203 can increase the adhesion between adjacent hierarchical structures (such as the tip metal layer 2021 and the second substrate 201), thereby improving the stability of each hierarchical structure in the electron source chip.
  • the material of the intermediate metal layer 203 can be any one of metal materials such as nickel (Ni), copper (Cu), aluminum (Al), palladium (Pd), titanium nitride (TiN), and tantalum nitride (TaN).
  • the hierarchical structure composed of multiple materials may also be a composite metal layer composed of multiple materials among the above-mentioned metal materials.
  • the material selected for the tip metal layer 2021 is a refractory metal, such as molybdenum (Mo), tungsten (W), etc.
  • Mo molybdenum
  • W tungsten
  • the intermediate metal layer 203 can also be used. To fill and form the metal needle tip 2026, so as to form a stable metal needle tip structure.
  • multiple tip structures 202 may be provided on the second substrate 201 , and each tip structure 202 is connected to a driving circuit 102 .
  • the electron source chip can emit multiple electron beams to meet the application scenario of multiple electron beams, and each tip structure 202 can be controlled by an independent driving circuit 102 to make the electron source chip more flexible in emitting electrons.
  • isolation grooves 204 are provided between adjacent needle tip structures 202. Specifically, as shown in FIGS. 3A, 5A, 6, 7, 8 and 9, the isolation groove 204 is disposed between the tip metal layers 2021 in the adjacent tip structures 202, and the isolation groove 204 is separated from the tip. The upper surface of the metal layer 2021 penetrates to the lower surface of the tip metal layer 2021, so that the two adjacent tip structures 202 are completely isolated without any electrical connection.
  • the isolation trench 204 can be filled with dielectric material to achieve electrical isolation.
  • the isolation groove 204 may not be filled with any dielectric material.
  • the isolation groove 204 is also in a vacuum. In this way, electrical isolation between different tip structures 202 can also be achieved.
  • the electron source chip 10 may further include a fourth dielectric layer 302.
  • the fourth dielectric layer 302 is located between the tip structure 202 and the second substrate 201 , that is, the second substrate 201 and the tip structure 202 are completely isolated through the fourth dielectric layer 302 to avoid passage between the multiple tip structures 202
  • the substrate makes electrical connections, thereby improving the performance and reliability of the electron source chip.
  • FIG. 10 it is a flow chart of a method for manufacturing an electron source chip provided by an embodiment of the present application. This manufacturing method is applicable to any electron source chip shown in FIG. 3A to FIG. 9 .
  • the manufacturing method of the electron source chip includes:
  • one or more driving circuits 102 are fabricated on one side of the third substrate 401, and the connection contacts 103 of the driving circuits 102 are located on the side of the driving circuit 102 away from the third substrate 401.
  • the third substrate 401 may be a silicon-on-insulator (SOI) wafer structure, and may include a silicon substrate, a silicon oxide layer, and a silicon layer sequentially arranged from bottom to top.
  • the driver circuit 102 is fabricated on the silicon layer.
  • the driving circuit 102 may be a CMOS circuit, a III-V compound semiconductor circuit, a high-voltage circuit, or the like. Therefore, the driving circuit 102 can be fabricated on the third substrate 401 according to specific circuit processes, and will not be described one by one here.
  • connection contact 103 connected to the tip metal 2021 is provided on the upper surface of the driving circuit 102, as shown in FIG. 11 .
  • the upper surface of the driving circuit 102 and the upper surface of the third substrate 401 can be made flush.
  • the tip structure 202 involves many structures, making the tip structure 202 in this step refers to making the tip metal layer 2021 in the tip structure 202 .
  • the tip metal layer 2021 has a protruding metal tip 2026 in the shape of a tip.
  • a groove in the shape of the metal tip 2026 can be dug on the third substrate, and then By depositing metal in the hollowed groove, the metal needle tip 2026 can be formed.
  • this step S1002 may include:
  • Step 1 As shown in FIG. 12 , the driver circuit 102 side is fabricated on the third substrate 401 , and one or more tapered grooves 402 are obtained by etching, and the tapered grooves 402 are located on one side of the driver circuit 102 .
  • the tapered groove 402 can be processed by a wet etching process or a dry etching process, and is not specifically limited in the embodiment of the present application.
  • the shape of the tapered groove 402 may be a cone, a quadrangular pyramid, a hexagonal pyramid, or other needle-like shape, and the embodiment of the present application is not particularly limited.
  • Step 2 As shown in Figure 13, a first dielectric layer 301 is formed on the surface of the third substrate 401 and the tapered groove 402, and the connection contacts 103 of the driving circuit 102 are exposed.
  • the processing of the first dielectric layer 301 can adopt a chemical vapor deposition (CVD) process, a thermal oxidation process, etc., and the embodiments of this application are not particularly limited.
  • connection contact 103 of the driving circuit 102 needs to be connected to the tip metal layer 2021 in the tip structure 202, when forming the first dielectric layer 301, the position of the connection contact 103 of the driving circuit 102 should be avoided so that The position above the connection contact 103 is not filled with dielectric material.
  • the first dielectric layer 301 is formed on the surfaces of the third substrate 401 and the tapered groove 402, and then the first dielectric layer 301 above the connection contact 103 is etched away through a photolithography process and an etching process. The connection contacts 103 are exposed.
  • Step 3 As shown in FIG. 14 , a tip metal layer 2021 is formed on the first dielectric layer 301 , and the tip metal layer 2021 is connected to the connection contact 103 on the drive circuit 102 . That is to say, the tip metal layer 2021 not only covers the first dielectric layer 301 , but also fills the area above the connection contact 103 that is not filled with dielectric material, so that the connection contact 103 of the driving circuit 102 and the tip metal layer 2021 contact each other to achieve electrical connection.
  • the processing of the tip metal layer 2021 can adopt a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, an electroplating process, etc., this application
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • electroplating process etc.
  • an intermediate metal layer 203 can be deposited on the tip metal layer 2021 during processing.
  • materials of the middle metal layer 203 and the tip metal layer 2021 please refer to the above structural description of the electron source chip, which will not be described again here.
  • the thickness of the tip metal layer 2021 and the middle metal layer 203 may not be enough to fill the entire Tapered groove 402, so the middle metal layer 203 can be processed into a multi-layer metal, such as the first metal layer 2031 and the second metal layer 2032 shown in Figure 16.
  • the second metal layer 2032 can use some fusible metal to make The second metal layer 2032 can fill the entire tapered groove 402 to smooth the surface of the middle metal layer 203 so that the wafer can be bonded to the surface of the middle metal layer 203 as the second substrate 201 .
  • the electron source chip is required to emit multiple electron beams.
  • multiple tip structures can be provided, and a driving circuit can be configured for each tip structure to drive the tip structure to emit electrons.
  • step S1002 may also include:
  • Step 4 As shown in Figure 17, an isolation groove 204 is formed on the tip metal layer 2021 between adjacent tapered grooves 402.
  • the isolation trench 204 can be formed using a photolithography process, a wet etching process, a dry etching process, etc., and is not particularly limited in the embodiment of the present application.
  • the isolation groove 204 please refer to the relevant description in the above structural description of the electron source chip, which will not be described again here.
  • the tip structure 202 here may refer to the tip metal layer 2021 of the tip structure 202 .
  • the tip metal layer 2021 itself is relatively thick, and the intermediate metal layer 203 does not need to be provided, and the fourth substrate 403 can be bonded on the tip metal layer 2021.
  • the fourth substrate 403 is bonded on the intermediate metal layer 203.
  • the fourth substrate 403 includes a silicon substrate and a silicon oxide layer, and during bonding, the silicon oxide layer is placed close to the tip metal layer 2021.
  • the third substrate 401 is thinned, and the tip structure 202 is exposed through a photolithography process and an etching process.
  • a mask and chemical mechanical polishing (CMP) process can be used to thin the third substrate 401 so that the thickness of the silicon layer above the driving circuit 102 meets the thickness of the first substrate 101 , and use this silicon layer as the first substrate 101.
  • CMP chemical mechanical polishing
  • the entire structure can then be turned over so that the thinned third substrate 401 faces upward.
  • the remaining silicon layer is etched using photolithography and etching processes to form a tip structure 202 with a tapered structure (i.e., The metal needle tip 2026) on the needle tip metal layer 2021 is exposed.
  • S1005 as shown in FIG. 21, form a second dielectric layer 2023 and a first metal electrode 2022 on the exposed tip structure 202, so that the second dielectric layer 2023 is located between the tip metal layer 2021 and the first metal electrode 2022.
  • the exposed needle tip structure 202 is only a part of the needle tip structure 202 , that is, the metal needle tip 2026 on the needle tip metal layer 2021 .
  • the second dielectric layer 2023 can be produced on the exposed metal tip 2026 using a chemical vapor deposition CVD process, a physical vapor deposition PVD process, an atomic layer deposition ALD process or a thermal oxidation process, and then the second dielectric layer 2023 can be formed on the exposed metal tip 2026.
  • the first metal electrode 2022 is formed on the layer 2023 by a physical vapor deposition process PVD, a chemical vapor deposition CVD process or an atomic layer deposition ALD process.
  • the first metal electrode 2022 and the second dielectric layer 2023 can also be processed through photolithography and etching processes to make the metal tip 2026 The top of the tip is exposed, so that when the electron source chip is working, the metal tip 2026 is in a vacuum environment to emit electrons.
  • S1006 as shown in FIG. 22, form a third dielectric layer 2025 and a second metal electrode 2024 on the side of the first metal electrode 2022 away from the second dielectric layer 2023, so that the third dielectric layer 2025 is located between the first metal electrode 2022 and the second metal electrode 2023. between the second metal electrodes 2024.
  • a third dielectric layer 2025 and a second metal electrode 2024 may also be formed on the first metal electrode 2022, and the specific process will not be described again.
  • the driving circuit is processed first and then the needle tip is processed during the manufacturing process, which can avoid damaging the needle tip during the processing and improve the yield and yield of the electron source chip. reliability.
  • the connection between the drive circuit and the tip structure does not require the through silicon via (TSV) process, making the manufacturing process simpler.
  • the tip structure i.e., the tip metal layer and the metal tip on it
  • a molding process that is, a groove is first dug in the substrate (third substrate) , forming a tapered groove, and then backfilling metal in the tapered groove.
  • the backfilling metal can use physical vapor deposition PVD process, chemical vapor deposition CVD process, atomic layer deposition ALD process or electroplating process.
  • refractory metals such as molybdenum (Mo), tungsten (W), etc.
  • Mo molybdenum
  • W tungsten
  • circuits and methods can be implemented in other ways.
  • the circuit embodiments described above are only illustrative.
  • the division of modules or units described is only a logical function division.
  • there may be other division methods, such as multiple units or components. may be combined or may be integrated into another device, or some features may be omitted, or not performed.
  • the units described as separate components may or may not be physically separated.
  • the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place, or they may be distributed to multiple different places. . Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

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Abstract

本申请提供一种电子源芯片及其制作方法、电子设备，涉及半导体技术领域，用于解决目前的电子源芯片不能兼容高压并应用于高压场景的问题。该电子源芯片的驱动电路单元和针尖单元采用不同的衬底，即分别采用第一衬底和第二衬底。驱动电路单元堆叠于针尖单元上，且驱动电路的连接触点与针尖结构电连接，可以使驱动电路对针尖结构中的两个电极施加电压，使针尖结构产生电场，以使针尖结构发射电子。驱动电路和针尖结构分别设置在不同的衬底上，驱动电路单元可以单独制作，使得驱动电路可以选择更多的电路结构，满足更多的场景需求，如可以选择能够驱动更高电压的高压电路等。

Description

电子源芯片及其制作方法、电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种电子源芯片及其制作方法、电子设备。
背景技术
电子源芯片是一种产生和发射电子的器件。通常情况下，电子源芯片包括针尖单元和驱动电路单元，针尖单元通过驱动电路单元控制施加在针尖单元电极上的电压，从而使针尖单元发射电子，满足各种应用场景的需求，如真空管器件、科学仪器、医疗器械、航空航天设备以及材料表征和半导体设备等。
然而，目前的电子源芯片一般采用有源器件驱动电子发射。如图1所示，该电子源芯片的针尖结构(包括针尖003-2和电极003-1)和驱动电路002，针尖结构与驱动电路002之间容易产生较大的串扰，当针尖结构的电压较高时容易影响驱动电路002，使得该电子源芯片中不能兼容高压，并应用在高压场景中。因此，研究出能够应用于高压场景的电子源芯片面临着挑战。
发明内容
本申请提供一种电子源芯片及其制作方法、电子设备，用于解决目前的电子源芯片不能兼容高压并应用于高压场景的问题，并提高电子源芯片的可靠性和稳定性。
第一方面，本申请提供一种电子源芯片。该电子源芯片包括驱动电路单元和针尖单元。驱动电路单元包括第一衬底、设置于第一衬底一侧的驱动电路以及设置于驱动电路上的连接触点。针尖单元包括第二衬底和设置于第二衬底上的针尖结构。驱动电路单元堆叠于针尖单元上，且驱动电路单元中的驱动电路朝向针尖单元，驱动电路上的连接触点与针尖结构电连接。
基于上述电子源芯片，该电子源芯片的驱动电路单元和针尖单元采用不同的衬底，即分别采用第一衬底和第二衬底。驱动电路单元堆叠于针尖结构上，且驱动电路的连接触点与针尖结构电连接，可以使驱动电路对针尖结构施加电压，使针尖结构产生电场，以使针尖结构发射电子。驱动电路和针尖结构分别设置在不同的衬底上，驱动电路和针尖结构之间能够实现很好的电学隔离，避免针尖结构的高压对驱动电路产生影响。此外，驱动电路和针尖结构分别设置在不同的衬底上，驱动电路可以单独制作，使得驱动电路可以选择更多的电路结构，满足更多的场景需求，如可以选择能够驱动更高电压的高压电路等。
进一步地，驱动电路的连接触点设置在驱动电路远离第一衬底的一侧，且驱动电路的连接触点与针尖结构相接触。如此，可以更加节约空间，使电子源芯片的尺寸更小。在此情况下，驱动电路的第一衬底则相当于覆盖在驱动电路之上，可以对驱动电路形成保护作用，避免针尖结构发射出的电子经外部结构碰撞后回弹，对驱动电路造成轰击和荷电作用，从而避免影响驱动电路的正常工作和运行。
进一步地，上述电子源芯片还可以包括第一介质层。该第一介质层位于针尖结构与驱动电路之间，除驱动电路的连接触点与针尖结构相接触的区域外的其他区域。如 此，可以实现驱动电路与针尖结构之间的电学隔离，避免针尖高压影响驱动电路的运行，从而进一步使该电子源芯片能够应用在高电压发射电子的场景。
可选地，针尖结构可以包括针尖金属层和位于针尖金属层远离第二衬底一侧的第一金属电极，针尖金属层上具有呈针尖形状凸起的金属针尖。第一金属电极为中空结构，且第一金属电极的中空结构位于金属针尖的上方。如此，驱动电路的连接触点可以与针尖金属层相接触，实现电学连接，从而使驱动电路在针尖金属层上施加电压，使针尖金属层与第一金属电极之间形成电压差，而产生电场。针尖金属层上的金属针尖在电场的作用下向外发射电子。
进一步地，上述针尖结构还可以包括第二介质层。该第二介质层位于针尖金属层与第一金属电极之间，远离金属针尖的区域。如此，通过第二介质层可以实现针尖金属层与第一金属电极之间的电学隔离。
可选地，针尖结构还可以包括第二金属电极和第三介质层；第二金属电极位于第一金属电极远离第二衬底的一侧。第二金属电极为中空结构，且第二金属电极的中空结构位于金属针尖上方。第三介质层位于第二金属电极与第一金属电极之间，远离第二金属电极的中空结构的区域。如此，通过设置第二金属电极，可以对金属针尖发射的电子再次处理，即通过改变空间电场分布来改变电子的运动轨迹，或阻挡离散的电子，从而对发射的电子产生汇聚作用，以提高电子束的聚集度，进而提升电子源芯片的电学性能。
可选地，第二金属电极为平坦结构。将第一金属电极设置为平坦结构后，能够更易于加工，并且第一金属电极不易被破坏，从而可以提高该电子源芯片的结构稳定性和可靠性。
可选地，第一金属电极为平坦结构。将第二金属电极设置为平坦结构后，能够更易于加工，并且第二金属电极不易被破坏，从而可以提高该电子源芯片的结构稳定性和可靠性。
可选地，上述电子源芯片还可以包括中间金属层。该中间金属层位于针尖结构与第二衬底之间。该中间金属层可以使与之相邻的层级结构(如针尖金属层、第二衬底)之间的附着力增加，以提高电子源芯片中的各层级结构的稳定性。
可选地，第二衬底上设置有多个针尖结构，每个针尖结构均连接一个驱动电路。如此，可以使电子源芯片可以发出多个电子束，满足多电子束的应用场景，并且每个针尖结构可以由独立的驱动电路控制，以使电子源芯片发射电子更加灵活。
可选地，上述电子源芯片还可以包括第四介质层。该第四介质层位于针尖结构与第二衬底之间。如此，可以通过第四介质层实现第二衬底与针尖结构的完全隔离，以避免多个针尖结构之间通过衬底进行电学连接，从而提高电子源芯片的性能和可靠性。
可选地，相邻的针尖结构之间设置有隔离槽。如此，可以实现不同的针尖结构之间的电学隔离。
第二方面，本申请提供一种电子设备。该电子设备包括电路板以及如上第一方面中任一种可能的实现方案中的电子源器件。该电子源器件设置于电路板上，且与电路板电连接。
第三方面，本申请提供一种电子源芯片的制作方法。该制作方法包括：在第三衬 底的一侧制作一个或多个驱动电路，且驱动电路的连接触点位于驱动电路远离第三衬底的一侧。在第三衬底制作驱动电路的一侧，制作针尖结构，且使驱动电路的连接触点与针尖结构相连接。在针尖结构远离第三衬底的一侧键合第四衬底。将第三衬底减薄，通过光刻工艺和刻蚀工艺裸露出针尖结构。
进一步地，在第三衬底制作驱动电路的一侧制作针尖结构，可以包括：在第三衬底制作驱动电路的一侧，刻蚀加工得到一个或多个锥形槽。在第三衬底以及锥形槽的表面，形成第一介质层，且使驱动电路的连接触点裸露在外。在第一介质层和驱动电路的连接触点上，形成针尖金属层，且使针尖金属层与驱动电路的连接触点相连接。
可选地，在第三衬底制作驱动电路的一侧，制作针尖结构，还可以包括：在相邻的锥形槽之间的针尖金属层上，形成隔离槽。
可选地，该制作方法还可以包括：在裸露出的针尖结构上，形成第二介质层和第一金属电极，使第二介质层位于针尖金属层与第一金属电极之间。
可选地，该制作方法还可以包括：在第一金属电极远离第二介质层的一侧，形成第三介质层和第二金属电极，使第三介质层位于第一金属电极与第二金属电极之间。
需要说明的是，针对上述电子源芯片的制作方法，在该制作过程中先加工驱动电路，然后再加工针尖，能够避免在加工过程中损伤针尖，提高电子源芯片的成品率和可靠性。此外，驱动电路与针尖结构的连接无需采用硅通孔(through silicon via，TSV)工艺，制作过程更加简单。
针尖结构(即针尖金属层以及其上的金属针尖)采用模板(molding)工艺实现，即先在衬底(即第三衬底)上挖槽，形成锥形槽，然后再在锥形槽内回填金属，回填金属可以采用物理气相沉积(physical vapor deposition，PVD)或化学气相沉积(chemical vapor deposition，CVD)等工艺方式。如此，通过模板工艺加工针尖结构，可以选择难熔金属，如钼(Mo)、钨(W)等，作为针尖结构的金属材质，以提高针尖结构的稳定性，并且实现过程更加简单，还能够保证针尖结构的均一性。
可以理解地，上述提供的任一种电子源芯片的制作方法、电子设备等，均可以由上文所提供的对应的电子源芯片来实现，或与上文所提供的对应的电子源芯片相关联，因此，其所能达到的有益效果可参考上文所提供的电子源芯片中的有益效果，此处不再赘述。
附图说明
图1为现有技术中有源驱动电子源芯片的结构示意图；
图2A为一种电子设备的结构示意图；
图2B为一种真空管器件的结构示意图；
图3A为本申请实施例提供的电子源芯片的侧面结构剖视图一；
图3B为图3A所示的电子源芯片的俯视图；
图4为本申请实施例提供的电子源芯片的侧面结构剖视图二；
图5A为本申请实施例提供的电子源芯片的侧面结构剖视图三；
图5B为图5A所示的电子源芯片的俯视图；
图6为本申请实施例提供的电子源芯片的侧面结构剖视图四；
图7为本申请实施例提供的电子源芯片的侧面结构剖视图五；
图8为本申请实施例提供的电子源芯片的侧面结构剖视图六；
图9为本申请实施例提供的电子源芯片的侧面结构剖视图七；
图10为本申请实施例提供的一种电子源芯片的制作方法的流程图；
图11为执行图10中的S1001形成的结构的示意图；
图12为在图11所示的结构上刻蚀形成锥形槽后的结构示意图；
图13为在图12所示的结构上沉积第一介质层后的结构示意图；
图14为在图13所示的结构上沉积针尖金属层后的结构示意图；
图15为在图13所示的结构上沉积针尖金属层和金属层后的结构示意图一；
图16为在图13所示的结构上沉积针尖金属层和金属层后的结构示意图二；
图17为在图14所示的结构上刻蚀形成隔离槽后的结构示意图；
图18为在图17所示的结构上键合第四衬底后的结构示意图；
图19为在图18所示的结构上减薄第三衬底后的结构示意图；
图20为在图19所示的结构上刻蚀裸露出针尖结构后的结构示意图；
图21为在图20所示的结构上形成第二介质层和第一金属电极后的结构示意图；
图22为在图21所示的结构上形成第三介质层和第二金属电极后的结构示意图。
附图标记：
01-电子设备；10-电子源芯片；20-信号输入接口；30-信号处理芯片；40-信号输出接口；50-电子收集芯片；001-衬底；002-驱动电路；003-1-电极；003-2-针尖；100-驱动电路单元；200-针尖单元；101-第一衬底；102-驱动电路；103-连接触点；104-转接板；201-第二衬底；202-针尖结构；301-第一介质层；2021-针尖金属层；2022-第一金属电极；2023-第二介质层；2024-第二金属电极；2025-第三介质层；2026-金属针尖；203-中间金属层；204-隔离槽；302-第四介质层；401-第三衬底；402-锥形槽；403-第四衬底；2031-第一金属层；2032-第二金属层。
具体实施方式
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c或a-b-c，其中a、b和c可以是单个，也可以是多个。字符“/”一般表示前后关联对象是一种“或”的关系。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和执行次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在本申请中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连 接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“电连接”可以是直接的电性连接，也可以是通过中间媒介间接的电性连接。
本申请实施例提供一种电子设备，该电子设备可以是真空管器件、科学仪器、医疗器械、航空航天设备以及材料表征和半导体设备等。本申请实施例对上述电子设备的具体形式不做特殊限制。
如图2A所示，该电子设备01可以包括电路板(printed Circuit Board，PCB)以及设置于该PCB上的电子源芯片10。在本申请的一些实施例中，上述电子源芯片10可以是具有产生和发射电子功能的芯片。
以电子设备01为真空管器件为例，真空管器件是一种在气密性封闭容器中产生电流传导，利用电场对真空中的电子流的作用以获得信号放大或振荡的电子器件。如图2B所示，该真空管器件包括电子源芯片10、信号输入接口20、信号处理芯片30、信号输出接口40以及电子收集芯片50。其中，信号处理芯片30可以接收电子源芯片10发射的电子，以及信号输入接口20输入的射频信号，使射频信号与电子之间发生能量交换，实现对射频信号的放大处理，然后通过信号输出接口40输出增强的射频信号。此外，经过信号处理芯片30的处理后的电子还可以通过电子收集芯片回收。
以下对上述电子源芯片10的结构以及制作方法进行举例说明。
在本申请的一些实施例中，如图3A所示，上述电子源芯片10包括驱动电路单元100和针尖单元200。在该电子源芯片中，驱动电路单元100用于控制施加在针尖单元200的电极上的电压，从而使针尖单元200发射电子。具体地，请参考图3A，驱动电路单元100包括第一衬底101、设置于第一衬底101一侧的驱动电路102，以及设置在驱动电路102上的连接触点103。针尖单元200包括第二衬底201和设置于第二衬底201上的针尖结构202。驱动电路单元100堆叠于针尖单元200上，且驱动电路单元100中的驱动电路102朝向针尖单元200，驱动电路102上的连接触点103与针尖结构202电连接。如此，在驱动电路102与针尖结构202电连接的状态下，可以使驱动电路102对针尖结构202施加电压，使针尖结构202产生电场，以使针尖结构202发射电子。
需要说明的是，在图3A所示的电子源芯片中，驱动电路102和针尖结构202分别设置在不同的衬底上，可以先制作驱动电路单元100，然后再制作针尖单元200。在制作驱动电路单元100时，可以直接在一块衬底上制作驱动电路102，使得驱动电路102的制作不受针尖结构202制作工艺的影响，因此该驱动电路102可以选择更多复杂的电路结构，满足更多的场景需求，如可以选择能够驱动更高电压的高压电路等。
示例性地，上述驱动电路102可以是基于硅衬底的互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)电路，也可以是其他特种工艺电路，如III-V族化合物半导体电路、IV主族元素半导体电路。其中，III-V族化合物半导体电路是指元素周期表中III主族元素和V主族元素组成的化合物半导体电路，如氮化镓(GaN)、砷化镓(GaAs)、磷化铟(InP)等。IV主族元素半导体电路，具体可以包括碳化硅(SiC)、金刚石(diamond)等电路结构。
此外，第一衬底101的材质可以由硅(Si)、碳化硅(SiC)以及玻璃(glass)等 材料。第一衬底101的厚度可以在1微米(um)至50微米之间。
第二衬底201的材质可以为硅(Si)、碳化硅(SiC)、蓝宝石(sapphire)、石英(quartz)、尖晶石(spinel)、玻璃(glass)、Alumina等材料。第二衬底201的厚度可以在500微米至675微米之间。
进一步地，驱动电路102上的连接触点103可以设置在驱动电路102远离第一衬底101的一侧，驱动电路102上的连接触点103朝向针尖结构202，并且使驱动电路102的连接触点103与针尖结构202相接触，从而实现驱动电路102与针尖结构202的电学连接。如此，可以更加节约空间，使电子源芯片的尺寸更小。在此情况下，驱动电路102的第一衬底101则相当于覆盖在驱动电路102之上。
应理解，电子源芯片在发射电子时，针尖结构202发射出的电子与外部的其他结构碰撞会回弹。驱动电路单元100中的第一衬底101覆盖在驱动电路102之上，可以对驱动电路102形成保护作用，避免针尖结构202发射出的电子经外部结构碰撞后回弹，对驱动电路102造成轰击和荷电作用，从而避免影响驱动电路102的正常工作和运行。
进一步地，上述电子源芯片10还可以包括第一介质层301。该第一介质层301位于针尖结构202与驱动电路102之间，除连接触点103与针尖结构202相接触的区域外的其他区域。该第一介质层301可以为氧化硅(SiO 2)、氮化硅(SiN x)、氮氧化硅(SiON)和氧化铝(AL 2O 3)等中的任意一种材料构成的层级结构，也可以是由上述材料组成的复合介质材料层。第一介质层301的厚度可以在100纳米到5微米之间。
应理解，第一介质层均采用绝缘材料，可以用于实现驱动电路102与针尖结构202之间的电学隔离，避免针尖高压影响驱动电路102的运行，从而进一步使该电子源芯片能够应用在高电压发射电子的场景。
需要说明的是，由于第一介质层301是为了实现针尖结构202与驱动电路102之间的电学隔离，而驱动电路102的连接触点还需要与针尖结构202相接触。因此，在制作第一介质层301时，可以在驱动电路102的连接触点103位置处形成接触孔，而针尖结构202在接触孔的位置处可以形成与针尖结构202同材质的接触凸台，该接触凸台***第一介质层301的接触孔内，从而使得针尖结构202与驱动电路102的连接触点103相接触而实现电学连接。
此外，驱动电路102上的连接触点103与针尖结构202之间的电学连接，还可以通过微凸台(micro-bump)的方式实现，如图4所示，如通过设置具有微凸台的转接板104，针尖结构202可通过转接板104上的微凸台与驱动电路102的连接触点103实现电学连接。
为了使针尖结构202能够实现电子的发射，并且该针尖结构202能够在驱动电路102的驱动下形成电压差，上述针尖结构202应该具有至少两个电极。具体地，如图3A和图3B所示，上述针尖结构202包括针尖金属层2021和位于针尖金属层2021远离第二衬底201一侧的第一金属电极2022。针尖金属层2021上具有呈针尖形状凸起的金属针尖2026。第一金属电极2022为中空结构，且第一金属电极2022的中空结构位于金属针尖2026上方。
此时，针尖金属层2021和针尖金属层2021上方的第一金属电极2022分别为针尖 结构202的两个电极。驱动电路102的连接触点103可以与针尖金属层2021相接触，实现电学连接，从而使驱动电路102在针尖金属层2021上施加电压。此外，还可以将第一金属电极2022接地，或者将第一金属电极2022通过硅通孔(through silicon via，TSV)技术与驱动电路102实现电学连接，使驱动电路102也对第一金属电极2022施加电压。如此可以使针尖金属层2021与第一金属电极2022之间形成电压差，而产生电场，针尖金属层2021上的金属针尖2026在电场的作用下向外发射电子。
需要说明的是，针尖金属层2021可以为钼(Mo)、钨(W)、铬(Cr)以及镍(Ni)等金属材料中的任意一种材料构成的层级结构，也可以是由上述金属材料中的多种材料构成的复合金属层。针尖金属层2021的厚度可以在50纳米至1微米之间。
第一金属电极2022可以由钨(W)、铬(Cr)、铌(Nb)、钼(Mo)、铂(Pt)等中的一种金属材料构成，也可以是上述金属材料中的多种材料构成的复合金属。第一金属电极2022的厚度可以在50纳米至500纳米之间。
应理解，第一金属电极2022的形状可以与针尖金属层2021上的金属针尖2026的外轮廓类似，即如图3A所示的具有折弯的结构，如此可以对金属针尖2026发射的电子产生汇聚的作用，使金属针尖2026发射的电子束更加聚集，性能更好。
此外，如图3B所示，第一金属电极2022的中空结构可以为圆形、三角形、四边形、六边形等各种形状，本申请对第一金属电极2022的中空结构的形状不做特殊限定。
进一步地，如图3A所示，上述针尖结构202还可以包括第二介质层2023，该第二介质层2023位于针尖金属层2021与第一金属电极2022之间，远离金属针尖2026的区域。该第二介质层2023可以为氧化硅(SiO 2)、氮化硅(SiN x)、氮氧化硅(SiON)和氧化铝(AL 2O 3)等中的任意一种材料构成的层级结构，也可以是由上述材料组成的复合介质材料层。第二介质层2023的厚度可以在100纳米至5微米之间。如此，通过第二介质层2023可以实现针尖金属层2021与第一金属电极2022之间的电学隔离。
需要说明的是，针尖金属层2021与第一金属电极2022之间的间隙在靠近针尖位置不填充任何材料，当整个芯片工作在真空环境中时，针尖金属层2021上的金属针尖2026可以处于真空环境中，从而使金属针尖2026在电场的作用下发射电子。
一些实施例中，如图5A和图5B所示，电子源芯片中的针尖结构202还可以包括第二金属电极2024和第三介质层2025。第二金属电极2024设置于第一金属电极2022远离第二介质层2023的一侧。第二金属电极2024也为中空结构，且第二金属电极2024的中空结构也位于金属针尖2026上方。如此，可以通过设置第二金属电极2024，对金属针尖2026发射的电子再次处理，即通过改变空间电场分布来改变电子的运动轨迹，或阻挡离散的电子，从而对发射的电子产生汇聚作用，以提高电子束的聚集度，进而提升电子源芯片的电学性能。
应理解，第二金属电极2024可以与第一金属电极2022采用相同的金属材质，也可以不同。第二金属电极2024的结构可以与第一金属电极2022的结构类似，此处不再赘述。
第三介质层2025位于第二金属电极2024与第一金属电极2022之间远离第二金属电极2024的中空结构的区域。该第三介质层2025的材质可以参考第二介质层2023，此处不再赘述。如此，可通过第三介质层2025实现第二金属电极2024与第一金属电 极2022之间的电学隔离。
在一些实施例中，如图6和图7所示，第一金属电极2022和第二金属电极2024均可以设置为平坦结构。将第一金属电极2022和第二金属电极2024设置为平坦结构后，能够更易于加工，并且第一金属电极2022和第二金属电极2024不易被破坏，从而可以提高该电子源芯片的结构稳定性和可靠性。
在一些实施例中，如图8和图9所示，电子源芯片10还可以包括中间金属层203。该中间金属层203位于针尖结构202与第二衬底201之间，也即该中间金属层203位于针尖结构202的针尖金属层2021与第二衬底201之间。该中间金属层203可以使与之相邻的层级结构(如针尖金属层2021、第二衬底201)之间的附着力增加，以提高电子源芯片中的各层级结构的稳定性。
其中，中间金属层203的材质可以为镍(Ni)、铜(Cu)、铝(Al)、钯(Pd)、氮化钛(TiN)以及氮化钽(TaN)等金属材料中的任意一种材料构成的层级结构，也可以是由上述金属材料中的多种材料构成的复合金属层。
应理解，当针尖金属层2021选择的材质为难熔金属，如钼(Mo)、钨(W)等，则针尖金属层2021上可能难以形成稳定的金属针尖2026，因而中间金属层203也可以用来填充形成金属针尖2026，以便形成稳定的金属针尖结构。
在一些实施例中，如图3A至图9所示，第二衬底201上可以设置有多个针尖结构202，每个针尖结构202均连接一个驱动电路102。如此，可以使电子源芯片可以发出多个电子束，满足多电子束的应用场景，并且每个针尖结构202可以由独立的驱动电路102控制，以使电子源芯片发射电子更加灵活。
进一步地，为实现不同的针尖结构202之间的电学隔离，相邻的针尖结构202之间设置有隔离槽204。具体地，如图3A、图5A、图6、图7、图8和图9所示，隔离槽204设置在相邻的针尖结构202中的针尖金属层2021之间，并且隔离槽204从针尖金属层2021的上表面贯穿至针尖金属层2021的下表面，使两个相邻的针尖结构202完全隔离，不存在任何电学连接关系。
应理解，在该隔离槽204中可以填充介质材料，以实现电学隔离。当然，该隔离槽204也可以不填充任何介质材料，当电子源芯片在工作时处于真空环境中，该隔离槽204中也为真空，如此也能够实现不同的针尖结构202之间的电学隔离。
此外，为实现不同的针尖结构202之间的电学隔离，电子源芯片10还可以包括第四介质层302。该第四介质层302位于针尖结构202与第二衬底201之间，即通过第四介质层302实现第二衬底201与针尖结构202的完全隔离，以避免多个针尖结构202之间通过衬底进行电学连接，从而提高电子源芯片的性能和可靠性。
另一方面，如图10所示，为本申请实施例提供的一种电子源芯片的制作方法的流程图。该制作方法适用于如图3A至图9所示的任一种电子源芯片。
请参考图10，该电子源芯片的制作方法包括：
S1001，如图11所示，在第三衬底401的一侧制作一个或多个驱动电路102，且驱动电路102的连接触点103位于驱动电路102远离第三衬底401的一侧。
示例性地，第三衬底401可以为绝缘衬底上的硅(silicon-on-insulator，SOI)晶圆结构，可以包括从下到上依次设置的硅衬底、氧化硅层和硅层。驱动电路102加工在 硅层上。
如上述电子源芯片10中的描述，驱动电路102可以是CMOS电路、III-V族化合物半导体电路或高压电路等。因此在第三衬底401上制作驱动电路102可以按照具体的电路工艺进行制作即可，此处不再一一描述。
应理解，为了使驱动电路102能够与针尖结构202中的针尖金属层2021相连接，且不需要额外增加连接结构，如连接线，以节省芯片的空间，可以将驱动电路102上，用于与针尖金属2021相连接的连接触点103，设置在驱动电路102的上表面，如图11所示。
此外，为了便于后续层级结构的制作，可以将驱动电路102的上表面与第三衬底401的上表面制作为齐平的状态。
S1002，在第三衬底401制作驱动电路102的一侧，制作针尖结构202，且使驱动电路102上的连接触点103与针尖结构202相接触。
应理解，由于针尖结构202涉及的结构比较多，因此在此步骤中制作针尖结构202，是指制作针尖结构202中的针尖金属层2021。如上述的电子源芯片，针尖金属层2021上具有呈针尖形状凸起的金属针尖2026，为形成上述的金属针尖2026，可以在第三衬底上挖出一个呈金属针尖2026形状的槽，再在挖空的槽内沉积金属，便可以形成金属针尖2026。具体地，该S1002步骤可以包括：
第一步：如图12所示，在第三衬底401制作驱动电路102一侧，刻蚀加工得到一个或多个锥形槽402，且使锥形槽402位于驱动电路102的一侧。应理解，锥形槽402的加工可以采用湿法刻蚀工艺加工，也可以采用干法刻蚀工艺加工，本申请实施例不做特殊限制。此外，锥形槽402的形状可以是圆锥形、四棱锥型、六棱锥型等类似针尖的形状，本申请实施例也不做特殊限制。
第二步：如图13所示，在第三衬底401以及锥形槽402的表面，形成第一介质层301，且使驱动电路102的连接触点103裸露在外。第一介质层301的加工可以采用化学气相沉积(chemical vapor deposition，CVD)工艺、热氧化工艺等，本申请实施例不做特殊限制。
应理解，由于驱动电路102的连接触点103需要与针尖结构202中的针尖金属层2021连接，因此在形成第一介质层301时，应当避开驱动电路102的连接触点103的位置，使该连接触点103上方的位置没有介质材料填充。或者，在第三衬底401以及锥形槽402的表面均形成第一介质层301，然后再通过光刻工艺和刻蚀工艺将连接触点103上方位置的第一介质层301刻蚀掉，以裸露出连接触点103。
第三步：如图14所示，在第一介质层301上，形成针尖金属层2021，且使针尖金属层2021与驱动电路102上的连接触点103相连接。也就是说，针尖金属层2021不仅覆盖在第一介质层301上，还需填满连接触点103上方的未填充介质材料的区域，以使驱动电路102的连接触点103与针尖金属层2021相接触，而实现电连接。针尖金属层2021的加工可以采用物理气相沉积(physical vapor deposition，PVD)工艺、化学气相沉积(chemical vapor deposition，CVD)工艺、原子层沉积(atomic layer deposition，ALD)工艺、电镀工艺等，本申请实施例不做特殊限制。
需要说明的是，如图15所示，为提高针尖金属层2021与其他层级结构的附着力， 在加工时可以在针尖金属层2021上沉积中间金属层203。中间金属层203以及针尖金属层2021的材质请参考上文关于电子源芯片的结构描述，此处不再赘述。
此外，若针尖金属层2021或中间金属层203选择的材质为一些难熔金属，如钼(Mo)、钨(W)等，针尖金属层2021和中间金属层203的厚度可能不足以填满整个锥形槽402，因此可以将中间金属层203加工为多层金属，如图16所示的第一金属层2031和第二金属层2032，第二金属层2032可以采用一些易熔金属，以使第二金属层2032能够填满整个锥形槽402，使中间金属层203的表面平整，以便在中间金属层203的表面键合晶圆，作为第二衬底201。
在某些应用场景中，需要电子源芯片能够发射出多个电子束。为使电子源芯片发射出多个电子束，可以设置多个针尖结构，并且可以为每个针尖结构配置一个驱动电路，以驱动针尖结构发射电子。在此情况下，为实现不同地针尖结构202之间的电学隔离，该S1002步骤还可以包括：
第四步：如图17所示，在相邻的锥形槽402之间的针尖金属层2021上，形成隔离槽204。隔离槽204的形成可以采用光刻工艺、湿法刻蚀工艺、干法刻蚀工艺等，本申请实施例不做特殊限定。隔离槽204的相关说明请参考上述电子源芯片的结构描述中的相关说明，此处不再赘述。
S1003，如图18所示，在针尖结构202远离第三衬底401的一侧，键合第四衬底403。
应理解，此处的针尖结构202可以指针尖结构202的针尖金属层2021。此时，针尖金属层2021本身比较厚，可以不再设置中间金属层203，则可以在针尖金属层2021上键合第四衬底403。
当然，若在针尖金属层2021上方还沉积有中间金属层203，则在中间金属层203上键合第四衬底403。其中，第四衬底403包括硅衬底和氧化硅层，且在键合时，将氧化硅层靠近针尖金属层2021。
S1004，如图19和图20所示，将第三衬底401减薄，通过光刻工艺和刻蚀工艺裸露出针尖结构202。
完成步骤S1003之后，可以利用掩膜和化学机械抛光(chemical mechanical polishing，CMP)工艺，将第三衬底401减薄，使驱动电路102上方的硅层的厚度，满足第一衬底101的厚度，并将该硅层作为第一衬底101。
然后可以将整个结构翻转，使经过减薄后的第三衬底401朝上。在第三衬底401(即剩余的硅层)上具有锥形槽402的位置处，利用光刻和刻蚀工艺对剩余的硅层进行刻蚀，使具有锥形结构的针尖结构202(即针尖金属层2021上的金属针尖2026)裸露出来。
S1005，如图21所示，在裸露出的针尖结构202上，形成第二介质层2023和第一金属电极2022，使第二介质层2023位于针尖金属层2021与第一金属电极2022之间。
目前，裸露出的针尖结构202只是针尖结构202的一部分，即针尖金属层2021上的金属针尖2026。此时，可以在裸露出的金属针尖2026上，采用化学气相沉积CVD工艺、物理气相沉积PVD工艺、原子层沉积ALD工艺或热氧化工艺，制作出第二介质层2023，然后再在第二介质层2023上通过物理气相沉积工艺PVD、化学气相沉积 CVD工艺或原子层沉积ALD工艺形成第一金属电极2022。
为使第二介质层2023和第一金属电极2022形成图21所示的结构，还可以通过光刻和刻蚀工艺对第一金属电极2022和第二介质层2023进行加工，以使金属针尖2026的顶部裸露出来，从而使电子源芯片在工作时，金属针尖2026处于真空环境中以发射电子。
S1006，如图22所示，在第一金属电极2022远离第二介质层2023的一侧，形成第三介质层2025和第二金属电极2024，使第三介质层2025位于第一金属电极2022与所述第二金属电极2024之间。
与步骤S1005类似，还可以在第一金属电极2022上，形成第三介质层2025和第二金属电极2024，具体过程不再赘述。
需要说明的是，针对图10所示的电子源芯片的制作方法，在该制作过程中先加工驱动电路，然后再加工针尖，能够避免在加工过程中损伤针尖，提高电子源芯片的成品率和可靠性。此外，驱动电路与针尖结构的连接无需采用硅通孔(through silicon via，TSV)工艺，制作过程更加简单。
在图10所示的电子源芯片的制作方法中，针尖结构(即针尖金属层以及其上的金属针尖)采用模板(molding)工艺实现，即先在衬底(第三衬底)上挖槽，形成锥形槽，然后再在锥形槽内回填金属，回填金属可以采用物理气相沉积PVD工艺、化学气相沉积CVD工艺、原子层沉积ALD工艺或电镀工艺等工艺方式。如此，通过模板工艺加工针尖结构，可以选择难熔金属，如钼(Mo)、钨(W)等，作为针尖结构的金属材质，以提高针尖结构的稳定性，并且实现过程更加简单，并且能够保证针尖结构的均一性。
在本申请所提供的几个实施例中，应该理解到，所揭露的电路和方法，可以通过其它的方式实现。例如，以上所描述的电路实施例仅仅是示意性的，例如，所描述的模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是一个物理单元或多个物理单元，即可以位于一个地方，或者也可以分布到多个不同地方。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种电子源芯片，其特征在于，包括驱动电路单元和针尖单元；
    所述驱动电路单元包括第一衬底、设置于所述第一衬底一侧的驱动电路，以及设置于所述驱动电路上的连接触点；
    所述针尖单元包括第二衬底和设置于所述第二衬底上的针尖结构；
    所述驱动电路单元堆叠于所述针尖单元上，且所述驱动电路单元中的所述驱动电路朝向所述针尖单元，所述驱动电路的连接触点与所述针尖结构电连接。
  2. 根据权利要求1所述的电子源芯片，其特征在于，所述驱动电路的连接触点设置在所述驱动电路远离所述第一衬底的一侧，且所述驱动电路的所述连接触点与所述针尖结构相接触。
  3. 根据权利要求2所述的电子源芯片，其特征在于，所述电子源芯片还包括第一介质层，所述第一介质层位于所述针尖单元与所述驱动电路单元之间，除所述驱动电路的连接触点与所述针尖结构相接触的区域外的其他区域。
  4. 根据权利要求1至3任一项所述的电子源芯片，其特征在于，所述针尖结构包括针尖金属层和位于所述针尖金属层远离所述第二衬底一侧的第一金属电极，所述针尖金属层上具有呈针尖形状凸起的金属针尖；
    所述第一金属电极为中空结构，且所述第一金属电极的中空结构位于所述金属针尖的上方。
  5. 根据权利要求4所述的电子源芯片，其特征在于，所述针尖结构还包括第二介质层，所述第二介质层位于所述针尖金属层与所述第一金属电极之间，远离所述金属针尖的区域。
  6. 根据权利要求4或5所述的电子源芯片，其特征在于，所述针尖结构还包括第二金属电极和第三介质层；所述第二金属电极位于所述第一金属电极远离所述第二衬底的一侧；
    所述第二金属电极为中空结构，且所述第二金属电极的中空结构位于所述金属针尖上；
    所述第三介质层位于第二金属电极与所述第一金属电极之间，远离所述第二金属电极的中空结构的区域。
  7. 根据权利要求6所述的电子源芯片，其特征在于，所述第二金属电极为平坦结构。
  8. 根据权利要求4至7任一项所述的电子源芯片，其特征在于，所述第一金属电极为平坦结构。
  9. 根据权利要求1至8任一项所述的电子源芯片，其特征在于，所述电子源芯片还包括中间金属层，所述中间金属层位于所述针尖结构与所述第二衬底之间。
  10. 根据权利要求1至9任一项所述的电子源芯片，其特征在于，所述第二衬底上设置有多个针尖结构，每个所述针尖结构均连接一个驱动电路。
  11. 根据权利要求10所述的电子源芯片，其特征在于，相邻的所述针尖结构之间设置有隔离槽。
  12. 根据权利要求11所述的电子源芯片，其特征在于，所述电子源芯片还包括第四介质层，所述第四介质层位于所述针尖结构与所述第二衬底之间。
  13. 一种电子设备，其特征在于，包括电路板以及如权利要求1至12任一项所述的电子源器件；所述电子源器件设置于所述电路板上，且与所述电路板电连接。
  14. 一种电子源芯片的制作方法，其特征在于，所述制作方法包括：
    在第三衬底的一侧制作一个或多个驱动电路，且所述驱动电路的连接触点位于所述驱动电路远离所述第三衬底的一侧；
    在所述第三衬底制作所述驱动电路的一侧，制作针尖结构，且使所述驱动电路的连接触点与所述针尖结构相连接；
    在所述针尖结构远离所述第三衬底的一侧，键合第四衬底；
    将所述第三衬底减薄，并通过光刻工艺和刻蚀工艺裸露出所述针尖结构。
  15. 根据权利要求14所述的制作方法，其特征在于，所述在所述第三衬底制作所述驱动电路的一侧，制作针尖结构，包括：
    在所述第三衬底制作所述驱动电路的一侧，刻蚀加工得到一个或多个锥形槽，使所述锥形槽位于所述驱动电路的一侧；
    在所述第三衬底以及所述锥形槽的表面，形成第一介质层，且使所述驱动电路的连接触点裸露在外；
    在所述第一介质层和所述驱动电路的连接触点上，形成针尖金属层，且使所述针尖金属层与所述驱动电路的连接触点相连接。
  16. 根据权利要求15所述的制作方法，其特征在于，所述在所述第三衬底制作所述驱动电路的一侧，制作针尖结构，还包括：
    在相邻的所述锥形槽之间的针尖金属层上，形成隔离槽。
  17. 根据权利要求15或16所述的制作方法，其特征在于，所述制作方法还包括：
    在裸露出的所述针尖结构上，形成第二介质层和第一金属电极，使所述第二介质层位于所述针尖金属层与所述第一金属电极之间。
  18. 根据权利要求17所述的制作方法，其特征在于，所述制作方法还包括：
    在所述第一金属电极远离所述第二介质层的一侧，形成第三介质层和第二金属电极，使所述第三介质层位于所述第一金属电极与所述第二金属电极之间。
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US5939833A (en) * 1996-12-21 1999-08-17 Electronics And Telecommunications Research Institute Field emission device with low driving voltage
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