WO2023124582A1

WO2023124582A1 - Circuit board integrated inductor, inductor, and electronic device

Info

Publication number: WO2023124582A1
Application number: PCT/CN2022/131515
Authority: WO
Inventors: 蓝昊; 陈奕君; 徐峰
Original assignee: Oppo广东移动通信有限公司
Priority date: 2021-12-30
Filing date: 2022-11-11
Publication date: 2023-07-06

Abstract

The present application provides a circuit board integrated inductor, an inductor, and an electronic device. The circuit board integrated inductor comprises: a circuit board, a coil being embedded in the circuit board; a magnetic adhesive layer, which is provided on at least one side of the two opposite sides of the circuit board, and at least partially overlaps with the coil; and a magnetic film layer, which is provided on the side of the magnetic adhesive layer away from the circuit board, wherein the magnetic conductivity of the magnetic film layer is greater than that of the magnetic adhesive layer. According to the circuit board integrated inductor in the present application, the inductor is integrated in the circuit board, so that more ultrathin and miniaturized properties are achieved, and packaging efficiency is improved; in addition, the magnetic adhesive layer and the magnetic film layer are combined together to serve as a magnetic layer in the circuit board integrated inductor, so that an inductance value of the obtained circuit board integrated inductor far exceeds the accumulated value of the inductance of the independent magnetic adhesive layer and the inductance of the independent magnetic film layer, and the ultrathin property and high-sensitivity can be better achieved.

Description

电路板集成电感、电感及电子设备Circuit board integrated inductor, inductor and electronic equipment

技术领域technical field

本申请涉及电子领域，具体涉及一种电路板集成电感、电感及电子设备。The present application relates to the field of electronics, in particular to a circuit board integrated inductor, inductor and electronic equipment.

背景技术Background technique

随着电子硬件的小型化和高密度发展趋势，电路板的表面积急剧减少，但板面上要求贴装的电子元件却有增无减。电感是电子设备不可缺少的元器件，当前的电感大多先制备成电感器后，再贴装至电路板上，这不仅占用了电路板的面积，还需要分立贴装，降低封装效率。With the miniaturization and high-density development trend of electronic hardware, the surface area of the circuit board has been reduced sharply, but the electronic components required to be mounted on the board have not decreased. Inductance is an indispensable component of electronic equipment. Most of the current inductors are prepared as inductors and then mounted on the circuit board. This not only occupies the area of the circuit board, but also requires discrete mounting, which reduces packaging efficiency.

发明内容Contents of the invention

针对上述问题，本申请第一方面实施例提供了一种电路板集成电感，其包括：In view of the above problems, the embodiment of the first aspect of the present application provides a circuit board integrated inductor, which includes:

电路板，所述电路板嵌设有线圈；A circuit board, the circuit board is embedded with a coil;

磁胶层，所述磁胶层设置于所述电路板相背的两侧中的至少一侧上，且与所述线圈至少部分交叠；以及a magnetic glue layer, the magnetic glue layer is disposed on at least one of the two opposite sides of the circuit board, and at least partially overlaps the coil; and

磁膜层，所述磁膜层设置于所述磁胶层背离所述电路板的一侧，其中，所述磁膜层的磁导率大于所述磁胶层的磁导率。A magnetic film layer, the magnetic film layer is disposed on a side of the magnetic glue layer away from the circuit board, wherein the magnetic permeability of the magnetic film layer is greater than that of the magnetic glue layer.

本申请第二方面实施例提供一种电感，其包括：The embodiment of the second aspect of the present application provides an inductor, which includes:

线圈层，所述线圈层具有线圈；a coil layer having coils;

磁胶层，所述磁胶层设置于所述线圈层相背两侧中的至少一侧上；以及a magnetic glue layer, the magnetic glue layer is disposed on at least one of the opposite sides of the coil layer; and

磁膜层，所述磁膜层设置于所述磁胶层背离所述线圈层的一侧，其中，所述磁膜层的磁导率大于所述磁胶层的磁导率。A magnetic film layer, the magnetic film layer is disposed on a side of the magnetic glue layer away from the coil layer, wherein the magnetic permeability of the magnetic film layer is greater than that of the magnetic glue layer.

本申请第三方面实施例提供一种电子设备，其特征在于，所述电子设备包括本申请实施例所述的电路板集成电感，或者，包括本申请实施例所述的电感。The embodiment of the third aspect of the present application provides an electronic device, which is characterized in that the electronic device includes the circuit board integrated inductor described in the embodiment of the present application, or includes the inductor described in the embodiment of the present application.

附图说明Description of drawings

为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the accompanying drawings that need to be used in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. Those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort.

图1是本申请一实施例的电路板集成电感的透视结构示意图。FIG. 1 is a schematic perspective view of a circuit board integrated inductor according to an embodiment of the present application.

图2是本申请一实施例的电路板集成电感沿图1中A-A方向的剖视结构示意图。FIG. 2 is a schematic cross-sectional structural diagram of a circuit board integrated inductor along the direction A-A in FIG. 1 according to an embodiment of the present application.

图3是本申请又一实施例的电路板集成电感沿图1中A-A方向的剖视结构示意图。FIG. 3 is a schematic cross-sectional structure diagram of a circuit board integrated inductor according to another embodiment of the present application along the direction A-A in FIG. 1 .

图4是本申请一实施例的电路板的结构示意图。FIG. 4 is a schematic structural diagram of a circuit board according to an embodiment of the present application.

图5是本申请又一实施例的电路板沿图1中A-A方向的剖视结构示意图。FIG. 5 is a schematic cross-sectional structure diagram of a circuit board along the direction A-A in FIG. 1 according to another embodiment of the present application.

图6是本申请又一实施例的电路板的结构示意图。FIG. 6 is a schematic structural diagram of a circuit board according to another embodiment of the present application.

图7是本申请又一实施例的电路板沿图1中A-A方向的剖视结构示意图。FIG. 7 is a schematic cross-sectional structure diagram of a circuit board along the direction A-A in FIG. 1 according to another embodiment of the present application.

图8是本申请又一实施例的电路板的结构示意图。FIG. 8 is a schematic structural diagram of a circuit board according to another embodiment of the present application.

图9是本申请又一实施例的线圈的结构示意图。Fig. 9 is a schematic structural diagram of a coil according to another embodiment of the present application.

图10是本申请又一实施例的电路板的结构示意图。FIG. 10 is a schematic structural diagram of a circuit board according to another embodiment of the present application.

图11是本申请一实施例的电路板集成电感的电路框图。FIG. 11 is a circuit block diagram of a circuit board integrated inductor according to an embodiment of the present application.

图12是本申请一实施例的磁膜层的结构示意图。FIG. 12 is a schematic structural diagram of a magnetic film layer according to an embodiment of the present application.

图13是本申请又一实施例的磁膜层的结构示意图。FIG. 13 is a schematic structural diagram of a magnetic film layer according to another embodiment of the present application.

图14是本申请又一实施例的电路板集成电感沿图1中A-A方向的剖视结构示意图。FIG. 14 is a schematic cross-sectional structure diagram of a circuit board integrated inductor according to another embodiment of the present application along the direction A-A in FIG. 1 .

图15是本申请一实施例的电路板集成电感的制备方法流程示意图。FIG. 15 is a schematic flowchart of a method for manufacturing a circuit board integrated inductor according to an embodiment of the present application.

图16是本申请一实施例的电路板的制备方法流程示意图。FIG. 16 is a schematic flowchart of a method for preparing a circuit board according to an embodiment of the present application.

图17是本申请一实施例的第一基板的结构示意图。FIG. 17 is a schematic structural diagram of a first substrate according to an embodiment of the present application.

图18是本申请又一实施例的电路板的制备方法流程示意图。FIG. 18 is a schematic flowchart of a method for preparing a circuit board according to another embodiment of the present application.

图19是本申请又一实施例的电路板的制备方法流程示意图。FIG. 19 is a schematic flowchart of a method for preparing a circuit board according to another embodiment of the present application.

图20是本申请一实施例的第二基板的结构示意图。FIG. 20 is a schematic structural diagram of a second substrate according to an embodiment of the present application.

图21是本申请一实施例的电路板集成电感的制备方法流程示意图。FIG. 21 is a schematic flowchart of a method for manufacturing a circuit board integrated inductor according to an embodiment of the present application.

图22是本申请一实施例的电感的结构示意图。FIG. 22 is a schematic structural diagram of an inductor according to an embodiment of the present application.

图23是本申请一实施例的电感沿图22中B-B方向的剖视的结构示意图。FIG. 23 is a schematic structural diagram of the cross-section of the inductor according to an embodiment of the present application along the B-B direction in FIG. 22 .

图24是本申请又一实施例的电感沿图22中B-B方向的剖视的结构示意图。FIG. 24 is a schematic structural diagram of a cross-section of an inductor according to another embodiment of the present application along the B-B direction in FIG. 22 .

图25是本申请一实施例的电源管理芯片的电路框图。FIG. 25 is a circuit block diagram of a power management chip according to an embodiment of the present application.

图26是本申请一实施例的电子设备的结构示意图。FIG. 26 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

图27是本申请一实施例的电子设备的部分***结构示意图。Fig. 27 is a schematic diagram of a partial exploded structure of an electronic device according to an embodiment of the present application.

图28是本申请一实施例的电子设备的电路框图。Fig. 28 is a circuit block diagram of an electronic device according to an embodiment of the present application.

图29是本申请一实施例的电子设备的部分***结构示意图。Fig. 29 is a schematic diagram of a partial exploded structure of an electronic device according to an embodiment of the present application.

图30是本申请一实施例的电子设备的电路框图。FIG. 30 is a circuit block diagram of an electronic device according to an embodiment of the present application.

图31是本申请一实施例的电子设备的部分***结构示意图。Fig. 31 is a schematic diagram of a partial exploded structure of an electronic device according to an embodiment of the present application.

图32是本申请一实施例的电子设备的电路框图。FIG. 32 is a circuit block diagram of an electronic device according to an embodiment of the present application.

附图标记说明：Explanation of reference signs:

100-电路板集成电感，10-电路板，11-线圈，12-介电层，14-导电层，14a-导线，10a-基板，10b-功能电路，11b-处理器，13b-存储器，20-磁胶层，30-磁膜层，31-磁膜子层，33-金属氧化物层，35-绝缘子层，50-绝缘层，10’-第一基板，11’-导体层，10”-第二基板，101-第一过孔，400-电感，410-线圈层，430-衬底，500-电源管理芯片，510-电源电路，600-电子设备，610-显示组件，620-中框，630-壳体，631-透光部，650-摄像头模组，700-电子设备，710-显示组件，730-壳体，740-电路板组件；800-电子设备，810-显示组件，830-壳体，840-电路板组件。100-circuit board integrated inductor, 10-circuit board, 11-coil, 12-dielectric layer, 14-conductive layer, 14a-wire, 10a-substrate, 10b-functional circuit, 11b-processor, 13b-memory, 20 -Magnetic glue layer, 30-Magnetic film layer, 31-Magnetic film sublayer, 33-Metal oxide layer, 35-Insulator layer, 50-Insulation layer, 10'-First substrate, 11'-Conductor layer, 10" -second substrate, 101-first via hole, 400-inductor, 410-coil layer, 430-substrate, 500-power management chip, 510-power circuit, 600-electronic equipment, 610-display component, 620-middle frame, 630-housing, 631-light-transmitting part, 650-camera module, 700-electronic equipment, 710-display assembly, 730-housing, 740-circuit board assembly; 800-electronic equipment, 810-display assembly, 830-housing, 840-circuit board assembly.

具体实施方式Detailed ways

第一方面，本申请提供一种电路板集成电感，其包括：In a first aspect, the present application provides a circuit board integrated inductor, which includes:

磁膜层，所述磁膜层设置于所述磁胶层背离所述电路板的一侧，A magnetic film layer, the magnetic film layer is arranged on the side of the magnetic glue layer away from the circuit board,

其中，所述磁膜层的磁导率大于所述磁胶层的磁导率。Wherein, the magnetic permeability of the magnetic film layer is greater than the magnetic permeability of the magnetic glue layer.

其中，所述磁胶层包括树脂及磁性颗粒，所述磁性颗粒分散于所述树脂中；在所述磁胶层中，所述磁性颗粒的重量分数的范围为85％至95％；所述磁性颗粒的D90粒径的范围为1μm≤D90≤10μm。Wherein, the magnetic glue layer includes resin and magnetic particles, and the magnetic particles are dispersed in the resin; in the magnetic glue layer, the weight fraction of the magnetic particles ranges from 85% to 95%; the The range of D90 particle size of the magnetic particles is 1 μm≤D90≤10 μm.

其中，所述树脂包括环氧树脂、聚氨酯及丙烯酸酯中的至少一种；所述磁性颗粒包括铁氧体颗粒、磁性金属颗粒、磁性合金颗粒中的至少一种；所述铁氧体包括MnZn铁氧体、NiZn铁氧体中的至少一种；所述磁性金属颗粒包括铁、钴、镍中的至少一种；所述磁性合金颗粒包括铁基晶态合金、铁基非晶合金、钴基非晶合金中的至少一种；所述铁基晶态合金包括FeNi合金、FeCo合金、FeAl合金、FeSiAl合金、FeNiMo合金、FeC合金中的至少一种；所述铁基非晶合金包括FeSiB合金、FeB合金、FeNiPB合金、FeNiMoB合金中的至少一种；所述钴基非晶合金包括CoFeSiB合金、CoFeCrSiB合金、CoNiFeSiB合金中的至少一种。Wherein, the resin includes at least one of epoxy resin, polyurethane and acrylate; the magnetic particles include at least one of ferrite particles, magnetic metal particles, and magnetic alloy particles; the ferrite includes MnZn At least one of ferrite and NiZn ferrite; the magnetic metal particles include at least one of iron, cobalt, and nickel; the magnetic alloy particles include iron-based crystalline alloys, iron-based amorphous alloys, cobalt At least one of the base amorphous alloys; the iron-based crystalline alloys include at least one of FeNi alloys, FeCo alloys, FeAl alloys, FeSiAl alloys, FeNiMo alloys, and FeC alloys; the iron-based amorphous alloys include FeSiB alloy, FeB alloy, FeNiPB alloy, and FeNiMoB alloy; the cobalt-based amorphous alloy includes at least one of CoFeSiB alloy, CoFeCrSiB alloy, and CoNiFeSiB alloy.

其中，所述电路板集成电感还包括绝缘层，所述绝缘层设置于所述线圈与所述磁胶层之间。Wherein, the circuit board integrated inductor further includes an insulating layer, and the insulating layer is arranged between the coil and the magnetic glue layer.

其中，所述磁膜层包括磁性金属、磁性合金中的至少一种；所述磁性金属包括铁、钴、镍中的至少一种；所述磁性合金包括铁基晶态合金、铁基非晶合金、钴基非晶合金中的至少一种；所述铁基晶态合金包括FeNi合金、FeCo合金、FeAl合金、FeSiAl合金、FeNiMo合金、FeC合金中的至少一种；所述铁基非晶合金包括FeSiB合金、FeB合金、FeNiPB合金、FeNiMoB合金中的至少一种；所述钴基非晶合金包括CoFeSiB合金、CoFeCrSiB合金、CoNiFeSiB合金中的至少一种。Wherein, the magnetic film layer includes at least one of magnetic metals and magnetic alloys; the magnetic metals include at least one of iron, cobalt, and nickel; the magnetic alloys include iron-based crystalline alloys, iron-based amorphous At least one of alloys and cobalt-based amorphous alloys; the iron-based crystalline alloys include at least one of FeNi alloys, FeCo alloys, FeAl alloys, FeSiAl alloys, FeNiMo alloys, and FeC alloys; the iron-based amorphous alloys The alloy includes at least one of FeSiB alloy, FeB alloy, FeNiPB alloy, and FeNiMoB alloy; the cobalt-based amorphous alloy includes at least one of CoFeSiB alloy, CoFeCrSiB alloy, and CoNiFeSiB alloy.

其中，沿所述电路板、所述磁胶层及所述磁膜层的层叠方向，所述磁胶层的厚度h1的范围为50μm≤h1≤500μm，所述磁膜层的厚度h2的范围为5μm≤h2≤35μm。Wherein, along the stacking direction of the circuit board, the magnetic glue layer and the magnetic film layer, the thickness h1 of the magnetic glue layer is in the range of 50 μm≤h1≤500 μm, and the thickness h2 of the magnetic film layer is in the range of 5μm≤h2≤35μm.

其中，所述电路板包括至少一层介电层及至少一层导电层；所述介电层与所述导电层依次交替层叠设置，所述导电层包括导线；当所述导电层为一层时，单层所述导电层的所述导线形成所述线圈；所述导电层为多层时，任意相邻的两层导电层的导线电连接，形成所述线圈。Wherein, the circuit board includes at least one dielectric layer and at least one conductive layer; the dielectric layer and the conductive layer are stacked alternately in sequence, and the conductive layer includes wires; when the conductive layer is a layer When the conductive layer is single-layer, the wires form the coil; when the conductive layer is multi-layered, the wires of any two adjacent conductive layers are electrically connected to form the coil.

其中，所述磁膜层包括改性磁性合金，所述改性磁性合金包括铬掺杂的铁镍合金、铬掺杂的铁钴合金、铬掺杂的铁硅铝合金中的至少一种。Wherein, the magnetic film layer includes a modified magnetic alloy, and the modified magnetic alloy includes at least one of chromium-doped iron-nickel alloy, chromium-doped iron-cobalt alloy, and chromium-doped sendust.

其中，所述磁膜层包括依次交替层叠设置的磁膜子层及金属氧化物层，所述磁膜子层为所述改性磁性合金层，所述金属氧化物层包括所述改性磁性合金中的至少一种金属的氧化物。Wherein, the magnetic film layer includes magnetic film sublayers and metal oxide layers alternately stacked in sequence, the magnetic film sublayer is the modified magnetic alloy layer, and the metal oxide layer includes the modified magnetic film layer. Oxides of at least one metal in the alloy.

其中，所述磁膜层包括依次交替层叠设置的绝缘子层及磁膜子层，所述绝缘子层包括二氧化硅、氧化铝中的至少一种，所述磁膜子层包括改性磁性合金。Wherein, the magnetic film layer includes insulating sublayers and magnetic film sublayers alternately stacked in sequence, the insulating sublayers include at least one of silicon dioxide and aluminum oxide, and the magnetic film sublayers include modified magnetic alloys.

其中，所述磁膜层的等效电导率σ的范围为4KS/m≤σ≤600KS/m；所述磁膜层的相对磁导率μr的范围为500≤μr≤6000。Wherein, the range of the equivalent electrical conductivity σ of the magnetic film layer is 4KS/m≤σ≤600KS/m; the range of the relative permeability μr of the magnetic film layer is 500≤μr≤6000.

第二方面，本申请提供一种电感，其包括：In a second aspect, the present application provides an inductor, which includes:

线圈层，所述线圈层具有线圈；a coil layer having coils;

磁膜层，所述磁膜层设置于所述磁胶层背离所述线圈层的一侧，a magnetic film layer, the magnetic film layer is disposed on the side of the magnetic glue layer away from the coil layer,

其中，所述磁胶层包括树脂及磁性颗粒，所述磁性颗粒分散于所述树脂中；在所述磁胶层中，所述磁性颗粒的重量分数的范围为85％至95％；所述磁性颗粒的D90粒径的范围为1μm≤D90≤10μm；所述树脂包括环氧树脂、聚氨酯及丙烯酸酯中的至少一种；所述磁性颗粒包括铁氧体颗粒、磁性合金颗粒中的至少一种；所述铁氧体颗粒包括MnZn铁氧体、NiZn铁氧体中的至少一种；所述磁性合金颗粒包括铁基晶态合金、铁基非晶合金、钴基非晶合金中的至少一种；所述铁基晶态合金为FeNi；所述铁基非晶合金包括FeSiAl合金、FeSiB合金中的至少一种；所述钴基非晶合金包括CoFeSiB合金、CoFeCrSiB合金中的至少一种。Wherein, the magnetic glue layer includes resin and magnetic particles, and the magnetic particles are dispersed in the resin; in the magnetic glue layer, the weight fraction of the magnetic particles ranges from 85% to 95%; the The range of the D90 particle size of the magnetic particles is 1 μm≤D90≤10 μm; the resin includes at least one of epoxy resin, polyurethane and acrylate; the magnetic particles include at least one of ferrite particles and magnetic alloy particles The ferrite particles include at least one of MnZn ferrite and NiZn ferrite; the magnetic alloy particles include at least one of iron-based crystalline alloys, iron-based amorphous alloys, and cobalt-based amorphous alloys. One; the iron-based crystalline alloy is FeNi; the iron-based amorphous alloy includes at least one of FeSiAl alloy and FeSiB alloy; the cobalt-based amorphous alloy includes at least one of CoFeSiB alloy and CoFeCrSiB alloy .

其中，所述电感还包括绝缘层，所述绝缘层设置于所述线圈层与所述磁胶层之间。Wherein, the inductor further includes an insulating layer, and the insulating layer is disposed between the coil layer and the magnetic glue layer.

其中，所述磁膜层包括铁氧体、磁性合金中的至少一种；所述铁氧体包括MnZn铁氧体、NiZn铁氧体中的至少一种；所述磁性合金包括铁基晶态合金、铁基非晶合金、钴基非晶合金中的至少一种；所述铁基晶态合金为FeNi；所述铁基非晶合金包括FeSiAl合金、FeSiB合金中的至少一种；所述钴基非晶合金包括CoFeSiB合金、CoFeCrSiB合金中的至少一种。Wherein, the magnetic film layer includes at least one of ferrite and magnetic alloy; the ferrite includes at least one of MnZn ferrite and NiZn ferrite; the magnetic alloy includes iron-based crystalline At least one of alloys, iron-based amorphous alloys, and cobalt-based amorphous alloys; the iron-based crystalline alloy is FeNi; the iron-based amorphous alloy includes at least one of FeSiAl alloys and FeSiB alloys; the The cobalt-based amorphous alloy includes at least one of CoFeSiB alloy and CoFeCrSiB alloy.

其中，沿所述线圈层、所述磁胶层及所述磁膜层的层叠方向，所述磁胶层的厚度h1的范围为50μm≤h1≤500μm，所述磁膜层的厚度h2的范围为5μm≤h2≤35μm。Wherein, along the stacking direction of the coil layer, the magnetic glue layer and the magnetic film layer, the thickness h1 of the magnetic glue layer is in the range of 50 μm≤h1≤500 μm, and the thickness h2 of the magnetic film layer is in the range of 5μm≤h2≤35μm.

第三方面，本申请提供一种电子设备，所述电子设备包括第一方面任一项所述的电路板集成电感，或者包括第二方面任一项所述的电感。In a third aspect, the present application provides an electronic device, which includes the circuit board integrated inductor described in any one of the first aspect, or includes the inductor described in any one of the second aspect.

为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiment of the application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the application. Obviously, the described embodiment is only It is a part of the embodiments of this application, but not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何的变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、***、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其他步骤或单元。The terms "first", "second" and the like in the specification and claims of the present application and the above drawings are used to distinguish different objects, rather than to describe a specific order. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally further includes For other steps or units inherent in these processes, methods, products or devices.

下面将结合附图，对本申请实施例中的技术方案进行描述。需要说明的是，为便于说明，在本申请的实施例中，相同的附图标记表示相同的部件，并且为了简洁，在不同实施例中，省略对相同部件的详细说明。The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings. It should be noted that, for ease of description, in the embodiments of the present application, the same reference numerals represent the same components, and for the sake of brevity, in different embodiments, detailed descriptions of the same components are omitted.

电感由线圈与磁性件组成，当线圈中通过交流电流时，在线圈的内部及其周围产生交变磁通，拥有储存和释放能量的功能，在电子线路中，电感对交流有限流作用，它与电阻器或电容器能组成高通滤波器或低通滤波器、移相电路及谐振电路，因此广泛应用于各类仪器及设备中。The inductance is composed of a coil and a magnetic part. When an alternating current passes through the coil, an alternating magnetic flux is generated inside and around the coil, which has the function of storing and releasing energy. It can form high-pass filter or low-pass filter, phase-shifting circuit and resonant circuit with resistor or capacitor, so it is widely used in various instruments and equipment.

电感器件在电路板上占用了较大的面积，例如在电源模块中，电感器件所占用电源板表面40％以上的面积，这不仅不利于产品的小型化和高密度化；且大部分电感器件都需要分立贴装，降低封装效率。The inductance device occupies a large area on the circuit board. For example, in the power module, the inductance device occupies more than 40% of the surface area of the power board, which is not conducive to the miniaturization and high density of the product; and most inductance devices Both require discrete mounting, which reduces packaging efficiency.

电感中采用磁膜作为磁性层时，由于磁膜的相对磁导率较高(磁膜的相对磁导率Ur通常为900至1000)，磁感线在磁膜中分布十分集中，电感容易达到磁饱和而失去实用性。如果要增加磁膜的饱和磁感应强度，可以通过增厚来提高磁膜的饱和磁感应强度，然而，磁膜厚度的增加会带来高频磁损提升、器件总厚度增厚等一系列副作用。此外，由于集肤效应，当磁膜增加到一定厚度后，即使磁膜厚度再增加，电感的感量的提升也很有限，这降低了磁膜的利用率。When the magnetic film is used as the magnetic layer in the inductor, since the relative magnetic permeability of the magnetic film is relatively high (the relative magnetic permeability Ur of the magnetic film is usually 900 to 1000), the distribution of the magnetic field lines in the magnetic film is very concentrated, and the inductance is easy to reach Magnetically saturated and loses practicality. If you want to increase the saturation magnetic induction of the magnetic film, you can increase the saturation magnetic induction of the magnetic film by thickening it. However, the increase in the thickness of the magnetic film will bring about a series of side effects such as increased high-frequency magnetic loss and increased device thickness. In addition, due to the skin effect, when the magnetic film is increased to a certain thickness, even if the thickness of the magnetic film is increased, the increase in the inductance of the inductance is very limited, which reduces the utilization rate of the magnetic film.

电感中采用磁胶作为磁性层时，由于磁胶的磁导率很低，与真空状态及绝缘材料的磁导率接近(磁胶的相对磁导率约为10至15，真空和绝缘材料的磁导率为1)，电感不容易出现磁饱和的现象，但是由于磁导率过低，要达到一定的感量，需要非常大的磁胶厚度才能实现，不仅使得电感的体积增大，不利于电感的集成化、小型化，而且也难以应用于柔性电路板(FPC)中。When the magnetic glue is used as the magnetic layer in the inductor, because the magnetic permeability of the magnetic glue is very low, it is close to the magnetic permeability of the vacuum state and the insulating material (the relative permeability of the magnetic glue is about 10 to 15, and the vacuum and insulating material The magnetic permeability is 1), and the inductor is not prone to magnetic saturation. However, because the magnetic permeability is too low, a very large thickness of the magnetic glue is required to achieve a certain inductance, which not only increases the volume of the inductor, but also does not It is beneficial to the integration and miniaturization of inductors, and it is also difficult to apply to flexible circuit boards (FPC).

请参见图1、图2及图3，本申请实施例提供一种电路板集成电感100，其应用于电子设备例如手机、平板电脑等中，本申请的电子设备以手机为例进行示意，不应该理解为对本申请保护范围的限制。本实施例的电路板集成电感100包括：电路板10、磁胶层20及磁膜层30。电路板10嵌设有线圈11；磁胶层20设置于电路板10相背的两侧中的至少一侧上，且与线圈11至少部分交叠；磁膜层30设置于磁胶层20背离电路板10的一侧，其中，磁膜层30的磁导率大于磁胶层20的磁导率。Please refer to Fig. 1, Fig. 2 and Fig. 3. The embodiment of the present application provides a circuit board integrated inductor 100, which is applied to electronic devices such as mobile phones and tablet computers. It should be understood as a limitation on the protection scope of this application. The circuit board integrated inductor 100 of this embodiment includes: a circuit board 10 , a magnetic glue layer 20 and a magnetic film layer 30 . The circuit board 10 is embedded with a coil 11; the magnetic glue layer 20 is arranged on at least one of the opposite sides of the circuit board 10, and at least partially overlaps with the coil 11; the magnetic film layer 30 is arranged on the magnetic glue layer 20 away from On one side of the circuit board 10 , the magnetic permeability of the magnetic film layer 30 is greater than that of the magnetic glue layer 20 .

电路板10可以为柔性电路板(FPC)，也可以为印制电路板(PCB)，对此本申请不作具体限定。电路板10上的线圈11的数量可以为一个，也可以为多个，例如，可以为但不限于为1个、2个、3个等，线圈11的具体数量可以根据实际应用需求进行设定，本申请不作具体限定。多个指两个以上或大于等于两个。The circuit board 10 may be a flexible circuit board (FPC), or a printed circuit board (PCB), which is not specifically limited in this application. The number of coils 11 on the circuit board 10 can be one or multiple, for example, but not limited to 1, 2, 3, etc. The specific number of coils 11 can be set according to actual application requirements , this application does not specifically limit. Multiple refers to two or more or greater than or equal to two.

可以理解，每个线圈11可以为但不限于为一匝线圈中的一部分(例如半匝线圈、0.3匝线圈等)、一匝线圈、两匝线圈、三匝线圈、四匝线圈、五匝线圈等。线圈11的匝数越多，在其他条件不变的情况下，电感量越大，因此，线圈11的匝数可以根据应用的场景、所需要达到的电感量等进行设计，本申请不作具体限定。It can be understood that each coil 11 can be, but not limited to, a part of a one-turn coil (such as a half-turn coil, a 0.3-turn coil, etc.), a one-turn coil, a two-turn coil, a three-turn coil, a four-turn coil, and a five-turn coil wait. The more turns of the coil 11, the greater the inductance when other conditions remain unchanged. Therefore, the number of turns of the coil 11 can be designed according to the application scene, the required inductance, etc., and this application does not make specific limitations. .

电路板10嵌设有线圈11，换言之，线圈11嵌设于电路板10内。线圈11嵌设于电路板10内，可以为线圈11至少部分被电路板10包裹；还可以为线圈11与电路板10集成为一体结构，线圈11直接由电路板10中的导线组成，电路板10在制备的过程中，一并形成线圈11；还可以为线圈11穿设于电路板10，换言之，线圈11部分穿过电路板10，部分露出电路板10。The circuit board 10 is embedded with the coil 11 , in other words, the coil 11 is embedded in the circuit board 10 . The coil 11 is embedded in the circuit board 10, and the coil 11 can be at least partially wrapped by the circuit board 10; it can also be an integrated structure of the coil 11 and the circuit board 10, and the coil 11 is directly composed of the wires in the circuit board 10, and the circuit board 10 During the preparation process, the coil 11 is formed together; the coil 11 can also be pierced through the circuit board 10 , in other words, the coil 11 partially passes through the circuit board 10 and partially exposes the circuit board 10 .

电路板10嵌设有线圈11，线圈11可以嵌设于电路板10需要设置电感的对应位置。线圈11为电路板10的一小部分，因此，磁胶层20可以仅设置在电路板10上设有线圈11的部分，此外，磁胶层20还可以覆盖线圈11之外的电路板10的表面。为了兼顾节省成本且使电路板集成电感100的电感具有更好的性能，磁胶层20可以覆盖整个线圈11。The circuit board 10 is embedded with a coil 11 , and the coil 11 may be embedded in a corresponding position of the circuit board 10 where an inductor needs to be provided. The coil 11 is a small part of the circuit board 10, therefore, the magnetic glue layer 20 can only be arranged on the part where the coil 11 is arranged on the circuit board 10, and in addition, the magnetic glue layer 20 can also cover the parts of the circuit board 10 other than the coil 11. surface. In order to save cost and improve the performance of the circuit board integrated inductor 100 , the magnetic glue layer 20 can cover the entire coil 11 .

磁胶层20设置于电路板10相背的两侧中的至少一侧上，可以为电路板10的一个表面上设有磁胶层20，也可以为电路板10相背的两个表面上均设有磁胶层20。磁胶层20设置于电路板10相背的两侧中的至少一侧上，可以为磁胶层20设置于电路板10的一侧，例如设置于电路板10的表面上，或者电路板10的表面设有绝缘层等膜层，磁胶层20设置在绝缘层等膜层的表面上；还可以为，磁胶层20设置于电路板10的相背两侧，换言之，电路板10相背的两侧均设有磁胶层20，如电路板10相背的两个表面均设有磁胶层20，或者电路板10相背的两个表面均设有绝缘层，磁胶层20设置于该绝缘层的表面。The magnetic glue layer 20 is arranged on at least one side of the opposite sides of the circuit board 10. It can be provided with the magnetic glue layer 20 on one surface of the circuit board 10, or on the two opposite surfaces of the circuit board 10. Both are provided with a magnetic glue layer 20 . The magnetic glue layer 20 is arranged on at least one side of the opposite sides of the circuit board 10, and the magnetic glue layer 20 can be arranged on one side of the circuit board 10, such as being arranged on the surface of the circuit board 10, or the circuit board 10 The surface of the surface is provided with insulating layers and other film layers, and the magnetic glue layer 20 is arranged on the surface of the insulating layer and other film layers; it can also be that the magnetic glue layer 20 is arranged on the opposite sides of the circuit board 10, in other words, the circuit board 10 Both sides of the back are provided with a magnetic adhesive layer 20, such as the two opposite surfaces of the circuit board 10 are provided with a magnetic adhesive layer 20, or the two opposite surfaces of the circuit board 10 are provided with an insulating layer, the magnetic adhesive layer 20 set on the surface of the insulating layer.

至少部分交叠指磁胶层20与线圈11在电路板10表面的正投影至少部分交叠。磁胶层20与线圈11至少部分交叠，可以为磁胶层20与线圈11部分交叠；还可以为磁胶层20覆盖整个线圈11的表面；还可以为磁胶层20覆盖部分线圈11，位于线圈11之内等。At least partially overlapping refers to at least partially overlapping the orthographic projection of the magnetic glue layer 20 and the coil 11 on the surface of the circuit board 10 . The magnetic glue layer 20 and the coil 11 at least partially overlap, and the magnetic glue layer 20 and the coil 11 can be partially overlapped; the magnetic glue layer 20 can also cover the entire surface of the coil 11; it can also be that the magnetic glue layer 20 covers part of the coil 11 , located within the coil 11, etc.

磁胶层20指包括磁性材料在其中不连续分布、磁性材料之间断开的膜层。磁膜层30指包括连续的磁性材料、中间没有断开的膜层。The magnetic glue layer 20 refers to a film layer in which magnetic materials are discontinuously distributed and the magnetic materials are disconnected. The magnetic film layer 30 refers to a film layer that includes continuous magnetic materials without interruptions in the middle.

本申请实施例的电路板集成电感100，将电感集成于电路板10上，应用于电子设备时，可以使得电子设备更加小型化、超薄化，且电感与电路板10一起制备，不需要独立贴装，提高了封装效率。此外，电感集成于电路板10内，电路板10上对应电感的位置可以节省出来，用于贴装其它元器件，节省了电路板10上的面积，增强了电路板10的布线、布件能力。再者，本申请将磁胶层20与磁膜层30结合共同作为电路板集成电感100中的磁性层，相较于仅有磁胶层20或磁膜层30的情况下，得到的电路板集成电感100的电感量大大增加，远超过单独磁胶层20的电感量和单独磁膜层30的电感量的累加值，可以更好的实现超薄高感，有利于电路板集成电感100的超薄化、小型化。The circuit board integrated inductor 100 of the embodiment of the present application integrates the inductor on the circuit board 10, and when applied to electronic equipment, it can make the electronic equipment more miniaturized and ultra-thin, and the inductor is prepared together with the circuit board 10 without independent Mounting, improving packaging efficiency. In addition, the inductor is integrated in the circuit board 10, and the position corresponding to the inductor on the circuit board 10 can be saved for mounting other components, saving the area on the circuit board 10, and enhancing the wiring and layout capabilities of the circuit board 10 . Furthermore, the present application combines the magnetic glue layer 20 and the magnetic film layer 30 together as the magnetic layer in the circuit board integrated inductor 100. Compared with the case of only the magnetic glue layer 20 or the magnetic film layer 30, the obtained circuit board The inductance of the integrated inductor 100 is greatly increased, far exceeding the cumulative value of the inductance of the single magnetic glue layer 20 and the inductance of the single magnetic film layer 30, which can better achieve ultra-thin and high inductance, which is conducive to the development of the circuit board integrated inductor 100. Ultra-thin and miniaturized.

请参见图4及图5，在一些实施例中，电路板10包括至少一层介电层12及至少一层导电层14；介电层12与导电层14依次交替层叠设置，导电层14包括导线14a；当导电层14为一层时，单层导电层14的导线14a形成线圈11；导电层14为多层时，任意相邻的两层导电层14的导线14a电连接，形成线圈11。通过采用电路板10原有的导电层14形成线圈11，从而将电感的线圈11集成于电路板10，使得制备工艺更加简单化，得到的电路板集成电感100更加超薄化、小型化。4 and 5, in some embodiments, the circuit board 10 includes at least one dielectric layer 12 and at least one conductive layer 14; the dielectric layer 12 and the conductive layer 14 are stacked alternately in sequence, and the conductive layer 14 includes Wire 14a; when conductive layer 14 is one layer, the wire 14a of single-layer conductive layer 14 forms coil 11; . By using the original conductive layer 14 of the circuit board 10 to form the coil 11 , the coil 11 of the inductor is integrated into the circuit board 10 , which simplifies the manufacturing process, and the obtained circuit board integrated inductor 100 is more ultra-thin and miniaturized.

请参见图4、图6及图7，述电路板10包括至少一层介电层12及至少一层导电层14；介电层12与导电层14依次交替层叠设置。如图6所示，在一些实施例中，电路板10包括层叠设置的一层介电层12及一层导电层14，导电层14包括导线14a，例如一根、两根、三根、四根等，导线14a形成线圈11(或者说一根导线14a形成一个线圈11)。如图4及图5所示，在另一些实施例中，电路板10包括层叠设置的一层介电层12及两层导电层14，两层导电层14分别设置于介电层12相背的两个表面上，两层导电层14均包括导线14a，两层导电层14的导线14a电连接，形成线圈11。如图7所示，在另一些实施例中，电路板10包括层叠设置的两层介电层12及三层导电层14，介电层12与导电层14依次交替层叠设置，三层导电层14均包括导线14a，任意相邻的两层导电层14的导线14a电连接，形成线圈11。本申请对电路板10中介电层12和导电层14的数量不作具体限定，只要能够形成介电层12与导电层14依次交替层叠的结构即可，具体可以根据实际需求进行设计。Referring to FIG. 4 , FIG. 6 and FIG. 7 , the circuit board 10 includes at least one dielectric layer 12 and at least one conductive layer 14 ; the dielectric layer 12 and the conductive layer 14 are stacked alternately in sequence. As shown in FIG. 6, in some embodiments, the circuit board 10 includes a layer of dielectric layer 12 and a layer of conductive layer 14 that are stacked, and the conductive layer 14 includes wires 14a, such as one, two, three, four etc., the wire 14a forms the coil 11 (or in other words, one wire 14a forms one coil 11). As shown in FIGS. 4 and 5 , in some other embodiments, the circuit board 10 includes a layer of dielectric layer 12 and two layers of conductive layers 14 stacked, and the two layers of conductive layers 14 are respectively arranged on the dielectric layer 12 opposite to each other. The two conductive layers 14 include wires 14 a on both surfaces of the two conductive layers 14 , and the wires 14 a of the two conductive layers 14 are electrically connected to form the coil 11 . As shown in FIG. 7 , in some other embodiments, the circuit board 10 includes two layers of dielectric layers 12 and three layers of conductive layers 14 stacked, the dielectric layers 12 and the conductive layers 14 are stacked alternately in sequence, and the three layers of conductive layers 14 each includes a wire 14a, and the wires 14a of any two adjacent conductive layers 14 are electrically connected to form the coil 11 . The present application does not specifically limit the number of dielectric layers 12 and conductive layers 14 in the circuit board 10, as long as the dielectric layer 12 and conductive layer 14 can be alternately stacked in sequence, which can be designed according to actual needs.

在一具体实施例中，电路板10包括层叠设置的一层介电层12及一层导电层14，导电层14包括一根导线14a，该导线14a形成一个线圈11，如图6所示。在另一具体实施例中，电路板10包括层叠设置的一层介电层12及两层导电层14，两层导电层14分别设置于介电层12相背的两个表面上，两层导电层14均包括一根导线14a，两层导电层14的导线14a电连接形成一个线圈11，如图4所示。在另一具体实施例中，电路板10包括层叠设置的一层介电层12及两层导电层14，两层导电层14分别设置于介电层12相背的两个表面上，两层导电层14均包括两根导线14a，两层导电层14的其中一根导线14a电连接形成一个线圈11，另一根导线14a电连接形成另一个线圈11，换言之，形成两个线圈11，如图8所示。In a specific embodiment, the circuit board 10 includes a layer of dielectric layer 12 and a layer of conductive layer 14 stacked, the conductive layer 14 includes a wire 14a, and the wire 14a forms a coil 11, as shown in FIG. 6 . In another specific embodiment, the circuit board 10 includes a layer of dielectric layer 12 and two layers of conductive layer 14 stacked, the two layers of conductive layer 14 are respectively arranged on the two surfaces of the dielectric layer 12 opposite, The conductive layers 14 each include a wire 14 a, and the wires 14 a of the two conductive layers 14 are electrically connected to form a coil 11 , as shown in FIG. 4 . In another specific embodiment, the circuit board 10 includes a layer of dielectric layer 12 and two layers of conductive layer 14 stacked, the two layers of conductive layer 14 are respectively arranged on the two surfaces of the dielectric layer 12 opposite, The conductive layers 14 each include two wires 14a. One of the wires 14a of the two conductive layers 14 is electrically connected to form a coil 11, and the other wire 14a is electrically connected to form another coil 11. In other words, two coils 11 are formed, such as Figure 8 shows.

可选地，介电层12可以包括但不限于包括聚酰亚胺(PI)、玻纤/环氧树脂复合板(Prepreg)等中的至少一种。导线14a可以包括但不限于包括铜、银导电金属或合金中的至少一种。当需要制备柔性电路板10(FPC)时，可以采用聚酰亚胺作为介电层12，当需要制备印制电路板10(PCB板)时，可以采用玻纤/环氧树脂复合板作为介电层12。在一具体实施例中，介电层12为聚酰亚胺，导线14a为铜线。Optionally, the dielectric layer 12 may include, but is not limited to, at least one of polyimide (PI), glass fiber/epoxy composite board (Prepreg), and the like. The wire 14a may include, but is not limited to, at least one of copper, silver conductive metal, or an alloy. When the flexible circuit board 10 (FPC) needs to be prepared, polyimide can be used as the dielectric layer 12, and when the printed circuit board 10 (PCB board) needs to be prepared, the glass fiber/epoxy composite board can be used as the dielectric layer. Electrical layer 12. In a specific embodiment, the dielectric layer 12 is polyimide, and the wires 14a are copper wires.

可选地，沿介电层12与导电层14的层叠方向上，每层介电层12的厚度为10μm至50μm；具体地，可以为但不限于为10μm、15μm、20μm、25μm、30μm、35μm、40μm、45μm、50μm等。介电层 12的厚度太小，如小于10μm时，介电层12的力学性能有限，难以对导电层14起到有效支撑作用；由于介电层12的磁导率很低，介电层12的厚度过大，例如大于50μm时，会增加磁路的长度，使得磁阻增大，不利于得到的电感的性能。Optionally, along the stacking direction of the dielectric layer 12 and the conductive layer 14, the thickness of each dielectric layer 12 is 10 μm to 50 μm; specifically, it can be but not limited to 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35μm, 40μm, 45μm, 50μm, etc. The thickness of the dielectric layer 12 is too small, such as when less than 10 μm, the mechanical properties of the dielectric layer 12 are limited, and it is difficult to effectively support the conductive layer 14; because the magnetic permeability of the dielectric layer 12 is very low, the dielectric layer 12 If the thickness is too large, such as greater than 50 μm, the length of the magnetic circuit will be increased, which will increase the reluctance, which is not conducive to the performance of the obtained inductor.

本申请实施例中，当涉及到数值范围a至b时，如未特别指明，均表示包括端点数值a，且包括端点数值b。例如，导线14a的厚度为50μm至150μm表示，导线14a的厚度可以为50μm至150μm之间的任意数值，包括端点50μm及端点150μm。In the embodiments of the present application, when it comes to the numerical range a to b, unless otherwise specified, it means that the endpoint value a is included, and the endpoint value b is included. For example, the thickness of the wire 14 a is 50 μm to 150 μm, and the thickness of the wire 14 a can be any value between 50 μm and 150 μm, including the endpoint 50 μm and the endpoint 150 μm.

请参见图9，可选地，沿介电层12与导电层14的层叠方向上，导线14a的厚度d1的范围为50μm至150μm，具体地，可以为但不限于为50μm、60μm、70μm、80μm、90μm、100μm、110μm、120μm、130μm、140μm、150μm等。Referring to FIG. 9, optionally, along the lamination direction of the dielectric layer 12 and the conductive layer 14, the thickness d1 of the wire 14a ranges from 50 μm to 150 μm, specifically, but is not limited to 50 μm, 60 μm, 70 μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, etc.

可选地，导线14a的宽度d2(即平行于介电层12延伸方向的宽度)的范围为100μm至300μm；具体地，可以为但不限于为100μm、110μm、120μm、130μm、140μm、150μm、180μm、200μm、220μm、240μm、280μm、300μm等。Optionally, the width d2 of the wire 14a (that is, the width parallel to the direction in which the dielectric layer 12 extends) ranges from 100 μm to 300 μm; 180μm, 200μm, 220μm, 240μm, 280μm, 300μm, etc.

可选地，同一匝线圈11中，相对设置的两部分导线14a的线距d3的范围为100μm至200μm；具体地，可以为但不限于为100μm、110μm、120μm、130μm、140μm、150μm、180μm、200μm。在一具体实施例中，导线14a的厚度为100μm，导线14a的宽度为200μm，导线14a的线距为150μm。Optionally, in the same turn of the coil 11, the line distance d3 of the two oppositely arranged wires 14a ranges from 100 μm to 200 μm; specifically, it can be but not limited to 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 180 μm , 200 μm. In a specific embodiment, the thickness of the wire 14 a is 100 μm, the width of the wire 14 a is 200 μm, and the pitch of the wire 14 a is 150 μm.

请参见图10及图11，在一些实施例中，电路板10还包括基板10a及功能电路10b，功能电路10b承载于基板10a，且与线圈11电连接。可选地，基板10a与介电层12为一体结构。Referring to FIG. 10 and FIG. 11 , in some embodiments, the circuit board 10 further includes a substrate 10 a and a functional circuit 10 b , the functional circuit 10 b is carried on the substrate 10 a and is electrically connected to the coil 11 . Optionally, the substrate 10a and the dielectric layer 12 are integrally structured.

请参见图11，功能电路10b包括处理器11b及存储器13b，处理器11b及存储器13b均设置于基板10a的表面，处理器11b分别与存储器13b及线圈11电连接。处理器11b用于控制线圈11电流的大小及方向等。存储器13b用于存储处理器11b运行所需的程序代码。Referring to FIG. 11 , the functional circuit 10b includes a processor 11b and a memory 13b, both of which are disposed on the surface of the substrate 10a, and the processor 11b is electrically connected to the memory 13b and the coil 11 respectively. The processor 11b is used for controlling the magnitude and direction of the current of the coil 11 and the like. The memory 13b is used to store program codes required for the operation of the processor 11b.

可选地，处理器11b包括一个或者多个通用处理器，其中，通用处理器可以是能够处理电子指令的任何类型的设备，包括中央处理器(Central Processing Unit,CPU)、微处理器、微控制器、主处理器、控制器以及ASIC等等。处理器11b用于执行各种类型的数字存储指令，例如存储在存储器中的软件或者固件程序，它能使计算设备提供较宽的多种服务。Optionally, the processor 11b includes one or more general-purpose processors, wherein the general-purpose processor can be any type of device capable of processing electronic instructions, including a central processing unit (Central Processing Unit, CPU), a microprocessor, a microprocessor Controllers, main processors, controllers and ASICs, etc. The processor 11b is used to execute various types of digitally stored instructions, such as software or firmware programs stored in memory, which enable the computing device to provide a wide variety of services.

可选地，存储器13b可以包括易失性存储器(Volatile Memory)，例如随机存取存储器(Random Access Memory，RAM)；存储器13b也可以包括非易失性存储器(Non-Volatile Memory，NVM)，例如只读存储器(Read-Only Memory，ROM)、快闪存储器(Flash Memory，FM)、硬盘(Hard Disk Drive，HDD)或固态硬盘(Solid-State Drive，SSD)。存储器13b还可以包括上述种类的存储器的组合。Optionally, the memory 13b can include a volatile memory (Volatile Memory), such as a Random Access Memory (Random Access Memory, RAM); the memory 13b can also include a non-volatile memory (Non-Volatile Memory, NVM), such as Read-only memory (Read-Only Memory, ROM), flash memory (Flash Memory, FM), hard disk (Hard Disk Drive, HDD) or solid-state drive (Solid-State Drive, SSD). The memory 13b may also include a combination of the above-mentioned kinds of memories.

在一些实施例中，磁胶层20包括树脂及磁性颗粒，磁性颗粒分散于树脂中。磁胶层20可以通过将磁性颗粒分散于液体树脂中形成磁性浆料，再将其涂覆或印刷于电路板10的表面，经过固化(例如紫外光光固化)形成。In some embodiments, the magnetic glue layer 20 includes resin and magnetic particles, and the magnetic particles are dispersed in the resin. The magnetic glue layer 20 can be formed by dispersing magnetic particles in a liquid resin to form a magnetic slurry, and then coating or printing it on the surface of the circuit board 10 and curing (for example, UV curing).

可选地，在磁胶层20中，磁性颗粒的重量分数的范围为85％至95％。具体地，磁性颗粒的重量分数可以为但不限于为85％、86％、87％、88％、89％、90％、91％、92％、93％、94％、95％等。当磁胶层20中磁性颗粒的重量分数小于85％时，形成的磁胶层20的磁导率过低，不利于提高电路板集成电感100中电感的感量，当磁胶层20中磁性颗粒的重量分数大于95％时，则树脂的含量过低，磁性颗粒有可能聚集在一起，等效成大颗粒的效果，使得电感的铁损增加。Optionally, in the magnetic glue layer 20 , the weight fraction of the magnetic particles ranges from 85% to 95%. Specifically, the weight fraction of the magnetic particles can be, but not limited to, 85%, 86%, 87%, 88%, 89%, 90%, 91%, 92%, 93%, 94%, 95%, etc. When the weight fraction of magnetic particles in the magnetic glue layer 20 is less than 85%, the magnetic permeability of the formed magnetic glue layer 20 is too low, which is not conducive to improving the inductance of the circuit board integrated inductor 100, when the magnetic glue layer 20 When the weight fraction of the particles is greater than 95%, the resin content is too low, and the magnetic particles may gather together, which is equivalent to the effect of large particles and increases the iron loss of the inductor.

可选地，磁性颗粒的D90粒径的范围为：1μm≤D90≤10μm。具体地，磁性颗粒的D90粒径可以为但不限于为1μm、2μm、4μm、6μm、8μm、10μm等。此外，磁性颗粒的D90粒径还可以为1μm至10μm之间的任意数值范围，例如1μm至5μm，或者4μm至8μm；或者5μm至10μm。磁性颗粒较小时，涡流被限制在很小的范围内，随着磁性颗粒的增大，可以供涡流流过的区域变大，从而增加了涡流损耗。但是当磁性颗粒的平均粒径小于1μm时，不仅增加了磁性颗粒的成本，且会降低磁胶层20的磁导率。当磁性颗粒的平均粒径大于10μm时，涡流损耗增大，也不利于电路板集成电感100的性能。D90指90％的颗粒的粒径尺寸在所测得的尺寸值。如磁性颗粒的D90粒径的范围为：1μm≤D90≤10μm指90％的磁性颗粒的粒径尺寸90％在1μm至10μm之间。Optionally, the range of D90 particle size of the magnetic particles is: 1 μm≤D90≤10 μm. Specifically, the D90 particle size of the magnetic particles may be, but not limited to, 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm and the like. In addition, the D90 particle size of the magnetic particles can also be in any numerical range between 1 μm and 10 μm, for example, 1 μm to 5 μm, or 4 μm to 8 μm; or 5 μm to 10 μm. When the magnetic particles are small, the eddy current is limited to a small range. With the increase of the magnetic particles, the area where the eddy current can flow becomes larger, thus increasing the eddy current loss. However, when the average particle size of the magnetic particles is less than 1 μm, not only the cost of the magnetic particles will be increased, but also the magnetic permeability of the magnetic glue layer 20 will be reduced. When the average particle size of the magnetic particles is greater than 10 μm, the eddy current loss increases, which is also detrimental to the performance of the circuit board integrated inductor 100 . D90 refers to the particle size of 90% of the particles in the measured size value. For example, the D90 particle size range of the magnetic particles is: 1 μm≤D90≤10 μm means that 90% of the magnetic particles have a particle size of 90% between 1 μm and 10 μm.

可选地，磁性颗粒为软磁颗粒。软磁具有高磁导率、低剩磁、低矫顽力、低磁阻、磁滞损耗小、且容易被磁化。可选地，磁性颗粒包括铁氧体颗粒、磁性金属颗粒、磁性合金颗粒中的至少一种。铁氧体颗粒尤其是NiZn铁氧体具有更低的电导率，因此有更低的损耗，磁性合金颗粒具有更高的磁饱和感应强度。因此，当要求磁胶层20具有更好的电绝缘性和更低的损耗时，可以选择较高配比的铁氧体颗粒作为磁性颗粒；当要求磁胶层20具有更高的磁饱和感应强度时，可以选择较高配比的磁性合金颗粒作为磁性颗粒。可选地，铁氧体颗粒包括MnZn铁氧体、NiZn铁氧体等中的至少一种。可选地，磁性金属颗粒包括铁、钴、镍中等的至少一种。可选地，磁性合金颗粒包括铁基晶态合金、铁基非晶合金、钴基非晶合金等中的至少一种。铁基晶态合金包括FeNi合金、FeCo合金、FeAl合金、FeSiAl合金、FeNiMo合金、FeC合金等中的至少一种。铁基非晶合金包括FeSiB合金、FeB合金、FeNiPB合金、FeNiMoB合金等中的至少一种。钴基非晶合金包括CoFeSiB合金、CoFeCrSiB合金、CoNiFeSiB合金等中的至少一种。Optionally, the magnetic particles are soft magnetic particles. Soft magnetism has high permeability, low remanence, low coercive force, low magnetic resistance, low hysteresis loss, and is easy to be magnetized. Optionally, the magnetic particles include at least one of ferrite particles, magnetic metal particles, and magnetic alloy particles. Ferrite particles, especially NiZn ferrite, have lower electrical conductivity and therefore lower loss, and magnetic alloy particles have higher magnetic saturation induction. Therefore, when the magnetic glue layer 20 is required to have better electrical insulation and lower loss, a higher ratio of ferrite particles can be selected as the magnetic particles; when the magnetic glue layer 20 is required to have higher magnetic saturation induction When, you can choose a higher ratio of magnetic alloy particles as magnetic particles. Optionally, the ferrite particles include at least one of MnZn ferrite, NiZn ferrite and the like. Optionally, the magnetic metal particles include at least one of iron, cobalt, nickel and the like. Optionally, the magnetic alloy particles include at least one of an iron-based crystalline alloy, an iron-based amorphous alloy, a cobalt-based amorphous alloy, and the like. The iron-based crystalline alloy includes at least one of FeNi alloy, FeCo alloy, FeAl alloy, FeSiAl alloy, FeNiMo alloy, FeC alloy and the like. The iron-based amorphous alloy includes at least one of FeSiB alloy, FeB alloy, FeNiPB alloy, FeNiMoB alloy and the like. The cobalt-based amorphous alloy includes at least one of CoFeSiB alloy, CoFeCrSiB alloy, CoNiFeSiB alloy and the like.

相较于铁基晶态合金及铁基非晶合金，钴基非晶合金具有更高的磁导率，因此，当磁胶层20要求较高的磁导率时，磁性颗粒可以采用钴基非晶合金中的至少一种。相较于钴基非晶合金，铁基晶态合金及铁基非晶合金具有较高的饱和磁特性，当磁胶层20要求较高的饱和磁特性时，磁性颗粒可以选用铁基晶态合金及铁基非晶合金等中的至少一种。相较于铁基晶态合金，铁基非晶合金及钴基非晶合金具有较低的矫顽力，当磁胶层20要求较低的矫顽力时，磁性颗粒可以选用铁基非晶合金及钴基非晶合金。Compared with iron-based crystalline alloys and iron-based amorphous alloys, cobalt-based amorphous alloys have higher magnetic permeability. Therefore, when the magnetic glue layer 20 requires higher magnetic permeability, the magnetic particles can use cobalt-based at least one of amorphous alloys. Compared with cobalt-based amorphous alloys, iron-based crystalline alloys and iron-based amorphous alloys have higher saturation magnetic properties. When the magnetic glue layer 20 requires higher saturation magnetic properties, the magnetic particles can be iron-based crystalline At least one of alloys and iron-based amorphous alloys. Compared with iron-based crystalline alloys, iron-based amorphous alloys and cobalt-based amorphous alloys have lower coercive forces. When the magnetic glue layer 20 requires a lower coercive force, the magnetic particles can be iron-based amorphous alloys. alloys and cobalt-based amorphous alloys.

可选地，当磁性颗粒为磁性合金颗粒时，磁性合金颗粒的表面具有钝化层，钝化层为绝缘层，换言之，钝化层是绝缘的。在一些实施例中，可以在磁性合金颗粒的表面包裹一层有机树脂，以使磁性合金颗粒具有绝缘性。在另一些实施例中，可以将磁性合金颗粒采用磷酸进行钝化，以在磁性合金颗粒的表面形成一层不导电的钝化层。Optionally, when the magnetic particles are magnetic alloy particles, the surface of the magnetic alloy particles has a passivation layer, and the passivation layer is an insulating layer, in other words, the passivation layer is insulating. In some embodiments, a layer of organic resin can be coated on the surface of the magnetic alloy particles to make the magnetic alloy particles insulative. In other embodiments, the magnetic alloy particles may be passivated with phosphoric acid to form a non-conductive passivation layer on the surface of the magnetic alloy particles.

可选地，树脂包括环氧树脂、聚氨酯及丙烯酸酯等中的至少一种。在一具体实施例中，当电路板10的介电层12为玻纤/环氧树脂复合板时，磁胶层20的树脂以为环氧树脂，这样可以使得磁胶层20与电路板10具有更好的结合性能，可以更好的附着于电路板10上。Optionally, the resin includes at least one of epoxy resin, polyurethane and acrylate. In a specific embodiment, when the dielectric layer 12 of the circuit board 10 is a glass fiber/epoxy resin composite board, the resin of the magnetic glue layer 20 is epoxy resin, so that the magnetic glue layer 20 and the circuit board 10 have the same With better bonding performance, it can be better attached to the circuit board 10 .

可选地，沿电路板10、磁胶层20及磁膜层30的层叠方向，磁胶层20的厚度h1的范围为50μm≤h1≤500μm，具体地，磁胶层20的厚度h1可以为但不限于为5μm、10μm、30μm、50μm、80μm、100μm、120μm、140μm、160μm、180μm、200μm、250μm、300μm、350μm、400μm、450μm、500μm等。当磁胶层20的厚度h1小于50μm时，磁胶层20可能难以完全覆盖裸露在电路板10表面的线圈11，导致磁胶层20的表面可能有台阶，不利于磁膜层30的沉积。当磁胶层20的厚度h1大于500μm时，制得的电感器件比较大，可能超出了电路板10的厚度，不利于埋感。Optionally, along the stacking direction of the circuit board 10, the magnetic glue layer 20 and the magnetic film layer 30, the thickness h1 of the magnetic glue layer 20 ranges from 50 μm≤h1≤500 μm, specifically, the thickness h1 of the magnetic glue layer 20 can be But not limited to 5 μm, 10 μm, 30 μm, 50 μm, 80 μm, 100 μm, 120 μm, 140 μm, 160 μm, 180 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, etc. When the thickness h1 of the magnetic glue layer 20 is less than 50 μm, it may be difficult for the magnetic glue layer 20 to completely cover the coil 11 exposed on the surface of the circuit board 10 , resulting in steps on the surface of the magnetic glue layer 20 , which is not conducive to the deposition of the magnetic film layer 30 . When the thickness h1 of the magnetic glue layer 20 is greater than 500 μm, the manufactured inductance device is relatively large, which may exceed the thickness of the circuit board 10 , which is not conducive to the buried inductance.

可选地，磁膜层30为软磁层。软磁具有高磁导率、低剩磁、低矫顽力、低磁阻、磁滞损耗小、且容易被磁化。可选地，磁膜层30可以包括但不限于为包括磁性金属、磁性合金中的至少一种。可选地，磁性金属可以包括铁、镍、钴中的至少一种。可选地，磁性合金可以包括铁基晶态合金、铁基非晶合金、钴基非晶合金中的至少一种；铁基晶态合金包括FeNi合金、FeCo合金、FeAl合金、FeSiAl合金、FeNiMo合金、FeC合金等中的至少一种。铁基非晶合金包括FeSiB合金、FeB合金、FeNiPB合金、FeNiMoB合金等中的至少一种。钴基非晶合金包括CoFeSiB合金、CoFeCrSiB合金、CoNiFeSiB合金等中的至少一种。Optionally, the magnetic film layer 30 is a soft magnetic layer. Soft magnetism has high permeability, low remanence, low coercivity, low reluctance, low hysteresis loss, and is easy to be magnetized. Optionally, the magnetic film layer 30 may include, but is not limited to, at least one of magnetic metal and magnetic alloy. Optionally, the magnetic metal may include at least one of iron, nickel, and cobalt. Optionally, the magnetic alloy may include at least one of iron-based crystalline alloys, iron-based amorphous alloys, and cobalt-based amorphous alloys; iron-based crystalline alloys include FeNi alloys, FeCo alloys, FeAl alloys, FeSiAl alloys, FeNiMo alloy, FeC alloy, and the like. The iron-based amorphous alloy includes at least one of FeSiB alloy, FeB alloy, FeNiPB alloy, FeNiMoB alloy and the like. The cobalt-based amorphous alloy includes at least one of CoFeSiB alloy, CoFeCrSiB alloy, CoNiFeSiB alloy and the like.

可选地，沿导电层14、磁胶层20及磁膜层30的层叠方向，磁膜层30的厚度h2的范围为5μm≤h2≤35μm。具体地，磁性层的厚度h2可以为但不限于为5μm、10μm、15μm、20μm、25μm、30μm、35μm等。当磁膜层30的厚度小于5μm时，电路板集成电感100的感量较低，当磁膜层30的厚度大于35μm时，由于集肤效应，即使磁膜层30的厚度有较大幅度增加，电感的感量增加非常有限，这降低了磁膜层30的利用率，且增加了磁膜层30的沉积难度。Optionally, along the stacking direction of the conductive layer 14 , the magnetic glue layer 20 and the magnetic film layer 30 , the thickness h2 of the magnetic film layer 30 is in the range of 5 μm≤h2≤35 μm. Specifically, the thickness h2 of the magnetic layer may be, but not limited to, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm and the like. When the thickness of the magnetic film layer 30 is less than 5 μm, the inductance of the circuit board integrated inductor 100 is low; , the increase of the inductance is very limited, which reduces the utilization rate of the magnetic film layer 30 and increases the difficulty of depositing the magnetic film layer 30 .

在一些实施例中，所述磁膜层30包括磁性合金，磁性合金为改性磁性合金。所述改性磁性合金包括铬掺杂的铁镍合金、铬掺杂的铁钴合金、铬掺杂的铁硅铝合金中的至少一种。磁性合金具有较高的相对磁导率，可以使得制得的电路板集成电感100具有更大的感量，同时通过铬掺杂可以使得磁性合金的相对磁导率不会下降太多，大大降低磁性合金的等效电导率，从而增加磁膜层30的集肤深度。因此，可以通过提高磁膜层30的厚度，使得磁膜层30具有更高的饱和磁感应强度，且可以更好的分散磁通，降低磁膜层30应用时的最大磁感应强度，从而使得电路板集成电感100可以更好的应用于较大电流的场景。In some embodiments, the magnetic film layer 30 includes a magnetic alloy, and the magnetic alloy is a modified magnetic alloy. The modified magnetic alloy includes at least one of chromium-doped iron-nickel alloy, chromium-doped iron-cobalt alloy and chromium-doped sendust. The magnetic alloy has a higher relative magnetic permeability, which can make the circuit board integrated inductor 100 to have a greater inductance, and at the same time, the relative magnetic permeability of the magnetic alloy can not be reduced too much by chromium doping, which can be greatly reduced. The equivalent conductivity of the magnetic alloy increases the skin depth of the magnetic film layer 30 . Therefore, by increasing the thickness of the magnetic film layer 30, the magnetic film layer 30 has a higher saturation magnetic induction intensity, and can better disperse the magnetic flux, reducing the maximum magnetic induction intensity when the magnetic film layer 30 is applied, thereby making the circuit board The integrated inductor 100 can be better applied to the scene of relatively large current.

请参见图12，在一些实施例中，所述磁膜层30包括依次交替层叠设置的磁膜子层31及金属氧化物层33，其中磁膜子层31可以为改性磁性合金层，金属氧化物层33包括改性磁性合金中的至少一种金属的氧化物。通过改性磁性合金与金属氧化物层33交替层叠设置，可以充分降低磁膜层30的等效电导率，但是又不会使磁膜层30的相对磁导率降低太多。Please refer to FIG. 12 , in some embodiments, the magnetic film layer 30 includes magnetic film sublayers 31 and metal oxide layers 33 alternately stacked in sequence, wherein the magnetic film sublayers 31 can be modified magnetic alloy layers, metal The oxide layer 33 includes an oxide of at least one metal in the modified magnetic alloy. By alternately laminating the modified magnetic alloy and the metal oxide layer 33 , the equivalent electrical conductivity of the magnetic film layer 30 can be sufficiently reduced without reducing the relative magnetic permeability of the magnetic film layer 30 too much.

可选地，本实施例的磁膜层30可以通过以下步骤制得：Optionally, the magnetic film layer 30 of this embodiment can be produced through the following steps:

1)在绝缘基材上先通过化学镀等方法沉积一层金属层作为种子层，以使得绝缘基材具有导电性；1) Depositing a layer of metal layer as a seed layer on the insulating substrate by means of electroless plating, so that the insulating substrate has conductivity;

2)将具有种子层的绝缘基材放入电镀液中进行电镀，该电镀液中包括铬离子、磁性合金所包括的金属的粒子例如铁离子、镍离子等，以在种子层的表面形成铬掺杂的磁性合金层；2) Putting the insulating base material with the seed layer into an electroplating solution for electroplating, the electroplating solution includes chromium ions, particles of metals included in the magnetic alloy, such as iron ions, nickel ions, etc., to form chromium on the surface of the seed layer doped magnetic alloy layer;

3)静置一段时间，以使得铬掺杂的磁性合金层的表面形成金属氧化物层33；以及3) standing for a period of time, so that the surface of the chromium-doped magnetic alloy layer forms a metal oxide layer 33; and

4)循环步骤2)及3)，以形成磁膜子层31与金属氧化物层33依次交替层叠的磁膜层30结构。4) Steps 2) and 3) are repeated to form a magnetic film layer 30 structure in which the magnetic film sub-layers 31 and the metal oxide layers 33 are stacked alternately in sequence.

请参见图13，在另一些实施例中，磁膜层30包括依次交替层叠设置的绝缘子层35及磁膜子层31，其中绝缘子层35包括二氧化硅、氧化铝中的至少一种，磁膜子层31包括改性磁性合金。通过无机绝缘层与磁性金属层的交替层叠设置，可以充分降低磁膜层30的等效电导率，但是又不会使磁膜层30的相对磁导率降低太多。Please refer to FIG. 13. In other embodiments, the magnetic film layer 30 includes insulating sublayers 35 and magnetic film sublayers 31 alternately stacked in sequence, wherein the insulating sublayers 35 include at least one of silicon dioxide and aluminum oxide. The membrane sublayer 31 includes a modified magnetic alloy. The equivalent electrical conductivity of the magnetic film layer 30 can be sufficiently reduced by alternately stacking the inorganic insulating layer and the magnetic metal layer, but the relative magnetic permeability of the magnetic film layer 30 will not be reduced too much.

可选地，绝缘子层35可以通过原子层沉积(ALD)或溅镀、蒸镀等方法镀一层纳米级的SiO2膜层或氧化铝膜层等起到绝缘效果。磁膜子层31可以通过电镀进行制备。Optionally, the insulator layer 35 can be coated with a nano-scale SiO2 film or aluminum oxide film by atomic layer deposition (ALD), sputtering, evaporation and other methods to achieve an insulating effect. The magnetic film sublayer 31 can be prepared by electroplating.

可选地，所述磁膜层的等效电导率σ的范围为4KS/m≤σ≤600KS/m；所述磁膜层的相对磁导率μr的范围为500≤μr≤6000。本实施例的磁膜层30在具有较高的相对磁导率的同时，具有较低的等效电导率，从而使得磁膜层30具有较厚的集肤深度及较高的感量。因此，可以通过增加磁膜层30的厚度提高磁膜层30的饱和磁感应强度，有效分散磁通，从而更好的适用于大电流的场景，此外还可以通过增加磁膜层30的厚度，提高电路板集成电感100的感量，提高磁膜层30的利用率。Optionally, the range of the equivalent electrical conductivity σ of the magnetic film layer is 4KS/m≤σ≤600KS/m; the range of the relative permeability μr of the magnetic film layer is 500≤μr≤6000. The magnetic film layer 30 of this embodiment has a relatively low equivalent electrical conductivity while having a high relative magnetic permeability, so that the magnetic film layer 30 has a thicker skin depth and a higher inductance. Therefore, the saturation magnetic induction intensity of the magnetic film layer 30 can be improved by increasing the thickness of the magnetic film layer 30, and the magnetic flux can be effectively dispersed, thereby being better applicable to the scene of a large current. In addition, the thickness of the magnetic film layer 30 can be increased to improve The circuit board integrates the inductance of the inductor 100 to improve the utilization rate of the magnetic film layer 30 .

所述磁膜层30的等效电导率σ的范围为4KS/m≤σ≤600KS/m；具体地，磁膜层30的电导率σ可以为但不限于为4KS/m、6KS/m、10KS/m、40KS/m、60KS/m、80KS/m、100KS/m、200KS/m、300KS/m、400KS/m、500KS/m、600KS/m等。在磁膜层30相对磁导率不变的情况下，磁膜层30的等效电导率σ越小，得到的磁膜层30的集肤深度越大，通过提高磁膜层30的厚度，可以更好的提高磁膜层30的饱和磁感应强度，从而使得电路板集成电感100可以更好的应用于较大电流的场景。“等效电导率”指该磁膜层30等效为均相材料得到的电导率。The range of the equivalent electrical conductivity σ of the magnetic film layer 30 is 4KS/m≤σ≤600KS/m; specifically, the electrical conductivity σ of the magnetic film layer 30 can be but not limited to 4KS/m, 6KS/m, 10KS/m, 40KS/m, 60KS/m, 80KS/m, 100KS/m, 200KS/m, 300KS/m, 400KS/m, 500KS/m, 600KS/m, etc. Under the constant relative magnetic permeability of the magnetic film layer 30, the smaller the equivalent electrical conductivity σ of the magnetic film layer 30, the larger the skin depth of the magnetic film layer 30 obtained, by increasing the thickness of the magnetic film layer 30, The saturation magnetic induction of the magnetic film layer 30 can be better improved, so that the circuit board integrated inductor 100 can be better applied to a scene with a large current. "Equivalent electrical conductivity" refers to the electrical conductivity obtained by equivalently using a homogeneous material as the magnetic film layer 30 .

所述磁膜层30的相对磁导率μr的范围为500≤μr≤6000；具体地，所述磁膜层30的相对磁导率μr可以为但不限于为500、800、1000、1500、2000、2500、3000、3500、4000、4500、5000、5500、6000等。磁膜层30的相对磁导率越小，则磁膜层30的集肤深度越大，但是，相对磁导率过低，会大大降低电路板集成电感100的感量，因此，磁膜层30的相对磁导率不宜太低。The range of the relative permeability μr of the magnetic film layer 30 is 500≤μr≤6000; specifically, the relative permeability μr of the magnetic film layer 30 can be but not limited to 500, 800, 1000, 1500, 2000, 2500, 3000, 3500, 4000, 4500, 5000, 5500, 6000, etc. The smaller the relative magnetic permeability of the magnetic film layer 30 is, the larger the skin depth of the magnetic film layer 30 will be. However, if the relative magnetic permeability is too low, the inductance of the circuit board integrated inductor 100 will be greatly reduced. Therefore, the magnetic film layer The relative permeability of 30 should not be too low.

可选地，磁膜层30在1MHz的频率下的集肤深度δ的范围为8.40μm≤δ≤103μm。具体地，集肤深度δ可以为但不限于为8.4μm、10μm、12.5μm、15μm、17.5μm、20μm、30μm、40μm、50μm、60μm、70μm、80μm、90μm、96μm、103μm等。集肤深度越大，可以更好的通过增加磁膜层30的厚度来提高磁膜层30的饱和磁感应强度，从而更好的分散磁通，使得电路板集成电感100可以更好的适用于大电流的场景，同时，也可以更好的通过增加磁膜层30的厚度来提高电路板集成电感100的感量，从而使得磁膜层30可以做得更厚。本申请的磁膜层30具有较高的集肤深度，从而可以更好的分散磁通，降低磁膜层30中的最大磁感应强度(Bm)，同时又具有较高的感量，从而使用具有较小的饱和磁感应强度的材料就可以获得具有较大感量的电感。Optionally, the skin depth δ of the magnetic film layer 30 at a frequency of 1 MHz is in the range of 8.40 μm≤δ≤103 μm. Specifically, the skin depth δ may be, but not limited to, 8.4 μm, 10 μm, 12.5 μm, 15 μm, 17.5 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 96 μm, 103 μm, etc. The greater the skin depth, the better the saturation magnetic induction of the magnetic film layer 30 can be increased by increasing the thickness of the magnetic film layer 30, thereby better dispersing the magnetic flux, so that the circuit board integrated inductor 100 can be better applied to large At the same time, the inductance of the circuit board integrated inductor 100 can be improved by increasing the thickness of the magnetic film layer 30 , so that the magnetic film layer 30 can be made thicker. The magnetic film layer 30 of the present application has a higher skin depth, which can better disperse the magnetic flux, reduce the maximum magnetic induction intensity (Bm) in the magnetic film layer 30, and have a higher inductance at the same time, thereby using A material with a smaller saturation magnetic induction can obtain an inductance with a larger inductance.

请参见图14，在一些实施例中，本实施例的电路板集成电感100还包括绝缘层50，绝缘层50设置于线圈11与磁胶层20之间，用于使线圈11与磁胶层20绝缘设置，防止磁胶层20的磁性颗粒分散不均匀，导致的局部磁性颗粒堆积与导电层14(或线圈11)发生短路。Please refer to FIG. 14 , in some embodiments, the circuit board integrated inductor 100 of this embodiment further includes an insulating layer 50, and the insulating layer 50 is arranged between the coil 11 and the magnetic glue layer 20 for making the coil 11 and the magnetic glue layer 20 is insulated to prevent uneven dispersion of magnetic particles in the magnetic glue layer 20 , resulting in local accumulation of magnetic particles and a short circuit between the conductive layer 14 (or the coil 11 ).

可选地，绝缘层50包括陶瓷绝缘层50、有机绝缘层50等中的至少一种；陶瓷绝缘层50包括氧化铝、二氧化硅等中的至少一种；有机绝缘层50包括聚丙烯、聚四氟乙烯、聚酰亚胺等中的至少一种。相较于有机绝缘层50，陶瓷绝缘层50具有更好的绝缘性能和机械强度，但是，有机绝缘层50具有更低的制备成本。绝缘层材料的选择，可以根据实际应用需求进行选择。可选地，绝缘层50可以通过物理气相沉积、原子层沉积或者其它镀膜工艺形成。Optionally, the insulating layer 50 includes at least one of a ceramic insulating layer 50, an organic insulating layer 50, etc.; the ceramic insulating layer 50 includes at least one of alumina, silicon dioxide, etc.; the organic insulating layer 50 includes polypropylene, At least one of polytetrafluoroethylene, polyimide and the like. Compared with the organic insulating layer 50, the ceramic insulating layer 50 has better insulating performance and mechanical strength, but the organic insulating layer 50 has lower manufacturing cost. The material of the insulating layer can be selected according to actual application requirements. Optionally, the insulating layer 50 can be formed by physical vapor deposition, atomic layer deposition or other coating processes.

请参见图15，本申请实施例还提供一种电路板集成电感100的制备方法，本实施例的包括：Please refer to FIG. 15, the embodiment of the present application also provides a method for preparing a circuit board integrated inductor 100, which includes:

S201，提供电路板10，电路板10嵌设有线圈11；S201, providing a circuit board 10, the circuit board 10 is embedded with a coil 11;

S202，在电路板10相背的两侧中的至少一侧上形成磁胶层20，其中，磁胶层20与线圈11至少部分交叠；S202, forming a magnetic glue layer 20 on at least one of the two opposite sides of the circuit board 10, wherein the magnetic glue layer 20 and the coil 11 at least partially overlap;

可选地，先将磁性颗粒分散于液体树脂中形成磁性浆料，再将磁性浆料采用涂覆、印刷(如钢网印刷)等方式在电路板10表面形成磁性浆料层，接着置于LED灯或汞灯等紫外光下以使液体树脂发生光固化形成固态树脂，得到磁胶层20。在其它实施例中，磁性浆料层也可以采用热固化进行固化，本申请对此不作具体限定。Optionally, first disperse the magnetic particles in the liquid resin to form a magnetic slurry, then apply the magnetic slurry to form a magnetic slurry layer on the surface of the circuit board 10 by coating, printing (such as steel screen printing), and then place Under ultraviolet light such as an LED lamp or a mercury lamp, the liquid resin is photocured to form a solid resin, and the magnetic adhesive layer 20 is obtained. In other embodiments, the magnetic paste layer may also be cured by thermal curing, which is not specifically limited in the present application.

S203，在磁胶层20背离电路板10的一侧设置磁膜层30。S203 , disposing the magnetic film layer 30 on the side of the magnetic glue layer 20 away from the circuit board 10 .

可选地，采用物理气相沉积法、或电沉积法等在磁胶层20背离电路板10的一侧沉积磁膜层30，其中，磁膜层30的磁导率大于磁胶层20的磁导率。采用物理气相沉积方法制得的磁膜层30的外观形貌好，但是容易产生脱落；采用电沉积方法制得的磁膜层30具有良好的耐剥离性能，不易脱落，但是表面形貌较差，且效率更高。因此当磁膜层30的厚度较小时，可以采用物理气相沉积方法制备；当磁膜层30的厚度较大或者要求提高沉积效率时，可以采用电沉积方法制备。在其他实施例中，磁膜层30还可以是现成的软磁薄膜，此时，软磁薄膜可以通过胶粘剂粘贴于磁胶层20上。Optionally, the magnetic film layer 30 is deposited on the side of the magnetic glue layer 20 away from the circuit board 10 by physical vapor deposition, or electrodeposition, etc., wherein the magnetic permeability of the magnetic film layer 30 is greater than that of the magnetic glue layer 20. Conductivity. The appearance and appearance of the magnetic film layer 30 prepared by the physical vapor deposition method is good, but it is easy to fall off; the magnetic film layer 30 prepared by the electrodeposition method has good peeling resistance and is not easy to fall off, but the surface appearance is relatively poor , and is more efficient. Therefore, when the thickness of the magnetic film layer 30 is small, it can be prepared by physical vapor deposition; when the thickness of the magnetic film layer 30 is large or it is required to improve the deposition efficiency, it can be prepared by electrodeposition. In other embodiments, the magnetic film layer 30 may also be a ready-made soft magnetic film. In this case, the soft magnetic film may be pasted on the magnetic glue layer 20 through an adhesive.

本实施例与上述实施例相同特征部分例如电路板10、线圈11、磁胶层20、磁膜层30等的详细描述请参见上述实施例，在此不再赘述。For detailed descriptions of the same features of this embodiment as the above embodiments, such as the circuit board 10 , the coil 11 , the magnetic glue layer 20 , the magnetic film layer 30 , etc., please refer to the above embodiments, and will not be repeated here.

本实施例的制备方法制得的电路板集成电感100，将电感集成于电路板10上，应用于电子设备时，可以使得电子设备更加小型化、超薄化，且电感与电路板10一起制备，不需要独立贴装，提高了封装效率。此外，电感集成于电路板10内，电路板10上对应电感的位置可以节省出来，用于贴装其它元器件，节省了电路板10上的面积，增强了电路板10的布线、布件能力。再者，本申请将磁胶层20与磁膜层30结合共同作为电路板集成电感100中的磁性层，相较于仅有磁胶层20或磁膜层30的情况下，得到的电路板集成电感100的电感量大大增加，远超过单独磁胶层20的电感量和单独磁膜层30的电感量的累加值，可以更好的实现超薄高感，有利于电路板集成电感100的超薄化、小型化。The circuit board integrated inductor 100 prepared by the preparation method of this embodiment integrates the inductor on the circuit board 10, and when applied to electronic equipment, it can make the electronic equipment more miniaturized and ultra-thin, and the inductor is prepared together with the circuit board 10 , does not need to be mounted independently, which improves the packaging efficiency. In addition, the inductor is integrated in the circuit board 10, and the position corresponding to the inductor on the circuit board 10 can be saved for mounting other components, saving the area on the circuit board 10, and enhancing the wiring and layout capabilities of the circuit board 10 . Furthermore, the present application combines the magnetic glue layer 20 and the magnetic film layer 30 together as the magnetic layer in the circuit board integrated inductor 100. Compared with the case of only the magnetic glue layer 20 or the magnetic film layer 30, the obtained circuit board The inductance of the integrated inductor 100 is greatly increased, far exceeding the cumulative value of the inductance of the single magnetic glue layer 20 and the inductance of the single magnetic film layer 30, which can better achieve ultra-thin and high inductance, which is conducive to the development of the circuit board integrated inductor 100. Ultra-thin and miniaturized.

请参见图16及图17，在一些实施例中，本申请实施例提供了一种电路板10的制备方法，其包括：Please refer to FIG. 16 and FIG. 17. In some embodiments, the embodiment of the present application provides a method for preparing a circuit board 10, which includes:

S2011，提供第一基板10’，第一基板10’包括介电层12及设置于介电层12相背的两个表面中的至少一个表面的导体层11’；S2011, providing a first substrate 10', the first substrate 10' comprising a dielectric layer 12 and a conductor layer 11' disposed on at least one of the two opposite surfaces of the dielectric layer 12;

在一具体实施例中，第一基板10’包括一层介电层12及一层导体层11’，介电层12与导体层11’层叠设置。在另一具体实施例中，第一基板10’包括依次层叠设置的导体层11’、介电层12、导体层11’。In a specific embodiment, the first substrate 10' includes a dielectric layer 12 and a conductive layer 11', and the dielectric layer 12 and the conductive layer 11' are laminated. In another specific embodiment, the first substrate 10' includes a conductive layer 11', a dielectric layer 12, and a conductive layer 11' that are sequentially stacked.

可选地，导体层11’可以为但不限于为包括铜、银等金属或合金等导电材料。关于介电层12的详细描述请参见上述实施例对应部分的描述，在此不再赘述。Optionally, the conductor layer 11' may be, but not limited to, conductive materials including metals such as copper and silver or alloys. For a detailed description of the dielectric layer 12 , please refer to the description of the corresponding part of the above embodiment, and details are not repeated here.

S2012，对第一基板10’的每层导体层11’进行刻蚀，以使导体层11’形成导电层14，导电层14包括导线14a；其中，当导电层14为一层时，单层导电层14的导线14a形成线圈11；当导电层14为两层时，两层导电层14的导线14a电连接，形成线圈11。S2012, etching each conductive layer 11' of the first substrate 10', so that the conductive layer 11' forms a conductive layer 14, and the conductive layer 14 includes a wire 14a; wherein, when the conductive layer 14 is one layer, a single layer The wires 14 a of the conductive layer 14 form the coil 11 ; when the conductive layer 14 has two layers, the wires 14 a of the two conductive layers 14 are electrically connected to form the coil 11 .

可选地，采用黄光刻蚀工艺，在导体层11’的表面涂覆光刻胶，对光刻胶先后进行软烤、曝光、显影、硬烤等工艺形成光刻胶掩膜板，接着对导体层11’进行刻蚀，以得到导电层14，导电层14包括导线14a，导线14a形成线圈11。关于导电层14、线圈11的详细描述请参见上述实施例对应部分的描述，在此不再赘述。Optionally, a yellow photolithography process is used to coat photoresist on the surface of the conductor layer 11', and the photoresist is successively subjected to processes such as soft baking, exposure, development, and hard baking to form a photoresist mask, and then The conductive layer 11 ′ is etched to obtain the conductive layer 14 , the conductive layer 14 includes wires 14 a , and the wires 14 a form the coil 11 . For detailed descriptions of the conductive layer 14 and the coil 11 , please refer to the descriptions of the corresponding parts of the above embodiments, which will not be repeated here.

请参见图18，在一些实施例中，当第一基板10’包括两层导体层11’且线圈11由两层导体层11’刻蚀形成的导线14a形成时，电路板10的制备方法包括：Referring to FIG. 18, in some embodiments, when the first substrate 10' includes two conductor layers 11' and the coil 11 is formed by conducting wires 14a formed by etching the two conductor layers 11', the preparation method of the circuit board 10 includes :

S2011a，提供第一基板10’，第一基板10’包括介电层12及设置于介电层12相背的两个表面的两层导体层11’；S2011a, providing a first substrate 10', the first substrate 10' comprising a dielectric layer 12 and two layers of conductor layers 11' disposed on two surfaces opposite to the dielectric layer 12;

关于步骤S2011a的详细描述请参见上述实施例对应部分的描述，在此不再赘述。For a detailed description of step S2011a, please refer to the description of the corresponding part of the above embodiment, and details are not repeated here.

S2012a，在第一基板10’的介电层12及两层导体层11’中的至少一层的预设位置形成第一过孔101；S2012a, forming a first via hole 101 at a preset position of at least one of the dielectric layer 12 and the two conductor layers 11' of the first substrate 10';

可选地，第一过孔101可以为通孔、也可以为盲孔；当第一过孔101为通孔时介电层12及两层导体层11’均被打穿；当第一过孔101为盲孔时，介电层12与两层导体中的至少一层被打穿。第一过孔101可以采用激光进行打孔。Optionally, the first via hole 101 can be a through hole or a blind hole; when the first via hole 101 is a through hole, the dielectric layer 12 and the two conductor layers 11' are pierced; When the hole 101 is a blind hole, at least one of the dielectric layer 12 and the two layers of conductors is punched through. The first via hole 101 may be drilled with a laser.

S2013a，对第一基板10’的两层导体层11’进行刻蚀，以使导体层11’形成导电层14，导电层14包括导线14a；S2013a, etching the two conductor layers 11' of the first substrate 10', so that the conductor layer 11' forms a conductive layer 14, and the conductive layer 14 includes a wire 14a;

关于步骤S2013a的详细描述请参见上述实施例对应部分的描述，在此不再赘述。For a detailed description of step S2013a, please refer to the description of the corresponding part of the above embodiment, and details are not repeated here.

S2014a，在第一过孔101中沉积导电材料，以将两层导电层14中的导线14a电连接形成线圈11。S2014a, deposit a conductive material in the first via hole 101 to electrically connect the wires 14a in the two conductive layers 14 to form the coil 11 .

具体地，可以采用物理气相沉积法(简称PVD)或电沉积法等沉积方法在第一过孔101中沉积导电材料，以将两层导电层14中的导线14a电连接形成线圈11。导电材料可以为但不限于为铜、银等金属或合金。Specifically, a deposition method such as physical vapor deposition (PVD for short) or electrodeposition can be used to deposit conductive material in the first via hole 101 to electrically connect the wires 14 a in the two conductive layers 14 to form the coil 11 . The conductive material may be, but not limited to, metals or alloys such as copper and silver.

本实施例与上述实施例相同特征部分的详细描述请参见上述实施例，在此不再赘述。For a detailed description of the same features of this embodiment and the above embodiment, please refer to the above embodiment, and details are not repeated here.

请参见图19及图20，在一些实施例中，当电路板10包括至少三层导电层14时，电路板10的制备方法包括：Referring to FIG. 19 and FIG. 20, in some embodiments, when the circuit board 10 includes at least three conductive layers 14, the method for preparing the circuit board 10 includes:

S2011b，提供第一基板10’，第一基板10’包括介电层12及设置于介电层12相背的两个表面的两层导体层11’；S2011b, providing a first substrate 10', the first substrate 10' comprising a dielectric layer 12 and two layers of conductor layers 11' disposed on two surfaces opposite to the dielectric layer 12;

S2012b，在第一基板10’的介电层12及两层导体层11’中的至少一层的预设位置形成第一过孔101；S2012b, forming a first via hole 101 at a preset position of at least one of the dielectric layer 12 and the two conductor layers 11' of the first substrate 10';

S2013b，对第一基板10’的两层导体层11’进行刻蚀，以使导体层11’形成导电层14，导电层14包括导线14a；S2013b, etching the two conductor layers 11' of the first substrate 10', so that the conductor layer 11' forms a conductive layer 14, and the conductive layer 14 includes a wire 14a;

S2014b，在第一过孔101中沉积导电材料，以将第一基板10’的两层导电层14中的导线14a电连接；S2014b, depositing a conductive material in the first via hole 101, so as to electrically connect the wires 14a in the two conductive layers 14 of the first substrate 10';

关于步骤S2011b至S2014b的详细描述请参见上述实施例对应部分的描述，在此不再赘述。For the detailed description of steps S2011b to S2014b, please refer to the description of the corresponding part of the above embodiment, and details are not repeated here.

S2015b，提供第二基板10”，第二基板10”包括介电层12及设置于介电层12表面的导体层11’；S2015b, providing a second substrate 10", the second substrate 10" includes a dielectric layer 12 and a conductor layer 11' disposed on the surface of the dielectric layer 12;

关于介电层12与导体层11’的详细描述请参见上述实施例对应部分的描述，在此不再赘述。For a detailed description of the dielectric layer 12 and the conductive layer 11', please refer to the description of the corresponding part of the above embodiment, and details are not repeated here.

S2016b，在第二基板10”的介电层12及导体层11’的预设位置形成第二过孔；S2016b, forming second via holes at predetermined positions of the dielectric layer 12 and the conductor layer 11' of the second substrate 10";

可选地，第二过孔为通孔；换言之，介电层12及两层导体层11’均被打穿。第二过孔可以采用激光进行打孔。Optionally, the second via hole is a through hole; in other words, both the dielectric layer 12 and the two conductor layers 11' are pierced. The second via hole may be drilled by laser.

S2017b，对第二基板10”的导体层11’进行刻蚀，以得到导线14a；S2017b, etching the conductor layer 11' of the second substrate 10" to obtain the wire 14a;

S2018b，将第一基板10’与第二基板10”压合；S2018b, pressing the first substrate 10' and the second substrate 10";

可选地，将第一基板10’与至少一个第二基板10”叠合，叠合第一基板10’的导电层14面向第二基板10”的介电层12叠合，以使得导电层14与介电层12可以形成依次交替层叠的结构，叠合后通过热压等方式将第一基板10’与第二基板10”粘合到一起，形成一体结构。Optionally, the first substrate 10' is stacked with at least one second substrate 10", and the conductive layer 14 of the stacked first substrate 10' faces the dielectric layer 12 of the second substrate 10", so that the conductive layer 14 and the dielectric layer 12 may form a structure alternately laminated in sequence, and after lamination, the first substrate 10 ′ and the second substrate 10 ″ are bonded together by hot pressing or the like to form an integrated structure.

S2019b，在第二过孔中沉积导电材料，以将第一基板10’的导线14a与第二基板10”的导线14a电连接，得到电路板10，其中，电路板10包括至少一层介电层12及至少一层导电层14；介电层12与导电层14依次交替层叠设置；其中，每层导电层14包括导线14a；任意相邻的两层导电层14的导线14a电连接，形成线圈11。S2019b, deposit a conductive material in the second via hole, so as to electrically connect the wire 14a of the first substrate 10' and the wire 14a of the second substrate 10", and obtain the circuit board 10, wherein the circuit board 10 includes at least one layer of dielectric layer 12 and at least one conductive layer 14; the dielectric layer 12 and the conductive layer 14 are stacked alternately in sequence; wherein, each layer of conductive layer 14 includes a wire 14a; the wires 14a of any adjacent two layers of conductive layer 14 are electrically connected to form Coil 11.

请参见图21，本申请实施例还提供了一种电路板集成电感100的制备方法，其包括：Please refer to FIG. 21 , the embodiment of the present application also provides a method for preparing a circuit board integrated inductor 100, which includes:

S301，提供电路板10，电路板10嵌设有线圈11；S301, providing a circuit board 10, the circuit board 10 is embedded with a coil 11;

关于步骤S301的详细描述请参见上述实施例对应部分的描述，在此不再赘述。For a detailed description of step S301, please refer to the description of the corresponding part of the above embodiment, and details are not repeated here.

S302，在电路板10相背的两个表面中的至少一个表面上形成绝缘层50，并使绝缘层50至少覆盖线圈11；S302, forming an insulating layer 50 on at least one of the two opposite surfaces of the circuit board 10, and making the insulating layer 50 cover at least the coil 11;

可选地，可以通过物理气相沉积、原子层沉积或者其它镀膜工艺在电路板10相背的两个表面中的至少一个表面上形成绝缘层50，并使绝缘层50至少覆盖线圈11。Optionally, the insulating layer 50 can be formed on at least one of the two opposite surfaces of the circuit board 10 by physical vapor deposition, atomic layer deposition or other coating processes, and the insulating layer 50 at least covers the coil 11 .

S303，在绝缘层50背离电路板10的表面形成磁胶层20；以及S303, forming the magnetic glue layer 20 on the surface of the insulating layer 50 away from the circuit board 10; and

S304，在磁胶层20背离电路板10的一侧设置磁膜层30。S304, disposing the magnetic film layer 30 on the side of the magnetic glue layer 20 away from the circuit board 10 .

关于步骤S303及步骤304的详细描述请参见上述实施例对应部分的描述，在此不再赘述。本实施例与上述实施例相同特征部分的详细描述请参见上述实施例，在此不再赘述。For a detailed description of step S303 and step 304, please refer to the description of the corresponding part of the above embodiment, and details are not repeated here. For a detailed description of the same features of this embodiment and the above embodiment, please refer to the above embodiment, and details are not repeated here.

以下通过具体示例对本申请实施例的电路板集成电感100做进一步说明。The circuit board integrated inductor 100 of the embodiment of the present application will be further described below through specific examples.

示例1Example 1

本示例的电路板集成电感100包括电路板10，电路板10包括介电层12及线圈11。介电层12为聚酰亚胺层，聚酰亚胺的厚度为12.5μm。线圈11部分嵌设于聚酰亚胺层中且部分裸露于聚酰亚胺相背的两个表面上，线圈11为铜线圈11，线圈11的匝数为1匝。铜线圈11的线宽为200μm，铜线圈11的线厚为100μm，铜线圈11的线距为150μm。本示例的电路板集成电感100还包括磁胶层20及磁膜层30，磁胶层20与磁膜层30依次叠设于电路板10相背的两个表面上，且至少覆盖线圈11(即，电路板10的相对两侧均依次层叠磁胶层20及磁膜层30)，磁胶层20的厚度为220μm，磁胶层20的相对磁导率为13。磁膜层30的厚度为30μm。磁膜层30为FeNi合金层。FeNi合金层的相对磁导率为800，电导率为40KS/m。The circuit board integrated inductor 100 of this example includes a circuit board 10 , and the circuit board 10 includes a dielectric layer 12 and a coil 11 . The dielectric layer 12 is a polyimide layer, and the thickness of the polyimide is 12.5 μm. The coil 11 is partially embedded in the polyimide layer and partially exposed on two opposite surfaces of the polyimide. The coil 11 is a copper coil 11 , and the number of turns of the coil 11 is 1 turn. The line width of the copper coil 11 is 200 μm, the line thickness of the copper coil 11 is 100 μm, and the line pitch of the copper coil 11 is 150 μm. The circuit board integrated inductor 100 of this example also includes a magnetic glue layer 20 and a magnetic film layer 30. The magnetic glue layer 20 and the magnetic film layer 30 are sequentially stacked on the two opposite surfaces of the circuit board 10, and at least cover the coil 11 ( That is, the magnetic glue layer 20 and the magnetic film layer 30 are sequentially stacked on opposite sides of the circuit board 10 , the thickness of the magnetic glue layer 20 is 220 μm, and the relative permeability of the magnetic glue layer 20 is 13. The thickness of the magnetic film layer 30 is 30 μm. The magnetic film layer 30 is a FeNi alloy layer. The relative magnetic permeability of the FeNi alloy layer is 800, and the electrical conductivity is 40KS/m.

对比例1Comparative example 1

本对比例的电路板集成电感100包括电路板10、电路板10包括介电层12及线圈11。介电层12为聚酰亚胺层，聚酰亚胺的厚度为12.5μm。线圈11部分嵌设于聚酰亚胺层中且部分裸露于聚酰亚胺相背的两个表面上，线圈11为铜线圈11，线圈11的匝数为1匝。铜线圈11的线宽为200μm，铜线圈11的线厚为100μm，铜线圈11的线距为150μm。本对比例的电路板集成电感100还包括磁胶层20，磁胶层20设置于电路板10相背的两个表面上，磁胶层20的厚度为220μm，磁胶层20的相对磁导率为13。The circuit board integrated inductor 100 of this comparative example includes a circuit board 10 , and the circuit board 10 includes a dielectric layer 12 and a coil 11 . The dielectric layer 12 is a polyimide layer, and the thickness of the polyimide is 12.5 μm. The coil 11 is partially embedded in the polyimide layer and partially exposed on two opposite surfaces of the polyimide. The coil 11 is a copper coil 11 , and the number of turns of the coil 11 is 1 turn. The line width of the copper coil 11 is 200 μm, the line thickness of the copper coil 11 is 100 μm, and the line pitch of the copper coil 11 is 150 μm. The circuit board integrated inductor 100 of this comparative example also includes a magnetic glue layer 20, the magnetic glue layer 20 is arranged on the two opposite surfaces of the circuit board 10, the thickness of the magnetic glue layer 20 is 220 μm, and the relative magnetic permeability of the magnetic glue layer 20 The rate is 13.

对比例2Comparative example 2

本对比例的电路板集成电感100包括电路板10、电路板10包括介电层12及线圈11。介电层12为聚酰亚胺层，聚酰亚胺的厚度为12.5μm。线圈11部分嵌设于聚酰亚胺层中且部分裸露于聚酰亚胺相背的两个表面上，线圈11为铜线圈11，线圈11的匝数为1匝。铜线圈11的线宽为200μm，铜线圈11的线厚为100μm，铜线圈11的线距为150μm。本对比例的电路板集成电感100还包括磁膜层30，磁膜层30设置于电路板10相背的两个表面上，磁膜层30的厚度为30μm。磁膜层30为FeNi合金层。FeNi合金层的相对磁导率为800，电导率为40KS/m。The circuit board integrated inductor 100 of this comparative example includes a circuit board 10 , and the circuit board 10 includes a dielectric layer 12 and a coil 11 . The dielectric layer 12 is a polyimide layer, and the thickness of the polyimide is 12.5 μm. The coil 11 is partially embedded in the polyimide layer and partially exposed on two opposite surfaces of the polyimide. The coil 11 is a copper coil 11 , and the number of turns of the coil 11 is 1 turn. The line width of the copper coil 11 is 200 μm, the line thickness of the copper coil 11 is 100 μm, and the line pitch of the copper coil 11 is 150 μm. The circuit board integrated inductor 100 of this comparative example further includes a magnetic film layer 30 disposed on two opposite surfaces of the circuit board 10 , and the thickness of the magnetic film layer 30 is 30 μm. The magnetic film layer 30 is a FeNi alloy layer. The relative magnetic permeability of the FeNi alloy layer is 800, and the electrical conductivity is 40KS/m.

根据标准GB/T 8554-1998进行模拟计算，得到示例1、对比例1及对比例2得到的电路板集成电感100的感量如下表1所示。According to the simulation calculation of the standard GB/T 8554-1998, the inductance of the circuit board integrated inductor 100 obtained in Example 1, Comparative Example 1 and Comparative Example 2 is shown in Table 1 below.

表1示例1及对比例1的电路板集成电感100的模拟测试数据The simulation test data of the circuit board integrated inductance 100 of table 1 example 1 and comparative example 1

示例example	示例1Example 1	对比例1Comparative example 1	对比例2Comparative example 2
磁胶层厚度(μm)Magnet layer thickness (μm)	220220	220220	//
磁膜层厚度(μm)Magnetic film thickness (μm)	3030	//	3030
感量(nH)Sensitivity (nH)	23twenty three	7.97.9	6.96.9

由表1的模拟计算结果可知，相较于只有磁胶层20作为磁性层，或者磁膜层30作为磁性层的方案，采用磁胶层20与磁膜层30共同作为电路板集成电感100的磁性层，电路板集成电感100的感量大大增加，且感量远超过单独磁胶层20的电感量和单独磁膜层30的电感量的累加值。From the simulation calculation results in Table 1, it can be seen that compared with the scheme in which only the magnetic glue layer 20 is used as the magnetic layer, or the magnetic film layer 30 is used as the magnetic layer, the use of the magnetic glue layer 20 and the magnetic film layer 30 together as the circuit board integrated inductor 100 The magnetic layer, the inductance of the circuit board integrated inductor 100 is greatly increased, and the inductance far exceeds the cumulative value of the inductance of the magnetic glue layer 20 alone and the inductance of the magnetic film layer 30 alone.

对比例3至对比例4本对比例的电路板集成电感100与对比例1的电路板集成电感100的不同之处在于磁胶层20的厚度不同，其他结构及参数均相同。Comparative Examples 3 to 4 The circuit board integrated inductor 100 of this comparative example is different from the circuit board integrated inductor 100 of Comparative Example 1 in that the thickness of the magnetic glue layer 20 is different, and other structures and parameters are the same.

对比例5至对比例6本对比例的电路板集成电感100与对比例2的电路板集成电感100的不同之处在于磁膜层30的厚度不同，其他结构及参数均相同。Comparative Examples 5 to 6 The difference between the circuit board integrated inductor 100 of this comparative example and the circuit board integrated inductor 100 of Comparative Example 2 is that the thickness of the magnetic film layer 30 is different, and other structures and parameters are the same.

根据标准GB/T 8554-1998进行模拟计算，得到对比例1至对比例6得到的电路板集成电感100的感量如下表2所示。According to the simulation calculation according to the standard GB/T 8554-1998, the inductance of the circuit board integrated inductor 100 obtained in Comparative Example 1 to Comparative Example 6 is shown in Table 2 below.

表2对比例1至对比例6的电路板集成电感100的模拟测试数据The simulated test data of the circuit board integrated inductor 100 of Table 2 Comparative Example 1 to Comparative Example 6

示例example	对比例1Comparative example 1	对比例3Comparative example 3	对比例4Comparative example 4	对比例2Comparative example 2	对比例5Comparative example 5	对比例6Comparative example 6
磁胶层厚度(μm)Magnet layer thickness (μm)	220220	500500	20002000	//	//	//
磁膜层厚度(μm)Magnetic film thickness (μm)	//	//	//	3030	6060	9090
感量(nH)Sensitivity (nH)	7.97.9	13.613.6	17.117.1	6.96.9	7.17.1	7.27.2

由表2中对比例1、对比例3及对比例4的测试数据可知，随着磁胶层20的厚度增加，电路板集成电感100的感量也随着增加，但是感量的增加远远低于磁胶层20厚度的增加，当磁胶层20的厚度提高至接近10倍时，感量仅增加至两倍多，且感量低于厚度较薄的磁胶层20、磁膜层30组合的示例1。由表2中对比例2、对比例5及对比例6的测试数据可知，随着磁膜层30的厚度增加，电路板集成电感100的感量也随着增加，但是感量的增加远远低于磁膜层30厚度的增加，当磁膜的层厚度分别提高至两倍、三倍时，感量的变化幅度很小。From the test data of Comparative Example 1, Comparative Example 3 and Comparative Example 4 in Table 2, it can be seen that as the thickness of the magnetic glue layer 20 increases, the inductance of the circuit board integrated inductor 100 also increases, but the increase in inductance is far from Below the increase of the thickness of the magnetic glue layer 20, when the thickness of the magnetic glue layer 20 is increased to nearly 10 times, the inductance is only increased to more than twice, and the inductance is lower than that of the thinner magnetic glue layer 20 and magnetic film layer. Example 1 of 30 combinations. From the test data of Comparative Example 2, Comparative Example 5 and Comparative Example 6 in Table 2, it can be seen that as the thickness of the magnetic film layer 30 increases, the inductance of the circuit board integrated inductor 100 also increases, but the increase in inductance is far from Compared with the increase of the thickness of the magnetic film layer 30 , when the layer thickness of the magnetic film is increased to two times and three times respectively, the variation range of the inductance is very small.

请参见图22及图23，本申请实施例还提供了一种电感400，其包括：线圈层410、磁胶层20以及磁膜层30。线圈层410具有线圈11；磁胶层20设置于线圈层410相背两侧中的至少一侧上；磁膜层30设置于磁胶层20背离线圈层410的一侧，其中，磁膜层30的磁导率大于磁胶层20的磁导率。Referring to FIG. 22 and FIG. 23 , the embodiment of the present application also provides an inductor 400 , which includes: a coil layer 410 , a magnetic glue layer 20 and a magnetic film layer 30 . The coil layer 410 has a coil 11; the magnetic glue layer 20 is arranged on at least one side of the opposite sides of the coil layer 410; the magnetic film layer 30 is arranged on the side of the magnetic glue layer 20 away from the coil layer 410, wherein the magnetic film layer The magnetic permeability of 30 is greater than that of the magnetic glue layer 20 .

可选地，线圈层410中线圈11的数量以为一个，也可以为多个，例如，可以为但不限于为1个、2个、3个等，线圈11的具体数量可以根据实际应用需求进行设定，本申请不作具体限定。多个指两个以上或大于等于两个。Optionally, the number of coils 11 in the coil layer 410 can be one or more, for example, but not limited to 1, 2, 3, etc. The specific number of coils 11 can be determined according to actual application requirements. setting, which is not specifically limited in this application. Multiple refers to two or more or greater than or equal to two.

本实施例的电感400将磁胶层20与磁膜层30结合共同作为电感400的磁性层，相较于仅有磁胶层20或磁膜层30的情况下，得到的电感400的感量大大增加，远超过单独磁胶层20的电感和单独磁膜层30的电感的感量累加值，从而可以更好的实现超薄高感，有利于电子设备的超薄化、小型化。The inductor 400 of this embodiment combines the magnetic glue layer 20 and the magnetic film layer 30 together as the magnetic layer of the inductor 400. Compared with the case of only the magnetic glue layer 20 or the magnetic film layer 30, the inductance of the inductor 400 obtained Greatly increased, far exceeding the cumulative inductance value of the inductance of the single magnetic glue layer 20 and the single magnetic film layer 30, so that ultra-thin and high-inductance can be better realized, which is beneficial to the ultra-thin and miniaturization of electronic equipment.

在一些实施例中，磁胶层20包括树脂及磁性颗粒，磁性颗粒分散于树脂中；在磁胶层20中，磁性颗粒的重量分数的范围为85％至95％。详细描述请参见上述实施例对应部分的描述，在此不再赘述。In some embodiments, the magnetic glue layer 20 includes resin and magnetic particles, and the magnetic particles are dispersed in the resin; in the magnetic glue layer 20 , the weight fraction of the magnetic particles ranges from 85% to 95%. For detailed description, please refer to the description of the corresponding part of the foregoing embodiments, and details are not repeated here.

可选地，磁性颗粒的D90粒径的范围为：1μm≤D90≤10μm。详细描述请参见上述实施例对应部分的描述，在此不再赘述。Optionally, the range of D90 particle size of the magnetic particles is: 1 μm≤D90≤10 μm. For detailed description, please refer to the description of the corresponding part of the foregoing embodiments, and details are not repeated here.

可选地，磁性颗粒为软磁颗粒。详细描述请参见上述实施例对应部分的描述，在此不再赘述。Optionally, the magnetic particles are soft magnetic particles. For detailed description, please refer to the description of the corresponding part of the foregoing embodiments, and details are not repeated here.

可选地，树脂包括环氧树脂、聚氨酯及丙烯酸酯中的至少一种。详细描述请参见上述实施例对应部分的描述，在此不再赘述。Optionally, the resin includes at least one of epoxy resin, polyurethane and acrylate. For detailed description, please refer to the description of the corresponding part of the foregoing embodiments, and details are not repeated here.

可选地，沿线圈层410、磁胶层20及磁膜层30层叠方向上，磁胶层20的厚度h1的范围为50μm≤h1≤500μm。详细描述请参见上述实施例对应部分的描述，在此不再赘述。Optionally, along the stacking direction of the coil layer 410 , the magnetic glue layer 20 and the magnetic film layer 30 , the thickness h1 of the magnetic glue layer 20 is in a range of 50 μm≤h1≤500 μm. For detailed description, please refer to the description of the corresponding part of the foregoing embodiments, and details are not repeated here.

可选地，磁膜层30为软磁层。详细描述请参见上述实施例对应部分的描述，在此不再赘述。Optionally, the magnetic film layer 30 is a soft magnetic layer. For detailed description, please refer to the description of the corresponding part of the foregoing embodiments, and details are not repeated here.

在一些实施例中所述磁膜层30包括磁性合金，磁性合金为改性磁性合金。所述改性磁性合金包括铬掺杂的铁镍合金、铬掺杂的铁钴合金、铬掺杂的铁硅铝合金中的至少一种。磁性合金具有较高的相对磁导率，可以使得制得的电感400具有更大的感量，同时通过铬掺杂可以使得磁性合金的相对磁导率不会下降太多，大大降低磁性合金的等效电导率，从而增加磁膜层30的集肤深度。因此，可以通过提高磁膜层30的厚度，使得磁膜层30具有更高的饱和磁感应强度，且可以更好的分散磁通，降低磁膜层30应用时的最大磁感应强度，从而使得电感400可以更好的应用于较大电流的场景。In some embodiments, the magnetic film layer 30 includes a magnetic alloy, and the magnetic alloy is a modified magnetic alloy. The modified magnetic alloy includes at least one of chromium-doped iron-nickel alloy, chromium-doped iron-cobalt alloy and chromium-doped sendust. The magnetic alloy has a higher relative magnetic permeability, which can make the manufactured inductor 400 have a larger inductance. At the same time, the relative magnetic permeability of the magnetic alloy will not drop too much through chromium doping, which greatly reduces the Equivalent conductivity, thereby increasing the skin depth of the magnetic film layer 30 . Therefore, by increasing the thickness of the magnetic film layer 30, the magnetic film layer 30 has a higher saturation magnetic induction, and can better disperse the magnetic flux, reducing the maximum magnetic induction intensity when the magnetic film layer 30 is applied, so that the inductance 400 It can be better applied to the scene of large current.

请再次参见图12，在一些实施例中，所述磁膜层30包括依次交替层叠设置的磁膜子层31及金属氧化物层33，其中磁膜子层31可以为改性磁性合金层，金属氧化物层33包括改性磁性合金中的至少一种金属的氧化物。通过改性磁性合金与金属氧化物层33交替层叠设置，可以充分降低磁膜层30的等效电导率，但是又不会使磁膜层30的相对磁导率降低太多。Please refer to FIG. 12 again. In some embodiments, the magnetic film layer 30 includes magnetic film sublayers 31 and metal oxide layers 33 alternately stacked in sequence, wherein the magnetic film sublayer 31 can be a modified magnetic alloy layer, The metal oxide layer 33 includes an oxide of at least one metal in the modified magnetic alloy. By alternately laminating the modified magnetic alloy and the metal oxide layer 33 , the equivalent electrical conductivity of the magnetic film layer 30 can be sufficiently reduced without reducing the relative magnetic permeability of the magnetic film layer 30 too much.

请再次参见图13，在另一些实施例中，磁膜层30包括依次交替层叠设置的绝缘子层35及磁膜子层31，其中绝缘子层35包括二氧化硅、氧化铝中的至少一种，磁膜子层31包括改性磁性合金。通过无机绝缘层与磁性金属层的交替层叠设置，可以充分降低磁膜层30的等效电导率，但是又不会使磁膜层30的相对磁导率降低太多。Please refer to FIG. 13 again. In some other embodiments, the magnetic film layer 30 includes insulating sublayers 35 and magnetic film sublayers 31 alternately stacked in sequence, wherein the insulating sublayers 35 include at least one of silicon dioxide and aluminum oxide, The magnetic film sublayer 31 includes a modified magnetic alloy. The equivalent electrical conductivity of the magnetic film layer 30 can be sufficiently reduced by alternately stacking the inorganic insulating layer and the magnetic metal layer, but the relative magnetic permeability of the magnetic film layer 30 will not be reduced too much.

可选地，所述磁膜层的等效电导率σ的范围为4KS/m≤σ≤600KS/m；所述磁膜层的相对磁导率μr的范围为500≤μr≤6000。本实施例的磁膜层30在具有较高的相对磁导率的同时，具有较低的等效电导率，从而使得磁膜层30具有较厚的集肤深度及较高的感量。因此，可以通过增加磁膜层30的厚度提高磁膜层30的饱和磁感应强度，有效分散磁通，从而更好的适用于大电流的场景，此外还可以通过增加磁膜层30的厚度，提高电感400的感量，提高磁膜层30的利用率。Optionally, the range of the equivalent electrical conductivity σ of the magnetic film layer is 4KS/m≤σ≤600KS/m; the range of the relative permeability μr of the magnetic film layer is 500≤μr≤6000. The magnetic film layer 30 of this embodiment has a relatively low equivalent electrical conductivity while having a high relative magnetic permeability, so that the magnetic film layer 30 has a thicker skin depth and a higher inductance. Therefore, the saturation magnetic induction intensity of the magnetic film layer 30 can be improved by increasing the thickness of the magnetic film layer 30, and the magnetic flux can be effectively dispersed, thereby being better applicable to the scene of a large current. In addition, the thickness of the magnetic film layer 30 can be increased to improve The inductance of the inductor 400 improves the utilization rate of the magnetic film layer 30 .

所述磁膜层30的等效电导率σ的范围为4KS/m≤σ≤600KS/m；具体地，磁膜层30的电导率σ可以为但不限于为4KS/m、6KS/m、10KS/m、40KS/m、60KS/m、80KS/m、100KS/m、200KS/m、300KS/m、400KS/m、500KS/m、600KS/m等。在磁膜层30相对磁导率不变的情况下，磁膜层30的等效电导率σ越小，得到的磁膜层30的集肤深度越大，通过提高磁膜层30的厚度，可以更好的提高磁膜层30的饱和磁感应强度，从而使得电感400可以更好的应用于较大电流的场景。“等效电导率”指该磁膜层30等效为均相材料得到的电导率。The range of the equivalent electrical conductivity σ of the magnetic film layer 30 is 4KS/m≤σ≤600KS/m; specifically, the electrical conductivity σ of the magnetic film layer 30 can be but not limited to 4KS/m, 6KS/m, 10KS/m, 40KS/m, 60KS/m, 80KS/m, 100KS/m, 200KS/m, 300KS/m, 400KS/m, 500KS/m, 600KS/m, etc. Under the constant relative magnetic permeability of the magnetic film layer 30, the smaller the equivalent electrical conductivity σ of the magnetic film layer 30, the larger the skin depth of the magnetic film layer 30 obtained, by increasing the thickness of the magnetic film layer 30, The saturation magnetic induction of the magnetic film layer 30 can be better improved, so that the inductor 400 can be better applied to a scene with a large current. "Equivalent electrical conductivity" refers to the electrical conductivity obtained by equivalently using a homogeneous material as the magnetic film layer 30 .

所述磁膜层30的相对磁导率μr的范围为500≤μr≤6000；具体地，所述磁膜层30的相对磁导率μr可以为但不限于为500、800、1000、1500、2000、2500、3000、3500、4000、4500、5000、5500、6000等。磁膜层30的相对磁导率越小，则磁膜层30的集肤深度越大，但是，相对磁导率过低，会大大降低电感400的感量，因此，磁膜层30的相对磁导率不宜太低。The range of the relative permeability μr of the magnetic film layer 30 is 500≤μr≤6000; specifically, the relative permeability μr of the magnetic film layer 30 can be but not limited to 500, 800, 1000, 1500, 2000, 2500, 3000, 3500, 4000, 4500, 5000, 5500, 6000, etc. The smaller the relative magnetic permeability of the magnetic film layer 30 is, the larger the skin depth of the magnetic film layer 30 will be. However, if the relative magnetic permeability is too low, the inductance of the inductance 400 will be greatly reduced. The magnetic permeability should not be too low.

可选地，磁膜层30在1MHz的频率下的集肤深度δ的范围为8.40μm≤δ≤103μm。具体地，集肤深度δ可以为但不限于为8.4μm、10μm、12.5μm、15μm、17.5μm、20μm、30μm、40μm、50μm、60μm、70μm、80μm、90μm、96μm、103μm等。集肤深度越大，可以更好的通过增加磁膜层30的厚度来提高磁膜层30的饱和磁感应强度，从而更好的分散磁通，使得电感400可以更好的适用于大电流的场景，同时，也可以更好的通过增加磁膜层30的厚度来提高电感400的感量，从而使得磁膜层30可以做得更厚。本申请的磁膜层30具有较高的集肤深度，从而可以更好的分散磁通，降低磁膜层30中的最大磁感应强度(Bm)，同时又具有较高的感量，从而使用具有较小的饱和磁感应强度的材料就可以获得具有较大感量的电感。可选地，沿线圈层410、磁胶层20及磁膜层30层叠方向上，磁膜层30的厚度h2的范围为5μm≤h2≤35μm。详细描述请参见上述实施例对应部分的描述，在此不再赘述。Optionally, the skin depth δ of the magnetic film layer 30 at a frequency of 1 MHz is in the range of 8.40 μm≤δ≤103 μm. Specifically, the skin depth δ may be, but not limited to, 8.4 μm, 10 μm, 12.5 μm, 15 μm, 17.5 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 96 μm, 103 μm, etc. The larger the skin depth, the better the saturation magnetic induction of the magnetic film layer 30 can be increased by increasing the thickness of the magnetic film layer 30, so as to better disperse the magnetic flux, so that the inductor 400 can be better applied to the scene of high current At the same time, the inductance of the inductor 400 can be improved by increasing the thickness of the magnetic film layer 30, so that the magnetic film layer 30 can be made thicker. The magnetic film layer 30 of the present application has a higher skin depth, which can better disperse the magnetic flux, reduce the maximum magnetic induction intensity (Bm) in the magnetic film layer 30, and have a higher inductance at the same time, thereby using A material with a smaller saturation magnetic induction can obtain an inductance with a larger inductance. Optionally, along the stacking direction of the coil layer 410 , the magnetic glue layer 20 and the magnetic film layer 30 , the thickness h2 of the magnetic film layer 30 is in a range of 5 μm≤h2≤35 μm. For detailed description, please refer to the description of the corresponding part of the foregoing embodiments, and details are not repeated here.

以下通过具体实施例对本申请的电感做进一步的说明。以下各实施例和对比例中，以磁膜层30的长1.6mm，宽为0.8mm的电感400进行模拟计算，其中，电感400中通过的最大电流为3A，应用频率为1MHz，线圈11匝数为1匝。磁膜层30的材料以铁镍合金或改性铁镍合金为例进行模拟计算。The inductor of the present application will be further described through specific examples below. In the following embodiments and comparative examples, the magnetic film layer 30 has a length of 1.6mm and a width of 0.8mm for the inductance 400 to carry out simulation calculations, wherein the maximum current passing through the inductance 400 is 3A, the application frequency is 1MHz, and the coil has 11 turns The number is 1 turn. The material of the magnetic film layer 30 is simulated by taking iron-nickel alloy or modified iron-nickel alloy as an example.

实施例1至实施例9及对比例7至对比例9 Embodiment 1 to embodiment 9 and comparative example 7 to comparative example 9

本实施例及对比例的电感400包括衬底，衬底上嵌设有线圈11。衬底为聚酰亚胺层，聚酰亚胺的厚度为12.5μm。线圈11部分嵌设于聚酰亚胺层中且部分裸露于聚酰亚胺相背的两个表面上，线圈11为铜线圈11。铜线圈11的线宽为200μm，铜线圈11的线厚为100μm，铜线圈11的线距为150μm。本实施例及对比例的电感400还包括磁胶层20及磁膜层30，磁胶层20与磁膜层30依次叠设于衬底相背的两个表面上，且至少覆盖线圈11，磁胶层20的厚度为60μm，磁胶层20的相对磁导率为13，磁膜层30的相对磁导率为6000，进行模拟计算时，假定磁膜层的相对磁导率为各向同性的。磁膜层30的相关参数如下表3、表4及表5所示。The inductor 400 of this embodiment and the comparative example includes a substrate on which a coil 11 is embedded. The substrate is a polyimide layer, and the thickness of the polyimide is 12.5 μm. The coil 11 is partially embedded in the polyimide layer and partially exposed on two opposite surfaces of the polyimide, and the coil 11 is a copper coil 11 . The line width of the copper coil 11 is 200 μm, the line thickness of the copper coil 11 is 100 μm, and the line pitch of the copper coil 11 is 150 μm. The inductor 400 of this embodiment and the comparative example also includes a magnetic glue layer 20 and a magnetic film layer 30, and the magnetic glue layer 20 and the magnetic film layer 30 are sequentially stacked on two surfaces opposite to the substrate, and at least cover the coil 11, The thickness of the magnetic glue layer 20 is 60 μm, the relative magnetic permeability of the magnetic glue layer 20 is 13, and the relative magnetic permeability of the magnetic film layer 30 is 6000. When performing simulation calculations, it is assumed that the relative magnetic permeability of the magnetic film layer is anisotropic. Same sex. The relevant parameters of the magnetic film layer 30 are shown in Table 3, Table 4 and Table 5 below.

根据标准GB/T 8554-1998进行模拟计算，得到各实施例及对比例的电感400的各数值如下表3、表4及表5所示。Carry out simulation calculation according to standard GB/T 8554-1998, obtain each numerical value of the inductance 400 of each embodiment and comparative example as shown in table 3, table 4 and table 5 below.

表3对比例7至对比例9的电感400的模拟测试数据The simulation test data of the inductance 400 of table 3 comparative example 7 to comparative example 9

由上表3中对比例7至对比例9可知，当电导率为1700KS/m时，磁膜层30的集肤深度约为5μm，对比例7至对比例9的磁膜层30的厚度均超出了此时的集肤深度，因此，磁膜层30厚度由10μm增加至30μm、50μm后，最大磁感应强度Bm下降很少，感量增加也很小，L/Bm略有增加，这说明此时难以通过增加磁膜层30的厚度来有效分散磁通，从而降低磁膜层30的最大磁感应强度Bm，以提高L/Bm的数值。From Comparative Example 7 to Comparative Example 9 in Table 3 above, it can be seen that when the electrical conductivity is 1700KS/m, the skin depth of the magnetic film layer 30 is about 5 μm, and the thickness of the magnetic film layer 30 in Comparative Example 7 to Comparative Example 9 is about 5 μm. The skin depth at this time is exceeded. Therefore, after the thickness of the magnetic film layer 30 increases from 10 μm to 30 μm and 50 μm, the maximum magnetic induction intensity Bm decreases very little, the inductance increases very little, and L/Bm increases slightly, which shows that this Sometimes it is difficult to effectively disperse the magnetic flux by increasing the thickness of the magnetic film layer 30 , thereby reducing the maximum magnetic induction Bm of the magnetic film layer 30 to increase the value of L/Bm.

表4实施例1至实施例5的电感400的模拟测试数据The simulation test data of the inductance 400 of table 4 embodiment 1 to embodiment 5

由上表4可知，当电导率降为40K S/m时，磁膜层30的集肤深度约为131μm，由实施例1至实施例5的模拟数据可知，当磁膜层30的厚度由10μm逐渐增加至50μm时，感量L的增幅不是很明显，但是磁膜层30的最大磁感应强度Bm大大增加，L/Bm也大大增加，当磁膜层30厚度增加为原来的五倍时，L/Bm也相应增大至原来的近四倍。这说明在集肤深度范围内，磁膜层30厚度的增加可以有效分散磁通，降低Bm，从而使得电感400只需要较小的Bm就可以获得较大的感量L，进而可以利用较小饱和磁感应强度的材料制作大感量的电感400。As can be seen from the above table 4, when the electrical conductivity is reduced to 40K S/m, the skin depth of the magnetic film layer 30 is about 131 μm. From the simulation data of Embodiment 1 to Embodiment 5, it can be known that when the thickness of the magnetic film layer 30 is by When 10 μm gradually increases to 50 μm, the increase of the inductance L is not very obvious, but the maximum magnetic induction intensity Bm of the magnetic film layer 30 increases greatly, and L/Bm also increases greatly. When the thickness of the magnetic film layer 30 increases to five times of the original, L/Bm also increased to nearly four times the original. This shows that within the skin depth range, the increase in the thickness of the magnetic film layer 30 can effectively disperse the magnetic flux and reduce Bm, so that the inductor 400 can obtain a larger inductance L with only a smaller Bm, and then can use a smaller The inductance 400 with large inductance is made of a material with saturated magnetic induction.

表5实施例6至实施例9的电感400的模拟测试数据The simulation test data of the inductance 400 of table 5 embodiment 6 to embodiment 9

由上表5可知，当磁膜层30的厚度不变，电导率逐渐增加时，则磁膜层30的集肤深度逐渐降低，磁膜层30的最大磁感应强度Bm逐渐增加，感量L基本不变，L/Bm逐渐降低。这说明，当磁膜层30厚度相同时，通过降低磁膜层30的电导率，可以大大降低磁膜层30的最大磁感应强度Bm，从而大大提高L/Bm；当电导率由600kS/m降低至4kS/m时，L/Bm由3.8nH/T升高至13.6nH/T，提高了接近四倍。这说明通过降低磁膜层30的电导率，可以有效降低磁膜层30的最大磁感应强度Bm，从而使得电感400只需要较小的Bm就可以获得较大的感量L，进而可以利用较小饱和磁感应强度的材料制作大感量的电感400。As can be seen from Table 5 above, when the thickness of the magnetic film layer 30 is constant and the electrical conductivity gradually increases, the skin depth of the magnetic film layer 30 gradually decreases, the maximum magnetic induction Bm of the magnetic film layer 30 gradually increases, and the inductance L is basically unchanged, L/Bm gradually decreased. This shows that when the thickness of the magnetic film layer 30 is the same, by reducing the electrical conductivity of the magnetic film layer 30, the maximum magnetic induction intensity Bm of the magnetic film layer 30 can be greatly reduced, thereby greatly improving L/Bm; when the electrical conductivity is reduced by 600kS/m When it reaches 4kS/m, L/Bm increases from 3.8nH/T to 13.6nH/T, an increase of nearly four times. This shows that by reducing the electrical conductivity of the magnetic film layer 30, the maximum magnetic induction intensity Bm of the magnetic film layer 30 can be effectively reduced, so that the inductance 400 can obtain a larger inductance L with only a smaller Bm, and then can use a smaller The inductance 400 with large inductance is made of a material with saturated magnetic induction.

请参见图24，在一些实施例中，本申请实施例的电感400还包括衬底430，衬底430用于承载线圈层410。在一些实施例中，线圈层410可以嵌设于衬底430中。具体地，线圈层410可以部分位于衬底430内部，部分位于衬底430表面；也可以全部位于衬底430内部。在另一些实施例中，线圈层410设置于衬底430的至少一个表面上。Please refer to FIG. 24 , in some embodiments, the inductor 400 of the embodiment of the present application further includes a substrate 430 for carrying the coil layer 410 . In some embodiments, the coil layer 410 may be embedded in the substrate 430 . Specifically, the coil layer 410 may be partly located inside the substrate 430 , partly located on the surface of the substrate 430 , or entirely located inside the substrate 430 . In other embodiments, the coil layer 410 is disposed on at least one surface of the substrate 430 .

可选地，衬底430可以为但不限于为聚酰亚胺层、玻纤/环氧树脂复合板、聚乙烯、聚四氟乙烯等，本申请不作具体限定。可选地，衬底430的厚度为10μm至50μm；具体地，可以为但不限于为10μm、15μm、20μm、25μm、30μm、35μm、40μm、45μm、50μm等。衬底430的厚度太小，如小于10μm时，则衬底430的力学性能有限，难以对线圈11起到有效支撑作用；由于衬底430的磁导率很低，衬底430的厚度过大，例如大于50μm时，则会增加磁路的长度，使得磁阻增大，不利于得到的电感400的性能。Optionally, the substrate 430 may be, but not limited to, a polyimide layer, a glass fiber/epoxy resin composite board, polyethylene, polytetrafluoroethylene, etc., which are not specifically limited in this application. Optionally, the thickness of the substrate 430 is 10 μm to 50 μm; specifically, it can be but not limited to 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc. The thickness of the substrate 430 is too small, such as when less than 10 μm, the mechanical properties of the substrate 430 are limited, and it is difficult to effectively support the coil 11; because the magnetic permeability of the substrate 430 is very low, the thickness of the substrate 430 is too large , for example, if it is greater than 50 μm, the length of the magnetic circuit will be increased, so that the reluctance will increase, which is not conducive to the performance of the obtained inductor 400 .

在一些实施例中，本申请实施例的电感400还包括绝缘层50，绝缘层50设置于线圈层410与磁胶层20之间，用于使线圈层410与磁胶层20绝缘设置。关于绝缘层50的详细描述请参见上述实施例对应部分的描述，在此不再赘述。In some embodiments, the inductor 400 of the embodiment of the present application further includes an insulating layer 50 disposed between the coil layer 410 and the magnetic glue layer 20 for insulating the coil layer 410 from the magnetic glue layer 20 . For a detailed description of the insulating layer 50 , please refer to the description of the corresponding part of the above embodiment, and details are not repeated here.

请参见图25，本申请实施例还提供一种电源管理芯片500，电源管理芯片500包括电源电路510及本申请上述实施例的电感400，电感400与电源电路510电连接。Please refer to FIG. 25 , the embodiment of the present application also provides a power management chip 500 , the power management chip 500 includes a power circuit 510 and the inductor 400 in the above embodiment of the present application, and the inductor 400 is electrically connected to the power circuit 510 .

电源管理芯片500(Power Management Integrated Circuits)，可以在电子设备***中担负起对电能的变换、分配、检测及其他电能管理的职责。电源管理芯片500主要负责识别CPU供电幅值，产生相应的短矩波，推动后级电路进行功率输出。在一具体实施例中，电感400可以应用于电源管理芯片500的变压电路中，例如升压电路、降压电路等。The power management chip 500 (Power Management Integrated Circuits) can take on the duties of power conversion, distribution, detection and other power management in the electronic equipment system. The power management chip 500 is mainly responsible for identifying the power supply amplitude of the CPU, generating a corresponding short moment wave, and driving the subsequent circuit to output power. In a specific embodiment, the inductor 400 can be applied in a voltage transforming circuit of the power management chip 500 , such as a boost circuit, a step-down circuit, and the like.

请参见图26、图27及图28，本申请实施例还提供一种电子设备600，电子设备600包括：显示组件610、电路板集成电感100及壳体630。显示组件610用于显示；壳体630设置于显示组件610的一侧；电路板集成电感100设置于显示组件610与壳体630之间，且与显示组件610电连接，电路板集成电感100的处理器还用于控制显示组件610进行显示。Referring to FIG. 26 , FIG. 27 and FIG. 28 , the embodiment of the present application also provides an electronic device 600 , which includes: a display component 610 , a circuit board integrated inductor 100 and a casing 630 . The display component 610 is used for display; the casing 630 is arranged on one side of the display component 610; the circuit board integrated inductor 100 is arranged between the display component 610 and the casing 630, and is electrically connected to the display component 610, and the circuit board integrated inductor 100 The processor is also used to control the display component 610 to display.

本申请实施例的电子设备600可以为但不限于为手机、平板电脑、笔记本电脑、台式电脑、智能手环、智能手表、电子阅读器、游戏机等便携式电子设备600。图26中电子设备600以手机为例进行示意，不应理解为对本申请实施例的限制。关于电路板集成电感100的详细描述，请参见上述实施例对应部分的描述，在此不再赘述。The electronic device 600 in the embodiment of the present application may be, but not limited to, portable electronic devices 600 such as mobile phones, tablet computers, notebook computers, desktop computers, smart bracelets, smart watches, e-readers, and game consoles. In FIG. 26 , the electronic device 600 is illustrated by taking a mobile phone as an example, which should not be construed as a limitation to the embodiment of the present application. For a detailed description of the circuit board integrated inductor 100 , please refer to the description of the corresponding part of the above embodiment, and details will not be repeated here.

本实施例的壳体630可以为2D结构、2.5D结构、3D结构等。本实施例的壳体630可以为电子设备600的后盖(电池盖)、或中框620及后盖一体化的外壳。The housing 630 in this embodiment may be in a 2D structure, a 2.5D structure, a 3D structure, or the like. The casing 630 in this embodiment may be the back cover (battery cover) of the electronic device 600, or a casing in which the middle frame 620 and the back cover are integrated.

可选地，显示组件610可以为但不限于为液晶显示组件610、发光二极管显示组件610(LED显示组件610)、微发光二极管显示组件610(Micro LED显示组件610)、次毫米发光二极管显示组件610(Mini LED显示组件610)、有机发光二极管显示组件610(OLED显示组件610)等中的一种或多种。Optionally, the display assembly 610 may be, but not limited to, a liquid crystal display assembly 610, a light emitting diode display assembly 610 (LED display assembly 610), a micro light emitting diode display assembly 610 (Micro LED display assembly 610), a submillimeter light emitting diode display assembly 610 (Mini LED display assembly 610), organic light emitting diode display assembly 610 (OLED display assembly 610) and the like.

请再次参见图27及图28，在一些实施例中，壳体630为电子设备600的后盖，电子设备600还包括中框620及摄像头模组650，中框620设置于显示组件610与壳体630之间，且中框620的侧面显露于壳体630与显示组件610。中框620与壳体630围合成容置空间，容置空间用于容置电路板集成电感100与摄像头模组650。摄像头模组650与电路板集成电感100的处理器11b电连接，用于在处理器11b的控制下，进行拍摄。Please refer to FIG. 27 and FIG. 28 again. In some embodiments, the casing 630 is the back cover of the electronic device 600. The electronic device 600 also includes a middle frame 620 and a camera module 650. The middle frame 620 is arranged between the display component 610 and the casing. Between the body 630 , and the sides of the middle frame 620 are exposed to the casing 630 and the display assembly 610 . The middle frame 620 and the casing 630 form an accommodating space, and the accommodating space is used for accommodating the circuit board integrated inductor 100 and the camera module 650 . The camera module 650 is electrically connected to the processor 11b of the circuit board integrated inductor 100 for taking pictures under the control of the processor 11b.

可选地，壳体630上具有透光部631，摄像头模组650可通过壳体630上的透光部631拍摄，即，本实施方式中的摄像头模组650为后置摄像头模组650。可以理解地，在其他实施方式中，透光部631可设置在显示组件610上，即，摄像头模组650为前置摄像头模组650。在本实施方式的示意图中，以透光部631为开口进行示意，在其他实施方式中，透光部631可以不为开口，而是为透光的材质，比如塑料、玻璃等。Optionally, the housing 630 has a light-transmitting portion 631 through which the camera module 650 can take pictures. That is, the camera module 650 in this embodiment is a rear camera module 650 . Understandably, in other implementation manners, the light-transmitting portion 631 may be disposed on the display assembly 610 , that is, the camera module 650 is the front camera module 650 . In the schematic diagram of this embodiment, the light-transmitting portion 631 is used as an opening for illustration. In other embodiments, the light-transmitting portion 631 may not be an opening, but a light-transmitting material, such as plastic or glass.

可以理解地，本实施方式中的电子设备600仅仅为电路板集成电感100所应用的电子设备600的一种形态，不应当理解为对本申请提供的电子设备600的限定，也不应当理解为对本申请各个实施方式提供的电路板集成电感100的限定。It can be understood that the electronic device 600 in this embodiment is only a form of the electronic device 600 applied by the circuit board integrated inductor 100, and should not be understood as a limitation to the electronic device 600 provided in this application, nor should it be understood as a limitation to this application. Limitations of the circuit board integrated inductor 100 provided in various embodiments of the application.

请参见图29及图30，本申请实施例还提供一种电子设备700，电子设备700包括显示组件710、壳体730以及电路板组件740。显示组件710用于显示；壳体730设置于显示组件710的一侧；电路板组件740设置于显示组件710与壳体730之间，且与显示组件710电连接，电路板组件740用于控制显示组件710进行显示。电路板组件740包括本申请实施例的电感400。关于电感400的详细描述，请参见上述实施例对应部分的描述，在此不再赘述。Referring to FIG. 29 and FIG. 30 , the embodiment of the present application further provides an electronic device 700 , and the electronic device 700 includes a display component 710 , a casing 730 and a circuit board component 740 . The display assembly 710 is used for display; the casing 730 is arranged on one side of the display assembly 710; the circuit board assembly 740 is arranged between the display assembly 710 and the casing 730, and is electrically connected with the display assembly 710, and the circuit board assembly 740 is used for controlling The display component 710 performs display. The circuit board assembly 740 includes the inductor 400 of the embodiment of the present application. For the detailed description of the inductor 400, please refer to the description of the corresponding part of the above embodiment, and details are not repeated here.

本实施例与上述各实施例相同特征的部分请参见上述实施例对应部分的描述，在此不再赘述。For parts of this embodiment that have the same features as those of the above-mentioned embodiments, please refer to the description of the corresponding parts of the above-mentioned embodiments, and details are not repeated here.

可以理解地，本实施方式中的电子设备700仅仅为电感所应用的电子设备700的一种形态，不应当理解为对本申请提供的电子设备700的限定，也不应当理解为对本申请各个实施方式提供的电感的限定。It can be understood that the electronic device 700 in this embodiment is only a form of the electronic device 700 to which inductance is applied, and should not be construed as a limitation to the electronic device 700 provided in this application, nor should it be understood as a limitation to each embodiment of this application. provided that the inductance is limited.

请参见图31及图32，本申请实施例还提供一种电子设备800，电子设备800包括显示组件810、壳体830以及电路板组件840。显示组件810用于显示；壳体830设置于显示组件810的一侧；电路板组件840设置于显示组件810与壳体830之间，且与显示组件810电连接，电路板组件840用于控制显示组件810进行显示。电路板组件840包括本申请实施例的电源管理芯片500。Referring to FIG. 31 and FIG. 32 , the embodiment of the present application also provides an electronic device 800 . The electronic device 800 includes a display component 810 , a casing 830 and a circuit board component 840 . The display assembly 810 is used for display; the casing 830 is arranged on one side of the display assembly 810; the circuit board assembly 840 is arranged between the display assembly 810 and the casing 830, and is electrically connected with the display assembly 810, and the circuit board assembly 840 is used for controlling The display component 810 performs display. The circuit board assembly 840 includes the power management chip 500 of the embodiment of the present application.

关于电源管理芯片500的详细描述，请参见上述实施例对应部分的描述，在此不再赘述。For the detailed description of the power management chip 500, please refer to the description of the corresponding part of the above embodiment, and details are not repeated here.

可以理解地，本实施方式中的电子设备800仅仅为电源管理芯片500所应用的电子设备800的一种形态，不应当理解为对本申请提供的电子设备800的限定，也不应当理解为对本申请各个实施方式提供的电源管理芯片500的限定。It can be understood that the electronic device 800 in this embodiment is only a form of the electronic device 800 applied by the power management chip 500, and should not be construed as a limitation to the electronic device 800 provided in this application, nor should it be interpreted as a limitation to this application. The limitations of the power management chip 500 provided in various embodiments.

在本申请中提及“实施例”“实施方式”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现所述短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本申请所描述的实施例可以与其它实施例相结合。此外，还应该理解的是，本申请各实施例所描述的特征、结构或特性，在相互之间不存在矛盾的情况下，可以任意组合，形成又一未脱离本申请技术方案的精神和范围的实施例。References in this application to "an embodiment" and "an implementation" mean that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of a phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those skilled in the art that the embodiments described in this application can be combined with other embodiments. In addition, it should also be understood that the features, structures or characteristics described in the various embodiments of the present application can be combined arbitrarily without departing from the spirit and scope of the technical solution of the present application if there is no contradiction between them. the embodiment.

最后应说明的是，以上实施方式仅用以说明本申请的技术方案而非限制，尽管参照以上较佳实施方式对本申请进行了详细说明，本领域的普通技术人员应当理解，可以对本申请的技术方案进行修改或等同替换都不应脱离本申请技术方案的精神和范围。Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application rather than limit them. Although the present application has been described in detail with reference to the above preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present application can be The modification or equivalent replacement of the scheme shall not deviate from the spirit and scope of the technical scheme of the present application.

Claims

一种电路板集成电感，其特征在于，包括：A circuit board integrated inductor, characterized in that it comprises:

电路板，所述电路板嵌设有线圈；A circuit board, the circuit board is embedded with a coil;

磁胶层，所述磁胶层设置于所述电路板相背的两侧中的至少一侧上，且与所述线圈至少部分交叠；以及a magnetic glue layer, the magnetic glue layer is disposed on at least one of the two opposite sides of the circuit board, and at least partially overlaps the coil; and

磁膜层，所述磁膜层设置于所述磁胶层背离所述电路板的一侧，A magnetic film layer, the magnetic film layer is arranged on the side of the magnetic glue layer away from the circuit board,

其中，所述磁膜层的磁导率大于所述磁胶层的磁导率。Wherein, the magnetic permeability of the magnetic film layer is greater than the magnetic permeability of the magnetic glue layer.
根据权利要求1所述的电路板集成电感，其特征在于，所述磁胶层包括树脂及磁性颗粒，所述磁性颗粒分散于所述树脂中；在所述磁胶层中，所述磁性颗粒的重量分数的范围为85％至95％；所述磁性颗粒的D90粒径的范围为1μm≤D90≤10μm。The circuit board integrated inductor according to claim 1, wherein the magnetic glue layer includes resin and magnetic particles, and the magnetic particles are dispersed in the resin; in the magnetic glue layer, the magnetic particles The weight fraction of the magnetic particle ranges from 85% to 95%; the D90 particle size range of the magnetic particles is 1 μm≤D90≤10 μm.
根据权利要求2所述的电路板集成电感，其特征在于，所述树脂包括环氧树脂、聚氨酯及丙烯酸酯中的至少一种；所述磁性颗粒包括铁氧体颗粒、磁性金属颗粒、磁性合金颗粒中的至少一种；所述铁氧体包括MnZn铁氧体、NiZn铁氧体中的至少一种；所述磁性金属颗粒包括铁、钴、镍中的至少一种；所述磁性合金颗粒包括铁基晶态合金、铁基非晶合金、钴基非晶合金中的至少一种；所述铁基晶态合金包括FeNi合金、FeCo合金、FeAl合金、FeSiAl合金、FeNiMo合金、FeC合金中的至少一种；所述铁基非晶合金包括FeSiB合金、FeB合金、FeNiPB合金、FeNiMoB合金中的至少一种；所述钴基非晶合金包括CoFeSiB合金、CoFeCrSiB合金、CoNiFeSiB合金中的至少一种。The circuit board integrated inductor according to claim 2, wherein the resin includes at least one of epoxy resin, polyurethane and acrylate; the magnetic particles include ferrite particles, magnetic metal particles, magnetic alloy At least one of the particles; the ferrite includes at least one of MnZn ferrite and NiZn ferrite; the magnetic metal particles include at least one of iron, cobalt, and nickel; the magnetic alloy particles Including at least one of iron-based crystalline alloys, iron-based amorphous alloys, and cobalt-based amorphous alloys; the iron-based crystalline alloys include FeNi alloys, FeCo alloys, FeAl alloys, FeSiAl alloys, FeNiMo alloys, and FeC alloys. At least one of; the iron-based amorphous alloy includes at least one of FeSiB alloy, FeB alloy, FeNiPB alloy, FeNiMoB alloy; the cobalt-based amorphous alloy includes at least one of CoFeSiB alloy, CoFeCrSiB alloy, CoNiFeSiB alloy kind.
根据权利要求1所述的电路板集成电感，其特征在于，所述电路板集成电感还包括绝缘层，所述绝缘层设置于所述线圈与所述磁胶层之间。The circuit board integrated inductor according to claim 1, wherein the circuit board integrated inductor further comprises an insulating layer, and the insulating layer is disposed between the coil and the magnetic glue layer.
根据权利要求1所述的电路板集成电感，其特征在于，所述磁膜层包括磁性金属、磁性合金中的至少一种；所述磁性金属包括铁、钴、镍中的至少一种；所述磁性合金包括铁基晶态合金、铁基非晶合金、钴基非晶合金中的至少一种；所述铁基晶态合金包括FeNi合金、FeCo合金、FeAl合金、FeSiAl合金、FeNiMo合金、FeC合金中的至少一种；所述铁基非晶合金包括FeSiB合金、FeB合金、FeNiPB合金、FeNiMoB合金中的至少一种；所述钴基非晶合金包括CoFeSiB合金、CoFeCrSiB合金、CoNiFeSiB合金中的至少一种。The circuit board integrated inductor according to claim 1, wherein the magnetic film layer includes at least one of magnetic metal and magnetic alloy; the magnetic metal includes at least one of iron, cobalt, and nickel; The magnetic alloy includes at least one of iron-based crystalline alloys, iron-based amorphous alloys, and cobalt-based amorphous alloys; the iron-based crystalline alloys include FeNi alloys, FeCo alloys, FeAl alloys, FeSiAl alloys, FeNiMo alloys, At least one of FeC alloys; the iron-based amorphous alloys include at least one of FeSiB alloys, FeB alloys, FeNiPB alloys, and FeNiMoB alloys; the cobalt-based amorphous alloys include CoFeSiB alloys, CoFeCrSiB alloys, and CoNiFeSiB alloys at least one of .
根据权利要求1-5任一项所述的电路板集成电感，其特征在于，沿所述电路板、所述磁胶层及所述磁膜层的层叠方向，所述磁胶层的厚度h1的范围为50μm≤h1≤500μm，所述磁膜层的厚度h2的范围为5μm≤h2≤35μm。According to the circuit board integrated inductor according to any one of claims 1-5, it is characterized in that, along the stacking direction of the circuit board, the magnetic glue layer and the magnetic film layer, the thickness h1 of the magnetic glue layer The range of the thickness h2 of the magnetic film layer is 50 μm≤h1≤500 μm, and the range of the thickness h2 of the magnetic film layer is 5 μm≤h2≤35 μm.
根据权利要求1-5任一项所述的电路板集成电感，其特征在于，所述电路板包括至少一层介电层及至少一层导电层；所述介电层与所述导电层依次交替层叠设置，所述导电层包括导线；当所述导电层为一层时，单层所述导电层的所述导线形成所述线圈；所述导电层为多层时，任意相邻的两层导电层的导线电连接，形成所述线圈。The circuit board integrated inductor according to any one of claims 1-5, wherein the circuit board comprises at least one dielectric layer and at least one conductive layer; the dielectric layer and the conductive layer are sequentially Alternately laminated, the conductive layer includes wires; when the conductive layer is one layer, the wires of the single layer of the conductive layer form the coil; when the conductive layer is multi-layered, any adjacent two The wires of the conductive layers are electrically connected to form the coil.
根据权利要求1-5任一项所述的电路板集成电感，其特征在于，所述磁膜层包括改性磁性合金，所述改性磁性合金包括铬掺杂的铁镍合金、铬掺杂的铁钴合金、铬掺杂的铁硅铝合金中的至少一种。The circuit board integrated inductor according to any one of claims 1-5, characterized in that, the magnetic film layer includes a modified magnetic alloy, and the modified magnetic alloy includes a chromium-doped iron-nickel alloy, a chromium-doped At least one of iron-cobalt alloy and chromium-doped sendust.
根据权利要求8所述的电感，其特征在于，所述磁膜层包括依次交替层叠设置的磁膜子层及金属氧化物层，所述磁膜子层为所述改性磁性合金层，所述金属氧化物层包括所述改性磁性合金中的至少一种金属的氧化物。The inductor according to claim 8, wherein the magnetic film layer comprises magnetic film sub-layers and metal oxide layers alternately stacked in sequence, the magnetic film sub-layer is the modified magnetic alloy layer, so The metal oxide layer includes an oxide of at least one metal in the modified magnetic alloy.
根据权利要求8所述的电路板集成电感，其特征在于，所述磁膜层包括依次交替层叠设置的绝缘子层及磁膜子层，所述绝缘子层包括二氧化硅、氧化铝中的至少一种，所述磁膜子层包括改性磁性合金。The circuit board integrated inductor according to claim 8, wherein the magnetic film layer comprises insulating sublayers and magnetic film sublayers arranged alternately in sequence, and the insulating sublayer comprises at least one of silicon dioxide and aluminum oxide. In an embodiment, the magnetic film sublayer includes a modified magnetic alloy.
根据权利要求1-5、9、10任一项所述的电路板集成电感，其特征在于，所述磁膜层的等效电导率σ的范围为4KS/m≤σ≤600KS/m；所述磁膜层的相对磁导率μr的范围为500≤μr≤6000。According to the circuit board integrated inductor according to any one of claims 1-5, 9, 10, it is characterized in that the range of the equivalent conductivity σ of the magnetic film layer is 4KS/m≤σ≤600KS/m; The range of the relative magnetic permeability μr of the magnetic film layer is 500≤μr≤6000.
一种电感，其特征在于，包括：An inductor, characterized in that it comprises:

线圈层，所述线圈层具有线圈；a coil layer having coils;

磁胶层，所述磁胶层设置于所述线圈层相背两侧中的至少一侧上；以及a magnetic glue layer, the magnetic glue layer is disposed on at least one of the opposite sides of the coil layer; and

磁膜层，所述磁膜层设置于所述磁胶层背离所述线圈层的一侧，a magnetic film layer, the magnetic film layer is disposed on the side of the magnetic glue layer away from the coil layer,

其中，所述磁膜层的磁导率大于所述磁胶层的磁导率。Wherein, the magnetic permeability of the magnetic film layer is greater than the magnetic permeability of the magnetic glue layer.
根据权利要求12所述的电感，其特征在于，所述磁胶层包括树脂及磁性颗粒，所述磁性颗粒分散于所述树脂中；在所述磁胶层中，所述磁性颗粒的重量分数的范围为85％至95％；所述磁性颗粒的D90粒径的范围为1μm≤D90≤10μm；所述树脂包括环氧树脂、聚氨酯及丙烯酸酯中的至少一种；所述磁性颗粒包括铁氧体颗粒、磁性合金颗粒中的至少一种；所述铁氧体颗粒包括MnZn铁氧体、NiZn铁氧体中的至少一种；所述磁性合金颗粒包括铁基晶态合金、铁基非晶合金、钴基非晶合金中的至少一种；所述铁基晶态合金为FeNi；所述铁基非晶合金包括FeSiAl合金、FeSiB合金中的至少一种；所述钴基非晶合金包括CoFeSiB合金、CoFeCrSiB合金中的至少一种。The inductor according to claim 12, wherein the magnetic glue layer comprises resin and magnetic particles, and the magnetic particles are dispersed in the resin; in the magnetic glue layer, the weight fraction of the magnetic particles The range is 85% to 95%; the D90 particle size range of the magnetic particles is 1μm≤D90≤10μm; the resin includes at least one of epoxy resin, polyurethane and acrylate; the magnetic particles include iron At least one of ferrite particles and magnetic alloy particles; the ferrite particles include at least one of MnZn ferrite and NiZn ferrite; the magnetic alloy particles include iron-based crystalline alloys, iron-based non- At least one of crystalline alloy and cobalt-based amorphous alloy; the iron-based crystalline alloy is FeNi; the iron-based amorphous alloy includes at least one of FeSiAl alloy and FeSiB alloy; the cobalt-based amorphous alloy At least one of CoFeSiB alloy and CoFeCrSiB alloy is included.
根据权利要求13所述的电感，其特征在于，所述电感还包括绝缘层，所述绝缘层设置于所述线圈层与所述磁胶层之间。The inductor according to claim 13, further comprising an insulating layer, the insulating layer is disposed between the coil layer and the magnetic glue layer.
根据权利要求12所述的电感，其特征在于，所述磁膜层包括铁氧体、磁性合金中的至少一种；所述铁氧体包括MnZn铁氧体、NiZn铁氧体中的至少一种；所述磁性合金包括铁基晶态合金、铁基非晶合金、钴基非晶合金中的至少一种；所述铁基晶态合金为FeNi；所述铁基非晶合金包括FeSiAl合金、FeSiB合金中的至少一种；所述钴基非晶合金包括CoFeSiB合金、CoFeCrSiB合金中的至少一种。The inductor according to claim 12, wherein the magnetic film layer comprises at least one of ferrite and magnetic alloy; and the ferrite comprises at least one of MnZn ferrite and NiZn ferrite The magnetic alloy includes at least one of an iron-based crystalline alloy, an iron-based amorphous alloy, and a cobalt-based amorphous alloy; the iron-based crystalline alloy is FeNi; the iron-based amorphous alloy includes a FeSiAl alloy . At least one of FeSiB alloys; the cobalt-based amorphous alloys include at least one of CoFeSiB alloys and CoFeCrSiB alloys.
根据权利要求12-15任一项所述的电感，其特征在于，沿所述线圈层、所述磁胶层及所述磁膜层的层叠方向，所述磁胶层的厚度h1的范围为50μm≤h1≤500μm，所述磁膜层的厚度h2的范围为5μm≤h2≤35μm。According to the inductor according to any one of claims 12-15, it is characterized in that, along the stacking direction of the coil layer, the magnetic glue layer and the magnetic film layer, the thickness h1 of the magnetic glue layer ranges from 50 μm≤h1≤500 μm, the thickness h2 of the magnetic film layer is in the range of 5 μm≤h2≤35 μm.
根据权利要求12-15任一项所述的电感，其特征在于，所述磁膜层包括改性磁性合金，所述改性磁性合金包括铬掺杂的铁镍合金、铬掺杂的铁钴合金、铬掺杂的铁硅铝合金中的至少一种。The inductor according to any one of claims 12-15, wherein the magnetic film layer includes a modified magnetic alloy, and the modified magnetic alloy includes chromium-doped iron-nickel alloy, chromium-doped iron-cobalt Alloy, at least one of chromium-doped sendust.
根据权利要求17所述的电感，其特征在于，所述磁膜层包括依次交替层叠设置的磁膜子层及金属氧化物层，所述磁膜子层为所述改性磁性合金层，所述金属氧化物层包括所述改性磁性合金中的至少一种金属的氧化物。The inductor according to claim 17, wherein the magnetic film layer comprises magnetic film sub-layers and metal oxide layers alternately stacked in sequence, the magnetic film sub-layer is the modified magnetic alloy layer, so The metal oxide layer includes an oxide of at least one metal in the modified magnetic alloy.
根据权利要求17所述的电感，其特征在于，所述磁膜层包括依次交替层叠设置的绝缘子层及磁膜子层，所述绝缘子层包括二氧化硅、氧化铝中的至少一种，所述磁膜子层包括改性磁性合金。The inductor according to claim 17, wherein the magnetic film layer comprises insulating sublayers and magnetic film sublayers arranged alternately in sequence, and the insulating sublayer comprises at least one of silicon dioxide and aluminum oxide, so The magnetic film sublayer includes a modified magnetic alloy.
一种电子设备，其特征在于，所述电子设备包括权利要求1-11任一项所述的电路板集成电感，或者包括权利要求12-19任一项所述的电感。An electronic device, characterized in that the electronic device includes the circuit board integrated inductor according to any one of claims 1-11, or includes the inductor according to any one of claims 12-19.