WO2023123947A1 - 零序电流抑制方法及装置、变流器和风力发电机组 - Google Patents

零序电流抑制方法及装置、变流器和风力发电机组 Download PDF

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Publication number
WO2023123947A1
WO2023123947A1 PCT/CN2022/102263 CN2022102263W WO2023123947A1 WO 2023123947 A1 WO2023123947 A1 WO 2023123947A1 CN 2022102263 W CN2022102263 W CN 2022102263W WO 2023123947 A1 WO2023123947 A1 WO 2023123947A1
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zero
converter
sequence current
converter units
sequence
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PCT/CN2022/102263
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English (en)
French (fr)
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王金鹏
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新疆金风科技股份有限公司
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Publication of WO2023123947A1 publication Critical patent/WO2023123947A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/70—Wind energy
    • Y02E10/76—Power conversion electric or electronic aspects

Definitions

  • the present disclosure generally relates to the field of converters, and more specifically, relates to a method and device for suppressing zero-sequence current, a converter and a wind power generating set.
  • the parallel connection of the converter cabinets or converter units of the converter can increase the capacity of the converter system, improve the conversion efficiency, and improve the stability and reliability of the system.
  • the actions of the switching devices in the converters cannot be completely synchronized, which will lead to various converter units or converter cabinets.
  • the output voltage is not the same, resulting in a zero-sequence voltage.
  • structural differences, sampling, control parameters, optical fiber delays, etc. of each module in the converter will also lead to inconsistent output voltages of each converter unit or converter cabinet.
  • the zero-sequence voltage acts on the equivalent resistance between wind power converters to form zero-sequence current or zero-sequence circulating current.
  • Zero-sequence circulating current will increase the loss of switching devices, reduce the efficiency of the system, increase the probability of wind power converter failure shutdown, and even destroy the entire converter system in serious cases. At present, there are no effective measures to suppress the zero-sequence circulating current of the converter.
  • One of the objectives of the present disclosure is to provide a zero-sequence current suppression method and a zero-sequence current suppression device capable of suppressing the zero-sequence current.
  • One of the objectives of the present disclosure is to provide a zero-sequence current suppression method and a zero-sequence current suppression device capable of simultaneously suppressing high-frequency components and low-frequency components of the zero-sequence current.
  • a zero-sequence current suppression method of a converter includes N converter units connected in parallel, N is a positive integer greater than or equal to 2, the zero-sequence current suppression method Including: obtaining the zero-sequence current of N-1 converter units among the N converter units; synchronizing the PWM control signals of all rectifiers on the N converter units, and synchronizing the PWM control signals of all inverters to suppress High-frequency components of the zero-sequence current of N converter units; use the zero-sequence current of N-1 converter units and the zero-sequence current reference value to perform PI regulation to suppress the low-frequency components of the zero-sequence current of N converter units .
  • a computer-readable storage medium stores instructions or programs, and when the instructions or programs are executed by a processor, the zero-sequence current suppression method as described above is implemented.
  • a zero-sequence current suppressing device for a converter
  • the zero-sequence current suppressing device includes: a current sampling unit, which acquires the zero-sequence current of N-1 converter units among the N converter units sequence current; the carrier synchronization unit synchronizes the PWM control signals of all rectifiers on N converter units and synchronizes the PWM control signals of all inverters to suppress the high-frequency components of the zero-sequence current of N converter units; PI The control unit performs PI regulation by using the zero-sequence currents of the N-1 converter units and the zero-sequence current reference value, so as to suppress low-frequency components of the zero-sequence currents of the N converter units.
  • a converter which includes the above-mentioned computer-readable storage medium or the above-mentioned zero-sequence current suppressing device.
  • a wind turbine comprising a converter as described above.
  • the zero-sequence current suppression method and zero-sequence current suppression device for a converter can generate a zero-sequence compensation voltage and reduce costs.
  • the zero-sequence current suppression method and zero-sequence current suppression device for a converter according to the embodiments of the present disclosure can improve the safety of the converter.
  • Fig. 1 and Fig. 2 are the schematic diagrams showing the circulation path of the zero-sequence current
  • FIG. 3 is a flow chart illustrating a zero-sequence current suppression method of a converter according to an embodiment of the present disclosure
  • FIG. 4 is a control block diagram showing suppression of high frequency components of zero sequence current according to an embodiment of the present disclosure
  • FIG. 5 is a control block diagram showing suppression of low frequency components of zero sequence current according to an embodiment of the present disclosure
  • FIG. 6 is a flow chart illustrating a zero-sequence current suppression method of a converter according to an embodiment of the present disclosure
  • FIG. 7 is a block diagram illustrating a zero-sequence current suppression device of a converter according to an embodiment of the present disclosure.
  • FIG. 8 is a block diagram illustrating a controller of a converter according to an embodiment of the present disclosure.
  • the zero-sequence current suppression method and zero-sequence current suppression device for a converter according to the embodiments of the present disclosure can be applied to a converter with multiple parallel-connected converter units or multiple converter cabinets (for example, a wind power converter device).
  • the zero-sequence current suppression method and the zero-sequence current suppression device of the converter suppress the parallel zero-sequence current, the high-frequency component and the low-frequency component of the zero-sequence current are suppressed respectively.
  • the high-frequency component in the zero-sequence current it is suppressed by means of carrier synchronization; for the low-frequency component in the zero-sequence circulating current, it is suppressed by means of PI adjustment.
  • the zero-sequence voltage output by the PI regulator is injected into the relevant controller to suppress the low-frequency component of the zero-sequence current, thereby reducing the amplitude of the parallel zero-sequence current to an acceptable range.
  • Fig. 1 and Fig. 2 are schematic diagrams showing the circulation path of zero-sequence current.
  • the converter according to the embodiment of the present disclosure may include a plurality of converter cabinets, and each converter cabinet may include a converter unit, however, the present disclosure is not limited thereto, and each converter cabinet may also have a plurality of converter units. flow unit. Multiple converter cabinets or multiple converter units can be connected in parallel with each other.
  • the wind power converter may include a first converter cabinet 21, a second converter cabinet 22 and a third converter cabinet 23, the first converter cabinet 21, the second converter cabinet
  • the cabinet 22 and the third converter cabinet 23 may be located between the generator side 10 and the grid side 30, and each of the first converter cabinet 21, the second converter cabinet 22 and the third converter cabinet 23 may accommodate a Converter unit.
  • FIG. 1 and FIG. 2 show that the wind power converter has three converter cabinets, the present disclosure is not limited thereto, and the wind power converter may have two converter cabinets, four converter cabinets or more converter cabinets, Each converter cabinet can have one converter unit.
  • Each converter unit may include a rectifier and an inverter, each converter unit may include a converter and an inverter, and a switching element of each of the rectifier and the inverter may be implemented by an IGBT.
  • the first converter cabinet 21 may include a first rectifier 211 and a first inverter 212
  • the second converter cabinet 22 may include a second rectifier 221 and a second inverter 222
  • the three-converter cabinet 23 may include a third rectifier 231 and a third inverter 232 .
  • the first converter cabinet 21 , the second converter cabinet 22 and the third converter cabinet 23 are connected in parallel.
  • the supporting capacitors on each converter unit are connected in the form of a common bus.
  • the zero-sequence circulating current path shown in Figure 2 is more than the zero-sequence circulating current path shown in Figure 1, but the elements on the zero-sequence circulating current path are less than those on the zero-sequence circulating current path shown in Figure 1, and the zero-sequence circulating current path shown in Figure 2
  • the suppression and control strategy of sequence circulation is more complex than the suppression and control strategy of zero-sequence circulation shown in Figure 1.
  • the zero-sequence current suppression method and the zero-sequence current suppression device are especially suitable for parallel-connected circulating current suppression of non-common buses (the zero-sequence circulating current suppression shown in FIG. 1 ).
  • each rectifier and each inverter may have a corresponding PWM controller.
  • FIG. 3 is a flow chart showing a zero-sequence current suppression method of a converter according to an embodiment of the present disclosure
  • Fig. 4 is a control block diagram showing a high-frequency component suppression of a zero-sequence current according to an embodiment of the present disclosure
  • FIG. 5 is a control block diagram illustrating suppression of low-frequency components of zero-sequence current according to an embodiment of the present disclosure
  • FIG. 6 is a flowchart illustrating a zero-sequence current suppression method of a converter according to an embodiment of the present disclosure.
  • the zero-sequence current suppression method of a converter may include steps S310, S320 and S330.
  • step S310 the zero-sequence current of N-1 converter units among the N converter units connected in parallel in the converter is obtained, where N can be a positive integer of 2 or greater, for example, N Can be 3.
  • N can be a positive integer of 2 or greater, for example, N Can be 3.
  • the three-phase current of the AC side of the rectifier of each of the N-1 converter units may be obtained respectively, and then the zero-sequence current of the corresponding converter unit is calculated or determined based on the three-phase current.
  • the zero-sequence currents of the N ⁇ 1 converter units can be calculated by using the input currents of the rectifiers of the corresponding converter units, or can be calculated by using the output currents of the inverters of the corresponding converter units.
  • the DC buses on each of the N converter units may be independent of each other.
  • step S320 the PWM control signals of all rectifiers on the N converter units are synchronized, and the PWM control signals of all inverters are synchronized, so as to suppress high-frequency components of the zero-sequence current of the N converter units.
  • the PWM control signals of all the rectifiers on the 3 converter units can be synchronized, and the PWM control signals of all the inverters can be synchronized to control the high-frequency components of the zero-sequence current of the 3 converter units.
  • the PWM controller of the rectifier of a converter unit for example, the i-th converter unit, i ⁇ N
  • the PWM controller of the inverter of the converter unit i-th converter unit
  • the PWM control signal of the rectifier is loaded to the PWM controllers of the other N-1 rectifiers in a clock-synchronous manner
  • the PWM control signal of the selected inverter is loaded to the PWM controllers of the other N-1 inverters in a clock-synchronous manner. controller.
  • the PWM controller of the first rectifier 211 and the PWM controller of the first inverter 212 can be selected, and then the PWM control signal of the selected PWM controller of the first rectifier 211 is loaded to the second rectifier 221 in a clock synchronous manner.
  • the PWM controller of the second inverter 222 and the PWM controller of the third rectifier 231, and the PWM control signal of the PWM control controller of the first inverter 212 is loaded to the PWM controller of the second inverter 222 and the third PWM controller of the inverter 232 .
  • the PWM controllers of the rectifiers in the adjacent converter units can communicate through the optical fiber connection, and the PWM controllers of the inverters in the adjacent converter units can also communicate through the optical fiber connection. That is to say, the PWM controllers of all the rectifiers in the N converter units (for example, the PWM controllers of the first rectifier to the PWM controllers of the Nth rectifier) can use optical fiber networking, and at the same time, all the PWM controllers of the N converter units The PWM controllers of the inverters (for example, the first inverter PWM controller to the Nth rectifier PWM controller) utilize optical fiber networking.
  • step S330 PI adjustment is performed using the zero-sequence currents of N ⁇ 1 converter units and the zero-sequence current reference value, so as to suppress low-frequency components of the zero-sequence current of N converter units.
  • each zero-sequence current of N-1 converter units and the zero-sequence current reference value can be input to the PI regulator to obtain the corresponding control voltage component, and then the corresponding control
  • the voltage component is applied to a corresponding space vector pulse width modulation (SVPWM) unit, so that the corresponding space vector pulse width modulation unit outputs the control for controlling the IGBT of the inverter on the corresponding converter unit in response to the corresponding control voltage component signal, thereby suppressing the low-frequency component of the zero-sequence current on the corresponding converter unit.
  • SVPWM space vector pulse width modulation
  • the step of performing PI regulation by using the zero-sequence currents of N-1 converter units and the zero-sequence current reference value to suppress the low-frequency components of the zero-sequence current of N converter units may include: Steps S610 and Step S620.
  • step S610 PI regulation is performed using the zero-sequence currents of the N-1 converter units and the zero-sequence current reference value, so as to obtain the corresponding voltage of the controller on each converter unit in the N-1 converter units Portion control.
  • step S620 the PWM controller of the inverter on the corresponding converter unit is controlled based on the voltage control component, so as to suppress low-frequency components of the zero-sequence current of the N converter units.
  • the difference between the zero-sequence current -i 0_1 of the first converter unit and a zero-sequence current reference value (for example, 0V) (that is, the zero-sequence current -i 0_1 ) can be input to the PI regulator , the PI regulator can output the control voltage component V 0 , the control voltage component V 0 can be loaded into the space vector pulse width modulation (SVPWM) unit together with other voltage control components U ⁇ _1 and U ⁇ _1 , and the space vector pulse width modulation unit can convert The PWM control signal PWM1 is output to the switching elements of the inverter on the first converter unit.
  • the coefficients of the proportional link of the PI regulator and the coefficients of the integral link can have constant values, and both can be empirical values.
  • the difference between the zero-sequence current -i 0_2 of the second converter unit and a zero-sequence current reference value (for example, 0V) may be input to the PI regulator,
  • the PI regulator can output the control voltage component V 0
  • the control voltage component V 0 can be loaded into the space vector pulse width modulation (SVPWM) unit together with other voltage control components U ⁇ _2 and U ⁇ _2
  • the space vector pulse width modulation unit can convert the PWM
  • the control signal PWM2 is output to the switching elements of the inverter on the second converter unit.
  • the difference between the zero-sequence current-i 0_n-1 of the N-1th converter unit and a zero-sequence current reference value (for example, 0V) may be input to the PI regulator, the PI regulator can output the control voltage component V 0 , the control voltage component V 0 can be loaded into the space vector pulse width modulation (SVPWM) unit together with other voltage control components U ⁇ _n-1 and U ⁇ _n-1 , the space vector
  • the pulse width modulation unit can output the PWM control signal PWMn-1 to the switching element of the inverter on the N-1th conversion unit.
  • the coefficients of the proportional link and the integral link of each PI regulator may have constant values, and both may be empirical values.
  • the control voltage component V 0 output by each PI regulator can be different.
  • U ⁇ _1 ... U ⁇ _n-1 , U ⁇ _1 ... U ⁇ _n-1 are all derived from control voltages formed by other control strategies. The specific control strategy is not limited, and the number of control voltages under this control measurement is not limited.
  • the three-phase currents of the AC side of the rectifier in the first converter unit can be obtained respectively, and then the zero-sequence current of the first converter unit can be calculated or determined based on the three-phase currents.
  • the PWM control signals of all rectifiers on the first converter unit and the second converter unit can be synchronized, and the PWM control signals of all inverters can be synchronized, so as to suppress the high-frequency components of the zero-sequence current of the two converter units.
  • the PWM controller of the second converter unit can be controlled based on the zero-sequence current of the first converter unit.
  • step S310, step S320 and step S330 may not be limited to sequential execution, the step of high-frequency carrier synchronization may be performed first, and then the steps of zero-sequence current measurement and low-frequency zero-sequence current suppression may be performed, or high-frequency carrier synchronization may be performed last A step of.
  • FIG. 7 is a block diagram illustrating a zero-sequence current suppressing device of a converter according to an embodiment of the present disclosure.
  • the zero-sequence current suppression device 700 for a converter may include: a current sampling unit 710 , a carrier synchronization unit 720 and a PI control unit 730 .
  • the current sampling unit 710 can acquire zero-sequence currents of N ⁇ 1 converter units among the N converter units.
  • the current sampling unit 710 may be located at the input port of the rectifier of each converter unit, or at the output port of the inverter of each converter unit.
  • FIG. 7 only shows an example in which the current sampling unit 10 is arranged at an input port of a certain converter unit. During specific implementation, it can be set according to actual conditions, and is not limited thereto.
  • the current sampling unit 710 may include a plurality of sensors located at the input port of the rectifier or the output port of the inverter of the conversion unit.
  • the carrier synchronization unit 720 can synchronize the PWM control signals of all the rectifiers on the N converter units, and synchronize the PWM control signals of all the inverters, so as to suppress the high-frequency components of the zero-sequence current of the N converter units.
  • the carrier synchronization unit 720 may include a PWM controller for synchronizing the PWM control signals of each rectifier, and the signals of each PWM controller may be synchronized by a clock signal, for example, the PWM control signal of a certain PWM controller may be synchronized by a clock signal It is loaded to other PWM controllers in a synchronous manner, and the communication between each PWM controller can be realized through optical fiber.
  • the PI control unit 730 may perform PI regulation by using the zero-sequence currents of the N ⁇ 1 converter units and the zero-sequence current reference value, so as to suppress low-frequency components of the zero-sequence currents of the N converter units.
  • the PI control unit 730 can use the difference between each zero-sequence current of the N-1 converter units and the zero-sequence current reference value (for example, 0V) to input to the PI regulator, and the PI regulator can output the control voltage component .
  • the zero-sequence current reference value for example, 0V
  • the corresponding control voltage components output by the PI control unit 730 can be respectively loaded to corresponding space vector pulse width modulation (SVPWM) units, so that the corresponding space vector pulse width modulation units are used to control the corresponding output in response to the corresponding control voltage components.
  • SVPWM space vector pulse width modulation
  • the PI control unit 730 can use the zero-sequence current of the N-1 converter units and the zero-sequence current reference value to perform PI regulation, so as to obtain the corresponding
  • the voltage control component of is used to control the PWM controller of the inverter on the corresponding converter unit based on the voltage control component, so as to suppress the low-frequency component of the zero-sequence current of the N converter units.
  • the PI control unit 730 may include a plurality of PI regulators, and the number of PI regulators may correspond to the number of inverters.
  • components other than the current sampling unit 710 , the carrier synchronization unit 720 and the PI control unit 730 are the same as the corresponding components in FIG. 4 , and the detailed description thereof will not be repeated here.
  • each unit or module in the zero-sequence current suppression device for a converter may be implemented as a hardware component and/or a software component.
  • Those skilled in the art can realize each unit by using, for example, field programmable gate array (FPGA), application specific integrated circuit (ASIC), software algorithm, etc. according to the defined processing performed by each unit.
  • FPGA field programmable gate array
  • ASIC application specific integrated circuit
  • means such as modules or their functions
  • methods may be implemented by programs or instructions stored in computer-readable storage media.
  • the processor may perform the function corresponding to the instruction or perform the method corresponding to the instruction.
  • At least a portion of a module may be implemented (eg, executed) by a processor.
  • At least a portion of the programming modules may include modules, programs, routines, sets of instructions, and procedures for performing at least one function.
  • instructions or software include machine code (such as that produced by a compiler) for direct execution by one or more processors or computers.
  • instructions or software comprise higher-level code that is executed by one or more processors or computers using an interpreter. Instructions or software may be written using any programming language based on the block diagrams and flowcharts shown in the drawings and the corresponding descriptions in the specification.
  • a module or programming module of the present disclosure may include at least one of the aforementioned components with some components omitted or other components added.
  • the operations of the modules, programming modules, or other components may be performed sequentially, in parallel, in a loop, or heuristically. Additionally, some operations may be performed in a different order, omitted, or augmented with other operations.
  • the zero-sequence current suppression method can be implemented via software, and the computer-readable storage medium of the exemplary embodiment of the present disclosure can store There is a computer program, and when the computer program is executed by a processor, the method for suppressing zero-sequence current of a wind power converter as described in the above exemplary embodiments is realized.
  • Examples of computer-readable storage media may include magnetic media such as floppy disks and magnetic tapes, optical media (including compact disk (CD) ROMs and DVD ROMs), magneto-optical media such as floppy disks, diskettes designed to store and execute program commands, such as ROM, RAM hardware devices, and flash memory.
  • the program commands include language codes executable by a computer using an interpreter and machine language codes generated by a compiler.
  • the above-described hardware devices may be realized by one or more software modules for performing operations of various embodiments of the present disclosure.
  • a wind power converter may include the above-mentioned computer-readable storage medium or the above-mentioned zero-sequence current suppression device.
  • the computer-readable storage medium, the zero-sequence current suppression device and/or the wind power converter as described above may be part of a wind power generating set.
  • a computer readable storage medium and/or a zero sequence current suppressing device may be a part of a PWM controller or a control system.
  • FIG. 8 is a block diagram illustrating a controller of a converter according to an embodiment of the present disclosure.
  • a controller 800 of a converter includes: a processor 810 and a memory 820 , wherein the memory 820 stores a computer program, and when the computer program is executed by the processor 810 , implement the zero-sequence current suppression method of the wind power converter as in the above exemplary embodiment.
  • the zero-sequence current suppression method and the zero-sequence current suppression device of the converter according to the embodiments of the present disclosure can suppress the zero-sequence current current suppression method of the zero-sequence current.
  • the zero-sequence current suppression method and the zero-sequence current suppression device of the converter according to the embodiments of the present disclosure can simultaneously suppress the high-frequency component and the low-frequency component of the zero-sequence current suppression method of the zero-sequence current.
  • the zero-sequence current suppression method and zero-sequence current suppression device for a converter can generate a zero-sequence compensation voltage and reduce costs.
  • the zero-sequence current suppression method and zero-sequence current suppression device for a converter according to the embodiments of the present disclosure can improve the safety of a wind power converter.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)
  • Inverter Devices (AREA)
  • Control Of Eletrric Generators (AREA)
  • Supply And Distribution Of Alternating Current (AREA)

Abstract

本公开提供一种零序电流抑制方法及装置、变流器和风力发电机组。变流器包括并联连接的N个变流单元，N是大于等于2的正整数，零序电流抑制方法包括：获取N个变流单元中的N-1个变流单元的零序电流；同步N个变流单元上的所有整流器的PWM控制信号，并同步所有逆变器的PWM控制信号，以抑制N个变流单元的零序电流的高频分量；利用N-1个变流单元的零序电流以及零序电流参考值执行PI调节，以抑制N个变流单元的零序电流的低频分量。根据本公开的实施例的零序电流抑制方法，可同时抑制变流器的零序电流的高频分量和低频分量。

Description

零序电流抑制方法及装置、变流器和风力发电机组
本申请要求于2021年12月29日提交的申请号为202111632947.0、申请名称为“零序电流抑制方法及装置、风电变流器、介质和机组”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开总体说来涉及变流器领域，更具体地讲，涉及一种零序电流抑制方法及装置、变流器和风力发电机组。
背景技术
变流器的变流柜或变流单元的并联能够增加变流***容量以及提高转换效率，提高***的稳定性和可靠性。
然而，由于并联的变流柜之间或者变流单元之间的硬件参数不能完全一致，导致变流器中的开关器件的动作不能完全同步，所以就会导致各个变流单元或变流柜的输出电压不一样，产生零序电压。另外，变流器中的各个模块的结构差异、采样、控制参数、光纤的延时等也会导致各个变流单元或变流柜的输出电压不一致。零序电压作用于风电变流器之间的等效电阻就会形成零序电流或零序环流。
零序环流会增加开关器件的损耗，降低***的效率，增加风电变流器故障停机的几率，严重时会摧毁整个变流***，目前还没有能够有效抑制变流器零序环流的措施。
以前，鉴于容量的限制，风电变流器的多个变流柜或变流单元并联的情况较少，随着风力发电机组的整机功率等级的不断增大，多个变流柜体并联的拓扑将成为一种应用趋势，而目前风电变流器的控制技术中无针对并联零序环流的抑制方案。
此外，对于采用增加电阻等使零序压差降低的方案，随着风电变流器的柜体或变流单元的增多，需要增加更多的电阻器件，同时会导致成本以及损耗的增加。
上述内容仅作为背景信息呈现，以供了解相关技术内容。上述内容的公开不意味着上述内容为现有技术。
发明内容
本公开的目的之一在于提供一种能够抑制零序电流的零序电流抑制方法和零序电流抑制装置。
本公开的目的之一在于提供一种能够同时抑制零序电流的高频分量和低频分量的零序电流抑制方法和零序电流抑制装置。
根据本公开的第一方面，提供一种变流器的零序电流抑制方法，该变流器包括并联连接的N个变流单元，N是大于等于2的正整数，该零序电流抑制方法包括：获取N个变流单元中的N-1个变流单元的零序电流；同步N个变流单元上的所有整流器的PWM控制信号，并同步所有逆变器的PWM控制信号，以抑制N个变流单元的零序电流的高频分量；利用N-1个变流单元的零序电流以及零序电流参考值执行PI调节，以抑制N个变流单元的零序电流的低频分量。
根据本公开的第二方面，提供一种计算机可读存储介质，该计算机可读存储介质存储有指令或程序，当指令或程序由处理器执行时实现如上所述的零序电流抑制方法。
根据本公开的第三方面，提供一种变流器的零序电流抑制装置，该零序电流抑制装置包括：电流采样单元，获取N个变流单元中的N-1个变流单元的零序电流；载波同步单元，同步N个变流单元上的所有整流器的PWM控制信号，并同步所有逆变器的PWM控制信号，以抑制N个变流单元的零序电流的高频分量；PI控制单元，利用N-1个变流单元的零序电流以及零序电流参考值执行PI调节，以抑制N个变流单元的零序电流的低频分量。
根据本公开的第四方面，提供一种变流器，该变流器包括如上所述的计算机可读存储介质或如上所述的零序电流抑制装置。
根据本公开的第五方面，提供一种风力发电机组，该风力发电机组包括如上所述的变流器。
根据本公开的实施例的变流器的零序电流抑制方法和零序电流抑制装置可产生零序补偿电压，降低成本。
根据本公开的实施例的变流器的零序电流抑制方法和零序电流抑制装置 可提高变流器的安全性。
将在接下来的描述中部分阐述本发明总体构思另外的方面和/或优点，还有一部分通过描述将是清楚的，或者可以经过本发明总体构思的实施而得知。
附图说明
通过下面结合示例性地示出实施例的附图进行的描述，本公开示例性实施例的上述和其他目的和特点将会变得更加清楚，其中：
图1和图2是示出零序电流的环流路径的示意图；
图3是示出根据本公开的实施例的变流器的零序电流抑制方法的流程图；
图4是示出根据本公开的实施例的抑制零序电流的高频分量的控制框图；
图5是示出根据本公开的实施例的抑制零序电流的低频分量的控制框图；
图6是示出根据本公开的实施例的变流器的零序电流抑制方法的流程图；
图7是示出根据本公开的实施例的变流器的零序电流抑制装置的框图；以及
图8是示出根据本公开的实施例的变流器的控制器的框图。
具体实施方式
根据本公开的实施例的变流器的零序电流抑制方法和零序电流抑制装置可以适用于具有多个并联连接的变流单元或多个变流柜的变流器(例如，风电变流器)。
根据本公开的实施例的变流器的零序电流抑制方法和零序电流抑制装置抑制并联零序电流时，分别对零序电流的高频分量和低频分量的进行抑制。其中，对于零序电流中的高频分量，通过载波同步的方式进行抑制；对于零序环流中的低频分量，通过PI调节的方式进行抑制。
PI调节器输出的零序电压注入到相关控制器中，实现对零序电流的低频分量的抑制，从而将并联零序电流的幅值降低到可承受的范围内。
下面将详细参照本公开的实施例，所述实施例的示例在附图中示出，其中，相同的标号始终指的是相同的部件。以下将通过参照附图来说明所述实施例，以便解释本公开。
图1和图2是示出零序电流的环流路径的示意图。
根据本公开的实施例的变流器可包括多个变流柜，每个变流柜中可包括 一个变流单元，然而，本公开不限于此，每个变流柜也可具有多个变流单元。多个变流柜或多个变流单元可彼此并联连接。
如图1和图2所示，作为示例，风电变流器可包括第一变流柜21、第二变流柜22和第三变流柜23，第一变流柜21、第二变流柜22和第三变流柜23可位于发电机侧10与电网侧30之间，第一变流柜21、第二变流柜22和第三变流柜23中的每个可容纳有一个变流单元。
虽然图1和图2示出风电变流器具有三个变流柜，但本公开不限于此，风电变流器可具有两个变流柜，四个变流柜或更多个变流柜，每个变流柜可具有一个变流单元。
每个变流单元可包括整流器和逆变器，每个变流单元可包括一个变流器和一个逆变器，整流器和逆变器中的每个的开关元件可通过IGBT实现。
如图1和图2所示，第一变流柜21可包括第一整流器211和第一逆变器212，第二变流柜22可包括第二整流器221和第二逆变器222，第三变流柜23可包括第三整流器231和第三逆变器232。
第一变流柜21、第二变流柜22和第三变流柜23并联连接。
如图1所示，在第一变流柜21和第二变流柜22之间、第二变流柜22和第三变流柜23之间以及第一变流柜21和第三变流柜23之间产生零序电压的情况下，就会在每个变流单元中产生零序电流。零序电流或零序环流的路径可如图1所示，分别在第一变流柜21和第二变流柜22之间、第二变流柜22和第三变流柜23之间以及第一变流柜21和第三变流柜23之间产生的第一零序环流路径、第二零序环流路径和第三零序环流路径。
如图2所示，每个变流单元上的支撑电容采用共母线的方式连接。图2所示的零序环流路径比图1所示的零序环流路径多，但零序环流路径上的元件比图1所示的零序环流路径上的元件少，图2所示的零序环流的抑制和控制策略比图1所示的零序环流的抑制和控制策略更为复杂。
在本公开的实施例中，零序电流抑制方法和零序电流抑制装置尤其适用于非共母线的并联环流抑制(图1所示的零序环流抑制)。虽然没有示出，但每个整流器和每个逆变器均可具有相应的PWM控制器。
图3是示出根据本公开的实施例的变流器的零序电流抑制方法的流程图，图4是示出根据本公开的实施例的抑制零序电流的高频分量的控制框图，图5是示出根据本公开的实施例的抑制零序电流的低频分量的控制框图，图6 是示出根据本公开的实施例的变流器的零序电流抑制方法的流程图。
根据本公开的实施例的变流器的零序电流抑制方法可包括步骤S310、S320和S330。
在步骤S310中，获取变流器所包括的并联连接的N个变流单元中的N-1个变流单元的零序电流，这里的N可以是2或更大的正整数，例如，N可以为3。当将N-1个变流单元的零序电流控制为0时，第N个变流单元的零序环流自然为0，因此，对于零序电流的低频分量的抑制，可以仅测量N-1个变流单元的零序电流进行控制。
作为示例，可分别获取N-1个变流单元中每个变流单元的整流器交流侧的三相电流，然后基于三相电流计算或确定相应变流单元的零序电流。
另外，N-1个变流单元的零序电流可分别利用相应变流单元的整流器的输入端电流计算得到，也可以分别利用相应变流单元的逆变器的输出端电流计算得到。N个变流单元中的每个变流单元上的直流母线可以彼此独立。
在步骤S320中，同步N个变流单元上的所有整流器的PWM控制信号，并同步所有逆变器的PWM控制信号，以抑制N个变流单元的零序电流的高频分量。
例如，可同步3个变流单元上的所有整流器的PWM控制信号，并且同步所有逆变器的PWM控制信号，以控制3个变流单元的零序电流的高频分量。
可以任意选取一个变流单元(例如，第i变流单元，i≤N)的整流器的PWM控制器以及该变流单元(第i变流单元)的逆变器的PWM控制器，然后将选取的整流器的PWM控制信号用时钟同步方式加载到其他N-1个整流器的PWM控制器，并且将选取的逆变器的PWM控制信号用时钟同步方式加载到其他N-1个逆变器的PWM控制器。
例如，可以选取第一整流器211的PWM控制器以及第一逆变器212的PWM控制器，然后将选取的第一整流器211的PWM控制器的PWM控制信号用时钟同步方式加载到第二整流器221的PWM控制器和第三整流器231的PWM控制器，并且将第一逆变器212的PWM控制控制器的PWM控制信号用时钟同步方式加载到第二逆变器222的PWM控制器和第三逆变器232的PWM控制器。
在N个变流单元中，相邻变流器单元中整流器的PWM控制器可通过光 纤连接进行通信，相邻变流单元中逆变器的PWM控制器同样也可通过光纤连接通信。也就是说，N个变流单元中的所有整流器的PWM控制器(例如，第一整流器PWM控制器至第N整流器PWM控制器)可利用光纤组网，同时，N个变流单元中的所有逆变器的PWM控制器(例如，第一逆变器PWM控制器至第N整流器PWM控制器)利用光纤组网。
在步骤S330中，利用N-1个变流单元的零序电流以及零序电流参考值执行PI调节，以抑制N个变流单元的零序电流的低频分量。
可将N-1个变流单元的每个零序电流分别与零序电流参考值(例如，0V)之间的差值输入到PI调节器，获得相应的控制电压分量，然后将相应的控制电压分量加载到相应的空间矢量脉宽调制(SVPWM)单元，以使相应的空间矢量脉宽调制单元响应于相应的控制电压分量输出用于控制相应变流单元上的逆变器的IGBT的控制信号，从而抑制相应变流单元上的零序电流的低频分量。
如图6所示，利用N-1个变流单元的零序电流以及零序电流参考值执行PI调节，以抑制N个变流单元的零序电流的低频分量的步骤可包括：步骤S610和步骤S620。
在步骤S610中，利用N-1个变流单元的零序电流以及零序电流参考值执行PI调节，以获得N-1个变流单元中每个变流单元上的控制器的相应的电压控制分量。
在步骤S620中，基于所述电压控制分量控制相应变流单元上逆变器的PWM控制器，以抑制N个变流单元的零序电流的低频分量。
参照图5，可将第一变流单元的零序电流-i 0_1与零序电流参考值(例如，0V)之间的差值(也就是，零序电流-i 0_1)输入到PI调节器，PI调节器可输出控制电压分量V 0，控制电压分量V 0可以与其他的电压控制分量U α_1、U β_1一起加载到空间矢量脉宽调制(SVPWM)单元，空间矢量脉宽调制单元可将PWM控制信号PWM1输出到第一变流单元上的逆变器的开关元件。PI调节器的比例环节的系数以及积分环节的系数可具有恒定值，并且均可以是经验值。
类似地，可将第二变流单元的零序电流-i 0_2与零序电流参考值(例如，0V)之间的差值(也就是，零序电流-i 0_2)输入到PI调节器，PI调节器可输出控制电压分量V 0，控制电压分量V 0可以与其他的电压控制分量U α_2、U β_2 一起加载到空间矢量脉宽调制(SVPWM)单元，空间矢量脉宽调制单元可将PWM控制信号PWM2输出到第二变流单元上的逆变器的开关元件。可将第N-1变流单元的零序电流-i 0_n-1与零序电流参考值(例如，0V)之间的差值(也就是，零序电流-i 0_n-1)输入到PI调节器，PI调节器可输出控制电压分量V 0，控制电压分量V 0可以与其他的电压控制分量U α_n-1、U β_n-1一起加载到空间矢量脉宽调制(SVPWM)单元，空间矢量脉宽调制单元可将PWM控制信号PWM n-1输出到第N-1变流单元上的逆变器的开关元件。
需要说明的是，每个PI调节器的比例环节的系数以及积分环节的系数可具有恒定值，并且均可以是经验值。每个PI调节器输出的控制电压分量V 0可不同。U α_1……U α_n-1、U β_1……U β_n-1均源自其他控制策略形成的控制电压，具体控制策略不受具体限制，该控制测量下的控制电压的数量也不受限制。
另外，当n＝2时，可分别获取第一变流单元中的整流器交流侧的三相电流，然后基于三相电流计算或确定第一变流单元的零序电流。
可同步第一变流单元和第二变流单元上的所有整流器的PWM控制信号，并同步所有逆变器的PWM控制信号，以抑制这两个变流单元的零序电流的高频分量。
由于第一变流单元和第二变流单元中的零序电流相同，可以基于第一变流单元的零序电流控制第二变流单元的PWM控制器。
另外，步骤S310、步骤S320和步骤S330的顺序可不限于顺序执行，可先执行高频载波同步的步骤，再执行零序电流测量和低频零序电流抑制的步骤，也可以最后执行高频载波同步的步骤。
图7是示出根据本公开的实施例的变流器的零序电流抑制装置的框图。
根据本公开的实施例的变流器的零序电流抑制装置700可包括：电流采样单元710、载波同步单元720和PI控制单元730。
电流采样单元710可获取N个变流单元中的N-1个变流单元的零序电流。电流采样单元710可位于每个变流单元的整流器输入端口，也可以位于每个变流单元的逆变器的输出端口。图7中仅示出了电流采样单元10设置于某一变流单元输入端口的示例，具体实施时，可根据实际情况而设，并不以此为限。
一般地，电流采样单元710可包括位于变流单元的整流器的输入端口或逆变器的输出端口的多个传感器。
载波同步单元720可同步N个变流单元上的所有整流器的PWM控制信号，并同步所有逆变器的PWM控制信号，以抑制N个变流单元的零序电流的高频分量。
载波同步单元720可包括用于同步各个整流器的PWM控制信号的PWM控制器，每个PWM控制器的信号可通过时钟信号进行同步，例如，可将某个PWM控制器的PWM控制信号通过时钟信号同步的方式加载到其他的PWM控制器，每个PWM控制器之间的通信可通过光纤实现。
PI控制单元730可利用N-1个变流单元的零序电流以及零序电流参考值执行PI调节，以抑制N个变流单元的零序电流的低频分量。
PI控制单元730可利用N-1个变流单元的每个零序电流分别与零序电流参考值(例如，0V)之间的差值输入到PI调节器，PI调节器可输出控制电压分量。
PI控制单元730输出的相应的控制电压分量可分别加载到相应的空间矢量脉宽调制(SVPWM)单元，以使相应的空间矢量脉宽调制单元响应于相应的控制电压分量输出用于控制相应的变流单元上的逆变器的IGBT的控制信号，从而抑制相应变流单元上的零序电流的低频分量。
例如，PI控制单元730可利用N-1个变流单元的零序电流以及零序电流参考值执行PI调节，以获得N-1个变流单元中每个变流单元上的控制器的相应的电压控制分量，基于电压控制分量控制相应变流单元上的逆变器的PWM控制器，以抑制N个变流单元的零序电流的低频分量。
PI控制单元730可包括多个PI调节器，PI调节器的数量可以与逆变器的数量相对应。
在图7中，除了电流采样单元710、载波同步单元720和PI控制单元730之外的组件均可与图4中的对应组件相同，其具体描述这里不再赘述。
应该理解，根据本公开的示例性实施例的变流器的零序电流抑制装置中的各个单元或模块可被实现硬件组件和/或软件组件。本领域技术人员可根据限定的各个单元所执行的处理，可以例如使用现场可编程门阵列(FPGA)、专用集成电路(ASIC)、软件算法等来实现各个单元。
根据本公开的各个实施例，装置(例如模块或它们的功能)或方法可以通过存储在计算机可读存储介质中的程序或指令来实现。在该指令被处理器执行的情况下，处理器可以执行对应于该指令的功能或执行对应于该指令的 方法。模块的至少一部分可以由处理器实现(例如，执行)。编程模块的至少一部分可以包括用于执行至少一个功能的模块、程序、例程、指令集和过程。在一个示例中，指令或软件包括由一个或更多个处理器或计算机直接执行的机器代码(诸如，由编译器产生的机器代码)。在另一示例中，指令或软件包括由一个或更多个处理器或计算机使用解释器执行的更高级代码。可基于附图中示出的框图和流程图以及说明书中的相应描述使用任何编程语言来编写指令或软件。
本公开的模块或编程模块可以包括在省略一些部件或添加其它部件的情况下前述部件中的至少一个。所述模块、编程模块或者其它部件的操作可以顺序执行、并行执行、循环执行或试探执行。此外，一些操作可以以不同的顺序执行、可被省略或用其他操作进行扩展。
上述步骤的各个操作可被编写为软件程序或指令，因此，根据本公开的示例性实施例的零序电流抑制方法可经由软件实现，本公开的示例性实施例的计算机可读存储介质可存储有计算机程序，当所述计算机程序被处理器执行时实现如上述示例性实施例所述的风电变流器的零序电流抑制方法。
计算机可读存储介质的示例可包括诸如软盘和磁带的磁介质、光介质(包括光盘(CD)ROM和DVD ROM)、诸如软式光盘的磁光介质、设计用于存储和执行程序命令的诸如ROM、RAM的硬件装置以及闪速存储器。所述程序命令包括由计算机使用解释器可执行的语言代码以及由编译器产生的机器语言代码。上述的硬件装置可以通过用于执行本公开的各个实施例的操作的一个或更多个软件模块来实现。
根据本公开的实施例的风电变流器可包括如上所述的计算机可读存储介质或如上所述的零序电流抑制装置。
如上所述的计算机可读存储介质、零序电流抑制装置和/或风电变流器可以是风力发电机组的一部分。
根据本公开的示例性实施例的计算机可读存储介质和/或零序电流抑制装置可以是PWM控制器或控制***的一部分。
图8是示出根据本公开的实施例的变流器的控制器的框图。
如图8所示，根据本公开的示例性实施例的变流器的控制器800包括：处理器810和存储器820，其中，存储器820存储有计算机程序，当所述计算机程序被处理器810执行时，实现如上述示例性实施例的风电变流器的零 序电流抑制方法。
根据本公开的实施例的变流器的零序电流抑制方法和零序电流抑制装置能够抑制零序电流的零序电流抑制方法。
根据本公开的实施例的变流器的零序电流抑制方法和零序电流抑制装置能够同时抑制零序电流的高频分量和低频分量的零序电流抑制方法。
根据本公开的实施例的变流器的零序电流抑制方法和零序电流抑制装置可产生零序补偿电压，降低成本。
根据本公开的实施例的变流器的零序电流抑制方法和零序电流抑制装置可提高风电变流器的安全性。
虽然已表示和描述了本公开的一些示例性实施例，但本领域技术人员应该理解，在不脱离由权利要求及其等同物限定其范围的本发明的原理和精神的情况下，可以对这些实施例进行修改，例如，可以将不同实施例的技术特征进行组合。通过组合不同实施例中的技术特征得到的实施例，应视为本公开的一部分。

Claims (10)

  1. 一种变流器的零序电流抑制方法，其中，所述变流器包括并联连接的N个变流单元，N是大于等于2的正整数，所述零序电流抑制方法包括：
    获取N个变流单元中的N-1个变流单元的零序电流；
    同步所述N个变流单元上的所有整流器的PWM控制信号，并同步所有逆变器的PWM控制信号，以抑制所述N个变流单元的零序电流的高频分量；
    利用所述N-1个变流单元的零序电流以及零序电流参考值执行PI调节，以抑制N个变流单元的零序电流的低频分量。
  2. 根据权利要求1所述的变流器的零序电流抑制方法，其中，利用所述N-1个变流单元的零序电流以及零序电流参考值执行PI调节，以抑制N个变流单元的零序电流的低频分量的步骤包括：
    利用所述N-1个变流单元的零序电流以及零序电流参考值执行PI调节，以获得所述N-1个变流单元中每个变流单元上的控制器的相应的电压控制分量；
    基于所述电压控制分量控制相应变流单元上逆变器的PWM控制器，以抑制N个变流单元的零序电流的低频分量。
  3. 根据权利要求1所述的变流器的零序电流抑制方法，其中，所述N个变流单元中的每个变流单元上的直流母线彼此独立。
  4. 根据权利要求1所述的变流器的零序电流抑制方法，其中，所述N-1个变流单元的零序电流分别利用相应变流单元整流器的输入端电流计算得到。
  5. 根据权利要求1所述的变流器的零序电流抑制方法，其中，在所述N个变流单元中，相邻变流单元中整流器的PWM控制器通过光纤连接通信，相邻变流单元中逆变器的PWM控制器通过光纤连接通信。
  6. 根据权利要求5所述的变流器的零序电流抑制方法，其中，利用时钟信号同步方式，同步所述N个变流单元上的所有整流器的PWM控制信号，并同步所有逆变器的PWM控制信号。
  7. 一种计算机可读存储介质，其中，所述计算机可读存储介质存储有指令或程序，当所述指令或程序由处理器执行时实现根据权利要求1至6中任一项所述的零序电流抑制方法。
  8. 一种零序电流抑制装置，其中，包括：
    电流采样单元，被配置为获取N个变流单元中的N-1个变流单元的零序电流；
    载波同步单元，被配置为同步所述N个变流单元上的所有整流器的PWM控制信号，并同步所有逆变器的PWM控制信号，以抑制所述N个变流单元的零序电流的高频分量；
    PI控制单元，被配置为利用所述N-1个变流单元的零序电流以及零序电流参考值执行PI调节，以抑制N个变流单元的零序电流的低频分量。
  9. 一种变流器，其特征在于，包括根据权利要求7所述的计算机可读存储介质或根据权利要求8所述的零序电流抑制装置。
  10. 一种风力发电机组，其中，包括根据权利要求9所述的变流器。
PCT/CN2022/102263 2021-12-29 2022-06-29 零序电流抑制方法及装置、变流器和风力发电机组 WO2023123947A1 (zh)

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