WO2023116383A1 - 带有超结结构的绝缘栅双极型晶体管及其制备方法 - Google Patents

带有超结结构的绝缘栅双极型晶体管及其制备方法 Download PDF

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WO2023116383A1
WO2023116383A1 PCT/CN2022/135910 CN2022135910W WO2023116383A1 WO 2023116383 A1 WO2023116383 A1 WO 2023116383A1 CN 2022135910 W CN2022135910 W CN 2022135910W WO 2023116383 A1 WO2023116383 A1 WO 2023116383A1
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layer
conductivity type
region
gate
trench
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PCT/CN2022/135910
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English (en)
French (fr)
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张鹏程
万力
马先东
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华润微电子（重庆）有限公司
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Priority to EP22909698.7A priority Critical patent/EP4336561A1/en
Publication of WO2023116383A1 publication Critical patent/WO2023116383A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the invention belongs to the technical field of semiconductor integrated circuit manufacturing, and relates to an insulated gate bipolar transistor with a super junction structure and a preparation method thereof.
  • Insulated Gate Bipolar Transistor is the core device for power conversion and transmission, and is the "CPU" of power electronic devices. Key parameters of the IGBT device include conduction voltage drop V ce , switching loss E off and short circuit withstand time t sc .
  • FIG. 1 it is a schematic cross-sectional structure diagram of a planar gate type insulated gate bipolar transistor in the prior art, including an N-drift region 10, an N buffer region 101, a P emitter 102, a drain 103, and a P-body region. 104, P+ contact region 105, N+ source region 106, gate 1071, gate oxide layer 1072, isolation dielectric layer 108 and source 109, as shown in FIG.
  • FIG. 1 Schematic diagram of the cross-sectional structure of a polar transistor, including N-drift region 10, N buffer region 101, P emitter 102, drain 103, P-body region 104, P+ contact region 105, N+ source region 106, trench 107, gate pole 1071, isolation dielectric layer 108, contact hole 1081, and source 109, wherein the trench gate technology is relative to the planar gate IGBT, and the trench IGBT structure does not include the function of a Junction Field-Effect Transistor (JFET) , so there is no JFET effect, the JFET resistance is eliminated, and the on-resistance is reduced, that is, the purpose of reducing the on-voltage drop is achieved.
  • JFET Junction Field-Effect Transistor
  • FIG. 3 it is a schematic cross-sectional structure diagram of a carrier storage type trench gate insulated gate bipolar transistor, including an N-drift region 10, a carrier storage region 100, an N buffer zone 101, and a P emitter 102. , drain 103, P-body region 104, P+ contact region 105, N+ source region 106, trench 107, gate 1071, isolation dielectric layer 108, contact hole 1081 and source 109, wherein the carrier storage technology is
  • the carrier storage region 100 is formed by doping the impurity with a suitable concentration in the structure shown in FIG. 3 to enhance the conductance modulation effect and achieve the purpose of reducing the conduction voltage drop.
  • the trench gate technology reduces the turn-on voltage drop V ce , it also increases the gate charge Q gc , resulting in an increase in the turn-off power consumption E off .
  • the purpose of the present invention is to provide an insulated gate bipolar transistor and its preparation method, which is used to solve the problem of reducing the conduction voltage drop V ce of the insulated gate bipolar transistor in the prior art. Turn off the power consumption E off problem.
  • the present invention provides a method for preparing an insulated gate bipolar transistor with a super junction structure, comprising the following steps:
  • a substrate of the first conductivity type is provided to form a drift region of the first conductivity type, and an epitaxial layer of the first conductivity type is formed on the upper surface of the substrate, and the doping concentration of the epitaxial layer is higher than that of the substrate Doping concentration;
  • a body region of the second conductivity type is formed in the upper surface layer of the epitaxial layer on both sides of the trench, and an adjacent body contact region of the second conductivity type and a source region of the first conductivity type are formed in the upper surface layer of the body region , and forming an isolation dielectric layer covering the upper surface of the epitaxial layer and the upper surface of the gate conductive layer;
  • the source conductive layer is filled in the contact hole and covers the isolation dielectric layer.
  • the preparation method of the insulated gate bipolar transistor further includes the following steps:
  • the buffer layer is located between the drift region and the emitter in the vertical direction;
  • a drain conductive layer electrically connected to the emitter is formed on the bottom surface of the substrate.
  • the first conductivity type is opposite to the conductivity type of the second conductivity type, and the conductivity type of the first conductivity type includes one of N type and P type, and the conductivity type of the second conductivity type The conductivity type includes one of N type and P type.
  • forming the filling layer further includes the following steps:.
  • forming the gate conductive layer further includes the following steps:
  • the upper surface of the filling layer and the lower surface of the gate conductive layer are lower than the bottom surface of the body region.
  • the present invention also provides an insulated gate bipolar transistor with a super junction structure, including:
  • an epitaxial layer located on the upper surface of the drift region, the doping concentration of the epitaxial layer being higher than that of the drift region;
  • the filling layer of the second conductivity type and the gate structure are sequentially arranged in the trench from bottom to top, the gate structure includes a gate dielectric layer and a gate conductive layer, and the gate dielectric layer is located on the inner wall of the trench and the upper surface of the filling layer and wrapping the sidewall and bottom surface of the gate conductive layer;
  • a second conductivity type body region located in the upper surface layer of the epitaxial layer on both sides of the trench;
  • the adjacent second conductivity type body contact region and first conductivity type source region are located in the upper surface layer of the body region;
  • the source conductive layer is filled in the contact hole and covers the isolation dielectric layer.
  • the upper surface of the filling layer and the lower surface of the gate conductive layer are lower than the bottom surface of the body region.
  • the IGBT further includes a first conductivity type buffer layer, a second conductivity type emitter and drain conductive layer, the buffer layer is located at the back of the drift region, and the emitter is located at the back of the drift region.
  • the back of the buffer layer, the drain conductive layer is located on the back of the emitter.
  • the IGBT with superjunction structure and the manufacturing method thereof of the present invention form a plurality of trenches arranged at intervals in the epitaxial layer of the first conductivity type, and in the trenches Forming a filling layer of the second conductivity type whose upper surface is lower than the top surface of the epitaxial layer, forming the gate dielectric layer on the inner wall of the trench and the upper surface of the filling layer, and then forming sidewalls and bottom surfaces covered by The gate conductive layer wrapped by the gate dielectric layer is in the trench, and the upper surface of the gate conductive layer is lower than the top surface of the epitaxial layer, and the upper surface of the filling layer and the gate conductive layer The lower surface of the layer is lower than the bottom surface of the body region, the doping concentration of the epitaxial layer is higher than that of the drift region, which reduces the conduction voltage drop V ce , and the epitaxial layer and the filling The layer forms charge balance, and during the process of turning off the transistor, the filling layer quickly
  • FIG. 1 is a schematic cross-sectional structure diagram of a planar gate IGBT in the prior art.
  • FIG. 2 is a schematic cross-sectional structure diagram of a trench-gate insulated gate bipolar transistor in the prior art.
  • Fig. 3 is a schematic cross-sectional structure diagram of a carrier storage trench-gate insulated gate bipolar transistor in the prior art.
  • FIG. 4 is a flow chart of a method for preparing an IGBT with a superjunction structure according to the present invention.
  • FIG. 5 is a schematic diagram of a cross-sectional structure after forming an epitaxial layer in the method for manufacturing an IGBT with a super-junction structure according to the present invention.
  • FIG. 6 is a schematic cross-sectional structure diagram after trenches are formed in the epitaxial layer in the method for manufacturing an IGBT with a superjunction structure according to the present invention.
  • FIG. 7 is a schematic cross-sectional structure diagram after the trench is filled with a conductive material of the second conductivity type in the method for manufacturing an IGBT with a superjunction structure according to the present invention.
  • FIG. 8 is a schematic cross-sectional structure diagram after forming a filling layer in the method for manufacturing an IGBT with a super-junction structure according to the present invention.
  • FIG. 9 is a schematic cross-sectional structure diagram after forming a gate dielectric layer on the inner wall of the trench and the upper surface of the filling layer in the method for manufacturing an IGBT with a super-junction structure according to the present invention.
  • FIG. 10 is a schematic cross-sectional view of the gate conductive material formed in the trench in the method for manufacturing an IGBT with a superjunction structure according to the present invention.
  • FIG. 11 is a schematic diagram of a cross-sectional structure after forming a gate conductive layer in the method for manufacturing an IGBT with a superjunction structure according to the present invention.
  • Fig. 12 is a schematic cross-sectional structure diagram after forming a body region of the second conductivity type, a body contact region of the second conductivity type and a source region of the first conductivity type in the preparation method of the IGBT with a superjunction structure of the present invention .
  • FIG. 13 is a schematic diagram of a cross-sectional structure after forming an isolation dielectric layer in the method for manufacturing an IGBT with a super-junction structure according to the present invention.
  • FIG. 14 is a schematic diagram of a cross-sectional structure after forming a contact hole in the method for manufacturing an IGBT with a super-junction structure according to the present invention.
  • FIG. 15 is a schematic cross-sectional structure diagram after forming a source conductive layer in the method for manufacturing an IGBT with a super-junction structure according to the present invention.
  • FIG. 16 is a schematic cross-sectional structure diagram after forming an emitter of the second conductivity type and a buffer layer of the first conductivity type in the manufacturing method of the IGBT with the superjunction structure of the present invention.
  • FIG. 17 is a schematic diagram of a cross-sectional structure after forming a drain conductive layer in the method for manufacturing an IGBT with a super-junction structure according to the present invention.
  • FIG. 4 is a flow chart of the method for manufacturing the insulated gate bipolar transistor, including the following steps:
  • S1 Provide a substrate of the first conductivity type to form a drift region of the first conductivity type, and form an epitaxial layer of the first conductivity type on the upper surface of the substrate, the doping concentration of the epitaxial layer is higher than that of the substrate The doping concentration of the bottom;
  • S2 forming a plurality of trenches arranged at intervals in the epitaxial layer, and forming a second conductivity type filling layer in the trenches, and the upper surface of the filling layer is lower than the top surface of the epitaxial layer;
  • S4 forming a body region of the second conductivity type in the upper surface layer of the epitaxial layer on both sides of the trench, and forming an adjacent body contact region of the second conductivity type and the first conductivity type in the upper surface layer of the body region source region, and forming an isolation dielectric layer covering the upper surface of the epitaxial layer and the upper surface of the gate conductive layer;
  • the step S1 is performed: providing a substrate 1 of the first conductivity type to form the drift region 11 of the first conductivity type, and forming an epitaxial layer 2 of the first conductivity type on the upper surface of the substrate 1 , the doping concentration of the epitaxial layer 2 is higher than the doping concentration of the substrate 1 .
  • the material of the substrate 1 includes silicon of the first conductivity type or other suitable semiconductor materials
  • the material of the epitaxial layer 2 includes silicon of the first conductivity type or other suitable semiconductor materials.
  • the method for forming the epitaxial layer 2 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
  • the specific doping concentrations of the substrate 1 and the epitaxial layer 2 are selected according to actual needs, and are not limited here.
  • the thickness of the epitaxial layer 2 can be set according to the actual situation, which is not limited here.
  • the step S2 is performed: forming a plurality of trenches 21 arranged at intervals in the epitaxial layer 2, and forming a second conductivity type filling layer 211 in the trenches 21, and the The top surface of the filling layer 211 is lower than the top surface of the epitaxial layer 2 .
  • the first conductivity type is opposite to the conductivity type of the second conductivity type, and the first conductivity type includes one of N type and P type, and the second conductivity type includes N type and P type. one of the types.
  • the first conductivity type is N type
  • the second conductivity type is P type.
  • the trench 21 before forming the trench 21, it also includes forming a mask layer on the upper surface of the epitaxial layer 2, and patterning the mask layer; then etching the epitaxial layer 2 to form the trench twenty one.
  • the method for forming the trench 21 includes wet etching, dry etching or other suitable methods.
  • forming the filling layer 211 further includes the following steps:
  • the conductive material 2111 on the upper surface of the epitaxial layer 2 is removed, and the conductive material 2111 in the trench 21 is removed to a predetermined depth to form a second conductive type filling layer 211 .
  • the method of forming the conductive material 2111 in the trench 21 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
  • the material of the conductive material 2111 includes silicon of the second conductivity type or other suitable semiconductor materials.
  • the method for removing the conductive material 2111 on the upper surface of the epitaxial layer 2 includes chemical mechanical polishing or other suitable methods.
  • the method for removing the conductive material 2111 in the trench 21 to a predetermined depth includes wet etching, dry etching or other suitable methods.
  • step S3 and step S4 are performed: a gate dielectric layer 212 is formed on the inner wall of the trench 21 and the upper surface of the filling layer 211, and then the sidewall and bottom surface are formed.
  • the gate conductive layer 213 wrapped by the gate dielectric layer 212 is in the trench 21, and the upper surface of the gate conductive layer 213 is lower than the top surface of the epitaxial layer 2; on both sides of the trench 21
  • a body region 22 of the second conductivity type is formed in the upper surface layer of the epitaxial layer 2, and an adjacent body contact region 221 of the second conductivity type and a source region 23 of the first conductivity type are formed in the upper surface layer of the body region 22, and
  • An isolation dielectric layer 3 covering the upper surface of the epitaxial layer 2 and the upper surface of the gate conductive layer 213 is formed.
  • the material of the gate dielectric layer 212 includes silicon dioxide or other suitable materials.
  • the method for forming the gate dielectric layer 212 includes chemical vapor deposition, thermal oxidation, or other suitable methods, and the thickness of the gate dielectric layer 212 is determined according to specific conditions, which will not be discussed here. limited.
  • a thin gate oxide layer is grown on the side walls of the trench 21 and the upper surface of the filling layer 211 by thermal oxidation, and the gate oxide layer on the upper surface of the epitaxial layer 2 is removed. to form the gate dielectric layer 212 .
  • forming the gate conductive layer 213 further includes the following steps:
  • the gate conductive material 2131 on the epitaxial layer 2 is removed, and the gate conductive material 2131 in the trench 21 is removed to a predetermined depth to form a gate conductive layer 213 .
  • the method of forming the gate conductive material 2131 in the trench 21 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
  • the material of the gate conductive material 2131 includes polysilicon or other suitable materials.
  • polysilicon is used as the gate conductive material.
  • the method for removing the gate conductive material 2131 on the upper surface of the epitaxial layer 2 includes chemical mechanical polishing or other suitable methods.
  • the method for removing the gate conductive material 2131 in the trench 21 includes wet etching, dry etching or other suitable methods.
  • the upper surface of the filling layer 211 and the lower surface of the gate conductive layer 213 are lower than the bottom surface of the body region 22 .
  • the method for forming the body region 22 includes ion implantation or other suitable methods.
  • the method of forming the body contact region 221 in the body region 22 includes ion implantation or other suitable methods.
  • the doping concentration of the body contact region 221 is higher than that of the body region 22 .
  • the method for forming the source region 23 in the body region 22 includes ion implantation or other suitable methods, and the implantation depth of the impurity ions of the first conductivity type in the source region 23 is smaller than that in the body region 22.
  • the implantation depth of impurity ions of the second conductivity type is smaller than that in the body region 22.
  • the method of ion implantation is used to implant second conductivity type impurity ions into the surface layer of the epitaxial layer 2 from above the epitaxial layer 2 to form the body region 22, and then Partial regions of the surface layer of the epitaxial layer 2 continue to be implanted with impurity ions of the second conductivity type to form the body contact region 221, and then implant the first conductivity type impurity ions to form the source region 23, the body contact region 221 and the source region 23 are adjacent to the upper surface of the body region 22, the body region 22, the body contact region 221 and the The ion implantation depth of the source region 23 is determined according to actual conditions, and is not limited here.
  • the body contact region 221 may be arranged side by side with the source region 23 .
  • an annealing treatment is performed after forming the body region 22 , the body contact region 221 and the source region 23 to activate impurity ions.
  • isolation dielectric layer 3 silicon nitride, silicon dioxide or other suitable insulating isolation layers are used as the isolation dielectric layer 3, and the thickness of the isolation dielectric layer 3 is set according to actual conditions, which is not limited here.
  • the isolation dielectric layer 3 is formed by chemical vapor deposition, physical vapor deposition or other suitable methods.
  • the step S5 is performed: forming a contact hole 31 through the isolation dielectric layer 3 to expose the source region 23 and the body contact region 221 at the same time, and forming the source conductive layer 4 , the source conductive layer 4 fills the contact hole 31 and covers the isolation dielectric layer 3 .
  • forming the contact hole 31 also includes forming a mask layer on the upper surface of the isolation dielectric layer 3, patterning the mask layer, and then forming the contact hole according to the patterned mask layer. 31.
  • the isolation dielectric layer 3 and the epitaxial layer 2 are etched by wet etching, dry etching or other suitable methods to form the contact holes 31 .
  • the source conductive layer 4 is described above.
  • the material of the source conductive layer 4 includes one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, and may also be other suitable conductive materials.
  • a step of forming a source passivation layer (not shown) on the upper surface of the source conductive layer 4 is further included.
  • the method for forming the source passivation layer includes one of chemical vapor deposition, physical vapor deposition and atomic layer deposition, and may also be other suitable methods.
  • Ion implantation is performed successively from the bottom surface of the substrate 1 to form a first conductivity type buffer layer 13 and a second conductivity type emitter 12, the buffer layer 13 is located between the drift region 11 and the emitter in the vertical direction Between 12;
  • a drain conductive layer 5 electrically connected to the emitter 12 is formed on the bottom surface of the substrate 1 .
  • FIG. 16 it is a schematic cross-sectional structure diagram after forming the buffer layer 13 and the emitter 12.
  • the buffer layer 13 is stacked above the emitter 12, that is, on the substrate 1.
  • the ion implantation depth of impurity ions of the first conductivity type is implanted into the bottom surface below the bottom surface of the bottom surface is greater than the ion implantation depth of impurity ions of the second conductivity type, and after the implantation of the two types of impurity ions is completed, an annealing process is required to activate the formation of impurity ions.
  • the buffer layer 13 and the emitter 12 .
  • the thickness and doping concentration of the emitter 12 are set according to actual conditions, which are not limited here.
  • the thickness and doping concentration of the buffer layer 13 are set according to actual conditions, which are not limited here.
  • the material of the drain conductive layer 5 includes one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, and may also be other suitable conductive materials.
  • FIG. 17 it is a schematic diagram of a cross-sectional structure after forming the drain conductive layer 5, using sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic
  • the drain conductive layer 5 is formed by vapor phase deposition, atomic layer deposition or other suitable methods.
  • the preparation method of the insulated gate bipolar transistor with a super junction structure in this embodiment is to form an upwardly stacked second conductivity type emitter 12, a first conductivity type buffer layer 13 and a first
  • the conductivity type drift region 11 is formed in the epitaxial layer 2 with a plurality of trenches 21 with openings upward and spaced apart, and a second conductivity type filling layer 211 is formed in the trenches 21, and then formed in the trenches.
  • the side walls of the trench 21 and the gate dielectric layer 212 on the upper surface of the filling layer 211 are formed in the trench 21.
  • the side walls and the bottom surface are wrapped by the gate dielectric layer 212 and the upper surface is lower than the epitaxial layer.
  • the gate conductive layer 213 on the top surface of the layer, the doping concentration of the epitaxial layer 2 is higher than the doping concentration of the drift region 11 to form charge balance with the filling layer 211, and realize the transistor turn-on voltage drop down.
  • This embodiment provides an insulated gate bipolar transistor with a superjunction structure. Please refer to FIG. Trench 21, second conductivity type filling layer 211, gate structure, second conductivity type body region 22, second conductivity type body contact region 221, first conductivity type source region 23, isolation dielectric layer 3 and source An extremely conductive layer 4, wherein the epitaxial layer 2 is located on the upper surface of the drift region 11, the doping concentration of the epitaxial layer 2 is higher than that of the drift region 11, and the trench 21 is located on the upper surface of the drift region 11.
  • the filling layer 211 and the gate structure are sequentially arranged in the trench 21 from bottom to top, the gate structure includes a gate dielectric layer 212 and a gate conductive layer 213, and the gate The dielectric layer 212 is located on the inner wall of the trench 21 and the upper surface of the filling layer 211 and wraps the sidewall and bottom surface of the gate conductive layer 213.
  • the body contact region 221 and the source region 23 are located in the body In the upper surface layer of the region 22 and adjacent to the body region 22, the isolation dielectric layer 3 covers the upper surface of the source region 23 and the upper surface of the gate conductive layer 213, and the isolation dielectric layer 3 is set There is a contact hole 31 penetrating through the isolation dielectric layer 3, the contact hole 31 exposes the source region 23 and the body contact region 221 at the same time, the source conductive layer 4 fills the contact hole 31 and covers the Describe the isolation dielectric layer 3.
  • the upper surface of the filling layer 211 and the lower surface of the gate conductive layer 213 are lower than the bottom surface of the body region 22 .
  • the IGBT further includes a first conductivity type buffer layer 13, a second conductivity type emitter 12 and a drain conductive layer 5, the buffer layer 13 is located on the back of the drift region 11, the The emitter 12 is located on the back of the buffer layer 13 , and the drain conductive layer 5 is located on the back of the emitter 12 .
  • the doping concentration of the buffer layer 12 is higher than that of the drift region 11 to generate conductance modulation, reduce the internal resistance of the transistor, and further reduce the turn-on voltage drop V ce of the transistor.
  • the transistor can be regarded as a thick base transistor driven by a MOSFET, and a PN junction is formed between the buffer layer 13 and the emitter 12 .
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the MOSFET is an N-channel field effect transistor
  • the transistor is a PNP transistor.
  • the gate conductive layer 213 When the gate conductive layer 213 When the voltage is greater than the turn-on voltage of the transistor, a channel is formed in the MOSFET and electron flow is generated, the PN junction formed between the buffer layer 13 and the emitter 12 is turned on, and the emitter 12 is connected to the The buffer layer 13 and the drift region 11 inject holes, and adjust the resistivity between the emitter 12 and the buffer layer 13 to reduce the total loss of the transistor turn-on.
  • a source passivation layer is provided on the upper surface of the source conductive layer 4 .
  • the filling layer 211 extracts the minority carriers of the epitaxial layer 2 and the drift region 11 to reduce the turn-off loss E off , and further reduce the turn-on voltage drop V ce .
  • the filling layer 211 shields the overlapping area between the bottom of the trench 21 and the drift region 11 to reduce the gate charge Q gc , thereby further reducing the turn-on voltage drop V ce .
  • the filling layer 211 is provided in the trench 21 under the gate conductive layer 213 in the trench 21 to shield remove the overlapping area between the bottom of the gate conductive layer 213 and the drift region 11 to reduce the gate charge Q gc , and use the filling layer 211 to extract the epitaxial layer 2 and the The minority carriers in the drift region 11, thereby reducing the turn-off loss E off of the transistor, thereby further reducing the turn-on voltage drop V ce of the transistor.
  • the insulated gate bipolar transistor with super junction structure and its manufacturing method of the present invention redesign the gate structure in the trench, under the gate conductive layer in the trench and located in the trench Form the second conductivity type filling layer at the bottom of the trench to shield the overlapping area of the trench bottom and the first conductivity type drift region, thereby reducing the gate charge Q gc , and use the filling layer to extract the minority carriers in the epitaxial layer and the drift region to reduce the transistor
  • the turn-off loss E off , and the doping concentration of the epitaxial layer and the buffer layer of the first conductivity type is higher than the doping concentration of the drift region to produce a conductance modulation effect, reduce the internal resistance of the transistor, and then reduce the turn-on voltage drop of the transistor V ce . Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

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Abstract

本发明提供一种带有超结结构的绝缘栅双极型晶体管及其制备方法，该晶体管包括第一导电类型漂移区、外延层、多个间隔设置的沟槽、第二导电类型填充层、栅极结构、体区、体接触区、源区、隔离介质层及源极导电层，其中，外延层位于漂移区的上表面，填充层与栅极结构自下而上依次设置于沟槽中，栅极结构包括栅导电层及位于沟槽内壁和填充层上表面且包裹栅导电层侧壁与底面的栅介质层，体接触区及源区位于体区的上表层且与体区的上表面邻接，隔离介质层中设有贯穿隔离介质层且显露源区及体接触区的接触孔，源极导电层填充于接触孔并覆盖隔离介质层。本发明通过于沟槽底部形成填充层以屏蔽沟槽底部与漂移区的重叠面积，从而降低栅极电荷Q gc。

Description

带有超结结构的绝缘栅双极型晶体管及其制备方法 技术领域
本发明属于半导体集成电路制造技术领域，涉及一种带有超结结构的绝缘栅双极型晶体管及其制备方法。
背景技术
绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)是电能转换和传输的核心器件，是电力电子装置的“CPU”。IGBT器件的关键参数包括导通压降V ce、开关损耗E off以及短路承受时间t sc。
在IGBT结构发展过程中，沟槽栅技术以及载流子存储技术的应用，极大降低了导通压降V ce，是IGBT的重要技术。如图1所示，为现有技术中平面栅型绝缘栅双极型晶体管的剖面结构示意图，包括N-漂移区10、N缓冲区101、P发射极102、漏极103、P-体区104、P+接触区105、N+源区106、栅极1071、栅氧化层1072、隔离介质层108及源极109，如图2所示，为现有技术中一种沟槽栅型绝缘栅双极型晶体管的剖面结构示意图，包括N-漂移区10、N缓冲区101、P发射极102、漏极103、P-体区104、P+接触区105、N+源区106、沟槽107、栅极1071、隔离介质层108、接触孔1081及源极109，其中，沟槽栅技术是相对平面栅IGBT，沟槽IGBT结构没有包含结型场效应晶体管(Junction Field-Effect Transistor，JFET)的功能，因此没有JFET效应，消除了JFET电阻，减小了导通电阻，即实现了降低导通压降的目的。如图3所示，为载流子存储型的沟槽栅绝缘栅双极型晶体管的剖面结构示意图，包括N-漂移区10、载流子存储区100、N缓冲区101、P发射极102、漏极103、P-体区104、P+接触区105、N+源区106、沟槽107、栅极1071、隔离介质层108、接触孔1081及源极109，其中，载流子存储技术是通过在如图3所示结构中掺杂合适浓度的杂质以形成载流子存储区100，以增强电导调制效应，实现了降低导通压降的目的。虽然沟槽栅技术降低了导通压降V ce，但同时也带来了栅极电荷Q gc的增大，导致关断功耗E off增加的问题。
因此，急需开发出一种能够既可以降低导通压降V ce又可以降低关断功耗E off的绝缘栅双极晶体管。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种绝缘栅双极型晶体管及其制备方法，用于解决现有技术中绝缘栅双极型晶体管降低导通压降V ce后关断功耗E off的问题。
为实现上述目的及其他相关目的，本发明提供一种带有超结结构的绝缘栅双极型晶体管的制备方法，包括以下步骤：
提供一第一导电类型的衬底以形成第一导电类型漂移区，并于所述衬底上表面形成一第一导电类型外延层，所述外延层的掺杂浓度高于所述衬底的掺杂浓度；
于所述外延层中形成多个间隔设置的沟槽，并于所述沟槽中形成第二导电类型填充层，且所述填充层的上表面低于所述外延层的顶面；
于所述沟槽的内壁及所述填充层的上表面形成一栅介质层，再形成侧壁及底面被所述栅介质层包裹的栅导电层于所述沟槽中，且所述栅导电层的上表面低于所述外延层的顶面；
于所述沟槽两侧的所述外延层的上表层中形成第二导电类型体区，于所述体区的上表层中形成邻接的第二导电类型体接触区及第一导电类型源区，并形成覆盖所述外延层的上表面及所述栅导电层的上表面的隔离介质层；
形成贯穿所述隔离介质层的接触孔以同时显露所述源区及所述体接触区，并形成源极导电层，所述源极导电层填充于所述接触孔中并覆盖所述隔离介质层。
可选地，所述绝缘栅双极型晶体管的制备方法还包括以下步骤：
从所述衬底底面减薄所述衬底至预设厚度；
自所述衬底的底面先后进行离子注入以形成第一导电类型缓冲层及第二导电类型发射极，所述缓冲层在垂直方向上位于所述漂移区与所述发射极之间；
于所述衬底的底面形成与所述发射极电连接的漏极导电层。
可选地，所述第一导电类型与所述第二导电类型的导电类型相反，且所述第一导电类型的导电类型包括N型及P型中的一种，所述第二导电类型的导电类型包括N型及P型中的一种。
可选地，形成所述填充层还包括以下步骤：。
形成第二导电类型导电材料于所述沟槽中及所述外延层上表面；
去除所述外延层上表面的所述导电材料，并去除所述沟槽中的所述导电材料至预设深度以形成第二导电类型填充层。
可选地，形成所述栅导电层还包括以下步骤：
形成栅极导电材料于所述沟槽中及所述外延层上；
去除位于所述外延层上的所述栅极导电材料，并去除所述沟槽中的所述栅极导电材料至预设深度以形成所述栅导电层。
可选地，所述填充层的上表面及所述栅导电层的下表面低于所述体区的底面。
本发明还提供了一种带有超结结构的绝缘栅双极型晶体管，包括：
漂移区；
外延层，位于所述漂移区的上表面，所述外延层的掺杂浓度高于所述漂移区的掺杂浓度；
多个间隔设置的沟槽，位于所述外延层中；
第二导电类型填充层及栅极结构，自下而上依次设置于所述沟槽中，所述栅极结构包括栅介质层及栅导电层，所述栅介质层位于所述沟槽的内壁及所述填充层的上表面并包裹所述栅导电层的侧壁与底面；
第二导电类型体区，位于所述沟槽两侧的所述外延层的上表层中；
邻接的第二导电类型体接触区与第一导电类型源区，位于所述体区的上表层中；
隔离介质层，覆盖所述源区的上表面及所述栅导电层的上表面，且所述隔离介质层中设置有贯穿所述隔离介质层的接触孔，所述接触孔同时显露所述源区及所述体接触区；
源极导电层，填充于所述接触孔并覆盖所述隔离介质层。
可选地，所述填充层的上表面及所述栅导电层的下表面低于所述体区的底面。
可选地，所述绝缘栅双极型晶体管还包括第一导电类型缓冲层、第二导电类型发射极及漏极导电层，所述缓冲层位于所述漂移区背面，所述发射极位于所述缓冲层背面，所述漏极导电层位于所述发射极背面。
如上所述，本发明的带有超结结构的绝缘栅双极型晶体管及其制备方法通过于第一导电类型的所述外延层中形成多个间隔设置的沟槽，并于所述沟槽中形成上表面低于所述外延层的顶面的第二导电类型填充层，于所述沟槽的内壁及所述填充层的上表面形成所述栅介质层，再形成侧壁及底面被所述栅介质层包裹的所述栅导电层于所述沟槽中，且所述栅导电层的上表面低于所述外延层的顶面，所述填充层的上表面及所述栅导电层的下表面低于所述体区的底面，所述外延层的掺杂浓度高于所述漂移区的掺杂浓度，降低了导通压降V ce，且所述外延层与所述填充层形成电荷平衡，在关断所述晶体管的过程中，所述填充层快速抽取所述外延层及所述漂移区中的少子，降低了关断功耗E off。此外，所述填充层屏蔽掉所述沟槽底部与所述漂移区的重叠面积，从而降低了栅极电荷Q gc，具有高度产业利用价值。
附图说明
图1显示为现有技术中平面栅型绝缘栅双极型晶体管的剖面结构示意图。
图2显示为现有技术中一种沟槽栅型绝缘栅双极型晶体管的剖面结构示意图。
图3显示为现有技术中一种载流子存储型的沟槽栅绝缘栅双极型晶体管的剖面结构示意 图。
图4显示为本发明的带有超结结构的绝缘栅双极型晶体管的制备方法流程图。
图5显示为本发明的带有超结结构的绝缘栅双极型晶体管的制备方法中的形成外延层后的剖面结构示意图。
图6显示为本发明的带有超结结构的绝缘栅双极型晶体管的制备方法中于外延层中形成沟槽后的剖面结构示意图。
图7显示为本发明的带有超结结构的绝缘栅双极型晶体管的制备方法中于沟槽中填充第二导电类型导电材料后的剖面结构示意图。
图8显示为本发明的带有超结结构的绝缘栅双极型晶体管的制备方法中形成填充层后的剖面结构示意图。
图9显示为本发明的带有超结结构的绝缘栅双极型晶体管的制备方法中于沟槽内壁及填充层的上表面形成栅介质层后的剖面结构示意图。
图10显示为本发明的带有超结结构的绝缘栅双极型晶体管的制备方法中于沟槽中形成栅极导电材料后的剖面结构示意图。
图11显示为本发明的带有超结结构的绝缘栅双极型晶体管的制备方法中形成栅导电层后的剖面结构示意图。
图12显示为本发明的带有超结结构的绝缘栅双极型晶体管的制备方法中形成第二导电类型体区、第二导电类体接触区及第一导电类型源区后的剖面结构示意图。
图13显示为本发明的带有超结结构的绝缘栅双极型晶体管的制备方法中形成隔离介质层后的剖面结构示意图。
图14显示为本发明的带有超结结构的绝缘栅双极型晶体管的制备方法中形成接触孔后的剖面结构示意图。
图15显示为本发明的带有超结结构的绝缘栅双极型晶体管的制备方法中形成源极导电层后的剖面结构示意图。
图16显示为本发明的带有超结结构的绝缘栅双极型晶体管的制备方法中形成第二导电类型发射极及第一导电类型缓冲层后的剖面结构示意图。
图17显示为本发明的带有超结结构的绝缘栅双极型晶体管的制备方法中形成漏极导电层后的剖面结构示意图。
元件标号说明：
10                     N-漂移区
100                    载流子存储区
101                    N缓冲区
102                    P发射极
103                    漏极
104                    P-体区
105                    P+接触区
106                    N+源区
107                    沟槽
1071                   栅极
1072                   栅氧化层
108                    隔离介质层
1081                   接触孔
109                    源极
1                      衬底
11                     漂移区
12                     发射极
13                     缓冲层
2                      外延层
21                     沟槽
211                    填充层
2111                   导电材料
212                    栅介质层
213                    栅导电层
2131                   栅极导电材料
22                     体区
221                    体接触区
23                     源区
3                      隔离介质层
31                     接触孔
4                      源极导电层
5                      漏极导电层
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图4至图17。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例一
本实施例提供一种带有超结结构的绝缘栅双极型晶体管的制备方法，请参阅图4，为该绝缘栅双极型晶体管的制备方法的流程图，包括以下步骤：
S1：提供一第一导电类型的衬底以形成第一导电类型漂移区，并于所述衬底上表面形成一第一导电类型外延层，所述外延层的掺杂浓度高于所述衬底的掺杂浓度；
S2：于所述外延层中形成多个间隔设置的沟槽，并于所述沟槽中形成第二导电类型填充层，且所述填充层的上表面低于所述外延层的顶面；
S3：于所述沟槽的内壁及所述填充层的上表面形成一栅介质层，再形成侧壁及底面被所述栅介质层包裹的栅导电层于所述沟槽中，且所述栅导电层的上表面低于所述外延层的顶面；
S4：于所述沟槽两侧的所述外延层的上表层中形成第二导电类型体区，于所述体区的上表层中形成邻接的第二导电类型体接触区及第一导电类型源区，并形成覆盖所述外延层的上表面及所述栅导电层的上表面的隔离介质层；
S5：形成贯穿所述隔离介质层的接触孔以同时显露所述源区及所述体接触区，并形成源极导电层，所述源极导电层填充于所述接触孔中并覆盖所述隔离介质层。
首先请参阅图5，执行所述步骤S1：提供一第一导电类型的衬底1以形成第一导电类型漂移区11，并于所述衬底1上表面形成一第一导电类型外延层2，所述外延层2的掺杂浓度高于所述衬底1的掺杂浓度。
具体的，所述衬底1的材质包括第一导电类型硅或者其他适合的半导体材料，所述外延 层2的材质包括第一导电类型硅或者其他适合的半导体材料。
具体的，形成所述外延层2的方法包括化学气相沉积、物理气相沉积或者其他适合的方法。
具体的，所述衬底1及所述外延层2的具体掺杂浓度根据实际需要进行选择，这里不做限定。
具体的，所述外延层2的厚度可以根据实际情况进行设定，这里不做限定。
请参阅图6至图8，执行所述步骤S2：于所述外延层2中形成多个间隔设置的沟槽21，并于所述沟槽21中形成第二导电类型填充层211，且所述填充层211的上表面低于所述外延层2的顶面。
作为示例，所述第一导电类型与所述第二导电类型的导电类型相反，且所述第一导电类型包括N型及P型中的一种，所述第二导电类型包括N型及P型中的一种。本实施例中，所述第一导电类型为N型，所述第二导电类型为P型。
具体的，形成所述沟槽21之前还包括于所述外延层2的上表面形成一掩膜层，并图案化所述掩膜层；再刻蚀所述外延层2以形成所述沟槽21。
具体的，如图6所示，为形成所述沟槽21后的剖面结构示意图，形成所述沟槽21的方法包括湿法刻蚀、干法刻蚀或者其他适合的方法。
作为示例，如图7所示，形成所述填充层211还包括以下步骤：
形成第二导电类型导电材料2111于所述沟槽21中及所述外延层2上表面；
去除所述外延层2上表面的所述导电材料2111，并去除所述沟槽21中的所述导电材料2111至预设深度以形成第二导电类型填充层211。
具体的，形成所述导电材料2111于所述沟槽21中的方法包括学气相沉积、物理气相沉积或者其他适合的方法。
具体的，所述导电材料2111的材质包括第二导电类型硅或者其他适合的半导体材料。
具体的，去除所述外延层2上表面的所述导电材料2111的方法包括化学机械研磨法或者其他适合的方法。
具体的，如图8所示，去除所述沟槽21中的所述导电材料2111至预设深度的方法包括湿法刻蚀、干法刻蚀或者其他适合的方法。
再请参阅图9至图13，执行所述步骤S3与所述步骤S4：于所述沟槽21的内壁及所述填充层211的上表面形成一栅介质层212，再形成侧壁及底面被所述栅介质层212包裹的栅导电层213于所述沟槽21中，且所述栅导电层213的上表面低于所述外延层2的顶面；于所述 沟槽21两侧的所述外延层2的上表层中形成第二导电类型体区22，于所述体区22的上表层中形成邻接的第二导电类型体接触区221及第一导电类型源区23，并形成覆盖所述外延层2的上表面及所述栅导电层213的上表面的隔离介质层3。
具体的，所述栅介质层212的材质包括二氧化硅或者其他适合的材料。
具体的，如图9所示，形成所述栅介质层212的方法包括化学气相沉积法、热氧化法或者其他适合的方法，且所述栅介质层212的厚度根据具体情况决定，这里不做限定。本实施例中，采用热氧化法于所述沟槽21侧壁及所述填充层211的上表面生长一层薄的栅氧化层，并去除所述外延层2上表面的所述栅氧化层以形成所述栅介质层212。
作为示例，形成所述栅导电层213还包括以下步骤：
形成栅极导电材料2131于所述沟槽21中及所述外延层2上；
去除位于所述外延层2上的所述栅极导电材料2131，并去除所述沟槽21中的所述栅极导电材料2131至预设深度以形成栅导电层213。
具体的，如图10所示，形成所述栅极导电材料2131于所述沟槽21中的方法包括化学气相沉积、物理气相沉积或者其他适合的方法。
具体的，所述栅极导电材料2131的材质包括多晶硅或者其他适合的材料。本实施例中，采用多晶硅作为栅极导电材料。
具体的，去除所述外延层2上表面的所述栅极导电材料2131的方法包括化学机械研磨法或者其他适合的方法。
具体的，如图11所示，去除所述沟槽21中所述栅极导电材料2131的方法包括湿法刻蚀、干法刻蚀或者其他适合的方法。
作为示例，所述填充层211的上表面及所述栅导电层213的下表面低于所述体区22的底面。
具体的，形成所述体区22的方法包括离子注入或者其他适合的方法。
具体的，于所述体区22中形成所述体接触区221的方法包括离子注入或者其他适合的方法。
具体的，所述体接触区221的掺杂浓度高于所述体区22的掺杂浓度。
具体的，于所述体区22中形成所述源区23的方法包括离子注入或者其他适合的方法，所述源区23中的第一导电类型杂质离子的注入深度小于所述体区22中第二导电类型杂质离子的注入深度。本实施例中，如图12所示，采用离子注入的方法，从所述外延层2的上方向所述外延层2的表层中注入第二导电类型杂质离子以形成所述体区22，于所述外延层2的表 层的部分区域继续进行第二导电类型杂质离子的注入以形成所述体接触区221，再从所述外延层2的上方向所述外延层2的表层中注入第一导电类型杂质离子以形成所述源区23，所述体接触区221及所述源区23与所述体区22的上表面邻接，所述体区22、所述体接触区221及所述源区23的离子注入深度根据实际情况决定，这里不做限定。
具体的，所述体接触区221可以与所述源区23并列设置。
具体的，形成所述体区22、所述体接触区221及所述源区23后进行退火处理以激活杂质离子。
具体的，采用氮化硅、二氧化硅或者其他适合的绝缘隔离层作为所述隔离介质层3，所述隔离介质层3的厚度根据实际情况设定，这里不做限定。
具体的，如图13所示，采用化学气相沉积、物理气相沉积或者其他适合的方法形成所述隔离介质层3。
再请参阅图14至图17，执行所述步骤S5：形成贯穿所述隔离介质层3的接触孔31以同时显露所述源区23及所述体接触区221，并形成源极导电层4，所述源极导电层4填充于所述接触孔31中并覆盖所述隔离介质层3。
具体的，形成所述接触孔31还包括于所述隔离介质层3的上表面形成掩膜层，并图案化所述掩膜层，然后根据图案化的所述掩膜层形成所述接触孔31。
具体的，如图14所示，采用湿法刻蚀、干法刻蚀或者其他适合的方法刻蚀所述隔离介质层3及所述外延层2以形成所述接触孔31。
具体的，如图15所示，采用溅射法、物理气相沉积、化学气相沉积法、金属化合物气相沉积法、分子束外延法、原子气相沉积法、原子层沉积法或者其他适合的方法形成所述源极导电层4。
具体的，所述源极导电层4的材质包括钛、氮化钛、银、金、铜、铝及钨中的一种，也可以是其他适合的导电材料。
作为示例，形成所述源极导电层4后还包括于所述源极导电层4的上表面形成源极钝化层(未图示)的步骤。
具体的，形成所述源极钝化层的方法包括化学气相沉积、物理气相沉积及原子层沉积中的一种，也可以是其他适合的方法。
作为示例，形成所述源极导电层4后还包括以下步骤：
从所述衬底1底面减薄所述衬底1至预设厚度；
自所述衬底1的底面先后进行离子注入以形成第一导电类型缓冲层13及第二导电类型发 射极12，所述缓冲层13在垂直方向上位于所述漂移区11与所述发射极12之间；
于所述衬底1的底面形成与所述发射极12电连接的漏极导电层5。
具体的，如图16所示，为形成所述缓冲层13及所述发射极12后的剖面结构示意图，所述缓冲层13叠于所述发射极12的上方，即于所述衬底1的底面下方向所述底面注入第一导电类型杂质离子的离子注入深度大于所述第二导电类型杂质离子的离子注入深度，且两种杂质离子注入完成后，需要进行退火工艺以激活杂质离子形成所述缓冲层13及所述发射极12。
具体的，所述发射极12的厚度及掺杂浓度根据实际情况设定，这里不做限定。
具体的，所述缓冲层13的厚度及掺杂浓度根据实际情况设定，这里不做限定。
具体的，所述漏极导电层5的材质包括钛、氮化钛、银、金、铜、铝及钨中的一种，也可以是其他适合的导电材料。
具体的，如图17所示，为形成所述漏极导电层5后的剖面结构示意图，采用溅射法、物理气相沉积、化学气相沉积法、金属化合物气相沉积法、分子束外延法、原子气相沉积法、原子层沉积法或者其他适合的方法形成所述漏极导电层5。
本实施例的带有超结结构的绝缘栅双极型晶体管的制备方法，通过于所述衬底1中形成向上堆叠的第二导电类型发射极12、第一导电类型缓冲层13及第一导电类型漂移区11，于所述外延层2中形成多个开口向上且间隔设置的所述沟槽21，并于所述沟槽21中形成第二导电类型填充层211，再于所述沟槽21的侧壁及所述填充层211的上表面的所述栅介质层212，于所述沟槽21中形成侧壁及底面被所述栅介质层212包裹且上表面低于所述外延层顶面的所述栅导电层213，所述外延层2掺杂浓度高于所述漂移区11的掺杂浓度以与所述填充层211形成电荷平衡，并实现了所述晶体管导通压降的降低。
实施例二
本实施例中提供一种带有超结结构的绝缘栅双极型晶体管，请参阅图17，为所述绝缘栅双极型晶体管的剖面结构示意图，包括漂移区11、外延层2、多个间隔设置的沟槽21、第二导电类型填充层211、栅极结构、第二导电类型体区22、第二导电类型体接触区221、第一导电类型源区23、隔离介质层3及源极导电层4，其中，所述外延层2位于所述漂移区11的上表面，所述外延层2的掺杂浓度高于所述漂移区11的掺杂浓度，所述沟槽21位于所述外延层2中，所述填充层211及所述栅极结构自下而上依次设置于所述沟槽21中，所述栅极结构包括栅介质层212及栅导电层213，所述栅介质层212位于所述沟槽21的内壁及所述填充层211的上表面并包裹所述栅导电层213的侧壁与底面，所述体接触区221与所述源区23位于所述体区22的上表层中且与所述体区22邻接，所述隔离介质层3覆盖所述源区23的上表 面及所述栅导电层213的上表面，且所述隔离介质层3中设置有贯穿所述隔离介质层3的接触孔31，所述接触孔31同时显露所述源区23及所述体接触区221，所述源极导电层4填充于所述接触孔31并覆盖所述隔离介质层3。
作为示例，所述填充层211的上表面及所述栅导电层213的下表面低于所述体区22的底面。
作为示例，所述绝缘栅双极型晶体管还包括第一导电类型缓冲层13、第二导电类型发射极12及漏极导电层5，所述缓冲层13位于所述漂移区11背面，所述发射极12位于所述缓冲层13背面，所述漏极导电层5位于所述发射极12背面。
具体的，所述缓冲层12的掺杂浓度高于所述漂移区11的掺杂浓度以产生电导调制，降低所述晶体管的内阻，进而降低所述晶体管的导通压降V ce。
具体的，所述晶体管可以看作由MOSFET驱动的厚基区晶体管，所述缓冲层13与所述发射极12之间形成有PN结。本实施例中，所述第一导电类型为N型，第二导电类型为P型，则所述MOSFET为N沟道场效应管，所述晶体管为PNP型晶体管，当所述栅导电层213的电压大于所述晶体管的开启电压时，所述MOSFET内形成沟道并产生电子流，所述缓冲层13与所述发射极12之间形成的PN结导通，所述发射极12向所述缓冲层13及所述漂移区11注入空穴，并调整所述发射极12向所述缓冲层13之间的电阻率，降低所述晶体管导通的总损耗。
作为示例，所述源极导电层4的上表面设置有源极钝化层。
作为示例，所述晶体管在关断过程中，所述填充层211抽取所述外延层2及所述漂移区11的少子以降低关断损耗E off，进一步降低导通压降V ce。
作为示例，所述填充层211屏蔽掉所述沟槽21底部与所述漂移区11的重叠面积以降低栅极电荷Q gc，从而进一步降低导通压降V ce。
本实施例的带有超结结构的绝缘栅双极型晶体管结构，通过于所述沟槽21中所述栅导电层213的下方的所述沟槽21中设置所述填充层211，以屏蔽掉所述栅导电层213底部与所述漂移区11的重叠面积以降低栅极电荷Q gc，且于所述晶体管关断的过程中，利用所述填充层211抽取所述外延层2及所述漂移区11中的少子，从而降低所述晶体管的关断损耗E off，从而进一步降低所述晶体管的导通压降V ce。
综上所述，本发明的带有超结结构的绝缘栅双极型晶体管及其制备方法通过对沟槽中的栅极结构重新设计，于沟槽中的栅导电层的下方且位于沟槽的底部形成第二导电类型填充层以屏蔽沟槽底部与第一导电类型漂移区的重叠面积，从而降低栅极电荷Q gc，并利用填充层抽 取外延层及漂移区中的少子以降低晶体管的关断损耗E off，又利用外延层与第一导电类型缓冲层的掺杂浓度高于漂移区掺杂浓度，以产生电导调制效应，降低所晶体管的内阻，进而降低晶体管的导通压降V ce。所以，本发明有效克服了现有技术中的种种缺点而具有高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (15)

  1. 一种带有超结结构的绝缘栅双极型晶体管的制备方法，其特征在于，包括以下步骤：
    提供一第一导电类型的衬底以形成第一导电类型漂移区，并于所述衬底上表面形成一第一导电类型外延层，所述外延层的掺杂浓度高于所述衬底的掺杂浓度；
    于所述外延层中形成多个间隔设置的沟槽，并于所述沟槽中形成第二导电类型填充层，且所述填充层的上表面低于所述外延层的顶面；
    于所述沟槽的内壁及所述填充层的上表面形成一栅介质层，再形成侧壁及底面被所述栅介质层包裹的栅导电层于所述沟槽中，且所述栅导电层的上表面低于所述外延层的顶面；
    于所述沟槽两侧的所述外延层的上表层中形成第二导电类型体区，于所述体区的上表层中形成邻接的第二导电类型体接触区及第一导电类型源区，并形成覆盖所述外延层的上表面及所述栅导电层的上表面的隔离介质层；
    形成贯穿所述隔离介质层的接触孔以同时显露所述源区及所述体接触区，并形成源极导电层，所述源极导电层填充于所述接触孔中并覆盖所述隔离介质层。
  2. 根据权利要求1所述的带有超结结构的绝缘栅双极型晶体管的制备方法，其特征在于，还包括以下步骤：
    从所述衬底底面减薄所述衬底至预设厚度；
    自所述衬底的底面先后进行离子注入以形成第一导电类型缓冲层及第二导电类型发射极，所述缓冲层在垂直方向上位于所述漂移区与所述发射极之间；
    于所述衬底的底面形成与所述发射极电连接的漏极导电层。
  3. 根据权利要求2所述的带有超结结构的绝缘栅双极型晶体管的制备方法，其特征在于，所述缓冲层的掺杂浓度高于所述漂移区的掺杂浓度。
  4. 根据权利要求1所述的带有超结结构的绝缘栅双极型晶体管的制备方法，其特征在于：所述第一导电类型与所述第二导电类型的导电类型相反，且所述第一导电类型包括N型及P型中的一种，所述第二导电类型包括N型及P型中的一种。
  5. 根据权利要求1所述的带有超结结构的绝缘栅双极型晶体管的制备方法，其特征在于，形成所述填充层包括以下步骤：
    形成第二导电类型导电材料于所述沟槽中及所述外延层上表面；
    去除所述外延层上表面的所述导电材料，并去除所述沟槽中的所述导电材料至预设深度以形成第二导电类型填充层。
  6. 根据权利要求1所述的带有超结结构的绝缘栅双极型晶体管的制备方法，其特征在于，形成所述栅导电层包括以下步骤：
    形成栅极导电材料于所述沟槽中及所述外延层上；
    去除位于所述外延层上的所述栅极导电材料，并去除所述沟槽中的所述栅极导电材料至预设深度以形成所述栅导电层。
  7. 根据权利要求1所述的带有超结结构的绝缘栅双极型晶体管的制备方法，其特征在于：所述填充层的上表面及所述栅导电层的下表面低于所述体区的底面。
  8. 根据权利要求1所述的带有超结结构的绝缘栅双极型晶体管的制备方法，其特征在于，所述制备方法还包括以下步骤：于所述源极导电层的上表面形成源极钝化层。
  9. 根据权利要求1所述的带有超结结构的绝缘栅双极型晶体管的制备方法，其特征在于，所述外延层的掺杂浓度高于所述漂移区的掺杂浓度。
  10. 一种带有超结结构的绝缘栅双极型晶体管，其特征在于，包括：
    漂移区；
    外延层，位于所述漂移区的上表面，所述外延层的掺杂浓度高于所述漂移区的掺杂浓度；
    多个间隔设置的沟槽，位于所述外延层中；
    第二导电类型填充层及栅极结构，自下而上依次设置于所述沟槽中；所述栅极结构包括栅介质层及栅导电层，所述栅介质层位于所述沟槽的内壁及所述填充层的上表面并包裹所述栅导电层的侧壁与底面；
    第二导电类型体区，位于所述沟槽两侧的所述外延层的上表层中；
    邻接的第二导电类型体接触区与第一导电类型源区，位于所述体区的上表层中；
    隔离介质层，覆盖所述源区的上表面及所述栅导电层的上表面，且所述隔离介质层中设置有贯穿所述隔离介质层的接触孔，所述接触孔同时显露所述源区及所述体接触区；
    源极导电层，填充于所述接触孔并覆盖所述隔离介质层。
  11. 根据权利要求10所述的带有超结结构的绝缘栅双极型晶体管，其特征在于：所述填充层的上表面及所述栅导电层的下表面低于所述体区的底面。
  12. 根据权利要求10所述的带有超结结构的绝缘栅双极型晶体管，其特征在于：所述绝缘栅双极型晶体管还包括第一导电类型缓冲层、第二导电类型发射极及漏极导电层，所述缓冲层位于所述漂移区背面，所述发射极位于所述缓冲层背面，所述漏极导电层位于所述发射极背面。
  13. 根据权利要求12所述的带有超结结构的绝缘栅双极型晶体管，其特征在于：所述缓冲层的掺杂浓度高于所述漂移区的掺杂浓度。
  14. 根据权利要求10所述的带有超结结构的绝缘栅双极型晶体管，其特征在于：所述第一导电类型与所述第二导电类型的导电类型相反，且所述第一导电类型包括N型及P型中的一种，所述第二导电类型包括N型及P型中的一种。
  15. 根据权利要求10所述的带有超结结构的绝缘栅双极型晶体管，其特征在于：所述源极导电层的上表面设置有源极钝化层。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117712122A (zh) * 2024-02-08 2024-03-15 深圳天狼芯半导体有限公司 碳化硅igbt的结构、制造方法及电子设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104969357A (zh) * 2013-02-05 2015-10-07 三菱电机株式会社 绝缘栅型碳化硅半导体装置及其制造方法
CN109192772A (zh) * 2018-08-29 2019-01-11 电子科技大学 一种沟槽型绝缘栅双极晶体管及其制备方法
CN110709997A (zh) * 2017-06-06 2020-01-17 三菱电机株式会社 半导体装置以及电力变换装置
CN111886680A (zh) * 2018-03-28 2020-11-03 三菱电机株式会社 碳化硅半导体装置及其制造方法
JP6981585B1 (ja) * 2020-08-25 2021-12-15 三菱電機株式会社 半導体装置、電力変換装置、および半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104969357A (zh) * 2013-02-05 2015-10-07 三菱电机株式会社 绝缘栅型碳化硅半导体装置及其制造方法
CN110709997A (zh) * 2017-06-06 2020-01-17 三菱电机株式会社 半导体装置以及电力变换装置
CN111886680A (zh) * 2018-03-28 2020-11-03 三菱电机株式会社 碳化硅半导体装置及其制造方法
CN109192772A (zh) * 2018-08-29 2019-01-11 电子科技大学 一种沟槽型绝缘栅双极晶体管及其制备方法
JP6981585B1 (ja) * 2020-08-25 2021-12-15 三菱電機株式会社 半導体装置、電力変換装置、および半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117712122A (zh) * 2024-02-08 2024-03-15 深圳天狼芯半导体有限公司 碳化硅igbt的结构、制造方法及电子设备
CN117712122B (zh) * 2024-02-08 2024-04-26 深圳天狼芯半导体有限公司 碳化硅igbt的结构、制造方法及电子设备

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