WO2023116093A1 - 嵌入式控制电路、控制方法、装置及芯片 - Google Patents

嵌入式控制电路、控制方法、装置及芯片 Download PDF

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WO2023116093A1
WO2023116093A1 PCT/CN2022/120577 CN2022120577W WO2023116093A1 WO 2023116093 A1 WO2023116093 A1 WO 2023116093A1 CN 2022120577 W CN2022120577 W CN 2022120577W WO 2023116093 A1 WO2023116093 A1 WO 2023116093A1
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instruction
module
request
program
cache module
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PCT/CN2022/120577
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English (en)
French (fr)
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王世好
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合肥市芯海电子科技有限公司
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Publication of WO2023116093A1 publication Critical patent/WO2023116093A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/451—Execution arrangements for user interfaces
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication

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  • the present application relates to the field of computer technology, in particular to an embedded control circuit, control method, device and chip.
  • a computer usually consists of a processor, a memory, a display, and a human-machine interface (keyboard, mouse, audio, etc.).
  • the processor (CPU) of the computer runs at a high speed, and the access to high-speed devices is fast.
  • the CPU's access to low-speed devices such as keyboards and GPIOs, will slow down the CPU's operating speed due to the slow response of low-speed devices.
  • the usual solution is to design an embedded controller (Embedded Controller, referred to as EC), which is placed on the computer motherboard to manage the low-speed devices of the computer. Remap CPU access to slow devices to CPU and EC chip access. In this way, the slow device access is handed over to the EC chip to ensure that the CPU runs at full speed and computer performance.
  • EC embedded Controller
  • the technical architecture of an EC chip usually consists of a processor, a bus matrix, on-chip random access memory (SRAM), a security module, and peripheral interfaces.
  • the memory in this architecture has only random access storage (RAM) and no non-volatile storage (ROM). This architecture has a slow power-on startup speed and high security risks.
  • the present application provides an embedded control circuit, a control method, a device and a chip, which can accelerate the power-on and start-up speed and reduce safety risks.
  • a technical solution adopted by this application is to provide a control method for an embedded control circuit, the embedded control circuit includes a processor, a non-volatile memory module and a The instruction cache module of the non-volatile memory module, the control method includes:
  • the instruction cache module after the judging whether there is a program instruction corresponding to the request in the instruction cache module, it further includes:
  • the storage block storing the program instruction from the non-volatile storage module and adding the storage block to the instruction cache module further includes:
  • the first address is stored in a preset address list.
  • the judging whether there is a program instruction corresponding to the request in the instruction cache module includes:
  • the obtaining the storage block storing the program instruction from the non-volatile storage module, adding the storage block to the instruction cache module further includes:
  • the selecting a target cache block from the instruction cache module includes:
  • the cache block with the smallest historical access amount is determined as the target cache block.
  • an embedded control circuit including: a processor, a non-volatile storage module, and a The instruction cache module,
  • the non-volatile storage module is used to store program instructions
  • the instruction cache module is used to cache the program instructions
  • the processor is used to execute the program instructions
  • the processor When the embedded control circuit is powered on, the processor sends a request for obtaining program instructions to the instruction cache module; the instruction cache module receives the request and determines whether there is a The program instruction corresponding to the above request, if it exists, send the program instruction to the processor, if it does not exist, obtain the program instruction from the non-volatile storage module, and add the program instruction into the instruction cache module, and send the program instructions to the processor, and the processor accepts and executes the program instructions.
  • An acquisition module configured to acquire a request sent by the processor to acquire program instructions from the non-volatile storage module after the embedded control circuit is powered on;
  • a judging module configured to judge whether there is a program instruction corresponding to the request in the instruction cache module
  • An execution module configured to send the program instruction to the processor to respond to the request if there is a program instruction corresponding to the request in the instruction cache module.
  • an embedded controller including: the control device for the embedded control circuit.
  • another technical solution adopted by the present application is to provide a chip, including: the embedded controller.
  • the beneficial effect of the present application is: by setting the non-volatile memory module inside the embedded controller, it solves the need to copy the program from the off-chip Flash and decrypt the program every time the power is turned on in the prior art, resulting in low security And reduce the problem of power-on startup speed; the processor obtains the program instructions of the non-volatile storage module through the instruction cache module, and realizes directly obtaining the cached program instructions from the instruction cache module to respond to the request, effectively speeding up the power-on Boot speed.
  • FIG. 1 is a schematic structural diagram of an embedded control circuit according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of an embedded control circuit according to another embodiment of the present application.
  • FIG. 3 is a schematic flow diagram of a control method of an embedded control circuit according to an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a control method of an embedded control circuit according to another embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a control method of an embedded control circuit according to another embodiment of the present application.
  • FIG. 6 is a schematic flowchart of a control method of an embedded control circuit according to another embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a control device of an embedded control circuit according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of an embedded controller according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a chip according to an embodiment of the present application.
  • first”, “second”, and “third” in this application are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, features defined as “first”, “second”, and “third” may explicitly or implicitly include at least one of these features.
  • “plurality” means at least two, such as two, three, etc., unless otherwise specifically defined. All directional indications (such as up, down, left, right, front, back%) in the embodiments of the present application are only used to explain the relative positional relationship between the various components in a certain posture (as shown in the drawings) , sports conditions, etc., if the specific posture changes, the directional indication also changes accordingly.
  • FIG. 1 is a schematic diagram of the architecture of the embedded control circuit of the embodiment of the present application, please refer to Figure 1, the embedded control circuit 10 includes a processor 11, a non-volatile storage module 12 and a connection processor 11, a non-volatile storage module 12 The instruction cache module 13.
  • the non-volatile storage module 12 of this embodiment is used to store program instructions.
  • the processor 11 of this embodiment sends a request for obtaining program instructions to the instruction cache module 13 through the bus matrix 14, and the instruction cache module 13 sends a corresponding request through the bus matrix 14. program instructions in response to the request.
  • the program instruction is sent to the processor 11 to respond to the request; if the instruction cache module 13 If there is no program instruction corresponding to the request, the program instruction is obtained from the non-volatile storage module 12, the program instruction is cached in the instruction cache module 13, and the program instruction is sent to the processor 11 to respond to the request.
  • the non-volatile storage module 12 can be an on-chip Flash, which is integrated inside the embedded controller.
  • the non-volatile storage module 12 also includes on-chip Flash121 and Flash controller 122, wherein the on-chip Flash121 includes a plurality of memory blocks (not shown in the figure), when the instruction cache module 13 needs to obtain the program instruction from the non-volatile storage module 12, it obtains the storage block that stores the corresponding program instruction from the Flash121 and stores the obtained storage block into the instruction cache Module 13.
  • the instruction cache module 13 may include a plurality of cache blocks for storing program instructions. For example, as shown in FIG. 2, the instruction cache module 13 includes a cache block 1 and a cache block 2, and the instruction The storage block obtained by the cache module 13 from the Flash 121 may be stored in the cache block 1 or the cache block 2 .
  • the on-chip Flash 121 in this embodiment can use parallel Flash with a data width of 128bit, 64bit or 32bit.
  • the cost of parallel Flash is higher than that of serial Flash, and parallel Flash has more pins, while the chip can receive fewer pins. Therefore, the combination of off-chip parallel Flash and chip will affect the application of the chip. limits and increase material costs.
  • the off-chip Flash in the prior art is mostly serial Flash, and the data width is 1 bit, 4 bits or 8 bits. For example, taking the data width of off-chip Flash as 1 bit as an example, the Flash storage object is generally larger, and the storage block is generally 128bit.
  • the off-chip Flash needs 128 clock cycles to retrieve the memory block, resulting in a long delay for program loss and affecting system performance.
  • the non-volatile storage module 12 of this embodiment can retrieve a storage block within one clock cycle. Therefore, compared with the existing off-chip Flash, the on-chip non-volatile storage module 12 of this embodiment has higher efficiency in obtaining data, and obtains program instructions by means of cache, without re-starting from the on-chip Copy the program instructions on the external Flash, which effectively speeds up the power-on and start-up speed.
  • the program instruction is sent to the processor 11 to respond to the request; if there is no program instruction corresponding to the request in the instruction cache module 13, the The volatile storage module 12 obtains the storage block storing the program instruction, adds the storage block to the instruction cache module 13, and sends the program instruction to the processor 11 in response to the request. Due to its own characteristics, the speed of the non-volatile memory module 12 is relatively slow (usually 30Mhz speed). If there is no instruction cache module 13, the operating speed of the processor 11 cannot exceed the operating speed (such as 30Mhz) of the non-volatile memory module 12. The non-volatile memory module 12 is a system bottleneck, and the processor 11 will not increase the speed if it runs too fast. System performance. Therefore, the instruction cache module 13 of this embodiment improves system performance and speeds up power-on and start-up speed.
  • the embedded control circuit 10 also includes an SRAM 15 connected to the bus matrix 14 , and the SRAM 15 has the same operating speed as the instruction cache module 13 , that is, the SRAM 15 operates at the operating speed of the processor 11 . In this case, there is no need to copy the program instructions to the SRAM 15 for execution, and the processor 11 directly reads the program instructions from the cache instruction module 13 and executes them.
  • each time the embedded control circuit 10 is powered on it is not necessary to copy the program instructions from the off-chip Flash to the on-chip RAM for execution, and can directly obtain the program instructions from the on-chip non-volatile storage module 12 and execute them on the processor 11.
  • the power-on and start-up speed is accelerated, and the step of copying the program from the off-chip Flash and decrypting the program is omitted every time the power is turned on in the prior art, thereby reducing security risks.
  • the embedded control circuit 10 can be applied to an EC chip, an MCU chip or an SoC chip, and the above-mentioned chip can be applied to a computer device, for example, on a motherboard of a tablet computer, a notebook computer or a server, It is mainly used for low-speed device management on the main board, switch machine management, power management, low power consumption management, communication management, etc., to realize the interaction between the high-performance processor on the main board and the low-speed device (such as keyboard, mouse, audio, etc.) on the main board, so that Improve the performance of the CPU, and solve the problem that the response speed of low-speed devices is slow, which causes the CPU to run at a lower speed.
  • the high-performance processor on the main board such as keyboard, mouse, audio, etc.
  • FIG. 3 is a schematic flowchart of a control method of an embedded control circuit according to an embodiment of the present application. It should be noted that if there are substantially the same results, the method of the present application is not limited to the flow sequence shown in Figure 1. As shown in Figure 3, the method includes steps:
  • Step S301 When the embedded control circuit is powered on, obtain a request from the processor for obtaining program instructions.
  • the state information of the low-speed device is generally stored in the non-volatile storage module in the form of program instructions, so that the computer can save the state information of the low-speed device that has been set before the power is turned off, and wait for the next time the computer When powered on, directly read the state information of the low-speed device in the non-volatile memory module inside the embedded controller, so that the computer can quickly restore to the previous protection state, and solve the problem of low-speed device state information caused by power failure. Data loss requires reading the status information of the low-speed device from the off-chip Flash every time the power is turned on.
  • the low-speed device in this embodiment includes at least one of a keyboard, a mouse, a serial port, and a power supply.
  • the non-volatile storage module in this embodiment can be an on-chip Flash, which is integrated inside the embedded controller.
  • the non-volatile storage module may use parallel Flash with a data width of 128bit, 64bit or 32bit.
  • Step S302 Determine whether there is a program instruction corresponding to the request in the instruction cache module.
  • step S302 the instruction cache module is provided with a preset address list, and the address list stores the first address corresponding to each program instruction stored in the instruction cache module, and the first address is stored in the program instruction.
  • the first address is used as the identifier of the program instruction stored in the instruction cache module.
  • step S302 includes the following steps:
  • Step S401 Obtain a second address corresponding to the request and detect whether there is a first address identical to the second address in the address list.
  • Step S402 If the first address same as the second address exists in the address list, it is determined that there is a program instruction corresponding to the request in the instruction module.
  • Step S403 If there is no first address identical to the second address in the address list, it is determined that there is no program instruction corresponding to the request in the instruction module.
  • the request carries the second address.
  • the header of the second address is compared with the headers of the first addresses in the address list. If the first address and the second address have the same header, the address is considered There is a first address identical to the second address in the list, and if the heads of all the first addresses are different from the headers of the second addresses, it is considered that there is no first address identical to the second address in the address list.
  • Step S303 If there is a program instruction corresponding to the request in the instruction cache module, send the program instruction to the processor to respond to the request.
  • the processor After the embedded control circuit is powered on, the processor sends the first request to read the program instructions from the instruction cache module for the first time. Since the cache space of the instruction cache module is empty at this time, the program instructions fetched are not in the instruction cache module. Cache misses for instructions. When the instruction cache is missing, the instruction cache module acquires a storage block storing the corresponding program instructions from the non-volatile storage module and fills it into the instruction cache module, and at the same time sends the corresponding program instructions to the processor. Next, the processor sends a next request to read the program instructions from the instruction cache module, and if the fetched program instructions are stored in the instruction cache module, the program instructions are sent to the processor in response to the request.
  • step S302 further include:
  • Step S304 If there is no program instruction corresponding to the request in the instruction cache module, obtain the storage block storing the program instruction from the non-volatile storage module, add the storage block to the instruction cache module, and send the program instruction Give the handler a response to the request.
  • the processor sends the first request to read the program instructions from the instruction cache module for the first time. Since the cache space of the instruction cache module is empty at this time, the fetched A program instruction that is not in the instruction cache module is called an instruction cache miss.
  • the instruction cache module acquires a storage block storing the corresponding program instructions from the non-volatile storage module and fills it into the instruction cache module, and at the same time sends the corresponding program instructions to the processor.
  • the processor sends the next request to read the program instruction from the instruction cache module, if the program instruction fetched still does not exist in the instruction cache module, then repeat step S304, if the fetched program instruction If it still exists in the instruction cache module, repeat step S303.
  • step S304 also includes the following steps:
  • Step S601 Calculate the remaining capacity space of the instruction cache module
  • Step S602 comparing the remaining capacity space with the storage space required to store the storage block
  • Step S603 If the remaining capacity space is less than the storage space, then select a target cache block from the instruction cache module, clear the target cache block and store the program instructions in the target cache block;
  • the target cache block is determined according to the historical access amount, specifically, the historical access amount of each cache block in the instruction cache module is counted, and the cache block with the smallest historical access amount is determined as the target cache block.
  • Step S604 If the remaining capacity space is greater than or equal to the storage space, add the storage block into the instruction cache module.
  • the control method of the embedded control circuit in the embodiment of the present application adds an instruction cache module between the processor and the non-volatile storage module, obtains program instructions from the instruction cache module to respond to the request, and omits the need for each upload in the prior art. It is necessary to copy the program from the off-chip Flash and decrypt the program, which speeds up the power-on and startup speed and reduces the security risk.
  • FIG. 7 is a schematic structural diagram of a control device of an embedded control circuit according to an embodiment of the present application.
  • the control device 70 includes an acquisition module 71 , a judgment module 72 and an execution module 73 .
  • the obtaining module 71 is used to obtain the request for obtaining program instructions sent by the processor when the embedded control circuit is powered on;
  • the judging module 72 is used to judge whether there is a program instruction corresponding to the request in the instruction cache module;
  • the execution module 73 is configured to send the program instruction to the processor to respond to the request if there is a program instruction corresponding to the request in the instruction cache module.
  • FIG. 8 is a schematic structural diagram of an embedded controller according to an embodiment of the present application.
  • the embedded controller 80 includes the above-mentioned control device 70 .
  • FIG. 9 is a schematic structural diagram of a chip according to an embodiment of the present application.
  • the chip 90 includes the above-mentioned embedded controller 80 , which may specifically be an EC chip, an MCU chip or a SoC chip.
  • the disclosed system, device and method can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or integrated. to another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

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Abstract

一种嵌入式控制电路、控制方法、装置及芯片，涉及计算机技术领域。该方法包括：当嵌入式控制电路上电时，获取处理器发送的获取程序指令的请求（S301）；判断指令缓存模块中是否存在与请求对应的程序指令（S302）；若指令缓存模块中存在与请求对应的程序指令，则将程序指令发送给处理器以响应所述请求（S303）；若指令缓存模块中不存在与请求对应的程序指令，则从非易失性存储模块中获取存储有程序指令的存储块，将存储块添加入指令缓存模块中，同时将程序指令发送给处理器以响应所述请求（S304）。通过上述方式能够加快启动速度，降低安全风险。

Description

嵌入式控制电路、控制方法、装置及芯片
本申请要求于2021年12月23日提交中国专利局、申请号为202111592264.7，发明名称为“嵌入式控制电路、控制方法、装置及芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，特别是涉及一种嵌入式控制电路、控制方法、装置及芯片。
背景技术
计算机通常有处理器、存储器、显示器、人机接口(键盘、鼠标、音频等)组成。计算机的处理器(CPU)运行速度高，对高速设备访问，访问速度快。但CPU对低速设备的访问，比如键盘、GPIO等，由于低速设备响应速度慢，会拉低CPU的运行速度。通常的解决方法是设计一个嵌入式控制器(Embedded Controller，简称EC)，放置在计算机主板上，用于管理计算机的低速设备。把CPU对慢速设备的访问，重映射成CPU和EC芯片访问。这样，把慢速设备访问交给EC芯片，保证CPU全速运行，保证计算机性能。
背景技术中EC芯片的技术架构，通常有处理器、总线矩阵、片内随机存储(SRAM)、安全模块和***接口组成。这种架构中存储器只有随机存储(RAM)，没有非易失存储(ROM)。这种架构的上电启动速度慢且安全风险高。
发明内容
本申请提供一种嵌入式控制电路、控制方法、装置及芯片，能够加快上电启动速度，降低安全风险。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种嵌 入式控制电路的控制方法，所述嵌入式控制电路包括处理器、非易失性存储模块以及连接所述处理器、所述非易失性存储模块的指令缓存模块，所述控制方法包括：
当所述嵌入式控制电路上电时，获取所述处理器发送的从所述非易失性存储模块获取程序指令的请求；
判断所述指令缓存模块中是否存在与所述请求对应的程序指令；
若所述指令缓存模块中存在与所述请求对应的程序指令，则将所述程序指令发送给所述处理器以响应所述请求。
根据本申请的一个实施例，所述判断所述指令缓存模块中是否存在与所述请求对应的程序指令之后，还包括：
若所述指令缓存模块中不存在与所述请求对应的程序指令，则从所述非易失性存储模块中获取存储有所述程序指令的存储块，将所述存储块添加入所述指令缓存模块中，并将所述程序指令发送给所述处理器以响应所述请求。
根据本申请的一个实施例，所述从所述非易失性存储模块中获取存储有所述程序指令的存储块，将所述存储块添加入所述指令缓存模块中之后，还包括：
生成与所述程序指令对应的第一地址，作为所述程序指令存在所述指令缓存模块的标识；
将所述第一地址存储到预设的地址列表中。
根据本申请的一个实施例，所述判断所述指令缓存模块中是否存在与所述请求对应的程序指令包括：
获取与所述请求对应的第二地址并检测所述地址列表中是否存在与所述第二地址相同的第一地址；
若所述地址列表中存在与所述第二地址相同的第一地址，则判定所述指令模块中存在与所述请求对应的程序指令；
若所述地址列表中不存在与所述第二地址相同的第一地址，则判定所述指令模块中不存在与所述请求对应的程序指令。
根据本申请的一个实施例，所述从所述非易失性存储模块中获取存 储有所述程序指令的存储块，将所述存储块添加入所述指令缓存模块中还包括：
计算所述指令缓存模块的剩余容量空间；
将所述剩余容量空间与存储所述存储块所需的存储空间进行比较；
若所述剩余容量空间小于所述存储空间，则从所述指令缓存模块中选取一个目标缓存块，将所述目标缓存块清空并将所述程序指令存储到所述目标缓存块中；
若所述剩余容量空间大于或等于所述存储空间，则将所述存储块添加入所述指令缓存模块中。
根据本申请的一个实施例，所述从所述指令缓存模块中选取一个目标缓存块包括：
统计所述指令缓存模块中各所述缓存块的历史访问量；
将历史访问量最小的所述缓存块确定为所述目标缓存块。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种嵌入式控制电路，包括：处理器、非易失性存储模块以及连接所述处理器、所述非易失性存储模块的指令缓存模块，
所述非易失性存储模块用于存储程序指令，所述指令缓存模块用于缓存所述程序指令，所述处理器用于执行所述程序指令；
当所述嵌入式控制电路上电时，所述处理器对所述指令缓存模块发送获取程序指令的请求；所述指令缓存模块接收所述请求，并判断所述指令缓存模块中是否存在与所述请求对应的程序指令，若存在，则将所述程序指令发送给所述处理器，若不存在，则从所述非易失性存储模块中获取所述程序指令，将所述程序指令添加入所述指令缓存模块中，并将所述程序指令发送给所述处理器，所述处理器接受并执行所述程序指令。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种嵌入式控制电路的控制装置，包括：
获取模块，用于当所述嵌入式控制电路上电后，获取所述处理器发送的从所述非易失性存储模块获取程序指令的请求；
判断模块，用于判断所述指令缓存模块中是否存在与所述请求对应的程序指令；
执行模块，用于若所述指令缓存模块中存在与所述请求对应的程序指令，则将所述程序指令发送给所述处理器以响应所述请求。
为解决上述技术问题，本申请采用的再一个技术方案是：提供一种嵌入式控制器，包括：所述的嵌入式控制电路的控制装置。
为解决上述技术问题，本申请采用的再一个技术方案是：提供一种芯片，包括：所述的嵌入式控制器。
本申请的有益效果是：通过将非易失性存储模块设于嵌入式控制器内部，解决了现有技术中每次上电需要从片外Flash复制程序并对程序进行解密，导致安全性低以及降低了上电启动速度的问题；处理器通过指令缓存模块获取非易失性存储模块的程序指令，实现从指令缓存模块中直接获取已缓存好的程序指令以响应请求，有效加快了上电启动速度。
附图说明
图1是本申请一实施例的嵌入式控制电路的架构示意图；
图2是本申请又一实施例的嵌入式控制电路的架构示意图；
图3是本申请一实施例的嵌入式控制电路的控制方法的流程示意图；
图4是本申请又一实施例的嵌入式控制电路的控制方法的流程示意图；
图5是本申请又一实施例的嵌入式控制电路的控制方法的流程示意图；
图6是本申请又一实施例的嵌入式控制电路的控制方法的流程示意图；
图7是本申请实施例的嵌入式控制电路的控制装置的结构示意图；
图8是本申请实施例的嵌入式控制器的结构示意图；
图9是本申请实施例的芯片的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请中的术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”、“第三”的特征可以明示或者隐含地包括至少一个该特征。本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。本申请实施例中所有方向性指示(诸如上、下、左、右、前、后……)仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、***、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
图1本申请实施例的嵌入式控制电路的架构示意图，请参见图1，嵌入式控制电路10包括处理器11、非易失性存储模块12以及连接处理器11、非易失性存储模块12的指令缓存模块13。本实施例的非易失性存储模块12用于存储程序指令，该实施例的处理器11通过总线矩阵14发送获取程序指令的请求给指令缓存模块13，指令缓存模块13通过总线矩阵14发送对应的程序指令以响应请求。具体地，判断指令缓存模块 13中是否存在与请求对应的程序指，若指令缓存模块13中存在与请求对应的程序指令，则将程序指令发送给处理器11以响应请求；若指令缓存模块13中不存在与请求对应的程序指令，则从非易失性存储模块12中获取程序指令，将程序指令缓存到指令缓存模块13中，并将程序指令发送给处理器11以响应请求。
非易失性存储模块12可以为片内的Flash，集成于嵌入式控制器的内部。在一种可实现的实施方式中，如图2所示，非易失性存储模块12还包括片内Flash121和Flash控制器122，其中，片内Flash121包括多个存储有程序指令的存储块(图中未示出)，当指令缓存模块13需要从非易失性存储模块12获取程序指令时，从Flash121获取存储有对应的程序指令的存储块并将所获取到的存储块存储到指令缓存模块13中。在一种可实现的实施例中，指令缓存模块13可以包括多个用于存储程序指令的缓存块，示例的，如图2所示，指令缓存模块13包括缓存块1和缓存块2，指令缓存模块13从Flash121获取到的存储块可以存储到缓存块1或缓存块2中。
本实施例的片内Flash121可以采用128bit、64bit或32bit数据宽度的并行Flash。一般情况下，并行Flash比串行Flash的成本更高，并且并行Flash的管脚较多，而芯片所能接收的管脚较少，因此，片外并行Flash与芯片结合会使芯片的应用受限，并且增加材料成本。而现有技术的片外Flash多为串行的Flash，数据宽度为1个bit、4个bit或8个bit。例如，以片外Flash的数据宽度为1个bit为例，Flash存储对象一般比较大，存储块一般为128bit，当指令缓存模块13遇到程序指令缺失时，即指令缓存模块13中不存在与请求对应的程序指令，片外Flash需要128个时钟周期才能把存储块取回来，导致程序缺失的延时较长，影响***性能。而本实施例的非易失性存储模块12可以在一个时钟周期取回存储块。因此，与现有的片外Flash相比，本实施例的片内的非易失性存储模块12获取数据的效率更高，并且通过缓存的方式获取程序指令，无需每次上电重新从片外Flash上拷贝程序指令，有效加快了上电启动速度。
该实施例中，若指令缓存模块13中存在与请求对应的程序指令，则将程序指令发送给处理器11以响应请求；若指令缓存模块13中不存在与请求对应的程序指令，则从非易失性存储模块12中获取存储有程序指令的存储块，将存储块添加入指令缓存模块13中，并将程序指令发送给处理器11以响应请求。非易失性存储模块12由于其自身的特性，速度比较慢(通常30Mhz速度)。如果没有指令缓存模块13，处理器11运行速度不能超过非易失性存储模块12的运行速度(比如30Mhz)，非易失性存储模块12是***瓶颈，处理器11运行太快也不会增加***性能，因此，本实施例的指令缓存模块13提高了***性能，加快了上电启动速度。
如图1和图2所示，嵌入式控制电路10还包括与总线矩阵14连接的SRAM15，SRAM15与指令缓存模块13具有相同的运行速度，即SRAM15按照处理器11的运行速度运行。本案无需将程序指令复制到SRAM15中执行，处理器11直接从缓存指令模块13中读取程序指令并执行。
通过上述方式，嵌入式控制电路10每次上电无需从片外Flash复制程序指令到片内RAM执行，可以直接从片内非易失性存储模块12获取程序指令并在处理器11上执行，加快了上电启动速度，省略了现有技术中每次上电需要从片外Flash复制程序并对程序进行解密的步骤，降低了安全性风险。
在一种可实现的实施例中，嵌入式控制电路10可以应用于EC芯片，MCU芯片或SoC芯片上，上述芯片可以应用于计算机设备上，例如，平板电脑、笔记本电脑或服务器的主板上，主要用于主板上低速设备管理，开关机管理、电源管理、低功耗管理、通信管理等，实现主板上高性能处理器与主板上低速设备(例如键盘、鼠标、音频等)的交互，从而提高CPU的性能，解决了低速设备响应速度慢，导致拉低CPU的运行速度的问题。
图3是本申请实施例的嵌入式控制电路的控制方法的流程示意图。需注意的是，若有实质上相同的结果，本申请的方法并不以图1所示的 流程顺序为限。如图3所示，该方法包括步骤：
步骤S301：当嵌入式控制电路上电时，获取处理器发送的获取程序指令的请求。
在步骤S301中，一般将低速设备的状态信息以程序指令的形式存储在非易失性存储模块，使得计算机在断电之前能够将已经设置好的低速设备的状态信息保存下来，待下次计算机上电时，直接读取嵌入式控制器内部的非易失性存储模块中的低速设备的状态信息，从而使得计算机能够快速恢复至之前的保护状态，解决了低速设备的状态信息因断电导致数据丢失，需要每次上电都从片外Flash读取低速设备的状态信息的问题。本实施例的低速设备包括键盘、鼠标、串口、电源中的至少一种。
该实施例的非易失性存储模块可为片内Flash，集成于嵌入式控制器的内部。在一种可实现的实施方式中，非易失性存储模块可以采用128bit、64bit或32bit数据宽度的并行Flash。
步骤S302：判断指令缓存模块中是否存在与请求对应的程序指令。
在步骤S302中，指令缓存模块中设有预设的地址列表，地址列表中存储有与存储在指令缓存模块中的各程序指令一一对应的第一地址，第一地址在程序指令存储进指令缓存模块时生成，第一地址作为程序指令存在指令缓存模块的标识。
在一种可实现的实施例中，请参见图4，步骤S302包括以下步骤：
步骤S401：获取与请求对应的第二地址并检测地址列表中是否存在与第二地址相同的第一地址。
步骤S402：若地址列表中存在与第二地址相同的第一地址，则判定指令模块中存在与请求对应的程序指令。
步骤S403：若地址列表中不存在与第二地址相同的第一地址，则判定指令模块中不存在与请求对应的程序指令。
该实施例的请求中携带有第二地址，将第二地址的头部与地址列表中各第一地址的头部进行比较，若第一地址和第二地址具有相同的头部，则认为地址列表中存在与第二地址相同的第一地址，若所有第一地址的 头部与第二地址的头部均不相同，则认为地址列表中不存在与第二地址相同的第一地址。
步骤S303：若指令缓存模块中存在与请求对应的程序指令，则将程序指令发送给处理器以响应请求。
嵌入式控制电路上电后，处理器发送第一个请求首次从指令缓存模块中读取程序指令，由于此时指令缓存模块的缓存空间为空，所取的程序指令不在指令缓存模块中，称为指令缓存缺失。在指令缓存缺失的情况下，指令缓存模块从非易失性存储模块获取一个存储有对应程序指令的存储块并填入指令缓存模块中，同时把对应程序指令发送给处理器。接下来，处理器发送下一个请求从指令缓存模块中读取程序指令，若所取程序指令存在指令缓存模块中，则将程序指令发送给处理器以响应请求。
在一种可实现的实施方式中，请参见图5，步骤S302之后，还包括：
步骤S304：若指令缓存模块中不存在与请求对应的程序指令，则从非易失性存储模块中获取存储有程序指令的存储块，将存储块添加入指令缓存模块中，并将程序指令发送给处理器以响应请求。
在一种可实现的实施例中，嵌入式控制电路上电后，处理器发送第一个请求首次从指令缓存模块中读取程序指令，由于此时指令缓存模块的缓存空间为空，所取的程序指令不在指令缓存模块中，称为指令缓存缺失。在指令缓存缺失的情况下，指令缓存模块从非易失性存储模块获取一个存储有对应程序指令的存储块并填入指令缓存模块中，同时把对应程序指令发送给处理器。在另一种可实现的实施例中，处理器发送下一个请求从指令缓存模块中读取程序指令，若所取程序指令仍不存在指令缓存模块中，则重复步骤S304，若所取程序指令仍存在指令缓存模块中，则重复步骤S303。
在一种可实现的实施例中，请参见图6，步骤S304还包括以下步骤：
步骤S601：计算指令缓存模块的剩余容量空间；
步骤S602：将剩余容量空间与存储存储块所需的存储空间进行比较；
步骤S603：若剩余容量空间小于存储空间，则从指令缓存模块中选 取一个目标缓存块，将目标缓存块清空并将程序指令存储到目标缓存块中；
在一种可实现的实施例中，目标缓存块根据历史访问量确定，具体地，统计指令缓存模块中各缓存块的历史访问量，将历史访问量最小的缓存块确定为目标缓存块。
步骤S604：若剩余容量空间大于或等于存储空间，则将存储块添加入指令缓存模块中。
本申请实施例的嵌入式控制电路的控制方法通过在处理器和非易失性存储模块之间增加指令缓存模块，从指令缓存模块获取程序指令以响应请求，省略了现有技术中每次上电需要从片外Flash复制程序并对程序进行解密的步骤，加快了上电启动速度，降低了安全性风险。
图7是本申请实施例的嵌入式控制电路的控制装置的结构示意图。如图7所示，该控制装置70包括获取模块71、判断模块72和执行模块73。
获取模块71用于当所述嵌入式控制电路上电后，获取所述处理器发送的获取程序指令的请求；
判断模块72用于判断所述指令缓存模块中是否存在与所述请求对应的程序指令；
执行模块73用于若所述指令缓存模块中存在与所述请求对应的程序指令，则将所述程序指令发送给所述处理器以响应所述请求。
请参阅图8，图8为本申请实施例的嵌入式控制器的结构示意图。如图8所示，该嵌入式控制器80包括上述控制装置70。
请参阅图9，图9为本申请实施例的芯片的结构示意图。如图9所示，该芯片90包括上述嵌入式控制器80，具体可以为EC芯片，MCU芯片或SoC芯片。
在本申请所提供的几个实施例中，应该理解到，所揭露的***，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以 集成到另一个***，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
以上仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (10)

  1. 一种嵌入式控制电路的控制方法，其特征在于，所述嵌入式控制电路包括处理器、非易失性存储模块以及连接所述处理器、所述非易失性存储模块的指令缓存模块，所述控制方法包括：
    当所述嵌入式控制电路上电时，获取所述处理器发送的获取程序指令的请求；
    判断所述指令缓存模块中是否存在与所述请求对应的程序指令；
    若所述指令缓存模块中存在与所述请求对应的程序指令，则将所述程序指令发送给所述处理器以响应所述请求。
  2. 根据权利要求1所述的控制方法，其特征在于，所述判断所述指令缓存模块中是否存在与所述请求对应的程序指令之后，还包括：
    若所述指令缓存模块中不存在与所述请求对应的程序指令，则从所述非易失性存储模块中获取存储有所述程序指令的存储块，将所述存储块添加入所述指令缓存模块中，并将所述程序指令发送给所述处理器以响应所述请求。
  3. 根据权利要求2所述的控制方法，其特征在于，所述从所述非易失性存储模块中获取存储有所述程序指令的存储块，将所述存储块添加入所述指令缓存模块中之后，还包括：
    生成与所述程序指令对应的第一地址，作为所述程序指令存在所述指令缓存模块的标识；
    将所述第一地址存储到预设的地址列表中。
  4. 根据权利要求3所述的控制方法，其特征在于，所述判断所述指令缓存模块中是否存在与所述请求对应的程序指令包括：
    获取与所述请求对应的第二地址并检测所述地址列表中是否存在与所述第二地址相同的第一地址；
    若所述地址列表中存在与所述第二地址相同的第一地址，则判定所述指令模块中存在与所述请求对应的程序指令；
    若所述地址列表中不存在与所述第二地址相同的第一地址，则判定 所述指令模块中不存在与所述请求对应的程序指令。
  5. 根据权利要求2所述的控制方法，其特征在于，所述从所述非易失性存储模块中获取存储有所述程序指令的存储块，将所述存储块添加入所述指令缓存模块中还包括：
    计算所述指令缓存模块的剩余容量空间；
    将所述剩余容量空间与存储所述存储块所需的存储空间进行比较；
    若所述剩余容量空间小于所述存储空间，则从所述指令缓存模块中选取一个目标缓存块，将所述目标缓存块清空并将所述程序指令存储到所述目标缓存块中；
    若所述剩余容量空间大于或等于所述存储空间，则将所述存储块添加入所述指令缓存模块中。
  6. 根据权利要求5所述的控制方法，其特征在于，所述从所述指令缓存模块中选取一个目标缓存块包括：
    统计所述指令缓存模块中各所述缓存块的历史访问量；
    将历史访问量最小的所述缓存块确定为所述目标缓存块。
  7. 一种嵌入式控制电路，其特征在于，包括：处理器、非易失性存储模块以及连接所述处理器、所述非易失性存储模块的指令缓存模块，
    所述非易失性存储模块用于存储程序指令，所述指令缓存模块用于缓存所述程序指令，所述处理器用于执行所述程序指令；
    当所述嵌入式控制电路上电时，所述处理器对所述指令缓存模块发送获取程序指令的请求；所述指令缓存模块接收所述请求，并判断所述指令缓存模块中是否存在与所述请求对应的程序指令，若存在，则将所述程序指令发送给所述处理器，若不存在，则从所述非易失性存储模块中获取所述程序指令，将所述程序指令添加入所述指令缓存模块中，并将所述程序指令发送给所述处理器，所述处理器接受并执行所述程序指令。
  8. 一种嵌入式控制电路的控制装置，其特征在于，包括：
    获取模块，用于当所述嵌入式控制电路上电后，获取所述处理器发送的从所述非易失性存储模块获取程序指令的请求；
    判断模块，用于判断所述指令缓存模块中是否存在与所述请求对应的程序指令；
    执行模块，用于若所述指令缓存模块中存在与所述请求对应的程序指令，则将所述程序指令发送给所述处理器以响应所述请求。
  9. 一种嵌入式控制器，其特征在于，包括：如权利要求8所述的嵌入式控制电路的控制装置。
  10. 一种芯片，其特征在于，包括：如权利要求9所述的嵌入式控制器。
PCT/CN2022/120577 2021-12-23 2022-09-22 嵌入式控制电路、控制方法、装置及芯片 WO2023116093A1 (zh)

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