WO2023092538A1 - 移位寄存器及其驱动方法、发光控制驱动器、显示装置 - Google Patents

移位寄存器及其驱动方法、发光控制驱动器、显示装置 Download PDF

Info

Publication number
WO2023092538A1
WO2023092538A1 PCT/CN2021/133900 CN2021133900W WO2023092538A1 WO 2023092538 A1 WO2023092538 A1 WO 2023092538A1 CN 2021133900 W CN2021133900 W CN 2021133900W WO 2023092538 A1 WO2023092538 A1 WO 2023092538A1
Authority
WO
WIPO (PCT)
Prior art keywords
level
node
terminal
shift register
signal
Prior art date
Application number
PCT/CN2021/133900
Other languages
English (en)
French (fr)
Inventor
韩承佑
郑皓亮
刘冬妮
肖丽
赵蛟
崔晓荣
玄明花
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/923,690 priority Critical patent/US20240221608A1/en
Priority to PCT/CN2021/133900 priority patent/WO2023092538A1/zh
Priority to CN202180003696.1A priority patent/CN116868263A/zh
Publication of WO2023092538A1 publication Critical patent/WO2023092538A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present application relates to the field of display technology, in particular to a shift register and a driving method thereof, a light emission control driver for a display device, and a display device.
  • a self-luminous device such as a light-emitting diode (LED)
  • the luminous efficiency of the self-luminous device decreases as the current density decreases, and when the current flowing in the self-luminous device reaches a certain amount or less, brightness occurs
  • PWM pulse width modulation
  • the types of thin film transistors commonly used in small-sized display panels and their manufacturing processes may no longer be suitable, and other types of thin film transistors need to be used.
  • the light emission control driver composed of other types of thin film transistors and the shift register circuit used in the related art there are defects in the light emission control driver composed of other types of thin film transistors and the shift register circuit used in the related art.
  • the present disclosure provides a shift register, including: an input circuit connected to an input signal terminal, a first clock terminal, and a first node, and configured to receive an input signal applied to the input signal terminal, and respond to The first clock signal applied to the first clock terminal transmits the input signal to the first node;
  • the first control circuit is connected to the second clock terminal, the first power supply terminal, the first node and the second node, and is configured to receiving a first power signal applied to a first power terminal, and controlling a voltage at the first node in response to a second clock signal applied to a second clock terminal and a voltage at the second node;
  • a second control circuit connected to the second A clock terminal, a second clock terminal, a first power supply terminal, a second power supply terminal, a first node, a second node and a fifth node, and configured to receive a first power supply signal and a second power supply applied to the second power supply terminal signal to control the voltage at the second node in response to the first clock signal, the second clock signal,
  • the voltage at the first node in response to the input signal being an inactive level and the first clock signal changing from an inactive level to an active level, changes from the second level to the first level, and, in response When the input signal is at an active level and the second clock signal changes from an inactive level to an active level, the voltage at the first node changes from the second level to a third level, the first level is an inactive level, and the second The second level and the third level are active levels, and the first level is smaller than the second level, and the second level is smaller than the third level.
  • the voltage at the second node in response to the input signal being at an inactive level and the second clock signal changing from an inactive level to an active level, changes from a fifth level to a sixth level, and in response When the input signal is at an active level and the first clock signal changes from an active level to an inactive level, the voltage at the second node changes from a fifth level to a fourth level, the fourth level is an inactive level, and the first The fifth level and the sixth level are active levels, and the fourth level is smaller than the fifth level, and the fifth level is smaller than the sixth level.
  • the first control circuit includes: a first control transistor, a second control transistor and a first control capacitor.
  • the control pole of the first control transistor is connected to the second clock terminal, the first pole is connected to the first node, and the second pole is connected to the third node.
  • the control electrode of the second control transistor is connected to the second node, the first electrode is connected to the third node, and the second electrode is connected to the first power supply terminal.
  • the first terminal of the first control capacitor is connected to the second clock terminal, and the second terminal is connected to the first node.
  • the second control circuit includes: a third control transistor, a fourth control transistor, a fifth control transistor, a sixth control transistor and a second control capacitor.
  • the control electrode of the third control transistor is connected to the first node, the first electrode is connected to the first clock terminal, and the second electrode is connected to the second node.
  • the control pole of the fourth control transistor is connected to the first clock terminal, the first pole is connected to the second power supply terminal, and the second pole is connected to the second node.
  • the control pole of the fifth control transistor is connected to the second node, the first pole is connected to the second clock terminal, and the second pole is connected to the fourth node.
  • the control pole of the sixth control transistor is connected to the second clock terminal, the first pole is connected to the fourth node, and the second pole is connected to the fifth node.
  • the first terminal of the second control capacitor is connected to the second node, and the second terminal is connected to the fourth node.
  • the second control circuit further includes: a seventh control transistor and a third control capacitor.
  • the control electrode of the seventh control transistor is connected to the first node, the first electrode is connected to the fifth node, and the second electrode is connected to the first power supply terminal.
  • a first end of the third control capacitor is connected to the fifth node, and a second end is connected to the first power supply end.
  • the output circuit includes: a first output transistor and a second output transistor.
  • the control pole of the first output transistor is connected to the first node, the first pole is connected to the second power supply terminal, and the second pole is connected to the output signal terminal.
  • the control pole of the second output transistor is connected to the fifth node, the first pole is connected to the output signal terminal, and the second pole is connected to the first power supply terminal.
  • the input circuit includes: a first input transistor, the control pole of the first input transistor is connected to the first clock terminal, the first pole is connected to the input signal terminal, and the second pole is connected to the first node.
  • all transistors making up the shift register are oxide thin film transistors.
  • the present disclosure provides a light emission control driver including a multi-stage shift register, each of which is the above-mentioned shift register.
  • the first clock terminal of the odd-numbered shift register in the multi-stage shift register is connected to the first clock signal line, and the second clock terminal is connected to the second clock signal line.
  • the first clock terminal of the even-numbered shift register in the multi-stage shift register is connected to the second clock signal line, and the second clock terminal is connected to the first clock signal line.
  • the clock signal applied to the first clock signal line and the clock signal applied to the second clock signal line have the same frequency and a phase difference of 180°.
  • the input signal terminal of the first-stage shift register in the multi-stage shift register is applied with a transmission start signal, and each of the multi-stage shift registers except the first stage The input signal end of the first-stage shift register is connected to the output signal end of the upper-stage shift register.
  • the present disclosure provides a display device including: a plurality of pixels, each of which is connected to a corresponding gate line among a plurality of gate lines, a corresponding data line among a plurality of data lines, and a corresponding one of a plurality of light emission control lines.
  • a display device including: a plurality of pixels, each of which is connected to a corresponding gate line among a plurality of gate lines, a corresponding data line among a plurality of data lines, and a corresponding one of a plurality of light emission control lines.
  • the output signal end of each stage of the shift register of the light emission control driver is connected to a corresponding one of the plurality of light emission control lines, so as to transmit the output signal from the shift register of this stage to the plurality of light emission control lines Corresponding one of the control lines.
  • the present disclosure provides a driving method of the above-mentioned shift register.
  • the first clock signal and the second clock signal have the same frequency and a phase difference of 180°.
  • the driving method includes: in a first period, applying an input signal with an inactive level to an input signal end of the shift register, providing a first clock signal with an active level and a second clock signal with an inactive level; In the second period, an input signal with an inactive level is applied to the input signal end of the shift register, and a first clock signal with an inactive level and a second clock signal with an active level are provided; in the third period, the input signal to the shift register An input signal with an inactive level is applied to the input signal end of the shift register to provide a first clock signal with an active level and a second clock signal with an inactive level; level input signal, providing a first clock signal with an inactive level and a second clock signal with an active level; in the fifth period, applying an input signal with an inactive level to the input signal terminal of the shift register, providing A first clock
  • the voltage at the first node changes from the second level to the first level as the first clock signal changes from an inactive level to an active level
  • the voltage at the first node changes from the second level to the third level
  • the first level is an inactive level
  • the second level and the third level are active levels
  • the first level is smaller than the second level
  • the second level is smaller than the third level
  • the voltage at the second node changes from a fifth level to a sixth level
  • the voltage at the second node changes from the fifth level to the fourth level, which is the inactive level level, the fifth level and the sixth level are active levels, and the fourth level is less than the fifth level, and the fifth level is less than the sixth level.
  • Figure 1 is a block diagram of a shift register according to some embodiments of the present disclosure
  • FIG. 2 is a circuit diagram of a shift register according to some embodiments of the present disclosure.
  • FIG. 3 is a timing diagram illustrating the operation of a shift register according to some embodiments of the present disclosure
  • 4A to 4J are diagrams illustrating working states of the shift register shown in FIG. 2 in various periods
  • FIG. 5 is a block diagram of a lighting control driver according to some embodiments of the present disclosure.
  • FIG. 6 is a block diagram of a display device according to some embodiments of the present disclosure.
  • 7A to 7C are respectively a block diagram, a circuit diagram and a timing diagram of a pixel of a display device.
  • FIG. 8 is a block diagram and a timing diagram showing an apparatus of a light emission control driver in the related art.
  • active level refers to a voltage capable of controlling the corresponding transistor to be turned on
  • active level refers to a voltage capable of controlling the corresponding transistor to be turned off.
  • the on level and active level may refer to high level
  • the off level and inactive level may refer to low level.
  • control electrode refers to the gate of the transistor, one of the first electrode and the second electrode is the source of the transistor, and the other is the drain of the transistor.
  • the off-level of a transistor refers to a level at which, when applied to the gate of the transistor, the transistor is turned off.
  • a pulse width modulation (Pulse Width Modulation, PWM) signal to control the light-emitting time of the self-luminous device to achieve grayscale display.
  • PWM pulse width modulation
  • a light emission control driver can be formed by cascading multiple shift registers, so as to transmit light emission control signals row by row to the self-luminous devices arranged in multiple rows.
  • the shift register can be composed of several thin film transistors.
  • the size of the display panel increases, it is difficult to manufacture thin film transistors such as LTPS transistors on large-sized substrates due to the limitation of the uniformity and reliability of the process. . Therefore, it is an industry trend to use N-type thin film transistors, especially N-type oxide thin film transistors, in large-size display panels.
  • the pulse width of the output light-emitting control signal cannot be determined by the pulse width of the initial input signal.
  • the shift register of each stage of EOA can be implemented by adding an inverter on the basis of any stage of shift register circuit architecture of GOA. Specifically, the input end of the inverter is connected to any stage of shift register circuit of GOA In the output end, the output end of the inverter outputs a light emission control signal to provide to the pixel. In this case, the pulse width of the light emission control signal is determined by the pulse width of the clock signal.
  • FIG. 8 shows an example of applying an EOA composed of oxide thin film transistors in the related art and its working timing.
  • the light emitting control terminals EM of pixels Pixel(n) in row n to Pixel(n+3) in row (n+3) are connected to shift registers EOA_(n)O and EOA_( n)E, EOA_(n+1)O, EOA_(n+1)E, the reset terminal Reset and scan control of Pixel(n) in row n to Pixel(n+3) in row (n+3)
  • Terminal Gate is connected to the shift registers GOA_(n-1) to GOA_(n+2) and GOA_last of the corresponding stages of GOA.
  • the output pulse width of the shift registers of the oxide thin film transistor EOA in the related art is determined by the clock pulse width, when the pixel is initialized, the output signal of the EOA needs to be kept at a cut-off level, therefore, the entire EOA needs Four clock signals ECK1, ECK2, ECK3, ECK4.
  • the present disclosure particularly provides a shift register and its driving method, a light emission control driver for a display device, and a display device, which substantially eliminate one of the problems caused by technical limitations and deficiencies in the related art or more.
  • the present disclosure provides a shift register, which includes an input circuit, a first control circuit, a second control circuit, and an output circuit, wherein all transistors constituting the shift register are N-type transistors, and the shift register
  • the duration of the period of the inactive level of the output signal of the bit register depends on the duration of the period of the inactive level of the input signal of the shift register, and the inactive level is a level capable of turning off the N-type transistor.
  • FIG. 1 shows a block diagram of a shift register according to an embodiment of the disclosure.
  • the shift register may include an input circuit 1 , a first control circuit 2 , a second control circuit 3 and an output circuit 4 .
  • the input circuit 1 can be connected to the input signal terminal INPUT, the first clock terminal CK and the first node NODE1, and is configured to receive the input signal applied to the input signal terminal INPUT, and respond to the first clock terminal applied to the first A clock signal is used to transmit the input signal to the first node.
  • the first control circuit 2 can be connected to the second clock terminal CKB, the first power supply terminal VGL, the first node NODE1 and the second node NODE2, and is configured to receive the first power supply signal applied to the first power supply terminal VGL, and respond The voltage at the first node NODE1 is controlled based on the second clock signal applied to the second clock terminal CKB and the voltage at the second node NODE2.
  • the second control circuit 3 may be connected to the first clock terminal CK, the second clock terminal CKB, the first power supply terminal VGL, the second power supply terminal VGH, the first node NODE1, the second node NODE2 and the fifth node NODE5, and configured controlling the voltage at the second node NODE2 in response to the first clock signal, the second clock signal and the voltage at the first node NODE1 for receiving the first power supply signal and the second power supply signal applied to the second power supply terminal VGH, and The voltage at the fifth node NODE5 is controlled in response to the second clock signal and the voltage at the first node NODE1.
  • the output circuit 4 can be connected to the first node NODE1, the fifth node NODE5, the first power supply terminal VGL, the second power supply terminal VGH and the output signal terminal OUT, and is configured to respond to the active level at the first node NODE1 to output
  • the second power signal is transmitted to the output signal terminal OUT
  • the first power signal is transmitted to the output signal terminal OUT in response to the active level at the fifth node NODE5.
  • the first power signal provided by the first power terminal VGL may have a constant inactive level
  • the second power signal provided by the second power terminal VGH may have a constant inactive level
  • the duration of a period having an inactive level of the output signal output from the output signal terminal OUT depends on the input applied to the input signal terminal INPUT.
  • the duration of a period of a signal with an inactive level may be substantially equal to the duration of the period of the input signal applied to the input signal terminal INPUT having an inactive level. Therefore, the number of control signals of the shift register can be reduced, and the connection and wiring of the shift register can be simplified.
  • all transistors constituting the shift register may be N-type transistors.
  • all transistors are N-type oxide thin film transistors. Therefore, the shift register can be applied to large-sized display panels.
  • the active level is a high level
  • the inactive level is a low level
  • the first power signal is a power signal with a constant low level
  • the second power signal is a power signal with a constant high level.
  • the voltage at the first node NODE1 when the input signal is at an inactive level and the first clock signal changes from an inactive level to an active level, the voltage at the first node NODE1 can change from the second level to is the first level, and when the input signal is an active level and the second clock signal changes from an inactive level to an active level, the voltage at the first node NODE1 can change from the second level to the third level, wherein, the first level is an inactive level, the second level and the third level are active levels, and the first level is smaller than the second level, and the second level is smaller than the third level.
  • the third level may be a higher level than the high level of the second power signal.
  • the voltage at the second node NODE2 when the input signal is at an inactive level and the second clock signal changes from an inactive level to an active level, the voltage at the second node NODE2 can change from the fifth level to is the sixth level, and when the input signal is an active level and the first clock signal changes from an active level to an inactive level, the voltage at the second node NODE2 can change from the fifth level to the fourth level, wherein, the fourth level is an inactive level, the fifth level and the sixth level are active levels, and the fourth level is smaller than the fifth level, and the fifth level is smaller than the sixth level.
  • the sixth level may be a higher level than the high level of the second power signal.
  • the pulse width of the output signal at the output signal terminal OUT can be adjusted according to the pulse width of the input signal. Therefore, the number of control signals of the shift register can be reduced, and the connection and wiring of the shift register can be simplified.
  • FIG. 2 shows a circuit diagram of a shift register according to some embodiments of the present disclosure.
  • the input circuit 1 may include a first input transistor M1.
  • the control electrode of the first input transistor M1 is connected to the first clock terminal CK, the first electrode is connected to the input signal terminal INPUT, and the second electrode is connected to the first node NODE1.
  • the first control circuit 2 may include a first control transistor M3 , a second control transistor M4 and a first control capacitor C3 .
  • the control electrode of the first control transistor M3 is connected to the second clock terminal CKB, the first electrode is connected to the first node NODE1, and the second electrode is connected to the third node NODE3.
  • the control electrode of the second control transistor M4 is connected to the second node NODE2, the first electrode is connected to the third node NODE3, and the second electrode is connected to the first power supply terminal VGL.
  • a first terminal of the first control capacitor C3 is connected to the second clock terminal CKB, and a second terminal is connected to the first node NODE1.
  • the second control circuit 3 may include a third control transistor M2 , a fourth control transistor M5 , a fifth control transistor M6 , a sixth control transistor M7 and a second control capacitor C1 .
  • the control electrode of the third control transistor M2 is connected to the first node NODE1, the first electrode is connected to the first clock terminal CK, and the second electrode is connected to the second node NODE2.
  • the control electrode of the fourth control transistor M5 is connected to the first clock terminal CK, the first electrode is connected to the second power supply terminal VGH, and the second electrode is connected to the second node NODE2.
  • the control electrode of the fifth control transistor M6 is connected to the second node NODE2, the first electrode is connected to the second clock terminal CKB, and the second electrode is connected to the fourth node NODE4.
  • the control electrode of the sixth control transistor M7 is connected to the second clock terminal CKB, the first electrode is connected to the fourth node NODE4, and the second electrode is connected to the fifth node NODE5.
  • a first end of the second control capacitor C1 is connected to the second node NODE2, and a second end is connected to the fourth node NODE4.
  • the second control circuit 3 may further include a seventh control transistor M8 and a third control capacitor C2.
  • the control electrode of the seventh control transistor M8 is connected to the first node NODE1, the first electrode is connected to the fifth node NODE5, and the second electrode is connected to the first power supply terminal VGL.
  • a first terminal of the third control capacitor C2 is connected to the fifth node NODE5, and a second terminal is connected to the first power supply terminal VGL.
  • the output circuit 4 may include a first output transistor M10 and a second output transistor M9 .
  • the control electrode of the first output transistor M10 is connected to the first node NODE1, the first electrode is connected to the second power supply terminal VGH, and the second electrode is connected to the output signal terminal OUT.
  • the control electrode of the second output transistor M9 is connected to the fifth node NODE5 , the first electrode is connected to the output signal terminal OUT, and the second electrode is connected to the first power supply terminal VGL.
  • the first clock signal applied to the first clock terminal CK and the second clock signal applied to the second clock terminal CKB have the same frequency and a phase difference of 180°. Due to the clock signal (including the first clock signal of the first clock terminal CK and the second clock signal applied to the second clock terminal CKB), it is difficult to achieve ideally instantaneous high-low level transitions, that is, the clock signal is switched at low level There is a rising edge time when it reaches a high level, and there is a falling edge time when switching from a high level to a low level; and, in order to avoid interference between different clock signals due to level changes, any two clock signals (such as the first clock terminal The rising edge time and/or falling edge time of the first clock signal of CK and the second clock signal applied to the second clock terminal (CKB) do not overlap.
  • the beginning of the period includes the rising edge time of the first clock signal from low to high, and during the period The end includes the falling edge time of the first clock signal changing from high to low; and for the period when the first clock signal applied to the first clock terminal CK is at low level, the first clock signal exhibits a fixed low level.
  • the beginning of the period includes the rising edge time of the second clock signal from low to high, and the end of the period includes the rising edge time of the second clock signal from low to high.
  • the input signal applied to the input signal terminal INPUT is at a high level.
  • the input signal applied to the signal input terminal INPUT is at low level
  • the first clock signal applied to the first clock terminal CK is at high level
  • the second clock signal applied to the second clock terminal CKB is low level.
  • the input circuit 1 transmits the input signal to the first node NODE1
  • the second control circuit 3 transmits the high-level power signal applied to the second power terminal VGH to the second node NODE2.
  • the first input transistor M1 is turned on, and the first node NODE1 is discharged through the first input transistor M1, so that the level at the first node NODE1 is substantially equal to the level of the input signal at the input terminal INPUT.
  • the same first level, so the first level is a low level.
  • the fourth control transistor M5 is turned on, and the second node NODE2 is charged through the fourth control transistor M5, so that the voltage at the second node NODE2 is charged to a fifth level that is substantially the same as the level of the second power supply signal, and the fifth level Ping is high level.
  • the second control transistor M4 is turned on, and the third node NODE3 is discharged to a low level through the second control transistor M4.
  • the fifth control transistor M6 is turned on, and the level of the second clock signal at the fourth node NODE4 is basically the same as that of the second clock terminal CKB, which is low level. Since both the sixth control transistor M7 and the seventh control transistor M8 are turned off, the fifth node NODE5 is in a floating state and maintains the level before the first period T1, which is a low level.
  • the first output transistor M10 and the second output transistor M9 are turned off due to the low voltages at the first node NODE1 and the fifth node NODE5 , so that the output signal terminal OUT is in a floating state and maintains the level before the first period T1 .
  • the input signal applied to the signal input terminal INPUT is at low level
  • the first clock signal applied to the first clock terminal CK is at low level
  • the second clock signal applied to the second clock terminal CKB is high level.
  • the second control circuit 3 increases the voltage at the second node NODE2 from the fifth level to a sixth level higher than the fifth level, and the first control circuit 2 controls the voltage at the first node NODE1 to is low level.
  • the fifth control transistor M6 is turned on, and the level of the second clock signal at the fourth node NODE4 and the second clock terminal CKB is basically the same, which is a high level.
  • the third control transistor M2 and the fourth control transistor M5 are turned off, the second node NODE2 is in a floating state, and the second control capacitor C1 is further raised from the fifth level to sixth level.
  • the second control transistor M4 and the first control transistor M3 are turned on, and the first node NODE1 is discharged through the second control transistor M4 and the first control transistor M3, so that the voltage at the first node NODE1 remains at a low level, and due to the second control
  • the voltage at the third node NODE3 is substantially the same as the level of the first power supply terminal VGL.
  • the sixth control transistor M7 is turned on, and the high level at the fourth node NODE4 is transmitted to the fifth node NODE5 through the sixth control transistor M7, so that the voltage at the fifth node NODE5 is at a high level.
  • the second output transistor M9 is turned on under the control of the fifth node NODE5, so that the output signal output from the output signal terminal OUT is at a low level.
  • the input signal applied to the signal input terminal INPUT is at low level
  • the first clock signal applied to the first clock terminal CK is at high level
  • the second clock signal applied to the second clock terminal CKB is low level.
  • the second control circuit 3 lowers the voltage at the second node NODE2 from the sixth level to the fifth level, and the input circuit 1 controls the voltage at the first node NODE1 to be at a low level.
  • the first input transistor M1 is turned on, so that the voltage at the first node NODE1 is at a low level that is substantially the same as the level of the input terminal INPUT, the third control transistor M2, the seventh control transistor M2 Transistor M8 and first output transistor M10 are turned off.
  • the fourth control transistor M5 is turned on so that the voltage at the second node NODE2 is the fifth level.
  • the second control transistor M4 is turned on, and the level of the third node NODE3 is basically the same as that of the first power supply terminal VGL, which is a low level.
  • the fifth control transistor M6 is turned on, and the level of the second clock signal at the fourth node NODE4 is basically the same as that of the second clock terminal CKB, which is low level.
  • the sixth control transistor M7 is turned off, and the voltage at the fifth node NODE5 is maintained at a high level due to the third control capacitor C2. Therefore, the second output transistor M9 remains turned on, and the output signal output from the output signal terminal OUT is at a low level.
  • the input signal applied to the signal input terminal INPUT is low level
  • the first clock signal applied to the first clock terminal CK is low level
  • the second clock signal applied to the second clock terminal CKB is high level.
  • the second control circuit 3 increases the voltage at the second node NODE2 from the fifth level to a sixth level higher than the fifth level, and the first control circuit 2 controls the voltage at the first node NODE1 to is low level.
  • the fifth control transistor M6 is turned on, and the level of the second clock signal at the fourth node NODE4 and the second clock terminal CKB is basically the same, which is a high level.
  • the second node NODE2 is in a floating state, and is further raised from the fifth level to the sixth level by the bootstrap effect of the second control capacitor C1.
  • the second control transistor M4 and the first control transistor M3 are turned on, and the first node NODE1 is discharged through the second control transistor M4 and the first control transistor M3, so that the voltage at the first node NODE1 remains at a low level, and due to the second control
  • the voltage at the third node NODE3 is basically the same as the level of the first power supply terminal VGL, which is a low level.
  • the sixth control transistor M7 is turned on, and the level of the fourth node NODE4 is transmitted to the fifth node NODE5 through the sixth control transistor M7, so that the voltage at the fifth node NODE5 is at a high level.
  • the second output transistor M9 is turned on under the control of the high voltage at the fifth node NODE5, so that the output signal output from the output signal terminal OUT is at a low level.
  • the input signal applied to the signal input terminal INPUT is at low level
  • the first clock signal applied to the first clock terminal CK is at high level
  • the second clock signal applied to the second clock terminal CKB is low level.
  • the second control circuit 3 lowers the voltage at the second node NODE2 from the sixth level to the fifth level, and the input circuit 1 controls the voltage at the first node NODE1 to be at a low level.
  • the first input transistor M1 is turned on, so that the voltage at the first node NODE1 remains low, and the third control transistor M2, the seventh control transistor M8 and the first output transistor M10 are turned off.
  • the fourth control transistor M5 is turned on so that the voltage at the second node NODE2 is the fifth level.
  • the second control transistor M4 is turned on, and the level of the third node NODE3 is basically the same as that of the first power supply terminal VGL, which is a low level.
  • the fifth control transistor M6 is turned on, and the level of the second clock signal at the fourth node NODE4 is basically the same as that of the second clock terminal CKB, which is low level.
  • the sixth control transistor M7 is turned off, and the voltage at the fifth node NODE5 is maintained at a high level due to the third control capacitor C2. Therefore, the second output transistor M9 remains turned on, and the output signal output from the output signal terminal OUT is at a low level.
  • the input signal applied to the signal input terminal INPUT is at a high level
  • the first clock signal applied to the first clock terminal CK is at a low level
  • the second clock signal applied to the second clock terminal CKB is high level.
  • the second control circuit 3 increases the voltage at the second node NODE2 from the fifth level to a sixth level higher than the fifth level, and the first control circuit 2 controls the voltage at the first node NODE1 to is low level.
  • the fifth control transistor M6 is turned on, and the level of the second clock signal at the fourth node NODE4 and the second clock terminal CKB is basically the same, which is a high level.
  • the second node NODE2 is in a floating state, and is further raised from the fifth level to the sixth level by the bootstrap effect of the second control capacitor C1.
  • the second control transistor M4 and the first control transistor M3 are turned on, and the first node NODE1 is discharged through the second control transistor M4 and the first control transistor M3, so that the voltage at the first node NODE1 remains at a low level, and the third node NODE3 The voltage at is also kept low.
  • the sixth control transistor M7 is turned on, and the high level at the fourth node NODE4 is transmitted to the fifth node NODE5 through the sixth control transistor M7, so that the voltage at the fifth node NODE5 is at a high level.
  • the second output transistor M9 is turned on under the control of the high voltage at the fifth node NODE5, thereby outputting a low level from the output signal terminal OUT.
  • the input signal applied to the signal input terminal INPUT is at a high level
  • the first clock signal applied to the first clock terminal CK is at a high level
  • the second clock signal applied to the second clock terminal CKB is low level.
  • the input circuit 1 transmits the input signal to the first node NODE1
  • the second control circuit 3 lowers the voltage at the second node NODE2 from the sixth level to the fifth level.
  • the first input transistor M1 is turned on, the first node NODE1 has a second level that is substantially the same as the level of the input signal at the input terminal INPUT, and the second level is a high level.
  • the third control transistor M2, the seventh control transistor M8 and the first output transistor M10 are turned on.
  • the fourth control transistor M5 is turned on, so that the voltage at the second node NODE2 is substantially the same as the high-level power signal of the second power supply terminal VGH, and the second control transistor M4 and the fifth control transistor M6 are turned on.
  • the third node NODE3 is discharged through the second control transistor M4, so that the voltage at the third node NODE3 maintains a low level.
  • the fourth node NODE4 is discharged through the fifth control transistor M6, so that the voltage at the fourth node NODE4 is at a low level.
  • the fifth node NODE5 is discharged through the seventh control transistor M8, so that the voltage at the fifth node NODE5 is at a low level.
  • the second node NODE2 is discharged through the third control transistor M2, so that the voltage at the second node NODE2 drops from the fifth level to a fourth level that is substantially the same as the level of the second clock signal at the second clock terminal CKB, and the fourth level is a low level.
  • the second output transistor M9 is turned off, and the first output transistor M10 is turned on, so that the output signal output from the output signal terminal OUT is at a high level.
  • the input signal applied to the signal input terminal INPUT is at a high level
  • the first clock signal applied to the first clock terminal CK is at a low level
  • the second clock signal applied to the second clock terminal CKB is high level.
  • the first control circuit 2 controls the voltage at the first node NODE1 to a third level
  • the second control circuit 3 controls the voltage at the second node NODE2 to a low level.
  • the second control transistor M4 and the fifth control transistor M6 are turned off. Since the first input transistor M1 is also turned off, the first node NODE1 is in a floating state, and the second clock signal applied to the second clock terminal CKB is at a high level, so the voltage at the first node NODE1 is due to the first control The bootstrap effect of the capacitor C3 is further increased from the second level to the third level.
  • the third control transistor M2, the first control transistor M3, the seventh control transistor M8, and the first output transistor M10 are turned on.
  • the third node NODE3 is charged through the first control transistor M3, so that the voltage at the third node NODE3 becomes a high level.
  • the voltage at the fifth node NODE5 maintains a low level due to the turn-on of the seventh control transistor M8, so that the second output transistor M9 is turned off.
  • a high level is output from the output signal terminal OUT. Since the voltage at the first node NODE1 is at the third level higher than the second level, the level of the output signal in the eighth period T8 is slightly higher than that in the seventh period T7.
  • the input signal applied to the signal input terminal INPUT is at a high level
  • the first clock signal applied to the first clock terminal CK is at a high level
  • the second clock signal applied to the second clock terminal CKB is low level.
  • the input circuit 1 transmits the input signal to the first node NODE1, and the second control circuit 3 controls the voltage at the second node NODE2 to the fifth level.
  • the first input transistor M1 is turned on, and the first node NODE1 is charged through the first input transistor M1, so that the voltage at the first node NODE1 is substantially the same as the level of the input signal at the input terminal INPUT , is high level.
  • the third control transistor M2, the seventh control transistor M8 and the first output transistor M10 are turned on.
  • the fourth control transistor M5 is turned on, so that the voltage at the second node NODE2 is a fifth level that is substantially the same as the high-level power signal of the second power supply terminal VGH, and the second control transistor M4 and the fifth control transistor M6 are turned on. Pass.
  • the third node NODE3 is discharged through the second control transistor M4, so that the voltage at the third node NODE3 maintains a low level.
  • the fourth node NODE4 is discharged through the fifth control transistor M6, so that the voltage at the fourth node NODE4 is at a low level.
  • the fifth node NODE5 is discharged through the seventh control transistor M8, so that the voltage at the fifth node NODE5 is at a low level.
  • the ninth period T9 when the first clock signal changes from high level to low level, the second node NODE2 is discharged through the third control transistor M2, so that the voltage at the second node NODE2 drops from the fifth level to low level.
  • the eighth period T7 the second output transistor M9 is turned off, and the first output transistor M10 is turned on, so that the output signal output from the output signal terminal OUT is at a high level.
  • the input signal applied to the signal input terminal INPUT is at a high level
  • the first clock signal applied to the first clock terminal CK is at a high level
  • the second clock signal applied to the second clock terminal CKB is low level.
  • the first control circuit 2 controls the voltage at the first node NODE1 to a third level
  • the second control circuit 3 controls the voltage at the second node NODE2 to a low level.
  • the second control transistor M4 and the fifth control transistor M6 are turned off. Since the first input transistor M1 is also turned off, the first node NODE1 is in a floating state, and the second clock terminal CKB is applied with a high-level clock signal, so the voltage at the first node NODE1 is due to the first control capacitor C3 The bootstrap effect becomes high to the third level.
  • the third control transistor M2, the first control transistor M3, the seventh control transistor M8, and the first output transistor M10 are turned on.
  • the second node NODE2 is discharged through the third control transistor M2, so that the voltage at the second node NODE2 becomes substantially the same low level as the first clock signal.
  • the third node NODE3 is charged through the first control transistor M3, so that the voltage at the third node NODE3 becomes a high level.
  • the voltage at the fifth node NODE5 maintains a low level due to the turn-on of the seventh control transistor M8, so that the second output transistor M9 is turned off.
  • the output signal output from the output signal terminal OUT is high level.
  • the input signal applied to the input signal terminal INPUT maintains a high level, and the first clock signal and the second clock signal continue to maintain the original frequency for switching between high and low levels until in response to a change in the input signal (for example, the input signal changes from high level to low level) and proceed to the next first period T1.
  • the second level and the fifth level may be the same or different, which is not limited in the present disclosure, as long as both the second level and the fifth level are effective levels.
  • the first level and the fourth level may be the same or different, which is not limited in the present disclosure, as long as the first level and the fourth level are both inactive levels.
  • all transistors constituting the shift register may be N-type transistors (for example, oxide thin film transistors whose conductivity type is N-type). Therefore, the shift register can be applied to large-sized display panels.
  • the pulse width of the output signal at the output signal terminal OUT can be adjusted according to the pulse width of the input signal. Therefore, the number of control signals of the shift register can be reduced, and the connection and wiring of the shift register can be simplified.
  • the present disclosure provides a light emission control driver, including a plurality of cascaded shift registers, where the shift registers are the above-mentioned shift registers.
  • the light emission control driver includes N cascaded shift registers (hereinafter referred to as N-stage shift registers).
  • the signal input end of the first-stage shift register is applied with a scan start signal EM_STV, and the signal input end of the i-th stage shift register is connected to the signal output end of the i-1-th stage shift register (2 ⁇ i ⁇ N) , and the shift registers of each stage output the signals EM_OUT ⁇ 1> to EM_OUT ⁇ N> of the stage respectively.
  • each stage of the shift register outputs light emission control signals for corresponding pixel rows.
  • the first clock terminal CK and the second clock terminal CKB of the shift registers of each stage are alternately connected to the first clock signal line EM_CK and the second clock signal line EM_CKB respectively.
  • the first clock terminal CK of the odd-numbered shift register is connected to the first clock signal line EM_CK
  • the second clock terminal CKB is connected to the second clock signal line EM_CKB
  • the first clock terminal of the even-numbered shift register CK is connected to the second clock signal line EM_CKB
  • the second clock terminal CKB is connected to the first clock signal line EM_CK.
  • the clock signal applied to the first clock signal line EM_CK and the clock signal EM_CKB applied to the second clock signal line have the same frequency and a phase difference of 180°.
  • all the transistors constituting the light emission controller can be N-type transistors (for example, oxide thin film transistors whose conductivity type is N-type), so the light emission controller can be applied to large-sized display panel.
  • the pulse width of the output signal of the output signal terminal OUT of the shift register at each level is adjusted according to the pulse width of the input signal, the output of the shift register at each level can be directly determined by setting the pulse width of the scan start signal EM_STV.
  • the pulse width of the light-emitting control signal without more complicated clock design and additional initialization control signal. Therefore, the number of control signals can be reduced, the connection and wiring can be simplified, and it is more conducive to the design of narrow-edge/borderless display panels.
  • the present disclosure provides a display device including the above light emission control driver.
  • FIG. 6 illustrates a display device according to some embodiments of the present disclosure.
  • the display device includes a plurality of pixels PX and a light emission control driver according to an embodiment of the present disclosure.
  • Multiple pixels PX are arranged in multiple rows and multiple columns.
  • a plurality of pixels PX are arranged in n rows and m columns, and each row of pixels PX is connected to a corresponding one of a plurality of gate lines G1 to Gn and a corresponding one of a plurality of light emission control lines E1 to En, and each column of pixels PX is connected to a corresponding one of the plurality of data lines D1 to Dm.
  • the output signal terminal of each stage of the shift register of the light emission control driver is connected to a corresponding one of the light emission control lines E1 to En, so as to transmit the corresponding light emission control signal (refer to EM_OUT ⁇ 1> to EM_OUT ⁇ N> in FIG. 5 ) to the light emission control lines E1 to En.
  • the display device may further include a gate driver and a data driver which provide scan signals and data signals to the gate lines G1 to Gn and the data lines D1 to Dm, respectively.
  • FIG. 7A is an exemplary block diagram of the pixel PX
  • FIG. 7B is an exemplary circuit diagram of the pixel PX
  • FIG. 7C is a timing diagram schematically showing the operation of the pixel PX.
  • the pixel PX may include a pixel driving circuit 100 and a light emitting device L
  • the pixel driving circuit 100 may include a driving subcircuit 10 , a writing subcircuit 20 and a grayscale control subcircuit 30 .
  • the pixel driving circuit 100 is connected to a scanning control terminal Gate for connecting to gate lines, a data signal terminal Data for connecting to data lines, and an emission control terminal EM for connecting to emission control lines.
  • the light emission control driver can be used to provide the light emission control signal to the light emission control terminal EM.
  • the gray scale control sub-circuit 30 is turned on, so that the light emission current can flow to the light emitting device L .
  • the data signal provided by the data driver through the data line is applied to the source of the transistor T5, and the scan signal provided by the gate driver through the gate line is applied to the gate of the transistor T5. pole.
  • the light emission control signal provided by the light emission controller through the light emission control line is applied to the gate of the transistor T2 to control the transmission path of the light emission current to the light emitting device L.
  • the driving transistor Td supplies a light emitting current corresponding to the data signal.
  • the light-emitting control signal applied to the light-emitting control terminal EM is at a low level, the transistor T2 is turned on, and the light-emitting current flows to the light-emitting device L to make it emit light.
  • FIGS. 7A to 7C are only examples of pixels PX shown to help explain the control function of the light emission control signal provided by the light emission control driver in the pixel PX, and the circuit structure and working process of the pixel PX are not limited to this.
  • a display device may be a micro LED display device.
  • the display device can be any product or component with a display function such as a monitor, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a monitor, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the present disclosure provides a driving method of the above-mentioned shift register.
  • the method includes: in a first period, applying an input signal with an inactive level to an input signal terminal of the shift register, providing a first clock signal with an active level and a second clock signal with an inactive level; During the period, an input signal with an inactive level is applied to the input signal terminal of the shift register, and a first clock signal with an inactive level and a second clock signal with an active level are provided; An input signal with an inactive level is applied to the input signal end to provide a first clock signal with an active level and a second clock signal with an inactive level; A flat input signal, providing a first clock signal with an inactive level and a second clock signal with an active level; in the fifth period, applying an input signal with an inactive level to the input signal end of the shift register, providing an input signal with an inactive level A first clock signal with an active level and a second clock signal with an inactive level; in the sixth period, an input signal with an active level is applied
  • the above-mentioned first to eighth periods are the periods T1 to T8 shown in FIG. 3
  • the first clock signal is the signal CK shown in FIG. 3
  • the second clock signal is the signal CKB shown in FIG.
  • the input signal is the signal INPUT shown in FIG. 3
  • the signal output from the output end of the shift register is the signal OUT shown in FIG. 3 .
  • the voltage at the first node NODE1 changes from the second level to is the first level
  • the voltage at the first node NODE1 changes from the second level to a higher level the third level
  • the voltage at the second node NODE2 changes from the fifth level to is a higher sixth level
  • the voltage at the second node NODE2 changes from the fifth level to fourth level
  • the above shift register driving method of the present disclosure it is possible to control the period of the output signal output from the output signal terminal OUT having the inactive level by setting the duration of the period of the input signal having the inactive level applied to the input signal terminal INPUT duration. Therefore, the number of control signals of the shift register can be reduced, and the connection and wiring of the shift register can be simplified.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)

Abstract

提供了移位寄存器及其驱动方法、发光控制驱动器、显示装置。移位寄存器包括：输入电路(1)，配置为接收输入信号；第一控制电路(2)，配置为响应于第二时钟信号(CKB)和第二节点(NODE2)的电压而控制第一节点(NODE1)的电压；第二控制电路(3)，配置为响应于第一时钟信号(CK)、第二时钟信号(CKB)和第一节点(NODE1)的电压而控制第二节点(NODE2)的电压，响应于第二时钟信号(CKB)和第一节点(NODE1)的电压而控制第五节点(NODE5)的电压；输出电路(4)，配置为响应于第一节点(NODE1)的有效电平而将第二电源信号(VGH)传输至输出信号端(OUT)，响应于第五节点(NODE5)的有效电平而将第一电源信号(VGL)传输至输出信号端(OUT)。从输出信号端(OUT)输出的输出信号的具有无效电平的时段的时长取决于输入信号的具有无效电平的时段的时长。构成移位寄存器的所有晶体管为N型晶体管。

Description

移位寄存器及其驱动方法、发光控制驱动器、显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种移位寄存器及其驱动方法、用于显示装置的发光控制驱动器、显示装置。
背景技术
在使用诸如发光二极管(LED)的自发光器件的显示面板中，自发光器件的发光效率会随着电流密度降低而降低，当自发光器件中流过的电流达到一定量以下时，就会发生亮度不均匀的现象，从而影响显示面板在低灰阶时的显示效果。因此，需要使用脉宽调制(Pulse Width Modulation，PWM)信号控制发光时间，来实现低灰阶显示。
随着显示面板尺寸的增大，在小尺寸显示面板中普遍采用的薄膜晶体管的类型及其制程可能不再适用，而是需要采用其他类型的薄膜晶体管。但是，相关技术中的由其他类型的薄膜晶体管构成的发光控制驱动器及其所采用的移位寄存器电路存在缺陷。
发明内容
在一方面，本公开提供一种移位寄存器，包括：输入电路，其连接至输入信号端、第一时钟端和第一节点，并被配置为接收施加至输入信号端的输入信号，并响应于施加至第一时钟端的第一时钟信号而将输入信号传至第一节点；第一控制电路，其连接至第二时钟端、第一电源端、第一节点和第二节点，并被配置为接收施加至第一电源端的第一电源信号，并且响应于施加至第二时钟端的第二时钟信号和第二节点处的电压而控制第一节点处的电压；第二控制电路，其连接至第一时钟端、第二时钟端、第一电源端、第二电源端、第一节点、第二节点和第五节点，并被配置为接收第一电源信号和施加至第二电源端的第 二电源信号，响应于第一时钟信号、第二时钟信号和第一节点处的电压而控制第二节点处的电压，并且响应于第二时钟信号和第一节点处的电压而控制第五节点处的电压；输出电路，其连接至第一节点、第五节点、第一电源端、第二电源端和输出信号端，并被配置为响应于第一节点处的有效电平而将第二电源信号传输至输出信号端，并且响应于第五节点处的有效电平而将第一电源信号传输至输出信号端。从输出信号端输出的输出信号的具有无效电平的时段的时长取决于施加至输入信号端的输入信号的具有无效电平的时段的时长。构成移位寄存器的所有晶体管为N型晶体管。
在一些实施例中，响应于输入信号为无效电平且第一时钟信号从无效电平变为有效电平，第一节点处的电压从第二电平变为第一电平，并且，响应于输入信号为有效电平且第二时钟信号从无效电平变为有效电平，第一节点处的电压从第二电平变为第三电平，第一电平是无效电平，第二电平和第三电平是有效电平，并且第一电平小于第二电平，第二电平小于第三电平。
在一些实施例中，响应于输入信号为无效电平且第二时钟信号从无效电平变为有效电平，第二节点处的电压从第五电平变为第六电平，并且，响应于输入信号为有效电平且第一时钟信号从有效电平变为无效电平，第二节点处的电压从第五电平变为第四电平，第四电平是无效电平，第五电平和第六电平是有效电平，并且第四电平小于第五电平，第五电平小于第六电平。
在一些实施例中，第一控制电路包括：第一控制晶体管、第二控制晶体管和第一控制电容。第一控制晶体管的控制极连接至第二时钟端，第一极连接至第一节点，第二极连接至第三节点。第二控制晶体管的控制极连接至第二节点，第一极连接至第三节点，第二极连接至第一电源端。第一控制电容的第一端连接至第二时钟端，第二端连接至第一节点。
在一些实施例中，第二控制电路包括：第三控制晶体管、第四控制晶体管、第五控制晶体管、第六控制晶体管和第二控制电容。第三控制晶体管的控制极连接至第一节点，第一极连接至第一时钟端，第二极连接至第二节点。第四控制晶体管的控制极连接至第一时钟端，第一极连接至第二电源端，第二极连接 至第二节点。第五控制晶体管的控制极连接至第二节点，第一极连接至第二时钟端，第二极连接至第四节点。第六控制晶体管的控制极连接至第二时钟端，第一极连接至第四节点，第二极连接至第五节点。第二控制电容的第一端连接至第二节点，第二端连接至第四节点。
在一些实施例中，第二控制电路还包括：第七控制晶体管和第三控制电容。第七控制晶体管的控制极连接至第一节点，第一极连接至第五节点，第二极连接至第一电源端。第三控制电容的第一端连接至第五节点，第二端连接至第一电源端。
在一些实施例中，输出电路包括：第一输出晶体管和第二输出晶体管。第一输出晶体管的控制极连接至第一节点，第一极连接至第二电源端，第二极连接至输出信号端。第二输出晶体管的控制极连接至第五节点，第一极连接至输出信号端，第二极连接至第一电源端。
在一些实施例中，输入电路包括：第一输入晶体管，第一输入晶体管的控制极连接至第一时钟端，第一极连接至输入信号端，第二极连接至第一节点。
在一些实施例中，构成移位寄存器的所有晶体管为氧化物薄膜晶体管。
在另一方面，本公开提供一种发光控制驱动器，包括多级移位寄存器，每个移位寄存器为上述移位寄存器。
在一些实施例中，所述多级移位寄存器中的奇数级移位寄存器的第一时钟端连接至第一时钟信号线，第二时钟端连接至第二时钟信号线。所述多级移位寄存器中的偶数级移位寄存器的第一时钟端连接至第二时钟信号线，第二时钟端连接至第一时钟信号线。施加至第一时钟信号线的时钟信号与施加至第二时钟信号线的时钟信号具有相同的频率以及相差180°的相位。
在一些实施例中，所述多级移位寄存器中的第一级移位寄存器的输入信号端被施加有发射起始信号，所述多级移位寄存器中的除第一级之外的每一级移位寄存器的输入信号端连接至上一级移位寄存器的输出信号端。
在另一方面，本公开提供一种显示装置，包括：多个像素，每个像素连接至多条栅线中的相应栅线、多条数据线中的相应数据线、多条发光控制线中的 相应发光控制线；以及上述发光控制驱动器，发光控制驱动器的每级移位寄存器的输出信号端连接至多条发光控制线中的相应一条，以将从该级移位寄存器的输出信号传输至多条发光控制线中的相应一条。
在另一方面，本公开提供一种上述移位寄存器的驱动方法。第一时钟信号和第二时钟信号具有相同的频率以及相差180°的相位。该驱动方法包括：在第一时段，向移位寄存器的输入信号端施加具有无效电平的输入信号，提供具有有效电平的第一时钟信号和具有无效电平的第二时钟信号；在第二时段，向移位寄存器的输入信号端施加具有无效电平的输入信号，提供具有无效电平的第一时钟信号和具有有效电平的第二时钟信号；在第三时段，向移位寄存器的输入信号端施加具有无效电平的输入信号，提供具有有效电平的第一时钟信号和具有无效电平的第二时钟信号；在第四时段，向移位寄存器的输入信号端施加具有无效电平的输入信号，提供具有无效电平的第一时钟信号和具有有效电平的第二时钟信号；在第五时段，向移位寄存器的输入信号端施加具有无效电平的输入信号，提供具有有效电平的第一时钟信号和具有无效电平的第二时钟信号；在第六时段，向移位寄存器的输入信号端施加具有有效电平的输入信号，提供具有无效电平的第一时钟信号和具有有效电平的第二时钟信号；在第七时段，向移位寄存器的输入信号端施加具有有效电平的输入信号，提供具有有效电平的第一时钟信号和具有无效电平的第二时钟信号；以及在第八时段，向移位寄存器的输入信号端施加具有有效电平的输入信号，提供具有无效电平的第一时钟信号和具有有效电平的第二时钟信号。第一时段至第八时段是在时间上顺序的时段，并且在紧挨第一时段在前的时段中，输入信号具有有效电平。
在一些实施例中，在第一时段的起始处，随着第一时钟信号从无效电平变为有效电平，第一节点处的电压从第二电平变为第一电平，并且，在第八时段的起始处，随着第二时钟信号从无效电平变为有效电平，第一节点处的电压从第二电平变为第三电平，第一电平是无效电平，第二电平和第三电平是有效电平，并且第一电平小于第二电平，第二电平小于第三电平。
在一些实施例中，在第二时段的起始处，随着第二时钟信号从无效电平变为有效电平，第二节点处的电压从第五电平变为第六电平，并且，在第七时段的结尾处，随着第一时钟信号从有效电平变为无效电平，第二节点处的电压从第五电平变为第四电平，第四电平是无效电平，第五电平和第六电平是有效电平，并且第四电平小于第五电平，第五电平小于第六电平。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的实施例一起用于解释本公开，但并不构成对本公开的限制。
图1是根据本公开一些实施例的移位寄存器的框图；
图2是根据本公开一些实施例的移位寄存器的电路图；
图3是示出根据本公开一些实施例的移位寄存器的操作的时序图；
图4A至图4J是示出图2所示的移位寄存器在各时段中的工作状态的示图；
图5是根据本公开一些实施例的发光控制驱动器的框图；
图6是根据本公开一些实施例的显示装置的框图；
图7A至图7C分别是显示装置的像素的框图、电路图和时序图；以及
图8是示出相关技术中发光控制驱动器的装置的框图和时序图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
在本文中，“有效电平”是指能够控制相应晶体管导通的电压，“无效电平”是指能够控制相应晶体管关断的电压。例如，当晶体管为N型晶体管时，导通电平、有效电平可以指高电平，截止电平、无效电平可以指低电平。
在本文中，对于晶体管元件来说，控制极是指该晶体管的栅极，第一极和第二极中的一者为该晶体管的源极，另一者为该晶体管的漏极。
在本文中，当元件被称为“连接”或“耦接”到另一元件时，它可以直接连接或耦接到另一元件，或者可以存在中间元件。
在本文中，晶体管的截止电平是指这样的电平，当该电平施加至该晶体管的栅极时，该晶体管被关断。
在使用自发光器件作为像素的显示面板中，通常需要使用脉宽调制(Pulse Width Modulation，PWM)信号控制自发光器件的发光时间，来实现灰阶显示。此时，除了一般显示面板中用于向各行像素提供扫描信号的栅极驱动器(GOA)以及用于向各列像素提供数据信号的数据驱动器之外，还需要控制各行像素发光的发光控制驱动器(EOA)。发光控制驱动器可以由多个移位寄存器级联而成，以将针对排布在多行的自发光器件逐行传递发光控制信号。
通常，移位寄存器可由数个薄膜晶体管组成，随着显示面板尺寸的增大，因为受限于其工艺制程的均一性和可靠度，难以在大尺寸基板上制备诸如LTPS晶体管之类的薄膜晶体管。因此在大尺寸显示面板中，采用N型薄膜晶体管，特别是导电类型为N型的氧化物薄膜晶体管是产业的趋势。
发明人发现，在相关技术的采用氧化物薄膜晶体管构成的EOA及采用其所构成的移位寄存器电路中，无法由初始输入信号的脉宽决定所输出的发光控制信号的脉宽。通常，EOA的每级移位寄存器，可以在GOA的任一级移位寄存器电路架构的基础上增加反相器实现，具体地，反相器的输入端连接GOA的任一级移位寄存器电路中的输出端，反相器的输出端输出发光控制信号，以提供给像素。这种情况下，发光控制信号的脉宽由时钟信号的脉宽决定。当对像素进行初始化时，需要将EOA的每级移位寄存器的输出信号在较长时间(例如，两个时钟周期以上)保持为关断(Off)状态，因此，需要向EOA的每级移位寄存器提供多个控制信号。此外，也可以采用在相关技术的其他电路结构(例如，针对EOA设计的移位寄存器)得到发光控制信号，但是这些电路结构中，同样存在上述问题，需要数量较多的控制信号或时钟信号。
图8示出了应用了相关技术中的由氧化物薄膜晶体管构成的EOA及其工作时序示例。参照图8，第n行像素Pixel(n)至第(n+3)行Pixel(n+3)各自的发 光控制端EM连接至EOA的相应各级移位寄存器EOA_(n)O、EOA_(n)E、EOA_(n+1)O、EOA_(n+1)E，第n行像素Pixel(n)至第(n+3)行Pixel(n+3)各自的复位端Reset和扫描控制端Gate连接至GOA的相应各级移位寄存器GOA_(n-1)至GOA_(n+2)和GOA_last。由于相关技术中的氧化物薄膜晶体管EOA的各级移位寄存器的输出脉宽由时钟脉宽决定，当对像素进行初始化时，需要将EOA的输出信号保持为截止电平，因此，整个EOA需要四个时钟信号ECK1、ECK2、ECK3、ECK4。
为此，本公开特别提供了一种移位寄存器及其驱动方法、用于显示装置的发光控制驱动器、显示装置，其基本上消除了由相关技术中技术的限制和不足导致的问题中的一个或多个。
在一方面，本公开提供一种移位寄存器，其包括输入电路、第一控制电路、第二控制电路和输出电路，其中，构成所述移位寄存器的所有晶体管为N型晶体管，并且该移位寄存器的输出信号的具有无效电平的时段的时长取决于该移位寄存器的输入信号的具有无效电平的时段的时长，无效电平是能够使N型晶体管截止的电平。
图1示出了根据本公开实施例的移位寄存器的框图。
参照图1，移位寄存器可以包括输入电路1、第一控制电路2、第二控制电路3和输出电路4。
输入电路1可以连接至输入信号端INPUT、第一时钟端CK和第一节点NODE1，并被配置为接收施加至输入信号端INPUT的输入信号，并响应于施加至所述第一时钟端的第一时钟信号而将所述输入信号传至所述第一节点。
第一控制电路2可以连接至第二时钟端CKB、第一电源端VGL、第一节点NODE1和第二节点NODE2，并被配置为接收施加至第一电源端VGL的第一电源信号，并且响应于施加至第二时钟端CKB的第二时钟信号和第二节点NODE2处的电压而控制第一节点NODE1处的电压。
第二控制电路3可以连接至第一时钟端CK、第二时钟端CKB、第一电源端VGL、第二电源端VGH、第一节点NODE1、第二节点NODE2和第五节点NODE5，并被配置为接收第一电源信号和施加至第二电源端VGH的第二电源信号，响应于 第一时钟信号、第二时钟信号和第一节点NODE1处的电压而控制第二节点NODE2处的电压，并且响应于第二时钟信号和第一节点NODE1处的电压而控制第五节点NODE5处的电压。
输出电路4可以连接至第一节点NODE1、第五节点NODE5、第一电源端VGL、第二电源端VGH和输出信号端OUT，并被配置为响应于第一节点NODE1处的有效电平而将第二电源信号传输至输出信号端OUT，并且响应于第五节点NODE5处的有效电平而将第一电源信号传输至输出信号端OUT。
第一电源端VGL提供的第一电源信号可以具有恒定的无效电平，第二电源端VGH提供的第二电源信号可以具有恒定的无效电平。
在该移位寄存器中，如后续参照图3和图4A至图4J描述的那样，从输出信号端OUT输出的输出信号的具有无效电平的时段的时长取决于施加至输入信号端INPUT的输入信号的具有无效电平的时段的时长。例如，输出信号的具有无效电平的时段的时长(换言之，脉冲宽度，或脉宽)可以基本上等于施加至输入信号端INPUT的输入信号的具有无效电平的时段的时长。由此，可以减少该移位寄存器的控制信号数量，并且简化移位寄存器的连接和走线。
在该移位寄存器中，如后续参照图2描述的那样，构成移位寄存器的所有晶体管可以为N型晶体管。例如，所有晶体管均为导电类型为N型的氧化物薄膜晶体管。由此，该移位寄存器可以适用于大尺寸显示面板。显然，这种情况下，有效电平为高电平，无效电平为低电平，并且第一电源信号为恒定低电平的电源信号，第二电源信号为恒定高电平的电源信号。
在该移位寄存器中，如后续将描述的那样，当输入信号为无效电平且第一时钟信号从无效电平变为有效电平时，第一节点NODE1处的电压可以从第二电平变为第一电平，并且，当输入信号为有效电平且第二时钟信号从无效电平变为有效电平时，第一节点NODE1处的电压可以从第二电平变为第三电平，其中，第一电平是无效电平，第二电平和第三电平是有效电平，并且第一电平小于第二电平，第二电平小于第三电平。第三电平可以是比第二电源信号的高电平更高的电平。
在该移位寄存器中，如后续将描述的那样，当输入信号为无效电平且第二时钟信号从无效电平变为有效电平，第二节点NODE2处的电压可以从第五电平变为第六电平，并且，当输入信号为有效电平且第一时钟信号从有效电平变为无效电平，第二节点NODE2处的电压可以从第五电平变为第四电平，其中，第四电平是无效电平，第五电平和第六电平是有效电平，并且第四电平小于第五电平，第五电平小于第六电平。第六电平可以是比第二电源信号的高电平更高的电平。
基于第一节点NODE1和第二节点NODE2的上述电平转变，可以使输出信号端OUT的输出信号的脉宽根据输入信号的脉宽而调整。由此，可以减少该移位寄存器的控制信号数量，并且简化移位寄存器的连接和走线。
图2示出了根据本公开一些实施例的移位寄存器的电路图。
在一些实施例中，参照图2，输入电路1可以包括第一输入晶体管M1。第一输入晶体管M1的控制极连接至第一时钟端CK，第一极连接至输入信号端INPUT，第二极连接至第一节点NODE1。
在一些实施例中，参照图2，第一控制电路2可以包括第一控制晶体管M3、第二控制晶体管M4和第一控制电容C3。第一控制晶体管M3的控制极连接至第二时钟端CKB，第一极连接至第一节点NODE1，第二极连接至第三节点NODE3。第二控制晶体管M4的控制极连接至第二节点NODE2，第一极连接至第三节点NODE3，第二极连接至第一电源端VGL。第一控制电容C3的第一端连接至第二时钟端CKB，第二端连接至第一节点NODE1。
在一些实施例中，参照图2，第二控制电路3可以包括第三控制晶体管M2、第四控制晶体管M5、第五控制晶体管M6、第六控制晶体管M7和第二控制电容C1。第三控制晶体管M2的控制极连接至第一节点NODE1，第一极连接至第一时钟端CK，第二极连接至第二节点NODE2。第四控制晶体管M5的控制极连接至第一时钟端CK，第一极连接至第二电源端VGH，第二极连接至第二节点NODE2。第五控制晶体管M6的控制极连接至第二节点NODE2，第一极连接至第二时钟端CKB，第二极连接至第四节点NODE4。第六控制晶体管M7的控制极连接至第二时钟端 CKB，第一极连接至第四节点NODE4，第二极连接至第五节点NODE5。第二控制电容C1的第一端连接至第二节点NODE2，第二端连接至第四节点NODE4。
在一些实施例中，参照图2，第二控制电路3还可以包括第七控制晶体管M8和第三控制电容C2。第七控制晶体管M8的控制极连接至第一节点NODE1，第一极连接至第五节点NODE5，第二极连接至第一电源端VGL。第三控制电容C2的第一端连接至第五节点NODE5，第二端连接至第一电源端VGL。
在一些实施例中，参照图2，输出电路4可以包括第一输出晶体管M10和第二输出晶体管M9。第一输出晶体管M10的控制极连接至第一节点NODE1，第一极连接至第二电源端VGH，第二极连接至输出信号端OUT。第二输出晶体管M9的控制极连接至第五节点NODE5，第一极连接至输出信号端OUT，第二极连接至第一电源端VGL。
下面结合图3和图4A至图4J说明根据本公开实施例的移位寄存器的工作过程。
需要说明的是，施加至第一时钟端CK的第一时钟信号和施加至第二时钟端CKB的第二时钟信号具有相同的频率以及相差180°的相位。由于时钟信号(包括第一时钟端CK的第一时钟信号和施加至第二时钟端CKB的第二时钟信号)难以实现理想情况下瞬时的高低电平跳变，即时钟信号在低电平切换到高电平时存在上升沿时间，高电平切换到低电平时存在下降沿时间；并且，为了避免不同时钟信号相互之间由于电平变化产生干扰，任意两个时钟信号(例如第一时钟端CK的第一时钟信号和施加至第二时钟端CKB的第二时钟信号)的上升沿时间和/或下降沿时间不存在重叠。在本公开实施例中，对于施加至第一时钟端CK的第一时钟信号为高电平的时段，在该时段的开始包括第一时钟信号由低变高的上升沿时间，在该时段的结尾包括由第一时钟信号由高变低的下降沿时间；而对于施加至第一时钟端CK的第一时钟信号为低电平的时段内，第一时钟信号表现为固定的低电平。同样地，对于施加至第二时钟端CK的第一时钟信号为高电平的时段，在该时段的开始包括第二时钟信号由低变高的上升沿时间，在该时段的结尾包括由第二时钟信号由高变低的下降沿时间；而对于施加至第二时 钟端CK的第二时钟信号为低电平的时段内，第二时钟信号表现为固定的低电平。
在第一时段T1之前，施加至输入信号端INPUT的输入信号为高电平。
在第一时段T1，施加至信号输入端INPUT的输入信号为低电平，施加至第一时钟端CK的第一时钟信号为高电平，施加至第二时钟端CKB的第二时钟信号为低电平。此时，输入电路1将输入信号传输至第一节点NODE1，第二控制电路3将施加至第二电源端VGH的高电平电源信号传输至第二节点NODE2。
具体地，参照图3和图4A，第一输入晶体管M1导通，第一节点NODE1通过第一输入晶体管M1放电，从而使第一节点NODE1处降为与输入端INPUT的输入信号的电平基本相同的第一电平，故第一电平为低电平。第四控制晶体管M5导通，第二节点NODE2通过第四控制晶体管M5充电，从而第二节点NODE2处的电压被充电至与第二电源信号的电平基本相同的第五电平，第五电平为高电平。第二控制晶体管M4导通，第三节点NODE3通过第二控制晶体管M4放电至低电平。第五控制晶体管M6导通，第四节点NODE4与第二时钟端CKB的第二时钟信号的电平基本相同，为低电平。由于第六控制晶体管M7和第七控制晶体管M8均关断，因此，第五节点NODE5处于浮置状态，维持第一时段T1之前的电平，为低电平。第一输出晶体管M10和第二输出晶体管M9由于第一节点NODE1和第五节点NODE5处的低电压而关断，从而输出信号端OUT处于浮置状态，维持第一时段T1之前的电平。
在第二时段T2，施加至信号输入端INPUT的输入信号为低电平，施加至第一时钟端CK的第一时钟信号为低电平，施加至第二时钟端CKB的第二时钟信号为高电平。此时，第二控制电路3将第二节点NODE2处的电压从第五电平提高至比第五电平更高的第六电平，第一控制电路2将第一节点NODE1处的电压控制为低电平。
具体地，参照图3和图4B，第五控制晶体管M6导通，第四节点NODE4与第二时钟端CKB的第二时钟信号的电平基本相同，为高电平。此时，由于第三控制晶体管M2和第四控制晶体管M5关断，第二节点NODE2处于浮置状态，在第二控制电容C1的自举(bootstrap)效应而由第五电平进一步抬高至第六电平。 第二控制晶体管M4和第一控制晶体管M3导通，第一节点NODE1通过第二控制晶体管M4和第一控制晶体管M3放电，从而第一节点NODE1处的电压保持低电平，并且由于第二控制晶体管M4的导通，第三节点NODE3处的电压与第一电源端VGL的电平基本相同。第六控制晶体管M7导通，第四节点NODE4处的高电平通过第六控制晶体管M7传输至第五节点NODE5，从而第五节点NODE5处的电压为高电平。第二输出晶体管M9在第五节点NODE5的控制下导通，从而输出信号端OUT输出的输出信号为低电平。
在第三时段T3，施加至信号输入端INPUT的输入信号为低电平，施加至第一时钟端CK的第一时钟信号为高电平，施加至第二时钟端CKB的第二时钟信号为低电平。此时，第二控制电路3将第二节点NODE2处的电压从第六电平降低至第五电平，输入电路1将第一节点NODE1处的电压控制为低电平。
具体地，参照图3和图4C，第一输入晶体管M1导通，从而第一节点NODE1处的电压为与输入端INPUT的电平基本相同的低电平，第三控制晶体管M2、第七控制晶体管M8和第一输出晶体管M10关断。第四控制晶体管M5导通，从而第二节点NODE2处的电压为第五电平。第二控制晶体管M4导通，第三节点NODE3与第一电源端VGL的电平基本相同，为低电平。第五控制晶体管M6导通，第四节点NODE4与第二时钟端CKB的第二时钟信号的电平基本相同，为低电平。第六控制晶体管M7关断，第五节点NODE5处的电压由于第三控制电容C2而保持为高电平。因此，第二输出晶体管M9保持导通，从输出信号端OUT输出的输出信号为低电平。
在第四时段T4，施加至信号输入端INPUT的输入信号为低电平，施加至第一时钟端CK的第一时钟信号为低电平，施加至第二时钟端CKB的第二时钟信号为高电平。此时，第二控制电路3将第二节点NODE2处的电压从第五电平提高至比第五电平更高的第六电平，第一控制电路2将第一节点NODE1处的电压控制为低电平。
具体地，参照图3和图4D，第五控制晶体管M6导通，第四节点NODE4与第二时钟端CKB的第二时钟信号的电平基本相同，为高电平。此时，第二节点NODE2 处于浮置状态，在第二控制电容C1的自举效应而由第五电平进一步抬高至第六电平。第二控制晶体管M4和第一控制晶体管M3导通，第一节点NODE1通过第二控制晶体管M4和第一控制晶体管M3放电，从而第一节点NODE1处的电压保持低电平，并且由于第二控制晶体管M4的导通，第三节点NODE3处的电压与第一电源端VGL的电平基本相同，为低电平。第六控制晶体管M7导通，第四节点NODE4的电平通过第六控制晶体管M7传输至第五节点NODE5，从而第五节点NODE5处的电压为高电平。第二输出晶体管M9在第五节点NODE5处的高电压的控制下导通，从而从输出信号端OUT输出的输出信号为低电平。
在第五时段T5，施加至信号输入端INPUT的输入信号为低电平，施加至第一时钟端CK的第一时钟信号为高电平，施加至第二时钟端CKB的第二时钟信号为低电平。此时，第二控制电路3将第二节点NODE2处的电压从第六电平降低至第五电平，输入电路1将第一节点NODE1处的电压控制为低电平。
具体地，参照图3和图4E，第一输入晶体管M1导通，从而第一节点NODE1处的电压保持低电平，第三控制晶体管M2、第七控制晶体管M8和第一输出晶体管M10关断。第四控制晶体管M5导通，从而第二节点NODE2处的电压为第五电平。第二控制晶体管M4导通，第三节点NODE3与第一电源端VGL的电平基本相同，为低电平。第五控制晶体管M6导通，第四节点NODE4与第二时钟端CKB的第二时钟信号的电平基本相同，为低电平。第六控制晶体管M7关断，第五节点NODE5处的电压由于第三控制电容C2而保持为高电平。因此，第二输出晶体管M9保持导通，从输出信号端OUT输出的输出信号为低电平。
在第六时段T6，施加至信号输入端INPUT的输入信号为高电平，施加至第一时钟端CK的第一时钟信号为低电平，施加至第二时钟端CKB的第二时钟信号为高电平。此时，第二控制电路3将第二节点NODE2处的电压从第五电平提高至比第五电平更高的第六电平，第一控制电路2将第一节点NODE1处的电压控制为低电平。
具体地，参照图3和图4F，第五控制晶体管M6导通，第四节点NODE4与第二时钟端CKB的第二时钟信号的电平基本相同，为高电平。此时，第二节点NODE2 处于浮置状态，在第二控制电容C1的自举效应而由第五电平进一步抬高至第六电平。第二控制晶体管M4和第一控制晶体管M3导通，第一节点NODE1通过第二控制晶体管M4和第一控制晶体管M3放电，从而第一节点NODE1处的电压保持低电平，并且第三节点NODE3处的电压也保持低电平。第六控制晶体管M7导通，第四节点NODE4处的高电平通过第六控制晶体管M7传输至第五节点NODE5，从而第五节点NODE5处的电压为高电平。第二输出晶体管M9在第五节点NODE5处的高电压的控制下导通，从而从输出信号端OUT输出低电平。
在第七时段T7，施加至信号输入端INPUT的输入信号为高电平，施加至第一时钟端CK的第一时钟信号为高电平，施加至第二时钟端CKB的第二时钟信号为低电平。此时，输入电路1将输入信号传输至第一节点NODE1，第二控制电路3将第二节点NODE2处的电压从第六电平降低至第五电平。
具体地，参照图3和图4G，第一输入晶体管M1导通，第一节点NODE1具有与输入端INPUT的输入信号的电平基本相同的第二电平，第二电平为高电平。此时，第三控制晶体管M2、第七控制晶体管M8和第一输出晶体管M10导通。第四控制晶体管M5导通，从而第二节点NODE2处的电压与第二电源端VGH的高电平电源信号基本相同，并且第二控制晶体管M4和第五控制晶体管M6导通。第三节点NODE3通过第二控制晶体管M4放电，从而第三节点NODE3处的电压保持低电平。第四节点NODE4通过第五控制晶体管M6放电，从而第四节点NODE4处的电压为低电平。第五节点NODE5通过第七控制晶体管M8放电，从而第五节点NODE5处的电压为低电平。在第七时段T7的结尾处，当第一时钟信号从高电平变为低电平时，第二节点NODE2通过第三控制晶体管M2放电，使得第二节点NODE2处的电压从第五电平降至与第二时钟端CKB的第二时钟信号的电平基本相同的第四电平，第四电平为低电平。在第七时段T7中，第二输出晶体管M9关闭，第一输出晶体管M10导通，从而从输出信号端OUT输出的输出信号为高电平。
在第八时段T8，施加至信号输入端INPUT的输入信号为高电平，施加至第一时钟端CK的第一时钟信号为低电平，施加至第二时钟端CKB的第二时钟信号 为高电平。此时，第一控制电路2将第一节点NODE1处的电压控制为第三电平，第二控制电路3将第二节点NODE2处的电压控制为低电平。
具体地，参照图3和图4H，由于在第七时段结尾，第二节点NODE2处的电压已经降至低电平，因此第二控制晶体管M4和第五控制晶体管M6关断。由于第一输入晶体管M1也关断，因此第一节点NODE1处于浮置状态，而施加至第二时钟端CKB的第二时钟信号为高电平，因此第一节点NODE1处的电压由于第一控制电容C3的自举效应由第二电平进一步提升至第三电平。第三控制晶体管M2、第一控制晶体管M3、第七控制晶体管M8和第一输出晶体管M10导通。第三节点NODE3通过第一控制晶体管M3充电，从而第三节点NODE3处的电压变为高电平。第五节点NODE5处的电压由于第七控制晶体管M8的导通而保持低电平，从而第二输出晶体管M9关断。从输出信号端OUT输出高电平。由于第一节点NODE1处的电压处于比第二电平更高的第三电平，因此，输出信号在第八时段T8的电平略高于在第七时段T7的电平。
在第九时段T9，施加至信号输入端INPUT的输入信号为高电平，施加至第一时钟端CK的第一时钟信号为高电平，施加至第二时钟端CKB的第二时钟信号为低电平。此时，输入电路1将输入信号传输至第一节点NODE1，第二控制电路3将第二节点NODE2处的电压控制为第五电平。
具体地，参照图3和图4I，第一输入晶体管M1导通，第一节点NODE1通过第一输入晶体管M1充电，从而第一节点NODE1处的电压与输入端INPUT的输入信号的电平基本相同，为高电平。此时，第三控制晶体管M2、第七控制晶体管M8和第一输出晶体管M10导通。第四控制晶体管M5导通，从而第二节点NODE2处的电压为与第二电源端VGH的高电平电源信号基本相同的第五电平，并且第二控制晶体管M4和第五控制晶体管M6导通。第三节点NODE3通过第二控制晶体管M4放电，从而第三节点NODE3处的电压保持低电平。第四节点NODE4通过第五控制晶体管M6放电，从而第四节点NODE4处的电压为低电平。第五节点NODE5通过第七控制晶体管M8放电，从而第五节点NODE5处的电压为低电平。在第九时段T9的结尾处，当第一时钟信号从高电平变为低电平时，第二节点 NODE2通过第三控制晶体管M2放电，使得第二节点NODE2处的电压从第五电平降至低电平。在第八时段T7中，第二输出晶体管M9关闭，第一输出晶体管M10导通，从而从输出信号端OUT输出的输出信号为高电平。
在第十时段T10，施加至信号输入端INPUT的输入信号为高电平，施加至第一时钟端CK的第一时钟信号为高电平，施加至第二时钟端CKB的第二时钟信号为低电平。此时，第一控制电路2将第一节点NODE1处的电压控制为第三电平，第二控制电路3将第二节点NODE2处的电压控制为低电平。
具体地，参照图3和图4J，第二控制晶体管M4和第五控制晶体管M6关断。由于第一输入晶体管M1也关断，因此第一节点NODE1处于浮置状态，而第二时钟端CKB被施加有高电平的时钟信号，因此第一节点NODE1处的电压由于第一控制电容C3的自举效应而变高至第三电平。第三控制晶体管M2、第一控制晶体管M3、第七控制晶体管M8和第一输出晶体管M10导通。第二节点NODE2通过第三控制晶体管M2放电，从而第二节点NODE2处的电压变为与第一时钟信号基本相同的低电平。第三节点NODE3通过第一控制晶体管M3充电，从而第三节点NODE3处的电压变为高电平。第五节点NODE5处的电压由于第七控制晶体管M8的导通而保持低电平，从而第二输出晶体管M9关断。从输出信号端OUT输出的输出信号为高电平。
此后，施加至输入信号端INPUT的输入信号保持高电平，第一时钟信号和第二时钟信号继续保持原频率进行高低电平的切换，直到响应于输入信号的变化(例如，输入信号再次从高电平变为低电平)而进行下一个第一时段T1。
需要说明的是，第二电平和第五电平可以相同，也可以不同，本公开对此不做限制，只要第二电平和第五电平均为有效电平即可。类似地，第一电平和第四电平可以相同，也可以不同，本公开对此不做限制，只要第一电平和第四电平均为无效电平即可。
在根据本公开实施例的移位寄存器中，构成移位寄存器的所有晶体管可以为N型晶体管(例如，导电类型为N型的氧化物薄膜晶体管)。由此，该移位寄存器可以适用于大尺寸显示面板。此外，可以使输出信号端OUT的输出信号的 脉宽根据输入信号的脉宽而调整。由此，可以减少该移位寄存器的控制信号数量，并且简化移位寄存器的连接和走线。
在另一方面，本公开提供了一种发光控制驱动器，包括多个级联的移位寄存器，所述移位寄存器为上述移位寄存器。
例如，参照图5，该发光控制驱动器包括N个级联的移位寄存器(后称N级移位寄存器)。第一级移位寄存器的信号输入端被施加有扫描起始信号EM_STV，第i级移位寄存器的信号输入端连接至第i-1级移位寄存器的信号输出端(2≤i≤N)，并且各级移位寄存器分别输出本级的信号EM_OUT<1>至EM_OUT<N>。例如，当发光控制驱动器用于驱动显示面板中的像素时，每级移位寄存器分别输出针对相应像素行的发光控制信号。各级移位寄存器的第一时钟端CK和第二时钟端CKB分别交替连接至第一时钟信号线EM_CK和第二时钟信号线EM_CKB。例如，参照图5，奇数级移位寄存器的第一时钟端CK连接至第一时钟信号线EM_CK，第二时钟端CKB连接至第二时钟信号线EM_CKB；偶数级移位寄存器的第一时钟端CK连接至第二时钟信号线EM_CKB，第二时钟端CKB连接至第一时钟信号线EM_CK。施加至第一时钟信号线EM_CK的时钟信号与施加至第二时钟信号线的时钟信号EM_CKB具有相同的频率以及相差180°的相位。
在根据本公开实施例的发光控制驱动器中，构成发光控制器的所有晶体管可以为N型晶体管(例如，导电类型为N型的氧化物薄膜晶体管)，因此，该发光控制器可以适用于大尺寸显示面板。此外，由于各级移位寄存器的输出信号端OUT的输出信号的脉宽根据输入信号的脉宽而调整，因此，可以直接通过设置扫描起始信号EM_STV的脉宽来确定各级移位寄存器输出的发光控制信号的脉宽，而无需更复杂的时钟设计以及额外的初始化控制信号。由此，可以减少控制信号数量，简化连接和走线，更有利于窄边/无边框显示面板设计。
在另一方面，本公开提供一种显示装置，包括上述发光控制驱动器。
图6示出了根据本公开一些实施例的显示装置。该显示装置包括多个像素PX以及根据本公开实施例的发光控制驱动器。多个像素PX按照多行多列排布。例如，参照图6，多个像素PX排列为n行m列，每行像素PX连接至多条栅线 G1至Gn中的相应一条和多条发光控制线E1至En中的相应一条，每列像素PX连接至多条数据线D1至Dm中的相应一条。发光控制驱动器的每级移位寄存器的输出信号端连接至发光控制线E1至En中的相应一条，以将从相应的发光控制信号(参照图5的EM_OUT<1>至EM_OUT<N>)传输至发光控制线E1至En。
如图6所示，显示装置还可以包括栅极驱动器和数据驱动器，其分别向栅线G1至Gn和数据线D1至Dm提供扫描信号和数据信号。
图7A是像素PX的示例性框图，图7B是像素PX的示例性电路图，图7C是示意性地示出像素PX的工作的时序图。像素PX可以包括像素驱动电路100和发光器件L，像素驱动电路100可以包括驱动子电路10、写入子电路20和灰阶控制子电路30。像素驱动电路100连接至用于与栅线相连的扫描控制端Gate、用于与数据线相连的数据信号端Data以及用于与发光控制线相连的发光控制端EM。可以采用根据本公开实施例的发光控制驱动器向发光控制端EM提供发光控制信号，当这样的发光控制信号为无效电平时，灰阶控制子电路30开启，以使得发光电流可流至发光器件L。例如，当像素PX具有如图7B所示的等效电路时，数据驱动器通过数据线提供的数据信号施加至晶体管T5的源极，栅极驱动器通过栅线提供的扫描信号施加至晶体管T5的栅极。发光控制器通过发光控制线提供的发光控制信号施加至晶体管T2的栅极，以控制发光电流传输至发光器件L的路径。驱动晶体管Td提供与数据信号对应的发光电流。当施加至发光控制端EM的发光控制信号为低电平时，晶体管T2导通，发光电流流至发光器件L，使其发光。
需要说明的是，图7A至图7C仅仅是为了帮助说明发光控制驱动器提供的发光控制信号在像素PX中的控制作用而示出的像素PX的示例，像素PX的电路结构和工作过程并不限于此。
在一些实施例中，根据本公开实施例的显示装置可为微型LED显示装置。
例如，该显示装置可为显示器、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在另一方面，本公开提供一种上述移位寄存器的驱动方法。该方法包括： 在第一时段，向移位寄存器的输入信号端施加具有无效电平的输入信号，提供具有有效电平的第一时钟信号和具有无效电平的第二时钟信号；在第二时段，向移位寄存器的输入信号端施加具有无效电平的输入信号，提供具有无效电平的第一时钟信号和具有有效电平的第二时钟信号；在第三时段，向移位寄存器的输入信号端施加具有无效电平的输入信号，提供具有有效电平的第一时钟信号和具有无效电平的第二时钟信号；在第四时段，向移位寄存器的输入信号端施加具有无效电平的输入信号，提供具有无效电平的第一时钟信号和具有有效电平的第二时钟信号；在第五时段，向移位寄存器的输入信号端施加具有无效电平的输入信号，提供具有有效电平的第一时钟信号和具有无效电平的第二时钟信号；在第六时段，向移位寄存器的输入信号端施加具有有效电平的输入信号，提供具有无效电平的第一时钟信号和具有有效电平的第二时钟信号；在第七时段，向移位寄存器的输入信号端施加具有有效电平的输入信号，提供具有有效电平的第一时钟信号和具有无效电平的第二时钟信号；以及在第八时段，向移位寄存器的输入信号端施加具有有效电平的输入信号，提供具有无效电平的第一时钟信号和具有有效电平的第二时钟信号。第一时段至第八时段是在时间上顺序的时段，并且在紧挨第一时段在前的时段中，输入信号具有有效电平。第一时钟信号和第二时钟信号具有相同的频率以及相差180°的相位。
例如，参照图3，上述第一时段至第八时段为图3所示的时段T1至T8，第一时钟信号为图3所示的信号CK，第二时钟信号为图3所示的信号CKB，输入信号为图3所示的信号INPUT，从移位寄存器输出端输出的信号为图3所示的信号OUT。
例如，参照上文中结合图3的分析，在第一时段T1的起始处，随着第一时钟信号从无效电平变为有效电平，第一节点NODE1处的电压从第二电平变为第一电平，并且，在第八时段T8的起始处，随着第二时钟信号从无效电平变为有效电平，第一节点NODE1处的电压从第二电平变为更高的第三电平。
例如，参照上文中结合图3的分析，在第二时段T2的起始处，随着第二时钟信号从无效电平变为有效电平，第二节点NODE2处的电压从第五电平变为更 高的第六电平，并且，在第七时段T7的结尾处，随着第一时钟信号从有效电平变为无效电平，第二节点NODE2处的电压从第五电平变为第四电平。
根据本公开的上述移位寄存器驱动方法，可以通过设置施加至输入信号端INPUT的输入信号的具有无效电平的时段的时长来控制从输出信号端OUT输出的输出信号的具有无效电平的时段的时长。由此，可以减少该移位寄存器的控制信号数量，并且简化移位寄存器的连接和走线。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (16)

  1. 一种移位寄存器，包括：
    输入电路，其连接至输入信号端、第一时钟端和第一节点，并被配置为接收施加至所述输入信号端的输入信号，并响应于施加至所述第一时钟端的第一时钟信号而将所述输入信号传至所述第一节点；
    第一控制电路，其连接至第二时钟端、第一电源端、所述第一节点和第二节点，并被配置为接收施加至所述第一电源端的第一电源信号，并且响应于施加至所述第二时钟端的第二时钟信号和所述第二节点处的电压而控制所述第一节点处的电压；
    第二控制电路，其连接至所述第一时钟端、所述第二时钟端、所述第一电源端、第二电源端、所述第一节点、所述第二节点和第五节点，并被配置为接收所述第一电源信号和施加至所述第二电源端的第二电源信号，响应于所述第一时钟信号、所述第二时钟信号和所述第一节点处的电压而控制所述第二节点处的电压，并且响应于所述第二时钟信号和所述第一节点处的电压而控制所述第五节点处的电压；
    输出电路，其连接至所述第一节点、所述第五节点、所述第一电源端、第二电源端和所述输出信号端，并被配置为响应于所述第一节点处的有效电平而将第二电源信号传输至所述输出信号端，并且响应于所述第五节点处的有效电平而将所述第一电源信号传输至所述输出信号端，
    其中，从所述输出信号端输出的输出信号的具有无效电平的时段的时长取决于施加至所述输入信号端的所述输入信号的具有无效电平的时段的时长，并且，
    其中，构成所述移位寄存器的所有晶体管为N型晶体管。
  2. 根据权利要求1所述的移位寄存器，其中，响应于所述输入信号为无效电平且所述第一时钟信号从无效电平变为有效电平，所述第一节点处的电压从 第二电平变为第一电平，并且，响应于所述输入信号为有效电平且所述第二时钟信号从无效电平变为有效电平，所述第一节点处的电压从所述第二电平变为第三电平，所述第一电平是无效电平，所述第二电平和所述第三电平是有效电平，并且所述第一电平小于所述第二电平，所述第二电平小于所述第三电平。
  3. 根据权利要求2所述的移位寄存器，其中，响应于所述输入信号为无效电平且所述第二时钟信号从无效电平变为有效电平，所述第二节点处的电压从第五电平变为第六电平，并且，响应于所述输入信号为有效电平且所述第一时钟信号从有效电平变为无效电平，所述第二节点处的电压从所述第五电平变为第四电平，所述第四电平是无效电平，所述第五电平和所述第六电平是有效电平，并且所述第四电平小于所述第五电平，所述第五电平小于所述第六电平。
  4. 根据权利要求1所述的移位寄存器，其中，所述第一控制电路包括：第一控制晶体管、第二控制晶体管和第一控制电容，
    所述第一控制晶体管的控制极连接至所述第二时钟端，第一极连接至所述第一节点，第二极连接至第三节点，
    所述第二控制晶体管的控制极连接至所述第二节点，第一极连接至所述第三节点，第二极连接至所述第一电源端，
    所述第一控制电容的第一端连接至所述第二时钟端，第二端连接至所述第一节点。
  5. 根据权利要求4所述的移位寄存器，其中，所述第二控制电路包括：
    第三控制晶体管、第四控制晶体管、第五控制晶体管、第六控制晶体管和第二控制电容，
    所述第三控制晶体管的控制极连接至所述第一节点，第一极连接至所述第一时钟端，第二极连接至所述第二节点，
    所述第四控制晶体管的控制极连接至所述第一时钟端，第一极连接至所述 第二电源端，第二极连接至所述第二节点，
    所述第五控制晶体管的控制极连接至所述第二节点，第一极连接至所述第二时钟端，第二极连接至第四节点，
    所述第六控制晶体管的控制极连接至所述第二时钟端，第一极连接至所述第四节点，第二极连接至所述第五节点，
    所述第二控制电容的第一端连接至所述第二节点，第二端连接至所述第四节点。
  6. 根据权利要求5所述的移位寄存器，其中，所述第二控制电路还包括：第七控制晶体管和第三控制电容，
    所述第七控制晶体管的控制极连接至所述第一节点，第一极连接至所述第五节点，第二极连接至所述第一电源端，
    所述第三控制电容的第一端连接至所述第五节点，第二端连接至所述第一电源端。
  7. 根据权利要求5或6所述的移位寄存器，其中，所述输出电路包括：第一输出晶体管和第二输出晶体管，
    所述第一输出晶体管的控制极连接至所述第一节点，第一极连接至所述第二电源端，第二极连接至所述输出信号端，
    所述第二输出晶体管的控制极连接至所述第五节点，第一极连接至所述输出信号端，第二极连接至所述第一电源端。
  8. 根据权利要求7所述的移位寄存器，其中，所述输入电路包括：第一输入晶体管，所述第一输入晶体管的控制极连接至所述第一时钟端，第一极连接至所述输入信号端，第二极连接至所述第一节点。
  9. 根据权利要求1-8中任一所述的移位寄存器，其中，构成所述移位寄存 器的所有晶体管为氧化物薄膜晶体管。
  10. 一种发光控制驱动器，包括多级移位寄存器，每个移位寄存器为根据权利要求1-9任一所述的移位寄存器。
  11. 根据权利要求10所述的发光控制驱动器，其中，所述多级移位寄存器中的奇数级移位寄存器的第一时钟端连接至第一时钟信号线，第二时钟端连接至第二时钟信号线，并且
    所述多级移位寄存器中的偶数级移位寄存器的第一时钟端连接至所述第二时钟信号线，第二时钟端连接至所述第一时钟信号线，
    施加至所述第一时钟信号线的时钟信号与施加至所述第二时钟信号线的时钟信号具有相同的频率以及相差180°的相位。
  12. 根据权利要求11所述的发光控制驱动器，其中，所述多级移位寄存器中的第一级移位寄存器的输入信号端被施加有发射起始信号，所述多级移位寄存器中的除所述第一级之外的每一级移位寄存器的输入信号端连接至上一级移位寄存器的输出信号端。
  13. 一种显示装置，包括：
    多个像素，每个像素连接至多条栅线中的相应栅线、多条数据线中的相应数据线、多条发光控制线中的相应发光控制线；以及
    权利要求10-12中任一所述的发光控制驱动器，所述发光控制驱动器的每级移位寄存器的输出信号端连接至所述多条发光控制线中的相应一条，以将从该级移位寄存器的输出信号传输至所述多条发光控制线中的所述相应一条。
  14. 一种移位寄存器的驱动方法，所述移位寄存器是根据权利要求1所述的移位寄存器，所述第一时钟信号和所述第二时钟信号具有相同的频率以及相 差180°的相位，
    所述驱动方法包括：
    在第一时段，向所述移位寄存器的输入信号端施加具有无效电平的输入信号，提供具有有效电平的第一时钟信号和具有无效电平的第二时钟信号；
    在第二时段，向所述移位寄存器的输入信号端施加具有无效电平的输入信号，提供具有无效电平的第一时钟信号和具有有效电平的第二时钟信号；
    在第三时段，向所述移位寄存器的输入信号端施加具有无效电平的输入信号，提供具有有效电平的第一时钟信号和具有无效电平的第二时钟信号；
    在第四时段，向所述移位寄存器的输入信号端施加具有无效电平的输入信号，提供具有无效电平的第一时钟信号和具有有效电平的第二时钟信号；
    在第五时段，向所述移位寄存器的输入信号端施加具有无效电平的输入信号，提供具有有效电平的第一时钟信号和具有无效电平的第二时钟信号；
    在第六时段，向所述移位寄存器的输入信号端施加具有有效电平的输入信号，提供具有无效电平的第一时钟信号和具有有效电平的第二时钟信号；
    在第七时段，向所述移位寄存器的输入信号端施加具有有效电平的输入信号，提供具有有效电平的第一时钟信号和具有无效电平的第二时钟信号；以及
    在第八时段，向所述移位寄存器的输入信号端施加具有有效电平的输入信号，提供具有无效电平的第一时钟信号和具有有效电平的第二时钟信号，
    其中，所述第一时段至所述第八时段是在时间上顺序的时段，并且
    在紧挨所述第一时段在前的时段中，所述输入信号具有有效电平。
  15. 根据权利要求14所述的驱动方法，其中，在所述第一时段的起始处，随着所述第一时钟信号从无效电平变为有效电平，所述第一节点处的电压从第二电平变为第一电平，并且，在所述第八时段的起始处，随着所述第二时钟信号从无效电平变为有效电平，所述第一节点处的电压从所述第二电平变为第三电平，所述第一电平是无效电平，所述第二电平和所述第三电平是有效电平，并且所述第一电平小于所述第二电平，所述第二电平小于所述第三电平。
  16. 根据权利要求15所述的驱动方法，其中，在所述第二时段的起始处，随着所述第二时钟信号从无效电平变为有效电平，所述第二节点处的电压从第五电平变为第六电平，并且，在所述第七时段的结尾处，随着所述第一时钟信号从有效电平变为无效电平，所述第二节点处的电压从所述第五电平变为所述第四电平，所述第四电平是无效电平，所述第五电平和所述第六电平是有效电平，并且所述第四电平小于所述第五电平，所述第五电平小于所述第六电平。
PCT/CN2021/133900 2021-11-29 2021-11-29 移位寄存器及其驱动方法、发光控制驱动器、显示装置 WO2023092538A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US17/923,690 US20240221608A1 (en) 2021-11-29 2021-11-29 Shift register and driving method thereof, light emission control driver and display apparatus
PCT/CN2021/133900 WO2023092538A1 (zh) 2021-11-29 2021-11-29 移位寄存器及其驱动方法、发光控制驱动器、显示装置
CN202180003696.1A CN116868263A (zh) 2021-11-29 2021-11-29 移位寄存器及其驱动方法、发光控制驱动器、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/133900 WO2023092538A1 (zh) 2021-11-29 2021-11-29 移位寄存器及其驱动方法、发光控制驱动器、显示装置

Publications (1)

Publication Number Publication Date
WO2023092538A1 true WO2023092538A1 (zh) 2023-06-01

Family

ID=86538768

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/133900 WO2023092538A1 (zh) 2021-11-29 2021-11-29 移位寄存器及其驱动方法、发光控制驱动器、显示装置

Country Status (3)

Country Link
US (1) US20240221608A1 (zh)
CN (1) CN116868263A (zh)
WO (1) WO2023092538A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015138916A (ja) * 2014-01-23 2015-07-30 古河電気工業株式会社 発光ダイオード表示装置及びその制御方法
CN106887209A (zh) * 2017-04-28 2017-06-23 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、移位寄存器以及显示装置
CN108198586A (zh) * 2018-01-18 2018-06-22 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动器和显示面板
CN111583880A (zh) * 2019-02-18 2020-08-25 合肥京东方光电科技有限公司 移位寄存器单元电路及驱动方法、栅极驱动器和显示装置
CN113066422A (zh) * 2019-12-13 2021-07-02 华为机器有限公司 扫描与发光驱动电路、扫描与发光驱动***、显示面板
CN113284459A (zh) * 2021-07-19 2021-08-20 深圳市柔宇科技股份有限公司 扫描驱动单元、扫描驱动电路、阵列基板及显示器
CN113625893A (zh) * 2020-05-07 2021-11-09 联咏科技股份有限公司 触控显示装置的驱动方法、驱动电路和触控显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015138916A (ja) * 2014-01-23 2015-07-30 古河電気工業株式会社 発光ダイオード表示装置及びその制御方法
CN106887209A (zh) * 2017-04-28 2017-06-23 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、移位寄存器以及显示装置
CN108198586A (zh) * 2018-01-18 2018-06-22 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动器和显示面板
CN111583880A (zh) * 2019-02-18 2020-08-25 合肥京东方光电科技有限公司 移位寄存器单元电路及驱动方法、栅极驱动器和显示装置
CN113066422A (zh) * 2019-12-13 2021-07-02 华为机器有限公司 扫描与发光驱动电路、扫描与发光驱动***、显示面板
CN113625893A (zh) * 2020-05-07 2021-11-09 联咏科技股份有限公司 触控显示装置的驱动方法、驱动电路和触控显示装置
CN113284459A (zh) * 2021-07-19 2021-08-20 深圳市柔宇科技股份有限公司 扫描驱动单元、扫描驱动电路、阵列基板及显示器

Also Published As

Publication number Publication date
US20240221608A1 (en) 2024-07-04
CN116868263A (zh) 2023-10-10

Similar Documents

Publication Publication Date Title
CN107154239B (zh) 一种像素电路、驱动方法、有机发光显示面板及显示装置
US9747854B2 (en) Shift register, gate driving circuit, method for driving display panel and display device
CN105702295B (zh) 移位寄存器单元、栅极驱动电路、显示面板及显示装置
TWI534781B (zh) Scan drive circuit and organic light emitting display
CN107358914B (zh) 一种发光控制电路、其驱动方法、显示面板及显示装置
CN105632444B (zh) 一种移位寄存器、栅极驱动电路及显示面板
US20220343855A1 (en) Gate driving circuit, display substrate, display device and gate driving method
WO2016184254A1 (zh) 一种有机发光二极管面板、栅极驱动电路及其单元
US11837147B2 (en) Display substrate, display panel, display apparatus and display driving method
WO2020228017A1 (zh) 信号产生方法、信号发生电路以及显示装置
CN105427790B (zh) 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
CN113299223B (zh) 一种显示面板和显示装置
CN111223449B (zh) 一种显示面板、其驱动方法及显示装置
WO2018126741A1 (zh) 移位寄存器电路及其驱动方法、栅极驱动电路、显示面板和显示装置
WO2019061981A1 (zh) 一种显示装置的驱动电路和驱动方法
KR20180073112A (ko) 발광 제어 드라이버 및 그를 이용한 유기 발광 다이오드 표시 장치
JP6110177B2 (ja) シフトレジスタ回路および画像表示装置
WO2023092538A1 (zh) 移位寄存器及其驱动方法、发光控制驱动器、显示装置
US20220406244A1 (en) Shift register and driving method thereof, gate driver and display device
CN112863449B (zh) 一种发光控制电路及其驱动方法、显示面板及显示装置
TWI713008B (zh) 驅動電路和其操作方法
WO2023019561A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
TW202034341A (zh) 移位暫存器與電子裝置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202180003696.1

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 17923690

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21965271

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE