WO2018126741A1 - 移位寄存器电路及其驱动方法、栅极驱动电路、显示面板和显示装置 - Google Patents

移位寄存器电路及其驱动方法、栅极驱动电路、显示面板和显示装置 Download PDF

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Publication number
WO2018126741A1
WO2018126741A1 PCT/CN2017/103352 CN2017103352W WO2018126741A1 WO 2018126741 A1 WO2018126741 A1 WO 2018126741A1 CN 2017103352 W CN2017103352 W CN 2017103352W WO 2018126741 A1 WO2018126741 A1 WO 2018126741A1
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Prior art keywords
node
reference voltage
terminal
potential
shift register
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PCT/CN2017/103352
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English (en)
French (fr)
Inventor
张杨
刘金良
陈沫
赵剑
高吉磊
孙松梅
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/768,487 priority Critical patent/US10541039B2/en
Publication of WO2018126741A1 publication Critical patent/WO2018126741A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register circuit and a driving method thereof, a gate driving circuit, a display panel, and a display device.
  • the shift register can operate as a gate drive circuit of the display device to sequentially supply gate scan signals to the respective gate lines to turn on transistors in each pixel row, thereby allowing data signals to be written to the respective pixels.
  • the high level of the gate scan signal In order to fully open each transistor, the high level of the gate scan signal generally needs to reach 25V or more. Due to the self-boosting effect of the storage capacitor in the shift register, the potential at some internal nodes of the shift register is even higher, for example, twice as high as the high level of the gate scan signal (50V or higher) ). Such a high potential causes a large change in the characteristics of the transistors connected to these internal nodes, resulting in a threshold voltage shift. If the display device is operated for a long time under such conditions, the shift register becomes unstable and a deteriorated gate scan signal is obtained.
  • a shift register circuit comprising: a set circuit configured to transmit the input pulse to a first node in response to an input pulse from a signal input being valid to a node setting is at an active potential; a first reset circuit configured to transmit a first reference voltage from the first reference voltage terminal to the first node to transmit the first in response to a reset pulse from the reset signal terminal being active
  • the node setting is at an inactive potential and will be responsive in response to a reset pulse from the reset signal terminal
  • the first reference voltage from the first reference voltage terminal is transmitted to a signal output;
  • the output circuit is configured to receive a first clock signal from the first clock signal end in response to the first node being at the active potential Transmitting to the signal output, and changing the effective potential of the first node further away from the inactive potential in response to the first clock signal being transmitted to the signal output being active; and a first control circuit, Configuring to maintain the first node at the active potential in response to the input pulse from the signal input being active, and based on the
  • the first control circuit includes: a first transistor having a gate and a first electrode each connected to the signal input, and a second electrode connected to the second node; and a second transistor having a gate connected to the signal output, a first electrode connected to the second reference voltage terminal, and a second electrode connected to the second node; and a first capacitor connected to the second node and Between the first nodes.
  • the output circuit includes: a third transistor having a gate connected to the first node, a first electrode connected to the first clock signal end, and a second connected to the signal output end a second electrode; and a second capacitor connected between the first node and the signal output end.
  • the first reset circuit includes: a fourth transistor having a gate connected to the reset signal terminal, a first electrode connected to the first reference voltage terminal, and a signal output terminal a second electrode; and a seventh transistor having a gate connected to the reset signal terminal, a first electrode connected to the first reference voltage terminal, and a second electrode connected to the first node.
  • the set circuit includes a sixth transistor having a gate and a first electrode each connected to the signal input, and a second electrode coupled to the first node.
  • the shift register circuit further includes: a second control circuit configured to pass the first reference from the first reference voltage terminal in response to the first node being at the active potential Transmitting a voltage to a third node to set the third node at an inactive potential, and responsive to a second clock signal from the second clock signal terminal being active and the first node being at the inactive potential Clock signal is transmitted to the a third node to set the third node at an active potential; and a second reset circuit configured to responsive to the third node being at the active potential, the first from the first reference voltage terminal a reference voltage is transmitted to the first node to set the first node at an inactive potential, and the first from the first reference voltage terminal is responsive to the third node being at the active potential A reference voltage is delivered to the signal output.
  • a second control circuit configured to pass the first reference from the first reference voltage terminal in response to the first node being at the active potential Transmitting a voltage to a third node to set the third node at an inactive potential, and responsive to a second clock
  • the second control circuit includes: a ninth transistor having a gate and a first electrode each connected to the second clock signal terminal, and a second electrode; a tenth transistor having a connection to the a gate of the second electrode of the ninth transistor, a first electrode connected to the second clock signal terminal, and a second electrode connected to the third node; an eleventh transistor having a connection to the a gate of a node, a first electrode connected to the first reference voltage terminal, and a second electrode connected to the second electrode of the ninth transistor; and a twelfth transistor having a connection to the a gate of a node, a first electrode connected to the first reference voltage terminal, and a second electrode connected to the third node.
  • the second reset circuit includes: a fifth transistor having a gate connected to the third node, a first electrode connected to the first reference voltage terminal, and a signal output connected a second electrode of the terminal; and an eighth transistor having a gate connected to the third node, a first electrode connected to the first reference voltage terminal, and a second electrode connected to the first node.
  • a gate drive circuit includes a plurality of cascaded shift register circuits as described above. Except for the first stage shift register circuit and the last stage shift register circuit, the signal output of each of the shift register circuits is coupled to the adjacent one of the next stage shift register circuits Both the signal input terminal and the reset signal terminal of the adjacent upper stage shift register circuit. The signal output of the first stage shift register circuit is coupled to the signal input of the second stage shift register circuit. The signal output of the last stage shift register circuit is coupled to the reset signal terminal of an adjacent one stage shift register circuit.
  • a display panel including a gate drive circuit as described above.
  • a display device comprising the display panel as described above.
  • a drive for shifting as described above The method of the circuit.
  • the method includes, in a first phase, transmitting the input pulse to the first node to set the first node at the active potential in response to the input pulse from the signal input being active And transmitting the first clock signal from the first clock signal terminal to the signal output in response to the first node being at the active potential; in response to transmitting to the signal in a second phase
  • the first clock signal at the output is active to change the effective potential of the first node further away from the inactive potential, and based on the responsive to the first clock signal being transmitted to the signal output being valid
  • the second reference voltage of the second reference voltage terminal limits a change in the effective potential of the first node, the second reference voltage having a magnitude of the valid first clock signal and the inactive potential Between the values; and in the third stage, the first from the first reference voltage terminal in response to the reset pulse from the reset signal terminal being active Transmitting a voltage to the first node to set the first node at an inactive potential,
  • the method further includes transmitting, in the first and second phases, the first reference voltage from the first reference voltage terminal to the first node at the active potential a third node to set the third node at an inactive potential; and in the third phase, in response to the second clock signal from the second clock signal terminal being active and the first node being at the inactive potential The second clock signal is transmitted to the third node to set the third node to an active potential.
  • the method further includes transmitting, in the third phase, the first reference voltage from the first reference voltage terminal to the third node in response to the third potential being at the active potential Determining a first node to set the first node at an inactive potential, and transmitting the first reference voltage from the first reference voltage terminal to the responsive to the third node being at the active potential Signal output.
  • FIG. 1 is a block diagram of a shift register circuit in accordance with a disclosed embodiment
  • FIG. 2 is an exemplary circuit diagram of the shift register circuit shown in FIG. 1;
  • FIG. 3 is a block diagram of a shift register circuit in accordance with an embodiment of the present disclosure.
  • FIG. 4 is an exemplary circuit diagram of the shift register circuit shown in FIG. 3;
  • Figure 5 is a timing diagram of the shift register circuit shown in Figure 4.
  • FIG. 6 is a block diagram of a gate driving circuit in accordance with an embodiment of the present disclosure.
  • FIG. 7 is a block diagram of a display device in accordance with an embodiment of the present disclosure.
  • FIG. 1 is a block diagram of a shift register circuit 100 in accordance with a disclosed embodiment.
  • the shift register circuit 100 includes a set circuit 110, a first reset circuit 120, a first control circuit 130, and an output circuit 140.
  • the set circuit 110 is connected to the signal input terminal IN and the first node N1.
  • the set circuit 110 is configured to transmit an input pulse to the first node N1 in response to the input pulse from the signal input IN being active to set the first node N1 at an active potential.
  • the first reset circuit 120 is connected to the reset signal terminal RST, the first reference voltage terminal VSS, the first node N1, and the signal output terminal OUT.
  • the first reset circuit 120 is configured to transmit a first reference voltage from the first reference voltage terminal VSS to the first node N1 to set the first node N1 at an inactive potential in response to the reset pulse from the reset signal terminal RST being active.
  • the first reset circuit 120 is further configured to transmit the first reference voltage from the first reference voltage terminal VSS to the signal output terminal OUT in response to the reset pulse from the reset signal terminal RST being active.
  • the output circuit 140 is connected to the first node N1, the first clock signal terminal CLK1, and the signal output terminal OUT.
  • the output circuit 140 is configured to transmit a first clock signal from the first clock signal terminal CLK1 to the signal output terminal OUT in response to the first node N1 being at an active potential.
  • the output circuit 140 is further configured to change the effective potential of the first node N1 further away from the inactive potential in response to the first clock signal transmitted to the signal output terminal OUT being active.
  • the first control circuit 130 is connected to the signal input terminal IN, the second reference voltage terminal VBB, and the first node N1.
  • the first control circuit 130 is configured to maintain the first node N1 at an active potential in response to the input pulse from the signal input IN being active.
  • the first control circuit 130 is further configured to limit the change in the effective potential of the first node N1 based on the second reference voltage from the second reference voltage terminal VBB in response to the first clock signal transmitted to the signal output terminal OUT being active.
  • the second reference voltage has a magnitude between the magnitude of the active first clock signal and the inactive potential.
  • the term "effective potential” as used herein refers to the potential at which the circuit component (eg, transistor) involved is enabled.
  • the term “valid signal” refers to a signal that has an effective potential to enable the circuit components involved.
  • the term “invalid potential” refers to the potential at which the circuit components involved are disabled.
  • the potential of the first node N1 can be limited by means of the first control circuit 130, thereby alleviating or eliminating problems caused by the potential of the first node N1 being too high, Such as changes in the operational characteristics of the circuit elements involved, instability of the output signal of the shift register circuit 100, and the like.
  • FIG. 2 is an exemplary circuit diagram of the shift register circuit 100 shown in FIG. 1. This example circuit is described below with reference to FIGS. 1 and 2.
  • the set circuit 110 includes a sixth transistor T6 having a gate and a first electrode each connected to the signal input terminal IN, and a second electrode connected to the first node N1.
  • the first reset circuit 120 includes a fourth transistor T4 and a seventh transistor T7.
  • the fourth transistor T4 has a gate connected to the reset signal terminal RST, a first electrode connected to the first reference voltage terminal VSS, and a second electrode connected to the signal output terminal OUT.
  • the seventh transistor T7 has a gate connected to the reset signal terminal RST, a first electrode connected to the first reference voltage terminal VSS, and a second electrode connected to the first node N1.
  • the first control circuit 130 includes a first transistor T1, a second transistor T2, and a first capacitor C1.
  • the first transistor T1 has a gate and a first electrode each connected to the signal input terminal IN, and a second electrode connected to the second node N2.
  • the second transistor T2 has a gate connected to the signal output terminal IN, a first electrode connected to the second reference voltage terminal VBB, and a second electrode connected to the second node N2.
  • the first capacitor C1 is connected between the second node N2 and the first node N1.
  • the output circuit 140 includes a third transistor T3 and a second capacitor C2.
  • the third transistor T3 has a gate connected to the first node N1, a first electrode connected to the first clock signal terminal CLK1, and a second electrode connected to the signal output terminal OUT.
  • the second capacitor C2 is connected between the first node N1 and the signal output terminal OUT.
  • the second reference voltage from the second reference voltage terminal VBB has a magnitude that is less than the magnitude of the active input pulse from the signal input terminal IN and greater than the inactive potential (ie, the magnitude of the valid input pulse) Between the dead potential and the). This can prevent the potential of the first node N1 from being pulled up too high when the shift register circuit 100 is operating due to the bootstrap action of the second capacitor. This is due to the following work process. During a period in which the first node N1 is at an active potential (high level in this example), the first clock signal from the first clock signal terminal CLK1 is transmitted to the signal output terminal OUT through the third transistor T3.
  • the second node N2 When the first clock signal transitions from the inactive potential (low level in this example) to the active potential, the second node N2 has been set to the active potential by the effective input pulse from the signal input terminal IN through the second transistor T2. And the potential of the first node N1 will be further pulled up due to the bootstrap action of the second capacitor C2.
  • the second reference from the second reference voltage terminal VBB The voltage is transmitted to the second node N2 through the second transistor T2 such that the potential of the second node N2 is decreased by a certain amount (equal to the difference between the magnitude of the effective input pulse and the magnitude of the second reference voltage). Due to the bootstrap action of the first capacitor C1, the potential of the first node N1 will be pulled low.
  • FIG. 3 is a block diagram of a shift register circuit 100A in accordance with an embodiment of the present disclosure.
  • the shift register circuit 100A further includes a second control circuit 150 and a second reset circuit 160 as compared with the shift register circuit 100 of FIG.
  • the configurations of the set circuit 110, the first reset circuit 120, the first control circuit 130, and the output circuit 140 are the same as those described above with respect to FIGS. 1 and 2, and are not repeated here.
  • the second control circuit 150 is connected to the second clock signal terminal CLK2, the first node N1, the third node N3, and the first reference voltage terminal VSS.
  • the second control circuit 150 is configured to transmit a first reference voltage from the first reference voltage terminal VSS to the third node N3 in response to the first node N1 being at an active potential to set the third node N3 to an inactive potential.
  • the second control circuit 150 is further configured to transmit the second clock signal CLK2 to the third node N3 to transmit the third node in response to the second clock signal from the second clock signal terminal CLK2 being active and the first node N1 being at an inactive potential
  • the N3 setting is at an effective potential.
  • the second reset circuit 160 is connected to the first node N1, the third node N3, the signal output terminal OUT, and the first reference voltage terminal VSS.
  • the second reset circuit 160 is configured to transmit a first reference voltage from the first reference voltage terminal VSS to the first node N1 in response to the third node N3 being at an active potential to set the first node N1 at an inactive potential.
  • the second reset circuit 160 is further configured to transmit the first reference voltage from the first reference voltage terminal VSS to the signal output terminal OUT in response to the third node N3 being at an active potential.
  • FIG. 4 is an exemplary circuit diagram of the shift register circuit 100A shown in FIG. This example circuit is described below with reference to FIGS. 3 and 4.
  • the configurations of the set circuit 110, the first reset circuit 120, the first control circuit 130, and the output circuit 140 are the same as those described above with respect to FIG. 2, and are not repeated here.
  • the second control circuit 150 includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12.
  • the ninth transistor T9 has a gate electrode and a first electrode, both connected to the second clock signal terminal CLK2, and a second electrode.
  • Tenth transistor T10 There is a gate connected to the second electrode of the ninth transistor T9, a first electrode connected to the second clock signal terminal CLK2, and a second electrode connected to the third node N3.
  • the eleventh transistor T11 has a gate connected to the first node N1, a first electrode connected to the first reference voltage terminal VSS, and a second electrode connected to the second electrode of the ninth transistor T9.
  • the twelfth transistor T12 has a gate connected to the first node N1, a first electrode connected to the first reference voltage terminal VSS, and a second electrode connected to the third node N3.
  • the second reset circuit 160 includes a fifth transistor T5 and an eighth transistor T8.
  • the fifth transistor T5 has a gate connected to the third node N3, a first electrode connected to the first reference voltage terminal VSS, and a second electrode connected to the signal output terminal OUT.
  • the eighth transistor T8 has a gate connected to the third node N3, a first electrode connected to the first reference voltage terminal VSS, and a second electrode connected to the first node N1.
  • each transistor is illustrated and described as an N-type transistor, although a P-type transistor is possible.
  • the gate-on voltage has a low level
  • the gate-off voltage has a high level.
  • each transistor can be a thin film transistor that is typically fabricated such that their first and second electrodes are used interchangeably. Other embodiments are also contemplated.
  • the second control circuit 150 and the second reset circuit 160 are operative to cause the first node N1 and the signal output terminal OUT to be more effectively reset by setting the potential of the third node N3.
  • FIG. 5 is a timing chart of the shift register circuit shown in FIG. The operation of the example shift register circuit will be described below with reference to FIGS. 4 and 5.
  • a high level is indicated by 1 and a low level is indicated by 0.
  • the high level of the first clock signal, the second clock signal, the input pulse, the reset pulse, and the output signal is VGH
  • the first reference voltage terminal VSS supplies a low level voltage
  • the second reference voltage terminal VBB is supplied with a quantity The value is the voltage of VGH/2.
  • the first node N1 is set to be at an effective potential such that the third transistor T3, The eleventh transistor T11 and the twelfth transistor T12 are turned on.
  • the turned-on ninth transistor T9 and the eleventh transistor T11 have a resistance voltage division effect, and the ninth transistor T9 and the eleventh transistor T11 are designed such that the equivalent resistance of the ninth transistor T9 is much larger than that of the eleventh transistor T11. Effective resistance.
  • the gate voltage of the tenth transistor T10 is insufficient to turn on the tenth transistor T10.
  • the turned-on twelfth transistor T12 transfers the first reference voltage from the first reference voltage terminal VSS to the third node N3, so that the third node N3 is set to the inactive potential.
  • the turned-on second transistor T2 transfers the second reference voltage from the second reference voltage terminal VBB to the second node N2 such that the potential of the second node N2 drops from VGH to VGH/2.
  • the bootstrap action of the first capacitor C1 limits the rise of the potential of the first node N1 due to the bootstrap action of the second capacitor C2, for example only to 1.5 VGH, rather than 2 VGH. This avoids the problem that the potential of the first node N1 is too high, such as the signal output from the signal output terminal OUT is unstable.
  • the turned-on eleventh transistor T11 transfers the first reference voltage from the first reference voltage terminal VSS to the gate of the tenth transistor T10, thereby turning off the tenth transistor T10.
  • the turned-on tenth transistor T12 transfers the first reference voltage from the first reference voltage terminal VSS to the third node N3 such that the third node N3 is at an inactive potential.
  • the fourth transistor T4 transmits a first reference voltage from the first reference voltage terminal VSS to the signal output terminal OUT such that the signal output terminal OUT outputs a low level signal.
  • the turned-on seventh transistor T7 transfers the first reference voltage from the first reference voltage terminal VSS to the first node N1 to be set to the inactive potential at the first node N1.
  • the turned-on ninth transistor T9 transmits the second clock signal from the second clock signal terminal CLK2 to the tenth transistor T10
  • the gate of the gate causes the tenth transistor T10 to be turned on.
  • the turned-on tenth transistor T10 transmits the second clock signal from the second clock signal terminal CLK2 to the third node N3 to set the third node at an effective potential such that the fifth transistor T5 and the eighth transistor T8 are turned on.
  • the turned-on fifth transistor T5 transmits the first reference voltage from the first reference voltage terminal VSS to the signal output terminal OUT, further ensuring that the signal output terminal OUT outputs a low level signal.
  • the turned-on eighth transistor T8 transfers the first reference voltage from the first reference voltage terminal VSS to the first node N1, further ensuring that the first node N1 is reset to the inactive potential.
  • the stages P1 - P3 as a whole may be repeated at intervals, so that the shift register circuit 100A outputs the gate scan signal at the interval via the signal output terminal OUT.
  • FIG. 6 is a block diagram of a gate drive circuit 600 in accordance with an embodiment of the present disclosure.
  • gate drive circuit 600 includes a plurality of cascaded shift register circuits, each of which may be shift register circuit 100 or 100A as described above with respect to Figures 1-4.
  • the signal output terminal OUT of each of the shift register circuits is connected to the signal input terminal IN of the adjacent next stage shift register circuit. And the reset signal terminal RST of the adjacent upper stage shift register circuit.
  • the signal output terminal OUT of the first stage shift register circuit is connected to the signal input terminal IN of the second stage shift register circuit.
  • the signal output terminal OUT of the last stage shift register circuit is connected to the reset signal terminal RST of the adjacent upper stage shift register circuit.
  • shift registers For convenience of explanation, only four shift registers are shown in FIG. 6, that is, the n-1th stage shift register, the nth stage shift register, the n+1th stage shift register, and the n+2th shift.
  • a register that outputs gate scan signals G[n-1], G[n], G[n+1], and G[n+2], respectively.
  • FIG. 7 is a block diagram of a display device 700 in accordance with an embodiment of the present disclosure.
  • the display device 700 includes a display panel 710, a timing controller 720, a gate driving circuit 730, and a data driving circuit 740.
  • the gate drive circuit 730 can be the gate drive circuit 600 described above with respect to FIG.
  • the display panel 710 is connected to the plurality of gate lines GL and the plurality of data lines DL.
  • the display panel 710 displays an image having a plurality of gradations based on the output image data RGBD'.
  • the gate line GL may extend in the first direction D1
  • the data line DL may extend in the second direction D2 crossing (eg, substantially perpendicular) to the first direction D1.
  • the display panel 710 may include a plurality of pixels (not shown) arranged in a matrix form. Each of the pixels may be electrically connected to a corresponding one of the gate lines GL and one corresponding one of the data lines DL.
  • Display panel 710 can be a liquid crystal display panel, an organic light emitting diode (OLED) display panel, or other suitable type of display panel.
  • OLED organic light emitting diode
  • the timing controller 720 controls the operations of the display panel 710, the gate drive circuit 730, and the data drive circuit 740.
  • the timing controller 720 receives input image data RGBD and an input control signal CONT from an external device (eg, a host).
  • the input image data RGBD may include a plurality of input pixel data for a plurality of pixels. Each of the input pixel data may include red gradation data R, green gradation data G, and blue gradation data B for a corresponding one of the plurality of pixels.
  • the input control signal CONT may include a main clock signal, a data enable signal, a vertical sync signal, a horizontal sync signal, and the like.
  • the timing controller 720 generates output image data RGBD', a first control signal CONT1, and a second control signal CONT2 based on the input image data RGBD and the input control signal CONT.
  • the gate drive circuit 730 receives the first control signal CONT1 from the timing controller 720.
  • the gate driving circuit 730 generates a plurality of gate signals for driving the gate lines GL based on the first control signal CONT1.
  • the gate driving circuit 730 may sequentially apply a plurality of gate signals to the gate lines GL.
  • the data driving circuit 740 receives the second control signal CONT2 and the output image data RGBD' from the timing controller 720.
  • the data driving circuit 740 generates a plurality of data voltages (e.g., analog data voltages) based on the second control signal CONT2 and the output image data RGBD' (e.g., digital image data).
  • the data driving circuit 740 can apply a plurality of data voltages to the data lines DL.
  • gate drive circuit 730 and/or data drive circuit 740 may be disposed (eg, directly mounted) on display panel 710, or may be by, for example, a Tape Carrier Package (TCP). Connected to display panel 710. In some embodiments, gate drive circuit 730 and/or data drive circuit 740 can be integrated in display panel 710.
  • TCP Tape Carrier Package
  • Examples of display device 700 include, but are not limited to, cell phones, tablets, televisions, displays, notebook computers, digital photo frames, navigators.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)

Abstract

一种移位寄存器电路，其包括置位电路(110)、第一复位电路(120)、第一控制电路(130)以及输出电路(140)。输出电路(140)被配置成响应于传送到信号输出端(OUT)的第一时钟信号(CLK1)有效而改变第一节点(N1)的有效电位进一步远离无效电位，并且第一控制电路(130)还被配置成响应于传送到信号输出端(OUT)的第一时钟信号(CLK1)有效而基于来自第二参考电压端(VBB)的第二参考电压限制第一节点(N1)的有效电位的改变，第二参考电压具有介于有效的输入脉冲的量值与无效电位之间的量值。

Description

移位寄存器电路及其驱动方法、栅极驱动电路、显示面板和显示装置
相关申请的交叉引用
本PCT申请要求2017年1月5日提交的中国专利申请号201710008154.9的权益，其全部公开内容通过引用合并于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器电路及其驱动方法、栅极驱动电路、显示面板和显示装置。
背景技术
移位寄存器可以操作为显示装置的栅极驱动电路以便向各栅线顺序地提供栅极扫描信号以开启各像素行中的晶体管，从而允许向各像素写入数据信号。
为了能够充分打开各晶体管，栅极扫描信号的高电平一般需要达到25V以上。由于移位寄存器中的存储电容的自举作用(self-boosting effect)，移位寄存器的某些内部节点处的电位甚至会更高，例如高出栅极扫描信号的高电平一倍(50V以上)。如此高的电位导致与这些内部节点相连的晶体管的特性发生较大的变化，产生阈值电压漂移。若显示装置在此种条件下长时间工作，移位寄存器会变得不稳定，得到恶化的栅极扫描信号。
发明内容
有利的是提供一种可以缓解、减轻或消除上述问题中的一个或多个的移位寄存器电路。
根据本公开的一个方面，提供了一种移位寄存器电路，包括：置位电路，被配置成响应于来自信号输入端的输入脉冲有效而将所述输入脉冲传送到第一节点以将所述第一节点设定处于有效电位；第一复位电路，被配置成响应于来自复位信号端的复位脉冲有效而将来自第一参考电压端的第一参考电压传送到所述第一节点以将所述第一节点设定处于无效电位，并且响应于来自复位信号端的复位脉冲有效而将 来自所述第一参考电压端的所述第一参考电压传送到信号输出端；输出电路，被配置成响应于所述第一节点处于所述有效电位而将来自第一时钟信号端的第一时钟信号传送到所述信号输出端，并且响应于传送到所述信号输出端的所述第一时钟信号有效而改变所述第一节点的所述有效电位进一步远离所述无效电位；以及第一控制电路，被配置成响应于来自所述信号输入端的所述输入脉冲有效而维持所述第一节点处于所述有效电位，并且响应于传送到所述信号输出端的所述第一时钟信号有效而基于来自第二参考电压端的第二参考电压限制所述第一节点的所述有效电位的改变，所述第二参考电压具有介于该有效的输入脉冲的量值与所述无效电位之间的量值。
在一些实施例中，所述第一控制电路包括：第一晶体管，具有均连接到所述信号输入端的栅极和第一电极、以及连接到第二节点的第二电极；第二晶体管，具有连接到所述信号输出端的栅极、连接到所述第二参考电压端的第一电极、以及连接到所述第二节点的第二电极；以及第一电容，连接于所述第二节点和所述第一节点之间。
在一些实施例中，所述输出电路包括：第三晶体管，具有连接到所述第一节点的栅极、连接到所述第一时钟信号端的第一电极、以及连接到所述信号输出端的第二电极；以及第二电容，连接于所述第一节点与所述信号输出端之间。
在一些实施例中，所述第一复位电路包括：第四晶体管，具有连接到所述复位信号端的栅极、连接到所述第一参考电压端的第一电极、以及连接到所述信号输出端的第二电极；以及第七晶体管，具有连接到所述复位信号端的栅极、连接到所述第一参考电压端的第一电极、以及连接到所述第一节点的第二电极。
在一些实施例中，所述置位电路包括第六晶体管，其具有均连接到所述信号输入端的栅极和第一电极、以及连接到所述第一节点的第二电极。
在一些实施例中，所述移位寄存器电路还包括：第二控制电路，被配置成响应于所述第一节点处于所述有效电位而将来自所述第一参考电压端的所述第一参考电压传送到第三节点以将所述第三节点设定处于无效电位，并且响应于来自第二时钟信号端的第二时钟信号有效且所述第一节点处于所述无效电位而将所述第二时钟信号传送到所述 第三节点以将所述第三节点设定处于有效电位；以及第二复位电路，被配置成响应于所述第三节点处于所述有效电位而将来自所述第一参考电压端的所述第一参考电压传送到所述第一节点以将所述第一节点设定处于无效电位，并且响应于所述第三节点处于所述有效电位而将来自所述第一参考电压端的所述第一参考电压传送到所述信号输出端。
在一些实施例中，所述第二控制电路包括：第九晶体管，具有均连接到所述第二时钟信号端的栅极和第一电极、以及第二电极；第十晶体管，具有连接到所述第九晶体管的所述第二电极的栅极、连接到所述第二时钟信号端的第一电极、以及连接到所述第三节点的第二电极；第十一晶体管，具有连接到所述第一节点的栅极、连接到所述第一参考电压端的第一电极、以及连接到所述第九晶体管的所述第二电极的第二电极；以及第十二晶体管，具有连接到所述第一节点的栅极、连接到所述第一参考电压端的第一电极、以及连接到所述第三节点的第二电极。
在一些实施例中，所述第二复位电路包括：第五晶体管，具有连接到所述第三节点的栅极、连接到所述第一参考电压端的第一电极、以及连接到所述信号输出端的第二电极；以及第八晶体管，具有连接到所述第三节点的栅极、连接到所述第一参考电压端的第一电极、以及连接到所述第一节点的第二电极。
根据本公开的另一方面，提供了一种栅极驱动电路，包括级联的多个如上所述的移位寄存器电路。除第一级移位寄存器电路和最后一级移位寄存器电路之外，所述移位寄存器电路中的每一个的所述信号输出端连接到相邻的下一级移位寄存器电路的所述信号输入端和相邻的上一级移位寄存器电路的所述复位信号端两者。第一级移位寄存器电路的所述信号输出端连接到第二级移位寄存器电路的所述信号输入端。最后一级移位寄存器电路的所述信号输出端连接到相邻的上一级移位寄存器电路的所述复位信号端。
根据本公开的另一方面，提供了一种显示面板，包括如上所述的栅极驱动电路。
根据本公开的另一方面，提供了一种显示装置，包括如上所述的显示面板。
根据本公开的又另一方面，提供了一种驱动如上所述的移位寄存 器电路的方法。所述方法包括：在第一阶段，响应于来自所述信号输入端的所述输入脉冲有效而将所述输入脉冲传送到所述第一节点以将所述第一节点设定处于所述有效电位，并且响应于所述第一节点处于所述有效电位而将来自所述第一时钟信号端的所述第一时钟信号传送到所述信号输出端；在第二阶段，响应于传送到所述信号输出端的所述第一时钟信号有效而改变所述第一节点的所述有效电位进一步远离所述无效电位，并且响应于传送到所述信号输出端的所述第一时钟信号有效而基于来自所述第二参考电压端的所述第二参考电压限制所述第一节点的所述有效电位的改变，所述第二参考电压具有介于该有效的第一时钟信号的量值与所述无效电位之间的量值；以及在第三阶段，响应于来自所述复位信号端的所述复位脉冲有效而将来自所述第一参考电压端的所述第一参考电压传送到所述第一节点以将所述第一节点设定处于无效电位，并且响应于来自所述复位信号端的所述复位脉冲有效而将来自所述第一参考电压端的所述第一参考电压传送到所述信号输出端。
在一些实施例中，所述方法还包括：在第一和第二阶段，响应于所述第一节点处于所述有效电位而将来自所述第一参考电压端的所述第一参考电压传送到第三节点以将所述第三节点设定处于无效电位；并且在所述第三阶段，响应于来自第二时钟信号端的第二时钟信号有效且所述第一节点处于所述无效电位而将所述第二时钟信号传送到所述第三节点以将所述第三节点设定处于有效电位。
在一些实施例中，所述方法还包括：在所述第三阶段，响应于所述第三节点处于所述有效电位而将来自所述第一参考电压端的所述第一参考电压传送到所述第一节点以将所述第一节点设定处于无效电位，并且响应于所述第三节点处于所述有效电位而将来自所述第一参考电压端的所述第一参考电压传送到所述信号输出端。
根据在下文中所描述的实施例，本公开的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
图1为根据公开实施例的移位寄存器电路的框图；
图2为图1所示的移位寄存器电路的示例性电路图；
图3为根据本公开实施例的移位寄存器电路的框图；
图4为图3所示的移位寄存器电路的示例性电路图；
图5为图4所示的移位寄存器电路的时序图；
图6为根据本公开实施例的栅极驱动电路的框图；并且
图7为根据本公开实施例的显示装置的框图。
具体实施方式
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件和/或部分，但是这些元件、部件和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件或部分与另一个元件、部件或部分相区分。因此，下面讨论的第一元件、部件或部分可以被称为第二元件、部件或部分而不偏离本公开的教导。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件被称为“连接到另一个元件”或“耦合到另一个元件”时，其可以直接连接到另一个元件或直接耦合到另一个元件，或者可以存在中间元件或层。相反，当元件被称为“直接连接到另一个元件”或“直接耦合到另一个元件”时，没有中间元件或层存在。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
下面将结合附图对本公开的实施例进行详细地描述。
图1为根据公开实施例的移位寄存器电路100的框图。参考图1，移位寄存器电路100包括置位电路110、第一复位电路120、第一控制电路130和输出电路140。
置位电路110连接到信号输入端IN和第一节点N1。置位电路110被配置成响应于来自信号输入端IN的输入脉冲有效而将输入脉冲传送到第一节点N1以将第一节点N1设定处于有效电位。
第一复位电路120连接到复位信号端RST、第一参考电压端VSS、第一节点N1和信号输出端OUT。第一复位电路120被配置成响应于来自复位信号端RST的复位脉冲有效而将来自第一参考电压端VSS的第一参考电压传送到第一节点N1以将第一节点N1设定处于无效电位。第一复位电路120还被配置成响应于来自复位信号端RST的复位脉冲有效而将来自第一参考电压端VSS的第一参考电压传送到信号输出端OUT。
输出电路140连接到第一节点N1、第一时钟信号端CLK1和信号输出端OUT。输出电路140被配置成响应于第一节点N1处于有效电位而将来自第一时钟信号端CLK1的第一时钟信号传送到信号输出端OUT。输出电路140还被配置成响应于传送到信号输出端OUT的第一时钟信号有效而改变第一节点N1的有效电位进一步远离无效电位。
第一控制电路130连接到信号输入端IN、第二参考电压端VBB和第一节点N1。第一控制电路130被配置成响应于来自信号输入端IN的输入脉冲有效而维持第一节点N1处于有效电位。第一控制电路130还被配置成响应于传送到信号输出端OUT的第一时钟信号有效而基于来自第二参考电压端VBB的第二参考电压限制第一节点N1的所述有效电位的改变。如下面将描述的，第二参考电压具有介于有效的第一时钟信号的量值与无效电位之间的量值。
如本文使用的术语“有效电位”是指所涉及的电路元件(例如，晶体管)被启用所处的电位。类似地，术语“有效信号”是指具有有效电位以启用所涉及的电路元件的信号。相反，术语“无效电位”是指所涉及的电路元件被禁用所处的电位。
在该实施例中，第一节点N1的电位可以借助于第一控制电路130而被限制，从而缓解或消除由于第一节点N1的电位过高而造成的问题， 诸如所涉及的电路元件的工作特性改变、移位寄存器电路100的输出信号的不稳定等等。
图2为图1所示的移位寄存器电路100的示例性电路图。下面参考图1和2描述该示例电路。
置位电路110包括第六晶体管T6，其具有均连接到信号输入端IN的栅极和第一电极、以及连接到第一节点N1的第二电极。
第一复位电路120包括第四晶体管T4和第七晶体管T7。第四晶体管T4具有连接到复位信号端RST的栅极、连接到第一参考电压端VSS的第一电极、以及连接到信号输出端OUT的第二电极。第七晶体管T7具有连接到复位信号端RST的栅极、连接到第一参考电压端VSS的第一电极、以及连接到第一节点N1的第二电极。
第一控制电路130包括第一晶体管T1、第二晶体管T2和第一电容C1。第一晶体管T1具有均连接到信号输入端IN的栅极和第一电极、以及连接到第二节点N2的第二电极。第二晶体管T2具有连接到信号输出端IN的栅极、连接到第二参考电压端VBB的第一电极、以及连接到第二节点N2的第二电极。第一电容C1连接于第二节点N2和第一节点N1之间。
输出电路140包括第三晶体管T3和第二电容C2。第三晶体管T3具有连接到第一节点N1的栅极、连接到第一时钟信号端CLK1的第一电极、以及连接到信号输出端OUT的第二电极。第二电容C2连接于第一节点N1与信号输出端OUT之间。
在该示例电路中，来自第二参考电压端VBB的第二参考电压具有小于来自信号输入端IN的有效输入脉冲的量值且大于无效电位的量值(即，介于有效输入脉冲的量值与无效电位之间)。这可以防止第一节点N1的电位当移位寄存器电路100在操作时由于第二电容的自举作用被拉升过高。这归因于以下工作过程。在第一节点N1处于有效电位(在该示例中，高电平)的时间段期间，来自第一时钟信号端CLK1的第一时钟信号通过第三晶体管T3被传送到信号输出端OUT。当第一时钟信号从无效电位(在该示例中，低电平)跳变至有效电位时，第二节点N2已经由来自信号输入端IN的有效输入脉冲通过第二晶体管T2设定处于有效电位，并且第一节点N1的电位由于第二电容C2的自举作用将被进一步拉高。同时，来自第二参考电压端VBB的第二参考 电压通过第二晶体管T2被传送至第二节点N2，使得第二节点N2的电位降低一定的量(等于有效输入脉冲的量值与第二参考电压的量值的差)。由于第一电容C1的自举作用，第一节点N1的电位将被拉低。第一电容C1的自举和第二电容C2的自举之间的折中导致第一节点N1的电位不被增加否则在没有第一控制电路130的情况下本应具有的量。以这种方式，移位寄存器电路100的内部节点N1的电位在操作中被限制。
图3为根据本公开实施例的移位寄存器电路100A的框图。参考图3，与图1的移位寄存器电路100相比，移位寄存器电路100A还包括第二控制电路150和第二复位电路160。置位电路110、第一复位电路120、第一控制电路130和输出电路140的配置与上面关于图1和2描述的那些相同，并且在此不再重复。
第二控制电路150连接到第二时钟信号端CLK2、第一节点N1、第三节点N3和第一参考电压端VSS。第二控制电路150被配置成响应于第一节点N1处于有效电位而将来自第一参考电压端VSS的第一参考电压传送到第三节点N3以将第三节点N3设定处于无效电位。第二控制电路150还被配置成响应于来自第二时钟信号端CLK2的第二时钟信号有效且第一节点N1处于无效电位而将第二时钟信号CLK2传送到第三节点N3以将第三节点N3设定处于有效电位。
第二复位电路160连接到第一节点N1、第三节点N3、信号输出端OUT和第一参考电压端VSS。第二复位电路160被配置成响应于第三节点N3处于有效电位而将来自第一参考电压端VSS的第一参考电压传送到第一节点N1以将第一节点N1设定处于无效电位。第二复位电路160还被配置成响应于第三节点N3处于有效电位而将来自第一参考电压端VSS的第一参考电压传送到信号输出端OUT。
图4为图3所示的移位寄存器电路100A的示例性电路图。下面参考图3和4描述该示例电路。置位电路110、第一复位电路120、第一控制电路130和输出电路140的配置与上面关于图2描述的那些相同，并且在此不再重复。
第二控制电路150包括第九晶体管T9、第十晶体管T10、第十一晶体管T11和第十二晶体管T12。第九晶体管T9具有均连接到第二时钟信号端CLK2的栅极和第一电极、以及第二电极。第十晶体管T10 具有连接到第九晶体管T9的第二电极的栅极、连接到第二时钟信号端CLK2的第一电极、以及连接到第三节点N3的第二电极。第十一晶体管T11具有连接到第一节点N1的栅极、连接到第一参考电压端VSS的第一电极、以及连接到第九晶体管T9的第二电极的第二电极。第十二晶体管T12具有连接到第一节点N1的栅极、连接到第一参考电压端VSS的第一电极、以及连接到第三节点N3的第二电极。
第二复位电路160包括第五晶体管T5和第八晶体管T8。第五晶体管T5具有连接到第三节点N3的栅极、连接到第一参考电压端VSS的第一电极、以及连接到信号输出端OUT的第二电极。第八晶体管T8具有连接到第三节点N3的栅极、连接到第一参考电压端VSS的第一电极、以及连接到第一节点N1的第二电极。
在各实施例中，各晶体管被图示和描述为N型晶体管，尽管P型晶体管是可能的。在P型晶体管的情况下，栅极开启电压具有低电平，并且栅极关闭电压具有高电平。在各实施例中，各晶体管可以是薄膜晶体管，其典型地被制作使得它们的第一电极和第二电极可互换地使用。还设想了其他实施例。
如下面将描述的，第二控制电路150和第二复位电路160操作用于通过设定第三节点N3的电位而使第一节点N1和信号输出端OUT被更有效地复位。
图5为图4所示的移位寄存器电路的时序图。下面参考图4和5描述该示例移位寄存器电路的操作。在以下描述中，以1表示高电平，并且以0表示低电平。还假定：第一时钟信号、第二时钟信号、输入脉冲、复位脉冲和输出信号的高电平为VGH，第一参考电压端VSS供应低电平电压，并且第二参考电压端VBB供应具有量值为VGH/2的电压。
在P1阶段，IN＝1，CLK2＝1，CLK1＝0，RST＝0。由于IN＝1并且CLK2＝1，因此第六晶体管T6、第九晶体管T9和第一晶体管T1导通。导通的第一晶体管T1将来自信号输入端IN的有效输入脉冲传送到第二节点N2以将第二节点设定处于有效电位，并且导通的第六晶体管T6将来自信号输入端IN的有效输入脉冲传送到第一节点N1以将第一节点设定处于有效电位。第一电容C1维持第一节点N1与第二节点N2之间的电压。第一节点N1被设定处于有效电位，使得第三晶体管T3、 第十一晶体管T11和第十二晶体管T12导通。导通的第三晶体管T3将来自第一时钟信号端CLK1的第一时钟信号传送到信号输出端OUT。由于此阶段CLK1＝0，因此信号输出端OUT输出低电平信号，使得第二晶体管T2关闭。导通的第九晶体管T9和第十一晶体管T11具有电阻分压效应，并且第九晶体管T9和第十一晶体管T11被设计使得第九晶体管T9的等效电阻远大于第十一晶体管T11的等效电阻。因此，第十晶体管T10的栅极电压不足以开启第十晶体管T10。这样，导通的第十二晶体管T12将来自第一参考电压端VSS的第一参考电压传送到第三节点N3，使得第三节点N3被设定处于无效电位。
在P2阶段，IN＝0，CLK2＝0，CLK1＝1，RST＝0。由于IN＝0并且CLK2＝0，因此第六晶体管T6、第九晶体管T9和第一晶体管T1关闭。由于CLK1＝1，第二电容C2的自举作用使得第一节点N1的电位进一步升高，使得第三晶体管T3、第十一晶体管T11和第十二晶体管T12保持导通状态。导通的第三晶体管T3将来自第一时钟信号端CLK1的第一时钟信号传送到信号输出端OUT。由于此阶段CLK1＝1，因此信号输出端OUT输出高电平信号，使得第二晶体管T2导通。导通的第二晶体管T2将来自第二参考电压端VBB的第二参考电压传送到第二节点N2，使得第二节点N2的电位从VGH下降到VGH/2。第一电容C1的自举作用限制第一节点N1的电位由于第二电容C2的自举作用引起的升高，例如仅仅升高到1.5VGH，而不是2VGH。这避免了第一节点N1的电位过高的问题，诸如信号输出端OUT输出的信号不稳定。另外，导通的第十一晶体管T11将来自第一参考电压端VSS的第一参考电压传送到第十晶体管T10的栅极，从而关闭第十晶体管T10。导通的第十二晶体管T12将来自第一参考电压端VSS的第一参考电压传送到第三节点N3，使得第三节点N3处于无效电位。
在P3阶段，IN＝0，CLK2＝1，CLK1＝0，RST＝1。由于CLK2＝1并且RST＝1，因此第四晶体管T4、第七晶体管T7和第九晶体管T9导通。导通的第四晶体管T4将来自第一参考电压端VSS的第一参考电压传送到信号输出端OUT，使得信号输出端OUT输出低电平信号。导通的第七晶体管T7将来自第一参考电压端VSS的第一参考电压传送到第一节点N1以第一节点N1设定处于无效电位。导通的第九晶体管T9将来自第二时钟信号端CLK2的第二时钟信号传送到第十晶体管T10 的栅极，使得第十晶体管T10导通。导通的第十晶体管T10将来自第二时钟信号端CLK2的第二时钟信号传送到第三节点N3以将第三节点设定处于有效电位，使得第五晶体管T5和第八晶体管T8导通。导通的第五晶体管T5将来自第一参考电压端VSS的第一参考电压传送到信号输出端OUT，进一步保证信号输出端OUT输出低电平信号。导通的第八晶体管T8将来自第一参考电压端VSS的第一参考电压传送到第一节点N1，进一步保证第一节点N1被复位到无效电位。
阶段P1-P3作为整体可以以一定的间隔重复，使得移位寄存器电路100A经由信号输出端OUT以该间隔输出栅极扫描信号。
图6为根据本公开实施例的栅极驱动电路600的框图。参考图6，栅极驱动电路600包括级联的多个移位寄存器电路，其每一个可以是上面关于图1-4描述的移位寄存器电路100或100A。
除第一级移位寄存器电路和最后一级移位寄存器电路之外，各移位寄存器电路中的每一个的信号输出端OUT连接到相邻的下一级移位寄存器电路的信号输入端IN和相邻的上一级移位寄存器电路的复位信号端RST两者。第一级移位寄存器电路的信号输出端OUT连接到第二级移位寄存器电路的信号输入端IN。最后一级移位寄存器电路的信号输出端OUT连接到相邻的上一级移位寄存器电路的复位信号端RST。
为了方便说明，图6中仅示出了四个移位寄存器，即第n-1级移位寄存器、第n级移位寄存器、第n+1级移位寄存器和第n+2级移位寄存器，其分别输出栅极扫描信号G[n-1]、G[n]、G[n+1]和G[n+2]。
图7为根据本公开实施例的显示装置700的框图。参考图7，显示装置700包括显示面板710、时序控制器720、栅极驱动电路730和数据驱动电路740。栅极驱动电路730可以是上面关于图6所述的栅极驱动电路600。
显示面板710连接至多个栅极线GL和多个数据线DL。显示面板710基于输出图像数据RGBD’显示具有多个灰度的图像。栅极线GL可在第一方向D1延伸，并且数据线DL可在与第一方向D1交叉(例如，基本垂直)的第二方向D2延伸。显示面板710可包括以矩阵形式排列的多个像素(未示出)。每个像素可电连接至栅极线GL的对应一个栅极线和数据线DL的对应一个数据线。显示面板710可以是液晶显示面板、有机发光二极管(OLED)显示面板或其他合适类型的显示面板。
时序控制器720控制显示面板710、栅极驱动电路730和数据驱动电路740的操作。时序控制器720从外部设备(例如，主机)接收输入图像数据RGBD和输入控制信号CONT。输入图像数据RGBD可包括用于多个像素的多个输入像素数据。每个输入像素数据可包括用于多个像素中的对应一个的红色灰度数据R、绿色灰度数据G和蓝色灰度数据B。输入控制信号CONT可包括主时钟信号、数据使能信号、垂直同步信号、水平同步信号等。时序控制器720基于输入图像数据RGBD和输入控制信号CONT生成输出图像数据RGBD’、第一控制信号CONT1和第二控制信号CONT2。
栅极驱动电路730从时序控制器720接收第一控制信号CONT1。栅极驱动电路730基于第一控制信号CONT1生成用于驱动栅极线GL的多个栅极信号。栅极驱动电路730可顺序地将多个栅极信号施加至栅极线GL。
数据驱动电路740从时序控制器720接收第二控制信号CONT2和输出图像数据RGBD’。数据驱动电路740基于第二控制信号CONT2和输出图像数据RGBD’(例如，数字图像数据)生成多个数据电压(例如，模拟数据电压)。数据驱动电路740可将多个数据电压施加至数据线DL。
在一些示例性实施例中，栅极驱动电路730和/或数据驱动电路740可被设置(例如，直接安装)在显示面板710上，或者可以借助例如带式载体封装(Tape Carrier Package，TCP)连接至显示面板710。在一些实施例中，栅极驱动电路730和/或数据驱动电路740可被集成在显示面板710中。
显示装置700的示例包括但不限于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (14)

  1. 一种移位寄存器电路，包括：
    置位电路，被配置成响应于来自信号输入端的输入脉冲有效而将所述输入脉冲传送到第一节点以将所述第一节点设定处于有效电位；
    第一复位电路，被配置成响应于来自复位信号端的复位脉冲有效而将来自第一参考电压端的第一参考电压传送到所述第一节点以将所述第一节点设定处于无效电位，并且响应于来自复位信号端的复位脉冲有效而将来自所述第一参考电压端的所述第一参考电压传送到信号输出端；
    输出电路，被配置成响应于所述第一节点处于所述有效电位而将来自第一时钟信号端的第一时钟信号传送到所述信号输出端，并且响应于传送到所述信号输出端的所述第一时钟信号有效而改变所述第一节点的所述有效电位进一步远离所述无效电位；以及
    第一控制电路，被配置成响应于来自所述信号输入端的所述输入脉冲有效而维持所述第一节点处于所述有效电位，并且响应于传送到所述信号输出端的所述第一时钟信号有效而基于来自第二参考电压端的第二参考电压限制所述第一节点的所述有效电位的改变，所述第二参考电压具有介于该有效的输入脉冲的量值与所述无效电位之间的量值。
  2. 如权利要求1所述的移位寄存器电路，其中所述第一控制电路包括：
    第一晶体管，具有均连接到所述信号输入端的栅极和第一电极、以及连接到第二节点的第二电极；
    第二晶体管，具有连接到所述信号输出端的栅极、连接到所述第二参考电压端的第一电极、以及连接到所述第二节点的第二电极；以及
    第一电容，连接于所述第二节点和所述第一节点之间。
  3. 如权利要求1所述的移位寄存器电路，其中所述输出电路包括：
    第三晶体管，具有连接到所述第一节点的栅极、连接到所述第一时钟信号端的第一电极、以及连接到所述信号输出端的第二电极；以及
    第二电容，连接于所述第一节点与所述信号输出端之间。
  4. 如权利要求1所述的移位寄存器电路，其中所述第一复位电路包括：
    第四晶体管，具有连接到所述复位信号端的栅极、连接到所述第一参考电压端的第一电极、以及连接到所述信号输出端的第二电极；以及
    第七晶体管，具有连接到所述复位信号端的栅极、连接到所述第一参考电压端的第一电极、以及连接到所述第一节点的第二电极。
  5. 如权利要求1所述的移位寄存器电路，其中所述置位电路包括第六晶体管，其具有均连接到所述信号输入端的栅极和第一电极、以及连接到所述第一节点的第二电极。
  6. 如权利要求1-5任一项所述的移位寄存器电路，还包括：
    第二控制电路，被配置成响应于所述第一节点处于所述有效电位而将来自所述第一参考电压端的所述第一参考电压传送到第三节点以将所述第三节点设定处于无效电位，并且响应于来自第二时钟信号端的第二时钟信号有效且所述第一节点处于所述无效电位而将所述第二时钟信号传送到所述第三节点以将所述第三节点设定处于有效电位；以及
    第二复位电路，被配置成响应于所述第三节点处于所述有效电位而将来自所述第一参考电压端的所述第一参考电压传送到所述第一节点以将所述第一节点设定处于无效电位，并且响应于所述第三节点处于所述有效电位而将来自所述第一参考电压端的所述第一参考电压传送到所述信号输出端。
  7. 如权利要求6所述的移位寄存器电路，其中所述第二控制电路包括：
    第九晶体管，具有均连接到所述第二时钟信号端的栅极和第一电极、以及第二电极；
    第十晶体管，具有连接到所述第九晶体管的所述第二电极的栅极、连接到所述第二时钟信号端的第一电极、以及连接到所述第三节点的第二电极；
    第十一晶体管，具有连接到所述第一节点的栅极、连接到所述第一参考电压端的第一电极、以及连接到所述第九晶体管的所述第二电 极的第二电极；以及
    第十二晶体管，具有连接到所述第一节点的栅极、连接到所述第一参考电压端的第一电极、以及连接到所述第三节点的第二电极。
  8. 如权利要求6所述的移位寄存器电路，其中所述第二复位电路包括：
    第五晶体管，具有连接到所述第三节点的栅极、连接到所述第一参考电压端的第一电极、以及连接到所述信号输出端的第二电极；以及
    第八晶体管，具有连接到所述第三节点的栅极、连接到所述第一参考电压端的第一电极、以及连接到所述第一节点的第二电极。
  9. 一种栅极驱动电路，包括级联的多个如权利要求1-8任一项所述的移位寄存器电路，其中：
    除第一级移位寄存器电路和最后一级移位寄存器电路之外，所述移位寄存器电路中的每一个的所述信号输出端连接到相邻的下一级移位寄存器电路的所述信号输入端和相邻的上一级移位寄存器电路的所述复位信号端两者；
    第一级移位寄存器电路的所述信号输出端连接到第二级移位寄存器电路的所述信号输入端；并且
    最后一级移位寄存器电路的所述信号输出端连接到相邻的上一级移位寄存器电路的所述复位信号端。
  10. 一种显示面板，包括如权利要求9所述的栅极驱动电路。
  11. 一种显示装置，包括如权利要求10所述的显示面板。
  12. 一种驱动如权利要求1-8任一项所述的移位寄存器电路的方法，所述方法包括：
    在第一阶段，响应于来自所述信号输入端的所述输入脉冲有效而将所述输入脉冲传送到所述第一节点以将所述第一节点设定处于所述有效电位，并且响应于所述第一节点处于所述有效电位而将来自所述第一时钟信号端的所述第一时钟信号传送到所述信号输出端；
    在第二阶段，响应于传送到所述信号输出端的所述第一时钟信号有效而改变所述第一节点的所述有效电位进一步远离所述无效电位，并且响应于传送到所述信号输出端的所述第一时钟信号有效而基于来自所述第二参考电压端的所述第二参考电压限制所述第一节点的所述 有效电位的改变，所述第二参考电压具有介于该有效的第一时钟信号的量值与所述无效电位之间的量值；以及
    在第三阶段，响应于来自所述复位信号端的所述复位脉冲有效而将来自所述第一参考电压端的所述第一参考电压传送到所述第一节点以将所述第一节点设定处于无效电位，并且响应于来自所述复位信号端的所述复位脉冲有效而将来自所述第一参考电压端的所述第一参考电压传送到所述信号输出端。
  13. 如权利要求12所述的方法，还包括：
    在第一和第二阶段，响应于所述第一节点处于所述有效电位而将来自所述第一参考电压端的所述第一参考电压传送到第三节点以将所述第三节点设定处于无效电位；并且
    在所述第三阶段，响应于来自第二时钟信号端的第二时钟信号有效且所述第一节点处于所述无效电位而将所述第二时钟信号传送到所述第三节点以将所述第三节点设定处于有效电位。
  14. 如权利要求13所述的方法，还包括：
    在所述第三阶段，响应于所述第三节点处于所述有效电位而将来自所述第一参考电压端的所述第一参考电压传送到所述第一节点以将所述第一节点设定处于无效电位，并且响应于所述第三节点处于所述有效电位而将来自所述第一参考电压端的所述第一参考电压传送到所述信号输出端。
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