WO2023077772A1 - Solar cell and preparation method therefor - Google Patents

Solar cell and preparation method therefor Download PDF

Info

Publication number
WO2023077772A1
WO2023077772A1 PCT/CN2022/093351 CN2022093351W WO2023077772A1 WO 2023077772 A1 WO2023077772 A1 WO 2023077772A1 CN 2022093351 W CN2022093351 W CN 2022093351W WO 2023077772 A1 WO2023077772 A1 WO 2023077772A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
silicon substrate
electrode
type silicon
silicon
Prior art date
Application number
PCT/CN2022/093351
Other languages
French (fr)
Chinese (zh)
Inventor
张东威
Original Assignee
西安隆基乐叶光伏科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202111314179.4A external-priority patent/CN114256381B/en
Priority claimed from CN202111648529.0A external-priority patent/CN114388633A/en
Application filed by 西安隆基乐叶光伏科技有限公司 filed Critical 西安隆基乐叶光伏科技有限公司
Publication of WO2023077772A1 publication Critical patent/WO2023077772A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
    • H01L31/0288—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention generally relates to the technical field of solar cells, in particular to a solar cell and a preparation method thereof.
  • Perc battery benefits from the development of alumina passivation technology, which greatly reduces the recombination of the back surface of the battery, and is currently the mainstream battery product in the photovoltaic market. With the upgrading of process and equipment technology, the efficiency improvement of Perc battery has encountered a bottleneck.
  • a solar cell provided by an embodiment of the present application includes: a P-type silicon substrate, the P-type silicon substrate has a front side and a back side, the back side is a smooth structure, and the back side is sequentially provided with tunneling silicon oxide from top to bottom layer, a phosphorus-doped polysilicon layer, a first passivation layer and a back electrode, and the back electrode is in contact with the phosphorus-doped polysilicon layer;
  • the front is a suede structure, and the front is provided with a second passivation layer and a front electrode in sequence from bottom to top.
  • the front electrode is in contact with the P-type silicon substrate, and a P+ layer is formed in the area where the front electrode contacts the P-type silicon substrate.
  • the back passivation effect is good, and the back electrode is not directly in contact with the P-type silicon substrate, effectively The metal recombination is reduced, thereby increasing the open circuit voltage of the battery.
  • the front electrode contacts the passivation layer and forms a P+ layer at the same time, which can effectively conduct current and play a field passivation role, which is conducive to enhancing the PN junction to shunt photogenerated carriers. The effect of reducing recombination loss and improving battery efficiency.
  • the thickness of the silicon oxide layer is less than 2 nm, and the thickness of the phosphorus-doped polysilicon layer is 110 nm-130 nm.
  • the thickness of the silicon oxide layer is 1.3nm-1.7nm.
  • the first passivation layer is a silicon nitride layer.
  • the second passivation layer is an aluminum oxide and silicon nitride layer.
  • the back electrode is a silver electrode and the front electrode is an aluminum electrode.
  • the N-type TOPCon cell includes an N-type monocrystalline silicon substrate, a front electrode and a back electrode, wherein the N-type monocrystalline silicon substrate has a P+ doped layer on the front, and the front electrode and the The P+ doped layer is in direct contact, and the area where the P+ doped layer is not in contact with the front electrode is covered with a front passivation layer; the back of the N-type single crystal silicon substrate has an N+ doped layer, and the back electrode In direct contact with the N+ doped layer, the area where the N+ doped layer and the corresponding monocrystalline silicon substrate are in contact with the back electrode has a textured pyramid structure, and the N+ doped layer is not in contact with the back electrode
  • the area of is a square shape, and the square size in the square shape is 20 ⁇ m ⁇ 2 ⁇ m.
  • the embodiments of the present application provide a method for preparing a solar cell according to the first aspect, comprising the following steps:
  • a tunneling silicon oxide layer and a polysilicon layer are sequentially deposited in a low-pressure chemical vapor deposition furnace;
  • the front electrode and the back electrode are printed respectively.
  • the P-type silicon substrate is polished in a cleaning machine filled with polishing liquid, wherein the polishing liquid includes water, lye and additives, the additives include surfactants, sodium citrate, and sodium benzoate, and the temperature of the polishing treatment is 53°C- 57°C, the time is 215s-225s.
  • the polishing liquid includes water, lye and additives
  • the additives include surfactants, sodium citrate, and sodium benzoate
  • the temperature of the polishing treatment is 53°C- 57°C
  • the time is 215s-225s.
  • the reflectivity of the front and back surfaces of the P-type silicon substrate is 38%-44%.
  • the front side of the P-type silicon substrate before the front side of the P-type silicon substrate is textured to form a textured structure, it also includes:
  • the front side of the P-type silicon substrate is placed in a washing solution filled with hydrofluoric acid at room temperature to remove the PSG on the front side of the P-type silicon substrate; wherein, the mass concentration of the washing solution of hydrofluoric acid is 8%-12%.
  • the front side of the P-type silicon substrate is textured to form a textured structure, including:
  • the P-type silicon substrate is immersed in the texturing liquid for texturing; wherein, the texturing liquid includes KOH solution, and the mass concentration of the KOH solution is 0.5%-1.5%; the temperature of the texturing liquid is 77°C-83°C, and the P-type silicon
  • the time for the substrate to be immersed in the texturing solution is 495s-505s.
  • the front surface of the P-type silicon substrate is textured to form a textured structure, wherein the reflectance of the textured structure is 8.7%-9.3%.
  • before printing the front electrode on the front side of the P-type silicon substrate including:
  • the front electrode is printed on the front surface of the P-type silicon substrate, wherein the paste for the front electrode is aluminum paste.
  • the method includes:
  • step (3) depositing a silicon oxide compound layer on the back side of the silicon wafer obtained in step (2);
  • step (4) Carry out backside etching treatment to the silicon wafer that step (4) obtains, and remove the silicon oxide compound layer of non-laser region;
  • the metal gate line on the back side of the silicon wafer is arranged at a position corresponding to the groove pattern.
  • the polished The etching amount is 0.58g ⁇ 0.05g, wherein, the temperature of the polishing treatment is 65°C ⁇ 3°C, the time is 400s ⁇ 20s, the polishing solution used includes alkali and polishing additives, and the alkali includes KOH and/or NaOH , the volume concentration of the alkali is 4v% ⁇ 0.2v%.
  • step (2) in the square shape, the square size is 20 ⁇ m ⁇ 2 ⁇ m.
  • the back reflectance of the silicon wafer obtained in step (2) is 42% ⁇ 1%.
  • the thickness of the silicon oxide compound layer is 90-150 nm.
  • step (4) the power of the laser grooving is 20W ⁇ 5W, and the frequency is 40000Hz ⁇ 2000Hz.
  • the temperature of the etching treatment is 80°C ⁇ 3°C, and the time is 120s ⁇ 10s, wherein the etching solution used in the etching treatment includes alkali, the The base includes KOH and/or NaOH, and the volume concentration of the base is 1v% ⁇ 0.2v%.
  • the method for preparing an N-type TopCon cell further includes: (7) taking the side of the silicon wafer with boron diffusion as the front side, implanting phosphorus into the polysilicon layer on the back of the silicon wafer, And remove the polysilicon layer on the front side of the silicon wafer; (8) deposit an aluminum oxide layer and a silicon nitride layer on the front side of the silicon wafer in sequence to form a front passivation layer; (9) deposit a silicon nitride layer on the back side of the silicon wafer to form a passivation layer on the back side (10) printing electrode paste on the front and back of the silicon wafer and sintering to obtain battery sheets.
  • FIG. 1 is a schematic structural view of a solar cell provided by an embodiment of the present invention
  • Fig. 2 is a flow chart of a method for preparing an N-type TopCon battery sheet according to an embodiment of the present invention
  • Fig. 3 is a schematic structural diagram of an N-type TopCon cell obtained by a method for preparing an N-type TopCon cell according to an embodiment of the present invention.
  • a solar cell according to an embodiment of the present invention is described below with reference to FIG. 1 .
  • the solar cell according to the embodiment of the present application includes: a P-type silicon substrate 1.
  • the P-type silicon substrate 1 has a front surface and a back surface.
  • the front side is a suede structure, and the second passivation layer 6 and the front electrode 7 are stacked in sequence on the front side, the front electrode 7 is in contact with the P-type silicon substrate 1, and the area where the front electrode 7 contacts the P-type silicon substrate 1 forms There are P+ layer 8.
  • the first passivation layer 4 on the back mainly plays a protective role and reduces metal recombination.
  • the specific type of the first passivation layer 4 is not limited, and those skilled in the art can select according to actual needs, such as the first passivation layer 4
  • the nitride layer 4 can be a silicon nitride layer, or a mixture layer of other metal oxides and silicon nitride; the smooth structure on the back makes the back have a good passivation effect; the textured structure on the front is conducive to increasing the front electrode 7
  • the contact area with the silicon substrate improves the contact resistance and reduces surface recombination; wherein, the textured structure on the front side can be a pyramid textured structure.
  • the back electrode 5 and the front electrode 7 may be commonly used metal electrodes, such as silver metal grid line electrodes and aluminum metal grid line electrodes.
  • aluminum paste or silver-aluminum paste can generally be used during the printing process of the front electrode. Since the number of valence electrons of aluminum is 3, the aluminum paste forms an aluminum-silicon alloy during the printing and sintering process with the silicon substrate. In this way, the P+ layer is formed, on the one hand, it plays the role of conducting current, on the other hand, it plays the role of field passivation, thereby enhancing the effect of PN junction shunting photogenerated carriers, reducing recombination loss, and improving battery efficiency.
  • the back passivation effect is good, and the back electrode is not directly in contact with the P-type silicon substrate, effectively The metal recombination is reduced, thereby increasing the open circuit voltage of the battery.
  • the front electrode contacts the passivation layer and forms a P+ layer at the same time, which can effectively conduct current and play a field passivation role, which is conducive to enhancing the PN junction to shunt photogenerated carriers. The effect of reducing recombination loss and improving battery efficiency.
  • the thickness of the tunneling silicon oxide layer 2 is less than 2 nm, and the thickness of the phosphorus-doped polysilicon layer 3 is 110 nm-130 nm.
  • the thickness of the tunneling silicon oxide layer 2 is 1.3nm-1.7nm, such as 1.3nm, 1.5nm, 1.7nm; the thickness of the phosphorus-doped polysilicon layer 3 is 110nm-130nm, such as 110nm , 115nm, 120nm, 125nm, 130nm.
  • the thickness of the silicon oxide layer and the thickness of the phosphorus-doped polysilicon layer in this embodiment ensure that the backside of the silicon substrate has an excellent passivation effect on the metal contact, effectively reducing the recombination under the metal contact on the backside, thereby increasing the open circuit voltage.
  • the first passivation layer is a silicon nitride layer.
  • the second passivation layer is an aluminum oxide and silicon nitride layer.
  • the back electrode is a silver electrode
  • the front electrode is an aluminum electrode
  • step S1 in the low-pressure chemical vapor deposition furnace sequentially deposits the deposition of the silicon oxide layer and the deposition of the polysilicon layer on the surface of the P-type silicon substrate, and the low-pressure chemical vapor deposition furnace can realize tunneling respectively.
  • the deposition of the silicon oxide layer and the deposition of the polysilicon layer do not need to take out the silicon substrate and then deposit the polysilicon layer after the tunneling silicon oxide layer is deposited, the operation is simple and convenient, and the process flow is saved;
  • step S2 the silicon substrate treated in step S1 is put into a phosphorus diffusion furnace, and phosphorus is doped on the back side of the silicon substrate to form a PSG layer, which further improves the passivation effect of the back side, and PSG can effectively protect the back side.
  • PSG phosphorus
  • the subsequent texturing process there is no need for mask protection on the back side, which can ensure that the back structure will not be etched.
  • the dewinding process is omitted, and the process steps are further shortened, which in turn helps to reduce the cost of battery manufacturing;
  • step S3 the front side of the silicon substrate is textured, and the silicon substrate is immersed in a tank-type texturing cleaning machine containing a texturing liquid, and the texturing liquid etches the front side of the silicon substrate, wherein the etching time and temperature are controlled to ensure the amount of etching At 0.6 ⁇ 0.05g, a front suede structure is formed.
  • the temperature and time should be controlled to avoid excessive time or high temperature from affecting the back structure, and at the same time prolong the time of the entire process;
  • step S4, S5 and S6 are executed in sequence to obtain the solar cell.
  • the cell is a back-junction cell, the PN junction is on the back side, and the photogenerated carriers are mainly transported vertically in the range from the front surface to the PN junction, and the lateral transport is less, so the front electrode and silicon
  • the substrate contact is good enough, there is no need to do boron doping on the front of the silicon substrate, which simplifies the process flow and reduces the manufacturing cost.
  • it avoids the impact of the high temperature process of the boron diffusion route on the life of the silicon substrate, and also avoids boron paste + laser The problem of damage to the silicon substrate caused by the route laser;
  • the texturing process can remove the front PSG layer and realize single-sided texturing on the front, and the back PSG layer is a mask to protect the back structure from being etched. Compared with the traditional process route, the dewinding and plating process is omitted, and the process is further shortened steps, reducing battery manufacturing costs;
  • S1 sequentially depositing a tunneling silicon oxide layer and depositing a polysilicon layer on the back of the P-type silicon substrate, it also includes:
  • the P-type silicon substrate is polished in a cleaning machine filled with polishing liquid, wherein the polishing liquid includes water, lye and additives, the additives include surfactants, sodium citrate, and sodium benzoate, and the temperature of the polishing treatment is 53°C- 57°C, the time is 215s-225s; the manufacturer of the additives can be Topband BP51, and in specific use, the ratio of H 2 O:KOH:additives in the polishing solution can be 340:16:4.
  • the lye in the polishing solution can be a potassium hydroxide solution with a mass concentration of about 4%, and of course it can also be other lye;
  • the polishing treatment temperature and time disclosed in this embodiment are conducive to ensuring the etching amount of the silicon substrate 0.2 ⁇ 0.02g, which is conducive to cleaning the surface of the silicon substrate, so that the reflectivity of the surface of the silicon substrate can meet a certain requirement, and at the same time ensure the reliable progress of the subsequent steps.
  • the reflectivity of the front and back surfaces of the P-type silicon substrate is 38%-44%.
  • the front side of the P-type silicon substrate before the front side of the P-type silicon substrate is textured to form a textured structure, it also includes:
  • the front side of the P-type silicon substrate is placed in a washing solution filled with hydrofluoric acid at room temperature to remove the PSG on the front side of the P-type silicon substrate; wherein, the mass concentration of the washing solution of hydrofluoric acid is 8%-12%.
  • step S2 when the polysilicon layer is doped with phosphorus, a PSG layer is also formed on the front side of the silicon substrate.
  • the process conditions of the texturing step are reduced. Therefore, the silicon substrate can be placed in the chain-type PSG cleaning machine, so that the front of the silicon substrate contacts the texturing liquid in the cleaning machine, and at the same time, the back is protected by spraying water to ensure that the hydrofluoric acid cleaning solution only etches the PSG on the front of the silicon substrate. , forming a suede structure on the front to ensure a smooth structure on the back.
  • the front side of the P-type silicon substrate is textured to form a textured structure, including:
  • the P-type silicon substrate is immersed in the texturing liquid for texturing; wherein, the texturing liquid includes KOH solution, and the mass concentration of the KOH solution is 0.5%-1.5%; the temperature of the texturing liquid is 77°C-83°C, and the P-type silicon
  • the time for the substrate to be immersed in the texturing solution is 495s-505s.
  • the suede liquid also includes some additives, the additives include surfactants, nucleating agents, dispersants, catalysts and defoamers, for example, the manufacturer is Shichuang TS53 additives .
  • the temperature of the texturing liquid can be 77°C, 78°C, 80°C, 81°C, 83°C
  • the time for the P-type silicon substrate to be immersed in the texturing liquid can be 495s, 497s, 499s, 501s, 503s, 505s.
  • the temperature and time disclosed in this embodiment are beneficial to ensure the formation of a suitable suede structure on the front side without etching the back side.
  • the conditions are mild and easy to implement.
  • the front surface of the P-type silicon substrate is textured to form a textured structure, wherein the reflectance of the textured structure is 8.7%-9.3%.
  • before printing the front electrode on the front side of the P-type silicon substrate including:
  • the area on the front side of the P-type silicon substrate where the front electrode needs to be provided is subjected to laser treatment to open the second passivation layer.
  • the second passivation layer is opened by laser to facilitate the printing of the front electrode and ensure the contact between the front electrode and the silicon substrate.
  • the front electrode is printed on the front surface of the P-type silicon substrate, wherein the paste for the front electrode is aluminum paste.
  • the aluminum paste replaces the traditional silver-aluminum paste, which has low cost and further reduces the battery manufacturing cost.
  • the first step is to place the P-type silicon substrate in a cleaning machine filled with polishing liquid for polishing.
  • the side length of the P-type silicon substrate is 182mm, the thickness is 175um, and the chamfer is 247mm.
  • the polishing liquid includes water, KOH and additives. Additives For Topband BP51, the temperature of the polishing treatment is 55°C, the time is 220s, the weighing before and after polishing shows that the etching amount is about 0.2g, and the reflectivity of the front and back of the silicon substrate is about 41%;
  • the second step is to sequentially deposit a tunneling silicon oxide layer and a polysilicon layer on the back of the P-type silicon substrate in a low-pressure chemical vapor deposition furnace; wherein, the thickness of the tunneling silicon oxide layer is 1.5nm, and the thickness of the P polysilicon layer is 120nm;
  • the silicon substrate is placed in a phosphorus diffusion furnace to perform phosphorus doping on the polysilicon layer to obtain a phosphorus-doped polysilicon layer;
  • Step 4 Use hydrofluoric acid with a mass concentration of 10% in the chain-type PSG removal machine at room temperature, so that the front side of the silicon substrate enters the hydrofluoric acid, spray water on the back side, and remove the front PSG layer;
  • the amount of substrate etching is about 0.6g, after testing, the reflectivity of the front is about 9%;
  • the sixth step is to deposit aluminum oxide and silicon nitride layers on the front side of the P-type silicon substrate after texturing to form a second passivation layer;
  • Step 7 depositing a silicon nitride layer on the phosphorus-doped polysilicon layer to form a first passivation layer;
  • the eighth step is to perform laser treatment on the front side of the P-type silicon substrate to open the second passivation layer;
  • Step 9 Open the second passivation layer on the front of the P-type silicon substrate and the back of the P-type silicon substrate by screen printing and sintering aluminum electrodes and silver electrodes respectively, and test sorting.
  • Example 1 After testing, the battery prepared in Example 1 was compared with the conventional Perc battery, and the results are shown in Table 1:
  • Eta represents conversion efficiency
  • Isc short circuit current
  • Uoc represents open circuit voltage
  • FF fill factor
  • the battery prepared by the method of the embodiment of the present application is superior to the existing Perc battery in terms of conversion efficiency, short-circuit current, open-circuit voltage and fill factor, further illustrating the preparation method of the embodiment of the present application
  • the prepared battery can effectively improve the performance of the existing Perc battery, break through the efficiency bottleneck of the Perc battery, and is expected to replace the Perc battery.
  • the invention provides a solar cell and a preparation method thereof.
  • the method includes:
  • the N-type silicon wafer containing boron diffusion on one side can be obtained by performing double-sided texturing and boron diffusion treatment on the N-type bare silicon wafer, and removing the BSG layer on the back side.
  • double-sided texturing on the N-type bare silicon wafer
  • a pyramid-shaped textured structure can be formed on the surface of the silicon substrate.
  • boron diffusion treatment is performed on the silicon wafer after texturing
  • a BSG layer can be formed on the surface of the silicon wafer. Before polishing, only the BSG layer on the backside of the silicon wafer can be removed, and the BSG layer on the front side of the silicon wafer can be retained.
  • process conditions used for double-sided texturing, boron diffusion treatment, and removal of the BSG layer on the back of the silicon wafer for the N-type bare silicon wafer are not particularly limited, and those skilled in the art can choose according to actual needs.
  • the N-type bare silicon wafer can be put into a tank-type texturing cleaning machine for alkali texturing treatment, wherein the texturing liquid can include alkali and texturing additives, and the alkali and texturing additives in the texturing liquid
  • the kind of velvet additive is not particularly limited, and those skilled in the art can select according to actual needs, for example, alkali can be KOH and/or NaOH, and the concentration of alkali can be about 1wt%, and velvet additive can be conventional in this field.
  • the temperature of the texturing liquid can be 80°C ⁇ 3°C
  • the time of texturing treatment can be 500s ⁇ 15s.
  • the double-sided textured silicon wafer can be placed in a boron diffusion furnace tube for boron diffusion treatment, wherein the boron diffusion temperature can be 950°C ⁇ 50°C, wherein the boron diffusion can be made
  • the square resistance of the processed silicon wafer reaches 120 ⁇ /sq ⁇ 20 ⁇ /sq, which is more conducive to combining with the subsequent process to make the final battery sheet have an ideal square resistance value.
  • the silicon wafer obtained by boron diffusion treatment can be treated with hydrofluoric acid so as to remove the BSG layer on the back of the silicon wafer.
  • the silicon wafer obtained by boron diffusion treatment can be placed in a chain In the type BSG cleaning machine, hydrofluoric acid with a concentration of 40 ⁇ 5wt% is used to remove the BSG layer on the back of the silicon wafer, and the controlled process temperature can be about 20°C, thereby ensuring that the BSG layer on the back of the silicon wafer can be cleaned. Effective removal.
  • the silicon wafer With the side of the silicon wafer facing away from the boron diffusion as the back, the silicon wafer is subjected to back polishing treatment to form a square shape of expected size on the back of the silicon wafer
  • the inventors have found that the passivation film on the back of the silicon wafer is more densely deposited on a larger square and flat silicon substrate, and the passivation effect is better.
  • the silicon wafer The size of the alkali throwing square on the back side cannot be too large, and it can only be controlled at about 5 ⁇ m at present.
  • the main purpose of the present invention is to break the limitation of the size of the alkali throwing square on the back side of the silicon wafer to the contact performance of the metal on the back of the battery. Purpose, the inventor imagined that the structure of the non-metal contact area on the back of the battery (i.e.
  • the area where the back of the silicon wafer is not in contact with the electrodes) and the structure of the metal contact area i.e. the area where the back of the silicon wafer is in contact with the electrodes
  • the square size of the small square structure on the back of the silicon wafer can be increased, thereby improving the passivation effect on the back, and for the metal contact area on the back of the battery, laser slotting (wherein laser opening The groove area is shown as 17 in Figure 3) and the texture process forms a textured pyramid structure in the metal contact area on the back of the silicon wafer, thereby improving the contact effect between the back of the silicon wafer and the electrode, and improving the conductivity, thereby effectively solving the problem of silicon wafer
  • the size of the alkali-polished square on the back side limits the contact performance of the metal on the back of the battery, which can not only improve the passivation effect on the back of the silicon wafer, but also ensure good contact
  • the square size in the square shape formed by the back polishing process, can be 20 ⁇ m ⁇ 2 ⁇ m, for example, it can be 19 ⁇ m, 19.5 ⁇ m, 20 ⁇ m, 20.5 ⁇ m or 21 ⁇ m, etc.
  • the inventors found that if the silicon wafer If the square size on the back side is too small, it is difficult to effectively improve the passivation effect on the back side of the silicon wafer, and if the square size on the back side of the silicon wafer is too large, the amount of etching will be larger, the silicon wafer will become thinner, and the reliability of the battery will be reduced.
  • the reflectivity of the backside of the silicon wafer can reach 42% ⁇ 1%.
  • the smoother, and the larger size of the silicon wafer can also improve the reflectivity of the silicon wafer backside.
  • by controlling the reflectivity of the silicon wafer backside to the above range it can be ensured that a denser passivation film can be formed on the silicon wafer substrate backside. The passivation effect can thus be further ensured.
  • the 182 silicon wafers with a thickness of 170 ⁇ m ⁇ 10 ⁇ m, a side length of 182 mm ⁇ 0.25 mm, and a chamfer diameter of 247 mm ⁇ 0.25 mm are used as a reference (or a thickness of 170 ⁇ m ⁇ 10 ⁇ m 182 chips with a plane area of 330.15cm2 as the reference), the etching amount of the back polishing treatment can be 0.58g ⁇ 0.05g, and the etching amount of the back polishing treatment in the conventional process is about 0.16g, but the inventor It is found that if the etching amount of the back polishing treatment is too small, it is difficult to fully remove the side and back of the battery, and if the etching amount of the back polishing treatment is too large, the silicon wafer will become thinner and the reliability of the battery will be reduced.
  • the reaction time is relatively long, which will reduce production efficiency and increase costs.
  • the present invention by controlling the above-mentioned etching amount range, it can ensure that the side and back of the battery can be completely removed, ensuring better parallel resistance of the battery and preventing leakage. It also ensures the reliability of the battery.
  • the polishing liquid used may include alkali and polishing additives, alkali and polishing additives in the polishing liquid.
  • the kind of polishing additive is not particularly limited, and those skilled in the art can select according to actual needs, for example, alkali can comprise KOH and/or NaOH, and polishing additive can be the polishing additive commonly used in this field, further, the volume concentration of alkali It can be 4v% ⁇ 0.2v%.
  • the temperature of the polishing treatment can be 65°C ⁇ 3°C, and the time can be 400s ⁇ 20s, wherein the backside of the silicon wafer can be polished in a tank cleaning machine.
  • the inventor After a large number of experiments and verifications, it is found that based on the 182 chip with a thickness of 170 ⁇ m ⁇ 10 ⁇ m and a silicon wafer plane area of 330.15cm 2 , by controlling the above polishing conditions, it is more conducive to obtaining a back surface with a size of 20 ⁇ m ⁇ 2 ⁇ m and a back reflectivity.
  • the etching amount is 0.58g ⁇ 0.05g, which is not only more conducive to the better passivation effect of the non-metallic area on the back of the final cell, but also ensures a higher A good battery is connected in parallel to prevent leakage.
  • a layer of SiOx can be deposited on the back of the battery in an atmospheric pressure chemical vapor deposition device (APCVD), specifically a silicon dioxide layer, wherein the thickness of the silicon oxide layer can be 90-150 nm , for example, can be 95nm, 100nm, 105nm, 115nm, 125nm, 135nm or 145nm, etc.
  • APCVD atmospheric pressure chemical vapor deposition device
  • the alkali in the texturing solution cannot effectively prevent the damage to the silicon matrix, and if the thickness of the silicon oxide compound layer is too large, it will not only affect the production efficiency but also lead to waste of raw materials, and will also increase the subsequent laser grooving. Difficulty, in the present invention, by controlling the thickness of the silicon oxide compound layer to the above range, it can not only protect the silicon substrate better, but also help to improve the production efficiency of the entire production process.
  • Partial laser grooving is performed on the silicon oxide compound layer to remove the silicon oxide compound layer at the grooved part and burn the underlying silicon to form an inverted pyramid structure
  • the silicon oxide compound layer (SiOx layer) on the battery backside can be laser-grooved on the ultraviolet laser (the laser region is shown as 17 in Fig. 3), and the pattern of groove here is the same as that in the subsequent silicon oxide layer.
  • the pattern of metal fine grid lines formed on the back of the chip is consistent.
  • the laser burns the underlying silicon at the same time to form an inverted pyramid structure.
  • Mark points are marked on the 4 corners of the battery for the subsequent wire Alignment during screen printing.
  • the metal grid line formed on the back of the silicon wafer is set at the position corresponding to the groove pattern, and the silicon oxide compound layer on the back of the battery is laser grooved to expose the silicon substrate and form an inverted pyramid structure.
  • the silicon substrate contacts the metal paste through an inverted pyramid structure, the mutual contact area is larger, the contact resistance is smaller, and the series resistance is correspondingly smaller, which can further improve the conductive effect. Therefore, even if the non-metallic contact on the back of the battery has a larger size of the alkali-polished square, it can ensure a good contact effect between the silicon substrate and the electrode, and improve the conductivity.
  • the power of laser grooving can be 20W ⁇ 5W, and the frequency can be 40000Hz ⁇ 2000Hz.
  • the inventors found that if the laser power is too small or the frequency is too low, it is difficult to achieve better laser grooving effect and the burning effect on the lower silicon, and if the laser power is too high or the frequency is too high, it is difficult to control the laser level, which is not conducive to the formation of the expected pyramid structure.
  • by controlling the above laser conditions it can be ensured that the silicon wafer
  • the metal contact area on the back forms a better inverted pyramid structure, which is more conducive to improving the contact effect between the back of the silicon wafer and the electrode, and improving conductivity.
  • step (4) Carry out backside etching treatment to the silicon wafer that step (4) obtains, and remove the silicon oxide compound layer of non-laser region;
  • the main purpose of carrying out the backside etching treatment on the silicon wafer is to eliminate the damaged layer formed by laser ablation in the previous step, and modify the inverted pyramid structure at the same time.
  • the SiOx layer in the non-laser area can be removed by hydrofluoric acid .
  • silicon wafers can be put into a tank-type texturing cleaning machine for backside corrosion treatment, wherein the corrosion solution can include alkali and corrosion additives, and the types of alkali and corrosion additives in the corrosion solution are not subject to special restrictions.
  • the alkali can be KOH and/or NaOH
  • the volume concentration of the alkali can be 1v% ⁇ 0.2v%
  • the corrosion additive can be the conventional corrosion additive in this field
  • the corrosion solution The temperature can be 80°C ⁇ 3°C
  • the corrosion treatment time can be 120s ⁇ 10s.
  • the deposition of the back tunneling oxide layer (SiO2) and the polysilicon (Poly) layer can be carried out in a low pressure chemical vapor deposition furnace (LPCVD), wherein the thicknesses of the tunneling oxide layer and the polysilicon layer are not affected by Especially limited, those skilled in the art can choose according to actual needs, for example, the thickness of the tunnel oxide layer can be about 1.5nm, and the thickness of the polysilicon layer can be about 120nm.
  • LPCVD low pressure chemical vapor deposition furnace
  • the method for preparing an N-type TopCon cell can further include: (7) taking the side of the silicon wafer with boron diffusion as the front side, implanting phosphorus into the polysilicon layer on the back side of the silicon wafer to form a passivation
  • the contact structure wherein this step can be carried out in the rear phosphorus diffusion furnace, by preparing an ultra-thin tunnel oxide layer and a thin layer of phosphorus-doped polysilicon on the back of the battery to form a passivation contact structure, which can be a silicon wafer
  • the backside provides good surface passivation, and the ultra-thin oxide layer can allow the multi-carrier electrons to tunnel into the polysilicon layer while blocking the recombination of the minority carrier-holes, and then the electrons are transported laterally in the polysilicon layer and collected by the metal, which can greatly reduce the metal contact recombination current , to increase the open circuit voltage and short circuit current of the battery.
  • the method for preparing N-type TopCon cells may further include: removing the polysilicon layer on the front side of the silicon wafer, specifically, a polishing solution may be used in a tank cleaning machine, wherein the polishing solution may include KOH And polishing additive, the concentration of KOH in the polishing liquid can be 4wt% effect, and polishing additive can be the polishing additive conventional in this field, and polishing temperature can be 66 °C ⁇ 3 °C, and process time can be 200s ⁇ 20s, by controlling this condition can Effectively remove the polysilicon layer on the front side of the silicon wafer.
  • a polishing solution may include KOH And polishing additive
  • the concentration of KOH in the polishing liquid can be 4wt% effect
  • polishing additive can be the polishing additive conventional in this field
  • polishing temperature can be 66 °C ⁇ 3 °C
  • process time can be 200s ⁇ 20s
  • the method for preparing an N-type TopCon battery sheet may further include: (8) depositing an aluminum oxide layer and a silicon nitride layer in sequence on the front side of the silicon wafer to form a front passivation layer; (9) Depositing a silicon nitride layer on the back of the silicon wafer to form a back passivation layer; (10) printing electrode paste on the front and back of the silicon wafer and sintering to obtain a battery sheet.
  • the method for preparing an N-type TopCon battery sheet deposits a silicon oxide compound layer on the backside of the silicon wafer after the back polishing treatment, and performs laser grooving on the silicon oxide compound layer and grooves the silicon oxide compound layer.
  • Burning the silicon in the lower layer can form an inverted pyramid structure on the surface of the silicon wafer, and then further texturing can remove the damaged surface caused by laser burning and modify the inverted pyramid structure.
  • the modified texture can be used
  • the pyramid structure is in contact with the metal electrode on the back, which increases the contact effect between the back of the silicon wafer and the metal electrode, improves conductivity, and allows a larger square size in the non-contact area, thereby achieving a better passivation effect.
  • this preparation process has at least the following advantages: 1. When polishing the back of the silicon wafer, a larger square shape can be formed on the back of the silicon wafer, for example, the size of the square can reach about 20 ⁇ m, compared with the existing back polishing.
  • the present invention can form a larger square size topography, and then make the passivation film deposited on a larger square, flat silicon substrate more dense, and the passivation effect is better;
  • the back of the silicon wafer When forming a larger square shape, the amount of etching controlled by the back polishing is also larger than that of the conventional process, which can ensure that the side and back of the battery are completely removed, ensuring better parallel resistance of the battery and preventing Leakage; 3.
  • the metallized area on the back of the silicon wafer that is, the area in contact with the back electrode
  • the silicon substrate contacts the metal paste through an inverted pyramid structure, and the mutual contact area is larger, so that the contact resistance is smaller and the series resistance is correspondingly smaller. 4.
  • the battery prepared by this method is compatible with the performance of good contact between the back passivation and the back metal paste and the silicon substrate, the resistance is lower, and the open circuit voltage, fill factor and conversion efficiency of the battery are all consistent.
  • the series resistance can be reduced by 1.5m ⁇ or more
  • the open circuit voltage can be increased by 5mV or more
  • the fill factor can be increased by 0.4% or more
  • the conversion efficiency of the battery can be increased by 0.3% or more.
  • an N-type TOPCon cell prepared by the method for preparing an N-type TopCon cell.
  • an N-type TOPCon cell can include an N-type monocrystalline silicon substrate 10, a front electrode 11 (such as an Ag/Al electrode) and a back electrode 12 (such as an Ag electrode) , wherein, the front side of the N-type single crystal silicon substrate 10 has a P+ doped layer 13, the front electrode 11 is in direct contact with the P+ doped layer 13, the area where the P+ doped layer 13 contacts the front electrode 11 has a textured pyramid structure, and the P+ doped
  • the area of the impurity layer 13 that is not in contact with the front electrode 11 is covered with a front passivation layer 14, wherein the front passivation layer 14 is sequentially formed with an aluminum oxide layer and a silicon nitride layer in a direction away from the front surface of the single crystal silicon substrate 10, and the
  • the square size in the square shape is 20 ⁇ m ⁇ 2 ⁇ m, and the square shape is covered with back passivation.
  • Layer 16 wherein the rear passivation layer 16 is formed in sequence with a polysilicon doped layer and a silicon nitride layer in a direction away from the rear surface of the single crystal silicon substrate 10.
  • the N-type TopCon battery has a larger square shape and better passivation effect, and the part of the back of the battery that is in contact with the back electrode is an inverted pyramid textured structure, which has a better contact effect with the electrode and conducts electricity.
  • the first step of the process is to put the N-type bare silicon wafer into the tank-type texturing cleaning machine for alkali texturing process.
  • the solution is 1 ⁇ 0.2v% concentration of KOH+texturing additive solution, and the solution temperature is 80°C ⁇ 3°C , the process time is 500s ⁇ 15s, the etching amount is 0.58 ⁇ 0.05g, and the reflectivity is 9 ⁇ 0.5%;
  • the cells after texturing are subjected to a boron diffusion process in a boron diffusion furnace tube, with a square resistance of 120 ⁇ 20 ⁇ /sq and a process temperature of 950 ⁇ 50°C;
  • the third step is to remove the back BSG layer in the chain type BSG cleaning machine, the solution is hydrofluoric acid with a concentration of 40 ⁇ 5wt%, and the process temperature is 20 ⁇ 3°C;
  • the fourth step is to carry out alkali polishing on the back side in a tank cleaning machine.
  • the solution is 4 ⁇ 0.2v% volume concentration of KOH+polishing additive, the solution temperature is 65 ⁇ 3°C, the process time is 400 ⁇ 20s, and the size of the back surface is 20 ⁇ m ⁇ 2 ⁇ m square, the back reflectivity is 42 ⁇ 1%;
  • the fifth step is to deposit a layer of SiOx on the back of the battery in the atmospheric pressure chemical vapor deposition equipment (APCVD), with a film thickness of 100 ⁇ 10nm;
  • APCVD atmospheric pressure chemical vapor deposition equipment
  • the sixth step is to laser groove the SiOx layer on the back of the battery on the ultraviolet laser.
  • the laser power is 20W and the frequency is 40000Hz.
  • the pattern of the groove here is consistent with the pattern of the metal fine grid line on the back.
  • the laser burns the lower layer of silicon at the same time to form an inverted pyramid structure, and finally mark points on the four corners of the battery for alignment during subsequent screen printing;
  • the seventh step is to carry out alkali corrosion in the tank cleaning machine.
  • the solution is KOH+corrosion additive with a concentration of 1 ⁇ 0.2v% (volume ratio), the solution temperature is 80 ⁇ 3°C, and the process time is 120 ⁇ 10s.
  • the main purpose is to eliminate the above The damaged layer formed by the first step of laser ablation, while modifying the inverted pyramid structure, and finally remove the SiOx film in the non-laser area in the hydrofluoric acid tank behind;
  • the eighth step is to deposit the back tunneling oxide layer (SiO2) and polysilicon (Poly) layer in a low-pressure chemical vapor deposition furnace (LPCVD).
  • the thickness of the tunneling oxide layer is 1.5 ⁇ 0.2nm, and the thickness of Poly is 120 ⁇ 20nm;
  • phosphorus diffusion furnace on the back injects phosphorus into the Poly layer on the back to form a passivation contact structure
  • the tenth step is to remove the front side winding Poly layer in the tank cleaning machine, the solution is 4 ⁇ 0.2v% (volume ratio) concentration of KOH+polishing additive, the temperature is 66 ⁇ 3°C, and the process time is 200 ⁇ 20s;
  • the eleventh step is AlOx+SiNx on the front and SiNx passivation film coating on the back;
  • the first step of the process is to put the N-type bare silicon wafer into the tank-type texturing cleaning machine for alkali texturing process.
  • the solution is 1 ⁇ 0.2v% (volume ratio) concentration of KOH+texturing additive solution, and the solution temperature is 80 ⁇ 3°C, process time 500 ⁇ 15s, etching amount 0.58 ⁇ 0.05g, reflectivity 9 ⁇ 0.5%;
  • the cells after texturing are subjected to a boron diffusion process in a boron diffusion furnace tube, with a square resistance of 120 ⁇ 20 ⁇ /sq and a process temperature of 950 ⁇ 50°C;
  • the third step is to remove the back BSG layer in the chain type BSG cleaning machine, the solution is hydrofluoric acid with a concentration of 40 ⁇ 5wt%, and the process temperature is 20 ⁇ 3°C;
  • the fourth step is to carry out alkali polishing on the back in the tank cleaning machine.
  • the solution is 4 ⁇ 0.2v% concentration of KOH+polishing additive, the solution temperature is 65 ⁇ 3°C, the process time is 160 ⁇ 10s, and the size of the back surface is 5 ⁇ 0.5 ⁇ m square, the back reflectivity is 40 ⁇ 1%;
  • the fifth step is to deposit the back tunneling oxide layer (SiO2) and polysilicon (Poly) layer in a low-pressure chemical vapor deposition furnace (LPCVD).
  • the thickness of the tunneling oxide layer is 1.5 ⁇ 0.2nm, and the thickness of Poly is 120 ⁇ 20nm;
  • phosphorus diffusion furnace on the back injects phosphorus into the Poly layer on the back to form a passivation contact structure
  • the seventh step is to remove the front side winding Poly layer in the tank cleaning machine, the solution is 4 ⁇ 0.2v% (volume ratio)% KOH+polishing additive, the temperature is 66 ⁇ 3°C, and the process time is 200 ⁇ 20s;
  • the eighth step is AlOx+SiNx on the front and SiNx passivation film coating on the back;
  • the fourth step is to carry out alkali polishing on the back in the tank cleaning machine.
  • the solution is KOH+polishing additive with a concentration of 4 ⁇ 0.2v% (volume ratio), the solution temperature is 65 ⁇ 3°C, the process time is 800 ⁇ 20s, and the back surface is A square with a size of 40 ⁇ 2 ⁇ m, the reflectivity of the back is 43 ⁇ 1%;
  • the fourth step is to carry out alkali polishing on the back in a tank cleaning machine.
  • the solution is KOH+polishing additive with a concentration of 4 ⁇ 0.2v% (volume ratio) wt%, the solution temperature is 65 ⁇ 3°C, and the process time is 600 ⁇ 20s. Appearance is a square with a size of 30 ⁇ 2 ⁇ m, and the reflectivity of the back is 42.5 ⁇ 1%;
  • the fifth step is to deposit a layer of SiOx on the back of the battery in the atmospheric pressure chemical vapor deposition equipment (APCVD), with a film thickness of 100 ⁇ 10nm;
  • APCVD atmospheric pressure chemical vapor deposition equipment
  • the sixth step is to laser groove the SiOx layer on the back of the battery on the ultraviolet laser.
  • the laser power is 20W and the frequency is 40000Hz.
  • the pattern of the groove here is consistent with the pattern of the metal fine grid line on the back.
  • the laser burns the lower layer of silicon at the same time to form an inverted pyramid structure, and finally mark points on the four corners of the battery for alignment during subsequent screen printing;
  • the seventh step is to carry out alkali corrosion in the tank cleaning machine.
  • the solution is KOH+corrosion additive with a concentration of 1 ⁇ 0.2v% (volume ratio), the solution temperature is 80 ⁇ 3°C, and the process time is 120 ⁇ 10s.
  • the main purpose is to eliminate the above The damaged layer formed by the first step of laser ablation, while modifying the inverted pyramid structure, and finally remove the SiOx film in the non-laser area in the subsequent hydrofluoric acid tank.
  • Example 1 100 24.54 723 41.33 82.12 Comparative example 1 100 24.22 716 41.31 81.90 Comparative example 2 100 24.52 722 41.35 82.13 Example 2 100 24.47 721 41.34 82.10
  • Example 2 and The silicon wafer in the solar cell prepared in Comparative Example 2 is relatively thinner, the limit load that the solar cell can carry is also smaller, and the risk of the solar cell is greater.
  • the device embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in One place, or it can be distributed to multiple network elements. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. It can be understood and implemented by those skilled in the art without any creative efforts.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
  • the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means can be embodied by one and the same item of hardware.
  • the use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Photovoltaic Devices (AREA)

Abstract

Disclosed in the present application are a solar cell and a preparation method therefor. The solar cell comprises a P-type silicon substrate having a front surface and a back surface. The back surface is of a smooth structure, and is sequentially provided, from top to bottom, with a tunneling silicon oxide layer, a phosphorus-doped polysilicon layer, a first passivation layer, and back electrodes, wherein the back electrodes are in contact with the phosphorus-doped polysilicon layer. The front surface is of a textured structure, and is sequentially provided, from bottom to top, with second passivation layers and front electrodes, wherein the front electrodes are in contact with the P-type silicon substrate, and P+ layers are formed in areas where the front electrodes are in contact with the P-type silicon substrate. The solar cell structure disclosed in the present application has a high open-circuit voltage and high battery efficiency, is simple in process, and is thus suitable for large-scale mass production.

Description

太阳能电池及其制备方法Solar cell and its preparation method
本申请要求在2021年11月8日提交中国专利局、申请号为202111314179.4、发明名称为“N型TopCon电池片及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。本申请要求在2021年12月29日提交中国专利局、申请号为202111648529.0、发明名称为“太阳能电池及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims the priority of the Chinese patent application with the application number 202111314179.4 and the title of the invention "N-type TopCon cell and its preparation method" submitted to the China Patent Office on November 8, 2021, the entire contents of which are incorporated herein by reference. Applying. This application claims the priority of the Chinese patent application with the application number 202111648529.0 and the invention title "Solar Cell and Its Preparation Method" filed with the China Patent Office on December 29, 2021, the entire contents of which are incorporated by reference in this application.
技术领域technical field
本发明一般涉及太阳能电池技术领域，具体涉及一种太阳能电池及其制备方法。The present invention generally relates to the technical field of solar cells, in particular to a solar cell and a preparation method thereof.
背景技术Background technique
Perc电池得益于氧化铝被钝化技术的发展，极大的降低了电池背表面的复合，目前作为光伏市场的主流电池产品。随着工艺、设备技术的升级，Perc电池的效率提升遇到瓶颈。Perc battery benefits from the development of alumina passivation technology, which greatly reduces the recombination of the back surface of the battery, and is currently the mainstream battery product in the photovoltaic market. With the upgrading of process and equipment technology, the efficiency improvement of Perc battery has encountered a bottleneck.
相关技术中发现Topcon电池的遂穿氧化层结构对金属接触的钝化作用，能够降低了背面金属接触下的复合，但是，如何进一步提升电池背面钝化效果，提高开路电压，最终提升电池效率实现Perc电池的升级换代仍然是一个研究难点。In related technologies, it is found that the passivation effect of the tunneling oxide layer structure of the Topcon battery on the metal contact can reduce the recombination under the metal contact on the back. However, how to further improve the passivation effect on the back of the battery, increase the open circuit voltage, and finally improve the battery efficiency. The upgrading of Perc batteries is still a research difficulty.
发明内容Contents of the invention
鉴于现有技术中的上述缺陷或不足，期望提供一种太阳能电池及其制备方法，其开路电压和电池效率高，工艺简单，适于大规模量产。In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a solar cell and a preparation method thereof, which have high open-circuit voltage and cell efficiency, simple process, and are suitable for mass production.
第一方面，本申请实施例提供的一种太阳能电池，包括：P型硅基体，P型硅基体具有正面和背面，背面为光面结构，且背面从上至下依次设置有隧穿氧化硅层、磷掺杂的多晶硅层、第一钝化层和背面电极，背面电极和磷掺杂的多晶硅层接触；In the first aspect, a solar cell provided by an embodiment of the present application includes: a P-type silicon substrate, the P-type silicon substrate has a front side and a back side, the back side is a smooth structure, and the back side is sequentially provided with tunneling silicon oxide from top to bottom layer, a phosphorus-doped polysilicon layer, a first passivation layer and a back electrode, and the back electrode is in contact with the phosphorus-doped polysilicon layer;
正面为绒面结构，正面从下至上依次设置有第二钝化层和正面电极，正面电极与P型硅基体接触，且正面电极与P型硅基体接触的区域形成 有P+层。The front is a suede structure, and the front is provided with a second passivation layer and a front electrode in sequence from bottom to top. The front electrode is in contact with the P-type silicon substrate, and a P+ layer is formed in the area where the front electrode contacts the P-type silicon substrate.
根据本申请实施例的太阳能电池，一方面通过在P型硅基体背面沉积氧化硅层和磷掺杂的多晶硅层，使得背面钝化效果好，并且背面电极不直接与P型硅基体接触，有效降低了金属复合，进而提高电池的开路电压，另一方面正面电极与钝化层接触的同时形成P+层，有效传导电流的同时起到场钝化作用，有利于增强PN结分流光生载流子的效应，减少复合损失，提高电池效率。According to the solar cell of the embodiment of the present application, on the one hand, by depositing a silicon oxide layer and a phosphorus-doped polysilicon layer on the back of the P-type silicon substrate, the back passivation effect is good, and the back electrode is not directly in contact with the P-type silicon substrate, effectively The metal recombination is reduced, thereby increasing the open circuit voltage of the battery. On the other hand, the front electrode contacts the passivation layer and forms a P+ layer at the same time, which can effectively conduct current and play a field passivation role, which is conducive to enhancing the PN junction to shunt photogenerated carriers. The effect of reducing recombination loss and improving battery efficiency.
在一些实施例中，氧化硅层厚度小于2nm，磷掺杂的多晶硅层厚度为110nm-130nm。In some embodiments, the thickness of the silicon oxide layer is less than 2 nm, and the thickness of the phosphorus-doped polysilicon layer is 110 nm-130 nm.
进一步地，氧化硅层厚度为1.3nm-1.7nm。Further, the thickness of the silicon oxide layer is 1.3nm-1.7nm.
在一些实施例中，第一钝化层为氮化硅层。In some embodiments, the first passivation layer is a silicon nitride layer.
在一些实施例中，第二钝化层为氧化铝和氮化硅层。In some embodiments, the second passivation layer is an aluminum oxide and silicon nitride layer.
在一些实施例中，背面电极为银电极，正面电极为铝电极。In some embodiments, the back electrode is a silver electrode and the front electrode is an aluminum electrode.
在本发明的一些实施例中，N型TOPCon电池片包括N型单晶硅基体、正面电极和背面电极，其中，所述N型单晶硅基体正面具有P+掺杂层，所述正面电极与所述P+掺杂层直接接触，所述P+掺杂层不与所述正面电极接触的区域覆盖有正面钝化层；所述N型单晶硅基体背面具有N+掺杂层，所述背面电极与所述N+掺杂层直接接触，所述N+掺杂层及对应的单晶硅基体与所述背面电极接触的区域具有绒面金字塔结构，所述N+掺杂层不与所述背面电极接触的区域为方块形貌，所述方块形貌中方块尺寸为20μm±2μm。In some embodiments of the present invention, the N-type TOPCon cell includes an N-type monocrystalline silicon substrate, a front electrode and a back electrode, wherein the N-type monocrystalline silicon substrate has a P+ doped layer on the front, and the front electrode and the The P+ doped layer is in direct contact, and the area where the P+ doped layer is not in contact with the front electrode is covered with a front passivation layer; the back of the N-type single crystal silicon substrate has an N+ doped layer, and the back electrode In direct contact with the N+ doped layer, the area where the N+ doped layer and the corresponding monocrystalline silicon substrate are in contact with the back electrode has a textured pyramid structure, and the N+ doped layer is not in contact with the back electrode The area of is a square shape, and the square size in the square shape is 20 μm±2 μm.
第二方面，本申请的实施例提供一种第一方面的太阳能电池的制备方法，包括如下步骤：In a second aspect, the embodiments of the present application provide a method for preparing a solar cell according to the first aspect, comprising the following steps:
对P型硅基体的背面在低压化学气相沉积炉中依次沉积隧穿氧化硅层以及沉积多晶硅层；On the back of the P-type silicon substrate, a tunneling silicon oxide layer and a polysilicon layer are sequentially deposited in a low-pressure chemical vapor deposition furnace;
对多晶硅层进行磷掺杂，得到磷掺杂的多晶硅层；Doping the polysilicon layer with phosphorus to obtain a phosphorus-doped polysilicon layer;
将P型硅基体的正面进行制绒，形成绒面结构；Texture the front side of the P-type silicon substrate to form a textured structure;
在制绒后的P型硅基体的正面沉积氧化铝和氮化硅层，形成第二钝化层；Deposit aluminum oxide and silicon nitride layers on the front side of the P-type silicon substrate after texturing to form a second passivation layer;
在磷掺杂的多晶硅层上沉积氮化硅层，形成第一钝化层；Depositing a silicon nitride layer on the phosphorus-doped polysilicon layer to form a first passivation layer;
在P型硅基体的正面和P型硅基体的背面分别印刷正面电极和背面 电极。On the front side of the P-type silicon substrate and the back side of the P-type silicon substrate, the front electrode and the back electrode are printed respectively.
在一些实施例中，在对P型硅基体的背面依次沉积隧穿氧化硅层以及沉积多晶硅层之前，还包括：In some embodiments, before sequentially depositing a tunneling silicon oxide layer and depositing a polysilicon layer on the back side of the P-type silicon substrate, further comprising:
将P型硅基体盛有抛光液的清洗机中进行抛光处理，其中，抛光液包括水、碱液和添加剂，添加剂包括表面活性剂，柠檬酸钠，苯甲酸钠，抛光处理的温度为53℃-57℃，时间为215s-225s。The P-type silicon substrate is polished in a cleaning machine filled with polishing liquid, wherein the polishing liquid includes water, lye and additives, the additives include surfactants, sodium citrate, and sodium benzoate, and the temperature of the polishing treatment is 53°C- 57°C, the time is 215s-225s.
进一步地，在将P型硅基体盛有抛光液的清洗机中进行抛光处理后，P型硅基体的正面和背面的反射率为38％-44％。Further, after polishing the P-type silicon substrate in a cleaning machine filled with polishing liquid, the reflectivity of the front and back surfaces of the P-type silicon substrate is 38%-44%.
在一些实施例中，在将P型硅基体的正面进行制绒，形成绒面结构之前，还包括：In some embodiments, before the front side of the P-type silicon substrate is textured to form a textured structure, it also includes:
将P型硅基体的正面在室温下，置于盛有氢氟酸的洗液中，去除P型硅基体的正面的PSG；其中，氢氟酸的洗液质量浓度为8％-12％。The front side of the P-type silicon substrate is placed in a washing solution filled with hydrofluoric acid at room temperature to remove the PSG on the front side of the P-type silicon substrate; wherein, the mass concentration of the washing solution of hydrofluoric acid is 8%-12%.
具体的，将P型硅基体的正面进行制绒，形成绒面结构，包括：Specifically, the front side of the P-type silicon substrate is textured to form a textured structure, including:
将P型硅基体浸入制绒液中，进行制绒；其中，制绒液包括KOH溶液，KOH溶液的质量浓度为0.5％-1.5％；制绒液温度为77℃-83℃，P型硅基体浸入制绒液的时间为495s-505s。The P-type silicon substrate is immersed in the texturing liquid for texturing; wherein, the texturing liquid includes KOH solution, and the mass concentration of the KOH solution is 0.5%-1.5%; the temperature of the texturing liquid is 77°C-83°C, and the P-type silicon The time for the substrate to be immersed in the texturing solution is 495s-505s.
进一步地，将P型硅基体的正面进行制绒，形成绒面结构，其中，绒面结构的反射率为8.7％-9.3％。Further, the front surface of the P-type silicon substrate is textured to form a textured structure, wherein the reflectance of the textured structure is 8.7%-9.3%.
在一些实施例中，在P型硅基体的正面印刷正面电极之前，包括：In some embodiments, before printing the front electrode on the front side of the P-type silicon substrate, including:
将P型硅基体的正面需要设置正面电极的区域，进行激光处理，以打开第二钝化层；Perform laser treatment on the front side of the P-type silicon substrate where the front electrode needs to be set, so as to open the second passivation layer;
在一些实施例，P型硅基体的正面印刷正面电极，其中，正面电极浆料采用铝浆。In some embodiments, the front electrode is printed on the front surface of the P-type silicon substrate, wherein the paste for the front electrode is aluminum paste.
在一些实施例中，所述方法包括：In some embodiments, the method includes:
(1)提供单面含有硼扩散的N型硅片；(1) Provide N-type silicon wafers with boron diffusion on one side;
(2)以所述硅片背离硼扩散的一侧为背面，对所述硅片进行背面抛光处理，以便在硅片背面形成预期尺寸的方块形貌；(2) Taking the side of the silicon wafer away from the boron diffusion as the back side, performing a back polishing process on the silicon wafer, so as to form a square shape of expected size on the back side of the silicon wafer;
(3)在步骤(2)得到的硅片背面沉积硅氧化合物层；(3) depositing a silicon oxide compound layer on the back side of the silicon wafer obtained in step (2);
(4)对所述硅氧化合物层进行局部激光开槽，以便去除开槽部位的硅氧化合物层并对下层硅进行烧灼，形成倒金字塔结构；(4) Carrying out partial laser grooves to the silicon oxide compound layer, so as to remove the silicon oxide compound layer at the grooved position and burn the lower layer of silicon to form an inverted pyramid structure;
(5)对步骤(4)得到的硅片进行背面腐蚀处理，并去除未激光区域的硅氧化合物层；(5) Carry out backside etching treatment to the silicon wafer that step (4) obtains, and remove the silicon oxide compound layer of non-laser region;
(6)在步骤(5)得到的硅片背面沉积隧穿氧化层和多晶硅层，(6) depositing a tunnel oxide layer and a polysilicon layer on the back side of the silicon wafer obtained in step (5),
其中，所述硅片背面金属栅线设置在对应开槽图形的位置。Wherein, the metal gate line on the back side of the silicon wafer is arranged at a position corresponding to the groove pattern.
在本发明的一些实施例中，步骤(2)中，以厚度为170μm±10μm、边长为182mm±0.25mm、倒角直径为247mm±0.25mm的182硅片为基准，所述抛光处理的刻蚀量为0.58g±0.05g，其中，所述抛光处理的温度为65℃±3℃，时间为400s±20s，采用的抛光液包括碱和抛光添加剂，所述碱包括KOH和/或NaOH，所述碱的体积浓度为4v％±0.2v％。In some embodiments of the present invention, in step (2), with a thickness of 170 μm ± 10 μm, a side length of 182 mm ± 0.25 mm, and a chamfer diameter of 247 mm ± 0.25 mm as a benchmark, the polished The etching amount is 0.58g±0.05g, wherein, the temperature of the polishing treatment is 65°C±3°C, the time is 400s±20s, the polishing solution used includes alkali and polishing additives, and the alkali includes KOH and/or NaOH , the volume concentration of the alkali is 4v%±0.2v%.
在本发明的一些实施例中，步骤(2)中，所述方块形貌中，方块尺寸为20μm±2μm。In some embodiments of the present invention, in step (2), in the square shape, the square size is 20 μm±2 μm.
在本发明的一些实施例中，步骤(2)得到的硅片背面反射率为42％±1％。In some embodiments of the present invention, the back reflectance of the silicon wafer obtained in step (2) is 42%±1%.
在本发明的一些实施例中，步骤(3)中，所述硅氧化合物层的厚度为90～150nm。In some embodiments of the present invention, in step (3), the thickness of the silicon oxide compound layer is 90-150 nm.
在本发明的一些实施例中，步骤(4)中，所述激光开槽的功率为20W±5W，频率为40000Hz±2000Hz。In some embodiments of the present invention, in step (4), the power of the laser grooving is 20W±5W, and the frequency is 40000Hz±2000Hz.
在本发明的一些实施例中，步骤(5)中，所述腐蚀处理的温度为80℃±3℃，时间为120s±10s，其中，所述腐蚀处理采用的腐蚀液中包括碱，所述碱包括KOH和/或NaOH，所述碱的体积浓度为1v％±0.2v％。In some embodiments of the present invention, in step (5), the temperature of the etching treatment is 80°C±3°C, and the time is 120s±10s, wherein the etching solution used in the etching treatment includes alkali, the The base includes KOH and/or NaOH, and the volume concentration of the base is 1v%±0.2v%.
在本发明的一些实施例中，制备N型TopCon电池片的方法进一步包括：(7)以所述硅片具有硼扩散的一侧为正面，在硅片背面的所述多晶硅层中注入磷，并去除硅片正面绕镀多晶硅层；(8)在硅片正面依次沉积氧化铝层和氮化硅层，形成正面钝化层；(9)在硅片背面沉积氮化硅层，形成背面钝化层；(10)在硅片正面和背面印刷电极浆料并进行烧结，得到电池片。In some embodiments of the present invention, the method for preparing an N-type TopCon cell further includes: (7) taking the side of the silicon wafer with boron diffusion as the front side, implanting phosphorus into the polysilicon layer on the back of the silicon wafer, And remove the polysilicon layer on the front side of the silicon wafer; (8) deposit an aluminum oxide layer and a silicon nitride layer on the front side of the silicon wafer in sequence to form a front passivation layer; (9) deposit a silicon nitride layer on the back side of the silicon wafer to form a passivation layer on the back side (10) printing electrode paste on the front and back of the silicon wafer and sintering to obtain battery sheets.
本发明的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其它目的、特征和优点能够更明显易懂，以下特举本发明的具体实施方式。The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the specific embodiments of the present invention are enumerated below.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显：Other characteristics, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:
图1为本发明实施例提供的太阳能电池的结构示意图；FIG. 1 is a schematic structural view of a solar cell provided by an embodiment of the present invention;
图2是根据本发明一个实施例的制备N型TopCon电池片的方法流程图；Fig. 2 is a flow chart of a method for preparing an N-type TopCon battery sheet according to an embodiment of the present invention;
图3是根据本发明一个实施例的采用制备N型TopCon电池片的方法得到的N型TopCon电池片的结构示意图。Fig. 3 is a schematic structural diagram of an N-type TopCon cell obtained by a method for preparing an N-type TopCon cell according to an embodiment of the present invention.
图中，In the figure,
1.P型硅基体，2.隧穿氧化硅层，3.磷掺杂的多晶硅层，4.第一钝化层，5.背面电极，6.第二钝化层，7.正面电极，8.P+层，10.N型单晶硅基体，11.正面电极，12.背面电极，13.P+掺杂层，14.正面钝化层，15.N+掺杂层，16.背面钝化层，17.激光开槽区域。1. P-type silicon substrate, 2. Tunneling silicon oxide layer, 3. Phosphorus-doped polysilicon layer, 4. First passivation layer, 5. Back electrode, 6. Second passivation layer, 7. Front electrode, 8. P+ layer, 10. N-type single crystal silicon substrate, 11. Front electrode, 12. Back electrode, 13. P+ doped layer, 14. Front passivation layer, 15. N+ doped layer, 16. Back passivation Layer, 17. Laser grooved area.
具体实施例specific embodiment
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与发明相关的部分。The application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain related inventions, rather than to limit the invention. It should also be noted that, for ease of description, only parts related to the invention are shown in the drawings.
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and embodiments.
本发明使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明。在本发明和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含 义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein and in the appended claims, the singular forms "a", "the", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
下面参考图1描述根据本发明实施例的太阳能电池。A solar cell according to an embodiment of the present invention is described below with reference to FIG. 1 .
根据本申请实施例的太阳能电池，如图1所示，包括：P型硅基体1，P型硅基体1具有正面和背面，背面为光面结构，且在所述背面依次层叠设置有隧穿氧化硅层2、磷掺杂的多晶硅层3、第一钝化层4和背面电极5，背面电极5和磷掺杂的多晶硅层3接触；The solar cell according to the embodiment of the present application, as shown in FIG. 1 , includes: a P-type silicon substrate 1. The P-type silicon substrate 1 has a front surface and a back surface. A silicon oxide layer 2, a phosphorus-doped polysilicon layer 3, a first passivation layer 4 and a back electrode 5, the back electrode 5 is in contact with the phosphorus-doped polysilicon layer 3;
正面为绒面结构，在所述正面依次层叠设置有第二钝化层6和正面电极7，正面电极7与P型硅基体1接触，且正面电极7与P型硅基体1接触的区域形成有P+层8。The front side is a suede structure, and the second passivation layer 6 and the front electrode 7 are stacked in sequence on the front side, the front electrode 7 is in contact with the P-type silicon substrate 1, and the area where the front electrode 7 contacts the P-type silicon substrate 1 forms There are P+ layer 8.
可以理解的是，背面的第一钝化层4主要起保护作用，减少金属复合，第一钝化层4具体的种类不做限定，本领域技术人员可以根据实际需要进行选择，例如第一钝化层4可以是氮化硅层，或其他金属氧化物与氮化硅的混合物层；背面的光面结构，使得背面具有良好的钝化效果；正面的绒面结构有利于增大正面电极7与硅基体的接触面积，改善接触电阻，降低表面复合；其中，正面的绒面结构可以是金字塔绒面结构。另外，背面电极5和正面电极7可以是常用的金属电电极，例如银金属栅线电极和铝金属栅线电极。It can be understood that the first passivation layer 4 on the back mainly plays a protective role and reduces metal recombination. The specific type of the first passivation layer 4 is not limited, and those skilled in the art can select according to actual needs, such as the first passivation layer 4 The nitride layer 4 can be a silicon nitride layer, or a mixture layer of other metal oxides and silicon nitride; the smooth structure on the back makes the back have a good passivation effect; the textured structure on the front is conducive to increasing the front electrode 7 The contact area with the silicon substrate improves the contact resistance and reduces surface recombination; wherein, the textured structure on the front side can be a pyramid textured structure. In addition, the back electrode 5 and the front electrode 7 may be commonly used metal electrodes, such as silver metal grid line electrodes and aluminum metal grid line electrodes.
还可以理解的是，正面电极在印刷过程中，一般可以是采用铝浆或者银铝浆，由于铝的价电子数为3，铝浆在与硅基体在印刷、烧结的过程中形成铝硅合金，如此形成P+层，一方面起到传导电流作用，另一方面起到场钝化作用，进而增强PN结分流光生载流子的效应，减少复合损失，提高电池效率。It can also be understood that during the printing process of the front electrode, aluminum paste or silver-aluminum paste can generally be used. Since the number of valence electrons of aluminum is 3, the aluminum paste forms an aluminum-silicon alloy during the printing and sintering process with the silicon substrate. In this way, the P+ layer is formed, on the one hand, it plays the role of conducting current, on the other hand, it plays the role of field passivation, thereby enhancing the effect of PN junction shunting photogenerated carriers, reducing recombination loss, and improving battery efficiency.
根据本申请实施例的太阳能电池，一方面通过在P型硅基体背面沉积氧化硅层和磷掺杂的多晶硅层，使得背面钝化效果好，并且背面电极不直接与P型硅基体接触，有效降低了金属复合，进而提高电池的开路电压，另一方面正面电极与钝化层接触的同时形成P+层，有效传导电流的同时起到场钝化作用，有利于增强PN结分流光生载流子的效应，减少复合损失，提高电池效率。According to the solar cell of the embodiment of the present application, on the one hand, by depositing a silicon oxide layer and a phosphorus-doped polysilicon layer on the back of the P-type silicon substrate, the back passivation effect is good, and the back electrode is not directly in contact with the P-type silicon substrate, effectively The metal recombination is reduced, thereby increasing the open circuit voltage of the battery. On the other hand, the front electrode contacts the passivation layer and forms a P+ layer at the same time, which can effectively conduct current and play a field passivation role, which is conducive to enhancing the PN junction to shunt photogenerated carriers. The effect of reducing recombination loss and improving battery efficiency.
在一些实施例中，隧穿氧化硅层2厚度小于2nm，磷掺杂的多晶硅层3厚度为110nm-130nm。In some embodiments, the thickness of the tunneling silicon oxide layer 2 is less than 2 nm, and the thickness of the phosphorus-doped polysilicon layer 3 is 110 nm-130 nm.
在优选的实施例中，隧穿氧化硅层2厚度为1.3nm-1.7nm，例如可以 是1.3nm，1.5nm，1.7nm；磷掺杂的多晶硅层3厚度为110nm-130nm，例如可以是110nm，115nm，120nm，125nm，130nm。本实施例中的氧化硅层厚度和磷掺杂的多晶硅层厚度，保证硅基体背面对金属接触具有优异的钝化作用，有效降低了背面金属接触下的复合，进而提高开路电压。In a preferred embodiment, the thickness of the tunneling silicon oxide layer 2 is 1.3nm-1.7nm, such as 1.3nm, 1.5nm, 1.7nm; the thickness of the phosphorus-doped polysilicon layer 3 is 110nm-130nm, such as 110nm , 115nm, 120nm, 125nm, 130nm. The thickness of the silicon oxide layer and the thickness of the phosphorus-doped polysilicon layer in this embodiment ensure that the backside of the silicon substrate has an excellent passivation effect on the metal contact, effectively reducing the recombination under the metal contact on the backside, thereby increasing the open circuit voltage.
在优选的实施例中，第一钝化层为氮化硅层。In a preferred embodiment, the first passivation layer is a silicon nitride layer.
在优选的实施例中，第二钝化层为氧化铝和氮化硅层。In a preferred embodiment, the second passivation layer is an aluminum oxide and silicon nitride layer.
进一步地，背面电极为银电极，正面电极为铝电极。Further, the back electrode is a silver electrode, and the front electrode is an aluminum electrode.
根据本申请实施例的一种太阳能电池的制备方法，包括如下步骤：A method for preparing a solar cell according to an embodiment of the present application includes the following steps:
S1、对P型硅基体的背面在低压化学气相沉积炉中依次沉积隧穿氧化硅层以及沉积多晶硅层，其中，P型硅基体边长182mm，厚度175um，倒角247mm；S1. On the back of the P-type silicon substrate, deposit a tunneling silicon oxide layer and a polysilicon layer sequentially in a low-pressure chemical vapor deposition furnace, wherein the side length of the P-type silicon substrate is 182mm, the thickness is 175um, and the chamfer is 247mm;
S2、对多晶硅层进行磷掺杂，得到磷掺杂的多晶硅层；S2. Doping the polysilicon layer with phosphorus to obtain a phosphorus-doped polysilicon layer;
S3、将P型硅基体的正面进行制绒，形成绒面结构；S3. Texturing the front side of the P-type silicon substrate to form a textured structure;
S4、在制绒后的P型硅基体的正面沉积氧化铝和氮化硅层，形成第二钝化层；S4. Deposit aluminum oxide and silicon nitride layers on the front side of the P-type silicon substrate after texturing to form a second passivation layer;
S5、在磷掺杂的多晶硅层上沉积氮化硅层，形成第一钝化层；S5, depositing a silicon nitride layer on the phosphorus-doped polysilicon layer to form a first passivation layer;
S6、在P型硅基体的正面和P型硅基体的背面分别印刷正面电极和背面电极。S6. Printing a front electrode and a back electrode on the front surface of the P-type silicon substrate and the back surface of the P-type silicon substrate, respectively.
需要说明的是，本申请实施例中S1步骤在低压化学气相沉积炉中对P型硅基体表面依次进行隧穿氧化硅层的沉积和多晶硅层的沉积，低压化学气相沉积炉能够分别实现隧穿氧化硅层的沉积和多晶硅层的沉积，无需在隧穿氧化硅层沉积完之后，取出硅基体再进行多晶硅层的沉积，操作简单方便，节省工艺流程；It should be noted that in the embodiment of the present application, step S1 in the low-pressure chemical vapor deposition furnace sequentially deposits the deposition of the silicon oxide layer and the deposition of the polysilicon layer on the surface of the P-type silicon substrate, and the low-pressure chemical vapor deposition furnace can realize tunneling respectively. The deposition of the silicon oxide layer and the deposition of the polysilicon layer do not need to take out the silicon substrate and then deposit the polysilicon layer after the tunneling silicon oxide layer is deposited, the operation is simple and convenient, and the process flow is saved;
步骤S2中将经过步骤S1处理有的硅基体放入磷扩散炉中，在硅基体的背面进行磷掺杂，形成PSG层，进一步提高了背面的钝化效果，并且PSG能够有效保护背面，在后续制绒处理中无需背面进行掩模保护，即可保证背面结构不被蚀刻，相比传统工艺路线省去了去绕度工艺，进一步缩短工艺步骤，进而有利于降低电池制造成本；In step S2, the silicon substrate treated in step S1 is put into a phosphorus diffusion furnace, and phosphorus is doped on the back side of the silicon substrate to form a PSG layer, which further improves the passivation effect of the back side, and PSG can effectively protect the back side. In the subsequent texturing process, there is no need for mask protection on the back side, which can ensure that the back structure will not be etched. Compared with the traditional process route, the dewinding process is omitted, and the process steps are further shortened, which in turn helps to reduce the cost of battery manufacturing;
步骤S3中对硅基体进行正面制绒，将硅基体浸入盛放有制绒液的槽式制绒清洗机，制绒液对硅基体的正面进行蚀刻，其中控制蚀刻时间和 温度，保证蚀刻量在0.6±0.05g，形成正面绒面结构。此处，控制温度和时间应当避免时间过长或者温度过高影响背面结构，同时延长整个工艺的时间；In step S3, the front side of the silicon substrate is textured, and the silicon substrate is immersed in a tank-type texturing cleaning machine containing a texturing liquid, and the texturing liquid etches the front side of the silicon substrate, wherein the etching time and temperature are controlled to ensure the amount of etching At 0.6±0.05g, a front suede structure is formed. Here, the temperature and time should be controlled to avoid excessive time or high temperature from affecting the back structure, and at the same time prolong the time of the entire process;
在上述步骤完成后，依次执行步骤S4、S5和S6即可得到太阳能电池。After the above steps are completed, step S4, S5 and S6 are executed in sequence to obtain the solar cell.
根据本申请实施例的方法，具有如下优势：The method according to the embodiment of the present application has the following advantages:
(1)基于本申请的太阳能电池结构，该电池是背结电池，PN结在背面，光生载流子在正表面至PN结范围内主要是纵向传输，横向传输较少，所以正面电极与硅基体接触足够好的情况下，无需对硅基体正面进行硼掺杂，简化了工艺流程，降低了制造成本，同时避免了硼扩散路线高温工艺对硅基体寿命的影响，也避免了硼浆+激光路线激光对硅基体造成损伤的难题；(1) Based on the solar cell structure of the present application, the cell is a back-junction cell, the PN junction is on the back side, and the photogenerated carriers are mainly transported vertically in the range from the front surface to the PN junction, and the lateral transport is less, so the front electrode and silicon When the substrate contact is good enough, there is no need to do boron doping on the front of the silicon substrate, which simplifies the process flow and reduces the manufacturing cost. At the same time, it avoids the impact of the high temperature process of the boron diffusion route on the life of the silicon substrate, and also avoids boron paste + laser The problem of damage to the silicon substrate caused by the route laser;
(2)制绒处理可以去除正面PSG层同时实现正面单面制绒，并且背面PSG层为掩膜保护背面结构不被刻蚀，相比传统工艺路线省去了去绕镀工艺，进一步缩短工艺步骤，降低了电池制造成本；(2) The texturing process can remove the front PSG layer and realize single-sided texturing on the front, and the back PSG layer is a mask to protect the back structure from being etched. Compared with the traditional process route, the dewinding and plating process is omitted, and the process is further shortened steps, reducing battery manufacturing costs;
(3)能够有效突破Perc电池的效率瓶颈，经过实验对比发现本申请实施例方法可产出平均量产效率大约24.5％abs的太阳能电池；并且工艺简单，在传统Perc电池线的基础上进行升级改造，投资成本较低，收益较大。(3) It can effectively break through the efficiency bottleneck of the Perc battery. Through experimental comparison, it is found that the method of the embodiment of the present application can produce solar cells with an average mass production efficiency of about 24.5% abs; and the process is simple, and it is upgraded on the basis of the traditional Perc battery line Transformation, lower investment cost, higher income.
进一步地，在S1、对P型硅基体的背面依次沉积隧穿氧化硅层以及沉积多晶硅层之前，还包括：Further, before S1, sequentially depositing a tunneling silicon oxide layer and depositing a polysilicon layer on the back of the P-type silicon substrate, it also includes:
将P型硅基体盛有抛光液的清洗机中进行抛光处理，其中，抛光液包括水、碱液和添加剂，添加剂包括表面活性剂，柠檬酸钠，苯甲酸钠，抛光处理的温度为53℃-57℃，时间为215s-225s；其中添加剂的厂家可以是拓邦BP51，在具体使用时，抛光液中H 2O：KOH：添加剂的配比可以是340：16：4。 The P-type silicon substrate is polished in a cleaning machine filled with polishing liquid, wherein the polishing liquid includes water, lye and additives, the additives include surfactants, sodium citrate, and sodium benzoate, and the temperature of the polishing treatment is 53°C- 57°C, the time is 215s-225s; the manufacturer of the additives can be Topband BP51, and in specific use, the ratio of H 2 O:KOH:additives in the polishing solution can be 340:16:4.
其中，抛光液中碱液可以是质量浓度为大约4％的氢氧化钾溶液，当然也可以是其他碱液；本实施方式中公开的抛光处理温度和时间，有利于保证对硅基体的蚀刻量0.2±0.02g，有利于清洗干净硅基体表面，使得硅基体表面的反射率达到一定要求，同时保证后续步骤的可靠进行。Wherein, the lye in the polishing solution can be a potassium hydroxide solution with a mass concentration of about 4%, and of course it can also be other lye; the polishing treatment temperature and time disclosed in this embodiment are conducive to ensuring the etching amount of the silicon substrate 0.2±0.02g, which is conducive to cleaning the surface of the silicon substrate, so that the reflectivity of the surface of the silicon substrate can meet a certain requirement, and at the same time ensure the reliable progress of the subsequent steps.
进一步地，在将P型硅基体盛有抛光液的清洗机中进行抛光处理后，P型硅基体的正面和背面的反射率为38％-44％。Further, after polishing the P-type silicon substrate in a cleaning machine filled with polishing liquid, the reflectivity of the front and back surfaces of the P-type silicon substrate is 38%-44%.
在一些实施例中，在将P型硅基体的正面进行制绒，形成绒面结构之前，还包括：In some embodiments, before the front side of the P-type silicon substrate is textured to form a textured structure, it also includes:
将P型硅基体的正面在室温下，置于盛有氢氟酸的洗液中，去除P型硅基体的正面的PSG；其中，氢氟酸的洗液质量浓度为8％-12％。The front side of the P-type silicon substrate is placed in a washing solution filled with hydrofluoric acid at room temperature to remove the PSG on the front side of the P-type silicon substrate; wherein, the mass concentration of the washing solution of hydrofluoric acid is 8%-12%.
需要说明的是，在上述步骤S2中，对多晶硅层进行磷掺杂时，在硅基体的正面同样形成了PSG层，为了保证硅基体表面形成可靠的绒面结构，降低制绒步骤的工艺条件，因此，可将硅基体至于链式去PSG清洗机中，使得硅基体正面接触清洗机中的制绒液，同时对背面进喷水保护，保证氢氟酸洗液只蚀刻硅基体正面的PSG，在正面形成绒面结构，保证背面的光面结构。It should be noted that in the above step S2, when the polysilicon layer is doped with phosphorus, a PSG layer is also formed on the front side of the silicon substrate. In order to ensure a reliable textured structure on the surface of the silicon substrate, the process conditions of the texturing step are reduced. Therefore, the silicon substrate can be placed in the chain-type PSG cleaning machine, so that the front of the silicon substrate contacts the texturing liquid in the cleaning machine, and at the same time, the back is protected by spraying water to ensure that the hydrofluoric acid cleaning solution only etches the PSG on the front of the silicon substrate. , forming a suede structure on the front to ensure a smooth structure on the back.
在优选的实施例中，将P型硅基体的正面进行制绒，形成绒面结构，包括：In a preferred embodiment, the front side of the P-type silicon substrate is textured to form a textured structure, including:
将P型硅基体浸入制绒液中，进行制绒；其中，制绒液包括KOH溶液，KOH溶液的质量浓度为0.5％-1.5％；制绒液温度为77℃-83℃，P型硅基体浸入制绒液的时间为495s-505s。The P-type silicon substrate is immersed in the texturing liquid for texturing; wherein, the texturing liquid includes KOH solution, and the mass concentration of the KOH solution is 0.5%-1.5%; the temperature of the texturing liquid is 77°C-83°C, and the P-type silicon The time for the substrate to be immersed in the texturing solution is 495s-505s.
可以理解的是，为了改善绒面结构的形貌，制绒液还包括一些添加剂，添加剂包括表面活性剂，成核剂，分散剂，催化剂以及消泡剂，例如，厂家是时创TS53的添加剂。It can be understood that, in order to improve the appearance of the suede structure, the suede liquid also includes some additives, the additives include surfactants, nucleating agents, dispersants, catalysts and defoamers, for example, the manufacturer is Shichuang TS53 additives .
本实施方式中，制绒液温度可以是77℃、78℃、80℃、81℃、83℃，P型硅基体浸入制绒液的时间可以是495s、497s、499s、501s、503s、505s。本实施方式公开的温度和时间有利于保证在正面形成合适的绒面结构，同时不会对背面进行蚀刻，条件温和，易于实现。In this embodiment, the temperature of the texturing liquid can be 77°C, 78°C, 80°C, 81°C, 83°C, and the time for the P-type silicon substrate to be immersed in the texturing liquid can be 495s, 497s, 499s, 501s, 503s, 505s. The temperature and time disclosed in this embodiment are beneficial to ensure the formation of a suitable suede structure on the front side without etching the back side. The conditions are mild and easy to implement.
进一步地，将P型硅基体的正面进行制绒，形成绒面结构，其中，绒面结构的反射率为8.7％-9.3％。Further, the front surface of the P-type silicon substrate is textured to form a textured structure, wherein the reflectance of the textured structure is 8.7%-9.3%.
在一些实施例中，在P型硅基体的正面印刷正面电极之前，包括：In some embodiments, before printing the front electrode on the front side of the P-type silicon substrate, including:
将P型硅基体的正面需要设置正面电极的区域，进行激光处理，以打开第二钝化层。The area on the front side of the P-type silicon substrate where the front electrode needs to be provided is subjected to laser treatment to open the second passivation layer.
本实施例中通过激光打开第二钝化层，方便印刷正面电极，保证正面电极和硅基体接触。In this embodiment, the second passivation layer is opened by laser to facilitate the printing of the front electrode and ensure the contact between the front electrode and the silicon substrate.
在优选的实施例中，P型硅基体的正面印刷正面电极，其中，正面电极浆料采用铝浆。本实施例中，铝浆代替传统的银铝浆，成本低，进一步降低电池制造成本。In a preferred embodiment, the front electrode is printed on the front surface of the P-type silicon substrate, wherein the paste for the front electrode is aluminum paste. In this embodiment, the aluminum paste replaces the traditional silver-aluminum paste, which has low cost and further reduces the battery manufacturing cost.
下面通过一个具体实施例对本发明进行说明，需要说明的是，下面的具体实施例仅仅是用于说明的目的，而不以任何方式限制本发明的范围，另外，如无特殊说明，未具体记载条件或者步骤的方法均为常规方法，所采用的试剂和材料均可从商业途径获得。The present invention is described below through a specific embodiment. It should be noted that the following specific embodiment is only for the purpose of illustration, and does not limit the scope of the present invention in any way. In addition, if there is no special description, no specific record The conditions and steps are conventional methods, and the reagents and materials used can be obtained from commercial sources.
实施例1Example 1
通过如下步骤制备一种太阳能电池：Prepare a solar cell by the following steps:
第一步、将P型硅基体置于盛有抛光液的清洗机中进行抛光处理，P型硅基体边长182mm，厚度175um，倒角247mm，其中，抛光液包括水、KOH和添加剂，添加剂为拓邦BP51，抛光处理的温度为55℃，时间为220s，抛光前后称重得出蚀刻量为大约0.2g，硅基体正面和背面的反射率均大约在41％；The first step is to place the P-type silicon substrate in a cleaning machine filled with polishing liquid for polishing. The side length of the P-type silicon substrate is 182mm, the thickness is 175um, and the chamfer is 247mm. The polishing liquid includes water, KOH and additives. Additives For Topband BP51, the temperature of the polishing treatment is 55°C, the time is 220s, the weighing before and after polishing shows that the etching amount is about 0.2g, and the reflectivity of the front and back of the silicon substrate is about 41%;
第二步、对P型硅基体的背面在低压化学气相沉积炉中依次沉积隧穿氧化硅层以及沉积多晶硅层；其中，隧穿氧化硅层厚度为1.5nm，P多晶硅层厚度为120nm；The second step is to sequentially deposit a tunneling silicon oxide layer and a polysilicon layer on the back of the P-type silicon substrate in a low-pressure chemical vapor deposition furnace; wherein, the thickness of the tunneling silicon oxide layer is 1.5nm, and the thickness of the P polysilicon layer is 120nm;
第三步、将硅基体置于在磷扩散炉中对多晶硅层进行磷掺杂，得到磷掺杂的多晶硅层；In the third step, the silicon substrate is placed in a phosphorus diffusion furnace to perform phosphorus doping on the polysilicon layer to obtain a phosphorus-doped polysilicon layer;
第四步、室温下在链式去PSG清洗机中，使用质量浓度为10％的氢氟酸，使得硅基体正面进入氢氟酸中，背面喷水保护，去除正面PSG层；Step 4: Use hydrofluoric acid with a mass concentration of 10% in the chain-type PSG removal machine at room temperature, so that the front side of the silicon substrate enters the hydrofluoric acid, spray water on the back side, and remove the front PSG layer;
第五步、将上述处理后的硅基体投入盛放有制绒液的槽式制绒清洗机中进行正面碱制绒处理，其中，制绒液为质量浓度大约1％的KOH溶液，以及制绒添加剂溶液，制绒液的配比为H 2O：KOH：添加剂＝354：5.5：2，添加剂的型号为时创TS53；温度80℃，时间500s；制绒前后称重得出单片硅基体蚀刻量大约0.6g，经过测试，正面的反射率大约为9％； The fifth step, put the above-mentioned treated silicon substrate into a tank-type texturing cleaning machine filled with texturing liquid for frontal alkali texturing treatment, wherein the texturing liquid is a KOH solution with a mass concentration of about 1%, and Texture additive solution, the ratio of the texturing liquid is H 2 O:KOH:additive=354:5.5:2, the type of additive is Shichuang TS53; the temperature is 80°C, the time is 500s; the monolithic silicon is weighed before and after texturing. The amount of substrate etching is about 0.6g, after testing, the reflectivity of the front is about 9%;
第六步、在制绒后的P型硅基体的正面沉积氧化铝和氮化硅层，形成第二钝化层；The sixth step is to deposit aluminum oxide and silicon nitride layers on the front side of the P-type silicon substrate after texturing to form a second passivation layer;
第七步、在磷掺杂的多晶硅层上沉积氮化硅层，形成第一钝化层； Step 7, depositing a silicon nitride layer on the phosphorus-doped polysilicon layer to form a first passivation layer;
第八步、对P型硅基体的正面进行激光处理，打开第二钝化层；The eighth step is to perform laser treatment on the front side of the P-type silicon substrate to open the second passivation layer;
第九步、在P型硅基体的正面打开第二钝化层处和P型硅基体的背面分别丝网印刷及烧结铝电极和银电极，测试分选。Step 9: Open the second passivation layer on the front of the P-type silicon substrate and the back of the P-type silicon substrate by screen printing and sintering aluminum electrodes and silver electrodes respectively, and test sorting.
经过测试，实施例1制备的电池与常规Perc电池对比，结果如表1所示：After testing, the battery prepared in Example 1 was compared with the conventional Perc battery, and the results are shown in Table 1:
表1 实施例1制备的电池与常规Perc电池的性能结果Table 1 The performance results of the battery prepared in Example 1 and the conventional Perc battery
 the Eta(％)Eta(%) Isc(A)Isc(A) Uoc(V)Uoc(V) FF(％)FF(%)
实施例1Example 1 24.5024.50 13.5713.57 0.7230.723 82.4182.41
Perc电池Perc battery 23.5023.50 13.3513.35 0.7070.707 82.2382.23
上述表格中，Eta代表转化效率，Isc代表短路电流，Uoc代表开路电压，FF代表填充因子。In the above table, Eta represents conversion efficiency, Isc represents short circuit current, Uoc represents open circuit voltage, and FF represents fill factor.
从上述表格中可得出，本申请实施例的方法制备得到的电池，在转化效率、短路电流、开路电压以及填充因子方面均优于现有的Perc电池，进一步说明本申请实施例的制备方法制备的得到的电池，能够有效改善现有Perc电池的性能，突破了Perc电池的效率瓶颈，有望替代Perc电池。It can be concluded from the above table that the battery prepared by the method of the embodiment of the present application is superior to the existing Perc battery in terms of conversion efficiency, short-circuit current, open-circuit voltage and fill factor, further illustrating the preparation method of the embodiment of the present application The prepared battery can effectively improve the performance of the existing Perc battery, break through the efficiency bottleneck of the Perc battery, and is expected to replace the Perc battery.
在本发明的一个方面，本发明提出了一种太阳能电池及其制备方法。根据本发明的实施例，参考图2所示，该方法包括：In one aspect of the invention, the invention provides a solar cell and a preparation method thereof. According to an embodiment of the present invention, as shown in FIG. 2, the method includes:
(1)提供单面含有硼扩散的N型硅片(1) Provide N-type silicon wafers with boron diffusion on one side
根据本发明的实施例，该单面含有硼扩散的N型硅片可以通过对N型裸硅片进行双面制绒和硼扩散处理处理，并去除背面的BSG层得到。其中，通过对N型裸硅片进行双面制绒可以在硅基体表面形成金字塔形绒面结构，对制绒后的硅片进行硼扩散处理，可以在硅片表面形成BSG层，在进行背面抛光处理前，可以仅去除硅片背面的BSG层，并保留硅片正面的BSG层。需要说明的是，对N型裸硅片进行双面制绒、硼扩散处理以及去除硅片背面BSG层时采用的工艺条件并不受特别限制，本领域技术人员可以根据实际需要进行选择。According to an embodiment of the present invention, the N-type silicon wafer containing boron diffusion on one side can be obtained by performing double-sided texturing and boron diffusion treatment on the N-type bare silicon wafer, and removing the BSG layer on the back side. Among them, by performing double-sided texturing on the N-type bare silicon wafer, a pyramid-shaped textured structure can be formed on the surface of the silicon substrate. After boron diffusion treatment is performed on the silicon wafer after texturing, a BSG layer can be formed on the surface of the silicon wafer. Before polishing, only the BSG layer on the backside of the silicon wafer can be removed, and the BSG layer on the front side of the silicon wafer can be retained. It should be noted that the process conditions used for double-sided texturing, boron diffusion treatment, and removal of the BSG layer on the back of the silicon wafer for the N-type bare silicon wafer are not particularly limited, and those skilled in the art can choose according to actual needs.
根据本发明的一个具体实施例，可以将N型裸硅片投入槽式制绒清洗机中进行碱制绒处理，其中，制绒液可以包括碱和制绒添加剂，制绒液中碱和制绒添加剂的种类并不受特别限制，本领域技术人员可以根据实际需要进行选择，例如，碱可以为KOH和/或NaOH，碱的浓度可以为1wt％左右，制绒添加剂可以为本领域常规的制绒添加剂，制绒液的温度可以为80℃±3℃，制绒处理的时间可以为500s±15s，通过控制该双面制绒条件，可以成功在N型裸硅片正面和背面均形成金字塔结构，其中，制绒后硅片表面的反射率可达到9％左右，由此可以进一步降低光学损失，保证最终制得的电池片对光 能的高利用率。According to a specific embodiment of the present invention, the N-type bare silicon wafer can be put into a tank-type texturing cleaning machine for alkali texturing treatment, wherein the texturing liquid can include alkali and texturing additives, and the alkali and texturing additives in the texturing liquid The kind of velvet additive is not particularly limited, and those skilled in the art can select according to actual needs, for example, alkali can be KOH and/or NaOH, and the concentration of alkali can be about 1wt%, and velvet additive can be conventional in this field. Texturing additives, the temperature of the texturing liquid can be 80°C±3°C, and the time of texturing treatment can be 500s±15s. By controlling the double-sided texturing conditions, it can be successfully formed on both the front and back of the N-type bare silicon wafer. Pyramid structure, in which the reflectivity of the surface of the silicon wafer after texturing can reach about 9%, which can further reduce the optical loss and ensure the high utilization rate of light energy of the final solar cell.
根据本发明的再一个具体实施例，可以将双面制绒后的硅片置于硼扩散炉管中进行硼扩散处理，其中硼扩散温度可以为950℃±50℃，其中可以使经硼扩散处理得到的硅片的方阻达到120Ω/sq±20Ω/sq，由此更有利于结合后续工艺使最终制得的电池片具有理想的方阻值。According to yet another specific embodiment of the present invention, the double-sided textured silicon wafer can be placed in a boron diffusion furnace tube for boron diffusion treatment, wherein the boron diffusion temperature can be 950°C ± 50°C, wherein the boron diffusion can be made The square resistance of the processed silicon wafer reaches 120Ω/sq±20Ω/sq, which is more conducive to combining with the subsequent process to make the final battery sheet have an ideal square resistance value.
根据本发明的又一个具体实施例，可以采用氢氟酸对硼扩散处理得到的硅片进行处理，以便去除硅片背面的BSG层，具体地，可以将硼扩散处理得到的硅片置于链式去BSG清洗机中，采用浓度为40±5wt％浓度的氢氟酸来去除硅片背面的BSG层，控制的工艺温度可以为20℃左右，由此可以确保硅片背面的BSG层能被有效去除。According to yet another specific embodiment of the present invention, the silicon wafer obtained by boron diffusion treatment can be treated with hydrofluoric acid so as to remove the BSG layer on the back of the silicon wafer. Specifically, the silicon wafer obtained by boron diffusion treatment can be placed in a chain In the type BSG cleaning machine, hydrofluoric acid with a concentration of 40±5wt% is used to remove the BSG layer on the back of the silicon wafer, and the controlled process temperature can be about 20°C, thereby ensuring that the BSG layer on the back of the silicon wafer can be cleaned. Effective removal.
(2)以硅片背离硼扩散的一侧为背面，对所述硅片进行背面抛光处理，在硅片背面形成预期尺寸的方块形貌(2) With the side of the silicon wafer facing away from the boron diffusion as the back, the silicon wafer is subjected to back polishing treatment to form a square shape of expected size on the back of the silicon wafer
根据本发明的实施例，发明人发现，硅片背面钝化膜在更大方块、平整的硅基体上沉积的更加致密，钝化效果更好，但为了兼容电池背面金属的接触性能，硅片背面碱抛方块的尺寸又不能过大，目前只能控制在5μm左右，鉴于此，本发明的主要目的在于打破硅片背面碱抛方块的尺寸对电池背面金属的接触性能的限制，为达到该目的，发明人设想，可以将电池背面的非金属接触区域(即硅片背面不与电极接触的区域)与金属接触区域(即硅片背面与电极接触的区域)的结构区别开来，参考图3理解，针对电池背面的非金属接触区域，可以提高硅片背面的小方块结构的方块尺寸，进而提高背面钝化效果，而针对电池背面的金属接触区域，可以通过激光开槽(其中激光开槽区域如图3中17所示)和制绒工艺在硅片背面的金属接触区域形成绒面金字塔结构，进而提高硅片背面与电极的接触效果，提高导电性，由此可以有效解决硅片背面碱抛方块的尺寸对电池背面金属的接触性能的限制，从而既可以提高硅片背面的钝化效果，还能保证硅片背面与电极的良好接触，提高导电性。According to the embodiments of the present invention, the inventors have found that the passivation film on the back of the silicon wafer is more densely deposited on a larger square and flat silicon substrate, and the passivation effect is better. However, in order to be compatible with the contact performance of the metal on the back of the battery, the silicon wafer The size of the alkali throwing square on the back side cannot be too large, and it can only be controlled at about 5 μm at present. In view of this, the main purpose of the present invention is to break the limitation of the size of the alkali throwing square on the back side of the silicon wafer to the contact performance of the metal on the back of the battery. Purpose, the inventor imagined that the structure of the non-metal contact area on the back of the battery (i.e. the area where the back of the silicon wafer is not in contact with the electrodes) and the structure of the metal contact area (i.e. the area where the back of the silicon wafer is in contact with the electrodes) can be distinguished, refer to Fig. 3Understanding, for the non-metal contact area on the back of the battery, the square size of the small square structure on the back of the silicon wafer can be increased, thereby improving the passivation effect on the back, and for the metal contact area on the back of the battery, laser slotting (wherein laser opening The groove area is shown as 17 in Figure 3) and the texture process forms a textured pyramid structure in the metal contact area on the back of the silicon wafer, thereby improving the contact effect between the back of the silicon wafer and the electrode, and improving the conductivity, thereby effectively solving the problem of silicon wafer The size of the alkali-polished square on the back side limits the contact performance of the metal on the back of the battery, which can not only improve the passivation effect on the back of the silicon wafer, but also ensure good contact between the back of the silicon wafer and the electrode, and improve conductivity.
根据本发明的一些具体实施例，背面抛光处理形成的方块形貌中，方块尺寸可以为20μm±2μm，例如可以为19μm、19.5μm、20μm、20.5μm或21μm等，发明人发现，若硅片背面的方块尺寸过小，难以有效改善硅片背面的钝化效果，而若硅片背面的方块尺寸过大，刻蚀量较大，硅片会变的更薄，电池可靠性降低，本发明中通过控制硅片背面的方块尺寸为上述范围，既可以确保电池背面非金属接触区域能够具有较好的钝化效果，还能保证刻蚀量不 会过大，保证电池的可靠性，同时反应所需时间相对较短，能够提高生产效率并降低成本。According to some specific embodiments of the present invention, in the square shape formed by the back polishing process, the square size can be 20 μm±2 μm, for example, it can be 19 μm, 19.5 μm, 20 μm, 20.5 μm or 21 μm, etc. The inventors found that if the silicon wafer If the square size on the back side is too small, it is difficult to effectively improve the passivation effect on the back side of the silicon wafer, and if the square size on the back side of the silicon wafer is too large, the amount of etching will be larger, the silicon wafer will become thinner, and the reliability of the battery will be reduced. By controlling the size of the square on the back of the silicon wafer to the above range, it can not only ensure that the non-metallic contact area on the back of the battery can have a good passivation effect, but also ensure that the amount of etching will not be too large to ensure the reliability of the battery. The relatively short time required increases productivity and reduces costs.
根据本发明的再一些具体实施例，可以使背面抛光处理后，硅片背面的反射率达到42％±1％，发明人发现，硅片背面的反射率越高，说明硅片背面形成的方块越平整，此外硅片尺寸较大也可以提升硅片背面的反射率，本发明中通过控制硅片背面的反射率为上述范围，可以确保在硅片基体背面能够形成较为致密的钝化膜，由此可以进一步保证钝化效果。According to some further specific embodiments of the present invention, after the back polishing treatment, the reflectivity of the backside of the silicon wafer can reach 42% ± 1%. The smoother, and the larger size of the silicon wafer can also improve the reflectivity of the silicon wafer backside. In the present invention, by controlling the reflectivity of the silicon wafer backside to the above range, it can be ensured that a denser passivation film can be formed on the silicon wafer substrate backside. The passivation effect can thus be further ensured.
根据本发明的又一些具体实施例，本发明中以厚度为170μm±10μm、边长为182mm±0.25mm、倒角直径为247mm±0.25mm的182硅片为基准(或以厚度为170μm±10μm、硅片平面面积为330.15cm 2的182芯片为基准)，背面抛光处理的刻蚀量可以为0.58g±0.05g，常规工艺中背面抛光处理的刻蚀量约为0.16g左右，但发明人发现，若背面抛光处理的刻蚀量过小，难以充分去除电池侧面、背面绕扩层，而若背面抛光处理的刻蚀量过大，硅片会变的更薄，电池可靠性降低，同时反应时间相对较长，会降低生产效率并增加成本，本发明中通过控制上述刻蚀量范围，可以确保能够完全去除电池侧面、背面绕扩层，保证较好的电池并联电阻，防止漏电，同时还能保证电池的可靠性。 According to still some specific embodiments of the present invention, the 182 silicon wafers with a thickness of 170 μm ± 10 μm, a side length of 182 mm ± 0.25 mm, and a chamfer diameter of 247 mm ± 0.25 mm are used as a reference (or a thickness of 170 μm ± 10 μm 182 chips with a plane area of 330.15cm2 as the reference), the etching amount of the back polishing treatment can be 0.58g ± 0.05g, and the etching amount of the back polishing treatment in the conventional process is about 0.16g, but the inventor It is found that if the etching amount of the back polishing treatment is too small, it is difficult to fully remove the side and back of the battery, and if the etching amount of the back polishing treatment is too large, the silicon wafer will become thinner and the reliability of the battery will be reduced. The reaction time is relatively long, which will reduce production efficiency and increase costs. In the present invention, by controlling the above-mentioned etching amount range, it can ensure that the side and back of the battery can be completely removed, ensuring better parallel resistance of the battery and preventing leakage. It also ensures the reliability of the battery.
根据本发明的又一些具体实施例，为了使硅片背面能够形成较大尺寸的碱抛方块，需要选择适宜的抛光条件，其中，采用的抛光液可以包括碱和抛光添加剂，抛光液中碱和抛光添加剂的种类并不受特别限制，本领域技术人员可以根据实际需要进行选择，例如，碱可以包括KOH和/或NaOH，抛光添加剂可以为本领域常用的抛光添加剂，进一步地，碱的体积浓度可以为4v％±0.2v％，针对该抛光液，抛光处理的温度可以为65℃±3℃，时间可以为400s±20s，其中可以在槽式清洗机中进行硅片背面抛光处理，发明人经大量试验验证发现，以厚度为170μm±10μm、硅片平面面积为330.15cm 2的182芯片为基准，通过控制上述抛光条件，更有利于获得背面形貌为尺寸为20μm±2μm、背面反射率为42％±1％、且刻蚀量为0.58g±0.05g的硅片，由此不仅更有利于使最终制得的电池片背面非金属区域具有较好的钝化效果，还能保证较好的电池并联电阻，防止漏电。 According to still some specific embodiments of the present invention, in order to enable the back side of the silicon wafer to form larger-sized alkali-polished squares, it is necessary to select suitable polishing conditions, wherein the polishing liquid used may include alkali and polishing additives, alkali and polishing additives in the polishing liquid. The kind of polishing additive is not particularly limited, and those skilled in the art can select according to actual needs, for example, alkali can comprise KOH and/or NaOH, and polishing additive can be the polishing additive commonly used in this field, further, the volume concentration of alkali It can be 4v%±0.2v%. For this polishing solution, the temperature of the polishing treatment can be 65°C±3°C, and the time can be 400s±20s, wherein the backside of the silicon wafer can be polished in a tank cleaning machine. The inventor After a large number of experiments and verifications, it is found that based on the 182 chip with a thickness of 170μm±10μm and a silicon wafer plane area of 330.15cm 2 , by controlling the above polishing conditions, it is more conducive to obtaining a back surface with a size of 20μm±2μm and a back reflectivity. 42% ± 1%, and the etching amount is 0.58g ± 0.05g, which is not only more conducive to the better passivation effect of the non-metallic area on the back of the final cell, but also ensures a higher A good battery is connected in parallel to prevent leakage.
(3)在步骤(2)得到的硅片背面沉积硅氧化合物层(3) deposition of a silicon oxide compound layer on the back side of the silicon wafer obtained in step (2)
根据本发明的实施例，可以在常压化学气相淀积设备(APCVD)中在电池背面沉积一层SiOx层，具体可以为二氧化硅层，其中，硅氧化合物层的厚 度可以为90～150nm，例如可以为95nm、100nm、105nm、115nm、125nm、135nm或145nm等，发明人发现，若该硅氧化合物层厚度过小，难以确保对硅基体的保护效果，在后续激光开槽后进行的制绒处理中，不能有效阻挡制绒液中的碱对硅基体的破坏，而若硅氧化合物层厚度过大，不仅影响制备效率还会导致原料浪费，同时还会增加后续激光开槽时的难度，本发明中通过控制硅氧化合物层为上述厚度范围，不仅可以对硅基体起到较好的保护作用，还有利于提高整个制备工艺的制备效率。According to an embodiment of the present invention, a layer of SiOx can be deposited on the back of the battery in an atmospheric pressure chemical vapor deposition device (APCVD), specifically a silicon dioxide layer, wherein the thickness of the silicon oxide layer can be 90-150 nm , for example, can be 95nm, 100nm, 105nm, 115nm, 125nm, 135nm or 145nm, etc. The inventors found that if the thickness of the silicon oxide compound layer is too small, it is difficult to ensure the protective effect on the silicon substrate. In the texturing process, the alkali in the texturing solution cannot effectively prevent the damage to the silicon matrix, and if the thickness of the silicon oxide compound layer is too large, it will not only affect the production efficiency but also lead to waste of raw materials, and will also increase the subsequent laser grooving. Difficulty, in the present invention, by controlling the thickness of the silicon oxide compound layer to the above range, it can not only protect the silicon substrate better, but also help to improve the production efficiency of the entire production process.
(4)对硅氧化合物层进行局部激光开槽，以便去除开槽部位的硅氧化合物层并对下层硅进行烧灼，形成倒金字塔结构(4) Partial laser grooving is performed on the silicon oxide compound layer to remove the silicon oxide compound layer at the grooved part and burn the underlying silicon to form an inverted pyramid structure
根据本发明的实施例，可以在紫外激光器上对电池背面的硅氧化合物层(SiOx层)进行激光开槽(激光区域如图3中17所示)，此处开槽的图形与后续在硅片背面形成的金属细栅线图形一致，在去除该图形区域的表层SiOx后，激光同时对下层的硅进行烧灼，形成倒金字塔结构，最后在电池4个角落打上Mark点，用于后道丝网印刷时对准。其中，后续在硅片背面形成的金属栅线设置在对应开槽图形的位置，对电池背面的硅氧化合物层进行激光开槽，可以将硅基体裸露出来并形成倒金字塔结构，在硅片背面金属化区域(即与背面电极接触的区域)，硅基体通过倒金字塔结构与金属浆料接触，相互接触面积更大，接触电阻更小，串联电阻也相应更小，可以进一步提高导电效果，由此，即便电池背面非金属接触具有较大碱抛方块尺寸，也能保证硅基体与电极的良好接触效果，提高导电性。According to an embodiment of the present invention, the silicon oxide compound layer (SiOx layer) on the battery backside can be laser-grooved on the ultraviolet laser (the laser region is shown as 17 in Fig. 3), and the pattern of groove here is the same as that in the subsequent silicon oxide layer. The pattern of metal fine grid lines formed on the back of the chip is consistent. After removing the surface layer SiOx in the pattern area, the laser burns the underlying silicon at the same time to form an inverted pyramid structure. Finally, Mark points are marked on the 4 corners of the battery for the subsequent wire Alignment during screen printing. Among them, the metal grid line formed on the back of the silicon wafer is set at the position corresponding to the groove pattern, and the silicon oxide compound layer on the back of the battery is laser grooved to expose the silicon substrate and form an inverted pyramid structure. On the back of the silicon wafer In the metallized area (that is, the area in contact with the back electrode), the silicon substrate contacts the metal paste through an inverted pyramid structure, the mutual contact area is larger, the contact resistance is smaller, and the series resistance is correspondingly smaller, which can further improve the conductive effect. Therefore, even if the non-metallic contact on the back of the battery has a larger size of the alkali-polished square, it can ensure a good contact effect between the silicon substrate and the electrode, and improve the conductivity.
根据本发明的一些具体实施例，激光开槽的功率可以为20W±5W，频率可以为40000Hz±2000Hz，发明人发现，若激光功率过小或频率过低，均难以实现较好的激光开槽效果和对下层硅的灼烧效果，而若激光功率过大或频率过高，又难以控制激光程度，不利于形成预期的金字塔结构，本发明中通过控制上述激光条件，可以确保能够在硅片背面的金属接触区域形成较好的倒金字塔结构，从而更有利于提高硅片背面与电极的接触效果，提高导电性。According to some specific embodiments of the present invention, the power of laser grooving can be 20W±5W, and the frequency can be 40000Hz±2000Hz. The inventors found that if the laser power is too small or the frequency is too low, it is difficult to achieve better laser grooving effect and the burning effect on the lower silicon, and if the laser power is too high or the frequency is too high, it is difficult to control the laser level, which is not conducive to the formation of the expected pyramid structure. In the present invention, by controlling the above laser conditions, it can be ensured that the silicon wafer The metal contact area on the back forms a better inverted pyramid structure, which is more conducive to improving the contact effect between the back of the silicon wafer and the electrode, and improving conductivity.
(5)对步骤(4)得到的硅片进行背面腐蚀处理，并去除未激光区域的硅氧化合物层；(5) Carry out backside etching treatment to the silicon wafer that step (4) obtains, and remove the silicon oxide compound layer of non-laser region;
根据本发明的实施例，对硅片进行背面腐蚀处理的主要目的是消除上步激光烧灼形成的损伤层，同时修饰倒金字塔结构，最后，可以采用氢氟酸将未激光区域的SiOx层去除掉。According to the embodiment of the present invention, the main purpose of carrying out the backside etching treatment on the silicon wafer is to eliminate the damaged layer formed by laser ablation in the previous step, and modify the inverted pyramid structure at the same time. Finally, the SiOx layer in the non-laser area can be removed by hydrofluoric acid .
根据本发明的一个具体实施例，可以将硅片投入槽式制绒清洗机中进行 背面腐蚀处理，其中，腐蚀液可以包括碱和腐蚀添加剂，腐蚀液中碱和腐蚀添加剂的种类并不受特别限制，本领域技术人员可以根据实际需要进行选择，例如，碱可以为KOH和/或NaOH，碱的体积浓度可以为1v％±0.2v％，腐蚀添加剂可以为本领域常规的腐蚀添加剂，腐蚀液的温度可以为80℃±3℃，腐蚀处理的时间可以为120s±10s，通过控制该制绒条件，可以有效消除上步激光烧灼形成的损伤层，同时修饰倒金字塔结构。According to a specific embodiment of the present invention, silicon wafers can be put into a tank-type texturing cleaning machine for backside corrosion treatment, wherein the corrosion solution can include alkali and corrosion additives, and the types of alkali and corrosion additives in the corrosion solution are not subject to special restrictions. Restrictions, those skilled in the art can choose according to actual needs, for example, the alkali can be KOH and/or NaOH, the volume concentration of the alkali can be 1v%±0.2v%, the corrosion additive can be the conventional corrosion additive in this field, the corrosion solution The temperature can be 80℃±3℃, and the corrosion treatment time can be 120s±10s. By controlling the texturing conditions, the damaged layer formed by laser burning in the previous step can be effectively eliminated, and the inverted pyramid structure can be modified at the same time.
(6)在步骤(5)得到的硅片背面沉积隧穿氧化层和多晶硅层。(6) Depositing a tunnel oxide layer and a polysilicon layer on the back of the silicon wafer obtained in step (5).
根据本发明的实施例，可以在低压化学气相沉积炉(LPCVD)中进行背面隧穿氧化层(SiO2)及多晶硅(Poly)层的沉积，其中，隧穿氧化层和多晶硅层的厚度并不受特别限制，本领域技术人员可以根据实际需要进行选择，例如隧穿氧化层的厚度可以为1.5nm左右，多晶硅层的厚度可以为120nm左右。According to an embodiment of the present invention, the deposition of the back tunneling oxide layer (SiO2) and the polysilicon (Poly) layer can be carried out in a low pressure chemical vapor deposition furnace (LPCVD), wherein the thicknesses of the tunneling oxide layer and the polysilicon layer are not affected by Especially limited, those skilled in the art can choose according to actual needs, for example, the thickness of the tunnel oxide layer can be about 1.5nm, and the thickness of the polysilicon layer can be about 120nm.
根据本发明的一些具体实施例，制备N型TopCon电池片的方法可以进一步包括：(7)以硅片具有硼扩散的一侧为正面，在硅片背面的多晶硅层中注入磷，形成钝化接触结构，其中该步骤可以在背面磷扩散炉中进行，通过在电池背面制备一层超薄的隧穿氧化层和一层磷掺杂的多晶硅薄层共同形成钝化接触结构，可以为硅片的背面提供良好的表面钝化，超薄氧化层可以使多子电子隧穿进入多晶硅层同时阻挡少子空穴复合，进而电子在多晶硅层横向传输被金属收集，从而能够极大地降低金属接触复合电流，提升电池的开路电压和短路电流。According to some specific embodiments of the present invention, the method for preparing an N-type TopCon cell can further include: (7) taking the side of the silicon wafer with boron diffusion as the front side, implanting phosphorus into the polysilicon layer on the back side of the silicon wafer to form a passivation The contact structure, wherein this step can be carried out in the rear phosphorus diffusion furnace, by preparing an ultra-thin tunnel oxide layer and a thin layer of phosphorus-doped polysilicon on the back of the battery to form a passivation contact structure, which can be a silicon wafer The backside provides good surface passivation, and the ultra-thin oxide layer can allow the multi-carrier electrons to tunnel into the polysilicon layer while blocking the recombination of the minority carrier-holes, and then the electrons are transported laterally in the polysilicon layer and collected by the metal, which can greatly reduce the metal contact recombination current , to increase the open circuit voltage and short circuit current of the battery.
根据本发明的再一些具体实施例，制备N型TopCon电池片的方法可以进一步包括：去除硅片正面绕镀多晶硅层，具体可以采用抛光液在槽式清洗机中进行，其中抛光液可以包括KOH和抛光添加剂，抛光液中KOH的浓度可以为4wt％作用，抛光添加剂可以为本领域常规的抛光添加剂，抛光温度可以为66℃±3℃，工艺时间可以为200s±20s，通过控制该条件可以有效去除硅片正面绕镀多晶硅层。According to still some specific embodiments of the present invention, the method for preparing N-type TopCon cells may further include: removing the polysilicon layer on the front side of the silicon wafer, specifically, a polishing solution may be used in a tank cleaning machine, wherein the polishing solution may include KOH And polishing additive, the concentration of KOH in the polishing liquid can be 4wt% effect, and polishing additive can be the polishing additive conventional in this field, and polishing temperature can be 66 ℃ ± 3 ℃, and process time can be 200s ± 20s, by controlling this condition can Effectively remove the polysilicon layer on the front side of the silicon wafer.
根据本发明的又一些具体实施例，制备N型TopCon电池片的方法可以进一步包括：(8)在硅片正面依次沉积氧化铝层和氮化硅层，形成正面钝化层；(9)在硅片背面沉积氮化硅层，形成背面钝化层；(10)在硅片正面和背面印刷电极浆料并进行烧结，得到电池片。According to some other specific embodiments of the present invention, the method for preparing an N-type TopCon battery sheet may further include: (8) depositing an aluminum oxide layer and a silicon nitride layer in sequence on the front side of the silicon wafer to form a front passivation layer; (9) Depositing a silicon nitride layer on the back of the silicon wafer to form a back passivation layer; (10) printing electrode paste on the front and back of the silicon wafer and sintering to obtain a battery sheet.
与现有技术相比，本发明上述实施例的制备N型TopCon电池片的方法于背面抛光处理后在硅片背面沉积硅氧化合物层，通过对硅氧化合物层进行 激光开槽并对开槽部位下层的硅进行烧灼，可以在硅片表面形成倒金字塔结构，之后再通过进一步制绒可以去除激光灼烧导致的损伤面并修饰倒金字塔结构，由此，既可以利用该制绒修饰后的金字塔结构与背面金属电极接触，增加硅片背面与金属电极的接触效果，提高导电性，还可以允许非接触区域的方块尺寸更大，从而达到更好的钝化效果。综上，该制备工艺至少具有以下优点：1、对硅片背面进行抛光时可以在硅片背面形成尺寸更大的方块形貌，例如可以使方块尺寸达到20μm左右，相对于现有背面抛光形成的5μm左右的方块尺寸，本发明中可以形成更大的方块尺寸形貌，进而使得钝化膜在更大方块、平整的硅基体上沉积更加致密，钝化效果更好；2、硅片背面形成尺寸更大的方块形貌时，背面抛光控制的刻蚀量与常规工艺相比也较大，由此能够确保电池侧面、背面绕扩层被完全去除，保证较好的电池并联电阻，防止漏电；3、在硅片背面金属化区域(即与背面电极接触的区域)，硅基体通过倒金字塔结构与金属浆料接触，相互接触面积更大，从而接触电阻更小，串联电阻也相应更小，可以进一步提高导电效果；4、采用该方法制得的电池可兼容背面钝化与背面金属浆料和硅基体良好接触的性能，电阻更低，开路电压、填充因子和电池的转换效率均能得到提升，例如，串联电阻可降低1.5mΩ甚至更大，开路电压可提升5mV甚至更大，填充因子可提高0.4％甚至更高，电池的转换效率可提高0.3％甚至更高。Compared with the prior art, the method for preparing an N-type TopCon battery sheet according to the above-mentioned embodiments of the present invention deposits a silicon oxide compound layer on the backside of the silicon wafer after the back polishing treatment, and performs laser grooving on the silicon oxide compound layer and grooves the silicon oxide compound layer. Burning the silicon in the lower layer can form an inverted pyramid structure on the surface of the silicon wafer, and then further texturing can remove the damaged surface caused by laser burning and modify the inverted pyramid structure. Therefore, the modified texture can be used The pyramid structure is in contact with the metal electrode on the back, which increases the contact effect between the back of the silicon wafer and the metal electrode, improves conductivity, and allows a larger square size in the non-contact area, thereby achieving a better passivation effect. In summary, this preparation process has at least the following advantages: 1. When polishing the back of the silicon wafer, a larger square shape can be formed on the back of the silicon wafer, for example, the size of the square can reach about 20 μm, compared with the existing back polishing. The square size of about 5 μm, the present invention can form a larger square size topography, and then make the passivation film deposited on a larger square, flat silicon substrate more dense, and the passivation effect is better; 2, the back of the silicon wafer When forming a larger square shape, the amount of etching controlled by the back polishing is also larger than that of the conventional process, which can ensure that the side and back of the battery are completely removed, ensuring better parallel resistance of the battery and preventing Leakage; 3. In the metallized area on the back of the silicon wafer (that is, the area in contact with the back electrode), the silicon substrate contacts the metal paste through an inverted pyramid structure, and the mutual contact area is larger, so that the contact resistance is smaller and the series resistance is correspondingly smaller. 4. The battery prepared by this method is compatible with the performance of good contact between the back passivation and the back metal paste and the silicon substrate, the resistance is lower, and the open circuit voltage, fill factor and conversion efficiency of the battery are all consistent. For example, the series resistance can be reduced by 1.5mΩ or more, the open circuit voltage can be increased by 5mV or more, the fill factor can be increased by 0.4% or more, and the conversion efficiency of the battery can be increased by 0.3% or more.
根据本发明的第二个方面，本发明还提出了一种采用上述制备N型TopCon电池片的方法制得的N型TOPCon电池片。具体地，根据本发明的一些具体示例，参考图3理解，N型TOPCon电池片可以包括N型单晶硅基体10、正面电极11(如Ag/Al电极)和背面电极12(如Ag电极)，其中，N型单晶硅基体10正面具有P+掺杂层13，正面电极11与P+掺杂层13直接接触，P+掺杂层13与正面电极11接触的区域具有绒面金字塔结构，P+掺杂层13不与正面电极11接触的区域覆盖有正面钝化层14，其中正面钝化层14在远离单晶硅基体10正面的方向上依次形成有氧化铝层和氮化硅层，正面电极11可以为Al电极或Ag电极；N型单晶硅基体10背面具有N+掺杂层15，背面电极12与N+掺杂层15直接接触，N+掺杂层15及对应的单晶硅基体10与背面电极12接触的区域具有绒面金字塔结构，N+掺杂层15不与背面电极12接触的区域为方块形貌，方块形貌中方块尺寸为20μm±2μm，方块形貌上覆盖有背面钝化层16，其中背面钝化层16在远离单晶硅基体10背面的方向上依次形成有多晶硅掺杂层和氮化硅层。与现有技术比，该N型 TopCon电池片背面方块形貌尺寸更大，钝化效果更好，且电池背面与背面电极接触的部分为倒金字塔绒面结构，与电极接触效果更好，导电性高，同时兼容了背面钝化与背面金属浆料和硅基体良好接触的性能，电阻更低，开路电压、填充因子和电池的转换效率均得到了提升。需要说明的是，针对上述制备N型TopCon电池片的方法所描述的特征及效果同样适用于该N型TopCon电池片，此处不再一一赘述。另外，需要说明的是，本发明中所述的“P+掺杂层”和所述“N+掺杂层”中，“P”指的是P型(positive，即正极)，“N”指的是N型(negative，即负极)，“+”指的重掺杂，相对于本征硅片掺杂浓度高，“P+掺杂层”表示P型重掺杂层，“N+掺杂层”表示N型重掺杂层。According to the second aspect of the present invention, the present invention also proposes an N-type TOPCon cell prepared by the method for preparing an N-type TopCon cell. Specifically, according to some specific examples of the present invention, it is understood with reference to FIG. 3 that an N-type TOPCon cell can include an N-type monocrystalline silicon substrate 10, a front electrode 11 (such as an Ag/Al electrode) and a back electrode 12 (such as an Ag electrode) , wherein, the front side of the N-type single crystal silicon substrate 10 has a P+ doped layer 13, the front electrode 11 is in direct contact with the P+ doped layer 13, the area where the P+ doped layer 13 contacts the front electrode 11 has a textured pyramid structure, and the P+ doped The area of the impurity layer 13 that is not in contact with the front electrode 11 is covered with a front passivation layer 14, wherein the front passivation layer 14 is sequentially formed with an aluminum oxide layer and a silicon nitride layer in a direction away from the front surface of the single crystal silicon substrate 10, and the front electrode 11 can be an Al electrode or an Ag electrode; the N-type single crystal silicon substrate 10 has an N+ doped layer 15 on the back, the back electrode 12 is in direct contact with the N+ doped layer 15, and the N+ doped layer 15 and the corresponding single crystal silicon substrate 10 are in contact with the The area in contact with the back electrode 12 has a suede pyramid structure, and the area where the N+ doped layer 15 is not in contact with the back electrode 12 has a square shape. The square size in the square shape is 20 μm ± 2 μm, and the square shape is covered with back passivation. Layer 16, wherein the rear passivation layer 16 is formed in sequence with a polysilicon doped layer and a silicon nitride layer in a direction away from the rear surface of the single crystal silicon substrate 10. Compared with the existing technology, the N-type TopCon battery has a larger square shape and better passivation effect, and the part of the back of the battery that is in contact with the back electrode is an inverted pyramid textured structure, which has a better contact effect with the electrode and conducts electricity. At the same time, it is compatible with the performance of good contact between the back passivation and the back metal paste and the silicon substrate, the resistance is lower, and the open circuit voltage, fill factor and conversion efficiency of the battery have been improved. It should be noted that the features and effects described above for the method for preparing the N-type TopCon cell are also applicable to the N-type TopCon cell, and will not be repeated here. In addition, it should be noted that in the "P+ doped layer" and the "N+ doped layer" mentioned in the present invention, "P" refers to P-type (positive, positive electrode), and "N" refers to It is N-type (negative, that is, negative electrode), "+" refers to heavy doping, and the doping concentration is higher than that of intrinsic silicon wafers. "P+ doped layer" means P-type heavily doped layer, and "N+ doped layer" Indicates N-type heavily doped layer.
下面描述的实施例是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。实施例中未注明具体技术或条件的，按照本领域内的文献所描述的技术或条件或者按照产品说明书进行。所用试剂或仪器未注明生产厂商者，均为可以通过市购获得的常规产品。The embodiments described below are exemplary only for explaining the present invention and should not be construed as limiting the present invention. If no specific technique or condition is indicated in the examples, it shall be carried out according to the technique or condition described in the literature in this field or according to the product specification. The reagents or instruments used were not indicated by the manufacturer, and they were all commercially available conventional products.
实施例1Example 1
制备N型TopCon电池片：Preparation of N-type TopCon cells:
1.工艺步骤第一步，将N型裸硅片投入槽式制绒清洗机中进行碱制绒工艺，溶液为1±0.2v％浓度的KOH+制绒添加剂溶液，溶液温度80℃±3℃，工艺时间500s±15s，刻蚀量0.58±0.05g，反射率9±0.5％；1. The first step of the process is to put the N-type bare silicon wafer into the tank-type texturing cleaning machine for alkali texturing process. The solution is 1±0.2v% concentration of KOH+texturing additive solution, and the solution temperature is 80°C±3°C , the process time is 500s±15s, the etching amount is 0.58±0.05g, and the reflectivity is 9±0.5%;
2.第二步制绒后的电池片在硼扩散炉管中进行硼扩散工艺，方阻120±20Ω/sq，工艺温度950±50℃；2. In the second step, the cells after texturing are subjected to a boron diffusion process in a boron diffusion furnace tube, with a square resistance of 120±20Ω/sq and a process temperature of 950±50°C;
3.第三步在链式去BSG清洗机中，去除背面BSG层，溶液为40±5wt％浓度的氢氟酸，工艺温度20±3℃；3. The third step is to remove the back BSG layer in the chain type BSG cleaning machine, the solution is hydrofluoric acid with a concentration of 40±5wt%, and the process temperature is 20±3°C;
4.第四步在槽式清洗机中进行背面碱抛光，溶液为4±0.2v％体积浓度的KOH+抛光添加剂，溶液温度65±3℃，工艺时间400±20s，背面形貌为尺寸20μm±2μm的方块，背面反射率42±1％；4. The fourth step is to carry out alkali polishing on the back side in a tank cleaning machine. The solution is 4±0.2v% volume concentration of KOH+polishing additive, the solution temperature is 65±3°C, the process time is 400±20s, and the size of the back surface is 20μm± 2μm square, the back reflectivity is 42±1%;
5.第五步在常压化学气相淀积设备(APCVD)中，在电池背面沉积一层SiOx层，膜厚100±10nm；5. The fifth step is to deposit a layer of SiOx on the back of the battery in the atmospheric pressure chemical vapor deposition equipment (APCVD), with a film thickness of 100 ± 10nm;
6.第六步在紫外激光器上对电池背面SiOx层进行激光开槽，激光功率为20W、频率为40000Hz，此处开槽的图形与背面金属细栅线图形一致，在去除该图形区域的表层SiOx后，激光同时对下层的硅进行烧灼，形成倒金字塔结构，最后在电池4个角落打上Mark点，用于后道丝网印刷时对准；6. The sixth step is to laser groove the SiOx layer on the back of the battery on the ultraviolet laser. The laser power is 20W and the frequency is 40000Hz. The pattern of the groove here is consistent with the pattern of the metal fine grid line on the back. After SiOx, the laser burns the lower layer of silicon at the same time to form an inverted pyramid structure, and finally mark points on the four corners of the battery for alignment during subsequent screen printing;
7.第七步在槽式清洗机中进行碱腐蚀，溶液为1±0.2v％(体积比)浓度 的KOH+腐蚀添加剂，溶液温度80±3℃，工艺时间120±10s，主要目的为消除上步激光烧灼形成的损伤层，同时修饰倒金字塔结构，最后在后面的氢氟酸槽中将未激光区域的SiOx膜去除掉；7. The seventh step is to carry out alkali corrosion in the tank cleaning machine. The solution is KOH+corrosion additive with a concentration of 1±0.2v% (volume ratio), the solution temperature is 80±3°C, and the process time is 120±10s. The main purpose is to eliminate the above The damaged layer formed by the first step of laser ablation, while modifying the inverted pyramid structure, and finally remove the SiOx film in the non-laser area in the hydrofluoric acid tank behind;
8.第八步在低压化学气相沉积炉(LPCVD)中进行背面隧穿氧化层(SiO2)及多晶硅(Poly)层的沉积，隧穿氧化层厚度1.5±0.2nm，Poly厚度120±20nm；8. The eighth step is to deposit the back tunneling oxide layer (SiO2) and polysilicon (Poly) layer in a low-pressure chemical vapor deposition furnace (LPCVD). The thickness of the tunneling oxide layer is 1.5±0.2nm, and the thickness of Poly is 120±20nm;
9.第九步背面磷扩散炉在背面Poly层中注入磷，形成钝化接触结构；9. In the ninth step, phosphorus diffusion furnace on the back injects phosphorus into the Poly layer on the back to form a passivation contact structure;
10.第十步在槽式清洗机中去正面绕镀Poly层，溶液为4±0.2v％(体积比)浓度的KOH+抛光添加剂，温度66±3℃，工艺时间200±20s；10. The tenth step is to remove the front side winding Poly layer in the tank cleaning machine, the solution is 4±0.2v% (volume ratio) concentration of KOH+polishing additive, the temperature is 66±3°C, and the process time is 200±20s;
11.第十一步正面AlOx+SiNx、背面SiNx钝化膜镀膜；11. The eleventh step is AlOx+SiNx on the front and SiNx passivation film coating on the back;
12.最后电池片丝网印刷及烧结测试分选。12. Screen printing and sintering test sorting of the final cell.
对比例1Comparative example 1
制备N型TopCon电池片：Preparation of N-type TopCon cells:
1.工艺步骤第一步，将N型裸硅片投入槽式制绒清洗机中进行碱制绒工艺，溶液为1±0.2v％(体积比)浓度的KOH+制绒添加剂溶液，溶液温度80±3℃，工艺时间500±15s，刻蚀量0.58±0.05g，反射率9±0.5％；1. The first step of the process is to put the N-type bare silicon wafer into the tank-type texturing cleaning machine for alkali texturing process. The solution is 1±0.2v% (volume ratio) concentration of KOH+texturing additive solution, and the solution temperature is 80 ±3°C, process time 500±15s, etching amount 0.58±0.05g, reflectivity 9±0.5%;
2.第二步制绒后的电池片在硼扩散炉管中进行硼扩散工艺，方阻120±20Ω/sq，工艺温度950±50℃；2. In the second step, the cells after texturing are subjected to a boron diffusion process in a boron diffusion furnace tube, with a square resistance of 120±20Ω/sq and a process temperature of 950±50°C;
3.第三步在链式去BSG清洗机中，去除背面BSG层，溶液为40±5wt％浓度的氢氟酸，工艺温度20±3℃；3. The third step is to remove the back BSG layer in the chain type BSG cleaning machine, the solution is hydrofluoric acid with a concentration of 40±5wt%, and the process temperature is 20±3°C;
4.第四步在槽式清洗机中进行背面碱抛光，溶液为4±0.2v％浓度的KOH+抛光添加剂，溶液温度65±3℃，工艺时间160±10s，背面形貌为尺寸5±0.5μm的方块，背面反射率40±1％；4. The fourth step is to carry out alkali polishing on the back in the tank cleaning machine. The solution is 4±0.2v% concentration of KOH+polishing additive, the solution temperature is 65±3°C, the process time is 160±10s, and the size of the back surface is 5±0.5 μm square, the back reflectivity is 40±1%;
5.第五步在低压化学气相沉积炉(LPCVD)中进行背面隧穿氧化层(SiO2)及多晶硅(Poly)层的沉积，隧穿氧化层厚度1.5±0.2nm，Poly厚度120±20nm；5. The fifth step is to deposit the back tunneling oxide layer (SiO2) and polysilicon (Poly) layer in a low-pressure chemical vapor deposition furnace (LPCVD). The thickness of the tunneling oxide layer is 1.5±0.2nm, and the thickness of Poly is 120±20nm;
6.第六步背面磷扩散炉在背面Poly层中注入磷，形成钝化接触结构；6. In the sixth step, phosphorus diffusion furnace on the back injects phosphorus into the Poly layer on the back to form a passivation contact structure;
7.第七步在槽式清洗机中去正面绕镀Poly层，溶液为4±0.2v％(体积比)％浓度的KOH+抛光添加剂，温度66±3℃，工艺时间200±20s；7. The seventh step is to remove the front side winding Poly layer in the tank cleaning machine, the solution is 4±0.2v% (volume ratio)% KOH+polishing additive, the temperature is 66±3°C, and the process time is 200±20s;
8.第八步正面AlOx+SiNx、背面SiNx钝化膜镀膜；8. The eighth step is AlOx+SiNx on the front and SiNx passivation film coating on the back;
9.最后电池片丝网印刷及烧结测试分选。9. Screen printing and sintering test sorting of the final cell.
对比例2Comparative example 2
与实施例1的区别在于：The difference with embodiment 1 is:
4.第四步在槽式清洗机中进行背面碱抛光，溶液为4±0.2v％(体积比) 浓度的KOH+抛光添加剂，溶液温度65±3℃，工艺时间800±20s，背面形貌为尺寸40±2μm的方块，背面反射率43±1％；4. The fourth step is to carry out alkali polishing on the back in the tank cleaning machine. The solution is KOH+polishing additive with a concentration of 4±0.2v% (volume ratio), the solution temperature is 65±3°C, the process time is 800±20s, and the back surface is A square with a size of 40±2μm, the reflectivity of the back is 43±1%;
实施例2Example 2
与实施例1区别在于，步骤4～7。具体地：The difference from Example 1 lies in steps 4-7. specifically:
4.第四步在槽式清洗机中进行背面碱抛光，溶液为4±0.2v％(体积比)wt％浓度的KOH+抛光添加剂，溶液温度65±3℃，工艺时间600±20s，背面形貌为尺寸30±2μm的方块，背面反射率42.5±1％；4. The fourth step is to carry out alkali polishing on the back in a tank cleaning machine. The solution is KOH+polishing additive with a concentration of 4±0.2v% (volume ratio) wt%, the solution temperature is 65±3°C, and the process time is 600±20s. Appearance is a square with a size of 30±2μm, and the reflectivity of the back is 42.5±1%;
5.第五步在常压化学气相淀积设备(APCVD)中，在电池背面沉积一层SiOx层，膜厚100±10nm；5. The fifth step is to deposit a layer of SiOx on the back of the battery in the atmospheric pressure chemical vapor deposition equipment (APCVD), with a film thickness of 100 ± 10nm;
6.第六步在紫外激光器上对电池背面SiOx层进行激光开槽，激光功率为20W、频率为40000Hz，此处开槽的图形与背面金属细栅线图形一致，在去除该图形区域的表层SiOx后，激光同时对下层的硅进行烧灼，形成倒金字塔结构，最后在电池4个角落打上Mark点，用于后道丝网印刷时对准；6. The sixth step is to laser groove the SiOx layer on the back of the battery on the ultraviolet laser. The laser power is 20W and the frequency is 40000Hz. The pattern of the groove here is consistent with the pattern of the metal fine grid line on the back. After SiOx, the laser burns the lower layer of silicon at the same time to form an inverted pyramid structure, and finally mark points on the four corners of the battery for alignment during subsequent screen printing;
7.第七步在槽式清洗机中进行碱腐蚀，溶液为1±0.2v％(体积比)浓度的KOH+腐蚀添加剂，溶液温度80±3℃，工艺时间120±10s，主要目的为消除上步激光烧灼形成的损伤层，同时修饰倒金字塔结构，最后在后面的氢氟酸槽中将未激光区域的SiOx膜去除掉。7. The seventh step is to carry out alkali corrosion in the tank cleaning machine. The solution is KOH+corrosion additive with a concentration of 1±0.2v% (volume ratio), the solution temperature is 80±3°C, and the process time is 120±10s. The main purpose is to eliminate the above The damaged layer formed by the first step of laser ablation, while modifying the inverted pyramid structure, and finally remove the SiOx film in the non-laser area in the subsequent hydrofluoric acid tank.
评价与结果Evaluation and Results
对实施例1～2和对比例1～2制得的电池片进行电性能测试，测试结果见表1。The electrical properties of the battery sheets prepared in Examples 1-2 and Comparative Examples 1-2 were tested, and the test results are shown in Table 1.
表1 实施例1～2和对比例1～2的电池片电性能参数(100片电池片的平均值)对比Table 1 Comparison of battery electrical performance parameters (average value of 100 batteries) of Examples 1-2 and Comparative Examples 1-2
 the 电池片数量Cell Quantity Eff(％)Eff(%) Voc(mV)Voc(mV) Jsc(mA/cm 2) Jsc(mA/cm 2 ) FF(％)FF(%)
实施例1Example 1 100100 24.5424.54 723723 41.3341.33 82.1282.12
对比例1Comparative example 1 100100 24.2224.22 716716 41.3141.31 81.9081.90
对比例2Comparative example 2 100100 24.5224.52 722722 41.3541.35 82.1382.13
实施例2Example 2 100100 24.4724.47 721721 41.3441.34 82.1082.10
其中，Total为电池片数量；Eff为电池转换效率；Voc为开路电压；Jsc为短路电流密度；FF为填充因子。Among them, Total is the number of cells; Eff is the conversion efficiency of the battery; Voc is the open circuit voltage; Jsc is the short circuit current density; FF is the fill factor.
从表1中可以看出，与对比例1中背面形貌为尺寸5±0.5μm的方块，且未结合激光开槽的工艺相比，采用本申请的制备工艺可以使得电池的开路电压、短路电流、填充因子和电池转换效率均得到提升。另外，还需要说明的是，虽然实施例2和对比例2中采用的碱抛光时间更长，获得的背面形貌方块尺寸更大，且电池片的平均性能参数与实施例1较为接近，但其测试采用的电池片均是选用的能够制备出来且合格的电池片，在实际操作过程中，与实施例1相比，实施例2和对比例2的电池片不仅制备效率较低，产率也较低，而且在电池片制备过程中，需要被保护的正面掩膜也出现有被部分刻蚀掉的情况，导致个别电池片性能下降，影响电池片的平均性能；此外，实施例2和对比例2中制得的电池片中硅片相对更薄，电池片能负载的极限载荷也更小，电池片风险更大。It can be seen from Table 1 that, compared with the process in Comparative Example 1 where the back surface was a square with a size of 5±0.5 μm and no laser slotting was used, the preparation process of the present application can make the open circuit voltage and short circuit voltage of the battery Current, fill factor and cell conversion efficiency are all improved. In addition, it should be noted that although the alkali polishing time used in Example 2 and Comparative Example 2 is longer, the size of the squares on the back surface obtained is larger, and the average performance parameters of the battery sheet are closer to those of Example 1, but The cells used in the test are all qualified cells that can be prepared. In the actual operation process, compared with Example 1, the cells of Example 2 and Comparative Example 2 not only have lower preparation efficiency, but also have a lower yield. It is also lower, and in the cell preparation process, the front mask that needs to be protected is also partially etched away, resulting in a decline in the performance of individual cells and affecting the average performance of the cell; in addition, Example 2 and The silicon wafer in the solar cell prepared in Comparative Example 2 is relatively thinner, the limit load that the solar cell can carry is also smaller, and the risk of the solar cell is greater.
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples and features of different embodiments or examples described in this specification without conflicting with each other.
尽管上面已经示出和描述了本发明的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention, those skilled in the art can make the above-mentioned The embodiments are subject to changes, modifications, substitutions and variations.
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。The device embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in One place, or it can be distributed to multiple network elements. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. It can be understood and implemented by those skilled in the art without any creative efforts.
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并 未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.
在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本发明可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

Claims (19)

  1. 一种太阳能电池，其特征在于，包括：P型硅基体，所述P型硅基体具有正面和背面，所述背面为光面结构，且在所述背面依次层叠有隧穿氧化硅层、磷掺杂的多晶硅层、第一钝化层和背面电极，所述背面电极和所述磷掺杂的多晶硅层接触；A solar cell, characterized in that it comprises: a P-type silicon substrate, the P-type silicon substrate has a front surface and a back surface, the back surface is a smooth structure, and a tunneling silicon oxide layer, a phosphorous a doped polysilicon layer, a first passivation layer, and a back electrode in contact with the phosphorus-doped polysilicon layer;
    所述正面为绒面结构，在所述正面依次层叠有第二钝化层和正面电极，所述正面电极与所述P型硅基体接触，且所述正面电极与所述P型硅基体接触的区域形成有P+层。The front side is a suede structure, and a second passivation layer and a front electrode are stacked in sequence on the front side, the front electrode is in contact with the P-type silicon substrate, and the front electrode is in contact with the P-type silicon substrate The region is formed with a P+ layer.
  2. 根据权利要求1所述的电池，其特征在于，所述隧穿氧化硅层厚度小于2nm，所述磷掺杂的多晶硅层厚度为110nm-130nm。The battery according to claim 1, wherein the thickness of the tunneling silicon oxide layer is less than 2nm, and the thickness of the phosphorus-doped polysilicon layer is 110nm-130nm.
  3. 根据权利要求2所述的电池，其特征在于，所述隧穿氧化硅层厚度为1.3nm-1.7nm。The battery according to claim 2, characterized in that the thickness of the tunneling silicon oxide layer is 1.3nm-1.7nm.
  4. 根据权利要求1所述的电池，其特征在于，所述第一钝化层为氮化硅层。The battery according to claim 1, wherein the first passivation layer is a silicon nitride layer.
  5. 根据权利要求1所述的电池，其特征在于，所述第二钝化层为氧化铝和氮化硅层。The battery according to claim 1, wherein the second passivation layer is an aluminum oxide and silicon nitride layer.
  6. 根据权利要求1所述的电池，其特征在于，所述背面电极为银电极，所述正面电极为铝电极。The battery according to claim 1, wherein the back electrode is a silver electrode, and the front electrode is an aluminum electrode.
  7. 一种太阳能电池，其特征在于，包括N型单晶硅基体、正面电极和背面电极，其中，所述N型单晶硅基体正面具有P+掺杂层，所述正面电极与所述P+掺杂层直接接触，所述P+掺杂层不与所述正面电极接触的区域覆盖有正面钝化层；所述N型单晶硅基体背面具有N+掺杂层，所述背面电极与所述N+掺杂层直接接触，所述N+掺杂层及对应的单晶硅基体与所述背面电极接触的区域具有绒面金字塔结构，所述N+掺杂层不与所述背面电极接触的区域为方块形貌，所述方块形貌中方块尺寸为20μm±2μm。A solar cell, characterized in that it comprises an N-type monocrystalline silicon base, a front electrode and a back electrode, wherein the N-type single crystal silicon base has a P+ doped layer on the front, and the front electrode is doped with the P+ Layers are in direct contact with the P+ doped layer, and the area where the P+ doped layer is not in contact with the front electrode is covered with a front passivation layer; the back of the N-type single crystal silicon substrate has an N+ doped layer, and the back electrode is in contact with the N+ doped layer. The impurity layer is in direct contact, the area where the N+ doped layer and the corresponding single crystal silicon substrate are in contact with the back electrode has a textured pyramid structure, and the area where the N+ doped layer is not in contact with the back electrode is square appearance, the square size in the square appearance is 20 μm±2 μm.
  8. 一种权利要求1-6任一项所述的太阳能电池的制备方法，其特征在于，包括如下步骤：A method for preparing a solar cell according to any one of claims 1-6, comprising the steps of:
    对所述P型硅基体的背面在低压化学气相沉积炉中依次沉积隧穿氧化硅层以及沉积多晶硅层；sequentially depositing a tunneling silicon oxide layer and depositing a polysilicon layer in a low-pressure chemical vapor deposition furnace on the back side of the P-type silicon substrate;
    对所述多晶硅层进行磷掺杂，得到所述磷掺杂的多晶硅层；Phosphorus-doped the polysilicon layer to obtain the phosphorus-doped polysilicon layer;
    将所述P型硅基体的正面进行制绒，形成所述绒面结构；Texturing the front side of the P-type silicon substrate to form the textured structure;
    在制绒后的所述P型硅基体的正面沉积氧化铝和氮化硅层，形成所述第二钝化层；Depositing aluminum oxide and silicon nitride layers on the front side of the P-type silicon substrate after texturing to form the second passivation layer;
    在所述磷掺杂的多晶硅层上沉积氮化硅层，形成所述第一钝化层；depositing a silicon nitride layer on the phosphorus-doped polysilicon layer to form the first passivation layer;
    在所述P型硅基体的正面和所述P型硅基体的背面分别印刷所述正面电极和所述背面电极。The front electrode and the back electrode are respectively printed on the front surface of the P-type silicon substrate and the back surface of the P-type silicon substrate.
  9. 根据权利要求8所述的方法，其特征在于，在对所述P型硅基体的背面依次沉积隧穿氧化硅层以及沉积多晶硅层之前，还包括：The method according to claim 8, characterized in that before sequentially depositing a tunneling silicon oxide layer and depositing a polysilicon layer on the back side of the P-type silicon substrate, further comprising:
    将所述P型硅基体盛有抛光液的清洗机中进行抛光处理，其中，所述抛光液包括水、碱液和添加剂，所述添加剂包括表面活性剂，柠檬酸钠，苯甲酸钠，所述抛光处理的温度为53℃-57℃，时间为215s-225s。The P-type silicon substrate is polished in a cleaning machine filled with polishing liquid, wherein the polishing liquid includes water, lye and additives, and the additives include surfactants, sodium citrate, sodium benzoate, the The temperature of the polishing treatment is 53°C-57°C, and the time is 215s-225s.
  10. 根据权利要求9所述的方法，其特征在于，在将所述P型硅基体置于盛有抛光液的清洗机中进行抛光处理后，所述P型硅基体的正面和背面的反射率为38％-44％。The method according to claim 9, characterized in that, after the P-type silicon substrate is placed in a cleaning machine filled with polishing liquid for polishing, the reflectivity of the front and back surfaces of the P-type silicon substrate is 38%-44%.
  11. 根据权利要求8所述的方法，其特征在于，在将所述P型硅基体的正面进行制绒，形成所述绒面结构之前，还包括：The method according to claim 8, characterized in that, before the front side of the P-type silicon substrate is textured to form the textured structure, it also includes:
    将所述P型硅基体的正面在室温下，置于盛有氢氟酸的洗液中，去除所述P型硅基体的正面的PSG；其中，所述氢氟酸的洗液质量浓度为8％-12％；The front side of the P-type silicon substrate is placed in a washing solution filled with hydrofluoric acid at room temperature to remove the PSG on the front side of the P-type silicon substrate; wherein the washing solution mass concentration of the hydrofluoric acid is 8%-12%;
    或；or;
    所述将所述P型硅基体的正面进行制绒，形成所述绒面结构，包括：The front side of the P-type silicon substrate is textured to form the textured structure, including:
    将所述P型硅基体浸入制绒液中，进行制绒；其中，所述制绒液包括KOH溶液，所述KOH溶液的质量浓度为0.5％-1.5％；所述制绒液温度为77℃-83℃，所述P型硅基体浸入制绒液的时间为495s-505s。The P-type silicon substrate is immersed in the texturing liquid for texturing; wherein, the texturing liquid includes KOH solution, and the mass concentration of the KOH solution is 0.5%-1.5%; the temperature of the texturing liquid is 77 °C-83 °C, the time for the P-type silicon substrate to be immersed in the texturing solution is 495s-505s.
    或；or;
    所述将所述P型硅基体的正面进行制绒，形成所述绒面结构，其中，所述绒面结构的反射率为8.7％-9.3％。The front side of the P-type silicon substrate is textured to form the textured structure, wherein the reflectance of the textured structure is 8.7%-9.3%.
    或；or;
    在所述P型硅基体的正面印刷所述正面电极之前，包括：Before printing the front electrode on the front side of the P-type silicon substrate, it includes:
    将所述P型硅基体的正面需要设置所述正面电极的区域，进行激光处理，以打开所述第二钝化层。Laser treatment is performed on the front side of the P-type silicon substrate where the front electrode needs to be disposed, so as to open the second passivation layer.
    或；or;
    所述P型硅基体的正面印刷所述正面电极，其中，所述正面电极浆料采用铝浆。The front electrode is printed on the front surface of the P-type silicon substrate, wherein the paste of the front electrode is aluminum paste.
  12. 一种权利要求7所述的太阳能电池的制备方法，其特征在于，所述方法包括：A method for preparing a solar cell according to claim 7, wherein the method comprises:
    (1)提供单面含有硼扩散的N型硅片；(1) Provide N-type silicon wafers with boron diffusion on one side;
    (2)以所述硅片背离硼扩散的一侧为背面，对所述硅片进行背面抛光处理，以便在硅片背面形成预期尺寸的方块形貌；(2) Taking the side of the silicon wafer away from the boron diffusion as the back side, performing a back polishing process on the silicon wafer, so as to form a square shape of expected size on the back side of the silicon wafer;
    (3)在步骤(2)得到的硅片背面沉积硅氧化合物层；(3) depositing a silicon oxide compound layer on the back side of the silicon wafer obtained in step (2);
    (4)对所述硅氧化合物层进行局部激光开槽，以便去除开槽部位的硅氧化合物层并对下层硅进行烧灼，形成倒金字塔结构；(4) Carrying out partial laser grooves to the silicon oxide compound layer, so as to remove the silicon oxide compound layer at the grooved position and burn the lower layer of silicon to form an inverted pyramid structure;
    (5)对步骤(4)得到的硅片进行腐蚀处理，并去除未激光区域的硅氧化合物层；(5) Etching the silicon wafer obtained in step (4), and removing the silicon oxide compound layer in the non-laser region;
    (6)在步骤(5)得到的硅片背面沉积隧穿氧化层和多晶硅层，(6) depositing a tunnel oxide layer and a polysilicon layer on the back side of the silicon wafer obtained in step (5),
    其中，所述硅片背面金属栅线设置在对应开槽图形的位置。Wherein, the metal gate line on the back side of the silicon wafer is arranged at a position corresponding to the groove pattern.
  13. 根据权利要求12所述的方法，其特征在于，步骤(2)中，以厚度为170μm±10μm、边长为182mm±0.25mm、倒角直径为247mm±0.25mm的182硅片为基准，所述抛光处理的刻蚀量为0.58g±0.05g，The method according to claim 12, characterized in that, in step (2), based on 182 silicon wafers with a thickness of 170 μm ± 10 μm, a side length of 182 mm ± 0.25 mm, and a chamfer diameter of 247 mm ± 0.25 mm, the The etching amount of the polishing treatment is 0.58g±0.05g,
    其中，所述抛光处理的温度为65℃±3℃，时间为400s±20s，采用的抛光液包括碱和抛光添加剂，所述碱包括KOH和/或NaOH，所述碱的体积浓度为4v％±0.2v％。Wherein, the temperature of the polishing treatment is 65°C±3°C, the time is 400s±20s, the polishing solution used includes alkali and polishing additives, the alkali includes KOH and/or NaOH, and the volume concentration of the alkali is 4v% ±0.2v%.
  14. 根据权利要求12所述的制备方法，其特征在于，步骤(2)中，所述方块形貌中，方块尺寸为20μm±2μm。The preparation method according to claim 12, characterized in that, in step (2), in the square shape, the square size is 20 μm±2 μm.
  15. 根据权利要求12所述的制备方法，其特征在于，步骤(2)得到的硅片背面反射率为42％±1％。The preparation method according to claim 12, characterized in that the back reflectance of the silicon wafer obtained in step (2) is 42%±1%.
  16. 根据权利要求12所述的制备方法，其特征在于，步骤(3)中，所述硅氧化合物层的厚度为90～150nm。The preparation method according to claim 12, characterized in that, in step (3), the thickness of the silicon oxide compound layer is 90-150 nm.
  17. 根据权利要求12所述的制备方法，其特征在于，步骤(4)中，所述激光开槽的功率为20W±5W，频率为40000Hz±2000Hz。The preparation method according to claim 12, characterized in that, in step (4), the power of the laser grooving is 20W±5W, and the frequency is 40000Hz±2000Hz.
  18. 根据权利要求12所述的制备方法，其特征在于，步骤(5)中，所述腐蚀处理的温度为80℃±3℃，时间为120s±10s，The preparation method according to claim 12, characterized in that, in step (5), the temperature of the corrosion treatment is 80°C±3°C, and the time is 120s±10s,
    其中，所述腐蚀处理采用的腐蚀液中包括碱，所述碱包括KOH和/ 或NaOH，所述碱的体积浓度为1v％±0.2v％。Wherein, the etching solution used in the etching treatment includes alkali, the alkali includes KOH and/or NaOH, and the volume concentration of the alkali is 1v%±0.2v%.
  19. 根据权利要求12-18中任一项所述的制备方法，其特征在于，进一步包括：The preparation method according to any one of claims 12-18, further comprising:
    (7)以所述硅片具有硼扩散的一侧为正面，在硅片背面的所述多晶硅层中注入磷，并去除硅片正面绕镀多晶硅层；(7) taking the side of the silicon wafer with boron diffusion as the front side, injecting phosphorus into the polysilicon layer on the back side of the silicon wafer, and removing the front side of the silicon wafer to wrap around the polysilicon layer;
    (8)在硅片正面依次沉积氧化铝层和氮化硅层，形成正面钝化层；(8) Depositing an aluminum oxide layer and a silicon nitride layer in turn on the front side of the silicon wafer to form a front passivation layer;
    (9)在硅片背面沉积氮化硅层，形成背面钝化层；(9) Depositing a silicon nitride layer on the back side of the silicon wafer to form a back passivation layer;
    (10)在硅片正面和背面印刷电极浆料并进行烧结，得到电池片。(10) Printing electrode paste on the front and back of the silicon wafer and sintering to obtain battery sheets.
PCT/CN2022/093351 2021-11-08 2022-05-17 Solar cell and preparation method therefor WO2023077772A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN202111314179.4A CN114256381B (en) 2021-11-08 2021-11-08 N-type TopCon battery piece and preparation method thereof
CN202111314179.4 2021-11-08
CN202111648529.0 2021-12-29
CN202111648529.0A CN114388633A (en) 2021-12-29 2021-12-29 Solar cell and preparation method thereof

Publications (1)

Publication Number Publication Date
WO2023077772A1 true WO2023077772A1 (en) 2023-05-11

Family

ID=86240624

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/093351 WO2023077772A1 (en) 2021-11-08 2022-05-17 Solar cell and preparation method therefor

Country Status (1)

Country Link
WO (1) WO2023077772A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116799091A (en) * 2023-06-16 2023-09-22 扬州大学 Laminated p-type passivation contact structure based on Poly finger and preparation method thereof
CN117040401A (en) * 2023-08-22 2023-11-10 苏州赛福天新能源技术有限公司 PERC efficient battery piece and battery piece yield improvement process
CN117577708A (en) * 2024-01-17 2024-02-20 金阳(泉州)新能源科技有限公司 Combined passivation back contact battery based on P-type silicon wafer, preparation method thereof and photovoltaic module

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0933822A2 (en) * 1998-01-20 1999-08-04 Sharp Kabushiki Kaisha Substrate for forming high-strenght thin semiconductor element and method for manufacturing high-strength thin semiconductor element
CN107845692A (en) * 2016-09-20 2018-03-27 上海神舟新能源发展有限公司 A kind of preparation method of modified back side tunnel oxidation passivation contact high-efficiency battery
CN108039374A (en) * 2017-10-31 2018-05-15 泰州隆基乐叶光伏科技有限公司 The preparation method of N-shaped double-side solar cell
US20190245111A1 (en) * 2018-02-02 2019-08-08 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Ultra-Thin Flexible Rear-Contact Si Solar Cells and Methods for Manufacturing the Same
CN112885925A (en) * 2021-02-05 2021-06-01 泰州隆基乐叶光伏科技有限公司 Solar cell and manufacturing method thereof
CN114256381A (en) * 2021-11-08 2022-03-29 泰州隆基乐叶光伏科技有限公司 N-type TopCon battery piece and preparation method thereof
CN114388633A (en) * 2021-12-29 2022-04-22 西安隆基乐叶光伏科技有限公司 Solar cell and preparation method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0933822A2 (en) * 1998-01-20 1999-08-04 Sharp Kabushiki Kaisha Substrate for forming high-strenght thin semiconductor element and method for manufacturing high-strength thin semiconductor element
CN107845692A (en) * 2016-09-20 2018-03-27 上海神舟新能源发展有限公司 A kind of preparation method of modified back side tunnel oxidation passivation contact high-efficiency battery
CN108039374A (en) * 2017-10-31 2018-05-15 泰州隆基乐叶光伏科技有限公司 The preparation method of N-shaped double-side solar cell
US20190245111A1 (en) * 2018-02-02 2019-08-08 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Ultra-Thin Flexible Rear-Contact Si Solar Cells and Methods for Manufacturing the Same
CN112885925A (en) * 2021-02-05 2021-06-01 泰州隆基乐叶光伏科技有限公司 Solar cell and manufacturing method thereof
CN114256381A (en) * 2021-11-08 2022-03-29 泰州隆基乐叶光伏科技有限公司 N-type TopCon battery piece and preparation method thereof
CN114388633A (en) * 2021-12-29 2022-04-22 西安隆基乐叶光伏科技有限公司 Solar cell and preparation method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116799091A (en) * 2023-06-16 2023-09-22 扬州大学 Laminated p-type passivation contact structure based on Poly finger and preparation method thereof
CN116799091B (en) * 2023-06-16 2024-02-20 扬州大学 Laminated p-type passivation contact structure based on Poly finger and preparation method thereof
CN117040401A (en) * 2023-08-22 2023-11-10 苏州赛福天新能源技术有限公司 PERC efficient battery piece and battery piece yield improvement process
CN117040401B (en) * 2023-08-22 2024-01-23 苏州赛福天新能源技术有限公司 PERC efficient battery piece and battery piece yield improvement process
CN117577708A (en) * 2024-01-17 2024-02-20 金阳(泉州)新能源科技有限公司 Combined passivation back contact battery based on P-type silicon wafer, preparation method thereof and photovoltaic module
CN117577708B (en) * 2024-01-17 2024-04-16 金阳(泉州)新能源科技有限公司 Combined passivation back contact battery based on P-type silicon wafer, preparation method thereof and photovoltaic module

Similar Documents

Publication Publication Date Title
WO2023077772A1 (en) Solar cell and preparation method therefor
WO2020057264A1 (en) Solar cell and preparation method therefor
CN110993700A (en) Heterojunction solar cell and preparation process thereof
WO2023071183A1 (en) Solar cell and preparation method therefor
WO2023093604A1 (en) Solar cell and preparation method for solar cell
CN108365022A (en) The preparation method of the black policrystalline silicon PERC battery structures of selective emitter
CN116705915B (en) Preparation method of novel double-sided TOPCON battery
CN109473487B (en) Crystalline silicon solar cell based on composite light trapping structure and preparation method thereof
TW201432925A (en) Silicon solar cell structure
CN113327999B (en) Monocrystalline silicon wafer with groove on surface, heterojunction solar cell and preparation method
CN117153953B (en) Preparation method of split-film type double-sided TOPCON battery
WO2024045917A1 (en) Back-contact solar cell and preparation method therefor
CN217280794U (en) Photovoltaic cell
CN116914033B (en) Preparation method of double-sided TOPCON battery
CN102983225A (en) Manufacturing process of local back surface field
CN112838132A (en) Solar cell laminated passivation structure and preparation method thereof
CN105529380A (en) Preparation method for single crystalline silicon solar cell piece with polished back surface
CN111463306A (en) Novel heterojunction battery and preparation method thereof
JP6502147B2 (en) Method of manufacturing solar cell and method of manufacturing solar cell module
CN114256381B (en) N-type TopCon battery piece and preparation method thereof
CN103247720A (en) Method for preparing crystalline silicon heterojunction solar cells
CN116387370A (en) P-type back contact battery structure, manufacturing method and solar battery
CN117594684A (en) Double-sided hybrid solar cell and preparation method thereof
CN114695593B (en) Preparation method of back contact battery and back contact battery
CN112466978A (en) Battery structure of crystalline silicon/amorphous silicon heterojunction battery and preparation method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22888809

Country of ref document: EP

Kind code of ref document: A1