WO2023071633A1 - 移位寄存器单元、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2023071633A1
WO2023071633A1 PCT/CN2022/120228 CN2022120228W WO2023071633A1 WO 2023071633 A1 WO2023071633 A1 WO 2023071633A1 CN 2022120228 W CN2022120228 W CN 2022120228W WO 2023071633 A1 WO2023071633 A1 WO 2023071633A1
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Prior art keywords
transistor
electrically connected
signal terminal
node
shift register
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PCT/CN2022/120228
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English (en)
French (fr)
Inventor
江鹏
陈晓晓
李云
朱宁
刘建涛
Original Assignee
京东方科技集团股份有限公司
武汉京东方光电科技有限公司
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Publication of WO2023071633A1 publication Critical patent/WO2023071633A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present disclosure relates to the field of display technology, in particular to a shift register unit, a gate drive circuit and a display device.
  • GOA Gate Driver on Array, array substrate row drive
  • TFT Thin Film Transistor, thin film transistor
  • the driving circuit is generally composed of multiple cascaded shift register units.
  • the output of the shift register unit is unstable, which can cause abnormal display.
  • the input circuit is configured to provide the signal of the second input signal terminal to the first node in response to the signal of the first input signal terminal;
  • a reset circuit configured to provide a signal at a first reference signal terminal to the first node in response to a signal at a reset signal terminal
  • a node control circuit configured to at least adjust the level of the signal of the first node according to the signals of the second reference signal terminal and the third reference signal terminal;
  • a cascade output circuit configured to provide a signal at the clock signal terminal to the cascade output terminal in response to the signal at the first node
  • the driving output circuit is configured to provide the signal of the clock signal terminal to the driving output terminal in response to the signal of the first node.
  • the input circuit includes: a first transistor
  • the gate of the first transistor is electrically connected to the first input signal terminal, the first pole of the first transistor is electrically connected to the second input signal terminal, and the second pole of the first transistor is electrically connected to the The first node is electrically connected.
  • the first input signal terminal and the second input signal terminal are the same signal terminal; or,
  • the first input signal terminal and the second input signal terminal are independent signal terminals.
  • the reset circuit includes: a second transistor
  • the gate of the second transistor is electrically connected to the reset signal terminal, the first pole of the second transistor is electrically connected to the first reference signal terminal, and the second pole of the second transistor is electrically connected to the first One node electrical connection.
  • the cascaded output circuit includes: a third transistor
  • the gate of the third transistor is electrically connected to the first node, the first pole of the third transistor is electrically connected to the clock signal terminal, and the second pole of the third transistor is connected to the cascade output electrical connection.
  • the node control circuit includes: a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
  • the gate of the fourth transistor and its first pole are both electrically connected to the third reference signal terminal, and the second pole of the fourth transistor is electrically connected to the gate of the fifth transistor;
  • the first pole of the fifth transistor is electrically connected to the third reference signal terminal, and the second pole of the fifth transistor is electrically connected to the second node;
  • the gate of the sixth transistor is electrically connected to the first node, the first pole of the sixth transistor is electrically connected to the second reference signal terminal, and the second pole of the sixth transistor is electrically connected to the first node.
  • the gate of the seventh transistor is electrically connected to the second node, the first pole of the seventh transistor is electrically connected to the second reference signal terminal, and the second pole of the seventh transistor is electrically connected to the first One node electrical connection.
  • the second reference signal terminal and the first reference signal terminal are the same signal terminal; or,
  • the second reference signal terminal and the first reference signal terminal are independent signal terminals, and the voltage of the second reference signal terminal is lower than the voltage of the first reference signal terminal.
  • the drive output circuit includes: an eighth transistor and a first capacitor
  • the gate of the eighth transistor is electrically connected to the first node, the first pole of the eighth transistor is electrically connected to the clock signal end, and the second pole of the eighth transistor is electrically connected to the drive output end electrical connection;
  • the first electrode plate of the first capacitor is electrically connected to the first node, and the second electrode plate of the first capacitor is electrically connected to the driving output terminal.
  • the driving output circuit is further configured to provide a signal of a fourth reference signal terminal to the driving output terminal in response to a signal of the second node.
  • the drive output circuit includes: a ninth transistor, a tenth transistor, and a second capacitor;
  • the gate of the ninth transistor is electrically connected to the first node, the first pole of the ninth transistor is electrically connected to the clock signal end, and the second pole of the ninth transistor is electrically connected to the drive output end electrical connection;
  • the gate of the tenth transistor is electrically connected to the second node, the first pole of the tenth transistor is electrically connected to the fourth reference signal terminal, and the second pole of the tenth transistor is electrically connected to the driver
  • the output terminal is electrically connected;
  • the first electrode plate of the second capacitor is electrically connected to the first node, and the second electrode plate of the second capacitor is electrically connected to the driving output terminal.
  • the first reference signal terminal and the fourth reference signal terminal are the same signal terminal; or,
  • the first reference signal terminal and the fourth reference signal terminal are independent signal terminals, and the voltage of the first reference signal terminal is lower than the voltage of the fourth reference signal terminal.
  • the shift register unit further includes: an eleventh transistor;
  • the gate of the eleventh transistor is electrically connected to the second node, the first pole of the eleventh transistor is electrically connected to the fifth reference signal terminal, and the second pole of the eleventh transistor is electrically connected to the The first node is electrically connected.
  • the fifth reference signal terminal and the first reference signal terminal are the same signal terminal; or,
  • the fifth reference signal terminal and the first reference signal terminal are independent signal terminals, and the voltage of the fifth reference signal terminal is lower than the voltage of the first reference signal terminal.
  • the node control circuit is further configured to adjust the level of the signal at the second node
  • the second node includes: M second sub-nodes; the node control circuit includes: M sub-control circuits; wherein, the m-th sub-control circuit among the M sub-control circuits corresponds to the M second sub-nodes
  • M is an integer and M ⁇ 1
  • m is an integer and 1 ⁇ m ⁇ M
  • the m th sub-control circuit is configured to adjust signals of the m th second sub-node and the first node;
  • the cascaded output circuit is further configured to provide the signal of the second reference signal terminal to the cascaded output terminal in response to the signals of the M second sub-nodes;
  • the driving output circuit is further configured to provide the signal of the fourth reference signal terminal to the cascade output terminal according to the signals of the M second sub-nodes.
  • the mth sub-control circuit corresponds to the mth third reference signal terminal
  • the mth sub-control circuit includes: the mth thirteenth transistor, the mth fourteenth transistor, the mth fifteenth transistor, the mth sixteenth transistor, and the mth seventeenth transistor;
  • the gate and first pole of the mth thirteenth transistor are electrically connected to the mth third reference signal terminal, and the second pole of the mth thirteenth transistor is electrically connected to the mth the gate of the fourteenth transistor is electrically connected;
  • the first pole of the mth fourteenth transistor is electrically connected to the mth third reference signal terminal, and the second pole of the mth fourteenth transistor is connected to the mth second sub-node electrical connection;
  • the gate of the mth fifteenth transistor is electrically connected to the first node, the first pole of the mth fifteenth transistor is electrically connected to the second reference signal terminal, and the mth fifteenth transistor is electrically connected to the second reference signal terminal.
  • the second pole of the fifteenth transistor is electrically connected to the mth second sub-node;
  • the gate of the m-th sixteenth transistor is electrically connected to the first node, the first pole of the m-th sixteenth transistor is electrically connected to the second reference signal terminal, and the m-th The second pole of the sixteenth transistor is electrically connected to the gate of the second transistor;
  • the gate of the m-th seventeenth transistor is electrically connected to the m-th second sub-node, and the first electrode of the m-th seventeenth transistor is electrically connected to the second reference signal terminal, so The second pole of the m-th seventeenth transistor is electrically connected to the first node.
  • the cascaded output circuit includes: an eighteenth transistor and M nineteenth transistors; wherein, the m-th nineteenth transistor among the M nineteenth transistors corresponds to the m-th second child node;
  • the gate of the eighteenth transistor is electrically connected to the first node, the first pole of the eighteenth transistor is electrically connected to the clock signal terminal, and the second pole of the eighteenth transistor is connected to the cascaded The output terminal is electrically connected;
  • the gate of the mth nineteenth transistor is electrically connected to the mth second sub-node, and the first electrode of the mth nineteenth transistor is electrically connected to the second reference signal terminal, so The second pole of the mth nineteenth transistor is electrically connected to the cascaded output end.
  • the drive output circuit includes: a twentieth transistor, a third capacitor, and M twenty-first transistors; wherein, the m-th twenty-first transistor of the M twenty-first transistors corresponds to the mth second child node;
  • the gate of the twentieth transistor is electrically connected to the first node, the first pole of the twentieth transistor is electrically connected to the clock signal terminal, and the second pole of the twentieth transistor is electrically connected to the drive signal terminal.
  • the output terminal is electrically connected;
  • the first pole of the third capacitor is electrically connected to the first node, and the second pole of the third capacitor is electrically connected to the drive signal output end;
  • the gate of the m-th twenty-first transistor is electrically connected to the m-th second sub-node, and the first pole of the m-th twenty-first transistor is electrically connected to the fourth reference signal terminal, so The second pole of the m-th twenty-first transistor is electrically connected to the drive signal output terminal.
  • the shift register unit further includes M twenty-second transistors; wherein, the gate of the m-th twenty-second transistor among the M twenty-second transistors is connected to the gate of the first The input signal terminal is electrically connected, the first pole of the mth twenty-second transistor is electrically connected to the second reference signal end, the mth twenty-second transistor is connected to the mth second sub-transistor The nodes are electrically connected.
  • the shift register unit further includes a twenty-third transistor
  • the gate of the twenty-third transistor is electrically connected to the initial reset signal terminal, the first pole of the twenty-third transistor is electrically connected to the second reference signal terminal, and the twenty-third transistor is electrically connected to the The first node is electrically connected.
  • the shift register unit also includes:
  • the cascade noise reduction unit is configured to provide the signal of the second reference signal terminal to the reset signal terminal in response to the signal of the cascade output terminal.
  • the cascaded noise reduction unit includes: a twelfth transistor
  • the gate of the twelfth transistor is electrically connected to the cascade output terminal, the first pole of the twelfth transistor is electrically connected to the second reference signal terminal, and the second pole of the twelfth transistor It is electrically connected with the reset signal terminal.
  • the gate drive circuit provided in the embodiment of the present disclosure, wherein, it includes a plurality of shift register units cascaded;
  • the first input signal end and the second input signal end are mutually independent signal ends, among every adjacent M shift register units in the cascade, the first input signal of the Mth shift register unit end is electrically connected to the cascaded output end of the first shift register unit, and the second input signal end of the Mth shift register unit is electrically connected to the drive output end of the first shift register unit; and, cascaded In every adjacent M+1 shift register units, the reset signal end of the first shift register unit is electrically connected to the cascaded output end of the M+1 shift register unit; wherein, M is greater than 1 integer;
  • the first input signal end of the Mth shift register unit is connected to the first input signal end of the second input signal end.
  • the cascaded output end of the first shift register unit is electrically connected; and, in every adjacent M+1 shift register units in the cascade, the reset signal end of the first shift register unit is connected to the M+1th shift register unit
  • the cascaded output terminals of the shift register cells are electrically connected.
  • the Mth shift register unit when the first input signal terminal and the second input signal terminal are independent signal terminals, in cascading every M adjacent shift register units, the Mth shift register unit
  • the first input signal end of the bit register unit is electrically connected to the cascaded output end of the first shift register unit and has a first length;
  • the second input signal end of the Mth shift register unit is connected to The wiring electrically connected to the driving output end of the first shift register unit has a second length;
  • the ratio between the first length and the second length is 1.0 ⁇ 1.5.
  • the display device provided in the embodiments of the present disclosure, including a plurality of gate lines and the gate driving circuit;
  • One gate line is electrically connected to a drive output end of a shift register unit in the gate drive circuit.
  • Fig. 1 is some structural schematic diagrams of the shift register unit in the embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of some specific shift register units in an embodiment of the present disclosure
  • FIG. 3 is a timing diagram of some signals in an embodiment of the present disclosure.
  • Fig. 4a is another specific structural schematic diagram of the shift register unit in the embodiment of the present disclosure.
  • Fig. 4b is another schematic structural diagram of the shift register unit in the embodiment of the present disclosure.
  • FIG. 5 is another schematic structural diagram of the shift register unit in an embodiment of the present disclosure.
  • FIG. 6 is another schematic structural diagram of the shift register unit in the embodiment of the present disclosure.
  • FIG. 7 is a timing diagram of some other signals in an embodiment of the present disclosure.
  • Fig. 8a is another specific structural schematic diagram of the shift register unit in the embodiment of the present disclosure.
  • Fig. 8b is another specific structural schematic diagram of the shift register unit in the embodiment of the present disclosure.
  • Fig. 9a is another specific structural schematic diagram of the shift register unit in the embodiment of the present disclosure.
  • Fig. 9b is another schematic structural diagram of the shift register unit in the embodiment of the present disclosure.
  • Fig. 10a is another schematic structural diagram of the shift register unit in the embodiment of the present disclosure.
  • Fig. 10b is another schematic structural diagram of the shift register unit in the embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of some other specific structures of the shift register unit in the embodiment of the present disclosure.
  • FIG. 12 is a timing diagram of some other signals in an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of some other specific structures of the shift register unit in the embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of some specific structures of the gate drive circuit in the embodiment of the present disclosure.
  • FIG. 15a is a schematic diagram of signals at cascaded output terminals of the gate drive circuit in an embodiment of the present disclosure
  • 15b is a schematic diagram of signals at the drive output end of the gate drive circuit in an embodiment of the present disclosure.
  • FIG. 16 is another schematic structural diagram of the gate driving circuit in the embodiment of the present disclosure.
  • some shift register units provided by the embodiments of the present disclosure may include:
  • the input circuit 10 is configured to provide the signal of the second input signal terminal INP2 to the first node N1 in response to the signal of the first input signal terminal INP1;
  • the reset circuit 20 is configured to provide the signal of the first reference signal terminal VR1 to the first node N1 in response to the signal of the reset signal terminal RST;
  • the node control circuit 30 is configured to at least adjust the level of the signal of the first node according to the signals of the second reference signal terminal VR2 and the third reference signal terminal VR3.
  • the node control circuit 30 is configured to make the level of the signal of the first node N1 opposite to the level of the signal of the second node according to the signals of the second reference signal terminal VR2 and the third reference signal terminal VR3;
  • the cascade output circuit 40 is configured to provide the signal of the clock signal terminal GCK to the cascade output terminal GT in response to the signal of the first node N1;
  • the driving output circuit 50 is configured to provide the signal of the clock signal terminal GCK to the driving output terminal ST in response to the signal of the first node N1.
  • the signal of the second input signal terminal is provided to the first node through the input circuit in response to the signal of the first input signal terminal.
  • the signal of the first reference signal terminal is provided to the first node through the reset circuit in response to the signal of the reset signal terminal.
  • the node control circuit at least adjusts the level of the signal of the first node according to the signals of the second reference signal terminal and the third reference signal terminal.
  • the signal at the clock signal terminal is provided to the cascade output terminal by the cascade output circuit in response to the signal at the first node.
  • the signal of the clock signal terminal is provided to the driving output terminal in response to the signal of the first node. This can improve the load carrying capacity of the drive output.
  • the input circuit 10 may include: a first transistor M1.
  • the gate of the first transistor M1 is electrically connected to the first input signal terminal INP1
  • the first pole of the first transistor M1 is electrically connected to the second input signal terminal INP2
  • the second pole of the first transistor M1 is electrically connected to the first node N1 electrical connection.
  • the first input signal terminal INP1 and the second input signal terminal INP2 may be set as mutually independent signal terminals. That is to say, the first input signal terminal INP1 and the second input signal terminal INP2 are not electrically connected to the same port or the same signal line.
  • the timing of the signal input from the first input signal terminal INP1 and the signal input from the second input signal terminal INP2 may be the same. For example, when the signal input to the first input signal terminal INP1 is at a high level, the signal input at the second input signal terminal INP2 is also at a high level. When the signal input to the first input signal terminal INP1 is at low level, the signal input at the second input signal terminal INP2 is also at low level.
  • the reset circuit 20 may include: a second transistor M2; wherein, the gate of the second transistor M2 is electrically connected to the reset signal terminal RST, and the second transistor M2 The first pole of the second transistor M2 is electrically connected to the first reference signal terminal VR1, and the second pole of the second transistor M2 is electrically connected to the first node N1.
  • the cascaded output circuit 40 may include: a third transistor M3; wherein, the gate of the third transistor M3 is electrically connected to the first node N1, and the third transistor M3 A first pole of the transistor M3 is electrically connected to the clock signal terminal GCK, and a second pole of the third transistor M3 is electrically connected to the cascade output terminal GT.
  • the node control circuit 30 may include: a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7; wherein, the fourth transistor The gate of M4 and its first pole are both electrically connected to the third reference signal terminal VR3, and the second pole of the fourth transistor M4 is electrically connected to the gate of the fifth transistor M5.
  • a first pole of the fifth transistor M5 is electrically connected to the third reference signal terminal VR3, and a second pole of the fifth transistor M5 is electrically connected to the second node N2.
  • the gate of the sixth transistor M6 is electrically connected to the first node N1, the first pole of the sixth transistor M6 is electrically connected to the second reference signal terminal VR2, and the second pole of the sixth transistor M6 is electrically connected to the second node N2.
  • the gate of the seventh transistor M7 is electrically connected to the second node N2, the first pole of the seventh transistor M7 is electrically connected to the second reference signal terminal VR2, and the second pole of the seventh transistor M7 is electrically connected to the first node N1.
  • the drive output circuit 50 may include: an eighth transistor M8 and a first capacitor C1; wherein, the gate of the eighth transistor M8 is electrically connected to the first node N1 connected, the first pole of the eighth transistor M8 is electrically connected to the clock signal terminal GCK, and the second pole of the eighth transistor M8 is electrically connected to the driving output terminal ST. And, the first electrode plate of the first capacitor C1 is electrically connected to the first node N1, and the second electrode plate of the first capacitor C1 is electrically connected to the driving output terminal ST.
  • the first pole of the above-mentioned transistor can be used as its source, and the second pole can be used as its drain; or, the first pole can be used as its drain, and the second pole can be used as its source. No specific distinction is made here.
  • the transistor mentioned in the above embodiments of the present disclosure may be a TFT or a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor, MOS), which is not limited herein.
  • MOS Metal Oxide Semiconductor
  • all transistors may be N-type transistors.
  • the signal of the first reference signal terminal VR1 is a low-level signal
  • the signal of the second reference signal terminal VR2 is a low-level signal
  • the signal of the third reference signal terminal VR3 is a high-level signal.
  • the first reference signal terminal VR1 and the second reference signal terminal VR2 may be independent signal terminals
  • the voltage vr2 of the second reference signal terminal VR2 may be lower than the voltage vr1 of the first reference signal terminal VR1.
  • the signal of the clock signal terminal GCK may be a clock signal in which a high level signal and a low level signal appear alternately.
  • the voltage vc1 of the low-level signal in the clock signal may be the same as the voltage vr2 of the second reference signal terminal VR2.
  • the P-type transistor is turned off under the control of a high-level signal, and turned on under the control of a low-level signal.
  • the N-type transistor is turned on under the control of a high-level signal, and turned off under the control of a low-level signal.
  • the working process of the shift register unit provided by the embodiment of the present disclosure will be described below in conjunction with the signal timing diagram shown in FIG. 3 .
  • the T1 stage, the T2 stage, and the T3 stage in the signal timing diagram shown in FIG. 3 are selected, and there are three stages in total.
  • the signal timing diagram shown in FIG. 3 is only the working process of a certain shift register unit in one display frame.
  • the working process of the shift register unit in other display frames is basically the same as the working process in this display frame, and will not be repeated here.
  • inp1 represents the signal of the first input signal terminal INP1
  • inp2 represents the signal of the second input signal terminal INP2
  • gck represents the signal of the clock signal terminal GCK
  • gt represents the signal of the cascade output terminal GT
  • st Represents the signal driving the output terminal ST
  • rst represents the signal of the reset signal terminal RST.
  • the signal inp1 is a high-level signal, which can control the first transistor M1 to be turned on, so as to provide the high-level signal of the signal inp2 to the first node N1, so that the signal of the first node N1 is a high-level signal , so that the sixth transistor M6, the third transistor M3 and the eighth transistor M8 can be controlled to be turned on, and the first capacitor C1 can be charged.
  • the turned-on sixth transistor M6 can provide the low-level signal of the second reference signal terminal VR2 to the second node N2, so that the signal of the second node N2 is a low-level signal, thereby controlling the seventh transistor M7 to be turned off.
  • the turned-on third transistor M3 can provide the low-level signal of the signal gck to the cascade output terminal GT, so that the signal gt output by the cascade output terminal GT is a low-level signal.
  • the turned-on eighth transistor M8 can provide the low-level signal of the signal gck to the driving output terminal ST, so that the signal st output from the driving output terminal ST is a low-level signal.
  • the signal rst is a low-level signal, which can control the second transistor M2 to be turned off.
  • the signal inp1 is a low-level signal, which can control the first transistor M1 to be turned off.
  • the signal rst is a low-level signal, which can control the second transistor M2 to be turned off. Due to the effect of the first capacitor C1, the signal of the first node N1 can be maintained as a high-level signal, thereby controlling the conduction of the sixth transistor M6, the third transistor M3 and the eighth transistor M8.
  • the turned-on sixth transistor M6 can provide the low-level signal of the second reference signal terminal VR2 to the second node N2, so that the signal of the second node N2 is a low-level signal, thereby controlling the seventh transistor M7 to be turned off.
  • the turned-on third transistor M3 can provide the high-level signal of the signal gck to the cascade output terminal GT, so that the signal gt output by the cascade output terminal GT is a high-level signal.
  • the turned-on eighth transistor M8 can provide the high-level signal of the signal gck to the driving output terminal ST, so that the signal st output from the driving output terminal ST is a high-level signal. Since the drive output terminal ST outputs a high-level signal, the first capacitor C1 further pulls the high level of the first node N1 high in order to maintain the voltage difference between its two ends, so that the third transistor M3 and the eighth transistor M8 can be possible full turn-on.
  • the third transistor M3 can provide the high-level signal of the signal gck to the cascade output terminal GT without voltage loss as much as possible, so that the signal gt output by the cascade output terminal GT can keep the voltage as stable as possible.
  • the eighth transistor M8 provide the high-level signal of the signal gck to the driving output terminal ST without voltage loss as much as possible, so that the voltage of the signal st output by the driving output terminal ST is as stable as possible.
  • the signal inp1 is a low-level signal, which can control the first transistor M1 to be turned off.
  • the signal rst is a low-level signal, which can control the second transistor M2 to be turned off. Due to the function of the first capacitor C1, the signal of the first node N1 can be maintained as a high level signal, thereby controlling the conduction of the sixth transistor M6, the third transistor M3 and the eighth transistor M8.
  • the turned-on sixth transistor M6 can provide the low-level signal of the second reference signal terminal VR2 to the second node N2, so that the signal of the second node N2 is a low-level signal, thereby controlling the seventh transistor M7 to be turned off.
  • the turned-on third transistor M3 can provide the low-level signal of the signal gck to the cascade output terminal GT, so that the signal gt output by the cascade output terminal GT is a low-level signal.
  • the turned-on eighth transistor M8 can provide the low-level signal of the signal gck to the driving output terminal ST, so that the signal st output from the driving output terminal ST is a low-level signal.
  • the signal inp1 is a low-level signal, which can control the first transistor M1 to be turned off.
  • the signal rst is a high-level signal, which can control the second transistor M2 to be turned on, so as to provide the low-level signal of the first reference signal terminal VR1 to the first node N1, and can make the signal of the first node N1 be low-level. level signal, so as to control the sixth transistor M6, the third transistor M3 and the eighth transistor M8 to be turned off.
  • the high-level signal of the third reference signal terminal VR3 can be input to the second node N2 through the turned-on fifth transistor M5, so that the signal of the second node N2 is a high-level signal, thereby
  • the seventh transistor M7 can be controlled to be turned on, so as to provide the signal of the second reference signal terminal VR2 to the first node N1, and further ensure that the signal of the first node N1 is a low-level signal.
  • the signal gt output from the cascade output terminal GT remains a low-level signal
  • the signal st output from the driving output terminal ST remains a low-level signal.
  • the signal st input to the gate line is output under the control of the eighth transistor M8, the signal gt for cascading the shift register units is output under the control of the third transistor M3 .
  • the size of the eighth transistor M8 can be made much larger than that of the third transistor M3, so that the carrying capacity of the signal st is much greater than that of the signal gt, thus improving the stability of the signal st.
  • the gate of the first transistor M1 since the gate of the first transistor M1 is separated from the signal of the first pole, the first signal terminal connected to the gate of the first transistor M1 can be connected to the cascade output terminal GT of the shift register unit in the cascade, and the second signal The terminal can be connected to the driving output terminal ST of the shift register unit in the cascade. Since the size of the eighth transistor M8 is prepared much larger than that of the third transistor M3, the carrying capacity of the signal st can be much greater than that of the signal gt. In this way, in the T1 phase, when the first transistor M1 is turned on, the high-level signal of the signal st is input to the first node N1, which can greatly improve the level-raising capability of the first node N1.
  • the voltage of the first node N1 is the voltage vr1 of the first reference signal terminal VR1
  • the gate voltage of the first transistor M1 is the voltage of the low-level signal of the first signal terminal, namely
  • the reset signal terminal RST to which the gate of the second transistor M2 is connected may be connected to the cascaded output terminal GT of the shift register unit in the cascade, and the first pole of the second transistor M2 may be connected to the first reference signal terminal VR1. Since the size of the eighth transistor M8 is prepared much larger than that of the third transistor M3, the carrying capacity of the signal st can be much greater than that of the signal gt. In this way, in the stages T1 and T2, when the second transistor M2 is turned off, the voltage of the gate of the second transistor M2 is the voltage of the low-level signal of the reset signal terminal RST, that is, the gate voltage of the second transistor M2 is the clock signal terminal The voltage vc1 of the low level signal of GCK.
  • the range of vc1-vr1 is -3 ⁇ -1.
  • Embodiments of the present disclosure provide structural schematic diagrams of other shift register units, as shown in FIG. 4 a and FIG. 4 b , which are modified for the implementation manners in the above embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the shift register unit in the embodiment of the present disclosure may further include: an eleventh transistor M11; wherein, the gate of the eleventh transistor M11 is electrically connected to the second node N2, and the tenth transistor M11 is electrically connected to the second node N2.
  • a first pole of a transistor M11 is electrically connected to the fifth reference signal terminal VR5, and a second pole of the eleventh transistor M11 is electrically connected to the first node N1.
  • the fifth reference signal terminal VR5 and the first reference signal terminal VR1 may be the same signal terminal.
  • the first pole of the eleventh transistor M11 is electrically connected to the first reference signal terminal VR1 .
  • the voltage vr2 of the second reference signal terminal VR2 can be made smaller than the voltage vr1 of the first reference signal terminal VR1.
  • a timing diagram of signals corresponding to the shift register units shown in FIG. 4a and FIG. 4b may be as shown in FIG. 3 .
  • the eleventh transistor M11 in the T1 and T2 phases, the eleventh transistor M11 is in a cut-off state under the control of the low-level signal of the second node N2.
  • the eleventh transistor M11 in the T3 phase, the eleventh transistor M11 is in a conduction state under the control of the high-level signal of the second node N2, and can further provide the signal of the fifth reference signal terminal VR5 to the first node N1, so that the The signal of the first node N1 is stable as a low-level signal, further improving the stability of the signal of the first node N1.
  • the working process of the remaining transistors can be basically the same as that in the above-mentioned embodiment, and details will not be repeated here.
  • the signal st input to the gate line is output under the control of the eighth transistor M8, the signal gt for cascading the shift register units is output under the control of the third transistor M3 .
  • the size of the eighth transistor M8 can be made much larger than that of the third transistor M3, so that the carrying capacity of the signal st is much greater than that of the signal gt, thus improving the stability of the signal st.
  • the gate of the first transistor M1 since the gate of the first transistor M1 is separated from the signal of the first pole, the first signal terminal connected to the gate of the first transistor M1 can be connected to the cascade output terminal GT of the shift register unit in the cascade, and the second signal The terminal can be connected to the driving output terminal ST of the shift register unit in the cascade. Since the size of the eighth transistor M8 is prepared much larger than that of the third transistor M3, the carrying capacity of the signal st can be much greater than that of the signal gt. In this way, in the T1 phase, when the first transistor M1 is turned on, the high-level signal of the signal st is input to the first node N1, which can greatly improve the level-raising capability of the first node N1.
  • the voltage of the first node N1 is the voltage vr1 of the first reference signal terminal VR1
  • the gate voltage of the first transistor M1 is the voltage of the low-level signal of the first signal terminal, namely
  • the gate voltage of the first transistor M1 is the voltage vc1 of the low-level signal of the clock signal terminal GCK.
  • the reset signal terminal RST to which the gate of the second transistor M2 is connected may be connected to the cascaded output terminal GT of the shift register unit in the cascade, and the first pole of the second transistor M2 may be connected to the first reference signal terminal VR1. Since the size of the eighth transistor M8 is prepared much larger than that of the third transistor M3, the carrying capacity of the signal st can be much greater than that of the signal gt. In this way, in the stages T1 and T2, when the second transistor M2 is turned off, the voltage of the gate of the second transistor M2 is the voltage of the low-level signal of the reset signal terminal RST, that is, the gate voltage of the second transistor M2 is the clock signal terminal The voltage vc1 of the low level signal of GCK.
  • Embodiments of the present disclosure provide still some schematic structural diagrams of shift register units, as shown in FIG. 5 , which are modified for the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the shift register unit may further include: a cascade noise reduction unit 60; wherein, the cascade noise reduction unit 60 is configured to respond to the signal of the cascade output terminal GT, The signal of the second reference signal terminal VR2 is provided to the reset signal terminal RST.
  • the cascade noise reduction unit 60 may include: a twelfth transistor M12; wherein, the gate of the twelfth transistor M12 is electrically connected to the cascade output terminal GT, and the twelfth A first pole of the transistor M12 is electrically connected to the second reference signal terminal VR2, and a second pole of the twelfth transistor M12 is electrically connected to the reset signal terminal RST.
  • the second reference signal terminal VR2 and the first reference signal terminal VR1 may be the same signal terminal.
  • the first pole of the sixth transistor M6 , the first pole of the seventh transistor M7 and the first pole of the second transistor M2 are all electrically connected to the first reference signal terminal VR1 .
  • the signal of the clock signal terminal GCK may be a clock signal in which a high level signal and a low level signal appear alternately.
  • the voltage vc1 of the low-level signal in the clock signal may be the same as the voltage vr2 of the second reference signal terminal VR2 and the voltage vr1 of the first reference signal terminal VR1.
  • the fifth reference signal terminal VR5 and the first reference signal terminal VR1 can be independent signal terminals, and the voltage of the fifth reference signal terminal VR5 is lower than the voltage of the first reference signal terminal VR1, or the fifth reference signal terminal The voltage of the terminal VR5 is greater than the voltage of the first reference signal terminal VR1.
  • the first input signal terminal INP1 and the second input signal terminal INP2 may be set as independent signal terminals. That is to say, the first input signal terminal INP1 and the second input signal terminal INP2 are not electrically connected to the same port or the same signal line.
  • the timing of the signal input from the first input signal terminal INP1 and the signal input from the second input signal terminal INP2 may also be the same. For example, when the signal input to the first input signal terminal INP1 is at a high level, the signal input at the second input signal terminal INP2 is also at a high level. When the signal input to the first input signal terminal INP1 is at low level, the signal input at the second input signal terminal INP2 is also at low level.
  • a timing diagram of signals corresponding to the shift register unit shown in FIG. 5 may be shown in FIG. 3 .
  • the twelfth transistor M12 is controlled by the low-level signal of the cascaded output terminal GT to be in a cut-off state.
  • the twelfth transistor M12 is controlled by the high-level signal of the cascaded output terminal GT to be in the conduction state, and can provide the signal of the second reference signal terminal VR2 to the reset signal terminal RST, so that the reset signal terminal RST inputs a low level signal to control the second transistor M2 to be further cut off.
  • the working process of the remaining transistors can be basically the same as that in the above-mentioned embodiment, and details will not be repeated here.
  • the gate of the second transistor M2 is input with a signal through the twelfth transistor M12, so that the leakage current of the second transistor M2 can be reduced, thereby reducing the leakage current of the first node and improving Voltage stability of the first node.
  • Embodiments of the present disclosure provide still some schematic structural diagrams of shift register units, as shown in FIG. 6 , which are modified for the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the first input signal terminal INP1 and the second input signal terminal INP2 may be the same signal terminal.
  • both the gate and the first electrode of the first transistor M1 are electrically connected to the first input signal terminal INP1 .
  • a timing diagram of signals corresponding to the shift register unit shown in FIG. 6 may be shown in FIG. 7 .
  • the first transistor M1 in the T1 phase, the first transistor M1 is turned on, and provides the high level signal of the signal inp1 to the first node N1.
  • the twelfth transistor M12 is controlled by the low-level signal of the cascade output terminal GT to be in a cut-off state.
  • the first transistor M1 is turned off.
  • the twelfth transistor M12 is controlled by the high-level signal of the cascade output terminal GT to be in a conductive state, and can provide the signal of the second reference signal terminal VR2 to the reset signal terminal RST, so that the input of the reset signal terminal RST is low level signal to control the second transistor M2 to be further cut off.
  • the first transistor M1 is turned off.
  • the twelfth transistor M12 is controlled by the low-level signal of the cascade output terminal GT to be in a cut-off state.
  • the working process of the remaining transistors may be basically the same as that in the above-mentioned embodiment, which will not be repeated here.
  • Embodiments of the present disclosure provide still some schematic structural diagrams of shift register units, as shown in FIG. 8a and FIG. 8b , which are modified for the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the first input signal terminal INP1 and the second input signal terminal INP2 may be independent signal terminals.
  • the gate of the first transistor M1 is electrically connected to the first input signal terminal INP1
  • the first pole of the first transistor M1 is electrically connected to the second input signal terminal INP2 .
  • the first input signal terminal INP1 and the second input signal terminal INP2 may be the same signal terminal.
  • both the gate and the first electrode of the first transistor M1 are electrically connected to the first input signal terminal INP1 .
  • the fifth reference signal terminal VR5 and the first reference signal terminal VR1 may be the same signal terminal.
  • the first pole of the eleventh transistor M11 and the first pole of the second transistor M2 are both electrically connected to the first reference signal terminal VR1 .
  • the voltage of the signal at the first reference signal terminal VR1 can be made greater than the voltage of the signal at the second reference signal terminal VR2 .
  • the voltage vc1 of the low-level signal in the clock signal may be the same as the voltage vr2 of the second reference signal terminal VR2.
  • FIG. 3 a timing diagram of signals corresponding to the shift register unit shown in FIG. 8a may be shown in FIG. 3 .
  • the working process of each transistor can be basically the same as the working process in the above-mentioned embodiment, and will not be repeated here.
  • a timing diagram of signals corresponding to the shift register unit shown in FIG. 8 b may be shown in FIG. 7 .
  • the working process of each transistor can be basically the same as the working process in the above-mentioned embodiment, and will not be repeated here.
  • Embodiments of the present disclosure provide some structural schematic diagrams of shift register units, as shown in FIG. 9 a and FIG. 9 b , which are modified for the implementation manners in the above embodiments. Only the differences between this embodiment and the above-mentioned embodiments will be described below, and the similarities will not be repeated here.
  • the driving output circuit 50 is further configured to provide the signal of the fourth reference signal terminal VR4 to the driving output terminal ST in response to the signal of the second node N2.
  • the drive output circuit 50 may include: a ninth transistor M9, a tenth transistor M10, and a second capacitor C2; wherein, the gate of the ninth transistor M9 is electrically connected to the first node N1
  • the first pole of the ninth transistor M9 is electrically connected to the clock signal terminal GCK
  • the second pole of the ninth transistor M9 is electrically connected to the driving output terminal ST.
  • the gate of the tenth transistor M10 is electrically connected to the second node N2, the first pole of the tenth transistor M10 is electrically connected to the fourth reference signal terminal VR4, and the second pole of the tenth transistor M10 is electrically connected to the driving output terminal ST.
  • the first electrode plate of the second capacitor C2 is electrically connected to the first node N1, and the second electrode plate of the second capacitor C2 is electrically connected to the driving output terminal ST.
  • the voltage vc1 of the low-level signal in the clock signal may be the same as the voltage vr2 of the second reference signal terminal VR2.
  • the voltage vr1 of the first reference signal terminal VR1 can be made the same as the voltage vr2 of the second reference signal terminal VR2.
  • the first input signal terminal INP1 and the second input signal terminal INP2 may be independent signal terminals.
  • the first reference signal terminal VR1 and the second reference signal terminal VR2 may be the same signal terminal.
  • the first reference signal terminal VR1 and the fourth reference signal terminal VR4 are mutually independent signal terminals, and the voltage of the first reference signal terminal VR1 is lower than the voltage of the fourth reference signal terminal VR4.
  • the first pole of the first transistor M1 and the first pole of the sixth transistor M6 and the first pole of the seventh transistor M7 can be electrically connected to the first reference signal terminal VR1 .
  • a timing diagram of signals corresponding to the shift register units shown in FIG. 9a and FIG. 9b may be as shown in FIG. 3 .
  • the working process of each transistor can be basically the same as the working process in the above-mentioned embodiment, and will not be repeated here.
  • Embodiments of the present disclosure provide still some schematic structural diagrams of shift register units, as shown in FIG. 10a and FIG. 10b , which are modified for the implementation manners in the foregoing embodiments. Only the differences between this embodiment and the above-mentioned embodiments will be described below, and the similarities will not be repeated here.
  • the first input signal terminal INP1 and the second input signal terminal INP2 may be the same signal terminal.
  • both the gate and the first electrode of the first transistor M1 are electrically connected to the first input signal terminal INP1 .
  • the voltage vc1 of the low-level signal in the clock signal may be the same as the voltage vr2 of the second reference signal terminal VR2.
  • the second reference signal terminal VR2 and the first reference signal terminal VR1 can be independent signal terminals, and the voltage vr1 of the first reference signal terminal VR1 can be made smaller than the voltage of the second reference signal terminal VR2 vr2.
  • the voltage of the first reference signal terminal VR1 and the voltage of the fourth reference signal terminal VR4 can be made the same. Further, the first reference signal terminal VR1 and the fourth reference signal terminal VR4 may be the same signal terminal. For example, as shown in FIG. 10b, the first pole of the second transistor M2 and the first pole of the tenth transistor M10 are both electrically connected to the first reference signal terminal VR1.
  • a timing diagram of signals corresponding to the shift register units shown in FIG. 10a and FIG. 10b may be as shown in FIG. 7 .
  • the working process of each transistor can be basically the same as the working process in the above-mentioned embodiment, and will not be repeated here.
  • Embodiments of the present disclosure provide still some schematic structural diagrams of shift register units, as shown in FIG. 11 , which are modified for the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the node control circuit 30 is further configured to adjust the level of the signal of the second node.
  • the second node N2 may include: M second sub-nodes; the node control circuit 30 may include: M sub-control circuits; wherein, the m-th sub-control circuit among the M sub-control circuits corresponds to the m-th among the M second sub-nodes second sub-node; M is an integer and M ⁇ 1, m is an integer and 1 ⁇ m ⁇ M; wherein, the mth sub-control circuit is configured to adjust the signal of the m-th second sub-node and the first node N1.
  • the cascaded output circuit 40 is further configured to provide the signal of the second reference signal terminal VR2 to the cascaded output terminal GT in response to the signals of the M second child nodes.
  • the driving output circuit 50 is further configured to provide the signal of the fourth reference signal terminal VR4 to the cascade output terminal ST according to the signals of the M second sub-nodes.
  • the node control circuit 30 may include: a first sub-control circuit 30-1 corresponding to the first second sub-node N2-1 one-to-one, a second sub-control circuit 30-1 corresponding to the second second sub-node N2-2 Circuit 30-2; wherein, the first sub-control circuit 30-1 is configured to adjust the signals of the first second sub-node N2-1 and the first node N1.
  • the second sub-control circuit 30-2 is configured to adjust the signals of the second second sub-node N2-2 and the first node N1.
  • the cascaded output circuit 40 is configured to make the cascaded output terminal GT output a signal according to the signals of the first node N1, the first second sub-node N2-1 and the second second sub-node N2-2.
  • the driving output circuit 50 is configured to make the driving output terminal ST output a signal according to the signals of the first node N1, the first second sub-node N2-1 and the second second sub-node N2-2.
  • the first sub-control circuit 30-1 corresponds to the first third reference signal terminal VR3-1.
  • the first sub-control circuit 30-1 may include: the first thirteenth transistor M13-1, the first fourteenth transistor M14-1, the first fifteenth transistor M15-1, the first sixteenth transistor Transistor M16-1 and the first seventeenth transistor M17-1;
  • Both the gate and the first electrode of the first thirteenth transistor M13-1 are electrically connected to the first third reference signal terminal VR3-1, and the second electrode of the first thirteenth transistor M13-1 is connected to the first The gate of a fourteenth transistor M14-1 is electrically connected;
  • the first pole of the first fourteenth transistor M14-1 is electrically connected to the first third reference signal terminal VR3-1, and the second pole of the first fourteenth transistor M14-1 is electrically connected to the first second terminal VR3-1.
  • Node N2-1 is electrically connected;
  • the gate of the first fifteenth transistor M15-1 is electrically connected to the first node N1, the first electrode of the first fifteenth transistor M15-1 is electrically connected to the second reference signal terminal VR2, and the first tenth
  • the second pole of the five-transistor M15-1 is electrically connected to the first second sub-node N2-1;
  • the gate of the first sixteenth transistor M16-1 is electrically connected to the first node N1, the first pole of the first sixteenth transistor M16-1 is electrically connected to the second reference signal terminal VR2, and the first tenth The second pole of the six transistor M16-1 is electrically connected to the gate of the first fourteenth transistor M14-1;
  • the gate of the first seventeenth transistor M17-1 is electrically connected to the first second sub-node N2-1, and the first pole of the first seventeenth transistor M17-1 is electrically connected to the second reference signal terminal VR2 , the second pole of the first seventeenth transistor M17-1 is electrically connected to the first node N1.
  • the second sub-control circuit 30-2 corresponds to the second third reference signal terminal VR3-2.
  • the second sub-control circuit 30-2 may include: the second thirteenth transistor M13-2, the second fourteenth transistor M14-2, the second fifteenth transistor M15-2, the second sixteenth transistor Transistor M16-2 and the second seventeenth transistor M17-2;
  • Both the gate and the first pole of the second thirteenth transistor M13-2 are electrically connected to the second third reference signal terminal VR3-2, and the second pole of the second thirteenth transistor M13-2 is connected to the second The gate of a fourteenth transistor M14-2 is electrically connected;
  • the first pole of the second fourteenth transistor M14-2 is electrically connected to the second third reference signal terminal VR3-2, and the second pole of the second fourteenth transistor M14-2 is connected to the second second sub-terminal Node N2-2 is electrically connected;
  • the gate of the second fifteenth transistor M15-2 is electrically connected to the first node N1, the first pole of the second fifteenth transistor M15-2 is electrically connected to the second reference signal terminal VR2, and the second tenth The second pole of the five-transistor M15-2 is electrically connected to the second second sub-node N2-2;
  • the gate of the second sixteenth transistor M16-2 is electrically connected to the first node N1, the first pole of the second sixteenth transistor M16-2 is electrically connected to the second reference signal terminal VR2, and the second tenth The second pole of the six transistor M16-2 is electrically connected to the gate of the second fourteenth transistor M14-2;
  • the gate of the second seventeenth transistor M17-2 is electrically connected to the second second sub-node N2-2, and the first pole of the second seventeenth transistor M17-2 is electrically connected to the second reference signal terminal VR2 , the second pole of the second seventeenth transistor M17-2 is electrically connected to the first node N1.
  • the cascaded output circuit 40 may include: an eighteenth transistor M18, a first nineteenth transistor M19-1, and a second nineteenth transistor M19-2;
  • the gate of the eighteenth transistor M18 is electrically connected to the first node N1, the first pole of the eighteenth transistor M18 is electrically connected to the clock signal terminal GLK, and the second pole of the eighteenth transistor M18 is electrically connected to the cascade output terminal GT ;
  • the gate of the first nineteenth transistor M19-1 is electrically connected to the first second sub-node N2-1, and the first pole of the first nineteenth transistor M19-1 is electrically connected to the second reference signal terminal VR2 , the second pole of the first nineteenth transistor M19-1 is electrically connected to the cascade output terminal GT;
  • the gate of the second nineteenth transistor M19-2 is electrically connected to the second second sub-node N2-2, and the first pole of the second nineteenth transistor M19-2 is electrically connected to the second reference signal terminal VR2 , the second pole of the second nineteenth transistor M19-2 is electrically connected to the cascade output terminal GT.
  • the size range of the nineteenth transistor M19-1 may be 200 ⁇ m ⁇ 800 ⁇ m.
  • the size of the nineteenth transistor M19-1 may be set to 200 ⁇ m.
  • the size of the nineteenth transistor M19-1 may also be set to 400 ⁇ m.
  • the size of the nineteenth transistor M19-1 may also be set to 600 ⁇ m.
  • the size of the nineteenth transistor M19-1 may also be set to 800 ⁇ m.
  • the size range of the nineteenth transistor M19-2 may be 200 ⁇ m ⁇ 800 ⁇ m.
  • the size of the nineteenth transistor M19-2 may be set to 200 ⁇ m.
  • the size of the nineteenth transistor M19-2 may also be set to 400 ⁇ m.
  • the size of the nineteenth transistor M19-2 may also be set to 600 ⁇ m.
  • the size of the nineteenth transistor M19-2 may also be set to 800 ⁇ m.
  • the size of the nineteenth transistor M19-1 and the nineteenth transistor M19-2 can be set to be the same, so that the nineteenth transistor M19- and the nineteenth transistor can be uniformly designed M19-2.
  • the drive output circuit 50 may include: a twentieth transistor M20, a third capacitor C3, a first twenty-first transistor M21-1, and a second transistor M21-1.
  • the gate of the twentieth transistor M20 is electrically connected to the first node N1, the first pole of the twentieth transistor M20 is electrically connected to the clock signal terminal GLK, and the second pole of the twentieth transistor M20 is electrically connected to the drive output terminal ST;
  • the first pole of the third capacitor C3 is electrically connected to the first node N1, and the second pole of the third capacitor C3 is electrically connected to the driving output terminal ST;
  • the gate of the first twenty-first transistor M21-1 is electrically connected to the first second sub-node N2-1, and the first pole of the first twenty-first transistor M21-1 is connected to the fourth reference signal terminal VR4 Electrically connected, the second pole of the first twenty-first transistor M21-1 is electrically connected to the drive output terminal ST;
  • the gate of the second twenty-first transistor M21-2 is electrically connected to the second second sub-node N2-2, and the first pole of the second twenty-first transistor M21-2 is connected to the fourth reference signal terminal VR4 Electrically connected, the second pole of the second twenty-first transistor M21-2 is electrically connected to the drive output terminal ST.
  • the shift register unit may also include two twenty-second transistors: the first twenty-second transistor M22-1 and the second twenty-second transistor M22-1 The twenty-second transistor M22-2; wherein, the gates of the first twenty-second transistor M22-1 and the second twenty-second transistor M22-2 are both electrically connected to the first input signal terminal INP1, The first poles of the first twenty-second transistor M22-1 and the second twenty-second transistor M22-2 are both electrically connected to the second reference signal terminal VR2.
  • the second pole of the first twenty-second transistor M22-1 is electrically connected to the first second sub-node N2-1, and the second pole of the second twenty-second transistor M22-2 is electrically connected to the second second sub-node N2-1.
  • the child node N2-2 is electrically connected.
  • the shift register unit may further include a twenty-third transistor M23; the gate of the twenty-third transistor M23 is connected to the initial reset signal terminal CRE is electrically connected, the first pole of the twenty-third transistor M23 is electrically connected to the second reference signal terminal VR2, and the twenty-third transistor M23 is electrically connected to the first node N2.
  • all transistors may be N-type transistors.
  • the signal at the first reference signal terminal VR1 can be a low-level signal
  • the signal at the second reference signal terminal VR2 can also be a low-level signal
  • the signal at the fourth reference signal terminal VR4 can also be a low-level signal.
  • the voltage of the signal of the first reference signal terminal VR1 can be made the same as the voltage of the signal of the second reference signal terminal VR2, so that the same signal terminal can be used to input voltages to the first reference signal terminal VR1 and the second reference signal terminal VR2, Thereby reducing the number of signal terminals and reducing the difficulty of wiring.
  • the second reference signal terminal VR2 and the first reference signal terminal VR1 can also be set as independent signal terminals, and the voltage of the second reference signal terminal VR2 is lower than the voltage of the first reference signal terminal VR1.
  • the TFTs in the pixels in the display area of the display panel can be completely turned off as much as possible.
  • all transistors may also be P-type transistors, which is not limited here.
  • the signal voltage of the first reference signal terminal VR1 and the fourth reference signal terminal VR4 are the same signal terminal, so that the same signal terminal can be used to input voltages to the first reference signal terminal VR1 and the second reference signal terminal VR2, thereby Reduce the number of signal terminals and reduce the difficulty of wiring.
  • the signal of the first third reference signal terminal VR3-1 and the signal of the second third reference signal terminal VR3-2 can be pulse signals switched between high level and low level respectively, and the first The level of the first third reference signal terminal VR3-1 is opposite to the level of the second third reference signal terminal VR3-2.
  • the first third reference signal terminal VR3-1 in the T10 stage, is a high-level signal, and the second third reference signal terminal VR3-2 is a low-level signal.
  • the first third reference signal terminal VR3-1 is a low-level signal
  • the second third reference signal terminal VR3-2 is a high-level signal.
  • the signal of the first third reference signal terminal VR3-1 and the signal of the second third reference signal terminal VR3-2 may also be DC signals respectively.
  • the first third reference signal terminal VR3-1 is loaded with a high-level DC signal
  • the second third reference signal terminal VR3-2 is not loaded with a signal or is loaded with a low-level DC signal.
  • the first third reference signal terminal VR3-1 is not loaded with a signal or is loaded with a low-level DC signal.
  • the first third reference signal terminal VR3-1 is a high-level DC signal
  • the second third reference signal terminal VR3-2 is a low-level DC signal.
  • the first third reference signal terminal VR3-1 is a low-level DC signal
  • the second third reference signal terminal VR3-2 is a high-level DC signal.
  • the order of the T10 stage and the T20 stage may be determined according to actual applications.
  • the work process in the T10 stage can be executed first, and then the work process in the T20 stage can be executed.
  • the work process in the T20 stage can also be executed first, and then the work process in the T10 stage can be executed.
  • the maintenance duration of the T10 stage can be made the same as that of the T20 stage.
  • the maintenance duration of the T10 phase and the maintenance duration of the T20 phase are respectively set to the duration of one display frame, the duration of multiple display frames, 2s, 1h or 24h, etc., which are not limited here.
  • the working process of the shift register unit provided by the embodiment of the present disclosure will be described in detail below in combination with the signal timing diagram shown in FIG. 12 .
  • the T10 stage and the T20 stage in the signal sequence diagram shown in FIG. 12 are selected.
  • the T11 stage, the T12 stage, and the T13 stage in the T10 stage are selected.
  • vr3-1 represents the signal of the first third reference signal terminal VR3-1
  • vr3-2 represents the signal of the second third reference signal terminal VR3-2.
  • the second and thirteenth transistor M13-2 is turned off.
  • the signal rst is at low level, so the second transistor M2 is turned off.
  • the signal inp1 is a high level signal, which can control the first transistor M1, the first twenty-second transistor M22-1 and the second twenty-second transistor M22-2 to be turned on.
  • the turned-on first transistor M1 provides the high-level signal of the signal inp2 to the first node N1, making the first node N1 a high-level signal, thereby controlling the first fifteenth transistor M15-1, the first The sixteenth transistor M16-1, the second fifteenth transistor M15-2, the second sixteenth transistor M16-2, the eighteenth transistor M18, and the twentieth transistor M20 are all turned on.
  • the turned-on first sixteenth transistor M16-1 can provide the low-level signal of the second reference signal terminal VR2 to the gate of the first fourteenth transistor M14-1 to control the first fourteenth Transistor M14-1 is off.
  • the turned-on first fifteenth transistor M15-1 can provide the low-level signal of the second reference signal terminal VR2 to the first second sub-node N2-1, so that the first second sub-node N2- 1 is a low level signal, so as to control the first seventeenth transistor M17-1, the first nineteenth transistor M19-1 and the first twenty-first transistor M21-1 to be turned off.
  • the turned-on first twenty-second transistor M22-1 provides the low-level signal of the second reference signal terminal VR2 to the first second sub-node N2-1, further making the first second sub-node N2-1 is a low level signal.
  • the turned-on second sixteenth transistor M16-2 can provide the low-level signal of the second reference signal terminal VR2 to the gate of the second fourteenth transistor M14-2, so as to control the second Fourteen transistors M14-2 are turned off.
  • the turned-on second fifteenth transistor M15-2 can provide the low-level signal of the second reference signal terminal VR2 to the second second sub-node N2-2, so that the second second sub-node N2- 2 is a low level signal, so as to control the second seventeenth transistor M17-2, the second nineteenth transistor M19-2 and the second twenty-first transistor M21-2 to be all cut off.
  • the turned-on second twenty-second transistor M22-2 provides the low-level signal of the second reference signal terminal VR2 to the second second sub-node N2-2, further making the second second sub-node N2-2 is a low level signal.
  • the turned-on eighteenth transistor M18 can provide the low-level signal of the clock signal terminal CLK to the cascade output terminal GT, so that the cascade output terminal GT outputs a low-level signal.
  • the turned-on twentieth transistor M20 can provide the low-level signal of the clock signal terminal CLK to the driving output terminal ST, so that the driving output terminal ST outputs a low-level signal.
  • the signal rst is at low level, so the second transistor M2 is turned off.
  • the signal inp1 is a low-level signal, which can control the first transistor M1, the first twenty-second transistor M22-1, and the second twenty-second transistor M22-2 to be turned off. Due to the effect of the third capacitor C3, the first node N1 can be kept as a high-level signal. Since the first node N1 is a high-level signal, the first fifteenth transistor M15-1, the first sixteenth transistor M16-1, the second fifteenth transistor M15-2, and the second transistor M15-2 are controlled. The sixteenth transistor M16 - 2 , the eighteenth transistor M18 and the twentieth transistor M20 are all turned on.
  • the turned-on first sixteenth transistor M16-1 can provide the low-level signal of the second reference signal terminal VR2 to the gate of the first fourteenth transistor M14-1 to control the first fourteenth Transistor M14-1 is off.
  • the turned-on first fifteenth transistor M15-1 can provide the low-level signal of the second reference signal terminal VR2 to the first second sub-node N2-1, so that the first second sub-node N2- 1 is a low level signal, so as to control the first seventeenth transistor M17-1, the first nineteenth transistor M19-1 and the first twenty-first transistor M21-1 to be turned off.
  • the turned-on second sixteenth transistor M16-2 can provide the low-level signal of the second reference signal terminal VR2 to the gate of the second fourteenth transistor M14-2, so as to control the second Fourteen transistors M14-2 are turned off.
  • the turned-on second fifteenth transistor M15-2 can provide the low-level signal of the second reference signal terminal VR2 to the second second sub-node N2-2, so that the second second sub-node N2- 2 is a low level signal, so as to control the second seventeenth transistor M17-2, the second nineteenth transistor M19-2 and the second twenty-first transistor M21-2 to be all cut off.
  • the turned-on eighteenth transistor M18 can provide the high-level signal of the clock signal terminal GLK to the cascade output terminal GT, so that the cascade output terminal GT outputs a high-level signal.
  • the turned-on twentieth transistor M20 can provide the high-level signal of the clock signal terminal GLK to the driving output terminal ST. Since the first node N1 is floating, the first node N1 is further pulled high, so that the twentieth transistor M20 can be completely turned on as much as possible, so that the high-level signal of the clock signal terminal GLK can be as free as possible without voltage loss.
  • the driving output terminal ST Provided to the driving output terminal ST, so that the driving output terminal ST outputs a high level signal.
  • the signal inp1 is a low-level signal, which can control the first transistor M1, the first twenty-second transistor M22-1, and the second twenty-second transistor M22-2 to all be turned off.
  • the signal rst is at a high level, so the second transistor M2 is turned on, and the low-level signal of the first reference signal terminal VR1 is provided to the first node N1, so that the first node N1 is a low-level signal, thereby controlling the first
  • the fifteenth transistor M15-1, the first sixteenth transistor M16-1, the second fifteenth transistor M15-2, the second sixteenth transistor M16-2, the eighteenth transistor M18 and the second All ten transistors M20 are turned off.
  • the second second sub-node N2-2 maintains a low-level signal, thereby controlling the second seventeenth transistor M17-2, the second nineteenth transistor M19-2, and the second twenty-first Transistors M21-2 are both turned off.
  • the first thirteenth transistor M13-1 is turned on under the control of the high-level signal of the first third reference signal terminal VR3-1, so as to turn on the high-level signal of the first third reference signal terminal VR3-1
  • the signal is provided to the gate of the first fourteenth transistor M14-1, thereby controlling the first fourteenth transistor M14-1 to be turned on.
  • the turned-on first fourteenth transistor M14-1 can provide the high-level signal of the first third reference signal terminal VR3-1 to the first second sub-node N2-1, so that the first The second sub-node N2-1 is a high-level signal, thereby controlling the first seventeenth transistor M17-1, the first nineteenth transistor M19-1, and the first twenty-first transistor M21-1 to be turned on .
  • the turned-on first seventeenth transistor M17-1 can provide the low-level signal of the second reference signal terminal VR2 to the first node N1, so that the first node N1 is further a low-level signal.
  • the turned-on first nineteenth transistor M19-1 can provide the low-level signal of the second reference signal terminal VR2 to the cascade output terminal GT, so that the cascade output terminal GT outputs a low-level signal.
  • the turned-on first twenty-first transistor M21-1 can provide the low-level signal of the fourth reference signal terminal VR4 to the driving output terminal ST, so that the driving output terminal ST outputs a low-level signal.
  • the first thirteenth transistor M13-1 is turned off.
  • the signal rst is at low level, so the second transistor M2 is turned off.
  • the signal inp1 is a high level signal, which can control the first transistor M1, the first twenty-second transistor M22-1 and the second twenty-second transistor M22-2 to be turned on.
  • the turned-on first transistor M1 provides the high-level signal of the signal inp2 to the first node N1, making the first node N1 a high-level signal, thereby controlling the first fifteenth transistor M15-1, the first The sixteenth transistor M16-1, the second fifteenth transistor M15-2, the second sixteenth transistor M16-2, the eighteenth transistor M18, and the twentieth transistor M20 are all turned on.
  • the turned-on first sixteenth transistor M16-1 can provide the low-level signal of the second reference signal terminal VR2 to the gate of the first fourteenth transistor M14-1 to control the first fourteenth Transistor M14-1 is off.
  • the turned-on first fifteenth transistor M15-1 can provide the low-level signal of the second reference signal terminal VR2 to the first second sub-node N2-1, so that the first second sub-node N2- 1 is a low level signal, so as to control the first seventeenth transistor M17-1, the first nineteenth transistor M19-1 and the first twenty-first transistor M21-1 to be turned off.
  • the turned-on first twenty-second transistor M22-1 provides the low-level signal of the second reference signal terminal VR2 to the first second sub-node N2-1, further making the first second sub-node N2-1 is a low level signal.
  • the turned-on second sixteenth transistor M16-2 can provide the low-level signal of the second reference signal terminal VR2 to the gate of the second fourteenth transistor M14-2, so as to control the second Fourteen transistors M14-2 are turned off.
  • the turned-on second fifteenth transistor M15-2 can provide the low-level signal of the second reference signal terminal VR2 to the second second sub-node N2-2, so that the second second sub-node N2- 2 is a low level signal, so as to control the second seventeenth transistor M17-2, the second nineteenth transistor M19-2 and the second twenty-first transistor M21-2 to be all cut off.
  • the turned-on second twenty-second transistor M22-2 provides the low-level signal of the second reference signal terminal VR2 to the second second sub-node N2-2, further making the second second sub-node N2-2 is a low level signal.
  • the turned-on eighteenth transistor M18 can provide the low-level signal of the clock signal terminal CLK to the cascade output terminal GT, so that the cascade output terminal GT outputs a low-level signal.
  • the turned-on twentieth transistor M20 can provide the low-level signal of the clock signal terminal CLK to the driving output terminal ST, so that the driving output terminal ST outputs a low-level signal.
  • the signal rst is at low level, so the second transistor M2 is turned off.
  • the signal inp1 is a low-level signal, which can control the first transistor M1, the first twenty-second transistor M22-1, and the second twenty-second transistor M22-2 to be turned off. Due to the effect of the third capacitor C3, the first node N1 can be kept as a high-level signal. Since the first node N1 is a high-level signal, the first fifteenth transistor M15-1, the first sixteenth transistor M16-1, the second fifteenth transistor M15-2, and the second transistor M15-2 are controlled. The sixteenth transistor M16 - 2 , the eighteenth transistor M18 and the twentieth transistor M20 are all turned on.
  • the turned-on first sixteenth transistor M16-1 can provide the low-level signal of the second reference signal terminal VR2 to the gate of the first fourteenth transistor M14-1 to control the first fourteenth Transistor M14-1 is off.
  • the turned-on first fifteenth transistor M15-1 can provide the low-level signal of the second reference signal terminal VR2 to the first second sub-node N2-1, so that the first second sub-node N2- 1 is a low level signal, so as to control the first seventeenth transistor M17-1, the first nineteenth transistor M19-1 and the first twenty-first transistor M21-1 to be turned off.
  • the turned-on second sixteenth transistor M16-2 can provide the low-level signal of the second reference signal terminal VR2 to the gate of the second fourteenth transistor M14-2 to control the second fourteenth Transistor M14-2 is off.
  • the turned-on second fifteenth transistor M15-2 can provide the low-level signal of the second reference signal terminal VR2 to the second second sub-node N2-2, so that the second second sub-node N2- 2 is a low level signal, so as to control the second seventeenth transistor M17-2, the second nineteenth transistor M19-2 and the second twenty-first transistor M21-2 to be all cut off.
  • the turned-on eighteenth transistor M18 can provide the high-level signal of the clock signal terminal GLK to the cascade output terminal GT, so that the cascade output terminal GT outputs a high-level signal.
  • the turned-on twentieth transistor M20 can provide the high-level signal of the clock signal terminal GLK to the driving output terminal ST. Since the first node N1 is floating, the first node N1 is further pulled high, so that the twentieth transistor M20 can be completely turned on as much as possible, so that the high-level signal of the clock signal terminal GLK can be as free as possible without voltage loss Provided to the driving output terminal ST, so that the driving output terminal ST outputs a high level signal.
  • the signal inp1 is a low-level signal, which can control the first transistor M1, the first twenty-second transistor M22-1, and the second twenty-second transistor M22-2 to all be turned off.
  • the signal rst is at a high level, so the second transistor M2 is turned on, and the low-level signal of the first reference signal terminal VR1 is provided to the first node N1, so that the first node N1 is a low-level signal, thereby controlling the first
  • the fifteenth transistor M15-1, the first sixteenth transistor M16-1, the second fifteenth transistor M15-2, the second sixteenth transistor M16-2, the eighteenth transistor M18 and the second All ten transistors M20 are turned off.
  • the first second sub-node N2-1 maintains a low-level signal, thereby controlling the first seventeenth transistor M17-1, the first nineteenth transistor M19-1, and the first twenty-first Transistors M21-1 are both turned off.
  • the second thirteenth transistor M13-2 is turned on under the control of the high-level signal of the second third reference signal terminal VR3-2, so as to turn on the high-level signal of the second third reference signal terminal VR3-2
  • the signal is provided to the gate of the second fourteenth transistor M14-2, thereby controlling the second fourteenth transistor M14-2 to be turned on.
  • the turned-on second fourteenth transistor M14-2 can provide the high-level signal of the second third reference signal terminal VR3-2 to the second second sub-node N2-2, so that the second The second sub-node N2-2 is a high-level signal, thereby controlling the second seventeenth transistor M17-2, the second nineteenth transistor M19-2, and the second twenty-first transistor M21-2 to be turned on .
  • the turned-on second seventeenth transistor M17-2 can provide the low-level signal of the second reference signal terminal VR2 to the first node N1, so that the first node N1 further receives a low-level signal.
  • the turned-on second nineteenth transistor M19-2 can provide the low-level signal of the second reference signal terminal VR2 to the cascade output terminal GT, so that the cascade output terminal GT outputs a low-level signal.
  • the turned-on second twenty-first transistor M21-2 can provide the low-level signal of the fourth reference signal terminal VR4 to the driving output terminal ST, so that the driving output terminal ST outputs a low-level signal.
  • the first sub-control circuit 30 - 1 works in the T10 stage.
  • the second sub-control circuit 30-2 operates in the T20 stage. Therefore, the characteristics of the transistor can be restored alternately, thereby reducing the influence on the stability and life of the output signal caused by the characteristic drift caused by the use of the transistor, thereby enhancing the life of the product and reducing the production cost.
  • the first input terminal and the second input signal terminal may also be set as the same signal terminal.
  • both the gate and the first electrode of the first transistor M1 are electrically connected to the first input terminal INP1 .
  • Embodiments of the present disclosure also provide some gate driving circuits, including a plurality of the above-mentioned shift register units cascaded.
  • the first input signal terminal INP1 and the second input signal terminal INP2 are independent signal terminals
  • the first input signal terminal INP1 of the shift register unit of the first stage is electrically connected to the cascade start signal terminal GTV.
  • the second input signal terminal INP2 of the first-stage shift register unit is electrically connected to the frame start signal terminal STV.
  • the signals of the concatenation start signal terminal GTV and the frame start signal terminal STV are the same.
  • the first input signal terminal INP1 of the Mth shift register unit is electrically connected to the cascaded output terminal GT of the first shift register unit, and the Mth shift register unit
  • the second input signal terminal INP2 of the first shift register unit is electrically connected to the drive output end ST of the first shift register unit; and, in every adjacent M+1 shift register units cascaded, the first shift register unit
  • the reset signal terminal RST of the bit register unit is electrically connected to the cascaded output terminal GT of the M+1th shift register unit.
  • M is an integer greater than 1.
  • the first shift register unit of the Mth shift register unit The wiring electrically connecting an input signal terminal INP1 to the cascaded output terminal GT of the first shift register unit has a first length CH1. And, the wiring electrically connected to the second input signal terminal INP2 of the Mth shift register unit and the drive output terminal ST of the first shift register unit has a second length CH2.
  • CH1/CH2 may be 1.0-1.5.
  • the wires electrically connected to the first input signal terminal INP1 of the Mth shift register unit and the cascaded output terminal GT of the first shift register unit and the Mth shift register Reasonable layout design is carried out for the wiring that electrically connects the second input signal terminal INP2 of the unit to the driving output terminal ST of the first shift register unit.
  • the second length CH2 is smaller than the first length CH1, which can reduce the delay of the signal of the second input signal terminal INP2 of the shift register unit.
  • CH1/CH2 can be 1.0, CH1/CH2 can also be 1.1, CH1/CH2 can also be 1.2, CH1/CH2 can also be 1.3, CH1/CH2 can also be 1.4, and CH1/CH2 can also be 1.5 , is not limited here.
  • the cascaded output terminal GT of the first-stage shift register unit SR1 is electrically connected to the first input signal terminal INP1 of the seventh-stage shift register unit SR7, that is, the first-stage shift
  • the signal st1 of the cascaded output terminal GT of the register unit SR1 is input as the signal of the first input signal terminal INP1 of the seventh-stage shift register unit SR7.
  • the cascaded output terminal GT of the second-stage shift register unit SR2 is electrically connected to the first input signal terminal INP1 of the eighth-stage shift register unit SR8, that is, the signal of the cascaded output terminal GT of the second-stage shift register unit SR2 st2 is used as the signal input of the first input signal terminal INP1 of the shift register unit SR8 of the eighth stage.
  • the cascaded output terminal GT of the third-stage shift register unit SR3 is electrically connected to the first input signal terminal INP1 of the ninth-stage shift register unit SR9, that is, the signal of the cascaded output terminal GT of the third-stage shift register unit SR3 st3 is used as the signal input of the first input signal terminal INP1 of the ninth stage shift register unit SR9.
  • the rest can be deduced in the same way, and will not be repeated here.
  • the cascaded output terminal GT of the eighth-stage shift register unit SR8 is electrically connected to the reset signal terminal RST of the first-stage shift register unit SR1, that is, the eighth-stage shift register unit
  • the signal st8 of the cascaded output terminal GT of SR8 is used as the signal input of the reset signal terminal RST of the shift register unit SR1 of the first stage.
  • the cascade output terminal GT of the ninth-stage shift register unit SR9 is electrically connected to the reset signal terminal RST of the second-stage shift register unit SR2, and the signal st9 of the cascade output terminal GT of the ninth-stage shift register unit SR9 is used as The signal input of the reset signal terminal RST of the second-stage shift register unit SR2. The rest can be deduced in the same way, and will not be repeated here.
  • the drive output terminal ST of the first-stage shift register unit SR1 is electrically connected to the second input signal terminal INP2 of the seventh-stage shift register unit SR7, that is, the first-stage shift register
  • the signal gt1 of the driving output terminal ST of the unit SR1 is input as the signal of the second input signal terminal INP2 of the seventh-stage shift register unit SR7.
  • the drive output terminal ST of the second-stage shift register unit SR2 is electrically connected to the second input signal terminal INP2 of the eighth-stage shift register unit SR8, and the signal gt2 of the drive output terminal ST of the second-stage shift register unit SR2 is used as The signal input of the second input signal terminal INP2 of the eighth-stage shift register unit SR8.
  • the driving output terminal ST of the third-stage shift register unit SR3 is electrically connected to the second input signal terminal INP2 of the ninth-stage shift register unit SR9, and the signal gt3 of the driving output terminal ST of the third-stage shift register unit SR3 is used as The signal input of the second input signal terminal INP2 of the ninth stage shift register unit SR9. The rest can be deduced in the same way, and will not be repeated here.
  • signals st1 - st14 are output from the cascaded output terminals GT of the first-stage shift register unit to the fourteenth-stage shift register unit.
  • Signals gt1 - gt14 output from the driving output terminals ST of the shift register units of the first stage to the fourteenth stage of shift register units.
  • M can also be set to other values, which can be designed and determined according to the requirements of practical applications, and are not limited here.
  • Another gate driving circuit provided by an embodiment of the present disclosure includes a plurality of the above-mentioned shift register units cascaded.
  • the first input signal terminal INP1 and the second input signal terminal INP2 are the same signal terminal
  • the first input signal terminal INP1 of the first-stage shift register unit is electrically connected to the frame start signal terminal STV.
  • the first input signal terminal INP1 of the Mth shift register unit is electrically connected to the cascade output terminal GT of the first shift register unit; and, each of the cascaded Among the adjacent M+1 shift register units, the reset signal terminal RST of the first shift register unit is electrically connected to the cascade output terminal GT of the M+1 shift register unit.
  • M is an integer greater than 1.
  • the seventh shift register unit The first input signal terminal INP1 of the register unit is electrically connected to the cascade output terminal GT of the first shift register unit; and, in cascading every 8 adjacent shift register units, the first shift register unit
  • the reset signal terminal RST is electrically connected to the cascaded output terminal GT of the eighth shift register unit.
  • the cascaded output terminal GT of the first-stage shift register unit SR1 is electrically connected to the first input signal terminal INP1 of the seventh-stage shift register unit SR7, that is, the first-stage shift
  • the signal st1 of the cascaded output terminal GT of the register unit SR1 is input as the signal of the first input signal terminal INP1 of the seventh-stage shift register unit SR7.
  • the cascaded output terminal GT of the second-stage shift register unit SR2 is electrically connected to the first input signal terminal INP1 of the eighth-stage shift register unit SR8, that is, the signal of the cascaded output terminal GT of the second-stage shift register unit SR2 st2 is used as the signal input of the first input signal terminal INP1 of the shift register unit SR8 of the eighth stage.
  • the cascaded output terminal GT of the third-stage shift register unit SR3 is electrically connected to the first input signal terminal INP1 of the ninth-stage shift register unit SR9, that is, the signal of the cascaded output terminal GT of the third-stage shift register unit SR3 st3 is used as the signal input of the first input signal terminal INP1 of the ninth stage shift register unit SR9.
  • the rest can be deduced in the same way, and will not be repeated here.
  • the cascaded output terminal GT of the eighth-stage shift register unit SR8 is electrically connected to the reset signal terminal RST of the first-stage shift register unit SR1, that is, the eighth-stage shift register unit
  • the signal st8 of the cascaded output terminal GT of SR8 is used as the signal input of the reset signal terminal RST of the shift register unit SR1 of the first stage.
  • the cascade output terminal GT of the ninth-stage shift register unit SR9 is electrically connected to the reset signal terminal RST of the second-stage shift register unit SR2, and the signal st9 of the cascade output terminal GT of the ninth-stage shift register unit SR9 is used as The signal input of the reset signal terminal RST of the second-stage shift register unit SR2. The rest can be deduced in the same way, and will not be repeated here.
  • the cascaded output terminals GT of the first stage shift register unit to the fourteenth stage shift register unit output signals st1 - st14 .
  • Signals gt1 - gt14 output from the driving output terminals ST of the shift register units of the first stage to the fourteenth stage of shift register units.
  • M can also be set to other values, which can be designed and determined according to the requirements of practical applications, and are not limited here.
  • each twenty-third transistor in the gate driving circuit can be electrically connected to the same frame reset terminal. In this way, each twenty-third transistor in the gate driving circuit can be controlled to be turned on simultaneously before a frame starts, so as to reset the first node as a whole.
  • an embodiment of the present disclosure further provides a display device, including a plurality of gate lines and the above-mentioned gate driving circuit provided by the embodiment of the present disclosure.
  • the problem-solving principle of the display device is similar to that of the aforementioned gate drive circuit, so the implementation of the display device can refer to the implementation of the aforementioned gate drive circuit, and repeated descriptions will not be repeated here.
  • one gate line can be made to correspond to one shift register unit in the gate drive circuit, so that the driving of one gate line and one shift register unit in the gate drive circuit
  • the output end ST is electrically connected so that the shift register unit inputs a scan signal to the electrically connected gate line.
  • the display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as limitations on the present disclosure.
  • the signal of the second input signal terminal is provided to the first node through the input circuit in response to the signal of the first input signal terminal.
  • the signal of the first reference signal terminal is provided to the first node through the reset circuit in response to the signal of the reset signal terminal.
  • the level of the signal at the first node and the level of the signal at the second node are reversed by the node control circuit according to the signals at the second reference signal terminal and the third reference signal terminal.
  • the signal at the clock signal terminal is provided to the cascade output terminal by the cascade output circuit in response to the signal at the first node.
  • the signal of the clock signal terminal is provided to the driving output terminal in response to the signal of the first node. This can improve the load carrying capacity of the drive output.

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Abstract

一种移位寄存器单元、栅极驱动电路及显示装置，输入电路(10)，被配置为响应于第一输入信号端(INP1)的信号，将第二输入信号端(INP2)的信号，提供给第一节点(N1)；复位电路(20)，被配置为响应于复位信号端(RST)的信号，将第一参考信号端(VR1)的信号，提供给第一节点(N1)；节点控制电路(30)，被配置为根据第二参考信号端(VR2)和第三参考信号端(VR3)的信号，至少调节第一节点(N1)的信号的电平；级联输出电路(40)，被配置为响应于第一节点(N1)的信号，将时钟信号端(GCK)的信号提供给级联输出端(GT)；驱动输出电路(50)，被配置为响应于第一节点(N1)的信号，将时钟信号端(GCK)的信号提供给驱动输出端(ST)。

Description

移位寄存器单元、栅极驱动电路及显示装置
相关申请的交叉引用
本申请要求在2021年10月26日提交中国专利局、申请号为202111245661.7、申请名称为“移位寄存器单元、栅极驱动电路及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及移位寄存器单元、栅极驱动电路及显示装置。
背景技术
随着显示技术的飞速发展，显示装置越来越向着高集成度和低成本的方向发展。其中，GOA(Gate Driver on Array，阵列基板行驱动)技术将TFT(Thin Film Transistor，薄膜晶体管)制备在显示装置的阵列基板上，以形成栅极驱动电路，从而实现对显示装置的扫描驱动。其中，驱动电路通常由多个级联的移位寄存器单元构成。然而，移位寄存器单元输出不稳定，会导致显示异常。
发明内容
本公开实施例提供的移位寄存器单元，包括：
输入电路，被配置为响应于第一输入信号端的信号，将第二输入信号端的信号，提供给第一节点；
复位电路，被配置为响应于复位信号端的信号，将第一参考信号端的信号，提供给所述第一节点；
节点控制电路，被配置为根据第二参考信号端和第三参考信号端的信号，至少调节所述第一节点的信号的电平；
级联输出电路，被配置为响应于所述第一节点的信号，将时钟信号端的信号提供给级联输出端；
驱动输出电路，被配置为响应于所述第一节点的信号，将所述时钟信号端的信号提供给驱动输出端。
在一些示例中，所述输入电路包括：第一晶体管；
所述第一晶体管的栅极与所述第一输入信号端电连接，所述第一晶体管的第一极与所述第二输入信号端电连接，所述第一晶体管的第二极与所述第一节点电连接。
在一些示例中，所述第一输入信号端和所述第二输入信号端为同一信号端；或者，
所述第一输入信号端和所述第二输入信号端为相互独立的信号端。
在一些示例中，所述复位电路包括：第二晶体管；
所述第二晶体管的栅极与所述复位信号端电连接，所述第二晶体管的第一极与所述第一参考信号端电连接，所述第二晶体管的第二极与所述第一节点电连接。
在一些示例中，所述级联输出电路包括：第三晶体管；
所述第三晶体管的栅极与所述第一节点电连接，所述第三晶体管的第一极与所述时钟信号端电连接，所述第三晶体管的第二极与所述级联输出端电连接。
在一些示例中，所述节点控制电路包括：第四晶体管、第五晶体管、第六晶体管以及第七晶体管；
所述第四晶体管的栅极及其第一极均与所述第三参考信号端电连接，所述第四晶体管的第二极与所述第五晶体管的栅极电连接；
所述第五晶体管的第一极与所述第三参考信号端电连接，所述第五晶体管的第二极与所述第二节点电连接；
所述第六晶体管的栅极与所述第一节点电连接，所述第六晶体管的第一极与所述第二参考信号端电连接，所述第六晶体管的第二极与所述第二节点 电连接；
所述第七晶体管的栅极与所述第二节点电连接，所述第七晶体管的第一极与所述第二参考信号端电连接，所述第七晶体管的第二极与所述第一节点电连接。
在一些示例中，所述第二参考信号端和所述第一参考信号端为同一信号端；或者，
所述第二参考信号端和所述第一参考信号端为相互独立的信号端，且所述第二参考信号端的电压小于所述第一参考信号端的电压。
在一些示例中，所述驱动输出电路包括：第八晶体管和第一电容；
所述第八晶体管的栅极与所述第一节点电连接，所述第八晶体管的第一极与所述时钟信号端电连接，所述第八晶体管的第二极与所述驱动输出端电连接；
所述第一电容的第一电极板与所述第一节点电连接，所述第一电容的第二电极板与所述驱动输出端电连接。
在一些示例中，所述驱动输出电路还被配置为响应于所述第二节点的信号，将第四参考信号端的信号提供给所述驱动输出端。
在一些示例中，所述驱动输出电路包括：第九晶体管和第十晶体管以及第二电容；
所述第九晶体管的栅极与所述第一节点电连接，所述第九晶体管的第一极与所述时钟信号端电连接，所述第九晶体管的第二极与所述驱动输出端电连接；
所述第十晶体管的栅极与所述第二节点电连接，所述第十晶体管的第一极与所述第四参考信号端电连接，所述第十晶体管的第二极与所述驱动输出端电连接；
所述第二电容的第一电极板与所述第一节点电连接，所述第二电容的第二电极板与所述驱动输出端电连接。
在一些示例中，所述第一参考信号端和所述第四参考信号端为同一信号 端；或者，
所述第一参考信号端和所述第四参考信号端为相互独立的信号端，且所述第一参考信号端的电压小于所述第四参考信号端的电压。
在一些示例中，所述移位寄存器单元还包括：第十一晶体管；
所述第十一晶体管的栅极与所述第二节点电连接，所述第十一晶体管的第一极与第五参考信号端电连接，所述第十一晶体管的第二极与所述第一节点电连接。
在一些示例中，所述第五参考信号端和所述第一参考信号端为同一信号端；或者，
所述第五参考信号端和所述第一参考信号端为相互独立的信号端，且所述第五参考信号端的电压小于所述第一参考信号端的电压。
在一些示例中，所述节点控制电路还被配置为调节第二节点的信号的电平；
所述第二节点包括：M个第二子节点；所述节点控制电路包括：M个子控制电路；其中，所述M个子控制电路中的第m个子控制电路对应所述M个第二子节点中的第m个第二子节点；M为整数且M≥1，m为整数且1≤m≤M；
所述第m个子控制电路被配置为调整所述第m个第二子节点和所述第一节点的信号；
所述级联输出电路还被配置为响应于所述M个第二子节点的信号，将所述第二参考信号端的信号提供给所述级联输出端；
所述驱动输出电路还被配置为根据所述M个第二子节点的信号，将第四参考信号端的信号提供给所述级联输出端。
在一些示例中，所述第m个子控制电路对应第m个第三参考信号端；
所述第m个子控制电路包括：第m个第十三晶体管、第m个第十四晶体管、第m个第十五晶体管、第m个第十六晶体管以及第m个第十七晶体管；
所述第m个第十三晶体管的栅极与第一极均与所述第m个第三参考信号端电连接，所述第m个第十三晶体管的第二极与所述第m个第十四晶体管的 栅极电连接；
所述第m个第十四晶体管的第一极与所述第m个第三参考信号端电连接，所述第m个第十四晶体管的第二极与所述第m个第二子节点电连接；
所述第m个第十五晶体管的栅极与所述第一节点电连接，所述第m个第十五晶体管的第一极与所述第二参考信号端电连接，所述第m个第十五晶体管的第二极与所述第m个第二子节点电连接；
所述第m个第十六晶体管的栅极与所述第一节点电连接，所述第m个第十六晶体管的第一极与所述第二参考信号端电连接，所述第m个第十六晶体管的第二极与所述第二晶体管的栅极电连接；
所述第m个第十七晶体管的栅极与所述第m个第二子节点电连接，所述第m个第十七晶体管的第一极与所述第二参考信号端电连接，所述第m个第十七晶体管的第二极与所述第一节点电连接。
在一些示例中，所述级联输出电路包括：第十八晶体管以及M个第十九晶体管；其中，所述M个第十九晶体管中的第m个第十九晶体管对应所述第m个第二子节点；
所述第十八晶体管的栅极与所述第一节点电连接，所述第十八晶体管的第一极与时钟信号端电连接，所述第十八晶体管的第二极与所述级联输出端电连接；
所述第m个第十九晶体管的栅极与所述第m个第二子节点电连接，所述第m个第十九晶体管的第一极与所述第二参考信号端电连接，所述第m个第十九晶体管的第二极与所述级联输出端电连接。
在一些示例中，所述驱动输出电路包括：第二十晶体管、第三电容以及M个第二十一晶体管；其中，所述M个第二十一晶体管的第m个第二十一晶体管对应所述第m个第二子节点；
所述第二十晶体管的栅极与所述第一节点电连接，所述第二十晶体管的第一极与时钟信号端电连接，所述第二十晶体管的第二极与所述驱动信号输出端电连接；
所述第三电容的第一极与所述第一节点电连接，第三电容的第二极与所述驱动信号输出端电连接；
所述第m个第二十一晶体管的栅极与所述第m个第二子节点电连接，所述第m个第二十一晶体管的第一极与第四参考信号端电连接，所述第m个第二十一晶体管的第二极与所述驱动信号输出端电连接。
在一些示例中，所述移位寄存器单元还包括M个第二十二晶体管；其中，所述M个第二十二晶体管中的第m个第二十二晶体管的栅极与所述第一输入信号端电连接，所述第m个第二十二晶体管的第一极与所述第二参考信号端电连接，所述第m个第二十二晶体管与所述第m个第二子节点电连接。
在一些示例中，所述移位寄存器单元还包括第二十三晶体管；
所述第二十三晶体管的栅极与初始复位信号端电连接，所述第二十三晶体管的第一极与所述第二参考信号端电连接，所述第二十三晶体管与所述第一节点电连接。
在一些示例中，所述移位寄存器单元还包括：
级联降噪单元，被配置为响应于所述级联输出端的信号，将所述第二参考信号端的信号提供给所述复位信号端。
在一些示例中，所述级联降噪单元包括：第十二晶体管；
所述第十二晶体管的栅极与所述级联输出端电连接，所述第十二晶体管的第一极与所述第二参考信号端电连接，所述第十二晶体管的第二极与复位信号端电连接。
本公开实施例中提供的栅极驱动电路，其中，包括级联的多个所述的移位寄存器单元；
在所述第一输入信号端和所述第二输入信号端为相互独立的信号端时，级联每相邻的M个移位寄存器单元中，第M个移位寄存器单元的第一输入信号端与第1个移位寄存器单元的级联输出端电连接，且第M个移位寄存器单元的第二输入信号端与第1个移位寄存器单元的驱动输出端电连接；并且，级联每相邻的M+1个移位寄存器单元中，第1个移位寄存器单元的复位信号 端与第M+1个移位寄存器单元的级联输出端电连接；其中，M为大于1的整数；
在所述第一输入信号端和所述第二输入信号端为同一信号端时，级联每相邻的M个移位寄存器单元中，第M个移位寄存器单元的第一输入信号端与第1个移位寄存器单元的级联输出端电连接；并且，级联每相邻的M+1个移位寄存器单元中，第1个移位寄存器单元的复位信号端与第M+1个移位寄存器单元的级联输出端电连接。
在一些示例中，在所述第一输入信号端和所述第二输入信号端为相互独立的信号端时，在级联每相邻的M个移位寄存器单元中，所述第M个移位寄存器单元的第一输入信号端与所述第1个移位寄存器单元的级联输出端电连接的走线具有第一长度；所述第M个移位寄存器单元的第二输入信号端与所述第1个移位寄存器单元的驱动输出端电连接的走线具有第二长度；
所述第一长度与所述第二长度之间的比值为1.0～1.5。
本公开实施例中提供的显示装置，其中，包括多条栅线以及所述的栅极驱动电路；
一条所述栅线与所述栅极驱动电路中的一个移位寄存器单元的驱动输出端电连接。
附图说明
图1为本公开实施例中的移位寄存器单元的一些结构示意图；
图2为本公开实施例中的移位寄存器单元的一些具体结构示意图；
图3为本公开实施例中的一些信号时序图；
图4a为本公开实施例中的移位寄存器单元的又一些具体结构示意图；
图4b为本公开实施例中的移位寄存器单元的又一些具体结构示意图；
图5为本公开实施例中的移位寄存器单元的又一些具体结构示意图；
图6为本公开实施例中的移位寄存器单元的又一些具体结构示意图；
图7为本公开实施例中的又一些信号时序图；
图8a为本公开实施例中的移位寄存器单元的又一些具体结构示意图；
图8b为本公开实施例中的移位寄存器单元的又一些具体结构示意图；
图9a为本公开实施例中的移位寄存器单元的又一些具体结构示意图；
图9b为本公开实施例中的移位寄存器单元的又一些具体结构示意图；
图10a为本公开实施例中的移位寄存器单元的又一些具体结构示意图；
图10b为本公开实施例中的移位寄存器单元的又一些具体结构示意图；
图11为本公开实施例中的移位寄存器单元的又一些具体结构示意图；
图12为本公开实施例中的又一些信号时序图；
图13为本公开实施例中的移位寄存器单元的又一些具体结构示意图；
图14为本公开实施例中的栅极驱动电路的一些具体结构示意图；
图15a为本公开实施例中的栅极驱动电路的级联输出端的信号的示意图；
图15b为本公开实施例中的栅极驱动电路的驱动输出端的信号的示意图；
图16为本公开实施例中的栅极驱动电路的另一些具体结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接， 而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
如图1所示，本公开实施例提供的一些移位寄存器单元，可以包括：
输入电路10，被配置为响应于第一输入信号端INP1的信号，将第二输入信号端INP2的信号，提供给第一节点N1；
复位电路20，被配置为响应于复位信号端RST的信号，将第一参考信号端VR1的信号，提供给第一节点N1；
节点控制电路30，被配置为根据第二参考信号端VR2和第三参考信号端VR3的信号，至少调节第一节点的信号的电平。例如，节点控制电路30，被配置为根据第二参考信号端VR2和第三参考信号端VR3的信号，使第一节点N1的信号的电平和第二节点的信号的电平相反；
级联输出电路40，被配置为响应于第一节点N1的信号，将时钟信号端GCK的信号提供给级联输出端GT；
驱动输出电路50，被配置为响应于第一节点N1的信号，将时钟信号端GCK的信号提供给驱动输出端ST。
本公开实施例提供的移位寄存器单元，通过输入电路响应于第一输入信号端的信号，将第二输入信号端的信号，提供给第一节点。通过复位电路响应于复位信号端的信号，将第一参考信号端的信号，提供给第一节点。通过节点控制电路根据第二参考信号端和第三参考信号端的信号，至少调节第一节点的信号的电平。通过级联输出电路响应于第一节点的信号，将时钟信号端的信号提供给级联输出端。以及通过驱动输出电路，响应于第一节点的信号，将时钟信号端的信号提供给驱动输出端。这样可以提高驱动输出端的带载能力。
在具体实施时，在本公开实施例中，如图2所示，输入电路10可以包括：第一晶体管M1。其中，第一晶体管M1的栅极与第一输入信号端INP1电连 接，第一晶体管M1的第一极与第二输入信号端INP2电连接，第一晶体管M1的第二极与第一节点N1电连接。
在具体实施时，在本公开实施例中，如图2所示，可以使第一输入信号端INP1和第二输入信号端INP2设置为相互独立的信号端。也就是说，第一输入信号端INP1和第二输入信号端INP2并不会电连接到同一个端口或同一条信号线。示例性地，如图3所示，可以使第一输入信号端INP1输入的信号和第二输入信号端INP2输入的信号的时序相同。例如，在第一输入信号端INP1输入的信号为高电平时，第二输入信号端INP2输入的信号也为高电平。在第一输入信号端INP1输入的信号为低电平时，第二输入信号端INP2输入的信号也为低电平。
在具体实施时，在本公开实施例中，如图2所示，复位电路20可以包括：第二晶体管M2；其中，第二晶体管M2的栅极与复位信号端RST电连接，第二晶体管M2的第一极与第一参考信号端VR1电连接，第二晶体管M2的第二极与第一节点N1电连接。
在具体实施时，在本公开实施例中，如图2所示，级联输出电路40可以包括：第三晶体管M3；其中，第三晶体管M3的栅极与第一节点N1电连接，第三晶体管M3的第一极与时钟信号端GCK电连接，第三晶体管M3的第二极与级联输出端GT电连接。
在具体实施时，在本公开实施例中，如图2所示，节点控制电路30可以包括：第四晶体管M4、第五晶体管M5、第六晶体管M6以及第七晶体管M7；其中，第四晶体管M4的栅极及其第一极均与第三参考信号端VR3电连接，第四晶体管M4的第二极与第五晶体管M5的栅极电连接。第五晶体管M5的第一极与第三参考信号端VR3电连接，第五晶体管M5的第二极与第二节点N2电连接。第六晶体管M6的栅极与第一节点N1电连接，第六晶体管M6的第一极与第二参考信号端VR2电连接，第六晶体管M6的第二极与第二节点N2电连接。第七晶体管M7的栅极与第二节点N2电连接，第七晶体管M7的第一极与第二参考信号端VR2电连接，第七晶体管M7的第二极与第 一节点N1电连接。
在具体实施时，在本公开实施例中，如图2所示，驱动输出电路50可以包括：第八晶体管M8和第一电容C1；其中，第八晶体管M8的栅极与第一节点N1电连接，第八晶体管M8的第一极与时钟信号端GCK电连接，第八晶体管M8的第二极与驱动输出端ST电连接。以及，第一电容C1的第一电极板与第一节点N1电连接，第一电容C1的第二电极板与驱动输出端ST电连接。
在具体实施时，根据信号的流通方向，上述晶体管的第一极可以作为其源极，第二极可以作为其漏极；或者，第一极作为其漏极，第二极作为其源极，在此不作具体区分。
需要说明的是，本公开上述实施例中提到的晶体管可以是TFT，也可以是金属氧化物半导体场效应管(Metal Oxide Semiconductor，MOS)，在此不作限定。
为了简化制备工艺，在具体实施时，在本公开实施例中，如图2所示，可以使所有晶体管均为N型晶体管。并且，第一参考信号端VR1的信号为低电平信号，第二参考信号端VR2的信号为低电平信号，第三参考信号端VR3的信号为高电平信号。示例性地，第一参考信号端VR1和第二参考信号端VR2可以为相互独立的信号端，并且，可以使第二参考信号端VR2的电压vr2小于第一参考信号端VR1的电压vr1。
示例性地，时钟信号端GCK的信号可以为高电平信号和低电平信号交替出现的时钟信号。其中，该时钟信号中的低电平信号的电压vc1可以与第二参考信号端VR2的电压vr2相同。
当然，在本公开实施例中，仅是以晶体管为N型晶体管为例进行说明的，对于晶体管为P型晶体管的情况，设计原理与本公开相同，也属于本公开保护的范围。
在具体实施时，P型晶体管在高电平信号的控制下截止，在低电平信号的控制下导通。N型晶体管在高电平信号的控制下导通，在低电平信号的控制 下截止。
以上仅是举例说明本公开实施例提供的移位寄存器单元的具体结构，在具体实施时，上述各电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
下面以图2所示的移位寄存器单元为例，结合图3所示的信号时序图对本公开实施例提供的上述移位寄存器单元的工作过程作以描述。例如，选取如图3所示的信号时序图中的T1阶段、T2阶段、T3阶段，共三个阶段。需要说明的是，图3所示的信号时序图仅是某一个移位寄存器单元在一个显示帧中的工作过程。该移位寄存器单元在其他显示帧中的工作过程分别与该显示帧中的工作过程基本相同，在此不作赘述。
并且，如图3所示，inp1代表第一输入信号端INP1的信号，inp2代表第二输入信号端INP2的信号，gck代表时钟信号端GCK的信号，gt代表级联输出端GT的信号，st代表驱动输出端ST的信号，rst代表复位信号端RST的信号。
在T1阶段，信号inp1为高电平信号，可以控制第一晶体管M1导通，以将信号inp2的高电平信号提供给第一节点N1，以使第一节点N1的信号为高电平信号，从而可以控制第六晶体管M6、第三晶体管M3以及第八晶体管M8导通，以及对第一电容C1充电。导通的第六晶体管M6可以将第二参考信号端VR2的低电平信号提供给第二节点N2，以使第二节点N2的信号为低电平信号，从而可以控制第七晶体管M7截止。导通的第三晶体管M3可以将信号gck的低电平信号提供给级联输出端GT，以使级联输出端GT输出的信号gt为低电平信号。导通的第八晶体管M8可以将信号gck的低电平信号提供给驱动输出端ST，以使驱动输出端ST输出的信号st为低电平信号。并且，信号rst为低电平信号，可以控制第二晶体管M2截止。
在T2阶段，信号inp1为低电平信号，可以控制第一晶体管M1截止。以及信号rst为低电平信号，可以控制第二晶体管M2截止。由于第一电容C1的作用，可以使第一节点N1的信号保持为高电平信号，从而可以控制第六晶 体管M6、第三晶体管M3以及第八晶体管M8导通。导通的第六晶体管M6可以将第二参考信号端VR2的低电平信号提供给第二节点N2，以使第二节点N2的信号为低电平信号，从而可以控制第七晶体管M7截止。导通的第三晶体管M3可以将信号gck的高电平信号提供给级联输出端GT，以使级联输出端GT输出的信号gt为高电平信号。导通的第八晶体管M8可以将信号gck的高电平信号提供给驱动输出端ST，以使驱动输出端ST输出的信号st为高电平信号。由于驱动输出端ST输出高电平信号，第一电容C1为了保持其两端电压差，使第一节点N1的高电平进一步被拉高，从而可以使第三晶体管M3以及第八晶体管M8尽可能的完全导通。这样可以使第三晶体管M3将信号gck的高电平信号尽可能无电压损失的提供给级联输出端GT，以使级联输出端GT输出的信号gt尽可能的保持电压稳定。以及使第八晶体管M8将信号gck的高电平信号尽可能无电压损失的提供给驱动输出端ST，以使驱动输出端ST输出的信号st尽可能的保持电压稳定。
在T3阶段，信号inp1为低电平信号，可以控制第一晶体管M1截止。以及信号rst为低电平信号，可以控制第二晶体管M2截止。由于第一电容C1的作用，可以使第一节点N1的信号保持为高电平信号，从而可以控制第六晶体管M6、第三晶体管M3以及第八晶体管M8导通。导通的第六晶体管M6可以将第二参考信号端VR2的低电平信号提供给第二节点N2，以使第二节点N2的信号为低电平信号，从而可以控制第七晶体管M7截止。导通的第三晶体管M3可以将信号gck的低电平信号提供给级联输出端GT，以使级联输出端GT输出的信号gt为低电平信号。导通的第八晶体管M8可以将信号gck的低电平信号提供给驱动输出端ST，以使驱动输出端ST输出的信号st为低电平信号。
之后，信号inp1为低电平信号，可以控制第一晶体管M1截止。并且，信号rst为高电平信号，可以控制第二晶体管M2导通，以将第一参考信号端VR1的低电平信号提供给第一节点N1，可以使第一节点N1的信号为低电平信号，从而可以控制第六晶体管M6、第三晶体管M3以及第八晶体管M8截 止。由于第四晶体管M4的作用，第三参考信号端VR3的高电平信号可以通过导通的第五晶体管M5输入到第二节点N2，以使第二节点N2的信号为高电平信号，从而可以控制第七晶体管M7导通，从而将第二参考信号端VR2的信号提供给第一节点N1，进一步保证第一节点N1的信号为低电平信号。级联输出端GT输出的信号gt保持为低电平信号，以及驱动输出端ST输出的信号st保持为低电平信号。
通过上述实施例可知，本公开实施例中，由于向栅线输入的信号st是由第八晶体管M8控制输出的，将移位寄存器单元进行级联的信号gt是由第三晶体管M3控制输出的。在实际中，可以将第八晶体管M8的尺寸制备的远大于第三晶体管M3的尺寸，可以使信号st的带载能力远大于信号gt的带载能力，因此可以提高信号st的稳定性。示例性地，第八晶体管M8的尺寸SM8与第三晶体管M3的尺寸SM3之间的比例SM8/SM3为5～16。例如，可以使SM8/SM3＝5，也可以使SM8/SM3＝7，也可以使SM8/SM3＝10，也可以使SM8/SM3＝12，也可以使SM8/SM3＝16，在此不作限定。
并且，由于第一晶体管M1的栅极和第一极的信号分离，第一晶体管M1的栅极连接的第一信号端可以接级联中移位寄存器单元的级联输出端GT，第二信号端可以接级联中移位寄存器单元的驱动输出端ST。由于第八晶体管M8的尺寸制备的远大于第三晶体管M3的尺寸，可以使信号st的带载能力远大于信号gt的带载能力。这样在T1阶段中，第一晶体管M1导通时，将信号st的高电平信号输入第一节点N1，可以大大提升第一节点N1的电平的抬升能力。在T3阶段中，第一晶体管M1截止时，第一节点N1的电压为第一参考信号端VR1的电压vr1，第一晶体管M1的栅极电压为第一信号端的低电平信号的电压，即第一晶体管M1的栅极电压为时钟信号端GCK的低电平信号的电压vc1。由于，vc1＝vr2，且vr2<vr1，则vc1<vr1。此时第一晶体管M1的栅源电压Vgs1＝vc1-vr1，即Vgs1<0，从而可以使第一晶体管M1的漏电相对更低，进而起到降低第一节点N1经第一晶体管M1这一路径的漏电作用。
并且，第二晶体管M2的栅极连接的复位信号端RST可以接级联中移位 寄存器单元的级联输出端GT，第二晶体管M2的第一极可以接第一参考信号端VR1。由于第八晶体管M8的尺寸制备的远大于第三晶体管M3的尺寸，可以使信号st的带载能力远大于信号gt的带载能力。这样在T1和T2阶段中，第二晶体管M2截止时，第二晶体管M2的栅极的电压为复位信号端RST的低电平信号的电压，即第二晶体管M2的栅极电压为时钟信号端GCK的低电平信号的电压vc1。由于，vc1＝vr2，且vr2<vr1，则vc1<vr1。此时第二晶体管M2的栅源电压Vgs2＝vc1-vr1，即Vgs2<0，从而可以使第二晶体管M2的漏电相对更低，进而起到降低第一节点N1经第二晶体管M2这一路径的漏电作用。示例性地，vc1-vr1的范围为-3～-1。例如，可以使vc1-vr1＝-3，也可以使vc1-vr1＝-2，也可以使vc1-vr1＝-1，在此不作限定。
本公开实施例提供了另一些移位寄存器单元的结构示意图，如图4a与图4b所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
示例性地，如图4a所示，本公开实施例中的移位寄存器单元还可以包括：第十一晶体管M11；其中，第十一晶体管M11的栅极与第二节点N2电连接，第十一晶体管M11的第一极与第五参考信号端VR5电连接，第十一晶体管M11的第二极与第一节点N1电连接。
本公开实施例中，可以使第五参考信号端VR5与第一参考信号端VR1为同一信号端。示例性地，如图4b所示，第十一晶体管M11的第一极与第一参考信号端VR1电连接。
本公开实施例中，可以使第二参考信号端VR2的电压vr2小于第一参考信号端VR1的电压vr1。
示例性地，图4a与图4b所示的移位寄存器单元对应的信号时序图可以如图3所示。其中，在T1和T2阶段中，第十一晶体管M11受第二节点N2的低电平信号的控制下处于截止状态。在T3阶段中，第十一晶体管M11受第二节点N2的高电平信号的控制下处于导通状态，可以将第五参考信号端VR5的信号进一步提供给第一节点N1，从而可以进一步使第一节点N1的信 号稳定为低电平信号，进一步提高第一节点N1的信号稳定性。并且，各阶段中，其余晶体管的工作过程可以与上述实施例中的工作过程基本相同，在此不作赘述。
通过上述实施例可知，本公开实施例中，由于向栅线输入的信号st是由第八晶体管M8控制输出的，将移位寄存器单元进行级联的信号gt是由第三晶体管M3控制输出的。在实际中，可以将第八晶体管M8的尺寸制备的远大于第三晶体管M3的尺寸，可以使信号st的带载能力远大于信号gt的带载能力，因此可以提高信号st的稳定性。
并且，由于第一晶体管M1的栅极和第一极的信号分离，第一晶体管M1的栅极连接的第一信号端可以接级联中移位寄存器单元的级联输出端GT，第二信号端可以接级联中移位寄存器单元的驱动输出端ST。由于第八晶体管M8的尺寸制备的远大于第三晶体管M3的尺寸，可以使信号st的带载能力远大于信号gt的带载能力。这样在T1阶段中，第一晶体管M1导通时，将信号st的高电平信号输入第一节点N1，可以大大提升第一节点N1的电平的抬升能力。在T3阶段中，第一晶体管M1截止时，第一节点N1的电压为第一参考信号端VR1的电压vr1，第一晶体管M1的栅极电压为第一信号端的低电平信号的电压，即第一晶体管M1的栅极电压为时钟信号端GCK的低电平信号的电压vc1。第一晶体管M1的源极电压为第一节点N1的电压vr1。由于，vc1＝vr2，且vr2<vr1，则vc1<vr1。此时第一晶体管M1的栅源电压Vgs1＝vc1-vr1，即Vgs1<0，从而可以使第一晶体管M1的漏电相对更低，进而起到降低第一节点N1经第一晶体管M1这一路径的漏电作用。
并且，第二晶体管M2的栅极连接的复位信号端RST可以接级联中移位寄存器单元的级联输出端GT，第二晶体管M2的第一极可以接第一参考信号端VR1。由于第八晶体管M8的尺寸制备的远大于第三晶体管M3的尺寸，可以使信号st的带载能力远大于信号gt的带载能力。这样在T1和T2阶段中，第二晶体管M2截止时，第二晶体管M2的栅极的电压为复位信号端RST的低电平信号的电压，即第二晶体管M2的栅极电压为时钟信号端GCK的低电 平信号的电压vc1。第二晶体管M2的源极电压为vr1。由于，vc1＝vr2，且vr2<vr1，则vc1<vr1。此时第二晶体管M2的栅源电压Vgs2＝vc1-vr1，即Vgs2<0，从而可以使第二晶体管M2的漏电相对更低，进而起到降低第一节点N1经第二晶体管M2这一路径的漏电作用。
本公开实施例提供了又一些移位寄存器单元的结构示意图，如图5所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，如图5所示，移位寄存器单元还可以包括：级联降噪单元60；其中，级联降噪单元60被配置为响应于级联输出端GT的信号，将第二参考信号端VR2的信号提供给复位信号端RST。
在本公开实施例中，如图5所示，级联降噪单元60可以包括：第十二晶体管M12；其中，第十二晶体管M12的栅极与级联输出端GT电连接，第十二晶体管M12的第一极与第二参考信号端VR2电连接，第十二晶体管M12的第二极与复位信号端RST电连接。
在本公开实施例中，可以使第二参考信号端VR2和第一参考信号端VR1为同一信号端。示例性地，如图5所示，第六晶体管M6的第一极、第七晶体管M7的第一极以及第二晶体管M2的第一极均与第一参考信号端VR1电连接。
示例性地，时钟信号端GCK的信号可以为高电平信号和低电平信号交替出现的时钟信号。其中，该时钟信号中的低电平信号的电压vc1可以与第二参考信号端VR2的电压vr2以及第一参考信号端VR1的电压vr1相同。
示例性地，可以使第五参考信号端VR5和第一参考信号端VR1为相互独立的信号端，且第五参考信号端VR5的电压小于第一参考信号端VR1的电压，或第五参考信号端VR5的电压大于第一参考信号端VR1的电压。
示例性地，可以使第一输入信号端INP1和第二输入信号端INP2设置为相互独立的信号端。也就是说，第一输入信号端INP1和第二输入信号端INP2并不会电连接到同一个端口或同一条信号线。示例性地，如图3所示，也可 以使第一输入信号端INP1输入的信号和第二输入信号端INP2输入的信号的时序相同。例如，在第一输入信号端INP1输入的信号为高电平时，第二输入信号端INP2输入的信号也为高电平。在第一输入信号端INP1输入的信号为低电平时，第二输入信号端INP2输入的信号也为低电平。
示例性地，图5所示的移位寄存器单元对应的信号时序图可以如图3所示。其中，在T1和T3阶段中，第十二晶体管M12受级联输出端GT的低电平信号的控制处于截止状态。在T2阶段中，第十二晶体管M12受级联输出端GT的高电平信号的控制处于导通状态，可以将第二参考信号端VR2的信号提供给复位信号端RST，从而使复位信号端RST输入低电平信号，以控制第二晶体管M2进一步为截止状态。并且，各阶段中，其余晶体管的工作过程可以与上述实施例中的工作过程基本相同，在此不作赘述。
通过上述实施例可知，本公开实施例中，通过第十二晶体管M12给第二晶体管M2的栅极输入信号，从而可以使第二晶体管M2的漏电流降低，从而降低第一节点的漏电，提高第一节点的电压稳定性。
本公开实施例提供了又一些移位寄存器单元的结构示意图，如图6所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
示例性地，可以使第一输入信号端INP1和第二输入信号端INP2为同一信号端。示例性地，如图6所示，第一晶体管M1的栅极及其第一极均与第一输入信号端INP1电连接。
示例性地，图6所示的移位寄存器单元对应的信号时序图可以如图7所示。其中，在T1阶段中，第一晶体管M1导通，将信号inp1的高电平信号提供给第一节点N1。并且，第十二晶体管M12受级联输出端GT的低电平信号的控制处于截止状态。在T2阶段中，第一晶体管M1截止。并且，第十二晶体管M12受级联输出端GT的高电平信号的控制处于导通状态，可以将第二参考信号端VR2的信号提供给复位信号端RST，从而使复位信号端RST输入低电平信号，以控制第二晶体管M2进一步为截止状态。在T3阶段中，第一 晶体管M1截止。并且，第十二晶体管M12受级联输出端GT的低电平信号的控制处于截止状态。以及，各阶段中，其余晶体管的工作过程可以与上述实施例中的工作过程基本相同，在此不作赘述。
本公开实施例提供了又一些移位寄存器单元的结构示意图，如图8a与图8b所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，可以使第一输入信号端INP1和第二输入信号端INP2为相互独立的信号端。示例性地，如图8a所示，第一晶体管M1的栅极与第一输入信号端INP1电连接，第一晶体管M1的第一极与第二输入信号端INP2电连接。
在本公开实施例中，可以使第一输入信号端INP1和第二输入信号端INP2为同一信号端。示例性地，如图8b所示，第一晶体管M1的栅极及其第一极均与第一输入信号端INP1电连接。
在本公开实施例中，可以使第五参考信号端VR5和第一参考信号端VR1为同一信号端。示例性地，如图8a与图8b所示，第十一晶体管M11的第一极与第二晶体管M2的第一极均与第一参考信号端VR1电连接。
在本公开实施例中，可以使第一参考信号端VR1的信号的电压大于第二参考信号端VR2的信号的电压。以及，该时钟信号中的低电平信号的电压vc1可以与第二参考信号端VR2的电压vr2相同。
示例性地，图8a所示的移位寄存器单元对应的信号时序图可以如图3所示。其中，各阶段中，各晶体管的工作过程可以与上述实施例中的工作过程基本相同，在此不作赘述。
示例性地，图8b所示的移位寄存器单元对应的信号时序图可以如图7所示。其中，各阶段中，各晶体管的工作过程可以与上述实施例中的工作过程基本相同，在此不作赘述。
本公开实施例提供了又一些移位寄存器单元的结构示意图，如图9a与图9b所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例 与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，驱动输出电路50还被配置为响应于第二节点N2的信号，将第四参考信号端VR4的信号提供给驱动输出端ST。示例性地，如图9a与图9b所示，驱动输出电路50可以包括：第九晶体管M9和第十晶体管M10以及第二电容C2；其中，第九晶体管M9的栅极与第一节点N1电连接，第九晶体管M9的第一极与时钟信号端GCK电连接，第九晶体管M9的第二极与驱动输出端ST电连接。第十晶体管M10的栅极与第二节点N2电连接，第十晶体管M10的第一极与第四参考信号端VR4电连接，第十晶体管M10的第二极与驱动输出端ST电连接。以及，所述第二电容C2的第一电极板与所述第一节点N1电连接，所述第二电容C2的第二电极板与所述驱动输出端ST电连接。
在本公开实施例中，可以使该时钟信号中的低电平信号的电压vc1可以与第二参考信号端VR2的电压vr2相同。
在本公开实施例中，可以使第一参考信号端VR1的电压vr1与第二参考信号端VR2的电压vr2相同。
在本公开实施例中，可以使第一输入信号端INP1与第二输入信号端INP2为相互独立的信号端。
在本公开实施例中，可以使第一参考信号端VR1和第二参考信号端VR2为同一信号端。以及使第一参考信号端VR1和第四参考信号端VR4为相互独立的信号端，且第一参考信号端VR1的电压小于第四参考信号端VR4的电压。例如，如图9b所示，可以使第一晶体管M1的第一极与第六晶体管M6的第一极以及第七晶体管M7的第一极均与第一参考信号端VR1电连接。
示例性地，图9a与图9b所示的移位寄存器单元对应的信号时序图可以如图3所示。其中，各阶段中，各晶体管的工作过程可以与上述实施例中的工作过程基本相同，在此不作赘述。
本公开实施例提供了又一些移位寄存器单元的结构示意图，如图10a与图10b所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实 施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，可以使第一输入信号端INP1与第二输入信号端INP2为同一信号端。例如，如图10a与图10b所示，第一晶体管M1的栅极及其第一极均与第一输入信号端INP1电连接。
在本公开实施例中，可以使该时钟信号中的低电平信号的电压vc1可以与第二参考信号端VR2的电压vr2相同。
在本公开实施例中，可以使第二参考信号端VR2和第一参考信号端VR1为相互独立的信号端，并可以使第一参考信号端VR1的电压vr1小于第二参考信号端VR2的电压vr2。
在本公开实施例中，可以使第一参考信号端VR1的电压与第四参考信号端VR4的电压相同。进一步地，可以使第一参考信号端VR1和第四参考信号端VR4为同一信号端。例如，如图10b所示，第二晶体管M2的第一极与第十晶体管M10的第一极均与第一参考信号端VR1电连接。
示例性地，图10a与图10b所示的移位寄存器单元对应的信号时序图可以如图7所示。其中，各阶段中，各晶体管的工作过程可以与上述实施例中的工作过程基本相同，在此不作赘述。
需要说明的是，上述信号的具体电压值可以根据实际应用的需求进行设计确定，在此不作限定。
本公开实施例提供了又一些移位寄存器单元的结构示意图，如图11所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图11所示，所述节点控制电路30还被配置为调节第二节点的信号的电平。第二节点N2可以包括：M个第二子节点；节点控制电路30可以包括：M个子控制电路；其中，M个子控制电路中的第m个子控制电路对应M个第二子节点中的第m个第二子节点；M为整数且M≥1，m为整数且1≤m≤M；其中，第m个子控制电路被配置为调整第m个第二子节点和第一节点N1的信号。所述级联输出电路40还被配置为 响应于M个第二子节点的信号，将第二参考信号端VR2的信号提供给级联输出端GT。所述驱动输出电路50还被配置为根据M个第二子节点的信号，将第四参考信号端VR4的信号提供给级联输出端ST。
示例性地，如图11所示，可以使M＝2，则第二节点N2可以包括：第1个第二子节点N2-1和第2个第二子节点N2-2。节点控制电路30可以包括：与第1个第二子节点N2-1一一对应的第1个子控制电路30-1，与第2个第二子节点N2-2一一对应的第2个子控制电路30-2；其中，第1个子控制电路30-1被配置为调整第1个第二子节点N2-1和第一节点N1的信号。第2个子控制电路30-2被配置为调整第2个第二子节点N2-2和第一节点N1的信号。级联输出电路40被配置为根据第一节点N1、第1个第二子节点N2-1以及第2个第二子节点N2-2的信号，使级联输出端GT输出信号。驱动输出电路50被配置为根据第一节点N1、第1个第二子节点N2-1以及第2个第二子节点N2-2的信号，使驱动输出端ST输出信号。在具体实施时，还可以使M＝3，M＝4，M＝5等，这可以根据实际应用环境来设计M的具体数值，在此不作限定。下面以M＝2为例进行说明。
在具体实施时，在本公开实施例中，如图11所示，第1个子控制电路30-1对应第1个第三参考信号端VR3-1。第1个子控制电路30-1可以包括：第1个第十三晶体管M13-1、第1个第十四晶体管M14-1、第1个第十五晶体管M15-1、第1个第十六晶体管M16-1以及第1个第十七晶体管M17-1；
第1个第十三晶体管M13-1的栅极与第一极均与第1个第三参考信号端VR3-1电连接，第1个第十三晶体管M13-1的第二极与第1个第十四晶体管M14-1的栅极电连接；
第1个第十四晶体管M14-1的第一极与第1个第三参考信号端VR3-1电连接，第1个第十四晶体管M14-1的第二极与第1个第二子节点N2-1电连接；
第1个第十五晶体管M15-1的栅极与第一节点N1电连接，第1个第十五晶体管M15-1的第一极与第二参考信号端VR2电连接，第1个第十五晶体管M15-1的第二极与第1个第二子节点N2-1电连接；
第1个第十六晶体管M16-1的栅极与第一节点N1电连接，第1个第十六晶体管M16-1的第一极与第二参考信号端VR2电连接，第1个第十六晶体管M16-1的第二极与第1个第十四晶体管M14-1的栅极电连接；
第1个第十七晶体管M17-1的栅极与第1个第二子节点N2-1电连接，第1个第十七晶体管M17-1的第一极与第二参考信号端VR2电连接，第1个第十七晶体管M17-1的第二极与第一节点N1电连接。
在具体实施时，在本公开实施例中，如图11所示，第2个子控制电路30-2对应第2个第三参考信号端VR3-2。第2个子控制电路30-2可以包括：第2个第十三晶体管M13-2、第2个第十四晶体管M14-2、第2个第十五晶体管M15-2、第2个第十六晶体管M16-2以及第2个第十七晶体管M17-2；
第2个第十三晶体管M13-2的栅极与第一极均与第2个第三参考信号端VR3-2电连接，第2个第十三晶体管M13-2的第二极与第2个第十四晶体管M14-2的栅极电连接；
第2个第十四晶体管M14-2的第一极与第2个第三参考信号端VR3-2电连接，第2个第十四晶体管M14-2的第二极与第2个第二子节点N2-2电连接；
第2个第十五晶体管M15-2的栅极与第一节点N1电连接，第2个第十五晶体管M15-2的第一极与第二参考信号端VR2电连接，第2个第十五晶体管M15-2的第二极与第2个第二子节点N2-2电连接；
第2个第十六晶体管M16-2的栅极与第一节点N1电连接，第2个第十六晶体管M16-2的第一极与第二参考信号端VR2电连接，第2个第十六晶体管M16-2的第二极与第2个第十四晶体管M14-2的栅极电连接；
第2个第十七晶体管M17-2的栅极与第2个第二子节点N2-2电连接，第2个第十七晶体管M17-2的第一极与第二参考信号端VR2电连接，第2个第十七晶体管M17-2的第二极与第一节点N1电连接。
在具体实施时，在本公开实施例中，如图11所示，级联输出电路40可以包括：第十八晶体管M18、第1个第十九晶体管M19-1以及第2个第十九晶体管M19-2；
第十八晶体管M18的栅极与第一节点N1电连接，第十八晶体管M18的第一极与时钟信号端GLK电连接，第十八晶体管M18的第二极与级联输出端GT电连接；
第1个第十九晶体管M19-1的栅极与第1个第二子节点N2-1电连接，第1个第十九晶体管M19-1的第一极与第二参考信号端VR2电连接，第1个第十九晶体管M19-1的第二极与级联输出端GT电连接；
第2个第十九晶体管M19-2的栅极与第2个第二子节点N2-2电连接，第2个第十九晶体管M19-2的第一极与第二参考信号端VR2电连接，第2个第十九晶体管M19-2的第二极与级联输出端GT电连接。
在具体实施时，在本公开实施例中，第十九晶体管M19-1的尺寸范围可以为200μm～800μm。示例性地，第十九晶体管M19-1的尺寸可以设置为200μm。或者，第十九晶体管M19-1的尺寸也可以设置为400μm。或者，第十九晶体管M19-1的尺寸也可以设置为600μm。或者，第十九晶体管M19-1的尺寸也可以设置为800μm。
在具体实施时，在本公开实施例中，第十九晶体管M19-2的尺寸范围可以为200μm～800μm。示例性地，第十九晶体管M19-2的尺寸可以设置为200μm。或者，第十九晶体管M19-2的尺寸也可以设置为400μm。或者，第十九晶体管M19-2的尺寸也可以设置为600μm。或者，第十九晶体管M19-2的尺寸也可以设置为800μm。
在具体实施时，在本公开实施例中，可以使第十九晶体管M19-1和第十九晶体管M19-2的尺寸设置为相同，这样可以统一设计第十九晶体管M19-和第十九晶体管M19-2。
在具体实施时，在本公开实施例中，如图11所示，驱动输出电路50可以包括：第二十晶体管M20、第三电容C3、第1个第二十一晶体管M21-1以及第2个第二十一晶体管M21-2；
第二十晶体管M20的栅极与第一节点N1电连接，第二十晶体管M20的第一极与时钟信号端GLK电连接，第二十晶体管M20的第二极与驱动输出 端ST电连接；
第三电容C3的第一极与第一节点N1电连接，第三电容C3的第二极与驱动输出端ST电连接；
第1个第二十一晶体管M21-1的栅极与第1个第二子节点N2-1电连接，第1个第二十一晶体管M21-1的第一极与第四参考信号端VR4电连接，第1个第二十一晶体管M21-1的第二极与驱动输出端ST电连接；
第2个第二十一晶体管M21-2的栅极与第2个第二子节点N2-2电连接，第2个第二十一晶体管M21-2的第一极与第四参考信号端VR4电连接，第2个第二十一晶体管M21-2的第二极与驱动输出端ST电连接。
在具体实施时，在本公开实施例中，如图11所示，所述移位寄存器单元还可以包括2个第二十二晶体管：第1个第二十二晶体管M22-1和第2个第二十二晶体管M22-2；其中，第1个第二十二晶体管M22-1和第2个第二十二晶体管M22-2的栅极均与所述第一输入信号端INP1电连接，第1个第二十二晶体管M22-1和第2个第二十二晶体管M22-2的第一极均与所述第二参考信号端VR2电连接。第1个第二十二晶体管M22-1的第二极与第1个第二子节点N2-1电连接，第2个第二十二晶体管M22-2的第二极与第2个第二子节点N2-2电连接。
在具体实施时，在本公开实施例中，如图11所示，所述移位寄存器单元还可以包括第二十三晶体管M23；所述第二十三晶体管M23的栅极与初始复位信号端CRE电连接，所述第二十三晶体管M23的第一极与所述第二参考信号端VR2电连接，所述第二十三晶体管M23与所述第一节点N2电连接。
以上仅是举例说明本公开实施例提供的移位寄存器单元的具体结构，在具体实施时，上述各电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
为了降低制备工艺，在具体实施时，在本公开实施例提供的移位寄存器单元中，如图11所示，所有晶体管均可以为N型晶体管。并且，第一参考信号端VR1的信号可以为低电平信号，第二参考信号端VR2的信号也可以为低 电平信号，第四参考信号端VR4的信号也可以为低电平信号。其中，可以使第一参考信号端VR1的信号的电压与第二参考信号端VR2的信号的电压相同，这样可以采用同一信号端对第一参考信号端VR1和第二参考信号端VR2输入电压，从而降低信号端的数量，降低布线难度。或者，也可以使第二参考信号端VR2和第一参考信号端VR1设置为相互独立的信号端，并使第二参考信号端VR2的电压小于第一参考信号端VR1的电压。这样可以使显示面板的显示区中像素内的TFT可以尽可能完全关断。当然，在具体实施时，所有晶体管也均可以为P型晶体管，在此不作限定。
示例性地，第一参考信号端VR1的信号的电压与第四参考信号端VR4为同一信号端，这样可以采用同一信号端对第一参考信号端VR1和第二参考信号端VR2输入电压，从而降低信号端的数量，降低布线难度。
在具体实施时，第1个第三参考信号端VR3-1的信号和第2个第三参考信号端VR3-2的信号可以分别为高电平和低电平切换的脉冲信号，并且，第1个第三参考信号端VR3-1的电平和第2个第三参考信号端VR3-2的电平相反。例如，如图12所示，在T10阶段中，第1个第三参考信号端VR3-1为高电平信号，第2个第三参考信号端VR3-2为低电平信号。在T20阶段中，第1个第三参考信号端VR3-1为低电平信号，第2个第三参考信号端VR3-2为高电平信号。或者，第1个第三参考信号端VR3-1的信号和第2个第三参考信号端VR3-2的信号也可以分别为直流信号。并且，在第1个第三参考信号端VR3-1加载高电平的直流信号时，第2个第三参考信号端VR3-2不加载信号或加载低电平的直流信号。在第2个第三参考信号端VR3-2加载高电平的直流信号时，在第1个第三参考信号端VR3-1不加载信号或加载低电平的直流信号。例如，如图12所示，在T10阶段中，第1个第三参考信号端VR3-1为高电平的直流信号，第2个第三参考信号端VR3-2为低电平的直流信号。在T20阶段中，第1个第三参考信号端VR3-1为低电平的直流信号，第2个第三参考信号端VR3-2为高电平的直流信号。
示例性地，T10阶段和T20阶段可以根据实际应用来确定先后顺序。例 如，可以先执行T10阶段中的工作过程，之后再执行T20阶段中的工作过程。或者，也可以先执行T20阶段中的工作过程，之后再执行T10阶段中的工作过程。
示例性地，可以使T10阶段的维持时长与T20阶段的维持时长相同。例如将T10阶段的维持时长与T20阶段的维持时长分别设置为1个显示帧的时长、多个显示帧的时长、2s、1h或24h等，在此不作限定。
下面以图11所示的移位寄存器单元的结构为例，结合图12所示的信号时序图，对本公开实施例提供的上述移位寄存器单元的工作过程作以详细的描述。其中，选取图12所示的信号时序图中的T10阶段和T20阶段。并且，选取T10阶段中的T11阶段、T12阶段、T13阶段。以及选取T20阶段中的T21阶段、T22阶段、T23阶段。vr3-1代表第1个第三参考信号端VR3-1的信号，vr3-2代表第2个第三参考信号端VR3-2的信号。
在T10阶段中，由于第2个第三参考信号端VR3-2为低电平信号，因此第2个第十三晶体管M13-2截止。
在T11阶段，信号rst为低电平，因此第二晶体管M2截止。信号inp1为高电平信号，可以控制第一晶体管M1、第1个第二十二晶体管M22-1以及第2个第二十二晶体管M22-2均导通。导通的第一晶体管M1将信号inp2的高电平信号提供给第一节点N1，使第一节点N1为高电平信号，从而控制第1个第十五晶体管M15-1、第1个第十六晶体管M16-1、第2个第十五晶体管M15-2、第2个第十六晶体管M16-2、第十八晶体管M18以及第二十晶体管M20均导通。导通的第1个第十六晶体管M16-1可以将第二参考信号端VR2的低电平信号提供给第1个第十四晶体管M14-1的栅极，以控制第1个第十四晶体管M14-1截止。导通的第1个第十五晶体管M15-1可以将第二参考信号端VR2的低电平信号提供给第1个第二子节点N2-1，以使第1个第二子节点N2-1为低电平信号，从而控制第1个第十七晶体管M17-1、第1个第十九晶体管M19-1以及第1个第二十一晶体管M21-1均截止。并且，导通的第1个第二十二晶体管M22-1将第二参考信号端VR2的低电平信号提供给第1个 第二子节点N2-1，进一步使第1个第二子节点N2-1为低电平信号。
以及，导通的第2个第十六晶体管M16-2可以将第二参考信号端VR2的低电平信号提供给第2个第十四晶体管M14-2的栅极，以控制第2个第十四晶体管M14-2截止。导通的第2个第十五晶体管M15-2可以将第二参考信号端VR2的低电平信号提供给第2个第二子节点N2-2，以使第2个第二子节点N2-2为低电平信号，从而控制第2个第十七晶体管M17-2、第2个第十九晶体管M19-2以及第2个第二十一晶体管M21-2均截止。并且，导通的第2个第二十二晶体管M22-2将第二参考信号端VR2的低电平信号提供给第2个第二子节点N2-2，进一步使第2个第二子节点N2-2为低电平信号。
以及，导通的第十八晶体管M18可以将时钟信号端CLK的低电平信号提供给级联输出端GT，以使级联输出端GT输出低电平信号。导通的第二十晶体管M20可以将时钟信号端CLK的低电平信号提供给驱动输出端ST，以使驱动输出端ST输出低电平信号。
在T12阶段，信号rst为低电平，因此第二晶体管M2截止。信号inp1为低电平信号，可以控制第一晶体管M1、第1个第二十二晶体管M22-1以及第2个第二十二晶体管M22-2均截止。由于第三电容C3的作用，可以使第一节点N1保持为高电平信号。由于第一节点N1为高电平信号，从而控制第1个第十五晶体管M15-1、第1个第十六晶体管M16-1、第2个第十五晶体管M15-2、第2个第十六晶体管M16-2、第十八晶体管M18以及第二十晶体管M20均导通。导通的第1个第十六晶体管M16-1可以将第二参考信号端VR2的低电平信号提供给第1个第十四晶体管M14-1的栅极，以控制第1个第十四晶体管M14-1截止。导通的第1个第十五晶体管M15-1可以将第二参考信号端VR2的低电平信号提供给第1个第二子节点N2-1，以使第1个第二子节点N2-1为低电平信号，从而控制第1个第十七晶体管M17-1、第1个第十九晶体管M19-1以及第1个第二十一晶体管M21-1均截止。
以及，导通的第2个第十六晶体管M16-2可以将第二参考信号端VR2的低电平信号提供给第2个第十四晶体管M14-2的栅极，以控制第2个第十四 晶体管M14-2截止。导通的第2个第十五晶体管M15-2可以将第二参考信号端VR2的低电平信号提供给第2个第二子节点N2-2，以使第2个第二子节点N2-2为低电平信号，从而控制第2个第十七晶体管M17-2、第2个第十九晶体管M19-2以及第2个第二十一晶体管M21-2均截止。
导通的第十八晶体管M18可以将时钟信号端GLK的高电平信号提供给级联输出端GT，以使级联输出端GT输出高电平信号。导通的第二十晶体管M20可以将时钟信号端GLK的高电平信号提供给驱动输出端ST。由于第一节点N1浮接，因此第一节点N1被进一步拉高，从而使第二十晶体管M20可以尽可能完全导通，以使时钟信号端GLK的高电平信号可以尽可能无电压损失的提供给驱动输出端ST，以使驱动输出端ST输出高电平信号。
在T13阶段，信号inp1为低电平信号，可以控制第一晶体管M1、第1个第二十二晶体管M22-1以及第2个第二十二晶体管M22-2均截止。信号rst为高电平，因此第二晶体管M2导通，将第一参考信号端VR1的低电平信号提供给第一节点N1，以使第一节点N1为低电平信号，从而控制第1个第十五晶体管M15-1、第1个第十六晶体管M16-1、第2个第十五晶体管M15-2、第2个第十六晶体管M16-2、第十八晶体管M18以及第二十晶体管M20均截止。并且，第2个第二子节点N2-2保持为低电平信号，从而控制第2个第十七晶体管M17-2、第2个第十九晶体管M19-2以及第2个第二十一晶体管M21-2均截止。
第1个第十三晶体管M13-1在第1个第三参考信号端VR3-1的高电平信号的控制下导通，以将第1个第三参考信号端VR3-1的高电平信号提供给第1个第十四晶体管M14-1的栅极，从而控制第1个第十四晶体管M14-1导通。导通的第1个第十四晶体管M14-1可以将第1个第三参考信号端VR3-1的高电平信号提供给第1个第二子节点N2-1，以使第1个第二子节点N2-1为高电平信号，从而控制第1个第十七晶体管M17-1、第1个第十九晶体管M19-1以及第1个第二十一晶体管M21-1均导通。导通的第1个第十七晶体管M17-1可以将第二参考信号端VR2的低电平信号提供给第一节点N1，以使第一节点 N1进一步为低电平信号。导通的第1个第十九晶体管M19-1可以将第二参考信号端VR2的低电平信号提供给级联输出端GT，以使级联输出端GT输出低电平信号。导通的第1个第二十一晶体管M21-1可以将第四参考信号端VR4的低电平信号提供给驱动输出端ST，以使驱动输出端ST输出低电平信号。
在T20阶段中，由于第1个第三参考信号端VR3-1为低电平信号，因此第1个第十三晶体管M13-1截止。
在T21阶段，信号rst为低电平，因此第二晶体管M2截止。信号inp1为高电平信号，可以控制第一晶体管M1、第1个第二十二晶体管M22-1以及第2个第二十二晶体管M22-2均导通。导通的第一晶体管M1将信号inp2的高电平信号提供给第一节点N1，使第一节点N1为高电平信号，从而控制第1个第十五晶体管M15-1、第1个第十六晶体管M16-1、第2个第十五晶体管M15-2、第2个第十六晶体管M16-2、第十八晶体管M18以及第二十晶体管M20均导通。导通的第1个第十六晶体管M16-1可以将第二参考信号端VR2的低电平信号提供给第1个第十四晶体管M14-1的栅极，以控制第1个第十四晶体管M14-1截止。导通的第1个第十五晶体管M15-1可以将第二参考信号端VR2的低电平信号提供给第1个第二子节点N2-1，以使第1个第二子节点N2-1为低电平信号，从而控制第1个第十七晶体管M17-1、第1个第十九晶体管M19-1以及第1个第二十一晶体管M21-1均截止。并且，导通的第1个第二十二晶体管M22-1将第二参考信号端VR2的低电平信号提供给第1个第二子节点N2-1，进一步使第1个第二子节点N2-1为低电平信号。
以及，导通的第2个第十六晶体管M16-2可以将第二参考信号端VR2的低电平信号提供给第2个第十四晶体管M14-2的栅极，以控制第2个第十四晶体管M14-2截止。导通的第2个第十五晶体管M15-2可以将第二参考信号端VR2的低电平信号提供给第2个第二子节点N2-2，以使第2个第二子节点N2-2为低电平信号，从而控制第2个第十七晶体管M17-2、第2个第十九晶体管M19-2以及第2个第二十一晶体管M21-2均截止。并且，导通的第2个第二十二晶体管M22-2将第二参考信号端VR2的低电平信号提供给第2个第 二子节点N2-2，进一步使第2个第二子节点N2-2为低电平信号。
以及，导通的第十八晶体管M18可以将时钟信号端CLK的低电平信号提供给级联输出端GT，以使级联输出端GT输出低电平信号。导通的第二十晶体管M20可以将时钟信号端CLK的低电平信号提供给驱动输出端ST，以使驱动输出端ST输出低电平信号。
在T22阶段，信号rst为低电平，因此第二晶体管M2截止。信号inp1为低电平信号，可以控制第一晶体管M1、第1个第二十二晶体管M22-1以及第2个第二十二晶体管M22-2均截止。由于第三电容C3的作用，可以使第一节点N1保持为高电平信号。由于第一节点N1为高电平信号，从而控制第1个第十五晶体管M15-1、第1个第十六晶体管M16-1、第2个第十五晶体管M15-2、第2个第十六晶体管M16-2、第十八晶体管M18以及第二十晶体管M20均导通。导通的第1个第十六晶体管M16-1可以将第二参考信号端VR2的低电平信号提供给第1个第十四晶体管M14-1的栅极，以控制第1个第十四晶体管M14-1截止。导通的第1个第十五晶体管M15-1可以将第二参考信号端VR2的低电平信号提供给第1个第二子节点N2-1，以使第1个第二子节点N2-1为低电平信号，从而控制第1个第十七晶体管M17-1、第1个第十九晶体管M19-1以及第1个第二十一晶体管M21-1均截止。导通的第2个第十六晶体管M16-2可以将第二参考信号端VR2的低电平信号提供给第2个第十四晶体管M14-2的栅极，以控制第2个第十四晶体管M14-2截止。导通的第2个第十五晶体管M15-2可以将第二参考信号端VR2的低电平信号提供给第2个第二子节点N2-2，以使第2个第二子节点N2-2为低电平信号，从而控制第2个第十七晶体管M17-2、第2个第十九晶体管M19-2以及第2个第二十一晶体管M21-2均截止。
导通的第十八晶体管M18可以将时钟信号端GLK的高电平信号提供给级联输出端GT，以使级联输出端GT输出高电平信号。导通的第二十晶体管M20可以将时钟信号端GLK的高电平信号提供给驱动输出端ST。由于第一节点N1浮接，因此第一节点N1被进一步拉高，从而使第二十晶体管M20 可以尽可能完全导通，以使时钟信号端GLK的高电平信号可以尽可能无电压损失的提供给驱动输出端ST，以使驱动输出端ST输出高电平信号。
在T23阶段，信号inp1为低电平信号，可以控制第一晶体管M1、第1个第二十二晶体管M22-1以及第2个第二十二晶体管M22-2均截止。信号rst为高电平，因此第二晶体管M2导通，将第一参考信号端VR1的低电平信号提供给第一节点N1，以使第一节点N1为低电平信号，从而控制第1个第十五晶体管M15-1、第1个第十六晶体管M16-1、第2个第十五晶体管M15-2、第2个第十六晶体管M16-2、第十八晶体管M18以及第二十晶体管M20均截止。并且，第1个第二子节点N2-1保持为低电平信号，从而控制第1个第十七晶体管M17-1、第1个第十九晶体管M19-1以及第1个第二十一晶体管M21-1均截止。
第2个第十三晶体管M13-2在第2个第三参考信号端VR3-2的高电平信号的控制下导通，以将第2个第三参考信号端VR3-2的高电平信号提供给第2个第十四晶体管M14-2的栅极，从而控制第2个第十四晶体管M14-2导通。导通的第2个第十四晶体管M14-2可以将第2个第三参考信号端VR3-2的高电平信号提供给第2个第二子节点N2-2，以使第2个第二子节点N2-2为高电平信号，从而控制第2个第十七晶体管M17-2、第2个第十九晶体管M19-2以及第2个第二十一晶体管M21-2均导通。导通的第2个第十七晶体管M17-2可以将第二参考信号端VR2的低电平信号提供给第一节点N1，以使第一节点N1进一步为低电平信号。导通的第2个第十九晶体管M19-2可以将第二参考信号端VR2的低电平信号提供给级联输出端GT，以使级联输出端GT输出低电平信号。导通的第2个第二十一晶体管M21-2可以将第四参考信号端VR4的低电平信号提供给驱动输出端ST，以使驱动输出端ST输出低电平信号。
并且，本公开实施例提供的上述移位寄存器单元，在T10阶段中，第1个子控制电路30-1工作。在T20阶段中，第2个子控制电路30-2工作。从而可以使晶体管的特***替进行恢复，从而可以降低由于晶体管使用造成的特性漂移导致的对输出信号的稳定性和寿命的影响，进而可以增强产品的寿命， 降低生产成本。
在本公开实施例中，也可以使第一输入端和第二输入信号端设置为同一信号端。例如，如图13所示，第一晶体管M1的栅极和第一极均与第一输入端INP1电连接。
本公开实施例还提供的一些栅极驱动电路，包括级联的多个上述移位寄存器单元。在第一输入信号端INP1和第二输入信号端INP2为相互独立的信号端时，第一级移位寄存器单元的第一输入信号端INP1与级联起始信号端GTV电连接。第一级移位寄存器单元的第二输入信号端INP2与帧起始信号端STV电连接。并且，级联起始信号端GTV和帧起始信号端STV的信号相同。以及，级联每相邻的M个移位寄存器单元中，第M个移位寄存器单元的第一输入信号端INP1与第1个移位寄存器单元的级联输出端GT电连接，且第M个移位寄存器单元的第二输入信号端INP2与第1个移位寄存器单元的驱动输出端ST电连接；并且，级联每相邻的M+1个移位寄存器单元中，第1个移位寄存器单元的复位信号端RST与第M+1个移位寄存器单元的级联输出端GT电连接。其中，M为大于1的整数。
示例性地，在第一输入信号端INP1和第二输入信号端INP2为相互独立的信号端时，在级联每相邻的M个移位寄存器单元中，第M个移位寄存器单元的第一输入信号端INP1与第1个移位寄存器单元的级联输出端GT电连接的走线具有第一长度CH1。以及，第M个移位寄存器单元的第二输入信号端INP2与第1个移位寄存器单元的驱动输出端ST电连接的走线具有第二长度CH2。其中，CH1/CH2可以为1.0～1.5。这样可以根据布线空间的面积，分别对第M个移位寄存器单元的第一输入信号端INP1与第1个移位寄存器单元的级联输出端GT电连接的走线以及第M个移位寄存器单元的第二输入信号端INP2与第1个移位寄存器单元的驱动输出端ST电连接的走线，进行合理的布局设计。并且，第二长度CH2小于第一长度CH1，可以降低移位寄存器单元的第二输入信号端INP2的信号的延迟。
示例性地，CH1/CH2可以为1.0，CH1/CH2也可以为1.1，CH1/CH2也 可以为1.2，CH1/CH2也可以为1.3，CH1/CH2也可以为1.4，CH1/CH2也可以为1.5，在此不作限定。
示例性地，以M＝7为例，在第一输入信号端INP1和第二输入信号端INP2为相互独立的信号端时，级联每相邻的7个移位寄存器单元中，第7个移位寄存器单元的第一输入信号端INP1与第1个移位寄存器单元的级联输出端GT电连接，且第7个移位寄存器单元的第二输入信号端INP2与第1个移位寄存器单元的驱动输出端ST电连接；并且，级联每相邻的8个移位寄存器单元中，第1个移位寄存器单元的复位信号端RST与第8个移位寄存器单元的级联输出端GT电连接。
例如，如图14与图15a所示，第一级移位寄存器单元SR1的级联输出端GT与第七级移位寄存器单元SR7的第一输入信号端INP1电连接，即将第一级移位寄存器单元SR1的级联输出端GT的信号st1作为第七级移位寄存器单元SR7的第一输入信号端INP1的信号输入。第二级移位寄存器单元SR2的级联输出端GT与第八级移位寄存器单元SR8的第一输入信号端INP1电连接，即将第二级移位寄存器单元SR2的级联输出端GT的信号st2作为第八级移位寄存器单元SR8的第一输入信号端INP1的信号输入。第三级移位寄存器单元SR3的级联输出端GT与第九级移位寄存器单元SR9的第一输入信号端INP1电连接，即将第三级移位寄存器单元SR3的级联输出端GT的信号st3作为第九级移位寄存器单元SR9的第一输入信号端INP1的信号输入。其余以此类推，在此不作赘述。
例如，如图14与图15a所示，第八级移位寄存器单元SR8的级联输出端GT与第一级移位寄存器单元SR1的复位信号端RST电连接，即将第八级移位寄存器单元SR8的级联输出端GT的信号st8作为第一级移位寄存器单元SR1的复位信号端RST的信号输入。第九级移位寄存器单元SR9的级联输出端GT与第二级移位寄存器单元SR2的复位信号端RST电连接，即将第九级移位寄存器单元SR9的级联输出端GT的信号st9作为第二级移位寄存器单元SR2的复位信号端RST的信号输入。其余以此类推，在此不作赘述。
例如，如图14与图15b所示，第一级移位寄存器单元SR1的驱动输出端ST与第七级移位寄存器单元SR7的第二输入信号端INP2电连接，即将第一级移位寄存器单元SR1的驱动输出端ST的信号gt1作为第七级移位寄存器单元SR7的第二输入信号端INP2的信号输入。第二级移位寄存器单元SR2的驱动输出端ST与第八级移位寄存器单元SR8的第二输入信号端INP2电连接，即将第二级移位寄存器单元SR2的驱动输出端ST的信号gt2作为第八级移位寄存器单元SR8的第二输入信号端INP2的信号输入。第三级移位寄存器单元SR3的驱动输出端ST与第九级移位寄存器单元SR9的第二输入信号端INP2电连接，即将第三级移位寄存器单元SR3的驱动输出端ST的信号gt3作为第九级移位寄存器单元SR9的第二输入信号端INP2的信号输入。其余以此类推，在此不作赘述。
如图14所示的栅极驱动电路，第一级移位寄存器单元至第十四级移位寄存器单元的级联输出端GT输出的信号st1～st14。第一级移位寄存器单元至第十四级移位寄存器单元的驱动输出端ST输出的信号gt1～gt14。
当然，在实际应用中，M还可以设置为其他数值，其可以根据实际应用的需求进行设计确定，在此不作限定。
本公开实施例还提供的另一些栅极驱动电路，包括级联的多个上述移位寄存器单元。在第一输入信号端INP1和第二输入信号端INP2为同一信号端时，第一级移位寄存器单元的第一输入信号端INP1与帧起始信号端STV电连接。级联每相邻的M个移位寄存器单元中，第M个移位寄存器单元的第一输入信号端INP1与第1个移位寄存器单元的级联输出端GT电连接；并且，级联每相邻的M+1个移位寄存器单元中，第1个移位寄存器单元的复位信号端RST与第M+1个移位寄存器单元的级联输出端GT电连接。其中，M为大于1的整数。
示例性地，以M＝7为例，在第一输入信号端INP1和第二输入信号端INP2为同一信号端时，级联每相邻的7个移位寄存器单元中，第7个移位寄存器单元的第一输入信号端INP1与第1个移位寄存器单元的级联输出端GT电连 接；并且，级联每相邻的8个移位寄存器单元中，第1个移位寄存器单元的复位信号端RST与第8个移位寄存器单元的级联输出端GT电连接。
例如，如图16与图15a所示，第一级移位寄存器单元SR1的级联输出端GT与第七级移位寄存器单元SR7的第一输入信号端INP1电连接，即将第一级移位寄存器单元SR1的级联输出端GT的信号st1作为第七级移位寄存器单元SR7的第一输入信号端INP1的信号输入。第二级移位寄存器单元SR2的级联输出端GT与第八级移位寄存器单元SR8的第一输入信号端INP1电连接，即将第二级移位寄存器单元SR2的级联输出端GT的信号st2作为第八级移位寄存器单元SR8的第一输入信号端INP1的信号输入。第三级移位寄存器单元SR3的级联输出端GT与第九级移位寄存器单元SR9的第一输入信号端INP1电连接，即将第三级移位寄存器单元SR3的级联输出端GT的信号st3作为第九级移位寄存器单元SR9的第一输入信号端INP1的信号输入。其余以此类推，在此不作赘述。
例如，如图16与图15a所示，第八级移位寄存器单元SR8的级联输出端GT与第一级移位寄存器单元SR1的复位信号端RST电连接，即将第八级移位寄存器单元SR8的级联输出端GT的信号st8作为第一级移位寄存器单元SR1的复位信号端RST的信号输入。第九级移位寄存器单元SR9的级联输出端GT与第二级移位寄存器单元SR2的复位信号端RST电连接，即将第九级移位寄存器单元SR9的级联输出端GT的信号st9作为第二级移位寄存器单元SR2的复位信号端RST的信号输入。其余以此类推，在此不作赘述。
如图16所示的栅极驱动电路，第一级移位寄存器单元至第十四级移位寄存器单元的级联输出端GT输出的信号st1～st14。第一级移位寄存器单元至第十四级移位寄存器单元的驱动输出端ST输出的信号gt1～gt14。
当然，在实际应用中，M还可以设置为其他数值，其可以根据实际应用的需求进行设计确定，在此不作限定。
并且，在移位寄存器单元还包括第二十三晶体管时，可以使栅极驱动电路中的每一个第二十三晶体管电连接同一帧复位端。这样可以在一帧开始前 可以控制栅极驱动电路中的每一个第二十三晶体管同时导通，以对第一节点进行整体复位。
基于同一公开构思，本公开实施例还提供了一种显示装置，包括多条栅线以及本公开实施例提供的上述栅极驱动电路。该显示装置解决问题的原理与前述栅极驱动电路相似，因此该显示装置的实施可以参见前述栅极驱动电路的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，可以使一条栅线对应栅极驱动电路中的一个移位寄存器单元，这样可以使一条栅线与栅极驱动电路中的一个移位寄存器单元的驱动输出端ST电连接，以使该移位寄存器单元向电连接的栅线输入扫描信号。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的移位寄存器单元、栅极驱动电路及显示装置，通过输入电路响应于第一输入信号端的信号，将第二输入信号端的信号，提供给第一节点。通过复位电路响应于复位信号端的信号，将第一参考信号端的信号，提供给第一节点。通过节点控制电路根据第二参考信号端和第三参考信号端的信号，使第一节点的信号的电平和第二节点的信号的电平相反。通过级联输出电路响应于第一节点的信号，将时钟信号端的信号提供给级联输出端。以及通过驱动输出电路，响应于第一节点的信号，将时钟信号端的信号提供给驱动输出端。这样可以提高驱动输出端的带载能力。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变 型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (24)

  1. 一种移位寄存器单元，其中，包括：
    输入电路，被配置为响应于第一输入信号端的信号，将第二输入信号端的信号，提供给第一节点；
    复位电路，被配置为响应于复位信号端的信号，将第一参考信号端的信号，提供给所述第一节点；
    节点控制电路，被配置为根据第二参考信号端和第三参考信号端的信号，至少调节所述第一节点的信号的电平；
    级联输出电路，被配置为响应于所述第一节点的信号，将时钟信号端的信号提供给级联输出端；
    驱动输出电路，被配置为响应于所述第一节点的信号，将所述时钟信号端的信号提供给驱动输出端。
  2. 如权利要求1所述的移位寄存器单元，其中，所述输入电路包括：第一晶体管；
    所述第一晶体管的栅极与所述第一输入信号端电连接，所述第一晶体管的第一极与所述第二输入信号端电连接，所述第一晶体管的第二极与所述第一节点电连接。
  3. 如权利要求2所述的移位寄存器单元，其中，所述第一输入信号端和所述第二输入信号端为同一信号端；或者，
    所述第一输入信号端和所述第二输入信号端为相互独立的信号端。
  4. 如权利要求1所述的移位寄存器单元，其中，所述复位电路包括：第二晶体管；
    所述第二晶体管的栅极与所述复位信号端电连接，所述第二晶体管的第一极与所述第一参考信号端电连接，所述第二晶体管的第二极与所述第一节点电连接。
  5. 如权利要求1所述的移位寄存器单元，其中，所述级联输出电路包括： 第三晶体管；
    所述第三晶体管的栅极与所述第一节点电连接，所述第三晶体管的第一极与所述时钟信号端电连接，所述第三晶体管的第二极与所述级联输出端电连接。
  6. 如权利要求1所述的移位寄存器单元，其中，所述节点控制电路包括：第四晶体管、第五晶体管、第六晶体管以及第七晶体管；
    所述第四晶体管的栅极及其第一极均与所述第三参考信号端电连接，所述第四晶体管的第二极与所述第五晶体管的栅极电连接；
    所述第五晶体管的第一极与所述第三参考信号端电连接，所述第五晶体管的第二极与所述第二节点电连接；
    所述第六晶体管的栅极与所述第一节点电连接，所述第六晶体管的第一极与所述第二参考信号端电连接，所述第六晶体管的第二极与所述第二节点电连接；
    所述第七晶体管的栅极与所述第二节点电连接，所述第七晶体管的第一极与所述第二参考信号端电连接，所述第七晶体管的第二极与所述第一节点电连接。
  7. 如权利要求6所述的移位寄存器单元，其中，所述第二参考信号端和所述第一参考信号端为同一信号端；或者，
    所述第二参考信号端和所述第一参考信号端为相互独立的信号端，且所述第二参考信号端的电压小于所述第一参考信号端的电压。
  8. 如权利要求1所述的移位寄存器单元，其中，所述驱动输出电路包括：第八晶体管和第一电容；
    所述第八晶体管的栅极与所述第一节点电连接，所述第八晶体管的第一极与所述时钟信号端电连接，所述第八晶体管的第二极与所述驱动输出端电连接；
    所述第一电容的第一电极板与所述第一节点电连接，所述第一电容的第二电极板与所述驱动输出端电连接。
  9. 如权利要求1所述的移位寄存器单元，其中，所述驱动输出电路还被配置为响应于所述第二节点的信号，将第四参考信号端的信号提供给所述驱动输出端。
  10. 如权利要求9所述的移位寄存器单元，其中，所述驱动输出电路包括：第九晶体管和第十晶体管以及第二电容；
    所述第九晶体管的栅极与所述第一节点电连接，所述第九晶体管的第一极与所述时钟信号端电连接，所述第九晶体管的第二极与所述驱动输出端电连接；
    所述第十晶体管的栅极与所述第二节点电连接，所述第十晶体管的第一极与所述第四参考信号端电连接，所述第十晶体管的第二极与所述驱动输出端电连接；
    所述第二电容的第一电极板与所述第一节点电连接，所述第二电容的第二电极板与所述驱动输出端电连接。
  11. 如权利要求9所述的移位寄存器单元，其中，所述第一参考信号端和所述第四参考信号端为同一信号端；或者，
    所述第一参考信号端和所述第四参考信号端为相互独立的信号端，且所述第一参考信号端的电压小于所述第四参考信号端的电压。
  12. 如权利要求1-11任一项所述的移位寄存器单元，其中，所述移位寄存器单元还包括：第十一晶体管；
    所述第十一晶体管的栅极与所述第二节点电连接，所述第十一晶体管的第一极与第五参考信号端电连接，所述第十一晶体管的第二极与所述第一节点电连接。
  13. 如权利要求12所述的移位寄存器单元，其中，所述第五参考信号端和所述第一参考信号端为同一信号端；或者，
    所述第五参考信号端和所述第一参考信号端为相互独立的信号端，且所述第五参考信号端的电压小于所述第一参考信号端的电压。
  14. 如权利要求1-4任一项所述的移位寄存器单元，其中，所述节点控制 电路还被配置为调节第二节点的信号的电平；
    所述第二节点包括：M个第二子节点；所述节点控制电路包括：M个子控制电路；其中，所述M个子控制电路中的第m个子控制电路对应所述M个第二子节点中的第m个第二子节点；M为整数且M≥1，m为整数且1≤m≤M；
    所述第m个子控制电路被配置为调整所述第m个第二子节点和所述第一节点的信号；
    所述级联输出电路还被配置为响应于所述M个第二子节点的信号，将所述第二参考信号端的信号提供给所述级联输出端；
    所述驱动输出电路还被配置为根据所述M个第二子节点的信号，将第四参考信号端的信号提供给所述级联输出端。
  15. 如权利要求14所述的移位寄存器单元，其中，所述第m个子控制电路对应第m个第三参考信号端；
    所述第m个子控制电路包括：第m个第十三晶体管、第m个第十四晶体管、第m个第十五晶体管、第m个第十六晶体管以及第m个第十七晶体管；
    所述第m个第十三晶体管的栅极与第一极均与所述第m个第三参考信号端电连接，所述第m个第十三晶体管的第二极与所述第m个第十四晶体管的栅极电连接；
    所述第m个第十四晶体管的第一极与所述第m个第三参考信号端电连接，所述第m个第十四晶体管的第二极与所述第m个第二子节点电连接；
    所述第m个第十五晶体管的栅极与所述第一节点电连接，所述第m个第十五晶体管的第一极与所述第二参考信号端电连接，所述第m个第十五晶体管的第二极与所述第m个第二子节点电连接；
    所述第m个第十六晶体管的栅极与所述第一节点电连接，所述第m个第十六晶体管的第一极与所述第二参考信号端电连接，所述第m个第十六晶体管的第二极与所述第二晶体管的栅极电连接；
    所述第m个第十七晶体管的栅极与所述第m个第二子节点电连接，所述第m个第十七晶体管的第一极与所述第二参考信号端电连接，所述第m个第 十七晶体管的第二极与所述第一节点电连接。
  16. 如权利要求15所述的移位寄存器单元，其中，所述级联输出电路包括：第十八晶体管以及M个第十九晶体管；其中，所述M个第十九晶体管中的第m个第十九晶体管对应所述第m个第二子节点；
    所述第十八晶体管的栅极与所述第一节点电连接，所述第十八晶体管的第一极与时钟信号端电连接，所述第十八晶体管的第二极与所述级联输出端电连接；
    所述第m个第十九晶体管的栅极与所述第m个第二子节点电连接，所述第m个第十九晶体管的第一极与所述第二参考信号端电连接，所述第m个第十九晶体管的第二极与所述级联输出端电连接。
  17. 如权利要求15所述的移位寄存器单元，其中，所述驱动输出电路包括：第二十晶体管、第三电容以及M个第二十一晶体管；其中，所述M个第二十一晶体管的第m个第二十一晶体管对应所述第m个第二子节点；
    所述第二十晶体管的栅极与所述第一节点电连接，所述第二十晶体管的第一极与时钟信号端电连接，所述第二十晶体管的第二极与所述驱动信号输出端电连接；
    所述第三电容的第一极与所述第一节点电连接，第三电容的第二极与所述驱动信号输出端电连接；
    所述第m个第二十一晶体管的栅极与所述第m个第二子节点电连接，所述第m个第二十一晶体管的第一极与第四参考信号端电连接，所述第m个第二十一晶体管的第二极与所述驱动信号输出端电连接。
  18. 如权利要求14所述的移位寄存器单元，其中，所述移位寄存器单元还包括M个第二十二晶体管；其中，所述M个第二十二晶体管中的第m个第二十二晶体管的栅极与所述第一输入信号端电连接，所述第m个第二十二晶体管的第一极与所述第二参考信号端电连接，所述第m个第二十二晶体管与所述第m个第二子节点电连接。
  19. 如权利要求14所述的移位寄存器单元，其中，所述移位寄存器单元 还包括第二十三晶体管；
    所述第二十三晶体管的栅极与初始复位信号端电连接，所述第二十三晶体管的第一极与所述第二参考信号端电连接，所述第二十三晶体管与所述第一节点电连接。
  20. 如权利要求1-11任一项所述的移位寄存器单元，其中，所述移位寄存器单元还包括：
    级联降噪单元，被配置为响应于所述级联输出端的信号，将所述第二参考信号端的信号提供给所述复位信号端。
  21. 如权利要求20所述的移位寄存器单元，其中，所述级联降噪单元包括：第十二晶体管；
    所述第十二晶体管的栅极与所述级联输出端电连接，所述第十二晶体管的第一极与所述第二参考信号端电连接，所述第十二晶体管的第二极与复位信号端电连接。
  22. 一种栅极驱动电路，其中，包括级联的多个如权利要求1-21任一项所述的移位寄存器单元；
    在所述第一输入信号端和所述第二输入信号端为相互独立的信号端时，级联每相邻的M个移位寄存器单元中，第M个移位寄存器单元的第一输入信号端与第1个移位寄存器单元的级联输出端电连接，且第M个移位寄存器单元的第二输入信号端与第1个移位寄存器单元的驱动输出端电连接；并且，级联每相邻的M+1个移位寄存器单元中，第1个移位寄存器单元的复位信号端与第M+1个移位寄存器单元的级联输出端电连接；其中，M为大于1的整数；
    在所述第一输入信号端和所述第二输入信号端为同一信号端时，级联每相邻的M个移位寄存器单元中，第M个移位寄存器单元的第一输入信号端与第1个移位寄存器单元的级联输出端电连接；并且，级联每相邻的M+1个移位寄存器单元中，第1个移位寄存器单元的复位信号端与第M+1个移位寄存器单元的级联输出端电连接。
  23. 如权利要求22所述的栅极驱动电路，其中，在所述第一输入信号端和所述第二输入信号端为相互独立的信号端时，在级联每相邻的M个移位寄存器单元中，所述第M个移位寄存器单元的第一输入信号端与所述第1个移位寄存器单元的级联输出端电连接的走线具有第一长度；所述第M个移位寄存器单元的第二输入信号端与所述第1个移位寄存器单元的驱动输出端电连接的走线具有第二长度；
    所述第一长度与所述第二长度之间的比值为1.0～1.5。
  24. 一种显示装置，其中，包括多条栅线以及如权利要求22或23所述的栅极驱动电路；
    一条所述栅线与所述栅极驱动电路中的一个移位寄存器单元的驱动输出端电连接。
PCT/CN2022/120228 2021-10-26 2022-09-21 移位寄存器单元、栅极驱动电路及显示装置 WO2023071633A1 (zh)

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