WO2023070520A1 - 一种发光芯片及其制备方法、发光装置 - Google Patents

一种发光芯片及其制备方法、发光装置 Download PDF

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Publication number
WO2023070520A1
WO2023070520A1 PCT/CN2021/127403 CN2021127403W WO2023070520A1 WO 2023070520 A1 WO2023070520 A1 WO 2023070520A1 CN 2021127403 W CN2021127403 W CN 2021127403W WO 2023070520 A1 WO2023070520 A1 WO 2023070520A1
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Prior art keywords
light
layer
heat dissipation
emitting chip
emitting
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PCT/CN2021/127403
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English (en)
French (fr)
Inventor
杨山伟
马俊杰
卢元达
熊志军
岂林霞
赵加伟
孙元浩
Original Assignee
京东方科技集团股份有限公司
京东方晶芯科技有限公司
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Application filed by 京东方科技集团股份有限公司, 京东方晶芯科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/127403 priority Critical patent/WO2023070520A1/zh
Priority to CN202180003178.XA priority patent/CN116888747A/zh
Priority to US17/918,214 priority patent/US20240213432A1/en
Publication of WO2023070520A1 publication Critical patent/WO2023070520A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/642—Heat extraction or cooling elements characterized by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/641—Heat extraction or cooling elements characterized by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0075—Processes relating to semiconductor body packages relating to heat extraction or cooling elements

Definitions

  • the present disclosure relates to the field of display technology, in particular to a light-emitting chip, a preparation method thereof, and a light-emitting device.
  • Mini LED light-emitting chips and Micro LED light-emitting chips are the main force in the development of LED (Light Emitting Diode, light-emitting diode) technology in recent years.
  • Mini/Micro LED light-emitting chips can be widely used in LCD backlight, Mini/Micro RGB display, small pitch Display and other fields.
  • Mini/Micro LED light-emitting chips In order to achieve mass production of low-cost and low-power Mini/Micro LED products, high-voltage chip designs such as 6V, 9V, and 12V are gradually introduced into Mini/Micro LED light-emitting chips, forming the existing high-voltage Mini/Micro LED chips. LED light emitting chip.
  • the existing high-voltage Mini/Micro LED light-emitting chip is divided into multiple small light-emitting units (cells). Due to the small area of each small light-emitting unit, the heat dissipation paths of the high-voltage Mini/Micro LED light-emitting chip are reduced, and the heat dissipation Performance deteriorates.
  • the present disclosure provides a light-emitting chip, including:
  • a light-emitting unit comprising an electron injection layer, a light-emitting layer and a hole injection layer sequentially stacked on the patterned substrate;
  • the first electrode is connected to the electron injection layer, and the second electrode is connected to the hole injection layer;
  • first passivation layer partially covering the light emitting unit, the first electrode, and the second electrode, the first passivation layer including a first opening, and the light emitting unit is partially exposed from the first opening;
  • the heat dissipation layer covers the first passivation layer and the exposed part of the light emitting unit from the first passivation layer.
  • the light emitting unit further includes a current spreading layer formed on the hole injection layer, and the current spreading layer is partially exposed from the first opening of the first passivation layer.
  • the light-emitting chip also includes:
  • an optical adjustment layer at least partially covering the heat dissipation layer
  • the first pad passes through the optical adjustment layer and the via hole on the heat dissipation layer and the first electrode exposing the first passivation layer
  • the second pad is connected to the second electrode exposing the first passivation layer through the optical adjustment layer and the via hole on the heat dissipation layer, and the heat dissipation layer has insulation.
  • the light-emitting chip also includes:
  • the heat dissipation end is disposed on the optical adjustment layer, and the optical adjustment layer is provided with a second opening exposing the heat dissipation layer, and the heat dissipation end is connected to the heat dissipation layer through the second opening.
  • the orthographic projection of the first opening on the patterned substrate overlaps with the orthographic projection of the heat dissipation end portion on the patterned substrate.
  • the height of the portion of the heat dissipation end portion beyond the optical adjustment layer is less than or equal to the height of the portion of the solder pad beyond the optical adjustment layer.
  • the heat dissipation end has a fin structure.
  • the heat dissipation end is embedded in the second opening.
  • the heat dissipation end part covers an edge of the optical adjustment layer close to the second opening.
  • the heat dissipation end is made of at least one of aluminum nitride and silicon carbide
  • the heat dissipation layer is made of at least one of aluminum nitride and silicon carbide.
  • the light-emitting chip includes at least three light-emitting units arranged in a target direction and connected in series through bridging electrodes, the first electrode and the second electrode are respectively connected to all the light-emitting units near both ends of the light-emitting chip.
  • the light-emitting unit is connected, the orthographic projection of the heat dissipation end on the patterned substrate and the orthographic projection of the light-emitting unit between the light-emitting units near the two ends of the light-emitting chip on the patterned substrate The projections overlap.
  • the first passivation layer includes:
  • a patterned first passivation sublayer the first electrode is connected to the electron injection layer of the corresponding light-emitting unit through a via hole on the first passivation sublayer, and the second electrode is connected to the corresponding electron injection layer
  • the hole injection layer of the light-emitting unit is connected through the via hole on the first passivation sublayer, the bridging electrode is arranged on the first passivation sublayer, and passes through the first passivation sublayer
  • the via holes connect the two light-emitting units;
  • a patterned second passivation sublayer covers the bridging electrodes, and the first opening is arranged in the second passivation sublayer.
  • the light-emitting chip also includes:
  • the second passivation layer is disposed on the optical adjustment layer and the sidewall of the via hole where the welding pad is located on the heat dissipation layer.
  • the thinnest thickness of the heat dissipation layer is greater than or equal to 1.2 ⁇ m and less than or equal to 4 ⁇ m.
  • the present disclosure also provides a method for preparing a light-emitting chip, which is used to prepare the above-mentioned light-emitting chip, and the method includes:
  • an electron injection layer, a light-emitting layer and a hole injection layer are sequentially stacked to obtain a light-emitting unit;
  • Patterning forms a first passivation layer, a first electrode and a second electrode; the first electrode is connected to the electron injection layer, the second electrode is connected to the hole injection layer, and the first passivation layer part Covering the light-emitting unit, the first electrode, and the second electrode, the first passivation layer includes a first opening, and the light-emitting unit is partially exposed from the first opening;
  • a heat dissipation layer is formed; the heat dissipation layer covers the first passivation layer and the exposed part of the light emitting unit from the first passivation layer.
  • the heat dissipation layer after forming the heat dissipation layer, it also includes:
  • the optical adjustment layer is provided with a second opening exposing the heat dissipation layer;
  • a heat dissipation end portion is formed on the heat dissipation layer exposed from the second opening.
  • the heat dissipation layer after forming the heat dissipation layer, it also includes:
  • the optical adjustment layer is provided with a second opening exposing the heat dissipation layer, and the heat dissipation layer includes a part embedded in the second opening;
  • a heat dissipation end portion is formed on the optical adjustment layer; the heat dissipation end portion covers the edge of the optical adjustment layer close to the second opening, and the heat dissipation end portion and the heat dissipation layer are embedded in the second opening Partial connection.
  • the method further includes:
  • the heat dissipation end portion is laser etched to form a fin structure on the heat dissipation end portion.
  • the present disclosure also provides a light-emitting device, including the above-mentioned light-emitting chip.
  • the light emitting device further includes a driving substrate, the driving substrate includes a first connection end and a second connection end, the light emitting chip includes a first bonding pad and a second bonding pad, and the first bonding pad and The first connection end is connected, the second pad is connected to the second connection end, and the drive substrate further includes a closed structure between the first connection end and the second connection end, so The sealing structure is used to seal the film layer exposed between the first connection end and the second connection end on the driving substrate, the light-emitting chip includes a heat dissipation end, and the heat dissipation end is connected to the sealing structural abutment.
  • Fig. 1 shows a schematic diagram of bridging of each light-emitting unit in an existing light-emitting chip
  • FIG. 2 shows a schematic diagram of an overhead light-emitting unit in an existing light-emitting chip
  • Fig. 3 shows a schematic diagram of an overhead light-emitting unit in another existing light-emitting chip
  • Fig. 4 shows a schematic cross-sectional view of a light-emitting chip according to an embodiment of the present disclosure
  • FIG. 5 shows a schematic cross-sectional view of another light-emitting chip according to an embodiment of the present disclosure
  • Fig. 6 shows a schematic cross-sectional view of another light-emitting chip according to an embodiment of the present disclosure
  • Fig. 7 shows a schematic top view of several arrangements of light emitting units according to an embodiment of the present disclosure
  • FIG. 8 shows a flow chart of the steps of a method for manufacturing a light-emitting chip according to an embodiment of the present disclosure
  • 9-18 show schematic cross-sectional views of the chip in the process flow of the method for preparing the light-emitting chip according to the embodiment of the present disclosure
  • 19-23 show the schematic diagrams of each processing flow after the light-emitting chip is manufactured according to the embodiment of the present disclosure
  • Fig. 24 shows a schematic cross-sectional view of a light emitting device according to an embodiment of the present disclosure
  • Fig. 25 shows a schematic cross-sectional view of another light emitting device according to an embodiment of the present disclosure.
  • Mini/Micro LED backlight and display products based on different packaging forms such as POG/POB (Package On Glass/Board), COB (Chip On Board), and COG (Chip On Glass).
  • POG/POB Package On Glass/Board
  • COB Chip On Board
  • COG Chip On Glass
  • Mini/Micro LED chips As the core light-emitting device of Mini/Micro LED products, Mini/Micro LED chips have increasingly stringent performance requirements. However, the heat conversion rate of current Mini/Micro LED chips is still high. Taking the high-voltage Mini LED chip used for backlight as an example, about 34% of its electric power is converted into heat through non-recombined radiation. For the 4*8mil and 3*6mil RGBMini LED chips used in small-pitch displays, the proportion of heat converted into heat through non-composite radiation can even be as high as about 70%. Therefore, it is very important to have good heat dissipation performance for high-voltage Mini/Micro LED chips.
  • the existing conventional high-voltage Mini/Micro LED chip includes more than two small light-emitting units (cells), as shown in the cross-sectional view of the chip in Figure 1, each The cells are connected together through the bridge electrode 03. Due to the small area of each cell inside the chip, the heat dissipation paths of the Mini/Micro LED chip are reduced, and the heat dissipation performance is deteriorated.
  • Mini/Micro LED backlight and display related products Poor thermal performance and poor mechanical performance are fatal problems for Mini/Micro LED backlight and display related products. If the heat dissipation performance of the Mini/Micro LED chip is not good, the heat generated by the Mini/Micro LED chip will accumulate inside it, which will increase the junction temperature of the Mini/Micro LED chip. An increase in junction temperature will further bring about problems such as reduced luminous efficiency of Mini/Micro LED chips, red-shifted luminous color, decreased forward voltage, and shortened lifespan. If the mechanical properties of the Mini/Micro LED chip are not good, the Mini/Micro LED chip will be easily broken, which will lead to the failure of the Mini/Micro LED chip.
  • Fig. 4, Fig. 5 and Fig. 6 respectively show cross-sectional schematic diagrams of three kinds of light-emitting chips 1000 according to embodiments of the present disclosure.
  • the light-emitting chip 1000 includes:
  • a light-emitting unit 20 comprising an electron injection layer 21, a light-emitting layer 22, and a hole injection layer 23 sequentially stacked on the patterned substrate 10;
  • the first electrode 30 and the second electrode 40, the first electrode 30 is connected to the electron injection layer 21, and the second electrode 40 is connected to the hole injection layer 23;
  • the first passivation layer 50 partially covers the light emitting unit 20, the first electrode 30 and the second electrode 40, the first passivation layer 50 includes a first opening 51, and the light emitting unit 20 is partially exposed from the first opening 51;
  • the heat dissipation layer 60 covers the first passivation layer 50 and the exposed part of the light emitting unit 20 from the first passivation layer 50 .
  • the patterned substrate 10 may be made of sapphire (Al 2 O 3 ) material, on which there is a patterned structure with a pitch of 1-2 ⁇ m, and the patterned structure can be used to reduce the defect density of the sapphire substrate and improve the crystal density. Quality, thereby improving the light extraction efficiency of the light emitting chip 1000.
  • sapphire Al 2 O 3
  • the light-emitting chip 1000 may further include a buffer layer 70 formed on the patterned substrate 10, usually made of GaN material, and the thickness may be 2 ⁇ m.
  • the buffer layer 70 can be used to improve the lattice constant mismatch between the sapphire substrate and the GaN material.
  • the electron injection layer 21 can be used to provide electrons.
  • the electron injection layer 21 can be made of GaN doped with Si, and can be used as the N region of the light emitting unit 20.
  • the thickness can be selected as about.
  • the light-emitting chip 1000 may further include a superlattice layer 80 formed on the electron injection layer 21.
  • the superlattice layer 80 It can include barrier/well pairs composed of 2nm InGaN and 25nm GaN, a total of 6 sets of barrier/well pairs, and the total thickness can be selected as Used to improve epitaxy quality.
  • the light-emitting layer 22 is the light-emitting region of the light-emitting chip 1000 and can confine carriers.
  • the light-emitting layer 22 can specifically be a multi-quantum well light-emitting layer, which can include barrier/potential well pairs composed of 3nm InGaN and 12nm GaN, a total of 9 sets of potential barrier/potential well pairs, and the total thickness is optional for
  • the light-emitting chip 1000 may further include an electron blocking layer 90 formed on the light-emitting layer 22, which can be used to block electrons from leaking to the P region of the light-emitting unit 20, and improve the light emission.
  • the electron blocking layer 90 can be made of InGaN, and the thickness can be
  • the hole injection layer 23 can be used to provide holes.
  • the hole injection layer 23 can be made of Mg-doped GaN, which can be used as the P region of the light emitting unit 20, and the thickness can be selected as about.
  • the first electrode 30 may be connected to the electron injection layer 21 to serve as an N electrode of the light emitting chip 1000 .
  • the second electrode 40 may be connected to the hole injection layer 23 to serve as a P electrode of the light emitting chip 1000 .
  • the first passivation layer 50 can be used to isolate the positions inside the light emitting chip 1000 except the conduction position, so as to prevent the short circuit of the light emitting chip 1000 .
  • a first opening 51 is disposed on the first passivation layer 50 , and a part of the light emitting unit 20 is exposed from the first opening 51 .
  • the first opening 51 can reserve a heat dissipation channel for the light emitting unit 20 .
  • the light-emitting unit 20 further includes a current spreading layer 110 formed on the hole injection layer 23 , and the current spreading layer 110 partially passes through the first opening 51 of the first passivation layer 50 exposed.
  • the current spreading layer 110 of the light emitting unit 20 partially exposes the first passivation layer 50 , so that the light emitting unit 20 can form direct contact with the heat dissipation layer 60 to form a heat dissipation channel, which is beneficial to the heat dissipation of the light emitting unit 20 .
  • the heat dissipation layer 60 can be used to dissipate the heat inside the light-emitting chip 1000 and speed up the heat transfer speed of each position of the PN junction to the outside.
  • the heat dissipation layer 60 can be introduced inside the light-emitting chip 1000 to increase the heat dissipation channels for the heat inside the light-emitting chip 1000, thereby quickly deriving the temperature inside the light-emitting chip 1000, improving the heat dissipation performance of the light-emitting chip 1000, reducing the overall temperature of the module.
  • the heat dissipation layer 60 can be used as a high-strength filling layer inside the light-emitting chip 1000 , thereby improving the mechanical strength of the light-emitting chip 1000 .
  • the light-emitting chip 1000 may further include:
  • the optical adjustment layer 120 at least partially covers the heat dissipation layer 60;
  • the pad 130 includes a first pad 131 and a second pad 132, the first pad 131 is connected to the first electrode 30 exposing the first passivation layer 50 through the via hole on the optical adjustment layer 120 and the heat dissipation layer 60, The second pad 132 is connected to the second electrode 40 exposing the first passivation layer 50 through the via holes on the optical adjustment layer 120 and the heat dissipation layer 60 , and the heat dissipation layer 60 has insulation properties.
  • the optical adjustment layer 120 can be used to make the light emitted by the light emitting layer 22 reflect more to the sapphire substrate, so as to improve the light extraction rate.
  • the optical adjustment layer 120 may include a distributed Bragg reflector structure.
  • the distributed Bragg reflector structure may specifically be a structure in which TiOx and SiOx film layers are stacked alternately, with a total of 48 layers, and the total thickness is optional. It is about 3.5 ⁇ m.
  • the pads 130 can be used to connect the electrodes of the light-emitting chip 1000 to the corresponding signal connection terminals on the drive substrate, wherein the first pad 131 is connected to the N electrode of the light-emitting chip 1000, and the second pad 132 is connected to the P electrode of the light-emitting chip 1000. connect.
  • Both the optical adjustment layer 120 and the heat dissipation layer 60 are provided with via holes for the pads to be connected to corresponding electrodes through the via holes. Since the pads and the corresponding electrodes need to be electrically connected, the heat dissipation layer 60 needs to be insulated, so as to avoid short circuit of the light emitting chip 1000 .
  • each pad may specifically include a pad connection portion and a pad body, wherein the pad connection portion is a portion where the pad is embedded in the via hole on the optical adjustment layer 120 and the heat dissipation layer 60, and the pad body is located at the pad connection portion.
  • the part is away from the side of the patterned substrate 10, and the pad body covers the edge of the optical adjustment layer 120 close to the via hole.
  • the light emitting chip 1000 further includes:
  • the heat dissipation end 140 is disposed on the optical adjustment layer 120 , and the optical adjustment layer 120 is provided with a second opening 121 exposing the heat dissipation layer 60 , and the heat dissipation end 140 is connected to the heat dissipation layer 60 through the second opening 121 .
  • the heat dissipation end 140 extends out of the light-emitting chip 1000, which can be used to increase the heat dissipation channel of the light-emitting chip 1000, and spread the heat inside the light-emitting chip 1000 to the outside of the light-emitting chip 1000 more quickly, further improving the heat dissipation performance of the light-emitting chip 1000.
  • the orthographic projection of the first opening 51 on the patterned substrate 10 overlaps with the orthographic projection of the heat dissipation end portion 140 on the patterned substrate 10 .
  • the first opening 51 overlaps with the heat dissipation end 140, that is, the heat dissipation end 140 can be arranged above the heat dissipation channel of the light emitting unit 20, so that the length of the light emitting unit 20 can be shortened.
  • the heat transfer path enables the heat of the light-emitting unit 20 to be dissipated to the outside of the light-emitting chip 1000 as soon as possible.
  • the height of the heat dissipation end portion 140 beyond the optical adjustment layer 120 is less than or equal to the height of the pad 130 beyond the optical adjustment layer. 120 for the height of the section.
  • the height of the heat dissipation end 140 should not exceed the height of the portion of the pad 130 beyond the optical adjustment layer 120, that is, the height of the heat dissipation end 140 should not exceed the height of the solder pad 130.
  • the height of the disk body can ensure the normal welding between the pad 130 and the driving substrate.
  • the heat dissipation end portion 140 has a fin structure. In this way, the heat dissipation area of the heat dissipation end portion 140 can be increased.
  • the heat dissipation end portion 140 may be embedded in the second opening 121 .
  • the heat dissipation end portion 140 may cover the edge of the optical adjustment layer 120 close to the second opening 121 .
  • the heat dissipation end portion 140 and the heat dissipation layer 60 are made of the same material, fewer process steps are required for the heat dissipation end portion 140 and the heat dissipation layer 60 , The process is relatively simple.
  • the laying area of the optical adjustment layer 120 is larger, so that the light extraction rate of the light-emitting chip 1000 can be higher.
  • the light-emitting chip 1000 includes at least three light-emitting units 20 arranged in the target direction and connected in series through the bridging electrodes 150, the first electrodes 30 and the second electrodes 40 are respectively connected to the light-emitting units 20 near both ends of the light-emitting chip 1000,
  • the orthographic projection of the heat dissipation end portion 140 on the patterned substrate 10 overlaps with the orthographic projection of at least one light-emitting unit between the light-emitting units near both ends of the light-emitting chip 1000 on the patterned substrate 10 .
  • the target direction is a preset direction, which can be preset according to requirements in practical applications. All the light emitting units 20 in series are arranged along the target direction, and the first electrode 30 and the second electrode 40 are respectively connected to the light emitting units 20 at the first and last positions (or first and last positions) of the series.
  • the first pad 131 can support the light-emitting unit 20 connected to the first electrode 30
  • the second pad 132 can support the light-emitting unit 20 connected to the second electrode 40 .
  • the light-emitting units 20 are supported, but the light-emitting units 20 between the front and rear light-emitting units 20 will be overhead on the driving substrate, and the driving substrate cannot support the light-emitting units 20 in the middle.
  • the heat-dissipating end 140 overlaps the light-emitting chip 1000 in the middle position. In this way, the heat-dissipating end 140 can be in contact with the driving substrate through height design, so that the middle position
  • the light emitting unit 20 forms a support, which improves the mechanical strength of the light emitting chip 1000 .
  • the heat dissipation end portion 140 may also be provided on the light emitting chip 1000 .
  • FIG. 7 it schematically shows a top view of the arrangement of several light-emitting units 20, wherein, in some light-emitting chips, the orthographic projection of each light-emitting unit 20 on the patterned substrate 10 is consistent with the patterns of the pads 130.
  • the orthographic projections on the substrate 10 all overlap, and such a light-emitting chip is a light-emitting chip without an overhead light-emitting unit 20 . After the light-emitting chip of the light-emitting unit 20 without overhead is assembled with the driving substrate, there is no light-emitting unit 20 completely suspended above the driving substrate.
  • the thinnest thickness of the heat dissipation layer 60 is greater than or equal to 1.2 ⁇ m and less than or equal to 4 ⁇ m.
  • the heat dissipation layer 60 satisfying this thickness range can not only play the role of heat dissipation, but also serve as a high-strength filling layer above the bridging electrodes, which can improve the mechanical strength of the bridging positions.
  • the first passivation layer 50 may include:
  • the patterned first passivation sublayer 52, the first electrode 30 is connected to the electron injection layer 21 of the corresponding light emitting unit 20 through the via hole on the first passivation sublayer 52, the second electrode 40 is connected to the corresponding light emitting unit 20
  • the hole injection layer 23 is connected through the via hole on the first passivation sublayer 52, the bridging electrode 150 is arranged on the first passivation sublayer 52, and connects the two through the via hole on the first passivation sublayer 52.
  • the patterned second passivation sublayer 53 covers the bridging electrodes 150 , and the first opening 51 is disposed on the second passivation sublayer 53 .
  • the bridge electrode 150 is disposed on the first passivation sublayer 52, and the first passivation sublayer 52 can be used to isolate the bridge electrode 150 from the conductive film layer in the light emitting unit 20, Only the positions on the light emitting unit 20 that need to be connected to the electrodes are reserved.
  • the second passivation sublayer 53 can be used to isolate the heat dissipation layer 60 from the bridging electrodes 150 , so as to prevent the short circuit of the light emitting chip 1000 .
  • the thickness of the second passivation sublayer 53 can be selected as or so, the thickness of the entire first passivation layer 50 can be in about.
  • the light-emitting chip 1000 may further include:
  • the second passivation layer 160 is disposed on the optical adjustment layer 120 and the sidewall of the via hole where the pad 130 is located on the heat dissipation layer 60 .
  • a second passivation layer 160 may be provided on the sidewall of the via hole where the pad 130 is located on the optical adjustment layer 120 and the heat dissipation layer 60, and the second passivation layer 160 may be used to isolate the connection portion of the pad from the The via holes prevent direct contact between the heat dissipation layer 60 and the pad 130 , the first electrode 30 , and the second electrode 40 , which can prevent the light emitting unit 20 from leaking through the heat dissipation layer 60 and prevent the light emitting chip 1000 from short circuiting.
  • At least one of aluminum nitride (AlN) and silicon carbide (SiC) can be used as the material of the heat dissipation end portion 140, and at least one of aluminum nitride and silicon carbide can be used as the material of the heat dissipation layer 60. at least one of .
  • AlN has an ultra-high thermal conductivity of up to 240W/(M ⁇ K) and a thermal expansion coefficient of 3.3 ⁇ 5.0 ( ⁇ 10 -6 /°C), which matches the thermal expansion coefficient of the light-emitting chip 1000 very well.
  • the melting point of AlN is 2470°C, which is very high temperature resistant , and has good insulation properties, ultra-high strength properties and ultra-high corrosion resistance.
  • AlN has good insulating properties, it is in contact with almost all the film layers inside the light-emitting chip 1000 that are electrically conductive.
  • a passivation layer is added to enhance the electrical performance of the light emitting chip 1000 .
  • the added passivation layer also enables not only AlN to be used as a heat dissipation film, but materials such as SiC, BeO and other materials that are not as insulating as AlN can also be used as a heat dissipation film, which is added to the inside of the light emitting chip 1000 to increase the heat dissipation performance of the chip.
  • SiC SiC
  • BeO can be used in light-emitting chip 1000 products according to law.
  • Both passivation layers can be made of SiO2.
  • the structures of the bridge electrode 150, the first electrode 30 and the second electrode 40 can all be a metal stack structure composed of Ti/Al/Ti/Ni/Ti/Al/Ti/Pt/Au.
  • the thickness of the first electrode 30 and the second electrode 40 can be selected to be about 1.47 ⁇ m, and the thickness of each metal layer is about 5/12/88/42/316/103/627/97/182 nm respectively.
  • the thickness of the bridging electrode 150 can be selected to be about 1.45 ⁇ m, and the thickness of each metal layer is about 3/5/86/42/312/98/623/93/189 nm respectively.
  • the current spreading layer 110 can be made of ITO material, and the thickness can be selected as about.
  • the structure of the pad connection part can be a metal stack structure composed of Ti/Al/Ti/Pt, Au alloy/Ni/Pt, and Au alloy, and the thickness of each metal layer is 94/206/92/63/328/58nm respectively.
  • the materials that can be used for the pad body are Sn, Ag, and Cu alloys, and the proportions of each material can be Sn-96.5%, Ag-3%, and Cu-0.5%, and the thickness of the pad body can be 8 ⁇ 0.8 ⁇ m.
  • the substrate material for example, the substrate adopts ceramic material with better heat dissipation
  • the heat dissipation method of the LED bracket material it is only applicable to Mini/Micro LED products in the form of POG packaging, but not to COB and COG For Mini/Micro LED products in package form, this is mainly because the substrate materials in COB and COG packages are fixed.
  • COB uses PCB or FPC substrates
  • COG uses glass substrates.
  • the heat dissipation performance tends to be saturated, and there is basically no room for improvement, and there is no LED bracket.
  • the heat dissipation of COB and COG is mainly by adding a temperature sensor.
  • the light-emitting chip provided by the embodiments of the present disclosure can achieve a good heat dissipation effect without adding any additional devices and without sacrificing optical effects.
  • the heat dissipation layer 60 may be introduced inside the light emitting chip 1000 , and the heat dissipation end portion 140 may be added outside the light emitting chip 1000 .
  • the heat dissipation layer 60 can dissipate the heat inside the light-emitting chip 1000 through heat conduction.
  • the heat dissipation layer 60 can also improve the mechanical strength of the bridge position of the light-emitting unit 20 .
  • the heat dissipation end 140 can conduct the heat inside the light emitting chip 1000 to the outside of the light emitting chip 1000 through heat radiation.
  • the heat dissipation end 140 can also support the overhead light emitting unit. In this way, the heat dissipation performance and mechanical performance of the light emitting chip 1000 are improved.
  • FIG. 8 it shows a flowchart of steps of a method for preparing a light-emitting chip 1000 according to an embodiment of the present disclosure.
  • the preparation method is used to prepare the above-mentioned light-emitting chip 1000.
  • the preparation method includes the following steps:
  • Step 801 sequentially stack an electron injection layer, a light emitting layer and a hole injection layer on a patterned substrate to obtain a light emitting unit.
  • the electron blocking layer 90, the hole injection layer 23, and the current spreading layer 110 are then etched through holes and isolation grooves at positions with larger thicknesses through processes such as photolithography and etching, so as to obtain the light emitting unit 20, as shown in Figure 9 shown.
  • Step 802 patterning to form a first passivation layer, a first electrode and a second electrode; the first electrode is connected to the electron injection layer, the second electrode is connected to the hole injection layer, and the first passivation layer partially covers the light emitting unit, the second electrode An electrode and a second electrode, the first passivation layer includes a first opening, and part of the light emitting unit is exposed from the first opening.
  • the first passivation sub-layer 52 is formed by patterning, and a desired position is exposed.
  • the first electrode 30 , the second electrode 40 and the bridge electrode 150 are patterned.
  • the second passivation sub-layer 53 is formed by patterning, and the required position is exposed to obtain the first passivation layer 50 .
  • Step 803 forming a heat dissipation layer; the heat dissipation layer covers the first passivation layer and the exposed part of the light emitting unit from the first passivation layer.
  • the heat dissipation layer after forming the heat dissipation layer, it also includes:
  • the optical adjustment layer is provided with a second opening exposing the heat dissipation layer, and the heat dissipation layer includes a part embedded in the second opening;
  • a heat dissipation end is formed on the optical adjustment layer; the heat dissipation end covers the edge of the optical adjustment layer close to the second opening, and the heat dissipation end is connected with the part of the heat dissipation layer embedded in the second opening.
  • a heat dissipation material layer and an optical adjustment material layer are sequentially formed, and then patterned to form a heat dissipation layer 60 and an optical adjustment layer 120, wherein the heat dissipation layer 60 includes embedding the first The part in the second opening 121 .
  • a second passivation layer 160 is formed on the sidewall of the via hole where the pad connection portion needs to be provided.
  • pad connection portions are formed.
  • a pad body is formed.
  • a heat dissipation end portion 140 may be formed on the optical adjustment layer 120 , wherein the heat dissipation end portion 140 is connected to the portion of the heat dissipation layer 60 embedded in the second opening 121 , to obtain a light emitting chip 1000 as shown in FIG. 4 .
  • the heat dissipation layer after the heat dissipation layer is formed, it further includes:
  • the optical adjustment layer is provided with a second opening exposing the heat dissipation layer;
  • a heat dissipation end portion is formed on the heat dissipation layer exposed from the second opening.
  • the process of forming the heat dissipation layer 60 , the optical adjustment layer 120 , the second passivation layer 160 , the pad connection part and the pad body is basically the same as that of the above-mentioned embodiments, the difference is that The heat dissipation layer 60 does not include a portion embedded in the second opening 121 .
  • a heat dissipation end portion 140 can be formed on the heat dissipation layer 60 exposed from the second opening 121 , wherein the heat dissipation end portion 140 is located in the second opening 121 , to obtain the light emitting chip 1000 as shown in FIG. 5 .
  • the process of forming the heat dissipation layer 60 , the optical adjustment layer 120 , the second passivation layer 160 , the pad connection portion and the pad body is basically the same as that of the above-mentioned embodiment, the difference is , the optical adjustment layer 120 does not include the opening 121 . After that, the heat dissipation end portion 140 is no longer formed, so that the light emitting chip 1000 as shown in FIG. 6 can be obtained.
  • the following step may also be included: laser etching the heat dissipation end portion 140 to form a fin structure on the heat dissipation end portion 140 .
  • the heat dissipation area of the heat dissipation end portion 140 can be increased.
  • the thickness of the sapphire substrate can be reduced by grinding, and further referring to FIG. 20 , the entire wafer is laser cut into single crystal grains. Dies can then be tested for opto-electronic characteristics, sorted to specifications, and manually inspected visually. Among them, referring to Figure 21, the photoelectric characteristic test is to test the photoelectric characteristics of each crystal grain through spot testing equipment. Referring to Figure 22, the classification according to the specifications means that the crystal grains are classified into different specifications according to the photoelectric parameters of the grains , referring to FIG. 23 , manual visual inspection means manual removal of grains with poor appearance.
  • preparation method may also include other conventional steps, which are not specifically limited in the embodiments of the present disclosure.
  • the heat dissipation layer 60 can be formed inside the light-emitting chip 1000, which increases the heat dissipation channel for the heat inside the light-emitting chip 1000, thereby quickly deriving the temperature inside the light-emitting chip 1000, improving the heat dissipation performance of the light-emitting chip 1000, reducing Displays the overall temperature of the device.
  • the heat dissipation layer 60 can be used as a high-strength filling layer inside the light-emitting chip 1000 , thereby improving the mechanical strength of the light-emitting chip 1000 .
  • the embodiment of the present disclosure also discloses a light emitting device, including the above light emitting chip 1000 .
  • the light-emitting device further includes a driving substrate 2000
  • the driving substrate 2000 includes a first connection end 2001 and a second connection end 2002
  • the light-emitting chip 1000 includes a first pad 131 and a second pad 132
  • the A pad 131 is connected to the first connection end 2001
  • a second pad 132 is connected to the second connection end 2002 .
  • the first connection end 2001 and the second connection end 2002 may specifically be pads.
  • the drive substrate 2000 may include two types, one is a drive substrate with a closed connection end as shown in FIG. 24 , and the other is a drive substrate with an open connection end as shown in FIG. 25 .
  • the drive substrate 2000 further includes a closed structure 2003 located between the first connection end 2001 and the second connection end 2002, and the closed structure 2003 is used to close the drive substrate 2000 from the first The film layer exposed between the connection end 2001 and the second connection end 2002 .
  • the heat dissipation end portion 140 may be in contact with the closed structure 2003 .
  • a driving substrate with a closed connection end and a driving substrate with an open connection end can also be combined to form a light-emitting device.
  • the heat dissipation layer 60 can be formed inside the light-emitting chip 1000, which increases the heat dissipation channel for the heat inside the light-emitting chip 1000, thereby quickly deriving the temperature inside the light-emitting chip 1000, improving the heat dissipation performance of the light-emitting chip 1000, reducing Displays the overall temperature of the device.
  • the heat dissipation layer 60 can be used as a high-strength filling layer inside the light-emitting chip 1000 , thereby improving the mechanical strength of the light-emitting chip 1000 .
  • references herein to "one embodiment,” “an embodiment,” or “one or more embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Additionally, please note that examples of the word “in one embodiment” herein do not necessarily all refer to the same embodiment.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
  • the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the disclosure can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means can be embodied by one and the same item of hardware.
  • the use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

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Abstract

本公开提供了一种发光芯片及其制备方法、发光装置，涉及显示技术领域。其中，发光芯片包括图形化衬底；发光单元，包括电子注入层、发光层和空穴注入层；第一电极，与电子注入层连接；第二电极，与空穴注入层连接；第一钝化层，部分覆盖发光单元、第一、第二电极，第一钝化层包括第一开口，发光单元部分从第一开口露出；散热层，覆盖第一钝化层，以及发光单元从第一钝化层露出的部分。在本公开中，可以在发光芯片内部引入散热层，增加了发光芯片内部热量的散热通道，从而将发光芯片内部的温度快速导出，提高了发光芯片的散热性能。同时，散热层可作为发光芯片内部的高强度填充层，从而可以提升发光芯片的机械强度。

Description

一种发光芯片及其制备方法、发光装置 技术领域
本公开涉及显示技术领域，特别是涉及一种发光芯片及其制备方法、发光装置。
背景技术
Mini LED发光芯片和Micro LED发光芯片是近年来LED(Light Emitting Diode，发光二极管)技术发展的主力，Mini/Micro LED发光芯片可广泛应用到液晶显示器背光源、Mini/Micro RGB显示屏、小间距显示屏等领域。
为实现低成本和低功耗的Mini/Micro LED产品的量产，诸如6V、9V和12V等高压芯片设计方案逐步被引入到Mini/Micro LED发光芯片中，形成了现有的高压Mini/Micro LED发光芯片。
但是，现有的高压Mini/Micro LED发光芯片内部分为多个小的发光单元(cell)，由于各个小发光单元的面积较小，使得高压Mini/Micro LED发光芯片的散热路径变少，散热性能变差。
发明内容
本公开提供一种发光芯片，包括：
图形化衬底；
发光单元，包括依次叠层形成在所述图形化衬底上的电子注入层、发光层和空穴注入层；
第一电极和第二电极，所述第一电极与所述电子注入层连接，所述第二电极与所述空穴注入层连接；
第一钝化层，部分覆盖所述发光单元、所述第一电极和所述第二电极，所述第一钝化层包括第一开口，所述发光单元部分从所述第一开口露出；
散热层，覆盖所述第一钝化层，以及所述发光单元从所述第一钝化层露出的部分。
可选地，所述发光单元还包括形成在所述空穴注入层上的电流扩展层，所述电流扩展层部分从所述第一钝化层的所述第一开口露出。
可选地，所述发光芯片还包括：
光学调整层，至少部分覆盖所述散热层；
焊盘，包括第一焊盘和第二焊盘，所述第一焊盘通过所述光学调整层和所述散热层上的过孔与露出所述第一钝化层的所述第一电极连接，所述第二焊盘通过所述光学调整层和所述散热层上的过孔与露出所述第一钝化层的所述第二电极连接，所述散热层具有绝缘性。
可选地，所述发光芯片还包括：
散热端部，设置在所述光学调整层上，所述光学调整层上设置有露出所述散热层的第二开口，所述散热端部通过所述第二开口与所述散热层连接。
可选地，所述第一开口在所述图形化衬底上的正投影与所述散热端部在所述图形化衬底上的正投影存在交叠。
可选地，在所述发光芯片的叠层方向上，所述散热端部超出所述光学调整层的部分的高度小于或等于所述焊盘超出所述光学调整层的部分的高度。
可选地，所述散热端部具有翅片结构。
可选地，所述散热端部嵌入所述第二开口中。
可选地，所述散热端部覆盖所述光学调整层靠近所述第二开口的边缘。
可选地，所述散热端部的材料采用氮化铝和碳化硅中的至少一种，所述散热层的材料采用氮化铝和碳化硅中的至少一种。
可选地，所述发光芯片包括沿目标方向排布，且通过桥接电极串联的至少三个所述发光单元，所述第一电极和所述第二电极分别与靠近所述发光芯片两端的所述发光单元连接，所述散热端部在所述图形化衬底上的正投影与靠近所述发光芯片两端的所述发光单元之间的所述发光单元在所述图形化衬底上的正投影存在交叠。
可选地，所述第一钝化层包括：
图案化的第一钝化子层，所述第一电极与对应的所述发光单元的电子注入层通过所述第一钝化子层上的过孔连接，所述第二电极与对应的所述发光单元的空穴注入层通过所述第一钝化子层上的过孔连接，所述桥接电极设置在所述第一钝化子层上，并通过所述第一钝化子层上的过孔连接两个所述发光单元；
图案化的第二钝化子层，覆盖所述桥接电极，所述第一开口设置在所述 第二钝化子层。
可选地，所述发光芯片还包括：
第二钝化层，设置在所述光学调整层和所述散热层上所述焊盘所在的过孔的侧壁上。
可选地，在所述发光芯片的叠层方向上，所述散热层的厚度最薄处大于或等于1.2μm，且小于或等于4微米。
本公开还提供一种发光芯片的制备方法，用于制备上述发光芯片，所述方法包括：
在图形化衬底上依次叠层形成电子注入层、发光层和空穴注入层，以得到发光单元；
图案化形成第一钝化层、第一电极和第二电极；所述第一电极与所述电子注入层连接，所述第二电极与所述空穴注入层连接，第一钝化层部分覆盖所述发光单元、所述第一电极和所述第二电极，所述第一钝化层包括第一开口，所述发光单元部分从所述第一开口露出；
形成散热层；所述散热层覆盖所述第一钝化层，以及所述发光单元从所述第一钝化层露出的部分。
可选地，所述形成散热层之后，还包括：
形成光学调整层；所述光学调整层上设置有露出所述散热层的第二开口；
在从所述第二开口露出的所述散热层上形成散热端部。
可选地，所述形成散热层之后，还包括：
形成光学调整层；所述光学调整层上设置有露出所述散热层的第二开口，所述散热层包括嵌入所述第二开口中的部分；
在所述光学调整层上形成散热端部；所述散热端部覆盖所述光学调整层靠近所述第二开口的边缘，所述散热端部与所述散热层嵌入所述第二开口中的部分连接。
可选地，所述在所述光学调整层上形成散热端部之后，还包括：
对所述散热端部激光刻蚀，以在所述散热端部上形成翅片结构。
本公开还提供一种发光装置，包括上述发光芯片。
可选地，所述发光装置还包括驱动基板，所述驱动基板包括第一连接端和第二连接端，所述发光芯片包括第一焊盘和第二焊盘，所述第一焊盘与所 述第一连接端连接，所述第二焊盘与所述第二连接端连接，所述驱动基板还包括位于所述第一连接端与所述第二连接端之间的封闭结构，所述封闭结构用于封闭所述驱动基板上从所述第一连接端与所述第二连接端之间露出的膜层，所述发光芯片包括散热端部，所述散热端部与所述封闭结构抵接。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了现有的一种发光芯片中各发光单元的桥接示意图；
图2示出了现有的一种发光芯片中存在架空发光单元的示意图；
图3示出了现有的另一种发光芯片中存在架空发光单元的示意图；
图4示出了本公开实施例的一种发光芯片的截面示意图；
图5示出了本公开实施例的另一种发光芯片的截面示意图；
图6示出了本公开实施例的再一种发光芯片的截面示意图；
图7示出了本公开实施例的几种发光单元排列方式的俯视示意图；
图8示出了本公开实施例的一种发光芯片的制备方法的步骤流程图；
图9-18示出了本公开实施例的发光芯片制备方法流程中的芯片截面示意图；
图19-23示出了本公开实施例的制成发光芯片后的各处理流程示意图；
图24示出了本公开实施例的一种发光装置的截面示意图；
图25示出了本公开实施例的另一种发光装置的截面示意图。
具体实施例
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于 本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等方位词仅用于表示基于附图的相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着显示技术的提高，人们对基于Mini/Micro LED的4K、8K等高性能的电视机(Television，TV)、显示器(Monitor，MNT)、笔记本电脑(NoteBookComputer，NB)和全彩显示屏等产品的需求越来越多。在实际应用中，已存在基于POG/POB(Package OnGlass/Board)、COB(Chip On Board)、COG(Chip On Glass)等不同封装形式的Mini/Micro LED背光和显示产品。
Mini/Micro LED芯片作为Mini/Micro LED产品核心发光器件，对其性能的要求越来越严苛。但是，目前的Mini/Micro LED芯片热量转换率仍然较高。以用于背光的高压Mini LED芯片为例，其有高达34％左右的电功率通过非复合辐射的方式转换成了热量。而对于小间距显示屏所用的4*8mil和3*6mil尺寸的RGBMini LED芯片，通过非复合辐射方式转换成热量的比例甚至可高达70％左右。因此，具备良好的散热性能对高压Mini/Micro LED芯片来说至关重要。
但是，有别于传统单颗低压Mini/Micro LED芯片，现有的常规高压Mini/Micro LED芯片其内部包括两个以上的小发光单元(cell)，如图1所述的芯片截面图，各个cell之间通过桥接电极03连接在一起。由于芯片内部各个cell的面积较小，使得Mini/Micro LED芯片的散热路径变少，散热性能变 差。
更为糟糕的是，对于例如如图2所示的cell布局方式(cell以1*3形式串联而成)，以及如图3所示的cell布局方式(cell以1*4形式串联而成)，会存在一些cell完全架空在驱动基板02之上，Mini/Micro LED芯片01与驱动基板02焊接后，架空的cell与驱动基板02无接触，架空的cell无法得到支撑，使得Mini/Micro LED芯片不仅散热性能差，且机械强度也很差。
散热性能差和机械性能差对于Mini/Micro LED背光和显示相关产品来说是个致命的问题。如果Mini/Micro LED芯片的散热性能不佳，将使得Mini/Micro LED芯片在工作时所产生的热量在其内部聚集，会使得Mini/Micro LED芯片的结温升高。而结温升高，则会进一步带来Mini/Micro LED芯片发光效率降低、发光颜色发生红移、正向电压下降、寿命缩短等问题。如果Mini/Micro LED芯片的机械性能不佳，将使得Mini/Micro LED芯片容易断裂，从而导致Mini/Micro LED芯片失效。
基于上述现有技术，提出了本公开实施例的一种发光芯片及其制备方法、发光装置。
图4、图5和图6分别示出了本公开实施例的三种发光芯片1000的截面示意图，参照图4、图5和图6，该发光芯片1000包括：
图形化衬底10；
发光单元20，包括依次叠层形成在图形化衬底10上的电子注入层21、发光层22和空穴注入层23；
第一电极30和第二电极40，第一电极30与电子注入层21连接，第二电极40与空穴注入层23连接；
第一钝化层50，部分覆盖发光单元20、第一电极30和第二电极40，第一钝化层50包括第一开口51，发光单元20部分从第一开口51露出；
散热层60，覆盖第一钝化层50，以及发光单元20从第一钝化层50露出的部分。
其中，可选地，图形化衬底10可以是蓝宝石(Al 2O 3)材质，其上有间距为1～2μm的图形化结构，图形化结构可用于降低蓝宝石衬底的缺陷密度，提高晶体质量，从而提高发光芯片1000的出光效率。
参照图4、图5和图6，在一些实施例中，发光芯片1000具体还可以包括形成在图形化衬底10上的缓冲层70，通常可采用GaN材料制成，厚度可选为2μm作用，缓冲层70可用于改善蓝宝石衬底和GaN材料间的晶格常数失配。
电子注入层21可用于提供电子，可选地，电子注入层21可采用掺杂了Si的GaN制成，可作为发光单元20的N区，厚度可选为
Figure PCTCN2021127403-appb-000001
左右。
参照图4、图5和图6，在一些实施例中，发光芯片1000具体还可以包括形成在电子注入层21上的超晶格层80，在一可选实施例中，超晶格层80可以包括2nm的InGaN和25nm的GaN组成的势垒/势阱对，共计6组势垒/势阱对，总厚度可选为
Figure PCTCN2021127403-appb-000002
用于改善外延质量。
发光层22是发光芯片1000的发光区，可对载流子起约束作用。在一些实施例中，发光层22具体可以是多量子阱发光层，可包括3nm的InGaN和12nm的GaN组成的势垒/势阱对，共计9组势垒/势阱对，总厚度可选为
Figure PCTCN2021127403-appb-000003
参照图4、图5和图6，在一些实施例中，发光芯片1000具体还可以包括形成在发光层22上的电子阻挡层90，可用于阻挡电子泄露到发光单元20的P区，提高发光复合区中电子和空穴的复合率。可选地，电子阻挡层90可采用InGaN制成，厚度可选为
Figure PCTCN2021127403-appb-000004
空穴注入层23可用于提供空穴，可选地，空穴注入层23可采用掺杂了Mg的GaN制成，可作为发光单元20的P区，厚度可选为
Figure PCTCN2021127403-appb-000005
左右。
第一电极30可以与电子注入层21连接，从而作为发光芯片1000的N电极。第二电极40可以与空穴注入层23连接，从而作为发光芯片1000的P电极。
第一钝化层50可用于隔离发光芯片1000内部除导通位置之外的位置，以防止发光芯片1000短路。第一钝化层50上设置有第一开口51，发光单元20部分从第一开口51露出，第一开口51可为发光单元20留出散热通道。
参照图4、图5和图6，可选地，发光单元20还包括形成在空穴注入层23上的电流扩展层110，电流扩展层110部分从第一钝化层50的第一开口51露出。其中，发光单元20的电流扩展层110部分露出第一钝化层50，从而可使发光单元20与散热层60形成直接接触，形成散热通道，有利于发光单元20的热量导出。
散热层60可用于发散发光芯片1000内部的热量，加快PN结各个位置的热量传输到外界的速度。
在本公开实施例中，可以在发光芯片1000内部引入散热层60，增加了发光芯片1000内部热量的散热通道，从而将发光芯片1000内部的温度快速导出，提高了发光芯片1000的散热性能，降低了模组的整体温度。同时，散热层60可作为发光芯片1000内部的高强度填充层，从而可以提升发光芯片1000的机械强度。
参照图4、图5和图6，可选地，发光芯片1000还可以包括：
光学调整层120，至少部分覆盖散热层60；
焊盘130，包括第一焊盘131和第二焊盘132，第一焊盘131通过光学调整层120和散热层60上的过孔与露出第一钝化层50的第一电极30连接，第二焊盘132通过光学调整层120和散热层60上的过孔与露出第一钝化层50的第二电极40连接，散热层60具有绝缘性。
光学调整层120可用于使得发光层22出射的光更多地反射到蓝宝石衬底上，从而提高光的提取率。在一些实施例中，光学调整层120可以包括分布式布拉格反射镜结构，可选地，分布式布拉格反射镜结构具体可以是TiOx和SiOx膜层交替堆叠的结构，共48层，总厚度可选为3.5μm左右。
焊盘130可用于将发光芯片1000的电极连接至驱动基板上对应的信号连接端，其中，第一焊盘131与发光芯片1000的N电极连接，第二焊盘132与发光芯片1000的P电极连接。光学调整层120和散热层60上都设置有过孔，用于焊盘可通过过孔与相应电极连接。由于焊盘与相应电极都需要电导通，因此，散热层60需要具有绝缘性，从而可以避免发光芯片1000短路。
具体地，每个焊盘具体可以包括焊盘连接部和焊盘本体，其中，焊盘连接部为焊盘嵌入光学调整层120和散热层60上过孔的部分，焊盘本***于焊盘连接部远离图形化衬底10的一侧，焊盘本体覆盖光学调整层120靠近过孔的边缘。
参照图4、图5和图6，可选地，发光芯片1000还包括：
散热端部140，设置在光学调整层120上，光学调整层120上设置有露出散热层60的第二开口121，散热端部140通过第二开口121与散热层60连接。
其中，散热端部140伸出发光芯片1000外部，可用于增加发光芯片1000 的散热通道，将发光芯片1000内部的热量更快速地扩散到发光芯片1000外部，进一步提高了发光芯片1000的散热性能。
可选地，在一些实施例中，第一开口51在图形化衬底10上的正投影与散热端部140在图形化衬底10上的正投影存在交叠。
其中，在发光芯片1000的叠层方向上，第一开口51与散热端部140存在交叠，也即散热端部140可设置在发光单元20的散热通道上方，如此，可缩短发光单元20的热量传递路径，从而使得发光单元20的热量能够尽快散发至发光芯片1000外部。
在一些实施例中，参照图4和图5，可选地，在发光芯片1000的叠层方向上，散热端部140超出光学调整层120的部分的高度小于或等于焊盘130超出光学调整层120的部分的高度。
由于发光芯片1000可通过焊盘130与驱动基板焊接，因此，散热端部140的高度应不超过焊盘130超出光学调整层120的部分的高度，也即散热端部140的高度应不超过焊盘本体的高度，从而可以保证焊盘130与驱动基板的正常焊接。
在一些实施例中，参照图4，可选地，散热端部140具有翅片结构。如此，可以增加散热端部140的散热面积。
在一种可选的实现方式中，参照图5，散热端部140可以嵌入第二开口121中。
在另一种可选的实现方式中，参照图4，散热端部140可以覆盖光学调整层120靠近第二开口121的边缘。
相较于第二种实现方式，在第一种实现方式中，在散热端部140与散热层60采用同种材料的情况下，散热端部140和散热层60所需的工艺步骤较少，工艺相对简单。
相较于第一二种实现方式，在第二种实现方式中，光学调整层120的铺设面积更大，可使发光芯片1000的光提取率更高。
可选地，发光芯片1000包括沿目标方向排布，且通过桥接电极150串联的至少三个发光单元20，第一电极30和第二电极40分别与靠近发光芯片1000两端的发光单元20连接，散热端部140在图形化衬底10上的正投影与靠近发光芯片1000两端的发光单元之间的至少一个发光单元在图形化衬底10上 的正投影存在交叠。
其中，目标方向为预设方向，在实际应用中可根据需求预设。串联的所有发光单元20都沿着目标方向设置，第一电极30和第二电极40分别与串联首尾位置(或尾首位置)的发光单元20连接。在现有技术中，在发光芯片1000与驱动基板焊接的情况下，第一焊盘131可以对第一电极30所连接发光单元20进行支撑，第二焊盘132可以对第二电极40所连接发光单元20进行支撑，但是首尾发光单元20之间的发光单元20，将会架空在驱动基板上，驱动基板无法对中间位置的发光单元20形成支撑。而在本公开实施例中，散热端部140在图形化衬底10上的正投影与靠近发光芯片1000两端的发光单元20之间的发光单元20在图形化衬底10上的正投影存在交叠，也即是在发光芯片1000的叠层方向上，散热端部140与中间位置的发光芯片1000存在交叠，如此，散热端部140通过高度设计可以与驱动基板抵接，从而对中间位置的发光单元20形成支撑，提高了发光芯片1000的机械强度。
当然，对于包括一个或两个发光单元20的发光芯片1000，也可以在发光芯片1000上设置散热端部140。
参照图7，示例性的示出了几种发光单元20的排布俯视图，其中，在一些发光芯片中，每个发光单元20在图形化衬底10上的正投影与焊盘130在图形化衬底10上的正投影均存在交叠，这样的发光芯片即为无架空的发光单元20的发光芯片。无架空的发光单元20的发光芯片与驱动基板组装后，不存在发光单元20完全架空在驱动基板之上。可以理解的是，对于无架空的发光单元的发光芯片1000，例如图7中的(1)、(4)、(5)和(6)，可以选择不设置散热端部140，发光芯片1000的机械性能仍然可维持较好的水平。图7中的(2)和(3)所示的发光单元排布方式，则可以设置散热端部140，其中，图7的(2)和(3)中的虚线所圈出的发光单元20即为架空在驱动基板之上的发光单元。
在本公开实施例中，还可选地，在发光芯片1000的叠层方向上，散热层60的厚度最薄处大于或等于1.2μm，且小于或等于4微米。满足此厚度范围的散热层60，在起到散热作用的同时，还可作为桥接电极上方的高强度填充层，可以提高桥接位置的机械强度。
参照图4、图5和图6，还可选地，第一钝化层50可以包括：
图案化的第一钝化子层52，第一电极30与对应的发光单元20的电子注入层21通过第一钝化子层52上的过孔连接，第二电极40与对应的发光单元20的空穴注入层23通过第一钝化子层52上的过孔连接，桥接电极150设置在第一钝化子层52上，并通过第一钝化子层52上的过孔连接两个发光单元20；
图案化的第二钝化子层53，覆盖桥接电极150，第一开口51设置在第二钝化子层53上。
参照图4、图5和图6，桥接电极150设置在第一钝化子层52上，第一钝化子层52可用于将桥接电极150与发光单元20中可导电的膜层进行隔离，只保留发光单元20上需要与电极导通的位置。第二钝化子层53可用于隔离散热层60与桥接电极150，从而防止发光芯片1000短路。
其中，第二钝化子层53的厚度可选为
Figure PCTCN2021127403-appb-000006
左右，整个第一钝化层50的厚度可以在
Figure PCTCN2021127403-appb-000007
左右。
参照图4、图5和图6，可选地，发光芯片1000还可以包括：
第二钝化层160，设置在光学调整层120和散热层60上焊盘130所在的过孔的侧壁上。
在一些实施例中，可以在光学调整层120和散热层60上焊盘130所在的过孔的侧壁上设置第二钝化层160，第二钝化层160可用于隔离焊盘连接部与过孔，从而使得散热层60与焊盘130、第一电极30、第二电极40之间不会形成直接接触，可避免发光单元20通过散热层60漏电，防止发光芯片1000短路。
可选地，在实际应用中，散热端部140的材料可以采用氮化铝(AlN)和碳化硅(SiC)中的至少一种，散热层60的材料也可以采用氮化铝和碳化硅中的至少一种。
AlN具备高达240W/(M·K)超高热导率、3.3～5.0(×10 -6/℃)的热膨胀系数，与发光芯片1000的热膨胀系数非常匹配，同时AlN熔点为2470℃，非常耐高温，且具备良好的绝缘性能、超高的强度性能和超高的耐腐蚀性能。
虽然AlN具备良好的绝缘性能，但因其与发光芯片1000内部具备电性导通的几乎所有膜层存在接触，因此，为了防止发光芯片1000出现漏电，可在 AlN导热层下方、焊盘周边都增加钝化层，以强化发光芯片1000的电学性能。所增加的钝化层也使得不仅AlN可以作为散热膜层，SiC、BeO等绝缘性不如AlN的材料也可以作为散热膜层，增加到发光芯片1000内部从而用于增加芯片的散热性能。若采用SiC，则需要制作较为致密的钝化层，以降低发光芯片1000的短路风险。而BeO则可依法在发光芯片1000产品中进行使用。
除上文一些膜层的示例性材料和厚度之外，以下再示例性地给出另一些膜层的材料及厚度。
钝化层均可以采用SiO2制成。桥接电极150、第一电极30和第二电极40，其结构均可为Ti/Al/Ti/Ni/Ti/Al/Ti/Pt/Au构成的金属叠层结构。其中，第一电极30和第二电极40的厚度可选为1.47μm左右，各金属层的厚度分别约为5/12/88/42/316/103/627/97/182nm。桥接电极150的厚度可选为1.45μm左右，各金属层的厚度分别约为3/5/86/42/312/98/623/93/189nm。电流扩展层110可采用ITO材料，厚度可选为
Figure PCTCN2021127403-appb-000008
左右。焊盘连接部的结构可为Ti/Al/Ti/Pt、Au合金/Ni/Pt、Au合金构成的金属叠层结构，各金属层厚度分别为94/206/92/63/328/58nm。焊盘本体可采用的材料为Sn、Ag、Cu合金，各材料比例可为Sn-96.5％、Ag-3％、Cu-0.5％，焊盘本体的厚度可为8±0.8μm。
在现有技术中，通过变更基板材料(例如基板采用散热性能较好的陶瓷材料)或LED支架材料的散热方式，仅适用于POG封装形式的Mini/Micro LED产品，而不适用于COB和COG封装形式的Mini/Micro LED产品，这主要是因为COB和COG封装形式的基板材质固定，COB使用PCB或FPC基板，COG使用玻璃基板，散热性能趋于饱和，基本无改善空间，且无LED支架。目前，COB和COG的散热主要是通过增加温度传感器，在Mini/Micro LED面板达到预设温度后，通过强行降低电流，牺牲亮度和光学效果的手段降低热量。与上述现有技术相比，本公开实施例提供的发光芯片，无需增加任何外加器件，不需牺牲光学效果，便可达到很好的散热效果。
在本公开实施例中，可以在发光芯片1000内部引入散热层60，以及在发光芯片1000外部增加散热端部140。散热层60可以通过热传导方式对发光芯片1000内部的热量进行发散，另外，散热层60还可以提高发光单元20桥接位置的机械强度。散热端部140可以通过热辐射方式将发光芯片1000内部的热量传导至发光芯片1000外部，另外，散热端部140还可以对架空的发光单 元起到支撑作用。如此，使得发光芯片1000的散热性能和机械性能都得到了提高。
参照图8，示出了本公开实施例的一种发光芯片1000的制备方法的步骤流程图，该制备方法用于制备上述发光芯片1000，该制备方法包括以下步骤：
步骤801：在图形化衬底上依次叠层形成电子注入层、发光层和空穴注入层，以得到发光单元。
在本步骤中，首先可以通过例如MOCVD(Metalorganic Chemical Vapor Deposition，金属有机化学气相沉积)工艺在PSS衬底上顺次生长缓冲层70、电子注入层21、超晶格层80、发光层22、电子阻挡层90、空穴注入层23和电流扩展层110，之后，通过例如光刻、刻蚀等工艺进行过孔以及厚度较大位置的隔离槽刻蚀，从而得到发光单元20，如图9所示。
步骤802：图案化形成第一钝化层、第一电极和第二电极；第一电极与电子注入层连接，第二电极与空穴注入层连接，第一钝化层部分覆盖发光单元、第一电极和第二电极，第一钝化层包括第一开口，发光单元部分从第一开口露出。
参照图10，图案化形成第一钝化子层52，并露出需要的位置。
参照图11，图案化形成第一电极30、第二电极40和桥接电极150。
参照图12，图案化形成第二钝化子层53，并露出需要的位置，得到第一钝化层50。
步骤803：形成散热层；散热层覆盖第一钝化层，以及发光单元从第一钝化层露出的部分。
在一种可选的实施方式中，形成散热层之后，还包括：
形成光学调整层；光学调整层上设置有露出散热层的第二开口，散热层包括嵌入第二开口中的部分；
在光学调整层上形成散热端部；散热端部覆盖光学调整层靠近第二开口的边缘，散热端部与散热层嵌入第二开口中的部分连接。
其中，参照图13至16，在一些实施例中，参照图13，依次形成散热材料层以及光学调整材料层，再图案化形成散热层60和光学调整层120，其中，散热层60包括嵌入第二开口121中的部分。参照图14，在需要设置焊盘连接 部的过孔侧壁上形成第二钝化层160。参照图15，形成焊盘连接部。参照图16，形成焊盘本体。
之后，可以在光学调整层120上形成散热端部140，其中，散热端部140与散热层60嵌入第二开口121中的部分连接，得到如图4所示的发光芯片1000。
在另一种可选的实施方式中，形成散热层之后，还包括：
形成光学调整层；光学调整层上设置有露出散热层的第二开口；
在从第二开口露出的散热层上形成散热端部。
其中，参照图17，在一些实施例中，形成散热层60、光学调整层120、第二钝化层160、焊盘连接部和焊盘本体的过程与上述实施例基本相同，不同的是，散热层60不包括嵌入第二开口121中的部分。
之后，可以在从第二开口121露出的散热层60上形成散热端部140，其中，散热端部140位于第二开口121中，得到如图5所示的发光芯片1000。
此外，参照图18，在另一些实施例中，形成散热层60、光学调整层120、第二钝化层160、焊盘连接部和焊盘本体的过程与上述实施例基本相同，不同的是，光学调整层120不包括开口121。之后，也不再形成散热端部140，从而可以得到如图6所示的发光芯片1000。
可选地，在光学调整层上形成散热端部之后，还可以包括以下步骤：对散热端部140激光刻蚀，以在散热端部140上形成翅片结构。如此，可以增加散热端部140的散热面积。
制成发光芯片1000后，参照图19，可以通过研磨将蓝宝石衬底的厚度减薄，进而参照图20，将整片晶片镭射切割为单一晶粒。然后，可以对晶粒进行光电特性测试、按照规格分类，以及人工目检。其中，参照图21，光电特性测试也即通过点测设备对每个晶粒进行光电特性的测试，参照图22，按照规格分类也即根据晶粒的光电参数，将晶粒分类为不同的规格，参照图23，人工目检也即人工去除外观不良的晶粒。
此外，该制备方法还可以包括其他的常规步骤，本公开实施例对此不作具体限定。
在本公开实施例中，可以在发光芯片1000内部形成散热层60，增加了发光芯片1000内部热量的散热通道，从而将发光芯片1000内部的温度快速导 出，提高了发光芯片1000的散热性能，降低了显示装置的整体温度。同时，散热层60可作为发光芯片1000内部的高强度填充层，从而可以提升发光芯片1000的机械强度。
本公开实施例还公开了一种发光装置，包括上述发光芯片1000。
其中，参照图24和图25，发光装置还包括驱动基板2000，驱动基板2000包括第一连接端2001和第二连接端2002，发光芯片1000包括第一焊盘131和第二焊盘132，第一焊盘131与第一连接端2001连接，第二焊盘132与第二连接端2002连接。其中，第一连接端2001和第二连接端2002具体可以是焊盘。
驱动基板2000可以包括两种，一种是如图24所示的封闭式连接端的驱动基板，另一种是如图25所示的开放式连接端的驱动基板。
对于图24所示的封闭式连接端的驱动基板，驱动基板2000还包括位于第一连接端2001与第二连接端2002之间的封闭结构2003，封闭结构2003用于封闭驱动基板2000上从第一连接端2001与第二连接端2002之间露出的膜层。
而对于图25所示的开放式连接端的驱动基板，第一连接端2001与第二连接端2002之间不存在封闭结构2003。
对于图24所示的封闭式连接端的驱动基板，在发光芯片1000包括散热端部140的情况下，散热端部140可以与封闭结构2003抵接。
对于图25所示的开放式连接端的驱动基板，在发光芯片1000包括散热端部140的情况下，散热端部140可以与从第一连接端2001与第二连接端2002之间露出的膜层适当保留一些距离。
当然，对于不包括散热端部140的发光芯片1000，也可以搭配封闭式连接端的驱动基板和开放式连接端的驱动基板，从而形成发光装置。
在本公开实施例中，可以在发光芯片1000内部形成散热层60，增加了发光芯片1000内部热量的散热通道，从而将发光芯片1000内部的温度快速导出，提高了发光芯片1000的散热性能，降低了显示装置的整体温度。同时，散热层60可作为发光芯片1000内部的高强度填充层，从而可以提升发光芯片1000的机械强度。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本公开的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本公开的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本公开可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
最后应说明的是：以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。

Claims (20)

  1. 一种发光芯片，其特征在于，包括：
    图形化衬底；
    发光单元，包括依次叠层形成在所述图形化衬底上的电子注入层、发光层和空穴注入层；
    第一电极和第二电极，所述第一电极与所述电子注入层连接，所述第二电极与所述空穴注入层连接；
    第一钝化层，部分覆盖所述发光单元、所述第一电极和所述第二电极，所述第一钝化层包括第一开口，所述发光单元部分从所述第一开口露出；
    散热层，覆盖所述第一钝化层，以及所述发光单元从所述第一钝化层露出的部分。
  2. 根据权利要求1所述的发光芯片，其特征在于，所述发光单元还包括形成在所述空穴注入层上的电流扩展层，所述电流扩展层部分从所述第一钝化层的所述第一开口露出。
  3. 根据权利要求1所述的发光芯片，其特征在于，所述发光芯片还包括：
    光学调整层，至少部分覆盖所述散热层；
    焊盘，包括第一焊盘和第二焊盘，所述第一焊盘通过所述光学调整层和所述散热层上的过孔与露出所述第一钝化层的所述第一电极连接，所述第二焊盘通过所述光学调整层和所述散热层上的过孔与露出所述第一钝化层的所述第二电极连接，所述散热层具有绝缘性。
  4. 根据权利要求3所述的发光芯片，其特征在于，所述发光芯片还包括：
    散热端部，设置在所述光学调整层上，所述光学调整层上设置有露出所述散热层的第二开口，所述散热端部通过所述第二开口与所述散热层连接。
  5. 根据权利要求4所述的发光芯片，其特征在于，所述第一开口在所述图形化衬底上的正投影与所述散热端部在所述图形化衬底上的正投影存在交叠。
  6. 根据权利要求4所述的发光芯片，其特征在于，在所述发光芯片的叠层方向上，所述散热端部超出所述光学调整层的部分的高度小于或等于所述焊盘超出所述光学调整层的部分的高度。
  7. 根据权利要求4所述的发光芯片，其特征在于，所述散热端部具有翅 片结构。
  8. 根据权利要求4所述的发光芯片，其特征在于，所述散热端部嵌入所述第二开口中。
  9. 根据权利要求4所述的发光芯片，其特征在于，所述散热端部覆盖所述光学调整层靠近所述第二开口的边缘。
  10. 根据权利要求4所述的发光芯片，其特征在于，所述散热端部的材料采用氮化铝和碳化硅中的至少一种，所述散热层的材料采用氮化铝和碳化硅中的至少一种。
  11. 根据权利要求4所述的发光芯片，其特征在于，所述发光芯片包括沿目标方向排布，且通过桥接电极串联的至少三个所述发光单元，所述第一电极和所述第二电极分别与靠近所述发光芯片两端的所述发光单元连接，所述散热端部在所述图形化衬底上的正投影与靠近所述发光芯片两端的所述发光单元之间的所述发光单元在所述图形化衬底上的正投影存在交叠。
  12. 根据权利要求11所述的发光芯片，其特征在于，所述第一钝化层包括：
    图案化的第一钝化子层，所述第一电极与对应的所述发光单元的电子注入层通过所述第一钝化子层上的过孔连接，所述第二电极与对应的所述发光单元的空穴注入层通过所述第一钝化子层上的过孔连接，所述桥接电极设置在所述第一钝化子层上，并通过所述第一钝化子层上的过孔连接两个所述发光单元；
    图案化的第二钝化子层，覆盖所述桥接电极，所述第一开口设置在所述第二钝化子层。
  13. 根据权利要求3所述的发光芯片，其特征在于，所述发光芯片还包括：
    第二钝化层，设置在所述光学调整层和所述散热层上所述焊盘所在的过孔的侧壁上。
  14. 根据权利要求1所述的发光芯片，其特征在于，在所述发光芯片的叠层方向上，所述散热层的厚度最薄处大于或等于1.2μm，且小于或等于4微米。
  15. 一种发光芯片的制备方法，其特征在于，所述方法包括：
    在图形化衬底上依次叠层形成电子注入层、发光层和空穴注入层，以得到发光单元；
    图案化形成第一钝化层、第一电极和第二电极；所述第一电极与所述电子注入层连接，所述第二电极与所述空穴注入层连接，第一钝化层部分覆盖所述发光单元、所述第一电极和所述第二电极，所述第一钝化层包括第一开口，所述发光单元部分从所述第一开口露出；
    形成散热层；所述散热层覆盖所述第一钝化层，以及所述发光单元从所述第一钝化层露出的部分。
  16. 根据权利要求15所述的方法，其特征在于，所述形成散热层之后，还包括：
    形成光学调整层；所述光学调整层上设置有露出所述散热层的第二开口；
    在从所述第二开口露出的所述散热层上形成散热端部。
  17. 根据权利要求15所述的方法，其特征在于，所述形成散热层之后，还包括：
    形成光学调整层；所述光学调整层上设置有露出所述散热层的第二开口，所述散热层包括嵌入所述第二开口中的部分；
    在所述光学调整层上形成散热端部；所述散热端部覆盖所述光学调整层靠近所述第二开口的边缘，所述散热端部与所述散热层嵌入所述第二开口中的部分连接。
  18. 根据权利要求16-17任一项所述的方法，其特征在于，所述在所述光学调整层上形成散热端部之后，还包括：
    对所述散热端部激光刻蚀，以在所述散热端部上形成翅片结构。
  19. 一种发光装置，其特征在于，包括权利要求1-14任一项所述的发光芯片。
  20. 根据权利要求19所述的发光装置，其特征在于，所述发光装置还包括驱动基板，所述驱动基板包括第一连接端和第二连接端，所述发光芯片包括第一焊盘和第二焊盘，所述第一焊盘与所述第一连接端连接，所述第二焊盘与所述第二连接端连接，所述驱动基板还包括位于所述第一连接端与所述 第二连接端之间的封闭结构，所述封闭结构用于封闭所述驱动基板上从所述第一连接端与所述第二连接端之间露出的膜层，所述发光芯片包括散热端部，所述散热端部与所述封闭结构抵接。
PCT/CN2021/127403 2021-10-29 2021-10-29 一种发光芯片及其制备方法、发光装置 WO2023070520A1 (zh)

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