WO2023070489A1 - 显示面板母板、显示面板和显示装置 - Google Patents

显示面板母板、显示面板和显示装置 Download PDF

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Publication number
WO2023070489A1
WO2023070489A1 PCT/CN2021/127263 CN2021127263W WO2023070489A1 WO 2023070489 A1 WO2023070489 A1 WO 2023070489A1 CN 2021127263 W CN2021127263 W CN 2021127263W WO 2023070489 A1 WO2023070489 A1 WO 2023070489A1
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Prior art keywords
layer
area
base substrate
display panel
partition
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PCT/CN2021/127263
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English (en)
French (fr)
Inventor
高昕伟
李朋
张帅
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180003160.XA priority Critical patent/CN116584175A/zh
Priority to PCT/CN2021/127263 priority patent/WO2023070489A1/zh
Publication of WO2023070489A1 publication Critical patent/WO2023070489A1/zh

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  • the present disclosure relates to the field of display technology, in particular to a display panel motherboard, a display panel and a display device.
  • Special-shaped display screen is a special-shaped display screen transformed on the basis of traditional display screens, so that the characteristics of the display screen can better meet customer needs.
  • the present disclosure provides a display panel motherboard, a display panel and a display device.
  • a display panel motherboard has a first panel area and a binding area located on one side of the first panel area, wherein the first The panel area has: a reserved area and a peripheral area located outside the reserved area;
  • the display panel motherboard includes: a base substrate, a cover plate arranged opposite to the base substrate, and a cover plate arranged between the base substrate and the base substrate.
  • the first light-emitting functional layer is located in the first panel region
  • the first adhesive layer surrounds the first panel area and is bonded to the cover plate and the base substrate, and the edge of the first adhesive layer on the side close to the binding area is on the an orthographic projection on the substrate substrate defines a first pattern;
  • the first blocking layer is located at the edge of the reserved area and separates the first light-emitting functional layer in the reserved area from the first light-emitting functional layer in the peripheral area.
  • the orthographic projection on the base substrate partially overlaps with the first pattern, and forms a second pattern with the first pattern; wherein, the second pattern is a closed pattern, and the first partition layer is in the The orthographic projection on the base substrate is within the range of the pattern defined by the orthographic projection of the first adhesive layer on the base substrate.
  • the reserved area includes a display area
  • the first partition layer includes a first partition part and a second partition part, the first partition part is arranged along the edge of the display area, and the first end of the second partition part is connected to the first partition part , the orthographic projection of the second end of the second partition portion on the base substrate partially overlaps with the first pattern;
  • the second end of the second partition part is located between the first bonding layer and the base substrate.
  • the reserved area further includes a routing area arranged on a side of the display area close to the binding area
  • the motherboard of the display panel further includes a plurality of pixel units and connecting signal lines, so The plurality of pixel units are located in the display area, the first end of the connection signal line is connected to the pixel unit, and the other end of the connection signal line passes through the wiring area and the binding area. binding end connection;
  • the second partition part is located on the first side and the second side of the wiring area, and the first side and the second side of the wiring area are arranged along a first direction, and the first direction is consistent with that from the display Regions cross in the direction of the binding region.
  • the orthographic projection of the second end of the second partition on the base substrate is the same as that of the first pattern
  • the size of the overlapping portion is greater than or equal to 45 ⁇ m.
  • the edge of the first adhesive layer close to the binding area is a first edge
  • the first adhesive layer further includes a second edge opposite to the first edge and a third edge located between the first edge and the second edge
  • the orthographic projection of the first partition layer on the base substrate is the same as that of the second edge on the base substrate Neither the orthographic projection nor the orthographic projection of the third edge on the base substrate overlaps.
  • the display panel motherboard further includes a second partition layer disposed on the same layer as the first partition layer, and the second partition layer includes a third partition part and a The fourth partition part on the side away from the display area, the third partition part is located in the peripheral area, the orthographic projection of the fourth partition part on the base substrate is the same as that of the second edge at the The orthographic projection on the base substrate and the orthographic projection of the third edge on the base substrate are overlapped, and the fourth partition is located between the base substrate and the first bonding between layers.
  • the first partition layer is strip-shaped, and the first partition layer includes at least one strip-shaped portion, and each strip-shaped portion includes a first portion close to the side of the cover plate, a a second portion on one side of the base substrate and a third portion located between the first portion and the second portion;
  • the cross-sectional area of the first portion is larger than the cross-sectional area of the third portion.
  • the cross-sectional area of the second portion is larger than the cross-sectional area of the third portion; or,
  • the cross-sectional area of the second portion is smaller than the cross-sectional area of the third portion.
  • each of the strip-shaped parts includes a first strip-shaped sub-section and a second strip-shaped sub-section abutting against the first strip-shaped sub-section, and the first strip-shaped sub-section and the second strip-shaped sub-section Two strip-shaped sub-parts are arranged along the width direction of the first partition layer;
  • the second strip-shaped sub-portion protrudes from the surface of the first strip-shaped sub-portion away from the base substrate.
  • the cross-sectional area of the first strip-shaped sub-portion gradually increases, and the cross-sectional area of the second strip-shaped sub-portion gradually decreases.
  • the number of the strip-shaped portions is multiple, the plurality of strip-shaped portions are arranged at intervals from each other, and the plurality of strip-shaped portions are arranged along the width direction of the first partition layer.
  • the display panel motherboard further includes: a third partition layer disposed on the same layer as the first partition layer, the third partition layer is located in the peripheral area, and the third partition layer
  • the layer includes a plurality of fifth partitions, and the plurality of fifth partitions are nested and arranged at intervals.
  • each of the fifth partitions includes a plurality of partition subsections, and the plurality of partition subsections are arranged at intervals from each other; or,
  • the orthographic projection of each of the fifth partitions on the base substrate is a continuous figure.
  • the display panel motherboard further includes a pixel circuit layer and a pixel definition layer disposed on the side of the first light-emitting functional layer close to the base substrate, and the pixel definition layer is located on the second Between a light-emitting functional layer and the pixel circuit layer;
  • the first partition layer is set on the same layer as the pixel defining layer; or,
  • the first isolation layer is set on the same layer as one of the metal film layers in the pixel circuit layer.
  • the distance between the outer edge of the orthographic projection of the first partition layer on the base substrate and the orthographic projection of the display area on the base substrate is greater than or equal to 850 ⁇ m.
  • the first light emitting functional layer includes a first light emitting functional sublayer located in the reserved area, a second light emitting functional sublayer located in the peripheral area, and a sublayer located in the reserved area and the peripheral area. a third light-emitting functional sublayer between the regions;
  • the third luminescent functional sublayer is located on the side of the first partition layer away from the base substrate, the first luminescent functional sublayer, the second luminescent functional sublayer and the third luminescent functional sublayer The functional sublayers are spaced apart from each other.
  • the display panel motherboard further includes: a first electrode disposed on a side of the first light-emitting functional layer away from the base substrate, and a first electrode disposed on a side of the first electrode away from the substrate. a planar layer on one side of the substrate, both the first electrode and the planar layer are located in the first panel region;
  • the first electrode in the reserved region and the first electrode in the peripheral region are separated by the first partition layer, the planar layer in the reserved region and the peripheral region
  • the planar layers are spaced apart by the first barrier layers.
  • the display panel motherboard further includes a first encapsulation layer disposed on a side of the planar layer away from the base substrate, and the first encapsulation layer extends continuously from the reserved area. to the peripheral area.
  • the display panel motherboard further includes a second adhesive layer disposed between the cover plate and the first encapsulation layer, the second adhesive layer is located on the first panel in the district.
  • the reserved area includes a display area and a wiring area arranged on a side of the display area close to the binding area;
  • the display panel motherboard also includes a plurality of pixel units and connection signal lines, the pixel units are located in the display area, the first ends of the connection signal lines are connected to the pixel units, and the connection signal lines The second end is connected to the binding end in the binding area through the wiring area;
  • the first bonding layer is also bonded to the connection signal line.
  • a second aspect of the present disclosure provides a display panel, wherein the display panel has a second panel area and a binding area located on one side of the second panel area;
  • the display panel includes: a base substrate, a cover plate opposite to the base substrate, a second light-emitting functional layer disposed between the base substrate and the cover plate, a second isolation layer and a third bonding layer. layer;
  • the third adhesive layer is located between the second panel area and the binding area, and is bonded with the cover plate and the base substrate, and the second light-emitting functional layer is located in the In the second panel area, the second partition layer is located at the edge of the second panel area, and the orthographic projection of the second partition layer on the base substrate is the same as that of the third adhesive layer on the
  • the orthographic projections on the base substrate overlap and can form a third pattern, wherein the third pattern is a closed pattern, and the orthographic projection of the second partition layer on the base substrate does not exceed the first pattern.
  • the orthographic projections of the three adhesive layers on the base substrate are away from the edge of one side of the orthographic projection of the second panel area on the base substrate.
  • the second panel area includes a display area
  • the second partition layer includes a sixth partition part and a seventh partition part, the sixth partition part is arranged along the edge of the display area, and the first end of the seventh partition part is connected to the sixth partition part , the orthographic projection of the second end of the seventh partition portion on the base substrate partly overlaps the orthographic projection of the third adhesive layer on the base substrate;
  • the second end of the seventh partition part is located between the third adhesive layer and the base substrate.
  • the second panel area further includes a routing area disposed on a side of the display area close to the binding area
  • the display panel further includes a plurality of pixel units and connecting signal lines, so The plurality of pixel units are located in the display area, the first end of the connection signal line is connected to the pixel unit, and the other end of the connection signal line passes through the wiring area and the binding area. binding end connection;
  • the seventh partition part is located on the first side and the second side of the routing area, and the first side and the second side of the routing area are arranged along a first direction, and the first direction is consistent with that from the display Regions cross in the direction of the binding region.
  • the display panel further includes:
  • the second light-emitting functional layer in the panel is spaced apart from the outside.
  • a third aspect of the present disclosure provides a display device, including: the above-mentioned display panel.
  • Figure 1a schematically shows a plan view of a display panel motherboard in a scale
  • Figure 1b schematically shows a cross-sectional view of Figure 1a along the section line BB';
  • FIG. 2a to 2c schematically illustrate plan views of a motherboard of a display panel according to an embodiment of the present disclosure
  • Figure 3a schematically shows a cross-sectional view of Figure 2c along section line CC';
  • Figure 3b schematically shows an enlarged view at position C in Figure 2c;
  • Fig. 4a schematically shows a plan view of a first panel area according to an embodiment of the present disclosure
  • Figure 4b schematically shows one of the cross-sectional views of Figure 4a along the section line DD';
  • Figure 4c schematically shows one of the enlarged views of position D in Figure 4a;
  • Fig. 5 schematically shows a cross-sectional view of Fig. 4c along section line EE';
  • Figure 6 schematically shows the second enlarged view of position D in Figure 4a;
  • Fig. 7 schematically shows the second cross-sectional view of Fig. 4a along the section line DD';
  • Fig. 8 schematically shows a schematic diagram of a first strip-shaped subsection and a second strip-shaped subsection according to an embodiment of the present disclosure
  • Fig. 9 schematically shows a schematic view in another first panel area according to an embodiment of the present disclosure.
  • Figure 10 schematically shows a cross-sectional view of Figure 9 along the section line FF';
  • FIG. 11a and Fig. 11b schematically show schematic diagrams in another first panel area according to an embodiment of the present disclosure
  • Figure 12 schematically shows a cross-sectional view of Figures 11a and 11b along the section line GG';
  • Fig. 13a schematically shows one of the schematic diagrams of a display panel according to an embodiment of the present disclosure
  • Fig. 13b schematically shows the second schematic diagram of a display panel according to an embodiment of the present disclosure
  • Figure 14a schematically shows a cross-sectional view of Figure 13b along the section line HH';
  • FIG. 14b schematically shows a cross-sectional view of FIG. 13b along the section line II'.
  • connection may refer to a physical connection, an electrical connection, a communicative connection, and/or a fluid connection.
  • the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system, and may be interpreted in a wider sense.
  • the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.
  • X, Y, and Z and "at least one selected from the group consisting of X, Y, and Z” may be interpreted as meaning only X, only Y, only Z, or Any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ.
  • the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • first means for describing various components, components, elements, regions, layers and/or sections
  • these components, components, elements, regions, layers and/or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, component, element, region, layer and/or section from another.
  • a first component, first member, first element, first region, first layer, and/or first portion discussed below could be termed a second component, second member, second element, second region , the second layer and/or the second portion, without departing from the teachings of the present disclosure.
  • spatially relative terms such as “upper,” “lower,” “left,” “right,” etc. may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. relation. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” or “above” the other elements or features.
  • the expression “thickness” refers to the dimension along the surface perpendicular to the display substrate on which each film layer is provided, that is, the dimension along the light emitting direction of the display substrate.
  • patterning process generally includes steps such as photoresist coating, exposure, development, etching, and photoresist stripping.
  • one patterning process means a process of forming patterned layers, components, members, etc. using one mask.
  • the expressions “same layer”, “set in the same layer” or similar expressions refer to the use of the same film forming process to form a film layer for forming a specific pattern, and then use the same mask to pass a patterning process on the film.
  • Layer structure formed by layer patterning may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific graphics may also be at different heights or have different thicknesses.
  • the expression “electrically connected” may mean that two components or elements are directly electrically connected, for example, component or element A is in direct contact with component or element B, and electrical signals may be transmitted between the two; It can mean that two components or elements are electrically connected through a conductive medium such as a conductive wire, for example, a component or element A is electrically connected with a component or element B through a conductive wire, so as to transmit electrical signals between the two parts or elements; it can also represent Two components or elements are electrically connected through at least one electronic component, for example, component or element A is electrically connected to component or element B through at least one thin film transistor, so as to transmit electrical signals between the two components or elements.
  • Figure 1a schematically shows a plan view of a pair of display panel motherboards in the ratio
  • Figure 1b schematically shows a cross-sectional view of Figure 1a along section line BB'
  • the display panel motherboard includes opposite The cover plate 11 and the array substrate 12 are provided.
  • the array substrate 12 may include a base substrate 121 , and a pixel circuit layer 122 , a light emitting layer 123 , and an encapsulation layer 124 arranged in sequence along a direction away from the base substrate 121 .
  • the display panel motherboard is divided into a plurality of first panel areas 13 , and the first panel areas 13 include a special-shaped display area 131 and a peripheral area 132 outside the special-shaped display area 131 .
  • the shape of the special-shaped display area 131 is different from that of the regular display area.
  • the more common regular display area is generally rectangular, while the special-shaped display area 131 refers to a non-rectangular display area, for example, A "heart-shaped" display area or a "circular” display area, etc.
  • the display panel motherboard can be roughly cut along the first panel area 13 to obtain an initial display panel, and then finely cut along the special-shaped display area 131 to obtain a special-shaped display panel. display panel.
  • the light emitting layer 123 is usually formed by evaporation process, and the encapsulation layer 124 is formed by chemical vapor deposition (CVD) or inkjet printing (IJP).
  • CVD chemical vapor deposition
  • IJP inkjet printing
  • the shape of the special-shaped display area 131 is relatively special, and the pattern of the mask plate used in the above process is usually rectangular, therefore, It is difficult to accurately form the light emitting layer 123 and the encapsulation layer 124 in the special-shaped display area 131 through the above process.
  • the light-emitting layer 123 is also formed outside the special-shaped display region 131 (that is, in the peripheral region 132). and encapsulation layer 124 .
  • the inventors have found through research that the motherboard of the display panel prepared in the above manner is prone to packaging failure during cutting.
  • the cover plate 11 and the array substrate 12 of the motherboard of the display panel are generally bonded together by an adhesive 14.
  • the adhesive 14 actually bonds the encapsulation layer 124 in the array substrate 12 and the cover plate 11 together, due to the adhesion between the encapsulation layer 124 and the base substrate 121 The adhesion is low, and the encapsulation layer 124 is easily separated from the base substrate 121 during cutting.
  • the encapsulation layer 124 is separated from the base substrate 121, it will directly cause the cover plate 11 to be separated from the array substrate 12. will cause package failure.
  • the luminescent layer 123 has a certain degree of water absorption. When the luminescent layer 123 is located in the peripheral region 132 , the luminescent layer 123 will become a medium for the intrusion of water and oxygen, which will also cause packaging failure.
  • FIG. 2a to FIG. 2c schematically show plan views of a display panel motherboard according to an embodiment of the present disclosure, and FIG. For the cross-sectional view of line CC', the first light-emitting functional layer is hidden in Fig. 2a to Fig. 2c for clarity.
  • the motherboard of the display panel has the first panel area P and the first panel area The binding area B on one side of P, wherein the first panel area P has: a reserved area S and a peripheral area W outside the reserved area S.
  • the display panel motherboard includes: a base substrate 1, a cover plate 2 disposed opposite to the base substrate 1, a first light-emitting functional layer EL disposed between the base substrate 1 and the cover plate 2, a first adhesive layer Dam and The first barrier layer Rib1.
  • the material of base substrate 1 and cover plate 2 can comprise flexible material or rigid material, for example, when the material of base substrate 1 is flexible material, flexible material can comprise polyimide etc.; When the material of base substrate 1 is When a rigid material is used, the rigid material may include glass or the like.
  • the first light-emitting functional layer EL can be an organic electroluminescent functional layer, and the first light-emitting functional layer EL can be a multilayer structure.
  • the first light-emitting functional layer EL can include a hole injection layer, a hole transport layer, an organic light-emitting layer , electron transport layer and electron injection layer to form a multi-layer structure.
  • the first light emitting functional layer EL is located in the first panel area P, for example, the first light emitting functional layer EL is located in the reserved area S and the peripheral area W.
  • the first adhesive layer Dam surrounds the first panel area P and is bonded to the cover plate 2 and the base substrate 1, and the edge (first edge D1) of the first adhesive layer Dam near the bonding area B is on the substrate
  • the orthographic projection on the substrate 1 defines a first pattern, for example, the first pattern may be a straight line.
  • the first blocking layer Rib1 is located at the edge of the reserved area S and separates the first light-emitting functional layer EL in the reserved area S from the first light-emitting functional layer EL in the peripheral area W, and the first blocking layer Rib1 is on the base substrate 1
  • the orthographic projection of is partially overlapped with the first pattern, and forms a second pattern with the first pattern.
  • the second pattern is a closed pattern, so that the first isolation layer Rib1 can surround the edge of the reserved area S, thereby separating the first light-emitting functional layer EL in the reserved area S from the first light-emitting functional layer EL in the peripheral area W.
  • the functional layers EL are all spaced apart, so as to cut off the moisture intrusion path formed by the extension of the first light-emitting functional layer EL into the peripheral region W.
  • the motherboard of the display panel may have a plurality of first panel regions P, and the plurality of first panel regions P may be arranged in an array, and one side of each first panel region P is provided with a A panel region P corresponds to the binding region B.
  • which side of the first panel area P the binding area B is specifically set on can be determined according to actual needs, and is not limited here.
  • the binding area B is located on the first panel Above the area P, for another example, as shown in FIG. 2c, the binding area B is located below the area P of the first panel.
  • the connecting signal lines extending from the first panel area P can be connected to the driving chip through the bonding area B, so that the light emitting devices in the first panel area can display under the driving of the driving chip.
  • the area defined by the first panel area P and the binding area B is the part that needs to be kept after the rough cutting of the motherboard of the display panel, and the area defined by the peripheral area W is the part for the display panel.
  • the reserved area S is a special-shaped area (that is, a non-rectangular area), for example, as shown in Figure 2a and Figure 2b, the reserved area S can be a similar "heart-shaped" area, or, as shown in Figure 2c,
  • the reserved area S is an area like a "circle” or the like.
  • the first bonding layer Dam may be dam glue, which may have certain water resistance.
  • the first adhesive layer Dam surrounds the first panel area P, and the shape of the first panel area P can be determined according to actual needs, and is not limited here.
  • the first panel area P can be square, and the first panel area P is arranged around
  • the first bonding layer Dam may be a square ring structure.
  • the first adhesive layer Dam can be directly bonded to the base substrate 1 and the cover plate 2, so that when the display panel motherboard When cutting, the adhesive glue can firmly bond the base substrate 1 and the cover plate 2 together without problems such as separation or displacement.
  • the first barrier layer Rib1 can be formed first, and then the first light-emitting functional layer EL is formed. In this way, when the first light-emitting functional layer EL is formed, the first light-emitting functional layer EL will be blocked by the first barrier layer Rib1. , so as to cut off the water vapor intrusion route formed by the first light-emitting functional layer EL, and avoid encapsulation failure.
  • the thickness of the first barrier layer Rib1 can be made larger than the thickness of the first light-emitting functional layer EL, and at the same time, the cross-sectional area of the first barrier layer Rib1 away from the base substrate 1 is larger, Therefore, it is beneficial to isolate the first light-emitting functional layer EL.
  • FIG. 3b schematically shows an enlarged view at position C in FIG. 2c.
  • the first light-emitting functional layer EL on the side of the first barrier layer Rib1 away from the base substrate 1 is hidden in FIG. 3b.
  • the orthographic projection of the first blocking layer Rib1 on the base substrate 1 partially overlaps with the first pattern, that is, the orthographic projection of the first blocking layer Rib1 on the base substrate 1 overlaps with the first bonding pattern.
  • the orthographic projection of the edge of the layer Dam near the binding region B overlaps on the base substrate 1, so as to ensure that the first barrier layer Rib1 will not expose the side of the first light-emitting functional layer EL due to limitations such as process precision.
  • the above-mentioned side surfaces of the first light-emitting functional layer EL refer to the side surfaces of the left and right sides of the first light-emitting functional layer EL in Fig. 3b.
  • the orthographic projection of the first blocking layer Rib1 on the base substrate 1 is located within the range of the pattern defined by the orthographic projection of the first adhesive layer Dam on the base substrate 1, for example, as As shown in Fig. 3b, the lower end of the first barrier layer Rib1 does not protrude from the first adhesive layer Dam.
  • the first adhesive layer Dam can enclose as large an area as possible, that is, even if the first panel area P has an area as large as possible, so that the first The film layer in the panel area P can also have as large an area as possible, which is beneficial to reduce the requirement of the display panel mother board on the process precision, thereby reducing the production cost.
  • Fig. 4a schematically shows a plan view of a first panel area in an embodiment of the present disclosure
  • Fig. 4b schematically shows one of the cross-sectional views of Fig. 4a along section line DD'.
  • the material of the first adhesive layer Dam used for bonding is generally relatively soft.
  • the cover plate 2 and the base substrate 1 are bonded together , a part of the first adhesive layer Dam will extend into the first panel area P under the action of pressure, and at this time, the part outside the first panel area P is the main body of the first adhesive layer Dam, and this part and The base substrate 1 and the cover plate 2 are bonded, and the first bonding layer Dam protruding into the first panel area P can be bonded to the first encapsulation layer TFE which will be mentioned below.
  • the first light-emitting functional layer EL includes a first light-emitting functional sublayer EL1 located in the reserved area S, a second light-emitting functional sub-layer EL2 located in the peripheral area W, and a sublayer located between the reserved area S and the peripheral area W.
  • the third light-emitting functional sublayer EL3 is located on the side of the first barrier layer Rib1 away from the base substrate 1, and the first light-emitting functional sub-layer EL1, the second light-emitting functional sub-layer EL2, and the third light-emitting functional sub-layer EL3 are spaced apart from each other.
  • the first luminescent functional layer EL when forming the luminescent functional layer EL, the first luminescent functional layer EL is separated by the first blocking layer Rib1 into three parts spaced apart from each other, that is, the first luminescent functional sublayer EL1, the second luminescent functional sublayer EL2 and the third light-emitting functional sub-layer EL3, so as to separate the first light-emitting functional layer EL in the reserved area S from the first light-emitting functional layer EL in the peripheral area W, and cut off the water vapor intrusion path formed by the first light-emitting layer EL .
  • the motherboard of the display panel further includes a pixel circuit layer 3 and a pixel defining layer (not shown in the figure) disposed on the side of the first light-emitting functional layer EL close to the base substrate 1, and the pixel defining layer is located on the second Between a light-emitting functional layer EL and the pixel circuit layer 3 .
  • the pixel circuit layer 3 includes a plurality of metal film layers and an insulating layer separating at least part of the metal film layers from each other, the insulating layer in the pixel circuit layer 3 may extend to the edge of the reserved area S, and the first isolation layer Rib1 It may be provided on an insulating layer extending to the edge of the reserved region S.
  • the first blocking layer Rib1 is disposed on the same layer as the pixel defining layer, wherein the setting of the first blocking layer Rib1 and the pixel defining layer on the same layer means that the first blocking layer Rib1 and the pixel defining layer are formed by the same film-forming process.
  • the first isolation layer Rib1 is provided on the same layer as one of the metal film layers in the pixel circuit layer 3, for example, the pixel circuit layer 3 includes a semiconductor layer, a first insulating layer, a first insulating layer, The gate layer, the second insulating layer, and the source-drain electrode layer, etc., the first isolation layer Rib1 can be arranged on the same layer as the source-drain electrode layer, and the arrangement of the first isolation layer Rib1 and the source-drain electrode layer on the same layer means that the first The isolation layer Rib1 and the source-drain electrode layer are formed by the same film-forming process.
  • the first barrier layer Rib1 can also be arranged on the same layer as other film layers or prepared through a separate film forming process, only need to make the preparation process of the first barrier layer Rib1 in It may be before the preparation process of the first light-emitting functional layer EL.
  • the reserved area S includes the display area AA, and the distance d1 between the outer edge of the orthographic projection of the first partition layer Rib1 on the base substrate 1 and the orthographic projection of the display area AA on the base substrate 1 greater than or equal to 850 ⁇ m, for example, the distance between the outer edge of the orthographic projection of the first barrier layer Rib1 on the base substrate 1 and the orthographic projection of the display area AA on the base substrate 1 is greater than or equal to 950 ⁇ m.
  • the first barrier layer Rib1 is strip-shaped, and the width of the first barrier layer Rib1 is greater than or equal to 850 ⁇ m.
  • the first barrier layer Rib1 is strip-shaped, and the width of the first barrier layer Rib1 is greater than or equal to 950 ⁇ m.
  • the outer edge of the orthographic projection of the first isolation layer Rib1 on the base substrate 1 means that the orthographic projection of the first isolation layer Rib1 on the base substrate 1 is away from the display area AA The edge on one side of the orthographic projection on the base substrate 1 .
  • the first partition layer Rib1 includes a first partition R1 and a second partition R2, the first partition R1 is arranged along the edge of the display area AA, the first end of the second partition R2 is connected to the first The partition part R1 is connected.
  • FIG. 4c schematically shows one of the enlarged views of position D in FIG. 4a. For clarity, the first light-emitting functional layer EL on the side of the first barrier layer Rib1 away from the base substrate 1 is hidden in FIG. 4c.
  • FIG. 5 schematically shows a cross-sectional view of FIG. 4c along section line EE′. As shown in FIG. 5 , the second end of the second partition R2 is located between the first adhesive layer Dam and the base substrate 1 .
  • the first adhesive layer Dam in the process of preparing the motherboard of the display panel, can be formed on the cover plate 2 first, and then the cover plate 2 and the base substrate 1 are bonded together.
  • the first adhesive layer Dam on the cover plate 2 can be pressed on the second partition R2, so that the second end of the second partition R2 is located between the first adhesive layer Dam and the base substrate 1 between.
  • other film layers such as the first encapsulation layer TFE mentioned below, may also be disposed between the second end of the second partition R2 and the first bonding layer Dam.
  • the reserved area S also includes a wiring area Z arranged on the side of the display area AA close to the binding area B, and the display panel motherboard also includes a plurality of pixel units (not shown in the figure), a plurality of pixel units are located in the display area AA.
  • the size of the wiring area Z in the direction from the display area AA to the binding area B, can be determined according to actual needs, and there is no limitation here.
  • the first end of the second partition R2 is connected to the end of the first partition R1 close to the binding area B, and the second The second end of the partition R2 extends toward the bonding region B until the orthographic projection of the second end of the second partition R2 on the base substrate 1 can partially overlap with the first pattern.
  • a plurality of pixel units may be arranged in an array, and each pixel unit may further include a plurality of sub-pixels, and each sub-pixel can display a color.
  • Each sub-pixel includes a light emitting device and a pixel circuit for providing driving current to the light emitting device, for example, the light emitting device may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED).
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the light-emitting device may include a first electrode 4, a second electrode (not shown in the figure) and the aforementioned first light-emitting functional layer EL, the first light-emitting functional layer EL is disposed between the first electrode 4 and the second electrode, Alternatively, the first electrode 4 and the second electrode are disposed on the same side of the first light emitting functional layer EL.
  • One of the first electrode 4 and the second electrode is an anode, and the other is a cathode.
  • the first electrode 4 may be a cathode.
  • the second electrode may be an anode.
  • the material of the first electrode 4 may include metal conductive materials, such as magnesium, aluminum, lithium and other metals and their alloys, or indium tin oxide (ITO), indium zinc oxide (IZO).
  • the material of the second electrode may include a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO) and the like.
  • the first electrode 4 is arranged on the side of the first light-emitting functional layer EL away from the base substrate 1, and the display panel mother board further includes: a flat plate arranged on the side of the first electrode 4 away from the base substrate 1 layer (not shown in the figure), the first electrode 4 and the planarization layer are located in the first panel area P.
  • the inventor found in research that, in addition to the first light-emitting layer EL, the first electrode 4 and the planar layer also constitute water vapor intrusion paths, which will also lead to package failure.
  • the first electrode 4 in the reserved area S and the first electrode 4 in the peripheral area W are separated by the first isolation layer Rib1, and the flat layer in the reserved area S and the peripheral area W
  • the flat layer in is separated by the first blocking layer Rib1, in other words, when forming the flat layer and the first electrode 4, based on the same principle as blocking the first light-emitting functional layer EL, the flat layer is separated by the first blocking layer Rib1. and the first electrode 4 are spaced into three parts, thereby separating the flat layer and the first electrode 4 in the reserved area S from the flat layer and the first electrode 4 in the peripheral area W, and cutting off the flat layer and the first electrode 4 formed by the flat layer and the first electrode 4 The formed water vapor intrusion path.
  • the motherboard of the display panel further includes a first encapsulation layer TFE disposed on the side of the planar layer away from the base substrate 1 , and the first encapsulation layer TFE extends continuously from the reserved area S to the peripheral area W.
  • the first encapsulation layer TFE also encapsulates the edge of the reserved area S near the binding area B, so that the edge of the reserved area S near the binding area B passes through the first encapsulation layer TFE blocks water vapor, and the other side edges of the retention area S block water vapor through the first barrier layer Rib1, in other words, a complete package structure can be formed through the first packaging layer TFE and the first barrier layer Rib1, thereby blocking the intrusion of water vapor and oxygen into the reservation Inside area S.
  • the first encapsulation layer TFE may include a first encapsulation sublayer, a second encapsulation sublayer and a third encapsulation sublayer arranged in sequence along a direction away from the base substrate 1 .
  • the first encapsulation sublayer and the third encapsulation sublayer may be made of inorganic materials, and the second encapsulation sublayer may be made of organic materials.
  • the first encapsulation sublayer and the third encapsulation sublayer can be prepared by a chemical vapor deposition process, and the second encapsulation layer can be prepared by an inkjet printing process.
  • the display substrate motherboard It is also possible to set up a corresponding retaining wall structure to prevent inkjet printed organic materials from overflowing to other areas (Overflow)
  • the first encapsulation layer TFE may only include the first encapsulation sub-layer, and the first encapsulation sub-layer may be prepared by chemical vapor deposition process.
  • the display substrate mother board may save The above-mentioned retaining wall structure is eliminated, thereby simplifying the preparation process.
  • the above-mentioned light emitting device can be driven actively or passively.
  • the passively driven OLED display panel is composed of a cathode and an anode, the intersection of the anode and the cathode can emit light, and the driving circuit can be externally mounted by a connection method such as a tape-carrying package or a chip-on-glass.
  • the active-driven OLED display panel can be equipped with a pixel circuit for each sub-pixel, and the pixel circuit is arranged in the above-mentioned pixel circuit layer 3, and the pixel circuit can include a thin film transistor with a switching function (that is, a switching transistor), a thin film transistor with a driving function, and a thin film transistor with a driving function.
  • the pixel circuit may also include other types of thin film transistors with a compensation function.
  • the pixel circuit works under the control of the data voltage signal transmitted through the data line, the gate scanning signal and the light emission control signal transmitted through the signal line, so as to drive the light emitting device to emit light, so as to realize display and other operations.
  • the motherboard of the display panel may also include various signal lines (not shown in the figure) provided on the base substrate, and the various signal lines include data voltage signal lines, gate scanning signal lines, light emitting Control signal lines, first power supply lines, second power supply lines, etc., so as to provide each pixel circuit with various signals such as data voltage signals, gate scanning signals, light emission control signals, first power supply voltages, and second power supply voltages.
  • the first power line may be a line that provides a VSS voltage signal
  • the second power line may be a line that provides a VDD voltage signal.
  • the first power line is electrically connected to the first electrode 4 of the light emitting device
  • the second power line is electrically connected to the second electrode of the light emitting device.
  • the second power line is electrically connected to the second electrode of the light emitting device
  • the second power line is electrically connected to the second electrode through electronic components such as thin film transistors in the pixel circuit.
  • the motherboard of the display panel further includes a connection signal line (not shown in the figure), the first end of the connection signal line is connected to the pixel unit, for example, the first end of the connection signal line passes through the data voltage signal line Connect to the pixel unit.
  • the second end of the connecting signal line is connected to the bonding end in the bonding area B through the wiring area Z.
  • the second partition R2 is located on the first side and the second side of the routing area Z, the first side and the second side of the routing area Z are arranged along the first direction, and the first direction is from the display area AA to the binding area B The directions intersect, for example, the first direction is perpendicular to the direction from the display area AA to the binding area B.
  • the first end of the connection signal line can be connected to the pixel circuit of each sub-pixel, for example, the first end of the connection signal line can be connected to the pixel circuit of each sub-pixel through the data signal line arranged in the display area AA.
  • the second end of the connection signal line is connected to the binding end in the binding area B, and the binding end in the binding area B is also used to connect with the driver chip. In this way, the driver chip can connect the signal line to the display area.
  • the pixel units in AA provide driving signals to enable the pixel units to display.
  • the second spacer R2 can be located outside the wiring area Z, thereby preventing the structure of the second spacer R2 from affecting the layout of the connecting signal lines in the wiring area Z.
  • the connection signal line can be prepared first, and then the first isolation layer Rib1 is prepared.
  • the connection signal line is located on the side of the second spacer R2 close to the base substrate 1, Some connection signal lines can be connected to structures in other film layers through via holes. Since the second spacer R2 is located outside the routing area Z, the second spacer R2 will not affect the direction of these connection signal lines.
  • the first bonding layer Dam in the vicinity of the routing area Z, is not only bonded to the base substrate 1 , but also bonded to the connection signal line L. As shown in FIG. 5 , in some specific embodiments, in the vicinity of the routing area Z, the first bonding layer Dam is not only bonded to the base substrate 1 , but also bonded to the connection signal line L. As shown in FIG. 5 , in some specific embodiments, in the vicinity of the routing area Z, the first bonding layer Dam is not only bonded to the base substrate 1 , but also bonded to the connection signal line L. As shown in FIG.
  • the orthographic projection of the second end of the second partition R2 on the base substrate 1 is the same as that of the first pattern
  • the dimension d2 of the overlapping portion is greater than or equal to 45 ⁇ m.
  • the size of the overlapping portion is greater than or equal to 50 ⁇ m.
  • the first partition layer Rib1 is strip-shaped, and the first partition layer Rib1 includes at least one strip-shaped part, and each strip-shaped part may include the first partition part R1 and the second partition part R2 mentioned above.
  • Fig. 6 schematically shows the second enlarged view of the position D in Fig. 4a.
  • the strips X are arranged at intervals from each other, and a plurality of strips X are arranged along the width direction of the first partition layer Rib1. By arranging a plurality of strips X, the first partition layer Rib1 can have a better water blocking effect.
  • the first barrier layer Rib1 in the embodiment of the present disclosure will be described below by taking the example that the first barrier layer Rib1 includes a strip portion.
  • FIG. 7 schematically shows the second cross-sectional view of FIG. 4a along the section line DD'.
  • FIG. 4b and FIG. A second section on one side and a third section located between the first section and the second section. Wherein, the cross-sectional area of the first part is larger than the cross-sectional area of the third part.
  • the first barrier layer Rib1 when preparing the motherboard of the display panel, the first barrier layer Rib1 can be formed first, and then the first light-emitting functional layer EL is formed.
  • the first light-emitting functional layer EL is formed by evaporation process, due to The cross-sectional area of the first part of the strip X is larger than that of the third part, therefore, the first light-emitting functional layer EL will be more easily blocked by the first blocking layer Rib1.
  • the cross-sectional area of the second part of the strip X is greater than that of the third part.
  • the longitudinal section of the strip X is an I-shaped structure.
  • the cross-sectional area of the second part of the strip X is smaller than that of the third part.
  • the longitudinal section of the strip X is an inverted trapezoidal structure.
  • the longitudinal section of the strip-shaped portion X refers to the longitudinal section obtained by cutting the strip-shaped portion X along the second direction, and the second direction is the two sides of the strip-shaped portion X. The arrangement direction of the long sides of the strips is also the width direction of the strip portion X.
  • the material of the strip X may include two (or more than two) metal materials, and the two metal materials form a sandwich structure , using the characteristics of different etching rates of the two metal materials to form an I-shaped structure.
  • the strip portion X may be a laminated structure of molybdenum-aluminum-molybdenum material, or a laminated structure of titanium-aluminum-titanium material.
  • Each layer of the strip portion X may also be made of other materials, which are not specifically limited in the embodiments of the present disclosure.
  • wet etching process since the etching rate of aluminum is greater than that of titanium or molybdenum, wet etching is performed on the multilayer structure of the "sandwich" structure of titanium aluminum titanium or molybdenum aluminum molybdenum. , the I-shaped structure mentioned above can be formed, the process is simple and the cost is low.
  • each strip X includes a first strip subsection and a second strip subsection abutting against the first strip subsection.
  • FIG. 8 schematically shows the first strip subsection in an embodiment of the present disclosure.
  • a schematic view of the strip-shaped subsection and the second strip-shaped subsection, as shown in FIG. 8 the first strip-shaped subsection X1 and the second strip-shaped subsection X2 are arranged along the width direction of the first partition layer Rib1 .
  • the second strip-shaped sub-portion X2 protrudes from the surface of the first strip-shaped sub-portion X1 away from the base substrate 1 .
  • the first strip-shaped sub-portion X1 and the second strip-shaped sub-portion X2 may be prepared through a two-step process, since the second strip-shaped sub-portion X2 protrudes beyond the first strip-shaped sub-portion X1 and is away from the base substrate 1
  • the surface on one side, therefore, the upper surface of the strip part X can form a stepped structure, on the one hand, it is beneficial to cut off the first light-emitting functional layer EL, and on the other hand, it is beneficial to increase the bonding area and improve the adhesion strength.
  • the cross-sectional area of the first strip-shaped sub-portion X1 gradually increases, and the cross-sectional area of the second strip-shaped sub-portion X2 gradually decreases.
  • the longitudinal section of the first strip-shaped subsection X1 is a regular trapezoid
  • the longitudinal section of the second strip-shaped subsection X2 is an inverted trapezoid
  • the longitudinal section of the first strip-shaped sub-portion X1 and the second strip-shaped sub-portion X2 refers to the section obtained after the first strip-shaped sub-portion X1 and the second strip-shaped sub-portion X2 are cut along the second direction A longitudinal section.
  • Fig. 9 shows a schematic view of another first panel area in an embodiment of the present disclosure.
  • the edge of the first bonding layer Dam near the side of the binding area B is the second An edge D1
  • the first adhesive layer Dam also includes a second edge D2 opposite to the first edge D1 and a third edge D3 between the first edge D1 and the second edge D2, for example, the first adhesive layer Dam is a square ring structure
  • the first edge D1 of the first bonding layer Dam is the side edge below the first bonding layer Dam
  • the second edge D2 is the side edge above the first bonding layer Dam
  • the third edge D3 is the edges on the left and right sides of the first bonding layer Dam.
  • the orthographic projection of the first partition layer Rib1 on the base substrate 1 partially overlaps with the first pattern, while the orthographic projection of the first partition layer Rib1 on the substrate 1 and the orthographic projection of the second edge on the substrate 1 And the orthographic projections of the third edge on the substrate 1 do not overlap.
  • the packaging reliability of the first barrier layer Rib1 can be improved by making the orthographic projection of the first barrier layer Rib1 on the base substrate 1 partially overlap with the first pattern.
  • the first The orthographic projection of the partition layer Rib1 on the base substrate 1 does not overlap with the orthographic projection of the second edge D2 on the base substrate 1 and the orthographic projection of the third edge D3 on the base substrate 1, so that the first adhesive The area enclosed by the junction layer Dam is further increased, so that the first panel region P can have a larger area, reducing the requirement on the precision of the manufacturing process.
  • the display panel motherboard further includes a second adhesive layer Filler disposed between the cover plate 2 and the first encapsulation layer TFE, and the second adhesive layer Filler is located in the first panel area P.
  • the second adhesive layer Filler can be located between the first encapsulation layer TFE and the cover plate 2, and evenly fill in the first panel area P, so that the first encapsulation layer TFE and the cover plate 2 glued together.
  • the motherboard of the display panel further includes a second isolation layer Rib2 arranged on the same layer as the first isolation layer Rib1.
  • FIG. 10 schematically shows a cross-sectional view of FIG. 9 along the section line FF'. For clarity, FIG. 10 only shows the base substrate 1 , the second barrier layer Rib2 , the first adhesive layer Dam and the cover plate 2 . As shown in FIG. 9 and FIG.
  • the second isolation layer Rib2 includes a third isolation portion R3 and a fourth isolation portion R4 located on the side of the third isolation portion R3 away from the display area AA, and the third isolation portion R3 is located in the peripheral area W , the orthographic projection of the fourth partition R4 on the base substrate 1 overlaps the orthographic projection of the second edge D2 on the base substrate 1 and the orthographic projection of the third edge on the base substrate 1, and the second The four partitions R4 are located between the base substrate 1 and the first bonding layer Dam.
  • setting the first barrier layer Rib1 and the second barrier layer Rib2 in the same layer means that the first barrier layer Rib1 and the second barrier layer Rib2 are formed by the same film-forming process.
  • the orthographic projection of the second barrier layer Rib2 on the base substrate 1 can be a continuous pattern or a discontinuous pattern, which can be determined according to actual needs.
  • the shape of the longitudinal section of the second barrier layer Rib2 may be the same as the shape of the longitudinal section of the first barrier layer Rib1.
  • the longitudinal section of the second isolation layer Rib2 is an inverted trapezoidal structure; for another example, the longitudinal section of the second isolation layer Rib2 may be an I-shaped structure.
  • the longitudinal section of the second isolation layer Rib2 refers to the longitudinal section obtained after the second isolation layer Rib2 is cut along the third direction, and the third direction is the second isolation layer Rib2
  • the arrangement direction of the two long sides of Rib2 is also the width direction of the second partition layer Rib2.
  • Fig. 11a and Fig. 11b schematically show another schematic view in the first panel region in the embodiment of the present disclosure
  • Fig. 12 schematically shows a cross-sectional view of Fig. 11a and Fig. 11b along section line GG', for clarity, in Fig. 12 Only the base substrate 1 , the second barrier layer Rib2 , the third barrier layer Rib3 , the first adhesive layer Dam and the cover plate 2 are shown. As shown in FIG. 11 and FIG.
  • the display panel motherboard further includes: a third isolation layer Rib3 arranged on the same layer as the first isolation layer Rib1, and the third isolation layer Rib3 is located in the peripheral area W,
  • the third partition layer Rib3 includes a plurality of fifth partitions R5, and the plurality of fifth partitions R5 are nested and arranged at intervals.
  • the setting of the first barrier layer Rib1 and the third barrier layer Rib3 in the same layer means that the first barrier layer Rib1 and the third barrier layer Rib3 are formed by the same film-forming process.
  • the orthographic projection of the third barrier layer Rib3 on the substrate can be a continuous pattern or a discontinuous pattern, which can be determined according to actual needs.
  • the orthographic projection of each fifth partition R5 on the base substrate 1 is a continuous figure.
  • each fifth partition R5 includes a plurality of partition subparts R51 , and the plurality of partition subparts R51 are arranged at intervals from each other.
  • the shape of the longitudinal section of the third barrier layer Rib3 may be the same as the shape of the longitudinal section of the first barrier layer Rib1.
  • the longitudinal section of the third isolation layer Rib3 may be an inverted trapezoidal structure; for another example, the shape of the longitudinal section of the third isolation layer Rib3 may be an I-shaped structure.
  • the longitudinal section of the third isolation layer Rib3 refers to the longitudinal section obtained after the third isolation layer Rib3 is cut along the fourth direction, and the fourth direction is the third isolation layer Rib3
  • the arrangement direction of the two long sides of Rib3 is also the width direction of the third partition layer Rib3.
  • the preparation method of the embodiment of the present disclosure includes:
  • first light-emitting functional layer EL is located in the entire first panel area P, and the first barrier layer Rib1 separates the first light-emitting functional layer EL in the reserved area S from the first light-emitting functional layer EL in the peripheral area W .
  • the first electrode 4 is located in the entire first panel region P, and the first isolation layer Rib1 separates the first electrode 4 in the reserved region S from the first electrode 4 in the peripheral region W.
  • the flat layer is located in the entire first panel area P, and the first isolation layer Rib1 separates the flat layer in the reserved area S from the flat layer in the peripheral area W.
  • the first light-emitting functional layer EL, the first electrode 4 and the planar layer can be prepared by an evaporation process.
  • the first encapsulation layer TFE extends from the reserved area S to the peripheral area W, and forms an encapsulation structure with the first isolation layer Rib1, so that the reserved Devices in region S are spaced apart from the outside world.
  • the first encapsulation layer TFE can be prepared by a CVD process.
  • the preparation process of a part of the film layer is omitted, for example, the second electrode, etc. In the actual preparation process, these omitted
  • the preparation process of the film layer can be prepared by using the traditional preparation process, so it will not be repeated here.
  • the preparation method of the disclosed embodiment may also include:
  • first light-emitting functional layer EL is located in the entire first panel area, and the first barrier layer Rib1 separates the first light-emitting functional layer EL in the reserved area S from the first light-emitting functional layer EL in the peripheral area W.
  • the first electrode 4 is located in the entire first panel region P, and the first isolation layer Rib1 separates the first electrode 4 in the reserved region S from the first electrode 4 in the peripheral region W.
  • the flat layer is located in the entire first panel area P, and the first blocking layer Rib1 separates the flat layer in the reserved area S from the flat layer in the peripheral area W.
  • the first light-emitting functional layer EL, the first electrode 4 and the planar layer can be prepared by an evaporation process.
  • the first encapsulation layer TFE extends from the reserved area S to the peripheral area W, and forms an encapsulation structure with the first isolation layer Rib1, so that the reserved Devices in region S are spaced apart from the outside world.
  • the first encapsulation layer TFE can be prepared by a CVD process.
  • the above-mentioned preparation methods are only two of the preparation methods in this application.
  • the second barrier layer Rib2 and/or the third barrier layer Rib3 while preparing the first barrier layer Rib1 the specific structures of the above-mentioned film layers have been described in detail above, for example, the longitudinal section of the first barrier layer Rib1 can be Inverted trapezoidal structure or I-shaped structure, etc., so details will not be repeated here.
  • the first encapsulation layer TFE may include a first encapsulation sublayer, a second encapsulation sublayer, and a third encapsulation sublayer arranged in sequence along a direction away from the base substrate 1 .
  • the first encapsulation sublayer and the third encapsulation sublayer may be made of inorganic materials
  • the second encapsulation sublayer may be made of organic materials.
  • the first encapsulation sublayer and the third encapsulation sublayer can be prepared by a chemical vapor deposition process
  • the second encapsulation layer can be prepared by an inkjet printing process.
  • the display substrate motherboard It is also possible to set up a corresponding retaining wall structure to prevent inkjet printed organic materials from overflowing to other areas (Overflow)
  • the first encapsulation layer TFE may only include the first encapsulation sub-layer, and the first encapsulation sub-layer may be prepared by chemical vapor deposition process.
  • the display substrate mother board may save The above-mentioned retaining wall structure is eliminated, thereby simplifying the preparation process.
  • Figure 2a to Figure 12 provided by the embodiment of the present invention only show some film layers closely related to the embodiment of the present disclosure, and other film layers are omitted for clarity, for example, the pixel defining layer and For the anode layer, etc., the omitted film layers can be set in the traditional way, so it will not be repeated here.
  • FIG. 13a schematically shows one of the schematic diagrams of the display panel in the embodiment of the present disclosure.
  • the display panel has a second panel area S' and is located on the second panel The binding area B on the side of the area S';
  • the display panel includes: a base substrate, a cover plate opposite to the base substrate, a second light-emitting functional layer arranged between the base substrate and the cover plate, and a second isolation layer Rib1' and the third adhesive layer Dam';
  • the third adhesive layer Dam' is located between the second panel area S' and the binding area B, and is bonded to the cover plate and the base substrate, and the second light-emitting functional layer
  • the orthographic projection of the second partition layer Rib1' on the base substrate partially overlaps the orthographic projection of the third bonding layer Dam' on the base substrate and can form a third pattern,
  • the third pattern is a closed pattern
  • the orthographic projection of the second partition layer Rib1' on the base substrate partially overlaps the orthographic projection of the third bonding layer Dam
  • the display panel may be obtained by cutting the display panel mother board in the above embodiments.
  • the first panel region P and the The area defined by the binding area B is roughly cut to obtain an initial display panel, and then the initial display panel is subjected to fine cutting and grinding to remove the peripheral area W and the first adhesive layer disposed around the peripheral area W Dam, thereby obtaining the display panel of the embodiment of the present disclosure.
  • the third adhesive layer Dam' is obtained by cutting the first adhesive layer Dam, specifically, after fine-cutting the motherboard of the display substrate, the first adhesive layer Dam is located between the reserved area S and the binding area B The part between is kept, and this part is the third bonding layer Dam'.
  • the second light-emitting functional layer is obtained by cutting the first light-emitting functional layer EL. Specifically, the part of the first light-emitting functional layer EL located in the reserved area S is retained, that is, the second light-emitting functional layer. After finishing, the first isolation layer Rib1 in the display panel motherboard can remain. In other words, the second isolation layer Rib1' of the display panel can be substantially the same as the first isolation layer Rib1 in the display panel motherboard.
  • the second panel area S' includes the display area AA.
  • the second partition layer Rib1' includes a sixth partition part R6 and a seventh partition part R7, the sixth partition part R6 is arranged along the edge of the display area AA, the first end of the seventh partition part R7 is connected to the sixth partition part R6, and the sixth partition part R6 is connected to the sixth partition part R6.
  • the orthographic projection of the second end of the seven partitions R7 on the base substrate 1 ′ partially overlaps the orthographic projection of the third adhesive layer Dam′ on the base substrate 1 ′.
  • the second end of the seventh partition R7 is located between the third adhesive layer Dam' and the base substrate 1'.
  • the second panel area S' also includes a wiring area Z arranged on the side of the display area AA close to the binding area B
  • the display panel also includes a plurality of pixel units and connecting signal lines, and the plurality of pixel units Located in the display area AA, the first end of the connection signal line is connected to the pixel unit, and the other end of the connection signal line is connected to the binding end in the binding area B through the wiring area Z.
  • the seventh partition R7 is located on the first side and the second side of the routing area Z, the first side and the second side of the routing area Z are arranged along the first direction, and the first direction is from the display area AA to the binding area B , that is, the seventh partition R7 is located outside the routing area Z, so as to prevent the second partition R2 from affecting the routing of the routing in the routing area Z.
  • Fig. 13b schematically shows the second schematic diagram of the display panel in the embodiment of the present disclosure.
  • the display panel further includes a The second encapsulation layer TFE' on the side, the second encapsulation layer TFE' is obtained by cutting the first encapsulation layer TFE, in other words, after the above-mentioned display panel mother board is precisely cut, the first encapsulation layer TFE is located in the reserved area S The part in is reserved, that is, the second encapsulation layer TFE'.
  • Fig. 14a schematically shows a cross-sectional view of Fig. 13b along section line HH'
  • Fig. 14b schematically shows a cross-sectional view of Fig. 13b along section line II', as shown in conjunction with Fig. 13a to Fig. 14b
  • the display panel of the embodiment of the present disclosure It includes a pixel circuit 3', a second light-emitting functional layer EL', a first electrode 4', a second encapsulation layer TFE', and a second adhesive layer Filler' arranged in sequence along the direction away from the base substrate 1'.
  • the base substrate 1', the pixel circuit 3', the first electrode 4', and the second adhesive layer Filler' all refer to that after the display panel motherboard is cut, the display panel motherboard is combined with these film layers The corresponding part of the film layer remains.
  • the second encapsulation layer TFE' and the second isolation layer Rib1' constitute the encapsulation structure of the display panel, and the encapsulation structure separates the second light-emitting functional layer in the display panel from the outside world.
  • the water blocking ability of the display panel can be effectively improved through the second barrier layer Rib1', and the light-emitting functional layer in the special-shaped display panel needs to be cut off.
  • the water vapor intrusion path formed to the periphery of the display panel prevents packaging failure of the display panel.
  • the second barrier layer Rib1' can also play a packaging role, and cooperate with the second packaging layer TFE' to form the packaging structure of the display panel, so that the second light-emitting functional layer and other film layers in the display panel It is separated from the outside world and protects the devices in the display panel.
  • Figures 13a to 14b provided by the embodiments of the present disclosure only show some film layers closely related to the embodiments of the present disclosure, and other film layers are omitted for clarity, for example, pixel defining layers and For the anode layer, etc., the omitted film layers can be set in the traditional way, so it will not be repeated here.
  • the present disclosure also provides a display device, which includes the above-mentioned display panel.
  • examples of the display device include a tablet personal computer (PC), a smart phone, a personal digital assistant (PDA), a portable multimedia player, a game console, or a wrist-watch electronic device, and the like.
  • PC personal computer
  • PDA personal digital assistant
  • the embodiments of the present disclosure do not intend to limit the types of display devices.
  • the display device can be used not only in large electronic devices such as televisions (TVs) or external billboards, but also in medium or small electronic devices such as PCs, notebook computers, car navigation devices, or cameras. middle.

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Abstract

本公开提供了一种显示面板母板，具有第一面板区和绑定区，第一面板区具有：保留区以及***区；显示面板母板包括衬底基板、盖板、第一发光功能层、第一粘结层和第一隔断层；第一发光功能层位于第一面板区中；第一粘结层环绕第一面板区且与盖板和衬底基板相粘结，第一粘结层靠近绑定区一侧的边缘在衬底基板上的正投影限定出第一图案；第一隔断层将保留区中的第一发光功能层与***区中的第一发光功能层间隔开，第一隔断层在衬底基板上的正投影与第一图案部分交叠且围成第二图案，第二图案为封闭图案，第一隔断层在衬底基板上的正投影位于第一粘结层在衬底基板上的正投影所限定出的图案的范围之内。本公开还提供了一种显示面板和显示装置。

Description

显示面板母板、显示面板和显示装置 技术领域
本公开涉及显示技术领域，具体涉及一种显示面板母板、显示面板和显示装置。
背景技术
随着显示屏技术的发展，显示屏除了传统的信息展示等作用外，为了更好的适应环境的整体结构和使用要求，在外形上的要求也在逐步提升，随之产生了异形显示屏。异形显示屏是在传统显示屏的基础上改造成的特殊形状的显示屏，以使显示屏的特点能更好的适应客户需求。
发明内容
本公开提供了一种显示面板母板、显示面板和显示装置。
根据本公开的第一个方面，提供了一种显示面板母板，所述显示面板母板具有第一面板区和位于所述第一面板区一侧的绑定区，其中，所述第一面板区具有：保留区以及位于所述保留区之外的***区；所述显示面板母板包括：衬底基板、与所述衬底基板相对设置的盖板、设置在所述衬底基板与所述盖板之间的第一发光功能层、第一粘结层和第一隔断层；
所述第一发光功能层位于所述第一面板区中；
所述第一粘结层环绕所述第一面板区且与所述盖板和所述衬底基板相粘结，所述第一粘结层靠近所述绑定区一侧的边缘在所述衬底基板上的正投影限定出第一图案；
所述第一隔断层位于所述保留区的边缘且将所述保留区中的第一发光功能层与所述***区中的第一发光功能层间隔开，所述第一隔断层在所述衬底基板上的正投影与所述第一图案部分交叠，且与所述第一图案围成第二图案；其中，所述第二图案为封闭图案，所述第一隔断层在所述衬底基板上的正投影位于所述第一粘结层在所述衬底基板上的正投影所限定出的图案的范围之内。
根据本公开的实施例，所述保留区包括显示区；
所述第一隔断层包括第一隔断部和第二隔断部，所述第一隔断部沿所述显示 区的边缘设置，所述第二隔断部的第一端与所述第一隔断部连接，所述第二隔断部的第二端在所述衬底基板上的正投影与所述第一图案部分交叠；
其中，所述第二隔断部的第二端位于所述第一粘结层与所述衬底基板之间。
根据本公开的实施例，所述保留区还包括设置在所述显示区靠近所述绑定区一侧的走线区，所述显示面板母板还包括多个像素单元和连接信号线，所述多个像素单元位于所述显示区中，所述连接信号线的第一端与所述像素单元连接，所述连接信号线的另一端经过所述走线区与所述绑定区中的绑定端连接；
所述第二隔断部位于所述走线区的第一侧和第二侧，所述走线区的第一侧和第二侧沿第一方向排列，所述第一方向与从所述显示区指向所述绑定区的方向交叉。
根据本公开的实施例，在从所述显示区指向所述绑定区的方向上，所述第二隔断部的第二端在所述衬底基板上的正投影与所述第一图案的交叠部分的尺寸大于或等于45μm。
根据本公开的实施例，所述第一粘结层靠近所述绑定区一侧的边缘为第一边缘，所述第一粘结层还包括与所述第一边缘相对设置的第二边缘和位于所述第一边缘和所述第二边缘之间的第三边缘，所述第一隔断层在所述衬底基板上的正投影与所述第二边缘在所述衬底基板上的正投影以及所述第三边缘在所述衬底基板上的正投影均不交叠。
根据本公开的实施例，所述显示面板母板还包括与所述第一隔断层同层设置的第二隔断层，所述第二隔断层包括第三隔断部和位于所述第三隔断部远离所述显示区一侧的第四隔断部，所述第三隔断部位于所述***区中，所述第四隔断部在所述衬底基板上的正投影与所述第二边缘在所述衬底基板上的正投影以及所述第三边缘在所述衬底基板上的正投影均交叠设置，并且，所述第四隔断部位于所述衬底基板与所述第一粘结层之间。
根据本公开的实施例，所述第一隔断层为条状，所述第一隔断层包括至少一个条状部，每个所述条状部包括靠近所述盖板一侧的第一部分、靠近所述衬底基板一侧的第二部分和位于所述第一部分和所述第二部分之间的第三部分；
所述第一部分的横截面积大于所述第三部分的横截面积。
根据本公开的实施例，所述第二部分的横截面积大于所述第三部分的横截面积；或者，
所述第二部分的横截面积小于所述第三部分的横截面积。
根据本公开的实施例，每个所述条状部包括第一条状子部和与所述第一条状子部相互抵靠的第二条状子部，所述第一条状子部和所述第二条状子部沿所述第一隔断层的宽度方向排列；
其中，所述第二条状子部突出于所述第一条状子部远离所述衬底基板一侧的表面。
根据本公开的实施例，沿靠近所述衬底基板的方向，所述第一条状子部的横截面积逐渐增大，所述第二条状子部的横截面积逐渐减小。
根据本公开的实施例，所述条状部的数量为多个，多个所述条状部彼此间隔设置，多个所述条状部沿所述第一隔断层的宽度方向排列。
根据本公开的实施例，所述显示面板母板还包括：与所述第一隔断层同层设置的第三隔断层，所述第三隔断层位于所述***区中，所述第三隔断层包括多个第五隔断部，所述多个第五隔断部相互嵌套且间隔设置。
根据本公开的实施例，每个所述第五隔断部包括多个隔断子部，所述多个隔断子部彼此间隔设置；或者，
每个所述第五隔断部在所述衬底基板上的正投影为连续的图形。
根据本公开的实施例，所述显示面板母板还包括设置在所述第一发光功能层靠近所述衬底基板一侧的像素电路层和像素界定层，所述像素界定层位于所述第一发光功能层与所述像素电路层之间；
所述第一隔断层与所述像素界定层同层设置；或者，
所述第一隔断层与所述像素电路层中的其中一层金属膜层同层设置。
根据本公开的实施例，所述第一隔断层在所述衬底基板上的正投影的外侧边缘与所述显示区在所述衬底基板上的正投影之间的距离大于或等于850μm。
根据本公开的实施例，所述第一发光功能层包括位于所述保留区的第一发光功能子层、位于所述***区的第二发光功能子层以及位于所述保留区和所述***区之间的第三发光功能子层；
其中，所述第三发光功能子层位于所述第一隔断层远离所述衬底基板的一侧，所述第一发光功能子层、所述第二发光功能子层和所述第三发光功能子层彼此间隔开。
根据本公开的实施例，所述显示面板母板还包括：设置在所述第一发光功能 层远离所述衬底基板一侧的第一电极和设置在所述第一电极远离所述衬底基板一侧的平坦层，所述第一电极和所述平坦层均位于所述第一面板区中；
所述保留区中的所述第一电极和所述***区中的所述第一电极被所述第一隔断层间隔开，所述保留区中的所述平坦层和所述***区中的所述平坦层被所述第一隔断层间隔开。
根据本公开的实施例，所述显示面板母板还包括设置在所述平坦层远离所述衬底基板一侧的第一封装层，所述第一封装层从所述保留区中连续地延伸至所述***区中。
根据本公开的实施例，所述显示面板母板还包括设置在所述盖板与所述第一封装层之间的第二粘结层，所述第二粘结层位于所述第一面板区中。
根据本公开的实施例，所述保留区包括显示区和设置在所述显示区靠近所述绑定区一侧的走线区；
所述显示面板母板还包括多个像素单元和连接信号线，所述像素单元位于所述显示区中，所述连接信号线的第一端与所述像素单元连接，所述连接信号线的第二端经过所述走线区与所述绑定区中的绑定端连接；
所述第一粘结层还与所述连接信号线相粘结。
本公开的第二方面提供了一种显示面板，其中，所述显示面板具有第二面板区和位于所述第二面板区一侧的绑定区；
所述显示面板包括：衬底基板、与所述衬底基板相对设置的盖板、设置在衬底基板与所述盖板之间的第二发光功能层、第二隔断层和第三粘结层；
其中，所述第三粘结层位于所述第二面板区与所述绑定区之间，且与所述盖板和所述衬底基板相粘结，所述第二发光功能层位于所述第二面板区中，所述第二隔断层位于所述第二面板区的边缘，所述第二隔断层在所述衬底基板上的正投影与所述第三粘结层在所述衬底基板上的正投影部分交叠且能够围成第三图案，其中，所述第三图案为封闭图案，所述第二隔断层在所述衬底基板上的正投影不超出所述第三粘结层在所述衬底基板上的正投影远离所述第二面板区在所述衬底基板上的正投影的一侧的边缘。
根据本公开的实施例，所述第二面板区包括显示区；
所述第二隔断层包括第六隔断部和第七隔断部，所述第六隔断部沿所述显示区的边缘设置，所述第七隔断部的第一端与所述第六隔断部连接，所述第七隔断 部的第二端在所述衬底基板上的正投影与所述第三粘结层在所述衬底基板上的正投影部分交叠；
其中，所述第七隔断部的第二端位于所述第三粘结层与所述衬底基板之间。
根据本公开的实施例，所述第二面板区还包括设置在所述显示区靠近所述绑定区一侧的走线区，所述显示面板还包括多个像素单元和连接信号线，所述多个像素单元位于所述显示区中，所述连接信号线的第一端与所述像素单元连接，所述连接信号线的另一端经过所述走线区与所述绑定区中的绑定端连接；
所述第七隔断部位于所述走线区的第一侧和第二侧，所述走线区的第一侧和第二侧沿第一方向排列，所述第一方向与从所述显示区指向所述绑定区的方向交叉。
根据本公开的实施例，所述显示面板还包括：
二发光功能层远离所述衬底基板一侧的第二封装层，其中，所述第二封装层与所述第二隔断层构成所述显示面板的封装结构，所述封装结构将所述显示面板中的所述第二发光功能层与外界间隔开。
本公开的第三方面提供了一种显示装置，其中，包括：上述的显示面板。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述内容以及其他目的、特征和优点将更为清楚，在附图中：
图1a示意性示出了一对比例中显示面板母板的平面图；
图1b示意性示出了图1a沿剖线BB'的剖视图；
图2a至图2c示意性示出了根据本公开实施例中显示面板母板的平面图；
图3a示意性示出了图2c沿剖线CC'的剖视图；
图3b示意性示出了图2c中位置C处的放大图；
图4a示意性示出了根据本公开实施例中一种第一面板区的平面图；
图4b示意性示出了图4a沿剖线DD'的剖视图之一；
图4c示意性示出了图4a中位置D的放大图之一；
图5示意性示出了图4c沿剖线EE'的剖视图；
图6示意性示出了图4a中位置D的放大图之二；
图7示意性示出了图4a沿剖线DD'的剖视图之二；
图8示意性示出了根据本公开实施例中第一条状子部和第二条状子部的示意图；
图9示意性示出了根据本公开实施例中另一种第一面板区中的示意图；
图10示意性示出了图9沿剖线FF'的剖视图；
图11a和图11b示意性示出了根据本公开实施例中另一种第一面板区中的示意图；
图12示意性示出了图11a和图11b沿剖线GG'的剖视图；
图13a示意性示出了根据本公开实施例中显示面板的示意图之一；
图13b示意性示出了根据本公开实施例中显示面板的示意图之二；
图14a示意性示出了图13b沿剖线HH'的剖视图；
图14b示意性示出了图13b沿剖线II'的剖视图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开的保护范围。
需要说明的是，在附图中，为了清楚和/或描述的目的，可以放大元件的尺寸和相对尺寸。如此，各个元件的尺寸和相对尺寸不必限于图中所示的尺寸和相对尺寸。在说明书和附图中，相同或相似的附图标号指示相同或相似的部件。
当元件被描述为“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件时，所述元件可以直接在所述另一元件上、直接连接到所述另一元件或直接结合到所述另一元件，或者可以存在中间元件。然而，当元件被描述为“直接在”另一元件“上”、“直接连接到”另一元件或“直接结合到”另一元件时，不存在中间元件。用于描述元件之间的关系的其他术语和/或表述应当以类似的方式解释，例如，“在……之间”对“直接在……之间”、“相邻”对“直接相邻”或“在……上”对“直接在……上”等。此外，术语“连接”可指的是物理连接、电连接、通信连接和/或流体连接。此外，X轴、Y轴和Z轴不限于直角坐标系的三个轴，并且可以以更广泛的含义解释。例如，X轴、Y轴和Z轴可彼此垂直，或者可代表彼此不垂直的 不同方向。出于本公开的目的，“X、Y和Z中的至少一个”和“从由X、Y和Z构成的组中选择的至少一个”可以被解释为仅X、仅Y、仅Z、或者诸如XYZ、XYY、YZ和ZZ的X、Y和Z中的两个或更多个的任何组合。如文中所使用的，术语“和/或”包括所列相关项中的一个或多个的任何组合和所有组合。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。因而，例如，下面讨论的第一部件、第一构件、第一元件、第一区域、第一层和/或第一部分可以被称为第二部件、第二构件、第二元件、第二区域、第二层和/或第二部分，而不背离本公开的教导。
为了便于描述，空间关系术语，例如，“上”、“下”、“左”、“右”等可以在此被使用，来描述一个元件或特征与另一元件或特征如图中所示的关系。应理解，空间关系术语意在涵盖除了图中描述的取向外，装置在使用或操作中的其它不同取向。例如，如果图中的装置被颠倒，则被描述为“在”其它元件或特征“之下”或“下面”的元件将取向为“在”其它元件或特征“之上”或“上面”。
本领域技术人员应该理解，在本文中，除非另有说明，表述“厚度”指的是沿垂直于显示基板设置有各个膜层的表面的尺寸，即沿显示基板的出光方向的尺寸。
在本文中，除非另有说明，表述“构图工艺”一般包括光刻胶的涂布、曝光、显影、刻蚀、光刻胶的剥离等步骤。表述“一次构图工艺”意指使用一块掩模板形成图案化的层、部件、构件等的工艺。
需要说明的是，表述“同一层”，“同层设置”或类似表述，指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
在本文中，除非另有说明，表述“电连接”可以表示两个部件或元件直接电连接，例如，部件或元件A与部件或元件B直接接触，并且二者之间可以传递电信号；也可以表示两个部件或元件通过例如导电线的导电媒介电连接，例如，部件或元件A通过导电线与部件或元件B电连接，以在两个部件或元件之间传递电信号；还可以表示两个部件或元件通过至少一个电子元器件电连接，例如，部 件或元件A通过至少一个薄膜晶体管与部件或元件B电连接，以在两个部件或元件之间传递电信号。
图1a示意性示出了一对比例中显示面板母板的平面图，图1b示意性示出了图1a沿剖线BB'的剖视图，结合图1a和图1b所示，显示面板母板包括相对设置的盖板11和阵列基板12，阵列基板12可以包括衬底基板121、以及沿远离衬底基板121的方向依次设置的像素电路层122、发光层123和封装层124等。显示面板母板划分为多个第一面板区13，第一面板区13包括异形显示区131和位于异形显示区131之外的***区132。如图1a所示，异形显示区131的形状区别于常规显示区的形状，示例性地，较为常见的常规显示区一般为矩形，而异形显示区131则是指非矩形的显示区，例如，“心形”的显示区或者“圆形”的显示区等。为展示清楚，图1a中仅示出了显示面板母板上的一个第一面板区13，实际上，显示面板母板上的第一面板区13的数量一般为多个，其数量可以根据实际需要确定，在此不作限制。在完成显示面板母板的制备工作之后，可以先沿着第一面板区13对显示面板母板进行粗切，以得到初始显示面板，之后再沿着异形显示区131进行精切，从而得到异形显示面板。
目前，在制备上述的显示面板母板时，通常采用蒸镀工艺形成发光层123，以及通过化学气相沉积(CVD)或者喷墨打印(IJP)等方式形成封装层124。在理想的情况下，期望在异形显示区131中形成发光层123以及封装层124，但是，由于异形显示区131的形状较为特殊，而上述工艺采用的掩膜板的图案通常为矩形，因此，通过上述工艺难以准确的在异形显示区131中形成发光层123以及封装层124。为了解决这一问题，在该对比例中，除了在异形显示区131中形成有发光层123以及封装层124之外，在异形显示区131外部(也即***区132中)也形成发光层123以及封装层124。然而，发明人通过研究发现，采用上述方式制备的显示面板母板在进行切割时容易发生封装失效。
例如，如图1b所示，显示面板母板的盖板11和阵列基板12一般通过粘结胶14贴合在一起，由于封装层124不仅位于异形显示区131中，同时还位于***区132中，通过传统的贴合方式进行贴合时，粘结胶14实际上是将阵列基板12中的封装层124与盖板11粘结在一起，由于封装层124与衬底基板121之间的粘附力较低，在进行切割时，封装层124容易与衬底基板121发生分离等问题，当封装层124与衬底基板121发生分离时，将直接导致盖板11与阵列基板12分 离，这会导致封装失效。
再例如，发光层123具有一定吸水性，当发光层123处于***区132中时，发光层123将会成为水氧入侵的媒介，而这也会引起封装失效。
有鉴于此，本公开实施例提供一种显示面板母板，图2a至图2c示意性示出了根据本公开实施例的显示面板母板的平面图，图3a示意性示出了图2c沿剖线CC'的剖视图，为展示清楚，图2a至图2c中隐去了第一发光功能层，结合图2a至图3a所示，显示面板母板具有第一面板区P和位于第一面板区P一侧的绑定区B，其中，第一面板区P具有：保留区S以及位于保留区S之外的***区W。显示面板母板包括：衬底基板1、与衬底基板1相对设置的盖板2、设置在衬底基板1与盖板2之间的第一发光功能层EL、第一粘结层Dam和第一隔断层Rib1。衬底基板1和盖板2的材料可以包括柔性材料或者刚性材料，例如，当衬底基板1的材料为柔性材料时，柔性材料可以包括聚酰亚胺等；当衬底基板1的材料为刚性材料时，刚性材料可以包括玻璃等。第一发光功能层EL可以为有机电致发光功能层，第一发光功能层EL可以为多层结构，例如，第一发光功能层EL可以包括空穴注入层、空穴传输层、有机发光层、电子传输层和电子注入层形成的多层结构。第一发光功能层EL位于第一面板区P中，例如，第一发光功能层EL位于保留区S和***区W中。第一粘结层Dam环绕第一面板区P且与盖板2和衬底基板1相粘结，第一粘结层Dam靠近绑定区B一侧的边缘(第一边缘D1)在衬底基板1上的正投影限定出第一图案，例如，第一图案可以是一段直线。第一隔断层Rib1位于保留区S的边缘且将保留区S中的第一发光功能层EL与***区W中的第一发光功能层EL间隔开，第一隔断层Rib1在衬底基板1上的正投影与第一图案部分交叠，且与第一图案围成第二图案。其中，第二图案为封闭图案，这样一来，第一隔断层Rib1能够将保留区S的边缘包围起来，从而将保留区S中的第一发光功能层EL与***区W中的第一发光功能层EL全部间隔开，从而切断由于第一发光功能层EL延伸至***区W中所构成的水汽入侵路径。
在本公开实施例中，显示面板母板可以具有多个第一面板区P，多个第一面板区P可以呈阵列排布，每个第一面板区P的一侧均设置有与该第一面板区P相对应的绑定区B。可选地，绑定区B具体设置在第一面板区P的哪一侧可以根据实际需要确定，在此不作限制，例如，如图2a和图2b所示，绑定区B位于第一面板区P的上方，再例如，如图2c所示，绑定区B位于第一面板区P的下方。 从第一面板区P中延伸出的连接信号线可以通过绑定区B与驱动芯片连接，从而使第一面板区中的发光器件能够在驱动芯片的驱动下进行显示。
在本公开实施例中，第一面板区P和绑定区B所限定出的区域为对显示面板母板进行粗切后所需保留下来的部分，***区W所限定出的区域为对显示面板母板进行精切后所需去除的部分。保留区S为一异形区域(也即非矩形的区域)，例如，如图2a和图2b所示，保留区S可以为一类似于“心形”的区域，或者，如图2c所示，保留区S为一类似于“圆形”的区域等。第一粘结层Dam可以是坝胶，其可以具有一定阻水性。第一粘结层Dam环绕第一面板区P，第一面板区P的形状可以根据实际需要确定，在此不作限制，例如，第一面板区P可以为方形，环绕第一面板区P设置的第一粘结层Dam可以为一方形的环状结构。由于位于第一面板区P边缘的盖板2和衬底基板1之间通常不设置其它结构，换句话说，显示面板母板的第一发光功能层EL以及封装层等虽然会延伸到保留区S之外，但不会延伸到第一面板区P之外，因此，第一粘结层Dam能够直接与衬底基板1和盖板2相粘结，这样一来，在对显示面板母板进行切割时，粘结胶能够将衬底基板1和盖板2牢固地粘结在一起而不会发生分离或者移位等问题。
下面以图2c中所示出的显示面板母板为例，对本公开实施例的显示面板母板中第一面板区的具体设置方式进行说明，结合图2c和图3a所示，在本公开实施例中，可以先形成第一隔断层Rib1，之后再形成第一发光功能层EL，这样一来，在形成第一发光功能层EL时，第一发光功能层EL将被第一隔断层Rib1隔断，从而切断由第一发光功能层EL构成的水汽入侵路线，避免封装失效。例如，在本公开实施例中，可以使第一隔断层Rib1的厚度大于第一发光功能层EL的厚度，同时，使第一隔断层Rib1远离衬底基板1一侧的横截面积较大，从而有利于将第一发光功能层EL隔断。
图3b示意性示出了图2c中位置C处的放大图，为展示清楚，图3b中隐去了第一隔断层Rib1远离衬底基板1一侧的第一发光功能层EL。如图3b所示，第一隔断层Rib1在衬底基板1上的正投影与第一图案部分交叠，也即，第一隔断层Rib1在衬底基板1上的正投影与第一粘结层Dam靠近绑定区B一侧的边缘在衬底基板1上的正投影部分交叠，这样能够保证第一隔断层Rib1不会由于工艺精度等限制而将第一发光功能层EL的侧面露出，从而提高第一隔断层Rib1隔绝水汽的可信赖性。需要说明的是，上述的第一发光功能层EL的侧面指的是 图3b中第一发光功能层EL的左右两侧的侧面。
在本公开实施例中，第一隔断层Rib1在衬底基板1上的正投影位于第一粘结层Dam在衬底基板1上的正投影所限定出的图案的范围之内，例如，如图3b所示，第一隔断层Rib1的下端没有突出第一粘结层Dam。这样一来，在保证第一隔断层Rib1的阻水性能的同时，使得第一粘结层Dam能够围出尽量大的面积，也即使第一面板区P具有尽量大的面积，这样，第一面板区P中的膜层也可以具有尽量大的面积，从而有利于降低显示面板母板对工艺精度的要求，从而能够降低生产成本。
下面以图2c中所示出的显示面板母板为例，结合图4a至图10对本公开实施例的显示面板母板进行进一步的说明。
图4a示意性示出了本公开实施例中一种第一面板区的平面图，图4b示意性示出了图4a沿剖线DD'的剖视图之一。结合图4a和图4b所示，在本公开实施例中，用于起到粘结作用的第一粘结层Dam的材料一般较软，当将盖板2与衬底基板1进行贴合时，第一粘结层Dam会有一部分在压力的作用下伸入第一面板区P中，此时，位于第一面板区P之外的部分为第一粘结层Dam的主体，该部分与衬底基板1和盖板2相粘结，而伸入第一面板区P中的第一粘结层Dam可以与下文将会提到的第一封装层TFE相粘结。
在一些具体实施例中，第一发光功能层EL包括位于保留区S的第一发光功能子层EL1、位于***区W的第二发光功能子层EL2以及位于保留区S和***区W之间的第三发光功能子层EL3。其中，第三发光功能子层EL3位于第一隔断层Rib1远离衬底基板1的一侧，第一发光功能子层EL1、第二发光功能子层EL2和第三发光功能子层EL3彼此间隔开，换句话说，在形成发光功能层EL时，第一发光功能层EL被第一隔断层Rib1隔断为彼此间隔开的三部分，也即第一发光功能子层EL1、第二发光功能子层EL2和第三发光功能子层EL3，从而将保留区S中的第一发光功能层EL和***区W中的第一发光功能层EL间隔开，切断第一发光层EL所构成的水汽入侵路径。
在一些具体实施例中，显示面板母板还包括设置在第一发光功能层EL靠近衬底基板1一侧的像素电路层3和像素界定层(图中未示出)，像素界定层位于第一发光功能层EL与像素电路层3之间。可选地，像素电路层3包括多个金属膜层和将至少部分金属膜层彼此间隔开的绝缘层，像素电路层3中的绝缘层可以 延伸到保留区S的边缘，第一隔断层Rib1可以设置在延伸到保留区S的边缘的绝缘层上。
可选地，第一隔断层Rib1与像素界定层同层设置，其中，第一隔断层Rib1与像素界定层同层设置是指，第一隔断层Rib1与像素界定层采用同一成膜工艺形成。或者，第一隔断层Rib1与像素电路层3中的其中一层金属膜层同层设置，例如，像素电路层3包括沿远离衬底基板1的方向依次设置的半导体层、第一绝缘层、栅极层、第二绝缘层、以及源漏电极层等等，第一隔断层Rib1可以与源漏电极层同层设置，第一隔断层Rib1与源漏电极层同层设置是指，第一隔断层Rib1与源漏电极层采用同一成膜工艺形成。
需要说明的是，在本公开实施例中，第一隔断层Rib1也可以与其他膜层同层设置或者通过单独的一道成膜工艺制备到得到，只需要使第一隔断层Rib1的制备工序在第一发光功能层EL的制备工序之前即可。
在一些具体实施例中，保留区S包括显示区AA，第一隔断层Rib1在衬底基板1上的正投影的外侧边缘与显示区AA在衬底基板1上的正投影之间的距离d1大于或等于850μm，例如，第一隔断层Rib1在衬底基板1上的正投影的外侧边缘与显示区AA在衬底基板1上的正投影之间的距离大于或等于950μm。可选地，第一隔断层Rib1为条状，第一隔断层Rib1的宽度大于或等于850μm，例如，第一隔断层Rib1为条状，第一隔断层Rib1的宽度大于或等于950μm。需要说明的是，在本公开实施例中，第一隔断层Rib1在衬底基板1上的正投影的外侧边缘是指：第一隔断层Rib1在衬底基板1上的正投影远离显示区AA在衬底基板1上的正投影的一侧的边缘。
在一些具体实施例中，第一隔断层Rib1包括第一隔断部R1和第二隔断部R2，第一隔断部R1沿显示区AA的边缘设置，第二隔断部R2的第一端与第一隔断部R1连接。图4c示意性示出了图4a中位置D的放大图之一，为展示清楚，图4c中隐去了第一隔断层Rib1远离衬底基板1一侧的第一发光功能层EL。结合图4a和图4c所示，第二隔断部R2的第二端在衬底基板1上的正投影与第一图案部分交叠，也即，第二隔断部R2的第二端在衬底基板1上的正投影与第一粘结层Dam靠近绑定区B的一侧边缘(第一边缘D1)在衬底基板1上的正投影部分交叠。其中，第二隔断部R2的第二端在衬底基板1上的正投影与第一图案部分交叠是指：第二隔断部R2的第二端在衬底基板1上的正投影与第一图案部 分重合(也即二者包括相同的区域)。图5示意性示出了图4c沿剖线EE'的剖视图，如图5所示，第二隔断部R2的第二端位于第一粘结层Dam与衬底基板1之间。
在本公开实施例中，在制备显示面板母板的过程中，可以先将第一粘结层Dam形成在盖板2上，之后，再将盖板2与衬底基板1贴合，在这一过程中，使盖板2上的第一粘结层Dam能够压覆在第二隔断部R2上，从而使第二隔断部R2的第二端位于第一粘结层Dam与衬底基板1之间。可选地，第二隔断部R2的第二端与第一粘结层Dam之间还可以设置有其他膜层，例如下文将会提到的第一封装层TFE等。
结合图4a和图4b所示，在一些具体实施例中，保留区S还包括设置在显示区AA靠近绑定区B一侧的走线区Z，显示面板母板还包括多个像素单元(图中未示出)，多个像素单元位于显示区AA中。
在本公开实施例中，在从显示区AA指向绑定区B的方向上，走线区Z的尺寸可以根据实际需要确定，在此不做限制。当在从显示区AA指向绑定区B的方向上走线区Z的尺寸较大时，第二隔断部R2的第一端与第一隔断部R1靠近绑定区B的一端连接，第二隔断部R2的第二端则朝向绑定区B延伸，直至第二隔断部R2的第二端在衬底基板1上的正投影能够与第一图案部分交叠。
在本公开实施例中，多个像素单元可以呈阵列排布，每一个像素单元可以进一步包括多个子像素，每个子像素能够显示一种颜色。每个子像素包括发光器件以及用于向该发光器件提供驱动电流的像素电路，例如，发光器件可以为有机发光二极管(OLED)或量子点发光二极管(QLED)等。发光器件可以包括第一电极4、第二电极(图中未示出)以及前文所述的第一发光功能层EL，第一发光功能层EL设置在第一电极4与第二电极之间，或者，第一电极4和第二电极设置在第一发光功能层EL的同一侧。第一电极4和第二电极中的一个为阳极，另一个为阴极。例如，第一电极4可以是阴极。第二电极可以是阳极。第一电极4的材料可以包括金属导电材料，例如镁、铝、锂等金属及其合金，或者氧化铟锡(ITO)、氧化铟锌(IZO)。第二电极的材料可以包括透明导电材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)等。
在一些具体实施例中，第一电极4设置在第一发光功能层EL远离衬底基板1的一侧，显示面板母板还包括：设置在第一电极4远离衬底基板1一侧的平坦层(图中未示出)，第一电极4和平坦层均位于第一面板区P中。发明人在研究 中发现，除第一发光层EL之外，第一电极4和平坦层也会构成水汽入侵路径，而这也会导致封装失效。有鉴于此，在一些具体实施例中，保留区S中的第一电极4和***区W中的第一电极4被第一隔断层Rib1间隔开，保留区S中的平坦层和***区W中的平坦层被第一隔断层Rib1间隔开，换句话说，在形成平坦层和第一电极4时，基于和隔断第一发光功能层EL相同的原理，通过第一隔断层Rib1将平坦层和第一电极4间隔成三个部分，从而将保留区S中的平坦层和第一电极4与***区W中的平坦层和第一电极4间隔开，切断由平坦层和第一电极4所构成的水汽入侵路径。
在一些具体实施例中，显示面板母板还包括设置在平坦层远离衬底基板1一侧的第一封装层TFE，第一封装层TFE从保留区S中连续地延伸至***区W中。
在本公开实施例中，第一封装层TFE还对保留区S靠近绑定区B一侧的边缘进行封装，这样一来，保留区S靠近绑定区B一侧的边缘通过第一封装层TFE阻隔水汽，保留区S的其他侧边缘通过第一隔断层Rib1阻隔水汽，换句话说，通过第一封装层TFE和第一隔断层Rib1能够构成完整的封装结构，从而阻隔水汽和氧气侵入保留区S内部。可选地，第一封装层TFE可以包括沿远离衬底基板1的方向依次设置的第一封装子层、第二封装子层以及第三封装子层。例如，第一封装子层和第三封装子层可以由无机材料构成，第二封装子层可以由有机材料构成。可选地，在本公开实施例中，第一封装子层和第三封装子层可以采用化学气相沉积工艺制备，第二封装层可以采用喷墨打印工艺制备，此时，显示基板母板上还可以对应设置挡墙结构，通过挡墙结构防止喷墨打印的有机材料向其他区域溢出(Overflow)
可选地，在另一些具体实施例中，第一封装层TFE还可以仅包括第一封装子层，第一封装子层可以采用化学气相沉积工艺制备，此时，显示基板母板上可以省去上述的挡墙结构，从而能够简化制备工艺。
还需要说明的是，上述的发光器件可以采用有源驱动或无源驱动。无源驱动OLED显示面板由阴极和阳极构成，阳极和阴极的交叉部分可以发光，驱动电路可由带载封装或玻璃载芯片等连接方式进行外装。有源驱动OLED显示面板对每个子像素可配备像素电路，该像素电路设置在上述的像素电路层3中，像素电路可以包括具有开关功能的薄膜晶体管(即开关晶体管)、具有驱动功能的薄膜晶 体管(即驱动晶体管)和一个存储电容。另外，像素电路还可以包括具有补偿功能的其他类型的薄膜晶体管。像素电路在通过数据线传输的数据电压信号和通过信号线传输的栅极扫描信号和发光控制信号的控制下工作，以驱动发光器件发光，从而实现显示等操作。
在一些具体实施例中，显示面板母板还可以包括设置在衬底基板上的各种信号线(图中未示出)，各种信号线包括数据电压信号线、栅极扫描信号线、发光控制信号线、第一电源线、第二电源线等，以便为每个像素电路提供数据电压信号、栅极扫描信号、发光控制信号、第一电源电压、第二电源电压等各种信号。
例如，第一电源线可以是提供VSS电压信号的走线，第二电源线可以是提供VDD电压信号的走线。例如，第一电源线电连接至发光器件的第一电极4，第二电源线电连接至发光器件的第二电极。需要说明的是，此处的“第二电源线电连接至发光器件的第二电极”可以表示：第二电源线通过像素电路中的薄膜晶体管等电子元器件与第二电极电连接。
在一些具体实施例中，显示面板母板还包括连接信号线(图中未示出)，连接信号线的第一端与像素单元连接，例如，连接信号线的第一端通过数据电压信号线与像素单元连接。连接信号线的第二端经过走线区Z与绑定区B中的绑定端连接。第二隔断部R2位于走线区Z的第一侧和第二侧，走线区Z的第一侧和第二侧沿第一方向排列，第一方向与从显示区AA指向绑定区B的方向交叉，例如，第一方向与从显示区AA指向绑定区B的方向垂直。
连接信号线的第一端具体可以与每个子像素的像素电路连接，例如，连接信号线的第一端可以通过布设在显示区AA中的数据信号线与每个子像素的像素电路连接。连接信号线的第二端与绑定区B中的绑定端连接，绑定区B中的绑定端还用于与驱动芯片连接，这一样来，驱动芯片能够通过连接信号线向显示区AA中的像素单元提供驱动信号，以使像素单元进行显示。
在本公开实施例中，如图4a所示，第二间隔部R2设置在走线区Z的第一侧和第二侧，也即，第二间隔部R2设置在走线区Z的左右两侧，这样一来，可以使第二间隔部R2位于走线区Z之外，从而避免第二间隔部R2的结构影响走线区Z中连接信号线的布设。例如，在本公开实施例中，可以先制备连接信号线，之后再制备第一隔断层Rib1，在走线区Z中，连接信号线位于第二间隔部R2靠近衬底基板1的一侧，一些连接信号线可以通过过孔与位于其他膜层中的 结构连接，由于第二间隔部R2位于走线区Z之外，因此，第二间隔部R2不会影响这些连接信号线的走向。
如图5所示，在一些具体实施例中，在走线区Z附近，第一粘结层Dam除与衬底基板1相粘结外，还与连接信号线L相粘结。
如图4c所示，在一些具体实施例中，在从显示区AA指向绑定区B的方向上，第二隔断部R2的第二端在衬底基板1上的正投影与第一图案的交叠部分的尺寸d2大于或等于45μm。例如，交叠部分的尺寸大于或等于50μm。
在一些具体实施例中，第一隔断层Rib1为条状，第一隔断层Rib1包括至少一个条状部，每个条状部均可以包括上述的第一隔断部R1和第二隔断部R2。图6示意性示出了图4a中位置D的放大图之二，如图6所示，在一些具体实施例中，第一隔断层Rib1包括多个条状部X，多个所述条状部彼此间隔设置，多个条状部X沿第一隔断层Rib1的宽度方向排列，通过设置多个条状部X可以使得第一隔断层Rib1具有较好的阻水效果。
下面以第一隔断层Rib1包括一个条状部为例，对本公开实施例的第一隔断层Rib1进行说明。
图7示意性示出了图4a沿剖线DD'的剖视图之二，结合图4b和图7所示，每个条状部X包括靠近盖板2一侧的第一部分、靠近衬底基板1一侧的第二部分和位于第一部分和第二部分之间的第三部分。其中，第一部分的横截面积大于第三部分的横截面积。
在本公开实施例中，在制备显示面板母板时，可以先形成第一隔断层Rib1，之后，再形成第一发光功能层EL，当通过蒸镀工艺形成第一发光功能层EL时，由于条状部X的第一部分的横截面积大于第三部分的横截面积，因此，第一发光功能层EL将较容易的被第一隔断层Rib1隔断。
在一些具体实施例中，条状部X的第二部分的横截面积大于第三部分的横截面积，例如，如图7所示，条状部X的纵截面为工字型结构。或者，条状部X的第二部分的横截面积小于第三部分的横截面积，如图4b所示，条状部X的纵截面为倒梯形结构。需要说明的是，在本公开实施例中，条状部X的纵截面是指条状部X在沿第二方向进行剖切后所得到的纵截面，第二方向为条状部X的两条长边的排列方向，也即条状部X的宽度方向。
在一些具体实施例中，当条状部X的纵截面为工字型结构时，条状部X的 材料可以包括两种(或者两种以上)金属材料，并由两种金属材料构成三明治结构，利用两种金属材料的刻蚀速率不同的特点，形成工字型结构。
示例性地，在本公开实施例中，条状部X可以为钼铝钼材料的层叠结构，或钛铝钛材料的层叠结构。条状部X的各层还可以为其他材料，本公开实施例对此不作具体限定。其中，在湿法刻蚀过程中，由于铝的刻蚀速率大于钛或钼的刻蚀速率，因此，对钛铝钛或钼铝钼这种“三明治”结构的多层结构进行湿法刻蚀，便可以形成前文所述的工字型结构，工艺简便，成本较低。
在一些具体实施例中，每个条状部X包括第一条状子部和与第一条状子部相互抵靠的第二条状子部，图8示意性示出了本公开实施例中第一条状子部和第二条状子部的示意图，如图8所示，第一条状子部X1和第二条状子部X2沿第一隔断层Rib1的宽度方向排列。其中，第二条状子部X2突出于第一条状子部X1远离衬底基板1一侧的表面。
在本公开实施例中，第一条状子部X1和第二条状子部X2可以是通过两步工艺制备得到的，由于第二条状子部X2突出于第一条状子部X1远离衬底基板1一侧的表面，因此，条状部X的上表面可以形成阶梯状结构，一方面有利于隔断第一发光功能层EL，另一方面有利于增大粘结面积，提高粘附力度。
在一些具体实施例中，沿靠近衬底基板的方向，第一条状子部X1的横截面积逐渐增大，第二条状子部X2的横截面积逐渐减小。
例如，如图8所示，第一条状子部X1的纵截面为正梯形，第二条状子部X2的纵截面为倒梯形。在本公开实施例中，第一条状子部X1和第二条状子部X2的纵截面是指第一条状子部X1和第二条状子部X2在沿第二方向进行剖切后所得到的纵截面。
图9示意出本公开实施例中另一种第一面板区中的示意图，如图9所示，在一些具体实施例中，第一粘结层Dam靠近绑定区B一侧的边缘为第一边缘D1，第一粘结层Dam还包括与第一边缘D1相对设置的第二边缘D2和位于第一边缘D1和第二边缘D2之间的第三边缘D3，例如，第一粘结层Dam为方形的环状结构，第一粘结层Dam的第一边缘D1即为第一粘结层Dam下方的一侧边缘，第二边缘D2即为第一粘结层Dam上方的一侧边缘，第三边缘D3即为第一粘结层Dam左右两侧的边缘。第一隔断层Rib1在衬底基板1上的正投影与第一图案部分交叠，而第一隔断层Rib1在衬底基板1上的正投影与第二边缘在衬底基板 1上的正投影以及第三边缘在衬底基板1上的正投影均不交叠。如前文所述，通过使第一隔断层Rib1在衬底基板1上的正投影与第一图案部分交叠可以提高第一隔断层Rib1的封装可信赖性，在此基础上，通过使第一隔断层Rib1在衬底基板1上的正投影与第二边缘D2在衬底基板1上的正投影以及第三边缘D3在衬底基板1上的正投影均不交叠，能够使得第一粘结层Dam所能够围出的面积进一步增大，从而使第一面板区P可以具有更大的面积，降低对制备工艺精度的要求。
在一些具体实施例中，显示面板母板还包括设置在盖板2与第一封装层TFE之间的第二粘结层Filler，第二粘结层Filler位于第一面板区P中。在本公开实施例中，第二粘结层Filler可以位于第一封装层TFE与盖板2之间，且均匀的填充在第一面板区P中，从而将第一封装层TFE与盖板2粘结在一起。
在一些具体实施例中，显示面板母板还包括与第一隔断层Rib1同层设置的第二隔断层Rib2，图10示意性示出了图9沿剖线FF'的剖视图，为表示清楚，图10中仅示出了衬底基板1、第二隔断层Rib2、第一粘结层Dam和盖板2。结合图9和图10所示，第二隔断层Rib2包括第三隔断部R3和位于第三隔断部R3远离显示区AA一侧的第四隔断部R4，第三隔断部R3位于***区W中，第四隔断部R4在衬底基板1上的正投影与第二边缘D2在衬底基板1上的正投影以及第三边缘在衬底基板1上的正投影均交叠设置，并且，第四隔断部R4位于衬底基板1与第一粘结层Dam之间。
在本公开实施例中，第一隔断层Rib1与第二隔断层Rib2同层设置是指，第一隔断层Rib1与第二隔断层Rib2采用同一成膜工艺形成。第二隔断层Rib2在衬底基板1上的正投影可以为连续的图形也可以为间断的图形，具体可以根据实际需要确定。第二隔断层Rib2的纵截面的形状可以与第一隔断层Rib1的纵截面的形状相同。例如，第二隔断层Rib2的纵截面以为倒梯形结构；再例如，第二隔断层Rib2的纵截面的形状可以为工字型结构。通过在***区W中布置第二隔断层Rib2，相当于在衬底基板1上设置了更多的“凸起”结构，这样可以增大第二粘结层Filler的粘结面积，从而能够提高粘附力。需要说明的是，在本公开实施例中，第二隔断层Rib2的纵截面是指第二隔断层Rib2在沿第三方向进行剖切后所得到的纵截面，第三方向为第二隔断层Rib2的两条长边的排列方向，也即第二隔断层Rib2的宽度方向。
图11a和图11b示意出本公开实施例中另一种第一面板区中的示意图，图12示意性示出了图11a和图11b沿剖线GG'的剖视图，为表示清楚，图12中仅示出了衬底基板1、第二隔断层Rib2、第三隔断层Rib3、第一粘结层Dam和盖板2。结合图11和图12所示，在一些具体实施例中，显示面板母板还包括：与第一隔断层Rib1同层设置的第三隔断层Rib3，第三隔断层Rib3位于***区W中，第三隔断层Rib3包括多个第五隔断部R5，多个第五隔断部R5相互嵌套且间隔设置。通过设置第三隔断层Rib3，相当于在衬底基板1上设置了更多的“凸起”结构，这样能够进一步地提高第二粘结层Filler的粘结面积，从而进一步地提高粘附力。
第一隔断层Rib1与第三隔断层Rib3同层设置是指，第一隔断层Rib1与第三隔断层Rib3采用同一成膜工艺形成。第三隔断层Rib3在衬底基板上的正投影可以为连续的图形也可以为间断的图形，具体可以根据实际需要确定。例如，如图11a所示，每个第五隔断部R5在衬底基板1上的正投影为连续的图形。例如，如图11b所示，每个第五隔断部R5包括多个隔断子部R51，多个隔断子部R51彼此间隔设置。第三隔断层Rib3的纵截面的形状可以与第一隔断层Rib1的纵截面的形状相同。例如，第三隔断层Rib3的纵截面可以为倒梯形结构；再例如，第三隔断层Rib3的纵截面的形状可以为工字型结构。需要说明的是，在本公开实施例中，第三隔断层Rib3的纵截面是指第三隔断层Rib3在沿第四方向进行剖切后所得到的纵截面，第四方向为第三隔断层Rib3的两条长边的排列方向，也即第三隔断层Rib3的宽度方向。
下面对本公开实施例中显示面板母板的其中一种制备方法进行说明，本公开实施例的制备方法包括：
S11、在衬底基板1上制备像素电路层3。
S12、在像素电路层远3离衬底基板1的一侧形成像素界定层，同时，在第一面板区P中对应于显示面板母板的保留区S的边缘形成第一隔断层Rib1。
S13、在像素界定层远离衬底基板1的一侧形成第一发光功能层EL。其中，第一发光功能层EL位于整个第一面板区P中，并且，第一隔断层Rib1将保留区S中的第一发光功能层EL与***区W中的第一发光功能层EL间隔开。
S14、在第一发光功能层EL远离衬底基板1的一侧形成第一电极4。其中，第一电极4位于整个第一面板区P中，并且，第一隔断层Rib1将保留区S中的 第一电极4与***区W中的第一电极4间隔开。
S15、在第一电极4远离衬底基板1的一侧形成平坦层。其中，平坦层位于整个第一面板区P中，并且，第一隔断层Rib1将保留区S中的平坦层与***区W中的平坦层间隔开。
在本公开实施例中，第一发光功能层EL、第一电极4和平坦层可以通过蒸镀工艺制备得到。
S16、在平坦层远离衬底基板1的一侧形成第一封装层TFE，第一封装层TFE从保留区S延伸至***区W中，且与第一隔断层Rib1构成封装结构，从而将保留区S中的器件与外界间隔开。
在本公开实施例中，第一封装层TFE可以通过CVD工艺制备得到。
S17、在盖板2上对应于第一面板区P边缘的位置涂覆第一粘结层Dam。
S18、在盖板2上的第一面板区P中涂覆第二粘结层Filler。
S19、将盖板2与衬底基板1贴合，且使第一间隔层Rib在衬底基板1上的正投影与第一粘结层Dam靠近绑定区B一侧的边缘在衬底基板1上的正投影部分交叠，从而得到本公开实施例的显示面板母板
需要说明的是，在上述的显示面板母板的制备方法中，为表述简便，故而略去了一部分膜层的制备过程，例如，第二电极等，在实际的制备过程中，略去的这些膜层的制备工艺可以采用传统的制备工艺制备得到，故在此不再赘述。
在另一些具体实施例中，本公开实施例的制备方法还可以包括：
S21、在衬底基板1上制备像素电路层3，其中，像素电路层3包括源漏金属层，在制备源漏金属层的同时，在第一面板区P中对应于显示面板母板的保留区S的边缘形成第一隔断层Rib1。
S22、在像素电路层3远离衬底基板1的一侧形成像素界定层
S23、在像素界定层远离衬底基板1的一侧形成第一发光功能层EL。其中，第一发光功能层EL位于整个第一面板区中，并且，第一隔断层Rib1将保留区S中的第一发光功能层EL与***区W中的第一发光功能层EL间隔开。
S24、在第一发光功能层EL远离衬底基板1的一侧形成第一电极4。其中，第一电极4位于整个第一面板区P中，并且，第一隔断层Rib1将保留区S中的第一电极4与***区W中的第一电极4间隔开。
S25、在第一电极4远离衬底基板1的一侧形成平坦层。其中，平坦层位于 整个第一面板区P中，并且，第一隔断层Rib1将保留区S中的平坦层与***区W中的平坦层间隔开。
在本公开实施例中，第一发光功能层EL、第一电极4和平坦层可以通过蒸镀工艺制备得到。
S26、在平坦层远离衬底基板1的一侧形成第一封装层TFE，第一封装层TFE从保留区S延伸至***区W中，且与第一隔断层Rib1构成封装结构，从而将保留区S中的器件与外界间隔开。
在本公开实施例中，第一封装层TFE可以通过CVD工艺制备得到。
S27、在盖板2上对应于第一面板区P边缘的位置涂覆第一粘结层Dam。
S28、在盖板2上的第一面板区P中涂覆第二粘结层Filler。
S29、将盖板2与衬底基板1贴合，且使第一隔断层Rib1在衬底基板1上的正投影与第一粘结层Dam靠近绑定区B一侧的边缘在衬底基板1上的正投影部分交叠，从而得到本公开实施例的显示面板母板
需要说明的是，上述的制备方法只是本申请中的其中两种制备方法，在一些具体实施例中，也可以在制备第一隔断层Rib1时使第一隔断层Rib1具有前文所描述的结构，或者，在制备第一隔断层Rib1的同时制备第二隔断层Rib2和/或第三隔断层Rib3，上述各个膜层的具体结构前文已有详细描述，例如第一隔断层Rib1的纵截面可以为倒梯形结构或者工字型结构等，故在此不再赘述。
需要说明的是，在本公开实施例中，第一封装层TFE可以包括沿远离衬底基板1的方向依次设置的第一封装子层、第二封装子层以及第三封装子层。例如，第一封装子层和第三封装子层可以由无机材料构成，第二封装子层可以由有机材料构成。可选地，在本公开实施例中，第一封装子层和第三封装子层可以采用化学气相沉积工艺制备，第二封装层可以采用喷墨打印工艺制备，此时，显示基板母板上还可以对应设置挡墙结构，通过挡墙结构防止喷墨打印的有机材料向其他区域溢出(Overflow)
可选地，在另一些具体实施例中，第一封装层TFE还可以仅包括第一封装子层，第一封装子层可以采用化学气相沉积工艺制备，此时，显示基板母板上可以省去上述的挡墙结构，从而能够简化制备工艺。
需要说明的是，本发明实施例所提供的图2a至图12仅仅示出了与本公开实施例密切相关的一些膜层，为展示清楚因而省去了其他膜层，例如、像素界定层 和阳极层等，省去的膜层可以采用传统的设置方式设置，故在此不再赘述。
本公开实施例还提供一种显示面板，图13a示意性示出了本公开实施例中显示面板的示意图之一，如图13a所示，显示面板具有第二面板区S'和位于第二面板区S'一侧的绑定区B；显示面板包括：衬底基板、与衬底基板相对设置的盖板、设置在衬底基板与盖板之间的第二发光功能层、第二隔断层Rib1'和第三粘结层Dam'；第三粘结层Dam'位于第二面板区S'与绑定区B之间，且与盖板和衬底基板相粘结，第二发光功能层位于第二面板区S'中，第二隔断层Rib1'在衬底基板上的正投影与第三粘结层Dam'在衬底基板上的正投影部分交叠且能够围成第三图案，其中，第三图案为封闭图案，第二隔断层Rib1'在衬底基板上的正投影不超出第三粘结层Dam'在衬底基板上的正投影远离第二面板区S'在衬底基板上的正投影的一侧的边缘。
在本公开实施例中，显示面板可以是由上述实施例中的显示面板母板切割后得到，例如，在对显示面板母板进行切割以得到显示面板时，可以先沿第一面板区P和绑定区B所限定出的区域进行粗切，以得到初始显示面板，之后，对初始显示面板进行精切和打磨等，以去除***区W以及设置在***区W周围的第一粘结层Dam，从而得到本公开实施例的显示面板。例如，第三粘结层Dam’由第一粘结层Dam切割后得到，具体地，在对显示基板母板进行精切之后，第一粘结层Dam位于保留区S与绑定区B之间的部分被保留下来，该部分即为第三粘结层Dam’。第二发光功能层由第一发光功能层EL切割后得到，具体地，第一发光功能层EL位于保留区S中的部分被保留下来，也即第二发光功能层。在精切后，显示面板母板中的第一隔断层Rib1可以保留下来，换句话说，显示面板的第二隔断层Rib1'可以与显示面板母板中的第一隔断层Rib1大致相同。
在一些具体实施例中，第二面板区S'包括显示区AA。第二隔断层Rib1'包括第六隔断部R6和第七隔断部R7，第六隔断部R6沿显示区AA的边缘设置，第七隔断部R7的第一端与第六隔断部R6连接，第七隔断部R7的第二端在衬底基板1’上的正投影与第三粘结层Dam’在衬底基板1’上的正投影部分交叠。其中，第七隔断部R7的第二端位于第三粘结层Dam’与衬底基板1’之间。
在一些具体实施例中，第二面板区S'还包括设置在显示区AA靠近绑定区B一侧的走线区Z，显示面板还包括多个像素单元和连接信号线，多个像素单元位于显示区AA中，连接信号线的第一端与像素单元连接，连接信号线的另一端经 过走线区Z与绑定区B中的绑定端连接。第七隔断部R7位于走线区Z的第一侧和第二侧，走线区Z的第一侧和第二侧沿第一方向排列，第一方向与从显示区AA指向绑定区B的方向交叉，也就是说，第七隔断部R7位于走线区Z之外，从而防止第二隔断部R2影响走线区Z中的走线的布设。
图13b示意性示出了本公开实施例中显示面板的示意图之二，如图13b所示，在一些具体实施例中，显示面板还包括设置在第二发光功能层远离衬底基板1’一侧的第二封装层TFE’，第二封装层TFE’由第一封装层TFE切割后得到，换句话说，在对上述的显示面板母板精切之后，第一封装层TFE位于保留区S中的部分被保留下来，也即第二封装层TFE’。
图14a示意性示出了图13b沿剖线HH'的剖视图，图14b示意性示出了图13b沿剖线II'的剖视图，结合图13a至图14b所示，本公开实施例的显示面板包括沿远离衬底基板1’的方向依次设置的像素电路3’、第二发光功能层EL’、第一电极4’、第二封装层TFE’、和第二粘结层Filler’。其中，衬底基板1’、像素电路3’、第一电极4’和第二粘结层Filler’均是指，在对显示面板母板切割后，由显示面板母板中与该些膜层相应的膜层保留下来的部分。在本公开实施例中，第二封装层TFE’与第二隔断层Rib1'构成显示面板的封装结构，封装结构将显示面板中的第二发光功能层与外界间隔开。
在本公开实施例中，在从显示面板母板切割得到显示面板的过程中，通过第二隔断层Rib1'能够有效的提高显示面板的阻水能力，切断由于异形显示面板中发光功能层需要延伸至显示面板***而形成的水汽入侵路径，避免显示面板发生封装失效。同时，在切割得到显示面板之后，第二隔断层Rib1'也可以起到封装作用，配合第二封装层TFE’构成显示面板的封装结构，从而将显示面板中的第二发光功能层等膜层与外界间隔开，对显示面板中的器件形成保护。
需要说明的是，本公开实施例所提供的图13a至图14b仅仅示出了与本公开实施例密切相关的一些膜层，为展示清楚因而省去了其他膜层，例如、像素界定层和阳极层等，省去的膜层可以采用传统的设置方式设置，故在此不再赘述。
本公开还提供一种显示装置，该显示装置包括上述的显示面板。
在本公开的其他实施方式中，显示装置的示例包括平板个人计算机(PC)、智能手机、个人数字助理(PDA)、便携式多媒体播放器、游戏机或腕表式电子装置等。然而，本公开的实施例并不意图限制显示装置的类型。在一些示例性实施例 中，显示装置不仅可用于诸如电视机(TV)或外部广告牌等大型电子装置中，而且可用于诸如PC、笔记本式计算机、汽车导航装置或相机等中型或小型电子装置中。
本领域技术人员可以理解，本公开的各个实施例和/或权利要求中记载的特征可以进行多种组合或/或结合，即使这样的组合或结合没有明确记载于本公开中。特别地，在不脱离本公开精神和教导的情况下，本公开的各个实施例和/或权利要求中记载的特征可以进行多种组合和/或结合。所有这些组合和/或结合均落入本公开的范围。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。本公开的范围由所附权利要求及其等同物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (25)

  1. 一种显示面板母板，所述显示面板母板具有第一面板区和位于所述第一面板区一侧的绑定区，其中，所述第一面板区具有：保留区以及位于所述保留区之外的***区；所述显示面板母板包括：衬底基板、与所述衬底基板相对设置的盖板、设置在所述衬底基板与所述盖板之间的第一发光功能层、第一粘结层和第一隔断层；
    所述第一发光功能层位于所述第一面板区中；
    所述第一粘结层环绕所述第一面板区且与所述盖板和所述衬底基板相粘结，所述第一粘结层靠近所述绑定区一侧的边缘在所述衬底基板上的正投影限定出第一图案；
    所述第一隔断层位于所述保留区的边缘且将所述保留区中的第一发光功能层与所述***区中的第一发光功能层间隔开，所述第一隔断层在所述衬底基板上的正投影与所述第一图案部分交叠，且与所述第一图案围成第二图案；其中，所述第二图案为封闭图案，所述第一隔断层在所述衬底基板上的正投影位于所述第一粘结层在所述衬底基板上的正投影所限定出的图案的范围之内。
  2. 根据权利要求1所述的显示面板母板，其中，所述保留区包括显示区；
    所述第一隔断层包括第一隔断部和第二隔断部，所述第一隔断部沿所述显示区的边缘设置，所述第二隔断部的第一端与所述第一隔断部连接，所述第二隔断部的第二端在所述衬底基板上的正投影与所述第一图案部分交叠；
    其中，所述第二隔断部的第二端位于所述第一粘结层与所述衬底基板之间。
  3. 根据权利要求2所述的显示面板母板，其中，所述保留区还包括设置在所述显示区靠近所述绑定区一侧的走线区，所述显示面板母板还包括多个像素单元和连接信号线，所述多个像素单元位于所述显示区中，所述连接信号线的第一端与所述像素单元连接，所述连接信号线的另一端经过所述走线区与所述绑定区中的绑定端连接；
    所述第二隔断部位于所述走线区的第一侧和第二侧，所述走线区的第一侧和第二侧沿第一方向排列，所述第一方向与从所述显示区指向所述绑定区的方向交 叉。
  4. 根据权利要求2所述的显示面板母板，其中，在从所述显示区指向所述绑定区的方向上，所述第二隔断部的第二端在所述衬底基板上的正投影与所述第一图案的交叠部分的尺寸大于或等于45μm。
  5. 根据权利要求1至4中任一项所述的显示面板母板，其中，所述第一粘结层靠近所述绑定区一侧的边缘为第一边缘，所述第一粘结层还包括与所述第一边缘相对设置的第二边缘和位于所述第一边缘和所述第二边缘之间的第三边缘，所述第一隔断层在所述衬底基板上的正投影与所述第二边缘在所述衬底基板上的正投影以及所述第三边缘在所述衬底基板上的正投影均不交叠。
  6. 根据权利要求5所述的显示面板母板，其中，所述显示面板母板还包括与所述第一隔断层同层设置的第二隔断层，所述第二隔断层包括第三隔断部和位于所述第三隔断部远离所述显示区一侧的第四隔断部，所述第三隔断部位于所述***区中，所述第四隔断部在所述衬底基板上的正投影与所述第二边缘在所述衬底基板上的正投影以及所述第三边缘在所述衬底基板上的正投影均交叠设置，并且，所述第四隔断部位于所述衬底基板与所述第一粘结层之间。
  7. 根据权利要求1至6中任一项所述的显示面板母板，其中，所述第一隔断层为条状，所述第一隔断层包括至少一个条状部，每个所述条状部包括靠近所述盖板一侧的第一部分、靠近所述衬底基板一侧的第二部分和位于所述第一部分和所述第二部分之间的第三部分；
    所述第一部分的横截面积大于所述第三部分的横截面积。
  8. 根据权利要求7所述的显示面板母板，其中，所述第二部分的横截面积大于所述第三部分的横截面积；或者，
    所述第二部分的横截面积小于所述第三部分的横截面积。
  9. 根据权利要求7所述的显示面板母板，其中，每个所述条状部包括第一条 状子部和与所述第一条状子部相互抵靠的第二条状子部，所述第一条状子部和所述第二条状子部沿所述第一隔断层的宽度方向排列；
    其中，所述第二条状子部突出于所述第一条状子部远离所述衬底基板一侧的表面。
  10. 根据权利要求9所述的显示面板母板，其中，沿靠近所述衬底基板的方向，所述第一条状子部的横截面积逐渐增大，所述第二条状子部的横截面积逐渐减小。
  11. 根据权利要求7所述的显示面板母板，其中，所述条状部的数量为多个，多个所述条状部彼此间隔设置，多个所述条状部沿所述第一隔断层的宽度方向排列。
  12. 根据权利要求1至11中任一项所述的显示面板母板，其中，所述显示面板母板还包括：与所述第一隔断层同层设置的第三隔断层，所述第三隔断层位于所述***区中，所述第三隔断层包括多个第五隔断部，所述多个第五隔断部相互嵌套且间隔设置。
  13. 根据权利要求12所述的显示面板母板，其中，每个所述第五隔断部包括多个隔断子部，所述多个隔断子部彼此间隔设置；或者，
    每个所述第五隔断部在所述衬底基板上的正投影为连续的图形。
  14. 根据权利要求1至13中任一项所述的显示面板母板，其中，所述显示面板母板还包括设置在所述第一发光功能层靠近所述衬底基板一侧的像素电路层和像素界定层，所述像素界定层位于所述第一发光功能层与所述像素电路层之间；
    所述第一隔断层与所述像素界定层同层设置；或者，
    所述第一隔断层与所述像素电路层中的其中一层金属膜层同层设置。
  15. 根据权利要求1至14中任一项所述的显示面板母板，其中，所述第一隔断层在所述衬底基板上的正投影的外侧边缘与所述显示区在所述衬底基板上的 正投影之间的距离大于或等于850μm。
  16. 根据权利要求1至15中任一项所述的显示面板母板，其中，所述第一发光功能层包括位于所述保留区的第一发光功能子层、位于所述***区的第二发光功能子层以及位于所述保留区和所述***区之间的第三发光功能子层；
    其中，所述第三发光功能子层位于所述第一隔断层远离所述衬底基板的一侧，所述第一发光功能子层、所述第二发光功能子层和所述第三发光功能子层彼此间隔开。
  17. 根据权利要求1至16中任一项所述的显示面板母板，其中，所述显示面板母板还包括：设置在所述第一发光功能层远离所述衬底基板一侧的第一电极和设置在所述第一电极远离所述衬底基板一侧的平坦层，所述第一电极和所述平坦层均位于所述第一面板区中；
    所述保留区中的所述第一电极和所述***区中的所述第一电极被所述第一隔断层间隔开，所述保留区中的所述平坦层和所述***区中的所述平坦层被所述第一隔断层间隔开。
  18. 根据权利要求17所述的显示面板母板，其中，所述显示面板母板还包括设置在所述平坦层远离所述衬底基板一侧的第一封装层，所述第一封装层从所述保留区中连续地延伸至所述***区中。
  19. 根据权利要求18所述的显示面板母板，其中，所述显示面板母板还包括设置在所述盖板与所述第一封装层之间的第二粘结层，所述第二粘结层位于所述第一面板区中。
  20. 根据权利要求1至19中任一项所述的显示面板母板，其中，所述保留区包括显示区和设置在所述显示区靠近所述绑定区一侧的走线区；
    所述显示面板母板还包括多个像素单元和连接信号线，所述像素单元位于所述显示区中，所述连接信号线的第一端与所述像素单元连接，所述连接信号线的第二端经过所述走线区与所述绑定区中的绑定端连接；
    所述第一粘结层还与所述连接信号线相粘结。
  21. 一种显示面板，其中，所述显示面板具有第二面板区和位于所述第二面板区一侧的绑定区；
    所述显示面板包括：衬底基板、与所述衬底基板相对设置的盖板、设置在衬底基板与所述盖板之间的第二发光功能层、第二隔断层和第三粘结层；
    所述第三粘结层位于所述第二面板区与所述绑定区之间，且与所述盖板和所述衬底基板相粘结，所述第二发光功能层位于所述第二面板区中，所述第二隔断层位于所述第二面板区的边缘，所述第二隔断层在所述衬底基板上的正投影与所述第三粘结层在所述衬底基板上的正投影部分交叠且能够围成第三图案，其中，所述第三图案为封闭图案，所述第二隔断层在所述衬底基板上的正投影不超出所述第三粘结层在所述衬底基板上的正投影远离所述第二面板区在所述衬底基板上的正投影的一侧的边缘。
  22. 根据权利要求21所述的显示面板，其中，所述第二面板区包括显示区；
    所述第二隔断层包括第六隔断部和第七隔断部，所述第六隔断部沿所述显示区的边缘设置，所述第七隔断部的第一端与所述第六隔断部连接，所述第七隔断部的第二端在所述衬底基板上的正投影与所述第三粘结层在所述衬底基板上的正投影部分交叠；
    其中，所述第七隔断部的第二端位于所述第三粘结层与所述衬底基板之间。
  23. 根据权利要求22所述的显示面板，其中，所述第二面板区还包括设置在所述显示区靠近所述绑定区一侧的走线区，所述显示面板还包括多个像素单元和连接信号线，所述多个像素单元位于所述显示区中，所述连接信号线的第一端与所述像素单元连接，所述连接信号线的另一端经过所述走线区与所述绑定区中的绑定端连接；
    所述第七隔断部位于所述走线区的第一侧和第二侧，所述走线区的第一侧和第二侧沿第一方向排列，所述第一方向与从所述显示区指向所述绑定区的方向交叉。
  24. 根据权利要求21至23中任一项所述的显示面板，其中，所述显示面板还包括：
    设置在所述第二发光功能层远离所述衬底基板一侧的第二封装层，所述第二封装层与所述第二隔断层构成所述显示面板的封装结构，所述封装结构将所述显示面板中的所述第二发光功能层与外界间隔开。
  25. 一种显示装置，其中，包括：如权利要求21至权利要求24中任一项所述的显示面板。
PCT/CN2021/127263 2021-10-29 2021-10-29 显示面板母板、显示面板和显示装置 WO2023070489A1 (zh)

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