WO2023065674A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2023065674A1
WO2023065674A1 PCT/CN2022/096038 CN2022096038W WO2023065674A1 WO 2023065674 A1 WO2023065674 A1 WO 2023065674A1 CN 2022096038 W CN2022096038 W CN 2022096038W WO 2023065674 A1 WO2023065674 A1 WO 2023065674A1
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WIPO (PCT)
Prior art keywords
display area
pixel
array substrate
light
anodes
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PCT/CN2022/096038
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English (en)
French (fr)
Inventor
许传志
谢正芳
夏振
Original Assignee
合肥维信诺科技有限公司
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Application filed by 合肥维信诺科技有限公司 filed Critical 合肥维信诺科技有限公司
Publication of WO2023065674A1 publication Critical patent/WO2023065674A1/zh
Priority to US18/358,197 priority Critical patent/US20230368715A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application belongs to the field of display technology, and in particular relates to an array substrate and a display panel.
  • notch screen With the development of display technology, users have higher and higher requirements for the screen-to-body ratio of the display panel.
  • technologies such as “notch screen”, “pop-up camera”, and “perforated screen” are all to increase the screen-to-body ratio of the display panel.
  • a light-transmitting display area can be set on the display panel, and photosensitive components such as cameras and infrared sensors are placed on the back of the light-transmitting display area.
  • photosensitive components such as cameras and infrared sensors are placed on the back of the light-transmitting display area.
  • a full-screen display of the display panel can be realized.
  • the driving circuit of the pixel light-emitting unit in the light-transmitting display area is arranged outside the light-transmitting display area, and the pixel anodes of the pixel light-emitting units in the light-transmitting display area need to be connected to corresponding drive circuit.
  • the anode leads will occupy the space of the light-transmitting display area, so that the number of pixel light-emitting units in the light-transmitting display area is limited, and the display effect of the display panel is reduced.
  • Embodiments of the present application provide an array substrate and a display panel, which can increase the number of pixel light-emitting units in the first display area, that is, the light-transmitting display area, so as to improve the display performance of the display panel.
  • an embodiment of the present application provides an array substrate.
  • the array substrate has a first display area and a second display area.
  • the light transmittance of the first display area is higher than the light transmittance of the second display area.
  • the array substrate includes: A plurality of pixel anodes, located in the first display area, corresponding to the plurality of pixel light-emitting units in the first display area; a plurality of driving circuits, located in the second display area, for driving the pixel light-emitting units in the first display area Light emission; a plurality of demultiplexing units, located in the first display area, corresponding to some pixel anodes, the projection of the demultiplexing unit on the array substrate overlaps with the projection of the corresponding pixel anode on the array substrate; multiple first leads , the demultiplexing unit is connected to the drive circuit through the first lead; multiple second leads, one demultiplexing unit is electrically connected to the anodes of N groups of pixels through N second leads, and N is an integer greater than 1.
  • an embodiment of the present application provides a display panel, including the array substrate of the first aspect.
  • an embodiment of the present application provides an array substrate, which has a first display area and a second display area, the light transmittance of the first display area is higher than the light transmittance of the second display area
  • the array substrate includes: a plurality of pixel anodes, located in the first display area, corresponding to the plurality of pixel light emitting units arranged in the first display area; a plurality of driving circuits, located in the second display area, It is used to drive the pixel light-emitting units in the first display area to emit light; a plurality of demultiplexing units are located in the first display area and are arranged corresponding to a part of the pixel anodes, and the demultiplexing units in the array
  • the projection on the substrate overlaps with the corresponding projection of the pixel anode on the array substrate; a plurality of first leads, the demultiplexing unit is connected to the driving circuit through the first leads; a plurality of second lead wires, one demultiplexing unit is electrically connected to N groups
  • Embodiments of the present application provide an array substrate and a display panel, wherein pixel anodes in the array substrate are disposed in a first display area, and a driving circuit is disposed in a second display area.
  • the demultiplexing unit is arranged corresponding to some of the pixel anodes, and the projection of the demultiplexing unit on the array substrate overlaps with the projection of the corresponding pixel anode on the array substrate.
  • the second lead for connecting the overlapping demultiplexing unit projected on the array substrate and the pixel anode does not extend beyond the pixel anode.
  • a demultiplexing unit When a demultiplexing unit is electrically connected to the anodes of N groups of pixels through N second leads, one second lead in the N second leads does not exceed the pixel anode, and the other second leads in the N second leads exceed the pixel anode.
  • the pixel anode can be driven by fewer leads beyond the pixel anode to drive more pixel anodes, that is, more pixel light-emitting units can be driven by fewer leads beyond the pixel anode, so that the set number of leads beyond the pixel anode
  • increase the number of pixel anodes in the first display area, that is, the light-transmitting display area that is, increase the number of pixel light-emitting units in the first display area, that is, the light-transmitting display area, and reduce the number of pixel light-emitting units in the light-transmitting display area Due to the limitation, the display performance of the display panel including the array substrate can be improved.
  • FIG. 1 is a schematic top view of an embodiment of an array substrate provided by the present application.
  • Fig. 2 is a partial enlarged view of an example of the Q1 area in Fig. 1;
  • Fig. 3 is a local enlarged view of another example of the Q1 region in Fig. 1;
  • FIG. 4 is a partial enlarged view of another example of the Q1 region in FIG. 1;
  • FIG. 5 is a schematic structural view of a light-transmitting display area of an array substrate
  • Fig. 6 is a partial enlarged view of another example of the Q1 area in Fig. 1;
  • FIG. 7 is a partial enlarged view of yet another example of the Q1 region in FIG. 1;
  • FIG. 8 is a schematic top view of another embodiment of the array substrate provided by the present application.
  • Fig. 9 is a partial enlarged view of an example of the Q2 area in Fig. 8.
  • FIG. 10 is a schematic top view of another embodiment of the array substrate provided by the present application.
  • FIG. 11 is a schematic structural diagram of an example of a demultiplexing unit in FIG. 7 .
  • a light-transmitting display area can be provided on the display panel, and the above-mentioned photosensitive component is arranged on the back of the light-transmitting display area, so that the full-screen display of the display panel can be realized on the basis of ensuring the normal operation of the photosensitive component.
  • the driving circuit of the pixel light-emitting unit in the light-transmitting display area can be arranged outside the light-transmitting display area.
  • the pixel anode of each pixel light-emitting unit in the light-transmitting display area is connected to the corresponding driving circuit of the pixel light-emitting unit through an anode lead, so that the driving circuit can drive the pixel light-emitting unit in the light-transmitting display area to emit light.
  • the anode leads need to occupy a certain space in the light-transmitting display area, the number of anode leads is limited.
  • the number of pixel light-emitting units in the light-transmitting display area is also limited, and the width of the light-transmitting display area is also limited. Restricted, reducing the display effect of the display panel; It will also be limited, affecting the display effect of the display panel.
  • the present application provides an array substrate and a display panel, which can control more pixel light-emitting units with fewer anode leads, reduce the limitation on the number of pixel light-emitting units in the light-transmitting display area, and increase the number of pixels in the light-transmitting display area.
  • the number of light-emitting units increases the width of the light-transmitting display area and improves the display effect of the display panel.
  • the array substrate has a display area AA and a non-display area NA.
  • the display area AA includes a first display area AA1 and a second display area AA2.
  • the second display area AA2 surrounds at least part of the first display area AA1.
  • the light transmittance of the first display area AA1 is higher than the light transmittance of the second display area AA2, and the first display area AA1 is a light-transmissive display area.
  • the light transmittance of the first display area AA1 may be greater than or equal to 15%, even greater than 40%, or have a higher light transmittance.
  • the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2, so that the display panel can integrate photosensitive components on the back of the first display area AA1, and at the same time, the first display area AA1 can also display pictures, improving the display panel.
  • the screen-to-body ratio realizes the full-screen design of the display panel.
  • the array substrate may include a pixel anode 11 , a driving circuit 12 , a demultiplexing unit 13 , a first lead 14 and a second lead 15 .
  • the pixel anode 11 is located in the first display area AA1.
  • a plurality of pixel anodes 11 are disposed in the first display area AA1.
  • the pixel anode 11 corresponds to the pixel light emitting unit in the first display area AA1.
  • the pixel anode 11 is the anode of the pixel light emitting unit in the first display area AA1.
  • the driving circuit 12 is located in the second display area AA2 and is used to drive the pixel light emitting units in the first display area to emit light.
  • the second display area AA2 is provided with a plurality of driving circuits 12 .
  • each pixel light emitting unit in the first display area AA1 is correspondingly provided with a driving circuit 12 in the second display area AA2.
  • the driving circuit 12 can provide driving signals for the pixel anodes 11 in the first display area AA1.
  • the demux unit 13 is located in the first display area AA1 and can be arranged corresponding to some of the pixel anodes 11 .
  • the first display area AA1 is provided with a plurality of demultiplexing units 13 .
  • the demultiplexing unit 13 can switch a common input line to one of a plurality of individual output lines.
  • One demultiplexing unit 13 can be electrically connected to N groups of pixel anodes 11 , N is the number of individual output lines that can be switched by the demultiplexing unit, and is an integer greater than 1.
  • the projection of the demultiplexing unit 13 on the array substrate overlaps with the projection of the corresponding pixel anode 11 on the array substrate.
  • the projection of the demultiplexing unit 13 on the array substrate falls into the projection of the corresponding pixel anode 11 on the array substrate.
  • the overlapping demultiplexing unit 13 projected on the array substrate is electrically connected to the pixel anode 11 .
  • the projection of one pixel anode 11 on the array substrate includes the projection of the demultiplexing unit 13 on the array substrate, that is, one demultiplexing unit
  • the projection of 13 on the array substrate falls into the projection of one pixel anode 11 in the N groups of pixel anodes 11 electrically connected to the demultiplexing unit 13 on the array substrate.
  • each pixel anode 11 in the N groups of pixel anodes 11 on the array substrate does not include the projection of the demultiplexing unit 13 on the array substrate.
  • the demultiplexing unit 13 is located between the pixel anode 11 and the base substrate of the array substrate.
  • the first lead 14 is electrically connected to the second lead 15 through the demultiplexing unit 13 .
  • the first lead 14 is used for connecting the driving circuit 12 and the demultiplexing unit 13 .
  • the demultiplexing unit 13 can be connected to the driving circuit 12 through the first wire 14 to realize the electrical connection between the driving circuit 12 and the demultiplexing unit 13 .
  • the second lead 15 is used to connect the demultiplexing unit 13 and the pixel anode 11 .
  • one demultiplexing unit 13 can be electrically connected to N groups of pixel anodes 11 through N second lead wires 15 , so as to realize the electrical connection between the demultiplexing unit 13 and the pixel anodes 11 .
  • the driving circuit 12 is electrically connected to the pixel anode 11 through the first lead 14 , the demultiplexing unit 13 and the second lead 15 .
  • N is an integer greater than 1.
  • the light emitting colors of the pixel light emitting units corresponding to the N groups of pixel anodes 11 electrically connected to the same demultiplexing unit 13 may be the same or different, which is not limited here.
  • a group of pixel anodes 11 includes one or more than two pixel anodes 11 .
  • one demultiplexing unit 13 is directly electrically connected to one pixel anode 11 in a group of pixel anodes 11 through one second lead 15 among N second leads 15, that is, one demultiplexing unit 13 is directly electrically connected to one pixel anode 11 through one second lead 15.
  • the lead 15 is connected to one pixel anode 11 .
  • a set of pixel anodes 11 includes one pixel anode 11 .
  • a second lead 15 is connected with a pixel anode 11, and the projection of the second lead 15 on the array substrate overlaps with the projection of the pixel anode 11 on the array substrate; another second lead 15 is connected with another pixel anode 11, at least part of the projection of the second lead 15 on the array substrate does not overlap with the projection of the pixel anode 11 on the array substrate.
  • a group of pixel anodes 11 includes one pixel anode 11 .
  • the second lead in FIG. 3 includes second lead 151 , 152 and 153 , and the pixel anode may include pixel anode 111 , 112 and 113 .
  • the second lead 151 is connected with the pixel anode 111, and the projection of the second lead 151 on the array substrate overlaps with the projection of the pixel anode 111 on the array substrate; the second lead 152 is connected with the pixel anode 112, and the second lead 152 is on the array substrate. At least part of the projection on the array substrate does not overlap with the projection of the pixel anode 112 on the array substrate; the second lead 153 is connected to the third pixel anode 113, and at least part of the projection of the second lead 153 on the array substrate does not overlap with the pixel anode 113 The projections on the array substrate overlap.
  • a group of pixel anodes 11 includes more than two pixel anodes 11 .
  • the pixel anodes 11 in the group of pixel anodes 11 are electrically connected sequentially.
  • the pixel anodes 11 in the set of pixel anodes 11 may be connected in series.
  • the pixel light emitting units corresponding to the pixel anodes 11 in a group of pixel anodes 11 have the same light emitting color.
  • a demultiplexing unit 13 can be electrically connected to a driving circuit 12 through a first lead 14 .
  • the driving circuit 12 can provide driving signals for N groups of pixel anodes 11 connected to the same demultiplexing unit 13 in time division, that is, one driving circuit 12 can provide driving signals for N groups of pixel anodes 11 .
  • the lead wire 15 is connected to the anode 11 of the pixel.
  • Whether the first display area is displayed or not can be controlled by the demultiplexing unit 13, and multiple demultiplexing units 13 in the first display area can be selectively turned on, for example, according to the application of the display panel including the array substrate The situation determines whether or not the plurality of demultiplexing units 13 in the first display area AA1 are turned on.
  • the multiple demultiplexing units 13 in the first display area AA1 are controlled to be disconnected, that is, the first display area AA1 is in a non-display state.
  • the display life of the first display area AA1 can be improved by controlling the first display area not to emit light when no display is required by the demultiplexing unit 13 .
  • the solution in this example can correspondingly reduce the number of driving circuits 12 for driving the pixel anodes 11 in the first display area AA1 in the second display area AA2 .
  • the number of driving circuits 12 in the second display area AA2 for driving the pixel anodes 11 in the first display area AA1 can be reduced by half.
  • the reduction in the number of drive circuits 12 used to drive the pixel anodes 11 in the first display area AA1 in the second display area AA2 can reduce the number of drive circuits 12 used to drive the pixel anodes 11 in the first display area AA1 in the second display area AA2.
  • the size of the space of the driving circuit 12 can provide more possibilities and scalability for the arrangement of the pixel light-emitting units in the second display area AA2.
  • the second lead 15 connecting them does not exceed the pixel anode 11 .
  • the projection of the pixel anode 11 on the array substrate includes the projection on the array substrate of the second lead 15 connecting the two, that is, for the array substrate.
  • There is no limit to the number of pixel light-emitting units in the first display area AA1 that is, the light-transmitting display area.
  • the lead wires beyond the pixel anode in the light-transmitting display area will affect the number of pixel light-emitting units in the light-transmitting display area.
  • the lead beyond the pixel anode refers to the lead whose at least part of its projection on the array substrate does not overlap with the projection of the pixel anode on the array substrate.
  • the array substrate in the embodiment of the present application is provided with a multi-channel distribution unit 13. Since the projection of the multi-channel distribution unit 13 on the array substrate overlaps with the projection of the corresponding pixel anode 11 on the array substrate, it is used to connect the multi-channel distribution unit. The unit 13 and a second lead 15 of the pixel anode 11 do not exceed the pixel anode 11 .
  • the demultiplexing unit 13 electrically connects N groups of pixel anodes 11, requiring one second lead 15 that does not exceed the pixel anode 11 and N-1 second leads 15 that exceed the pixel anode 11, under the condition that the same number of pixel anodes can be driven , reducing the number of leads beyond the pixel anode 11. That is, in the case of a certain number of lead wires beyond the pixel anode 11, a larger number of pixel anodes can be driven, reducing the limitation on the number of pixel light-emitting units in the light-transmitting display area.
  • the light-transmitting display area AA3 is provided with several pixel anodes 21 , and each pixel anode 21 is connected to the driving circuit outside the light-transmitting display area AA3 through an anode lead 22 .
  • the anode lead 22 is a lead beyond the pixel anode 21 .
  • the number of anode leads 22 is equal to the number of pixel anodes 21 .
  • One anode lead 22 can drive one pixel anode 22 .
  • thirty anode leads 22 are arranged in the light-transmitting display area AA3, correspondingly, thirty pixel anodes 22 are arranged in the light-transmitting display area AA3, and the number of pixel anodes 22 in the light-transmitting display area AA3 is restricted by a large number of anode leads 22. Therefore, the number of pixel light-emitting units in the light-transmitting display area AA3 is limited by a large number of anode leads 22 .
  • the lead wires beyond the pixel anode 11 in the first display area AA1 will affect the number of pixel light emitting units in the first display area AA1 .
  • the second lead wire 15 used to connect the demultiplexing unit 13 with non-overlapping projections on the array substrate and the pixel anode 11 extends beyond the pixel anode 11 . That is, at least part of the projection on the array substrate of the second wire 15 connecting the demultiplexing unit 13 and the pixel anode 11 whose projections do not overlap on the array substrate do not overlap with the projection of the pixel anode 11 on the array substrate.
  • the 2 can drive two pixel anodes 11 through the demultiplexing unit 13 by using one second lead 15 not exceeding the pixel anode 11 and one second lead 15 exceeding the pixel anode 11 .
  • the second lead 15 beyond the pixel anode 11 can be regarded as an anode lead, that is to say, two pixel anodes 11 can be driven by one anode lead, and the number of anode leads 11 can be increased in the first display area AA1
  • the number of pixel anodes 11 increases the number of pixel light emitting units in the first display area AA1.
  • a group of pixel anodes 11 includes one pixel anode 11 , and one demultiplexing unit 13 is electrically connected to two pixel anodes 11 through two second lead wires 15 .
  • Thirty second lead wires 15 extending beyond the pixel anodes 11 are provided in the first display area AA1 to drive sixty pixel anodes 11 .
  • the number of pixel anodes 11 in the first display area AA1 in the embodiment of the present application is doubled.
  • the number of pixel anodes 11 in the first display area AA1 in the embodiment of the present application The number of light emitting units has also been doubled.
  • the pixel anode 11 is disposed in the first display area AA1, and the driving circuit 12 is disposed in the second display area AA2.
  • the demultiplexing unit 13 is arranged corresponding to some of the pixel anodes 11, and the projection of the demultiplexing unit 13 on the array substrate overlaps with the projection of the corresponding pixel anode 11 on the array substrate.
  • the second lead 15 used to connect the demultiplexing unit 13 and the pixel anode 11 projected and overlapped on the array substrate does not extend beyond the pixel anode.
  • one demultiplexing unit 13 When one demultiplexing unit 13 is electrically connected to N groups of pixel anodes 11 through N second lead wires 15, one second lead wire 15 in the N second lead wires 15 does not exceed the pixel anode, and one of the N second lead wires 15 does not exceed the pixel anode.
  • N-1 second lead wires 15 beyond the pixel anode 11 can use fewer lead wires beyond the pixel anode 11 to drive more pixel anodes 11, that is, fewer lead wires beyond the pixel anode 11 can be used to drive more pixels
  • Light-emitting unit so that under the condition that the number of lead wires beyond the pixel anode 11 is fixed, the number of pixel anodes 11 in the first display area AA1 can be increased, that is, the pixel light-emitting unit in the first display area AA1, that is, the light-transmitting display area can be increased reduce the number of pixel light-emitting units in the first display area AA1, that is, the light-transmitting display area, and improve the display performance of the display panel including the array substrate.
  • the demultiplexing unit 13 may be electrically connected to the N control signal lines.
  • the demultiplexing unit 13 can be used to control the conduction of the N driving branches in a staggered manner under the action of N control signals provided by the control signal line.
  • one of the N driving branches is turned on.
  • Each driving branch includes a first lead 14 , a second lead 15 and a group of pixel anodes 11 .
  • the demultiplexing unit 13 is electrically connected to two control signal lines 17 .
  • the demultiplexing units 13 corresponding to the pixel anodes 11 in the same row may share N control signal lines, which is not limited here.
  • the number of wires in the first display area AA1 can be further reduced by using N control signal wires in common.
  • control signal line may include a clock signal line or a light emission control signal line connected to the driving circuit.
  • the clock signal line can provide a clock signal, and the effective levels of the clock signals provided by the two clock signal lines connected to the same demultiplexing unit 13 are staggered in time.
  • the two light emission control signal lines connected to the same demultiplexing unit 13, that is, the EM lines can be the light emission control signal lines 171 respectively connected to the two row driving circuits in the second display area AA2, that is, the EM lines connected to one demultiplexing unit 13.
  • the control signal lines include light emission control signal lines connected to the corresponding two row driving circuits. For example, as shown in FIG.
  • one demultiplexing unit 13 is electrically connected to two lighting control signal lines 171 .
  • the two light emission control signal lines 171 are respectively connected to the two row driving circuits in the second display area AA2.
  • the demultiplexing units 13 corresponding to the pixel anodes 11 in the same row can share the light emission control signal lines 171 respectively connected to the driving circuits of the two rows in the second display area AA2 .
  • the first display area AA1 may include a first area AA11 and a second area AA12 .
  • the first area AA11 is located between the second display area AA2 and the second area AA12.
  • the first area AA11 may surround at least a portion of the second area AA12. Compared with the second area AA12, the first area AA11 is closer to the second display area AA2.
  • the demultiplexing unit 13 in the above embodiments may be located in the second area AA12. That is, the demultiplexing unit 13 is provided corresponding to at least part of the pixel anodes 11 located in the second area AA12. As shown in FIG. 9 , the demultiplexing unit 13 is not provided in the first area AA11 , and the demultiplexing unit 13 is located in the second area AA12 .
  • the pixel anodes 11 in the first area AA11 can be electrically connected to the driving circuit 12 in the second display area AA2, specifically, the pixel anodes 11 in the first area AA11 can be connected to the driving circuit in the second display area AA2 through wires.
  • the driving circuit 12 is electrically connected, and the driving circuit 12 connected to the pixel anode 11 in the first area AA11 is not shown in FIG. 9 . Since the boundary of the second area AA12 is very close to the second display area AA2, that is, the area ratio of the first area AA11 occupied by the first display area AA1 is relatively small, and the number of pixel anodes 11 in the first area AA11 is also very small. Although the pixel anode 11 in the first area AA11 is connected to the driving circuit 12 through wires, the number of wires is very small, so the connection between the pixel anode 11 and the driving circuit in the first area AA11 will not affect the pixels in the first display area AA1. The number of anodes 11 is limited, or only negligibly small, and has no adverse effect on increasing the number of pixel light-emitting units in the first display region.
  • the second display area AA2 may include a third area AA21 and a fourth area AA22 .
  • the fourth area AA22 is located between the third area AA21 and the first display area AA1.
  • the third area AA21 can be regarded as the main screen area, and the fourth area AA22 can be regarded as the transition area.
  • the fourth area AA22 may surround at least a portion of the first display area AA1.
  • the driving circuit 12 may be located in the fourth area AA22.
  • one drive circuit 12 can drive N groups of pixel anodes 11 through one first lead 14, which can correspondingly reduce the number of pixel anodes 11 used to drive the first display area AA1 in the fourth area AA22.
  • the number of driving circuits 12 can be reduced, so that the size of the fourth area AA22 can be reduced.
  • the light transmittance of the fourth area AA22 may be smaller than the light transmittance of the first display area AA1, and the light transmittance of the fourth area AA22 may be greater than or equal to the light transmittance of the second display area AA2. limited.
  • one demultiplexing unit 13 may include N thin film transistors.
  • the control end of the thin film transistor can be electrically connected to the control signal line, the first end of the thin film transistor can be electrically connected to the first lead 14 , and the second end of the thin film transistor can be electrically connected to the second lead 15 .
  • the thin film transistor Under the action of the control signal provided by the control signal line 17, the thin film transistor can be turned on or off, so as to realize the turning on and off of the driving branch.
  • the control terminal of the thin film transistor may be a gate, the first terminal may be a source, and the second terminal may be a drain; or, the control terminal of the thin film transistor may be a gate, the first terminal may be a drain, and the second terminal may be a drain.
  • the two terminals can be source electrodes, which are not limited here.
  • the demultiplexing unit 13 includes two thin film transistors, denoted as M1 and M2 respectively.
  • the control end of the thin film transistor M1 is connected to the light emission control signal line 171 connected to the driving circuit 12 , the first end of the thin film transistor M1 is connected to the first lead 14 , and the second end of the thin film transistor M1 is connected to another second lead 15 .
  • the control end of the thin film transistor M2 is connected to the light emission control signal line 171 connected to another row driving circuit 12, the first end of the thin film transistor M2 is connected to the first lead 14, and the second end of the thin film transistor M2 is connected to another second lead 15 .
  • the pixel anode 11 can be driven by controlling the turn-on or turn-off of the thin film transistors M1 and M2. In some examples, thin film transistors M1 and M2 are not turned on at the same time.
  • the first lead wire 14 and the second lead wire 15 in the above embodiment may be traces of transparent materials such as traces of indium tin oxide (ITO traces), or traces of non-transparent materials, which are not limited herein.
  • transparent materials such as traces of indium tin oxide (ITO traces), or traces of non-transparent materials, which are not limited herein.
  • the present application also provides a display panel.
  • the display panel may include the array substrate in the above embodiments.
  • the specific content of the array substrate please refer to the relevant descriptions in the above embodiments, and the technical effect of the array substrate in the above embodiments can be realized, and will not be repeated here.
  • the present application also provides a display device.
  • the display device includes the display panel in the above-mentioned embodiments.
  • the display device may specifically be a mobile phone, a computer, a tablet computer, a TV, an electronic paper, and other devices with a display function, which are not limited herein.

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Abstract

一种阵列基板、显示面板及显示装置，属于显示技术领域。阵列基板具有第一显示区（AA1）和第二显示区（AA2），第一显示区（AA1）的透光率高于第二显示区（AA2）的透光率，阵列基板包括：像素阳极（11），位于第一显示区（AA1），与第一显示区（AA1）中的像素发光单元对应；驱动电路（12），位于第二显示区（AA2），用于驱动第一显示区（AA1）中的像素发光单元发光；多路分配单元（13），位于第一显示区（AA1），与部分像素阳极对应设置，多路分配单元（13）在阵列基板上的投影与对应的像素阳极（11）在阵列基板上的投影重叠；第一引线（14），多路分配单元（13）通过第一引线（14）与驱动电路（12）连接；第二引线（15），一个多路分配单元（13）通过N条第二引线（15）与N组像素阳极（11）电连接。

Description

阵列基板及显示面板
相关申请的交叉引用
本申请要求享有于2021年10月21日提交的名称为“阵列基板、显示面板及显示装置”的中国专利申请202111229137.0的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本申请属于显示技术领域，尤其涉及一种阵列基板及显示面板。
背景技术
随着显示技术的发展，用户对显示面板的屏占比要求越来越高。“刘海屏”、“弹出式摄像头”、“打孔屏”等技术的出现都是为了提升显示面板的屏占比。现阶段，在显示面板上可设置透光显示区，将摄像头、红外光传感器等感光组件设置在透光显示区背面，在保证感光组件正常工作的基础上，实现显示面板的全面屏显示。
为了保证透光显示区的透光性能，透光显示区内像素发光单元的驱动电路设置在透光显示区外，透光显示区内像素发光单元的像素阳极需要通过阳极引线一一连接到对应的驱动电路。阳极引线会占用透光显示区的空间，使得透光显示区内像素发光单元数量受到限制，降低了显示面板的显示效果。
发明内容
本申请实施例提供一种阵列基板及显示面板，能够增加第一显示区即透光显示区中像素发光单元的数量，以提高显示面板的显示性能。
第一方面，本申请实施例提供一种阵列基板，阵列基板具有第一显示区和第二显示区，第一显示区的透光率高于第二显示区的透光率，阵列基 板包括：多个像素阳极，位于第一显示区，与设于第一显示区中的多个像素发光单元对应；多个驱动电路，位于第二显示区，用于驱动第一显示区中的像素发光单元发光；多个多路分配单元，位于第一显示区，与部分像素阳极对应设置，多路分配单元在阵列基板上的投影与对应地像素阳极在阵列基板上的投影重叠；多条第一引线，多路分配单元通过第一引线与驱动电路连接；多条第二引线，一个多路分配单元通过N条第二引线与N组像素阳极电连接，N为大于1的整数。
第二方面，本申请实施例提供一种显示面板，包括第一方面的阵列基板。
第三方面，本申请实施例提供一种一种阵列基板，具有第一显示区和第二显示区，所述第一显示区的透光率高于所述第二显示区的透光率，所述阵列基板包括：多个像素阳极，位于所述第一显示区，与设于所述第一显示区中的多个像素发光单元对应；多个驱动电路，位于所述第二显示区，用于驱动所述第一显示区中的像素发光单元发光；多个多路分配单元，位于所述第一显示区，与部分所述像素阳极对应设置，所述多路分配单元在所述阵列基板上的投影与对应地所述像素阳极在所述阵列基板上的投影重叠；多条第一引线，所述多路分配单元通过所述第一引线与所述驱动电路连接；多条第二引线，一个所述多路分配单元通过N条所述第二引线与N组所述像素阳极电连接，N等于1。
本申请实施例提供一种阵列基板及显示面板，阵列基板中的像素阳极设置在第一显示区，驱动电路设置于第二显示区。多路分配单元与部分像素阳极对应设置，多路分配单元在阵列基板上的投影与对应的像素阳极在阵列基板上的投影重叠。用于连接在阵列基板上投影重叠的多路分配单元和像素阳极的第二引线并未超出像素阳极。一个多路分配单元通过N条第二引线与N组像素阳极电连接的情况下，N条第二引线中的一条第二引线未超出像素阳极，N条第二引线中的其他第二引线超出像素阳极，则可利用更少的超出像素阳极的引线驱动更多的像素阳极，即可利用更少的超出像素阳极的引线驱动更多像素发光单元，从而在设置的超出像素阳极的引线的数量一定的情况下，增加第一显示区即透光显示区中像素阳极的数 量，即增加第一显示区即透光显示区中像素发光单元的数量，减小透光显示区内像素发光单元数量受到的限制，提高包括该阵列基板的显示面板的显示性能。
附图说明
图1为本申请提供的阵列基板的一实施例的俯视示意图；
图2为图1中Q1区域的一示例的局部放大图；
图3为图1中Q1区域的另一示例的局部放大图；
图4为图1中Q1区域的又一示例的局部放大图；
图5为一种阵列基板的透光显示区的结构示意图；
图6为图1中Q1区域的再一示例的局部放大图；
图7为图1中Q1区域的又另一示例的局部放大图；
图8为本申请提供的阵列基板的另一实施例的俯视示意图；
图9为图8中Q2区域的一示例的局部放大图；
图10为本申请提供的阵列基板的又一实施例的俯视示意图；
图11为图7中一多路分配单元的一示例的结构示意图。
具体实施方式
随着显示技术的发展，用户对显示面板的屏占比要求越来越高。在诸如手机、平板电脑等显示装置上，需要在显示面板的一侧集成如前置摄像头、红外光传感器、接近光传感器等感光组件。可在显示面板上设置透光显示区，将上述感光组件设置在透光显示区背面，从而能够在保证感光组件正常工作的基础上，实现显示面板的全面屏显示。
为了保证感光组件能够正常工作，需要保证透光显示区的透光性能，可以将透光显示区内像素发光单元的驱动电路设置在透光显示区外。透光显示区内的每个像素发光单元的像素阳极通过一条阳极引线连接到该像素发光单元对应的驱动电路，以使得驱动电路可驱动透光显示区中的像素发光单元发光。但由于阳极引线在透光显示区中需要占据一定空间，阳极引线数量受到限制，对应地，一方面，透光显示区内像素发光单元的数量也 受到限制，透光显示区的宽度也随之受到了限制，降低了显示面板的显示效果；另一方面，透光显示区内像素发光单元的像素密度(Pixels Per Inch，PPI)、透光显示区外的显示区的像素发光单元的像素密度也会受到限制，影响显示面板的显示效果。
本申请提供一种阵列基板及显示面板，能够利用更少的阳极引线控制更多的像素发光单元，减小透光显示区中像素发光单元的数量受到的限制，能够增加透光显示区中像素发光单元的数量，增加透光显示区的宽度，提高显示面板的显示效果。
如图1所示，阵列基板具有显示区AA和非显示区NA。显示区AA包括第一显示区AA1和第二显示区AA2。
第二显示区AA2围绕第一显示区AA1的至少部分。第一显示区AA1的透光率高于第二显示区AA2的透光率，第一显示区AA1即为透光显示区。例如，第一显示区AA1的透光率可大于等于15％，甚至大于40％，或具有更高的透光率。第一显示区AA1的透光率大于第二显示区AA2的透光率，使得显示面板在第一显示区AA1的背面可以集成感光组件，同时第一显示区AA1还能够显示画面，提高显示面板的屏占比，实现显示面板的全面屏设计。
如图2、图3和图4所示，阵列基板可包括像素阳极11、驱动电路12、多路分配单元13、第一引线14和第二引线15。
像素阳极11位于第一显示区AA1。第一显示区AA1中设置有多个像素阳极11。像素阳极11与第一显示区AA1中的像素发光单元对应。像素阳极11即为第一显示区AA1中像素发光单元的阳极。
驱动电路12位于第二显示区AA2，用于驱动第一显示区中的像素发光单元发光。第二显示区AA2设置有多个驱动电路12。在一些示例中，第一显示区AA1中的每个像素发光单元在第二显示区AA2对应设置有一个驱动电路12。驱动电路12可为第一显示区AA1中的像素阳极11提供驱动信号。
多路分配单元13即demux单元位于第一显示区AA1，可与部分像素阳极11对应设置。第一显示区AA1设置有多个多路分配单元13。多路分 配单元13可将一条公共输入线切换到多条单独输出线中的一条。一个多路分配单元13可与N组像素阳极11电连接，N为多路分配单元能够支持切换的单独输出线的数目，为大于1的整数。多路分配单元13在阵列基板上的投影与对应的像素阳极11在阵列基板上的投影重叠。即多路分配单元13在阵列基板上的投影落入对应的像素阳极11在阵列基板上的投影。在阵列基板上投影重叠的多路分配单元13和像素阳极11电连接。在与一个多路分配单元13电连接的N组像素阳极11中，有一个像素阳极11在阵列基板上的投影包括该多路分配单元13在阵列基板上的投影，即，一个多路分配单元13在阵列基板上的投影落入与该多路分配单元13电连接的N组像素阳极11中的一个像素阳极11在阵列基板上的投影。并不是N组像素阳极11中的每一个像素阳极11在阵列基板上的投影都包括该多路分配单元13在阵列基板上的投影。在一些示例中，多路分配单元13位于像素阳极11与阵列基板的衬底基板之间。
第一引线14通过多路分配单元13与第二引线15电连接。第一引线14用于连接驱动电路12和多路分配单元13。具体地，多路分配单元13可通过第一引线14与驱动电路12连接，实现驱动电路12与多路分配单元13的电连接。第二引线15用于连接多路分配单元13与像素阳极11。具体地，一个多路分配单元13可通过N条第二引线15与N组像素阳极11电连接，实现多路分配单元13与像素阳极11的电连接。对应地，驱动电路12通过第一引线14、多路分配单元13和第二引线15实现与像素阳极11的电连接。其中，N为大于1的整数。在一些示例中，与同一个多路分配单元13电连接的N组像素阳极11对应的像素发光单元的发光颜色可以相同，也可不同，在此并不限定。
一组像素阳极11包括一个或两个以上的像素阳极11。具体地，一个多路分配单元13通过N条第二引线15中的一条第二引线15与一组像素阳极11中的一个像素阳极11直接电连接，即一个多路分配单元13通过一条第二引线15与一个像素阳极11连接。
在一些示例中，一组像素阳极11包括一个像素阳极11。如图2所示，一个多路分配单元13可通过两条第二引线15与两个像素阳极11连 接，即N＝2。其中，一条第二引线15与一个像素阳极11连接，且该第二引线15在阵列基板上的投影与该像素阳极11在阵列基板上的投影重叠；另一条第二引线15与另一个像素阳极11连接，该第二引线15在阵列基板上的至少部分投影不与该像素阳极11在阵列基板上的投影重叠。
如图3所示，一组像素阳极11包括一个像素阳极11。图3中的第二引线包括第二引线151、152和153，像素阳极可包括像素阳极111、112和113。一个多路分配单元13可通过三条第二引线151、152、153与三个像素阳极111、112、113连接，即N＝3。其中，第二引线151与像素阳极111连接，且第二引线151在阵列基板上的投影与像素阳极111在阵列基板上的投影重叠；第二引线152与像素阳极112连接，第二引线152在阵列基板上的至少部分投影不与像素阳极112在阵列基板上的投影重叠；第二引线153与第三个像素阳极113连接，第二引线153在阵列基板上的至少部分投影不与像素阳极113在阵列基板上的投影重叠。
在另一些示例中，一组像素阳极11包括两个以上的像素阳极11。在一组像素阳极11包括两个以上的像素阳极11的情况下，这一组像素阳极11中的像素阳极11依次电连接。例如，这一组像素阳极11中的像素阳极11可串联连接。具体地，在一组像素阳极11包括两个以上的像素阳极11的情况下，一组像素阳极11中的像素阳极11对应的像素发光单元的发光颜色相同。
在一些示例中，如图4所示，一个多路分配单元13可通过一条第一引线14与一个驱动电路12电连接。该驱动电路12可分时为与同一多路分配单元13连接的N组像素阳极11提供驱动信号，即可利用一个驱动电路12为N组像素阳极11提供驱动信号。
在一些示例中，N＝1，即一个多路分配单元13可通过一条第二引线15与一组像素阳极11电连接，即与该多路分配单元13连接的驱动电路12能够驱动该第二引线15连接的像素阳极11。可通过多路分配单元13控制第一显示区的显示与否，第一显示区中的多个多路分配单元13可有选择性地导通，如，根据包括该阵列基板的显示面板的应用情况确定第一显示区AA1中的多个多路分配单元13是否导通。例如，在某些需要使用感光 组件的情况下，控制第一显示区AA1中的多个多路分配单元13断开，即第一显示区AA1处于不显示状态。通过多路分配单元13控制第一显示区在不需要显示时不发光，可提高第一显示区AA1的显示寿命。
在N＞1的情况下，本示例的方案能够对应减少第二显示区AA2中用于驱动第一显示区AA1像素阳极11的驱动电路12的数量。例如，在N＝2的情况下，第二显示区AA2中用于驱动第一显示区AA1中像素阳极11的驱动电路12的数量可以减少一半。第二显示区AA2中用于驱动第一显示区AA1中像素阳极11的驱动电路12的数量的减小，可减小第二显示区AA2中用于设置驱动第一显示区AA1中像素阳极11的驱动电路12的空间的大小，为第二显示区AA2中像素发光单元的设置可提供更多的可能性和可扩展性。
对于在阵列基板上投影重叠的多路分配单元13和像素阳极11，连接两者的第二引线15未超出该像素阳极11。对于在阵列基板上投影重叠的多路分配单元13和像素阳极11，该像素阳极11在阵列基板上的投影包括连接两者的第二引线15在阵列基板上的投影，即，对于在阵列基板上投影重叠的多路分配单元13和像素阳极11，连接两者的第二引线15在阵列基板上的投影，与该像素阳极11在阵列基板上的投影重叠，连接两者的第二引线15并不会对第一显示区AA1即透光显示区中像素发光单元的数量造成限制。
透光显示区中超出像素阳极的引线会对透光显示区中像素发光单元的数量带来影响。超出像素阳极的引线指在阵列基板上的至少部分投影不与该像素阳极在阵列基板上的投影重叠的引线。本申请实施例中的阵列基板设置有多路分配单元13，由于多路分配单元13在阵列基板上的投影与对应的像素阳极11在阵列基板上的投影重叠，使得用于连接该多路分配单元13与该像素阳极11的一条第二引线15并未超出像素阳极11。多路分配单元13电连接N组像素阳极11需要一条未超出像素阳极11的第二引线15和N-1条超出像素阳极11的第二引线15，在能够驱动相同数量的像素阳极的情况下，减少超出像素阳极11的引线的数量。即在超出像素阳极11的引线的数量一定的情况下，能够驱动更多数量的像素阳极，减小 透光显示区内像素发光单元数量受到的限制。
如图5所示，透光显示区AA3设置有若干像素阳极21，每个像素阳极21都通过一条阳极引线22与透光显示区AA3外的驱动电路连接。阳极引线22为超出像素阳极21的引线。阳极引线22的数量与像素阳极21的数量相等。一条阳极引线22可驱动一个像素阳极22。
例如，透光显示区AA3设置三十条阳极引线22，对应地，透光显示区AA3对应设置三十个像素阳极22，透光显示区AA3中像素阳极22的数量受到了大量阳极引线22的限制，因此，透光显示区AA3中像素发光单元的数量受到了大量阳极引线22的限制。
在本申请实施例中，第一显示区AA1中超出像素阳极11的引线会对第一显示区AA1中像素发光单元的数量带来影响。如图2所示，用于连接在阵列基板上投影不重叠的多路分配单元13与像素阳极11的第二引线15超出该像素阳极11。即用于连接在阵列基板上投影不重叠的多路分配单元13与像素阳极11的第二引线15在阵列基板上的至少部分投影，不与该像素阳极11在阵列基板上的投影重叠。图1和图2所示的阵列基板可通过多路分配单元13利用一条不超出像素阳极11的第二引线15和一条超出像素阳极11的第二引线15驱动两个像素阳极11。可将超出像素阳极11的第二引线15视为阳极引线，也就是说，可通过一条阳极引线可驱动两个像素阳极11，可在阳极引线数量一定的情况下，增加第一显示区AA1中像素阳极11的数量，即增加第一显示区AA1中像素发光单元的数量。
例如，一组像素阳极11包括一个像素阳极11，一个多路分配单元13通过两条第二引线15与两个像素阳极11电连接。每两条第二引线15中有一条未超出像素阳极11的第二引线15和一条超出像素阳极11的第二引线15。第一显示区AA1设置三十条超出像素阳极11的第二引线15，可驱动六十个像素阳极11。相对于采用图5在透光显示区的设置方式，本申请实施例中第一显示区AA1中像素阳极11的数量翻了一倍，对应地，本申请实施例中第一显示区AA1中像素发光单元的数量也翻了一倍。
在本申请实施例中，像素阳极11设置在第一显示区AA1，驱动电路12设置于第二显示区AA2。多路分配单元13与部分像素阳极11对应设 置，多路分配单元13在阵列基板上的投影与对应的像素阳极11在阵列基板上的投影重叠。用于连接在阵列基板上投影重叠的多路分配单元13和像素阳极11的第二引线15并未超出像素阳极。一个多路分配单元13通过N条第二引线15与N组像素阳极11电连接的情况下，N条第二引线15中的一条第二引线15未超出像素阳极，N条第二引线15中的N-1条第二引线15超出像素阳极11，则可利用更少的超出像素阳极11的引线驱动更多的像素阳极11，即可利用更少的超出像素阳极11的引线驱动更多像素发光单元，从而在设置的超出像素阳极11的引线的数量一定的情况下，可增加第一显示区AA1中像素阳极11的数量，即增加第一显示区AA1即透光显示区中像素发光单元的数量，减小第一显示区AA1即透光显示区内像素发光单元数量受到的限制，提高包括该阵列基板的显示面板的显示性能。
而且，在设置的超出像素阳极11的引线的数量一定的情况下，增加第一显示区AA1即透光显示区中像素发光单元的数量，也提高了第一显示区AA1即透光显示区中像素发光单元的像素密度。
在上述实施例中，多路分配单元13可与N条控制信号线电连接。多路分配单元13可用于在控制信号线提供的N个控制信号的作用下，控制N条驱动支路错开导通。在同一时刻，N条驱动支路中的一条驱动支路导通。每条驱动支路包括一条第一引线14、一条第二引线15和一组像素阳极11。例如，N＝2，则第一条驱动支路导通时，第二条驱动支路断开；第二条驱动支路导通时，第一条驱动支路断开。例如，如图6所示，N＝2，多路分配单元13与两条控制信号线17电连接。
在一些示例中，同一行像素阳极11对应设置的多路分配单元13可共用N条控制信号线，在此并不限定。通过通用N条控制信号线可进一步减少第一显示区AA1中的走线数量。
在一些示例中，控制信号线可包括时钟信号线或与驱动电路连接的发光控制信号线。时钟信号线可提供时钟信号，与同一多路分配单元13连接的两条时钟信号线提供的时钟信号的生效电平在时间上错开。与同一多路分配单元13连接的两条发光控制信号线即EM线可为第二显示区AA2 中两行驱动电路各自连接的发光控制信号线171，即与一个多路分配单元13连接的控制信号线包括对应的两行驱动电路各自连接的发光控制信号线。例如，如图7所示，N＝2，一个多路分配单元13与两条发光控制信号线171电连接。这两条发光控制信号线171分别连接第二显示区AA2中两行驱动电路。同一行像素阳极11对应设置的多路分配单元13可共用第二显示区AA2中两行驱动电路分别连接的发光控制信号线171。
如图8所示，第一显示区AA1可包括第一区域AA11和第二区域AA12。第一区域AA11位于第二显示区AA2和第二区域AA12之间。第一区域AA11可包围第二区域AA12的至少部分。与第二区域AA12相比，第一区域AA11距离第二显示区AA2更近。
上述实施例中的多路分配单元13可位于第二区域AA12。即多路分配单元13与位于第二区域AA12中的至少部分像素阳极11对应设置。如图9所示，第一区域AA11中并不设置多路分配单元13，多路分配单元13位于第二区域AA12。位于第一区域AA11中的像素阳极11可与第二显示区AA2中的驱动电路12电连接，具体地，第一区域AA11中的像素阳极11可通过引线与第二显示区AA2中的驱动电路12电连接，图9中未示出与第一区域AA11中的像素阳极11连接的驱动电路12。由于第二区域AA12的边界与第二显示区AA2的距离极近，即第一区域AA11所占第一显示区AA1的面积比例较小，第一区域AA11中像素阳极11的数量也很少，虽然第一区域AA11中像素阳极11与驱动电路12之间通过引线连接，但引线数量很少，因此第一区域AA11中像素阳极11与驱动电路的连接不会对第一显示区AA1中的像素阳极11的数量带来限制，或只会带来可忽略的极小的限制，并不会对增加第一显示区中像素发光单元的数量带来不良影响。
如图10所示，第二显示区AA2可包括第三区域AA21和第四区域AA22。第四区域AA22位于第三区域AA21与第一显示区AA1之间。第三区域AA21可视为主屏区，第四区域AA22可视为过渡区。第四区域AA22可包围第一显示区AA1的至少部分。驱动电路12具体可位于第四区域AA22。
在一些示例中，在N＞1的情况下，一个驱动电路12可通过一条第一引线14驱动N组像素阳极11，能够对应减少第四区域AA22中用于驱动第一显示区AA1像素阳极11的驱动电路12的数量，从而能够减小第四区域AA22的大小。
在一些示例中，第四区域AA22的透光率可小于第一显示区AA1的透光率，第四区域AA22的透光率可大于等于第二显示区AA2的透光率，在此并不限定。
在上述实施例中，一个多路分配单元13可包括N个薄膜晶体管。薄膜晶体管的控制端可与控制信号线电连接，薄膜晶体管的第一端可与第一引线14电连接，薄膜晶体管的第二端可与第二引线15电连接。在控制信号线17提供的控制信号的作用下，薄膜晶体管可导通或关断，以实现驱动支路的导通和断开。具体地，薄膜晶体管的控制端可为栅极，第一端可为源极，第二端可为漏极；或者，薄膜晶体管的控制端可为栅极，第一端可为漏极，第二端可为源极，在此并不限定。
如图7和图11所示，N＝2，多路分配单元13包括两个薄膜晶体管，分别记为M1和M2。薄膜晶体管M1的控制端与一行驱动电路12连接的发光控制信号线171连接，薄膜晶体管M1的第一端与第一引线14连接，薄膜晶体管M1的第二端与另一条第二引线15连接。薄膜晶体管M2的控制端与另一行驱动电路12连接的发光控制信号线171连接，薄膜晶体管M2的第一端与第一引线14连接，薄膜晶体管M2的第二端与另一条第二引线15连接。通过控制薄膜晶体管M1和M2的导通或关断，即可实现对像素阳极11的驱动。在一些示例中，薄膜晶体管M1和M2不同时导通。
上述实施例中的第一引线14和第二引线15可以为透明材料走线如氧化铟锡走线即ITO走线，也可为非透明材料走线，在此并不限定。
本申请还提供一种显示面板。该显示面板可包括上述实施例中的阵列基板。关于阵列基板的具体内容可参见上述实施例中的相关说明，能够实现上述实施例中阵列基板的技术效果，在此不再赘述。
本申请还提供一种显示装置。该显示装置包括上述实施例中的显示面板。关于显示面板中阵列基板的具体内容可参见上述实施例中的相关说 明，在此不再赘述。显示装置具体可为手机、计算机、平板电脑、电视、电子纸等具有显示功能的装置，在此并不限定。
需要明确的是，对于显示面板实施例、显示装置实施例而言，相关之处可以参见阵列基板实施例的说明部分。本申请并不局限于上文所描述并在图中示出的特定结构。本领域的技术人员可以在领会本申请的精神之后，作出各种改变、修改和添加。并且，为了简明起见，这里省略对已知技术的详细描述。

Claims (17)

  1. 一种阵列基板，具有第一显示区和第二显示区，所述第一显示区的透光率高于所述第二显示区的透光率，所述阵列基板包括：
    多个像素阳极，位于所述第一显示区，与设于所述第一显示区中的多个像素发光单元对应；
    多个驱动电路，位于所述第二显示区，用于驱动所述第一显示区中的像素发光单元发光；
    至少一个多路分配单元，位于所述第一显示区，与部分所述像素阳极对应设置，所述多路分配单元在所述阵列基板上的投影与对应地所述像素阳极在所述阵列基板上的投影重叠；
    至少一条第一引线，所述多路分配单元通过所述第一引线与所述驱动电路连接；
    多条第二引线，一个所述多路分配单元通过N条所述第二引线与N组所述像素阳极电连接，N为大于1的整数。
  2. 根据权利要求1所述的阵列基板，其中，
    所述多路分配单元与N条控制信号线电连接，用于在所述控制信号线提供的N个控制信号的作用下，控制N条驱动支路单独导通，在同一时刻，N条所述驱动支路中的一条所述驱动支路导通，一条所述驱动支路包括一条所述第一引线、一条所述第二引线和一组所述像素阳极。
  3. 根据权利要求2所述的阵列基板，其中，
    同一行所述像素阳极对应设置的所述多路分配单元共用N条所述控制信号线。
  4. 根据权利要求2所述的阵列基板，其中，
    所述多路分配单元包括N个薄膜晶体管，所述薄膜晶体管的控制端与所述控制信号线电连接，所述薄膜晶体管的第一端与所述第一引线电连接，所述薄膜晶体管的第二端与所述第二引线电连接。
  5. 根据权利要求2所述的阵列基板，其中，所述控制信号线包括时钟信号线或与所述驱动电路连接的发光控制信号线。
  6. 根据权利要求5所述的阵列基板，其中，与同一所述多路分配单元连接的两条所述时钟信号线提供的时钟信号的生效电平在时间上错开。
  7. 根据权利要求5所述的阵列基板，其中，与一个所述多路分配单元连接的所述控制信号线包括对应的两行所述驱动电路各自连接的所述发光控制信号线。
  8. 根据权利要求1所述的阵列基板，其中，N＝2，
    一个所述多路分配单元通过两条所述第二引线与两组所述像素阳极连接。
  9. 根据权利要求8所述的阵列基板，其中，与一个所述多路分配单元连接的所述控制信号线包括两行所述驱动电路各自连接的发光控制信号线。
  10. 根据权利要求1所述的阵列基板，其中，
    对于在所述阵列基板上投影重叠的所述多路分配单元和所述像素阳极，连接所述多路分配单元和所述像素阳极的所述第二引线在所述阵列基板上的投影，与所述像素阳极在所述阵列基板上的投影重叠。
  11. 根据权利要求1所述的阵列基板，其中，
    所述第一显示区包括第一区域和第二区域，所述第一区域位于所述第二显示区和所述第二区域之间，所述多路分配单元位于所述第二区域。
  12. 根据权利要求1所述的阵列基板，其中，
    所述第二显示区包括第三区域和第四区域，所述第四区域位于所述第三区域与所述第一显示区之间，所述驱动电路位于所述第四区域。
  13. 根据权利要求1或12所述的阵列基板，其中，一个所述驱动电路通过一条所述第一引线驱动N组所述像素阳极。
  14. 根据权利要求1所述的阵列基板，其中，
    一组所述像素阳极包括一个所述像素阳极或依次电连接的两个以上所述像素阳极。
  15. 根据权利要求1所述的阵列基板，其中，一组所述像素阳极中的所述像素阳极对应的像素发光单元的发光颜色相同。
  16. 一种显示面板，包括如权利要求1至15中任意一项所述的阵列 基板。
  17. 一种阵列基板，具有第一显示区和第二显示区，所述第一显示区的透光率高于所述第二显示区的透光率，所述阵列基板包括：
    多个像素阳极，位于所述第一显示区，与设于所述第一显示区中的多个像素发光单元对应；
    多个驱动电路，位于所述第二显示区，用于驱动所述第一显示区中的像素发光单元发光；
    多个多路分配单元，位于所述第一显示区，与部分所述像素阳极对应设置，所述多路分配单元在所述阵列基板上的投影与对应地所述像素阳极在所述阵列基板上的投影重叠；
    多条第一引线，所述多路分配单元通过所述第一引线与所述驱动电路连接；
    多条第二引线，一个所述多路分配单元通过N条所述第二引线与N组所述像素阳极电连接，N等于1。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007299012A (ja) * 2007-07-24 2007-11-15 Semiconductor Energy Lab Co Ltd 表示装置
CN111162199A (zh) * 2020-01-02 2020-05-15 昆山国显光电有限公司 显示面板及显示装置
CN111785761A (zh) * 2020-07-20 2020-10-16 武汉天马微电子有限公司 一种显示面板及显示装置
CN112117320A (zh) * 2020-09-30 2020-12-22 武汉天马微电子有限公司 一种显示面板和显示装置
CN113053981A (zh) * 2021-03-15 2021-06-29 京东方科技集团股份有限公司 阵列基板、其制作方法、显示面板及显示装置
CN113920879A (zh) * 2021-10-21 2022-01-11 合肥维信诺科技有限公司 阵列基板、显示面板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007299012A (ja) * 2007-07-24 2007-11-15 Semiconductor Energy Lab Co Ltd 表示装置
CN111162199A (zh) * 2020-01-02 2020-05-15 昆山国显光电有限公司 显示面板及显示装置
CN111785761A (zh) * 2020-07-20 2020-10-16 武汉天马微电子有限公司 一种显示面板及显示装置
CN112117320A (zh) * 2020-09-30 2020-12-22 武汉天马微电子有限公司 一种显示面板和显示装置
CN113053981A (zh) * 2021-03-15 2021-06-29 京东方科技集团股份有限公司 阵列基板、其制作方法、显示面板及显示装置
CN113920879A (zh) * 2021-10-21 2022-01-11 合肥维信诺科技有限公司 阵列基板、显示面板及显示装置

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