WO2023039918A1 - 一种GaN基沟槽金属氧化物肖特基势垒二极管及其制备方法 - Google Patents

一种GaN基沟槽金属氧化物肖特基势垒二极管及其制备方法 Download PDF

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WO2023039918A1
WO2023039918A1 PCT/CN2021/119549 CN2021119549W WO2023039918A1 WO 2023039918 A1 WO2023039918 A1 WO 2023039918A1 CN 2021119549 W CN2021119549 W CN 2021119549W WO 2023039918 A1 WO2023039918 A1 WO 2023039918A1
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layer
gan
concentration
doped epitaxial
trench
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French (fr)
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刘扬
周毓昊
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中山大学
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Definitions

  • the invention belongs to the field of semiconductor power electronic devices, in particular to a GaN-based trench metal oxide Schottky barrier diode and a preparation method thereof.
  • Schottky diodes have the advantages of forward voltage drop and high switching frequency, and are widely used in various fields of power electronics, such as switching power supplies and drive circuits.
  • Traditional Schottky diodes are mostly made of Si materials. Silicon-based power devices have reached their theoretical limit, and the power density growth tends to be saturated, which can no longer meet people's needs for high-voltage and high-power density electronic products.
  • GaN material has high critical breakdown field strength and high electron mobility, so it has a large Baliga figure of merit (BFOM), which can fundamentally break through the theoretical limit of Si devices in terms of physical characteristics. Therefore, the development of GaN-based Schottky diodes is of great value.
  • BFOM Baliga figure of merit
  • the traditional Schottky diode also has the disadvantage of large reverse leakage, which will cause soft breakdown of the device and reduce the breakdown voltage. This is due to the image force barrier lowering effect and tunneling leakage of the Schottky junction under strong reverse bias.
  • the method adopted is to use the principle of charge coupling to shield the depletion region under the Schottky junction, thereby reducing the electric field on the surface of the Schottky junction.
  • Devices using this principle initially had junction barrier Schottky diodes (JBS), and later developed trench MOS barrier Schottky diodes (TMBS).
  • the working principle of the TMBS device is as follows: under forward bias, the Schottky junction is turned on, and the turn-on voltage is small, which retains the excellent forward conduction characteristics of the Schottky diode; The N-type epitaxial layer is depleted to reduce the surface electric field, thereby reducing the leakage current and increasing the breakdown voltage of the device.
  • the TMBS structure has the following advantages: 1.
  • the preparation process is simple, there is no need to form a p-GaN region, and the ion implantation or epitaxial p-GaN process steps are omitted, and only a layer of dielectric needs to be deposited after etching the trench layer, which greatly simplifies the process flow; 2.
  • JBS relies on the lateral depletion expansion of the pn junction to pinch off the channel, but due to the formation of the p-GaN region , the doping is not uniform, and the acceptor impurities on the sidewall are much less than those at the bottom of the trench, which leads to insufficient lateral depletion of the JBS and a decrease in the ability to shield the surface electric field of the Schottky junction.
  • the MOS structure is not troubled by this , the lateral depletion effect is stronger.
  • High-performance TMBS devices can achieve a good trade-off between forward conduction resistance and breakdown voltage.
  • GaN-based TMBS There have been some reports on GaN-based TMBS, but most of them focus on how to improve the breakdown voltage.
  • the main problems faced by GaN-based TMBS are the following two points: 1.
  • the electric field in the dielectric layer at the corner of the trench of GaN-based TMBS device is very large. Under long-term reverse bias, this will cause fatigue of the dielectric layer, resulting in unreliability; 2. Weak anti-surge capability.
  • power devices When power devices are used in practical electronic circuits, they often encounter current overshoot or oscillation, which can easily lead to device burnout.
  • the TMBS device is a unipolar device, the conduction voltage drop will increase significantly when working in a state of high current density, resulting in a decrease in device surge reliability.
  • the common measure is to use a surge protection device to bypass the surge to the ground through the protection device.
  • the introduction of the protection device will increase the overall volume, which is not conducive to integration. Therefore, it is very important to improve the anti-surge capability of the TMBS device itself.
  • the present invention provides a GaN-based trench metal oxide Schottky barrier diode and a preparation method thereof.
  • the technical solution adopted in the present invention is: a GaN-based trench metal oxide Schottky barrier diode, the diode includes from bottom to top: an ohmic contact metal layer covering the substrate—the cathode; GaN Self-supporting substrate; n-type lightly doped epitaxial layer, the upper surface of n-type lightly doped epitaxial layer is formed with multiple parallel groove structures; p-type high-concentration GaN layer at the bottom of the groove; the inner surface of the groove The dielectric layer; the metal layer on the upper surface - the anode.
  • the dielectric layer covers the inner wall of the trench and the top of the p-type high-concentration GaN layer, and a window is opened at a middle position above the p-type high-concentration GaN layer.
  • the dielectric layer there is no dielectric layer above the p-type high-concentration GaN layer, only the dielectric layer on the sidewall of the trench remains, and the dielectric layer extends to the mesa of the n-type lightly doped epitaxial layer.
  • the inclination angle of the mesa of the diode is less than 90 degrees, and the metal layer—the anode completely fills the entire trench.
  • the sidewall of the trench also has a p-type high-concentration GaN layer.
  • the substrate is an n-type GaN self-supporting substrate; the resistivity range of the substrate is 0.001-0.05 ⁇ .cm; the thickness is 350 ⁇ m-400 ⁇ m.
  • the n-type lightly doped epitaxial layer is an unintentionally doped epitaxial layer, a Si-doped epitaxial layer, or an As-doped epitaxial layer; the thickness is 1 ⁇ m to 30 ⁇ m, and the doping concentration is 1 ⁇ 10 14 cm -3 ⁇ 5 ⁇ 10 17 cm -3 .
  • the p-type high-concentration GaN layer is an epitaxially formed p-GaN material, with a thickness of 0.2 ⁇ m to 2 ⁇ m, and a hole concentration of 1 ⁇ 10 16 cm -3 to 1 ⁇ 10 19 cm -3 .
  • the dielectric layer is SiO 2 , Al 2 O 3 , Si 3 N 4 , or HfO 2 , with a thickness of 0.05 ⁇ m ⁇ 0.6 ⁇ m.
  • the ohmic contact metal layer covering the substrate - cathode material is Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy or Ti Any of the /Al/Ti/TiN alloys.
  • the metal layer covering the upper surface of the device—the anode material is one of Ni, Au, Be, Pt, Pd or a stacked structure thereof.
  • the present invention also provides a method for manufacturing a GaN-based trench metal oxide Schottky barrier diode, comprising the following steps:
  • Photolithographic development defines the position of the contact hole window of the dielectric layer, and removes the dielectric layer at the window with buffered hydrofluoric acid to expose the p-type high-concentration GaN layer;
  • an epitaxial method is used to form a p-GaN region with a higher concentration at the bottom of the trench; in order to solve the GaN
  • a contact window is first opened on the dielectric layer, and then the deposited anode metal is connected to the p-GaN region through the contact window, so that minority carrier injection can occur in the drift region and generate electrical conductivity. modulation phenomenon.
  • the n-type lightly doped epitaxial layer and the p-type high-concentration GaN layer of the device can also be epitaxially grown by MBE or HVPE.
  • the deposition of the dielectric layer can also be realized by PECVD, HDPCVD, LPCVD.
  • etching the n-type lightly doped epitaxial layer can also be realized by ICP, reactive ion etching, or TMAH wet etching.
  • step S8 high-temperature thermal oxidation is performed after metal evaporation, and the Ni/Au metal forms a Schottky contact with the n-type drift region, and forms an ohmic contact with the p-type high-concentration GaN layer .
  • the depth of the groove region of the n-type lightly doped epitaxial layer is 1 ⁇ m ⁇ 6 ⁇ m, and the width of the groove is 2 ⁇ m.
  • the p-type high-concentration GaN layer includes a plurality of GaN strips arranged in parallel, the width of the GaN strips is 2 ⁇ m, adjacent to the GaN strips The pitch is 1 ⁇ m to 4 ⁇ m.
  • the step S2 specifically includes:
  • the p-type high-concentration GaN layer may also be etched first, and then the n-type lightly doped epitaxial layer is selectively epitaxially grown.
  • the present invention first opens a contact window on the dielectric layer, and then the deposited anode metal is connected to the p-type high-concentration GaN layer through the contact window, and the p-type high-concentration GaN layer is connected to the n-type GaN layer.
  • the lightly doped epitaxial layer forms a pn junction.
  • the forward bias voltage reaches about 0.7V
  • the Schottky junction is first turned on; when the forward voltage reaches about 3V, the pn junction is also turned on, forming an additional current discharge path, which can be used when the device encounters a short-term voltage pulse or current When pulsed, it absorbs a large current to prevent the device from burning out;
  • the invention first epitaxially p-type high-concentration GaN layer at the bottom of the trench, avoiding the problems of lattice damage and low hole concentration caused by ion implantation, and can obtain p-GaN with higher concentration area, and then deposit a dielectric layer on the p-type high-concentration GaN layer.
  • this preparation method can transfer the extremely high electric field peak at the corner of the dielectric layer to the pn junction interface, greatly reducing the electric field in the dielectric layer, and the longitudinal electric field distribution is more uniform, thus improving device strike. wear voltage.
  • FIG. 6 shows a schematic diagram of the overall structure of the device in Embodiment 1;
  • FIG. 7 to 8 are schematic diagrams of the process of the device in Embodiment 2 of the present invention, wherein FIG. 8 shows a schematic diagram of the overall structure of the device in Embodiment 2;
  • FIG. 15 shows a schematic diagram of the overall structure of the device in Embodiment 3;
  • Figures 16 to 18 are schematic diagrams of the process of the device in Embodiment 4 of the present invention.
  • the schematic diagram of the overall structure of the device in Embodiment 4 is shown in Figure 6, which is consistent with the schematic diagram of the overall structure of the device in Embodiment 1, except that the process steps in the manufacturing process are different;
  • FIG. 19 to 20 are schematic diagrams of the process of the device in Embodiment 5 of the present invention, wherein FIG. 20 shows a schematic diagram of the overall structure of the device in Embodiment 5.
  • a GaN-based trench metal oxide Schottky barrier diode structure in this example includes a GaN self-supporting substrate 2; an n-type lightly doped epitaxial layer 3 is arranged on the substrate ; A plurality of trench structures arranged in parallel are formed in the n-type lightly doped epitaxial layer 3, each of the trench structures includes a p-type high-concentration GaN layer formed at the bottom and a dielectric layer 5 formed on the inner surface; the dielectric layer 5 A small window is opened in the middle of the bottom of the trench; at the same time, it forms a Schottky contact with the n-type lightly doped epitaxial layer of the device, and a metal layer that forms an ohmic contact with the p-type high-concentration GaN layer—the anode 6; covering the substrate A metal layer that forms an ohmic contact on the surface—cathode 1.
  • n-type lightly doped epitaxial layer 3 is epitaxially grown on an n-type GaN low-resistivity self-supporting substrate 2 with a thickness of 1 ⁇ m to 20 ⁇ m and a doping concentration of 1 ⁇ 10 15 to 1 ⁇ 10 17 cm -3 . As shown in Figure 1.
  • the preferred doping concentration of the epitaxial layer in this example is 1 ⁇ 10 16 cm ⁇ 3 .
  • the substrate needs to be cleaned organically to remove surface impurities.
  • step 2 includes the following steps:
  • Reactive plasma etching is used to etch the epitaxial wafer, and the n-type lightly doped epitaxial layer 3 covered by the mask is etched to form grooves;
  • the photoresist 8 is removed with acetone, and the device structure is shown in FIG. 2 after completion.
  • the n-type lightly doped epitaxial layer 3 may also be etched by a reactive plasma etching (RIE) process.
  • RIE reactive plasma etching
  • different groove depths can also be obtained by changing the ICP etching time and power.
  • the mask layer 7 is removed by buffered hydrofluoric acid, and the completed structure is shown in FIG. 3 .
  • the thickness of the p-type high-concentration GaN layer is 0.2-2 ⁇ m, and the hole concentration is 1 ⁇ 10 16 to 1 ⁇ 10 19 cm -3 .
  • the p-type dopant is magnesium;
  • the p-type high-concentration GaN layer includes a plurality of GaN strips arranged in parallel, the width of the GaN strips is 2 ⁇ m, and the distance between adjacent GaN strips is 1-4 ⁇ m .
  • thermal oxidation at high temperature is required to form an ohmic contact with the p-type high-concentration GaN layer.
  • the side wall forms a MIS structure
  • the dielectric layer 5 region is deposited on the surface of the device by atomic layer deposition
  • the n-type lightly doped epitaxial layer 3 is etched by ICP to form an inclined mesa structure
  • PECVD deposits a mask layer 7 on the surface of the device, removes the photoresist 8 at the bottom of the trench after exposure and development, and retains the photoresist 8 on the top of the n-type lightly doped epitaxial layer 3 of the device and the side walls of the trench. engraving 8;
  • the p-type high-concentration GaN layer 4 has a thickness of 0.2-2 ⁇ m, and a hole concentration of 1 ⁇ 10 16 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the p-type dopant is usually magnesium.
  • the p-type high-concentration GaN layer 4 includes a plurality of GaN strips arranged in parallel, the width of the GaN strips is 2 ⁇ m, and the distance between adjacent GaN strips is 1 ⁇ 4 ⁇ m.
  • Dielectric layer 5 is formed on the side wall and bottom of the trench
  • thermal oxidation at high temperature is required to form an ohmic contact with the p-type high-concentration GaN layer.
  • the epitaxial wafer is etched by ICP, and grooves are etched in the p-type high-concentration GaN layer 4 covered by the mask layer 7. After completion, the device structure is shown in FIG. 17 ;
  • the final device structure of this embodiment is shown in Figure 20.
  • the process of this embodiment is similar to that of Embodiment 1.
  • the chamber pressure, growth time, Factors such as temperature, source flow rate, and source flux make the p-type high-concentration GaN layer 4 of a certain thickness grow on the sidewall to form the structure shown in FIG.
  • the layer 5 is opened, and the electrode is evaporated to form the device structure of this embodiment, as shown in Figure 20.
  • a special treatment is made to the dielectric layer of the device, and a small contact hole is opened to make the anode metal contact with the p-type high-concentration GaN layer 4, which significantly improves the forward anti-surge capability of the device.
  • the p-type high-concentration GaN layer 4 under the dielectric layer 5 can reduce the high electric field at the corner of the dielectric layer 5, and the longitudinal electric field distribution is more uniform, so that the reliability of the dielectric layer 5 is enhanced and the breakdown voltage is increased.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • the features defined as “first” and “second” may explicitly or implicitly include at least one of these features.
  • “plurality” means at least two, such as two, three, etc., unless otherwise specifically defined.
  • the first feature may be in direct contact with the first feature or the first and second feature may be in direct contact with the second feature through an intermediary. touch.
  • “above”, “above” and “above” the first feature on the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature.
  • “Below”, “beneath” and “beneath” the first feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is less horizontally than the second feature.

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Abstract

本发明涉及一种GaN基沟槽金属氧化物肖特基势垒二极管及其制备方法。器件结构由下到上依次包括：覆盖衬底的欧姆接触金属层即阴极；GaN自支撑衬底；n型轻掺杂外延层；平行排列的p型高浓度GaN层；沟槽内的介质层；覆盖器件上表面的金属层即阳极。本发明先通过选择区域外延方法形成p型高浓度GaN层，获得高载流子浓度的p型高浓度GaN层；再淀积介质层，对介质层开接触孔，将阳极金属通过接触孔与p型高浓度GaN层相连，形成欧姆接触。p型高浓度GaN层与底部的n型轻掺杂外延层形成pn结，大大增强了正向导通时的抗浪涌能力，同时介质层下的p型高浓度GaN层还能降低介质层拐角处的高电场，提高了介质层可靠性和器件的击穿电压。

Description

一种GaN基沟槽金属氧化物肖特基势垒二极管及其制备方法 技术领域
本发明属于半导体功率电子器件领域，特别是涉及一种GaN基沟槽金属氧化物肖特基势垒二极管及其制备方法。
背景技术
肖特基二极管具有正向压降低，开关频率高等优点，被广泛应用于功率电子各领域，如开关电源，驱动电路。传统的肖特基二极管大多基于Si材料制作，硅基功率器件已达到其理论极限，功率密度增长趋于饱和，已不能满足人们对电子产品高压高功率密度的需求。GaN材料具有高临界击穿场强，高电子迁移率，从而具有大的Baliga品质因数(BFOM),能从物理特性上根本突破Si器件的理论极限。因此，发展GaN基肖特基二极管具有重大价值。
但传统的肖特基二极管也具有反向漏电大的缺点，这会使得器件软击穿，降低击穿电压。这是由于在强反向偏压下肖特基结的镜像力势垒降低效应和隧穿漏电引起的。为了解决这个问题，采用的方法是利用电荷耦合原理，将肖特基结下的耗尽区屏蔽，从而减小肖特基结表面的电场。利用该原理的器件最开始有结势垒肖特基二极管(JBS)，后来发展出了沟槽MOS势垒肖特基二极管(TMBS)。TMBS器件工作原理为：在正向偏压下，肖特基结开启，开启电压小，保留了肖特基二极管优异的正向导通特性；在反偏压下，MOS结构对沟槽之间的N型外延层进行耗尽，降低表面电场，从而减小漏电流，提高器件击穿电压。TMBS结构相比JBS结构，有着如下优势：1、制备工艺简单，不需要形成p-GaN区域，省去了离子注入或者外延p-GaN工艺步骤，只需要刻蚀沟槽后淀积一层介质层，大大简化了工艺流程；2、屏蔽肖特基表面电场能力更强，在反向时，JBS是靠pn结横向耗尽扩展来夹断沟道，但由于p-GaN区域在形成过程中，掺杂并不均匀，侧壁的受主杂质比沟槽底部的少很多，这导致JBS横向耗尽不足，屏蔽肖特基结表面电场能力下降，相比之下，MOS结构不受这个困扰，横向耗尽作用更强。
高性能的TMBS器件能够在正向导通电阻和击穿电压取得很好的折衷关系， 已经有一些关于GaN基TMBS的报道，但大多围绕在如何提高击穿电压考虑的。而目前GaN基TMBS面临的主要问题还有以下两点：1、GaN基TMBS器件沟槽拐角处介质层内电场非常大。在长期反偏压下，这会带来介质层的疲劳，产生不可靠性；2、抗浪涌能力弱。功率器件在应用于实际的电子电路中，常常会遇到电流过冲或振荡，容易导致器件烧坏。由于TMBS器件为单极性器件，工作在高电流密度状态时导通压降会大幅增加，导致器件浪涌可靠性降低。为了提高整体电路稳定性，常常需要采取防浪涌措施，常见措施是采用浪涌保护器件，使得浪涌通过保护器件旁路到地端，但保护器件的引入会增加整体的体积，不利于集成化，所以提高TMBS器件自身的抗浪涌能力至关重要。
发明内容
本发明为克服上述现有技术中的缺陷，提供一种GaN基沟槽金属氧化物肖特基势垒二极管及其制备方法，。
为解决上述技术问题，本发明采用的技术方案是：一种GaN基沟槽金属氧化物肖特基势垒二极管，二极管由下至上依次包括：覆盖衬底的欧姆接触金属层——阴极；GaN自支撑衬底；n型轻掺杂外延层，n型轻掺杂外延层上表面形成有多个平行排列的沟槽结构；位于沟槽底部的p型高浓度GaN层；沟槽内表面的介质层；位于上表面的金属层——阳极。
在其中一个实施例中，所述的介质层覆盖沟槽内壁及p型高浓度GaN层上方，且在p型高浓度GaN层上方的中间位置开设有窗口。
在其中一个实施例中，所述的p型高浓度GaN层上方无介质层，只保留沟槽侧壁的介质层，且介质层延伸到n型轻掺杂外延层台面上。
在其中一个实施例中，所述二极管的台面倾斜角度小于90度，金属层——阳极全部填满整个沟槽。
在其中一个实施例中，所述的沟槽的侧壁也有p型高浓度GaN层。
在其中一个实施例中，所述的衬底为n型GaN自支撑衬底；衬底的电阻率范围为0.001～0.05Ω.cm；厚度为350μm～400μm。
在其中一个实施例中，所述n型轻掺杂外延层为非故意掺杂的外延层、Si掺杂外延层、或As掺杂外延层；厚度为1μm～30μm，掺杂浓度为1×10 14cm -3～5×10 17cm -3。
在其中一个实施例中，所述p型高浓度GaN层为外延形成的p-GaN材料， 厚度为0.2μm～2μm，空穴浓度为1×10 16cm -3～1×10 19cm -3。
在其中一个实施例中，所述介质层为SiO 2、Al 2O 3、Si 3N 4、或HfO 2，厚度为0.05μm～0.6μm。
在其中一个实施例中，所述覆盖衬底的欧姆接触金属层——阴极材料为Ti/Al/Ni/Au合金、Ti/Al/Ti/Au合金、Ti/Al/Mo/Au合金或Ti/Al/Ti/TiN合金中的任一种。
在其中一个实施例中，所述覆盖器件上表面的金属层——阳极材料为Ni、Au、Be、Pt、Pd中的一种或者其堆叠结构。
本发明还提供一种GaN基沟槽金属氧化物肖特基势垒二极管的制作方法，包括以下步骤：
S1.在GaN自支撑衬底上外延生长n型轻掺杂外延层；
S2.在n型轻掺杂外延层上通过PECVD淀积SiO2作为掩膜层，去除器件沟槽位置处的掩膜；
S3.对n型轻掺杂外延层进行ICP刻蚀形成沟槽，刻蚀完毕后用丙酮去除光胶；
S4.利用掩膜层SiO2作为阻挡层，外延生长一定厚度的p型高浓度GaN层；
S5.在器件上表面通过ALD淀积介质层，然后用缓冲氢氟酸去除肖特基结上的掩膜；
S6.光刻显影定义介质层接触孔窗口的位置，用缓冲氢氟酸去除窗口处的介质层，露出p型高浓度GaN层；
S7.对衬底采用电子束蒸发法或磁控溅射法蒸镀Ti/Al/Ni/Au金属，并通过退火形成欧姆接触，作为二极管阴极；
S8.在器件的正面采用电子束蒸发法或磁控溅射法蒸镀Ni/Au金属作为二极管阳极。
在本发明中，为了解决GaN基TMBS沟槽拐角处介质层内电场过大带来的可靠性问题，采用外延的方法，在沟槽的底部形成较高浓度的p-GaN区域；为了解决GaN基TMBS器件抗浪涌能力弱的问题，先在介质层上开一个接触窗口，然后淀积的阳极金属通过接触窗口与p-GaN区域相连，由此可以让漂移区发生少子的注入，产生电导调制现象。
在其中一个实施例中，所述步骤S1、S4中，器件n型轻掺杂外延层，p型高浓度GaN层还可以采用MBE、HVPE方法外延生长。
在其中一个实施例中，所述步骤S5中，对介质层进行淀积还可以采用PECVD、HDPCVD、LPCVD来实现。
在其中一个实施例中，所述步骤S3中，对n型轻掺杂外延层进行刻蚀，还可以通过ICP、反应离子刻蚀、TMAH湿法刻蚀实现。
在其中一个实施例中，所述步骤S8中，金属蒸镀完后还要进行高温热氧化，Ni/Au金属与n型漂移区形成肖特基接触，与p型高浓度GaN层形成欧姆接触。
在其中一个实施例中，所述步骤S3中，n型轻掺杂外延层沟槽区深度为1μm～6μm，沟槽宽度为2μm。
在其中一个实施例中，所述步骤S4中，所述p型高浓度GaN层包括多个平行排列的GaN条状体，所述GaN条状体宽度为2μm，相邻所述GaN条状体间距为1μm～4μm。
在其中一个实施例中，所述的步骤S2具体包括：
S21.使用PECVD在n型轻掺杂外延层上沉积1μm～20μm的SiO2掩膜层；
S22.在要刻蚀形成沟槽的位置的掩膜层上通过光刻开窗口；
S23.使用缓冲氢氟酸去除未被光刻胶覆盖的掩膜层。
在其中一个实施例中，还可以先刻蚀p型高浓度GaN层，再选区外延生长n型轻掺杂外延层。
与现有技术相比，有益效果是：
1、提高器件本身的抗浪涌能力：本发明先在介质层上开一个接触窗口，然后淀积的阳极金属通过接触窗口与p型高浓度GaN层相连，p型高浓度GaN层与n型轻掺杂外延层形成pn结。当正向偏压到达0.7V左右，肖特基结率先开启；当正向电压达到3V左右，pn结也开启，形成额外的电流泄放通路，可以在器件遇到短时间的电压脉冲或电流脉冲时，吸收大电流，防止器件烧毁；
2、提高介质层的可靠性：本发明先在沟槽底部外延p型高浓度GaN层，避免离子注入带来的晶格损伤和空穴浓度低的问题，能获得更高浓度的p-GaN区域，再在p型高浓度GaN层上淀积介质层。相比于单一介质层，这种制备方法能够将介质层拐角处的极高电场峰值转移到pn结界面，大大减小了介质层中的电场，且纵向电场分布更加均匀，因此提高了器件击穿电压。
附图说明
图1至图6是本发明实施例1的器件的工艺过程示意图，其中图6表示实施例1中器件的整体结构示意图；
图7至图8是本发明实施例2的器件的工艺过程示意图，其中图8表示实施例2中器件的整体结构示意图；
图9至图15是本发明实施例3的器件的工艺过程示意图，其中图15表示实施例3中器件的整体结构示意图；
图16至图18是本发明实施例4的器件的工艺过程示意图，实施例4中器件的整体结构示意图为图6，与实施例1的器件整体结构示意图一致，只是制造过程中工艺步骤不同；
图19至图20是本发明实施例5的器件的工艺过程示意图，其中图20表示实施例5中器件的整体结构示意图。
附图标记：1、阴极；2、衬底；3、n型轻掺杂外延层；4、p型高浓度GaN层；5、介质层；6、阳极；7、掩膜层；8、光刻胶。
具体实施方式
附图仅用于示例性说明，不能理解为对本发明的限制；为了更好说明本实施例，附图某些部件会有省略、放大或缩小，并不代表实际产品的尺寸；对于本领域技术人员来说，附图中某些公知结构及其说明可能省略是可以理解的。附图中描述位置关系仅用于示例性说明，不能理解为对本发明的限制。
实施例1：
如图6所示，本实例中的一种GaN基沟槽金属氧化物肖特基势垒二极管结构，它包括GaN自支撑衬底2；在衬底上设置有n型轻掺杂外延层3；在n型轻掺杂外延层3中形成有多个平行排列的沟槽结构，各所述沟槽结构包括在底部形成的p型高浓度GaN层和内部表面形成的介质层5；介质层5在沟槽底部中间位置开了一个小窗口；同时与器件n型轻掺杂外延层形成肖特基接触，与p型高浓度GaN层形成欧姆接触的金属层—阳极6；覆盖在衬底表面形成欧姆接触的金属层—阴极1。
本实施例的具体制备方法，如图1至图6所示，包括以下步骤：
1.初始外延结构形成
在n型GaN低电阻率自支撑衬底2上外延生长n型轻掺杂外延层3，厚度 为1μm～20μm，掺杂浓度为1×10 15～1×10 17cm -3，完成后结构如图1所示。
本实例优选的外延层掺杂浓度为1×10 16cm -3。
需要说明的是，在生长n型轻掺杂外延层之前，还需对衬底进行有机清理，以去除表面杂质。
2.在n型轻掺杂外延层内形成沟槽结构
进一步地，步骤2包括以下步骤：
2.1.在n型轻掺杂外延层3上通过PECVD淀积SiO 2作为掩膜层7；
2.2.在掩膜层7上涂覆光刻胶8，曝光显影形成用于沟槽刻蚀的窗口，使用缓冲氢氟酸选择性去除掩膜层7；
2.3.采用反应等离子体刻蚀(ICP)对外延片进行刻蚀，无掩膜覆盖的n型轻掺杂外延层3被刻蚀出沟槽；
2.4.采用丙酮去除光刻胶8，完成后器件结构如图2所示。
其中，还可以采用反应等离子体刻蚀(RIE)工艺来刻蚀n型轻掺杂外延层3。
另外，还可以通过改变ICP刻蚀时间和功率得到不同的沟槽深度。
3.在沟槽底部外延形成p型高浓度GaN层4
3.1.将外延片放入MOCVD设备中，外延生长p型高浓度GaN层；
3.2.采用缓冲氢氟酸去除掩膜层7，完成后结构如图3所示。
其中，p型高浓度GaN层厚度为0.2～2μm，空穴浓度为1×10 16～1×10 19cm -3。
另外，p型掺杂剂为镁；p型高浓度GaN层包括多个平行排列的GaN条状体，所述GaN条状体宽度为2μm，相邻所述GaN条状体间距为1～4μm。
4.在沟槽侧壁和底部形成介质层5
4.1.通过ALD在器件正面淀积介质层5；
4.2.在器件正面涂覆光刻胶，再曝光显影去除台面的光刻胶；
4.3.介质层5刻蚀，去除覆盖在台面上的介质层5；
4.4.采用丙酮去除沟槽内剩余光刻胶8，再对表面进行有机清洗；完成后的器件如图4所示。
5.介质层5开孔
5.1.在器件正面涂覆光刻胶8，再曝光显影形成介质层5接触孔窗口；
5.2.用缓冲氢氟酸去除未被光刻胶遮蔽的介质层5；
5.3.用丙酮去除剩余的光刻胶8，完成后器件结构如图5所示。
6.电极蒸镀
6.1.在外延片的背面蒸镀Ti/Al/Ni/Au形成欧姆接触，作为器件的阴极1；
6.2.在正面蒸镀Ni/Au金属，与n型轻掺杂外延层3形成肖特基接触，通过介质层5接触孔与p型高浓度GaN层形成欧姆接触，完成后器件结构如图6所示。
具体地，蒸镀完Ni/Au金属后，还需在高温下进行热氧化使其与p型高浓度GaN层形成欧姆接触。
实施例2
本实施例最终器件结构如图7所示，与实施例1相比，区别在于实施例1中器件p型高浓度GaN层4外延完成后，在本实施例中进行以下工艺步骤：
1.侧壁形成MIS结构
1.1.采用原子层淀积法在器件表面淀积介质层5区域；
1.2.在介质层5上涂覆光刻胶，曝光显影后去除器件n型轻掺杂外延层3台顶和p型高浓度GaN层上的光刻胶；
1.3.采用缓冲氢氟酸刻蚀去除未被光刻胶覆盖的介质层5；
1.4.采用丙酮去除光刻胶，完成后器件结构如图7所示.
2.电极蒸镀
2.1.在外延片的背面蒸镀Ti/Al/Ni/Au形成欧姆接触，作为器件的阴极1；
2.2.在正面蒸镀Ni/Au或者Pd金属，与n型轻掺杂外延层3形成肖特基接触，与p型高浓度GaN层4形成欧姆接触，完成后器件结构如图8所示。
实施例3
本实施例最终器件结构如图12所示，与实施例1相比，区别在于初始外延结构形成后的沟槽刻蚀步骤2，其余步骤与实施例1类似，在本实施例中进行以下工艺步骤：
1.在n型轻掺杂外延层3内形成沟槽结构
1.1.在n型轻掺杂外延层3上涂覆4～6μm厚的光刻胶8，器件结构如图9所示；
1.2.将晶片放置在温度恒定的加热板上加热，使光刻胶8快速回流，器件结构如图10所示；
1.3.利用光刻胶8作为阻挡层，采用ICP刻蚀n型轻掺杂外延层3，形成倾斜台面结构；
1.4.采用丙酮去除光刻胶8，完成后器件结构如图11所示.
2.在沟槽底部外延形成p型高浓度GaN层4
2.1.PECVD在器件表面淀积掩膜层7，曝光显影后去除曝光显影后去除沟槽底部的光刻胶8，保留器件n型轻掺杂外延层3台顶和沟槽侧壁上的光刻胶8；
2.2.采用缓冲氢氟酸选择性去除沟槽底部的掩膜层7；
2.3.将外延片放入MOCVD设备中，在沟槽底部外延生长p型高浓度GaN层4；
2.4.生长完成后去除剩余的掩膜，完成后器件结构如图12。
其中，p型高浓度GaN层4厚度为0.2～2μm，空穴浓度为1×10 16～1×10 19cm -3。p型掺杂剂通常为镁。
另外，p型高浓度GaN层4包括多个平行排列的GaN条状体,所述GaN条状体宽度为2μm，相邻所述GaN条状体间距为1～4μm。
3.沟槽侧壁和底部形成介质层5
3.1.通过ALD在器件正面淀积介质层5；
3.2.在器件正面涂覆光刻胶8，再曝光显影去除台面的光刻胶8；
3.3.介质层5刻蚀，去除覆盖在台面上的介质层5；
3.4.采用丙酮去除沟槽内剩余光刻胶8，再对表面进行有机清洗；完成后的器件如图13所示。
4.介质层5开孔
4.1.在器件正面涂覆光刻胶8，再曝光显影形成介质层5接触孔窗口；
4.2.用缓冲氢氟酸去除未被光刻胶8遮蔽的介质层5；
4.3.用丙酮去除剩余的光刻胶8，完成后器件结构如图14所示。
5.电极蒸镀
5.1.在外延片的背面蒸镀Ti/Al/Ni/Au形成欧姆接触，作为器件的阴极1；
5.2.在正面蒸镀Ni/Au或者Pd金属，与n型轻掺杂外延层3形成肖特基接触，通过介质层5接触孔与p型高浓度GaN层4形成欧姆接触，完成后器件结 构如图15所示。
具体地，蒸镀完Ni/Au金属后，还需在高温下进行热氧化使其与p型高浓度GaN层形成欧姆接触。
实施例4
本实施例最终器件结构如图19所示，与实施例1最终结构一致，其制作工艺过程与实施例1不同，区别在于本实施例先刻蚀p型高浓度GaN层4，再选区外延n型轻掺杂外延层3。其余步骤与实施例1类似，在本实施例中进行以下工艺步骤：
1.初始外延结构形成
在n型GaN低电阻率自支撑衬底2上外延生长n型轻掺杂外延层3，完成后继续外延p型导电的p型高浓度GaN层4，本步骤完成后材料外延结构如图16所示。
2.选区刻蚀与外延
2.1.在器件p型高浓度GaN层4上采用PECVD沉积SiO 2作为掩膜层7；
2.2.在SiO2掩膜层7涂覆光刻胶8，曝光显影后露出要去除的掩膜层17，使用缓冲氢氟酸溶液选择性刻蚀掩膜区；
2.3.采用ICP对外延片进行刻蚀，在无掩膜层7遮盖的p型高浓度GaN层4中刻蚀出凹槽，完成后器件结构如图17所示；
2.4.将外延片放入外延室内生长n型轻掺杂外延层3，生长完成后去除剩余掩膜层7，完成后结构如图18所示。
后续步骤与实施例1的步骤一致，在此不再赘述，最终器件结构如图6所示。
实施例5
本实施例最终器件结构如图20所示，本实施例的工艺过程与实施例1类似，通过控制实施例1的步骤3：外延p型高浓度GaN层4过程中腔室气压、生长时间、温度、源的流速，源通量等因素，使得侧壁也生长一定厚度的p型高浓度GaN层4，形成图19所示结构；其余步骤与实施例1一致，淀积介质层5和介质层5开孔，蒸镀电极后，形成本实施例器件结构，如图20所示.
本发明实施例对器件的介质层做了特殊处理，开了一个小的接触孔，使阳极金属与p型高浓度GaN层4接触，显著了提高了器件正向抗浪涌能力。同时在反偏压时，介质层5下的p型高浓度GaN层4能够将介质层5拐角的高电场降低，且纵向电场分布更均匀，使得介质层5可靠性增强，击穿电压增加。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本发明的描述中，“多个”的含义是至少两个，例如两个、三个等，除非另有明确具体的限定。
在本发明中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。而且，第一特征在第二特征“之上”、“上方”和“上面”可是第一特征在第二特征正上方或斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”可以是第一特征在第二特征正下方或斜下方，或仅仅表示第一特征水平高度小于第二特征。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且， 描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本发明的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。
显然，本发明的上述实施例仅仅是为清楚地说明本发明所作的举例，而并非是对本发明的实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明权利要求的保护范围之内。

Claims (10)

  1. 一种GaN基沟槽金属氧化物肖特基势垒二极管，其特征在于，二极管由下至上依次包括：覆盖衬底(2)的欧姆接触金属层即阴极(1)；GaN自支撑衬底(2)；n型轻掺杂外延层(3)，n型轻掺杂外延层(3)上表面形成有多个平行排列的沟槽结构；位于沟槽底部的p型高浓度GaN层(4)；沟槽内表面的介质层(5)；位于二极管上表面的金属层即阳极(6)。
  2. 根据权利要求1所述的GaN基沟槽金属氧化物肖特基势垒二极管，其特征在于，所述的介质层(5)覆盖沟槽内壁及p型高浓度GaN层(4)上方，且在p型高浓度GaN层(4)上方的中间位置开设有窗口。
  3. 根据权利要求1所述的GaN基沟槽金属氧化物肖特基势垒二极管，其特征在于，所述的p型高浓度GaN层(4)上方无介质层(5)，只保留沟槽侧壁的介质层(5)，且介质层(5)延伸到n型轻掺杂外延层(3)台面上。
  4. 根据权利要求2所述的GaN基沟槽金属氧化物肖特基势垒二极管，其特征在于，所述二极管的台面倾斜角度小于90度，所述阳极(6)全部填满整个沟槽。
  5. 根据权利要求2所述的GaN基沟槽金属氧化物肖特基势垒二极管，其特征在于，所述的沟槽的侧壁也有p型高浓度GaN层(4)。
  6. 根据权利要求1至4任一项所述的GaN基沟槽金属氧化物肖特基势垒二极管，其特征在于，所述的衬底(2)为n型GaN自支撑衬底；衬底(2)的电阻率范围为0.001～0.05Ω.cm；厚度为350μm～400μm；所述n型轻掺杂外延层(3)为非故意掺杂的外延层、Si掺杂外延层、或As掺杂外延层；厚度为1μm～30μm，掺杂浓度为1×10 14cm -3～5×10 17cm -3；所述p型高浓度GaN层(4)为外延形成的p-GaN材料，厚度为0.2μm～2μm，空穴浓度为1×10 16cm -3～1×10 19cm -3；所述介质层(5)为SiO 2、Al 2O 3、Si 3N 4、或HfO 2，厚度为0.05μm～0.6μm；所述阴极(1)材料为Ti/Al/Ni/Au合金、Ti/Al/Ti/Au合金、Ti/Al/Mo/Au合金或Ti/Al/Ti/TiN合金中的任一种；所述阳极(6)材料为Ni、Au、Be、Pt、Pd中的一种或者其堆叠结构。
  7. 一种GaN基沟槽金属氧化物肖特基势垒二极管的制备方法，其特征在于，包括以下步骤：
    S1.在GaN自支撑衬底(2)上外延生长n型轻掺杂外延层(3)；
    S2.在n型轻掺杂外延层(3)上通过PECVD淀积SiO 2(7)作为掩膜层，去除器件沟槽位置处的掩膜；
    S3.对n型轻掺杂外延层(3)进行ICP刻蚀形成沟槽，刻蚀完毕后用丙酮去除光胶；
    S4.利用掩膜层SiO 2(7)作为阻挡层，外延生长一定厚度的p型高浓度GaN层(4)；
    S5.在器件上表面通过ALD淀积介质层(5)，然后用缓冲氢氟酸去除肖特基结上的掩膜；
    S6.光刻显影定义介质层(5)接触孔窗口的位置，用缓冲氢氟酸去除窗口处的介质层(5)，露出p型高浓度GaN层(4)；
    S7.对衬底(2)采用电子束蒸发法或磁控溅射法蒸镀Ti/Al/Ni/Au金属，并通过退火形成欧姆接触，作为二极管阴极(1)；
    S8.在器件的正面采用电子束蒸发法或磁控溅射法蒸镀Ni/Au金属作为二极管阳极(6)。
  8. 根据权利要求7所述的GaN基沟槽金属氧化物肖特基势垒二极管的制备方法，其特征在于，所述步骤S1、S4中，器件n型轻掺杂外延层(3)，p型高浓度GaN层(4)还可以采用MBE、HVPE方法外延生长；所述步骤S5中，对介质层(5)进行淀积还可以采用PECVD、HDPCVD、LPCVD来实现；所述步骤S3中，对n型轻掺杂外延层(3)进行刻蚀，还可以通过ICP、反应离子刻蚀、TMAH湿法刻蚀实现。
  9. 根据权利要求7所述的GaN基沟槽金属氧化物肖特基势垒二极管的制备方法，其特征在于，所述的步骤S2具体包括：
    S21.使用PECVD在n型轻掺杂外延层(3)上沉积1μm～20μm的SiO 2掩膜层；
    S22.在要刻蚀形成沟槽的位置的掩膜层(7)上通过光刻开窗口；
    S23.使用缓冲氢氟酸去除未被光刻胶覆盖的掩膜层(7)。
  10. 根据权利要求7所述的GaN基沟槽金属氧化物肖特基势垒二极管的制备方法，其特征在于，还可以先刻蚀p型高浓度GaN层(4)，再选区外延生长n型轻掺杂外延层(3)。
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CN117326520A (zh) * 2023-10-09 2024-01-02 江苏致芯微电子技术有限公司 一种车规级mems压力传感器芯片的工艺方法
CN117326520B (zh) * 2023-10-09 2024-05-28 江苏致芯微电子技术有限公司 一种车规级mems压力传感器芯片的工艺方法

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