WO2023030013A1 - 一种数据处理方法及装置 - Google Patents

一种数据处理方法及装置 Download PDF

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Publication number
WO2023030013A1
WO2023030013A1 PCT/CN2022/113098 CN2022113098W WO2023030013A1 WO 2023030013 A1 WO2023030013 A1 WO 2023030013A1 CN 2022113098 W CN2022113098 W CN 2022113098W WO 2023030013 A1 WO2023030013 A1 WO 2023030013A1
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Prior art keywords
copy
data
address
read
memory
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PCT/CN2022/113098
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English (en)
French (fr)
Inventor
张陈旭
罗小东
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP22863153.7A priority Critical patent/EP4386536A1/en
Publication of WO2023030013A1 publication Critical patent/WO2023030013A1/zh
Priority to US18/591,561 priority patent/US20240201890A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/065—Replication mechanisms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/067—Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Definitions

  • the present application relates to the field of data storage, and in particular to a data processing method and device.
  • the second submission method and the third submission method are proposed to ensure data writing
  • the atomicity of the write request makes all the data carried in this write request written or not written at all.
  • the second submission method or the third submission method is based on the log to store the data to be written in the persistent storage, resulting in high input/output (Input/Output, IO) overhead and long network round-trip time, which reduces the performance of the storage system .
  • IO input/output
  • the present application discloses a data processing method and device, which can realize the atomicity of data writing, save IO overhead, and improve the performance of a storage system.
  • the present application provides a data processing method, the method comprising: a processor or a network card of a client generates a first copy and a second copy of data; wherein, the processor communicates with the network card; and the network card uses a unilateral remote In the memory access RDMA mode, the first copy is written to the first address of the memory of the storage device, and the second copy is written to the second address of the memory.
  • the network card of the client uses unilateral RDMA to write data into the memory of the storage device, which avoids the access of the operating systems of both parties during the data writing process, reduces the memory bandwidth and computing power consumption during the data writing process, and improves Data writing efficiency.
  • the network card of the client realizes the continuous double writing of the first copy and the second copy of the data in the memory of the storage device through one-time unilateral RDMA technology, that is, writing the first copy to the first address in the memory of the storage device , after the first copy is written to the first address, the second copy is written to the second address of the memory.
  • one-time unilateral RDMA technology that is, writing the first copy to the first address in the memory of the storage device , after the first copy is written to the first address, the second copy is written to the second address of the memory.
  • the above memory is persistent memory.
  • the persistent memory can improve the speed and efficiency of the client to read and write data, and realize the persistence of the stored data.
  • the method further includes: the network card reads the first copy from the first address and the second copy from the second address in a unilateral RDMA manner; the processor or the network card verifies the read first copy and The second copy is read, and valid data is determined from the first copy read and the second copy read.
  • the processor or network card of the client may also verify the validity or integrity of the first copy read from the first address and the second copy read from the second address, so as to obtain valid data from them.
  • the processor or the network card checks the read first copy and the read second copy, and determines valid data from the read first copy and the read second copy, specifically: the processing When the controller or the network card detects that the read first copy is identical to the read second copy, it determines that the read first copy and the read second copy are valid data.
  • the read first copy is the same as the read second copy includes any one of the following two implementations:
  • the first copy read is identical to the first copy of the data
  • the second copy read is identical to the second copy of the data. In this case, it means that the first copy of the data has been successfully written into the first address of the memory, and the second copy of the data has been successfully written into the second address of the memory.
  • the processor or the network card of the client confirms that the read first copy and the read second copy are valid data, which ensures the atomicity of data writing.
  • the first copy read is the same as the initial data stored at the first address of the memory
  • the second copy read is the same as the initial data stored at the second address of the memory
  • the first address stores
  • the initial data is the data stored at the first address before the first copy of the data is written to the first address of the memory
  • the initial data stored at the second address is stored at the second address before the second copy of the data is written to the second address of the memory
  • the initial data stored at the first address is the same as the initial data stored at the second address.
  • the present application provides a data processing method, the method comprising: the network card of the storage device receives the unilateral remote memory access RDMA write request sent by the client; the unilateral RDMA write request includes the first copy of the data and the second copy, and the first address of the first copy in the memory of the storage device and the second address of the second copy in the memory; the network card writes the first copy to the first address, and writes the second copy to the second address.
  • the network card of the storage device uses one-time unilateral RDMA to realize the continuous double writing of the first copy of the data and the second copy of the data in the memory of the storage device, that is, write the first copy to the first address of the memory and then Writing the second copy to the second address of the memory not only reduces IO consumption, but also reduces data writing delay, effectively improving the performance of the storage system.
  • the memory is persistent memory.
  • the persistent memory can improve the speed and efficiency of the client to read and write data, and realize the persistence of the stored data.
  • the method further includes: the network card or processor of the storage device reads the first copy from the first address and reads the second copy from the second address; the network card or processor of the storage device verifies the read first The copy and the read second copy, when it is detected that the read first copy is inconsistent with the read second copy, perform a data overwriting operation on the data stored at the first address or the data stored at the second address.
  • the network card or processor of the storage device when the network card or processor of the storage device detects that the read first copy is inconsistent with the read second copy, it can perform a data overwriting operation so that the data stored at the first address is different from the data stored at the second address.
  • the data is the same, thus realizing the atomicity of data writing.
  • the read first copy includes the first data and the first check code
  • the read second copy includes the second data and the second check code
  • the first data is different from the second data means that the content of the first data is different from the content of the second data.
  • the difference between the first check code and the second check code means that the content of the first check code is different from the content of the second check code.
  • the length of the first data is the same as that of the second data
  • the length of the first check code is the same as that of the second check code
  • performing a data overwriting operation on the data stored at the first address or the data stored at the second address includes: when the first data is successfully verified based on the first check code, using the first data and the first check code Overwrite the data stored at the second address.
  • the success of verifying the first data based on the first verification code indicates that the read first copy is complete and valid, that is to say, the data stored at the first address is complete and valid, therefore, using the first copy
  • the first data and the first check code cover the data stored at the second address, so that the data stored at the first address is exactly the same as the data stored at the second address, thereby realizing the atomicity of data writing.
  • performing a data overwriting operation on the data stored at the first address or the data stored at the second address includes: when the first data fails to be verified based on the first verification code and the second data is verified based on the second verification code When successful, use the second data and the second check code to overwrite the data stored at the first address.
  • failure to verify the first data based on the first check code indicates that data tearing has occurred in the read first copy, that is, the data stored at the first address has data tearing.
  • the success of verifying the second data based on the second check code indicates that the read second copy is complete and valid, that is to say, the data stored at the second address is complete and valid. Therefore, using the second data and the second The check code covers the data stored at the first address, so that the data stored at the first address is exactly the same as the data stored at the second address, thereby realizing the atomicity of data writing.
  • the method further includes: when the network card or the processor of the storage device detects that the read first copy is consistent with the read second copy, determining that the read first copy and the read second copy are valid data.
  • the processor or network card of the storage device can also verify the validity or integrity of the first copy read from the first address and the second copy read from the second address, so as to obtain valid data from them for use .
  • the present application provides a data processing device, which includes: a generating unit, configured to generate a first copy and a second copy of data; a writing unit, configured to use a unilateral remote memory access RDMA method to The first address of the memory of the storage device is written into the first copy, and the second copy is written into the second address of the memory.
  • the memory is persistent memory.
  • the device further includes: a reading unit, configured to read the first copy from the first address and read the second copy from the second address in a unilateral RDMA manner; a verification unit, configured to verify the read and determine valid data from the first copy of the read and the second copy of the read.
  • a reading unit configured to read the first copy from the first address and read the second copy from the second address in a unilateral RDMA manner
  • a verification unit configured to verify the read and determine valid data from the first copy of the read and the second copy of the read.
  • the verifying unit is specifically configured to: when detecting that the read first copy is identical to the read second copy, determine that the read first copy and the read second copy are valid data.
  • the present application provides a data processing device, which includes: a receiving unit, configured to receive a unilateral remote memory access RDMA write request sent by a client; the RDMA write request includes a first copy and a second copy of data , and the first copy is at a first address in the memory of the storage device and the second copy is at a second address in the memory;
  • the writing unit is used for writing the first copy into the first address, and writing the second copy into the second address.
  • the memory is persistent memory.
  • the device further includes: a reading unit, configured to read the first copy from the first address and read the second copy from the second address; a processing unit, used to verify the read first copy and read The fetched second copy, when it is detected that the read first copy is inconsistent with the read second copy, performs a data overwriting operation on the data stored at the first address or the data stored at the second address.
  • a reading unit configured to read the first copy from the first address and read the second copy from the second address
  • a processing unit used to verify the read first copy and read The fetched second copy, when it is detected that the read first copy is inconsistent with the read second copy, performs a data overwriting operation on the data stored at the first address or the data stored at the second address.
  • the read first copy includes the first data and the first check code
  • the read second copy includes the second data and the second check code
  • the processing unit is specifically configured to: when the verification of the first data based on the first verification code is successful, use the first data and the first verification code to overwrite the data stored at the second address.
  • the processing unit is specifically configured to: use the second data and the second verification code to overwrite the The data stored at the first address.
  • the processing unit is specifically configured to: when detecting that the read first copy is consistent with the read second copy, determine that the read first copy and the read second copy are valid data.
  • the present application provides a device, which includes at least one processor and a network card, wherein the processor communicates with the network card; the processor or the network card is used to generate the first copy and the second copy of the data; the network card is used to The first copy is written to the first address of the memory of the storage device, and the second copy is written to the second address of the memory by using a unilateral remote memory access RDMA method.
  • the memory is persistent memory.
  • the network card is also used to read the first copy from the first address and the second copy from the second address in a unilateral RDMA manner; the processor or the network card is also used to verify the read first copy and read The second copy is fetched, and valid data is determined from the first copy read and the second copy read.
  • the processor or the network card is further configured to verify the read first copy and the read second copy, and determine valid data from the read first copy and the read second copy, including: processing When the controller or the network card further detects that the read first copy is identical to the read second copy, it is determined that the read first copy and the read second copy are valid data.
  • the device may be a chip or an integrated circuit, or the device described in the third aspect above.
  • the present application provides a device, the device includes a network card and a memory, wherein the network card is used to receive the unilateral remote memory access RDMA write request sent by the client; the unilateral RDMA write request includes the first copy of the data and The second copy, and the first address of the first copy in memory and the second address of the second copy in memory; the network card is used to write the first copy into the first address, and write the second copy into the second address.
  • the memory is persistent memory.
  • the data processing device further includes a processor; the processor communicates with the network card; the network card or processor is used to read the first copy from the first address and read the second copy from the second address; the network card or processor It is also used to verify the read first copy and the read second copy. When it is detected that the read first copy is inconsistent with the read second copy, the data stored at the first address or the second address is stored Perform data overwrite operation on the data.
  • the read first copy includes the first data and the first check code
  • the read second copy includes the second data and the second check code
  • performing a data overwriting operation on the data stored at the first address or the data stored at the second address includes: when the first data is successfully verified based on the first check code, using the first data and the first check code Overwrite the data stored at the second address.
  • performing a data overwriting operation on the data stored at the first address or the data stored at the second address includes: when the first data fails to be verified based on the first verification code and the second data is verified based on the second verification code When successful, use the second data and the second check code to overwrite the data stored at the first address.
  • the network card or the processor is further configured to: determine that the read first copy and the read second copy are valid data when detecting that the read first copy is identical to the read second copy.
  • the device may be a chip or an integrated circuit, or the device described in the fourth aspect above.
  • the present application provides a computer-readable storage medium, including computer instructions.
  • the computer instructions are executed by a processor, the above-mentioned first aspect or any possible implementation of the first aspect can be realized. method.
  • the present application provides a computer-readable storage medium, including computer instructions.
  • the computer instructions are executed by a processor, the above-mentioned second aspect or any possible implementation of the second aspect can be realized. method.
  • the present application provides a computer program product.
  • the computer program product When the computer program product is executed by a processor, the method in the above-mentioned first aspect or any possible embodiment of the first aspect is implemented.
  • the computer program product can be, for example, a software installation package. If the method provided by any possible design of the first aspect above needs to be used, the computer program product can be downloaded and executed on the processor. , so as to implement the first aspect or the method in any possible embodiment of the first aspect.
  • the present application provides a computer program product.
  • the computer program product When the computer program product is executed by a processor, the method in the above-mentioned second aspect or any possible embodiment of the second aspect is implemented.
  • the computer program product may be, for example, a software installation package. If the method provided by any possible design of the second aspect above needs to be used, the computer program product may be downloaded and executed on the processor. , so as to implement the second aspect or the method in any possible embodiment of the second aspect.
  • FIG. 1 is a schematic diagram of data tearing during a data writing process
  • FIG. 2 is a schematic diagram of a system architecture provided by an embodiment of the present application.
  • FIG. 3 is a flow chart of a data processing method provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of an interrupt event occurring before data is written to the first address provided by the embodiment of the present application
  • Fig. 5 is a schematic diagram of an interrupt event occurring in the process of writing data to the first address provided by the embodiment of the present application;
  • FIG. 6 is a schematic diagram of an interrupt event occurring when data is about to be written to a second address provided by an embodiment of the present application
  • FIG. 7 is a schematic diagram of an interrupt event occurring during data writing to a second address provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of an interrupt event occurring after data is written to a second address provided by an embodiment of the present application.
  • Fig. 9 is a schematic diagram of a unified operation provided by the embodiment of the present application.
  • Fig. 10 is a schematic diagram of another unified operation provided by the embodiment of the present application.
  • Fig. 11 is a flowchart of another data processing method provided by the embodiment of the present application.
  • Fig. 12 is a flowchart of another data processing method provided by the embodiment of the present application.
  • FIG. 13 is a schematic diagram of the functional structure of a device provided in this embodiment of the present application.
  • FIG. 14 is a schematic diagram of the functional structure of a device provided in this embodiment of the present application.
  • Fig. 15 is a schematic structural diagram of another device provided in this embodiment of the present application.
  • Figure 1 is a schematic diagram of data tearing during the data writing process.
  • the data "1234" and the check code “CRC0” are stored in storage area 0 at time t1.
  • the client wants to write the data “4312” and the check code “CRC1” into the storage area 0 at this moment, and assume that the system is powered off after the check code "CRC1" and the data "43” are successfully written at time t2.
  • the data stored in storage area 0 becomes "4334" and the stored check code is "CRC1". It can be seen from this that only part of the data "43” in the data "4312” is successfully written, resulting in data Tearing occurs.
  • RDMA Remote Direct Memory Access
  • the atomicity problem of data writing can be solved by two submissions.
  • the application does not directly write the data/metadata to be written, but first writes a log In the file, the log file can be called log log, in this process. Then write the data/metadata in the log file for the second time for persistent writing.
  • the writing of data/metadata in the target file is triggered according to a preset period, and this process is called a checkpoint checkpoint or commit. If a power outage or downtime occurs during this process, the file system can analyze the log after restarting, and re-execute the unsuccessful commit operation in the log until the commit is successfully executed.
  • the embodiment of the present application provides a method for writing data.
  • the data When data needs to be written into the memory space of the storage device each time, the data is continuously double-written by using one IO, and the two copies of the memory space are used to achieve more efficient use of the data.
  • the atomicity of data writing is ensured, which is conducive to improving system performance.
  • FIG. 2 exemplarily shows a schematic diagram of a system architecture.
  • This system is used to implement atomic writes of data.
  • the system includes a client and a storage device.
  • the client and the storage device are connected and communicated through a network, and the network may be a wide area network or a local area network, which is not specifically limited in this embodiment of the present application.
  • the client is used to send a one-sided RDMA write request to the storage device, and the one-sided RDMA write request is used to instruct the storage device to write the data to be written to two addresses of the memory of the storage device respectively.
  • the storage device is used to write the data to be written according to the unilateral RDMA write request and to verify the data in the two addresses, so as to ensure the atomicity of the data to be written.
  • the memory can be persistent memory (Persistent Memory, PMEM).
  • the client can use the unilateral RDMA method to continuously write the data to be written to two addresses in the memory of the storage device (for example, PMEM), and the storage device is used to The data in the address is verified and other processing. In this way, the time delay of data writing can be reduced, and the performance of the system can be improved.
  • PMEM the storage device
  • the system shown in FIG. 2 may be a distributed persistent memory system, then the number of clients shown in FIG. 2 is multiple, and the number of storage devices shown in FIG. 2 is also multiple, Any one of the multiple clients can communicate with multiple storage devices, that is, the client can send a write command to at least one storage device.
  • FIG. 2 is only an exemplary architecture diagram, but does not limit the number of network elements included in the system shown in FIG. 2 .
  • FIG. 2 may also include other functional entities.
  • the method provided in the embodiment of the present application can be applied to the communication system shown in FIG. 2 , of course, the method provided in the embodiment of the present application can also be applied to other communication systems, which is not limited in the embodiment of the present application.
  • the so-called guaranteed atomicity of data writing means: if the data write operation is successfully executed, the data in the address is the target data; If the operation fails, the data stored in the address is still the data stored before the time when the data write operation is performed. Based on this idea, a data writing method that achieves atomicity of data writing based on as little IO consumption as possible is proposed.
  • Fig. 3 is a flow chart of a data processing method provided by an embodiment of the present application, which can realize the atomicity of data writing based on as little IO overhead as possible, which is conducive to reducing network round-trip overhead and improving system performance .
  • the method includes but is not limited to the following steps:
  • S101 The client sends a unilateral RDMA write request to the storage device.
  • the first address in the memory of the storage device stores the first target data
  • the second address also stores the first target data
  • the data stored at the first address is the same as the data stored at the second address.
  • the address of the first address is different from the second address.
  • the first target data includes data 1 and check code 1, wherein check code 1 corresponds to data 1, and check code 1 is used to uniquely indicate the integrity and correctness of data 1.
  • Check code 1 can check data 1.
  • the first target data may be "1234 CRC1", where "1234" is called data 1, and "CRC1" is called check code 1.
  • the unilateral RDMA write request includes two copies of the second target data (ie, the first copy of the second target data and the second copy of the second target data), and the first copy of the second target data is stored in the memory of the storage device.
  • the unilateral RDMA write request is used to instruct the storage device to write the first copy of the second target data into the first address and write the second copy of the second target data into the second address.
  • the two pieces of second target data are completely the same.
  • the second target data includes data 2 and check code 2 .
  • the data 2 in the second target data corresponds to the check code 2, in other words, the check code 2 is used to uniquely represent the correctness and integrity of the data 2, and the data 2 can be checked based on the check code 2.
  • the second target data may be "4321 CRC2", where "4321” is called data 2, and "CRC2" is called check code 2.
  • the length of the second target data is the same as that of the first target data, but the content of the second target data is different from that of the first target data.
  • the length of the second target data is the same as the length of the first target data means: the length of the data 2 is equal to the length of the data 1, and the length of the check code 2 is equal to the length of the check code 1.
  • the content of the second object data is different from the content of the first object data means that the content of the data 2 is different from the content of the data 1, and the content of the check code 2 is different from the content of the check code 1.
  • the storage device writes the two copies of the second target data into the first address and the second address of the memory of the storage device respectively in turn, wherein writing separately refers to: writing the two copies of the second target data
  • the first copy of the second target data is written to the first address to cover the first target data in the first address
  • the second copy of the second target data in the two copies of the second target data is written to the second address to cover the second address
  • the result of the storage device writing the first copy of the second target data into the first address of the storage device may include two results.
  • the first is that the storage device writes the first copy of the second target data into the first The address is successful.
  • the storage device fails to write the first copy of the second target data into the first address.
  • the success of the storage device writing the first copy of the second target data into the first address means: the first copy of the second target data completely covers the first target data in the first address, specifically, the first copy of the second target data Data 2 completely covers the data 1 of the first target number in the first address, and the check code 2 in the first second target data completely covers the check code 1 in the first target data in the first address. Otherwise, the storage device fails to write the first copy of the second target data into the first address.
  • the success or failure of the storage device to write the second copy of the second target data to the second address please refer to the relevant description of the success or failure of the storage device to write the first copy of the second target data to the first address, which will not be repeated here. repeat.
  • the data writing operation in the storage device may specifically be a network card of the storage device.
  • the writing sequence of the data 2 and the check code 2 in the second target data is not limited. Take writing the first copy of the second target data into the first address as an example, in the first copy of the second target data, data 2 can be written into the first address before the check code 2, or the check code can be written 2 is written into the first address before the data 2, and the data 2 and the check code 2 can also be written into the first address at the same time, which is not specifically limited in this embodiment of the present application.
  • the client may perform a copy operation on the first copy of the second target data to obtain the second copy of the second target data.
  • S102 The storage device detects that an interrupt event occurs during the execution of the unilateral RDMA write request.
  • the interruption event may be a power outage event, a downtime event, a fault event, and the like.
  • the content stored at the first address and the content stored at the second address include the following situations:
  • Case 1 The interrupt event occurs before the first copy of the second target data is written into the first address.
  • the content stored at the first address is the same as the content stored at the second address.
  • an interrupt event occurs.
  • the content stored in the first address and the content stored in the second address The contents of all remain as the first target data.
  • FIG. 4 is a schematic diagram of an interrupt event occurring before data is written to the first address provided by an embodiment of the present application.
  • the content stored at the first address is the first target data "1234 CRC1”
  • the content stored at the second address is also the first target data "1234 CRC1”. If an interrupt event occurs when the second target data "4321 CRC2" is written into the first address, after the interrupt event occurs, the content stored in the first address is still the first target data "1234 CRC1", and the content stored in the second address is also The first target data "1234 CRC1".
  • Case 2 The interrupt event occurs during the process of writing the first copy of the second target data into the first address. At this time, the content stored at the first address is different from the content stored at the second address. Specifically, when the storage device writes part of the first second target data into the first address, an interrupt event occurs. At this time, the first target data stored at the first address is partially changed, and the content stored at the second address Keep as the first target data.
  • the storage device writes the first copy of the second target data into the first address, first writes the data 2, and then writes the check code 2, then the partial change of the first target data stored at the first address may include The following situations: (1) Part of the data 2 is written into the first address, and the check code 2 is not written into the first address; (2) All of the data 2 is written into the first address, and the check code 2 is not written into the first address; ( 3) All of the data 2 is written into the first address, and part of the check code 2 is written into the first address.
  • the storage device writes the first copy of the second target data into the first address, first writes the verification code 2, and then writes the data 2, then the partial change of the first target data stored at the first address may include The following situations: (1) part of the check code 2 is written into the first address, and the data 2 is not written into the first address; (2) all of the check code 2 is written into the first address, and the data 2 is not written into the first address; ( 3) All of the check code 2 is written into the first address, and part of the data 2 is written into the first address.
  • the storage device does not limit the writing sequence of data 2 and check code 2 in the first copy of second target data when writing the first copy of second target data to the first address, then in addition to the above, it also includes: data The case where 2 parts are written to the first address and 2 parts of the check code are written to the first address.
  • FIG. 5 is a schematic diagram of an interrupt event occurring during the process of writing data to the first address provided by the embodiment of the present application.
  • FIG. 5 is only an example, and does not limit When an interrupt event occurs during the process, it is only in the form shown in Figure 5.
  • the content stored at the first address is the first target data "1234 CRC1”
  • the content stored at the second address is also the first target data "1234 CRC1”.
  • Case 3 The interrupt event occurs after the first copy of the second target data is written into the first address and before the second copy of the target data is written into the second address.
  • the content stored at the first address is different from the content stored at the second address.
  • the storage device successfully writes the first copy of the second target data into the first address, but before writing the second copy of the second target data into the second address, an interrupt event occurs.
  • the first address stores The content of has been updated to the second target data; and the second copy of the second target data has not been written into the second address, then the content stored in the second address is still the first target data.
  • FIG. 6 is a schematic diagram of an interrupt event occurring when data is about to be written to the second address provided by an embodiment of the present application.
  • the content stored at the first address is the first target data "1234 CRC1”
  • the content stored at the second address is also the first target data "1234 CRC1”.
  • the first target data "1234" stored in the first address CRC1" is updated to the second target data "4321 CRC2". Since the second target data is not written into the second address, the content stored in the second address remains as the first target data "1234 CRC1".
  • the interrupt event occurs during the process of writing the second copy of the second target data into the second address.
  • the content stored at the first address is different from the content stored at the second address.
  • the storage device successfully writes the first copy of the second target data into the first address, and then writes part of the second copy of the second target data into the second address, an interrupt event occurs.
  • the first address stores The content of is updated from the first object data to the second object data, and the first object data stored at the second address is partially changed.
  • the storage device writes the second copy of the second target data into the second address, first writes the data 2, and then writes the check code 2, then the second target data stored at the second address is partially changed, which may include The following situations: (1) Part of the data 2 is written into the second address, and the check code 2 is not written into the second address; (2) All of the data 2 is written into the second address, and the check code 2 is not written into the second address; ( 3) All of the data 2 is written into the second address, and part of the check code 2 is written into the second address.
  • the storage device writes the second copy of the second target data into the second address
  • the second target data stored at the second address is partially changed, which may include The following situations: (1) part of the check code 2 is written into the second address, and the data 2 is not written into the second address; (2) all of the check code 2 is written into the second address, and the data 2 is not written into the second address; ( 3) All of the check code 2 is written into the second address, and part of the data 2 is written into the second address.
  • the storage device does not limit the writing sequence of data 2 and check code 2 in the second copy of second target data when writing the second copy of second target data into the second address, then in addition to the above, it also includes: data 2 part is written to the second address and the verification code 2 part is written to the second address.
  • FIG. 7 is a schematic diagram of an interrupt event occurring during the process of writing data to the second address provided by the embodiment of the present application.
  • FIG. 7 is only an example, and does not limit When an interrupt event occurs during the process, it is only in the form shown in Figure 7.
  • the content stored at the first address is the first target data "1234 CRC1"
  • the content stored at the second address is also the first target data "1234 CRC1”.
  • An interrupt event occurs during the writing of the second target data "4321 CRC2" to the second address, and after the interrupt event occurs, the first target data "1234 CRC1" stored at the first address has been updated to the second target data "4321 CRC2 ", the content stored at the second address remains as the first target data "1234 CRC1" is partially changed to "4321 CRC1".
  • Case 5 The interrupt event occurs after the second copy of the second target data is written into the second address. At this time, the content stored at the first address is the same as the content stored at the second address. It can be understood that, in this case, both pieces of second target data are successfully written.
  • FIG. 8 is a schematic diagram of an interrupt event occurring after data is written to the second address provided by an embodiment of the present application.
  • the content stored at the first address is the first target data "1234 CRC1”
  • the content stored at the second address is also the first target data "1234 CRC1”.
  • S103 The storage device detects the content stored at the first address and the content stored at the second address.
  • the processor or the network card of the storage device detects the content stored at the first address and the content stored at the second address.
  • the storage device detects whether the content of the first address is the same as the content of the second address, and if it is detected that the content of the first address is the same as the content of the second address, that is Indicates that the situation of writing two copies of the second target data is the above-mentioned situation 1 or 5, which proves that the atomicity of data writing is guaranteed, no additional processing is required, and the process ends; if it is detected that the content stored in the first address is the same as the The contents of the two addresses are different, which means that the two copies of the second target data are written in any of the above-mentioned cases 2-4, which proves that the atomicity of data writing cannot be guaranteed, and additional processing is required. Enter Step S104.
  • the detection of whether the content of the first address is the same as that of the second address is specifically: comparing whether the data currently stored in the first address is the same as the data currently stored in the second address, and whether the data currently stored in the first address Check whether the check code is the same as the check code currently stored in the second address.
  • the content stored in the first address is the same as the content in the second address refers to: whether the data currently stored in the first address is the same as the data currently stored in the second address, and whether the check code currently stored in the first address is the same as that in the second address
  • the check code stored in the address is the same.
  • the content stored in the first address is different from the content stored in the second address means: the data currently stored in the first address is different from the data currently stored in the second address and/or the check code currently stored in the first address is different from that stored in the second address
  • the check codes are different.
  • the data currently stored at the first address is called data 3 and the check code currently stored at the first address is called check code 3 .
  • the data currently stored at the second address is called data 4 and the check code currently stored at the second address is called check code 4 .
  • an interrupt event occurs after the first copy of the second target data is written to the first address and before the second copy of the second target data is written to the second address, so that the content stored in the first address is updated to the second target data but the content of the second address remains as the first target data.
  • the storage device checks the content stored at the first address, that is, checks the data 3 according to the check code 3. Since the content stored at the first address has been updated to the second target data, the data 3 is the same as the data 2 and the check code is the same as the data 2. The verification code 3 is the same as the verification code 2. Therefore, if the data 3 is successfully verified according to the verification code 3, it means that the content stored in the first address has not been torn.
  • an interrupt event occurs during the process of writing the second copy of the second target data to the second address, so that the content stored in the first address is updated to the second target data but the first target data stored in the second address was partially changed.
  • the storage device verifies the content stored at the first address, that is, verifies data 3 according to the verification code 3, and since the content stored at the first address is updated to the second target data, then data 3 is the same as data 2 and verified
  • the code 3 is the same as the check code 2. Therefore, if the data 3 is successfully verified according to the check code 3, it means that the content stored in the first address has not been torn.
  • the storage device detects that the content stored at the first address is different from the content stored at the second address, it further detects whether data tearing occurs in the content stored at the first address, and the detection results show that: for case 2 in S102 , data tearing occurs in the content stored at the first address; for cases 3 and 4 in S102, no data tearing occurs in the content stored at the first address.
  • the storage device When the content stored at the first address is different from the content stored at the second address, the storage device performs a unified operation on the content stored at the first address and the content stored at the second address, so that the content stored at the first address is different from the content stored at the second address.
  • the content is the same, thus ensuring the atomicity of data writing.
  • the unified operation may also be referred to as a data overwriting operation.
  • the content stored at the first address and the content stored at the second address perform a unified operation, specifically: the content stored at the second address overwrites the content stored at the first address, and the content stored at the second address remains as the first target data, then the The content stored at an address is restored to the first target data, that is to say, the content stored at the first address and the second address are both data 1 and check code 1.
  • FIG. 9 is a schematic diagram of a unified operation provided by an embodiment of the present application.
  • the content stored at the first address is "4334 CRC1", that is, the first target data stored at the first address is partially changed, and the content stored at the second address remains as the first target Data "1234 CRC1". Since the content stored at the first address is different from the content stored at the second address, and it is found that the content stored at the first address is torn, therefore, a unified operation is performed to overwrite the content stored at the first address with the content stored at the second address. content, then the contents stored in the first address and the second address are both the first target data "1234 CRC1".
  • the content stored at the first address and the content stored at the second address perform a unified operation, specifically: overwrite the content stored at the first address with the content stored at the second address, and the content stored at the first address is the second target data, then update the content stored at the second address to the second target data, also That is to say, the contents stored in the first address and the second address are both data 2 and check code 2 .
  • FIG. 10 is a schematic diagram of a unified operation provided by an embodiment of the present application.
  • the content stored at the first address is "4321 CRC2", that is, the content stored at the first address has been updated to the second target data
  • the content stored at the second address is "4321 CRC1 ”, that is, the first target data stored at the second address is partially changed.
  • the data to be written is continuously double-written on two addresses in the memory of the storage device that store the same content.
  • the data writing process is interrupted, according to the data in The writing of the two addresses performs a unified operation so that the contents stored in the two addresses are the same, thereby realizing the atomicity of data writing, reducing IO consumption, and improving system performance.
  • the atomicity of data writing can be achieved by sequentially writing the data to be written into two addresses in the memory of the storage device.
  • the client can also use the unilateral RDMA technology to sequentially write the data to be written to two addresses in the memory of the storage device.
  • the data in one computer can be transmitted to another computer using the network without the intervention of the operating systems of both parties, eliminating the overhead of copying and moving data packets between user space and kernel space and context switching, reducing Reduce memory bandwidth and computing power consumption.
  • FIG. 11 is a flowchart of another data processing method provided by the embodiment of the present application. Compared with the embodiment in FIG. 3 , in FIG. 11 , the data writing operation is performed by the client instead of the storage device in the embodiment in FIG. 3 . FIG. 11 may be independent of the FIG. 3 embodiment. The method includes but is not limited to the following steps:
  • S201 The client sequentially writes two copies of the second target data into the first address and the second address of the memory of the storage device based on the unilateral RDMA technology.
  • the first address of the memory of the storage device stores the first target data and the second address also stores the first target data, that is to say , the content stored at the first address is exactly the same as the content stored at the second address.
  • the relevant descriptions of the first target data and the second target data in S101 in the embodiment of FIG. 3 which will not be repeated here.
  • the first address is different from the second address.
  • the client uses unilateral RDMA technology to sequentially write two copies of the second target data into the first address and the second address of the memory of the storage device, wherein writing separately refers to: the client writes two copies of The first copy of the second target data in the second target data is written into the first address of the internal memory of the storage device to cover the first target data at the first address, and the second copy of the second target data in the two copies of the second target data The data is written to the second address of the memory of the storage device to cover the first target data of the second address; the sequence means: the client first writes the first copy of the second target data into the first address, and waits for the first copy of the second target data After the data is successfully written to the first address, the client writes the second copy of the second target data to the second address.
  • writing separately refers to: the client writes two copies of The first copy of the second target data in the second target data is written into the first address of the internal memory of the storage device to cover the first target data at the first address, and the second copy of the second target data in the
  • the data writing operation performed by the client may specifically be the network card of the client.
  • the use of the unilateral RDMA technology by the client means that all data write/read operations are performed by the client.
  • the client writes data into the target address of the memory of the storage device, and the storage device does not need to perform any operation during the data writing process.
  • the client acquires two addresses (for example, the first address and the second address) of the memory of the storage device and the use rights of the two addresses in advance.
  • the second set of second target data among the two sets of second target data may be obtained by the client copying the first set of second target data.
  • the two copies of the second target data are written by the client to the first address and the second address based on one IO consumption.
  • S202 An interrupt event occurs during data writing, and the storage device detects the content stored at the first address and the content stored at the second address.
  • an interruption event occurs during the process of data writing by the client.
  • the writing of the two copies of the second target data to the first address and the second address of the memory of the storage device can be specified as follows: Refer to the relevant descriptions of Case 1-Case 5 in S102 in the embodiment of FIG. 3 above, and details are not repeated here. It should be noted that the difference from S102 is that the execution subject of data writing is replaced by the client in S102 by the storage device.
  • the process of the storage device detecting the content of the first address and the content of the second address may refer to the related description of S103 in FIG.
  • S203 When the storage device detects that the content stored at the first address is different from the content stored at the second address, perform a unified operation on the content stored at the first address and the content stored at the second address. For details of this step, reference may be made to the relevant description of S104 in FIG. 3 , and details are not repeated here for the sake of brevity in the description.
  • the unilateral RDMA technology is used to continuously double-write the data to be written in the two addresses of the memory of the storage device based on one IO, which can effectively reduce the time delay of data writing and improve data security.
  • Write efficiency When the data writing process is interrupted, a unified operation is performed according to the writing of data in the two addresses so that the contents stored in the two addresses are the same, thereby realizing the atomicity of data writing, reducing the consumption of IO, and effectively Help to improve system performance.
  • FIG. 12 is a flowchart of another data processing method provided by an embodiment of the present application.
  • the embodiment described in FIG. 12 may be independent from the embodiment in FIG. 3 and FIG. 11 , or may be a supplement to the embodiment in FIG. 3 and FIG. 11 .
  • the method includes but is not limited to the following steps:
  • S301 A processor or a network card of a client generates a first copy and a second copy of data.
  • the first copy and the second copy are completely identical. It should be noted that this data is equivalent to the second target data in the embodiment of Fig. 3 or Fig. 11, wherein the first copy is the first copy of the second target data in the embodiment of Fig. 3 or Fig. 11, and the second copy That is, the second set of second target data in the embodiment shown in FIG. 3 or FIG. 11 .
  • the network card of the client uses one-time unilateral RDMA to write the first copy to the first address of the internal memory of the storage device, and writes the second copy to the second address of the internal memory.
  • the storage device is independent from the client.
  • the memory is persistent memory.
  • the network card of the client uses the unilateral RDMA method to write the first copy to the first address of the memory of the storage device and write the second copy to the second address of the memory, that is, the data written
  • the subject of execution is the client.
  • this step reference may be made to the related description of S201 in the embodiment of FIG. 11 , which will not be repeated here.
  • S302 may not be executed, and the following S3021 and S3022 are executed to replace S302.
  • S3021 The client sends a unilateral RDMA write request to the storage device.
  • S3021 may be executed.
  • the client sends a unilateral RDMA write request to the storage device.
  • the network card of the storage device receives the unilateral RDMA write request.
  • the unilateral RDMA write request includes the first copy and the second copy of the data, and the first address of the first copy in the memory of the storage device and the second address of the second copy in the memory. It can be understood that the one-sided RDMA write request is used to instruct writing the first copy into the first address of the memory of the storage device and writing the second copy into the second address of the memory.
  • S3022 The network card of the storage device writes the first copy to the first address and writes the second copy to the second address according to the unilateral RDMA write request.
  • S3021 and S3022 also realize writing the first copy of data to the first address of the memory and writing the second copy of data to the second address of the memory, which is different from the execution of data writing in S302, S3021 and S3022
  • the subject is a storage device.
  • S101 in the embodiment of FIG. 3 which will not be repeated here.
  • S303 The processor or the network card of the storage device reads the first copy from the first address and the second copy from the second address, and verifies the read first copy and the read second copy.
  • the fetched first copy is inconsistent with the read second copy, perform a data overwriting operation on the data stored at the first address or the data stored at the second address.
  • the read first copy includes the first data and the first check code
  • the read second copy includes the second data and the second check code
  • the read first copy is inconsistent with the read second copy: the first data is different from the second data; or the first check code is different from the second check code.
  • performing a data overwriting operation on the data stored at the first address or the data stored at the second address may be: when it is detected that the read When the fetched first copy is inconsistent with the read second copy, if the first data is successfully verified based on the first check code, the first data and the first check code are used to overwrite the data stored at the second address.
  • This embodiment corresponds to the content stored at the first address overwriting the content at the second address in S104 in the embodiment of FIG. 3 .
  • performing a data overwriting operation on the data stored at the first address or the data stored at the second address may be: when it is detected that the read When the fetched first copy is inconsistent with the read second copy, if the verification of the first data based on the first verification code fails and the verification of the second data based on the second verification code succeeds, use the second data and the second The check code covers the data stored at the first address.
  • This embodiment corresponds to the content stored at the second address overwriting the content stored at the first address in S104 in the embodiment of FIG. 3 .
  • the data overwriting operation is a unified operation in the embodiment shown in FIG. 3 or FIG. 11 , and its purpose is to make the data stored at the first address exactly the same as the data stored at the second address.
  • the processor or the network card of the client may also generate three copies of the data, which are respectively the first copy, the second copy and the third copy.
  • the network card of the client can use a unilateral RDMA method to write the first copy to the first address of the memory of the storage device, write the second copy to the second address of the memory, and write the second copy to the third address of the memory.
  • the client can also send a unilateral RDMA write request to the storage device to instruct the storage device to write the first copy to the first address of the memory and write the second copy to the first address of the memory according to the write RDMA write request.
  • the address and the third address for writing the third copy into the memory are not specifically limited in this embodiment of the present application.
  • a processor or network card of the storage device reads the first copy from the first address, the second copy from the second address, and the third copy from the third address, upon detecting the first copy read, the read copy
  • the read copy When there are two inconsistencies between the second copy and the read third copy, perform a data overwriting operation on at least one of the data stored at the first address, the data stored at the second address, or the data stored at the third address, so as to The data stored in the three addresses of the messenger are the same.
  • S304 The network card of the client uses unilateral RDMA to read the first copy from the first address and read the second copy from the second address.
  • S305 The processor or the network card of the client verifies the read first copy and the read second copy, and determines valid data from the read first copy and the read second copy.
  • the processor or the network card of the client when the processor or the network card of the client detects that the read first copy is identical to the read second copy, it determines that the read first copy and the read second copy are valid data.
  • the first copy read is identical to the first copy of the data
  • the second copy read is identical to the second copy of the data.
  • it means that the first copy of the data has been successfully written into the first address of the memory, and the second copy of the data has been successfully written into the second address of the memory.
  • the processor or the network card of the client confirms that the read first copy and the read second copy are valid data, which ensures the atomicity of data writing.
  • this embodiment may refer to the case 5 of S102 in the embodiment of FIG. 3 .
  • the first copy read is the same as the initial data stored at the first address of the memory
  • the second copy read is the same as the initial data stored at the second address of the memory
  • the first address stores
  • the initial data is the data stored at the first address before the first copy of the data is written to the first address of the memory
  • the initial data stored at the second address is stored at the second address before the second copy of the data is written to the second address of the memory
  • the initial data stored at the first address is the same as the initial data stored at the second address.
  • the initial data stored at the first address may be the first target data in the embodiment of FIG. 3
  • the initial data stored at the second address is also the first target data in the embodiment of FIG. 3 .
  • this embodiment may refer to the case 1 of S102 in the embodiment of FIG. 3 .
  • two copies of the data are written into the two memory addresses of the storage device by means of one-time unilateral RDMA.
  • the The data of the address performs a data overwriting operation so that the data stored in the two memory addresses are the same, so as to ensure the atomicity of data writing with as little IO consumption as possible, reduce the delay of data writing, and help improve the storage system. performance.
  • FIG. 13 is a schematic functional structure diagram of a device provided by an embodiment of the present application.
  • the device 30 includes a generating unit 310 and a writing unit 312 .
  • the device 30 can be realized by hardware, software or a combination of software and hardware.
  • the generating unit 310 is configured to generate the first copy and the second copy of the data; the writing unit 312 is configured to write the first a copy, writing the second copy to the second address of the memory.
  • the device 30 further includes a checking unit 314 and a reading unit 316, and the reading unit 316 is used to read the first copy from the first address and the second copy from the second address in a unilateral RDMA manner. Two copies; the verification unit 314 is configured to verify the read first copy and the read second copy, and determine valid data from the read first copy and the read second copy.
  • Each functional module of the device 30 can also be used to implement the method described in the embodiment of FIG. 12 .
  • the generating unit 310 can be used to perform S301
  • the writing unit 312 can be used to perform S302.
  • the reading unit 316 can be used to execute S304
  • the checking unit 314 can be used to execute S305.
  • Each functional module of the device 30 can also be used to implement the methods described in the embodiments in FIG. 3 and FIG. 11 , and for the sake of brevity in the description, details are not repeated here.
  • FIG. 14 is a schematic functional structure diagram of a device provided by an embodiment of the present application.
  • the device 40 includes a receiving unit 410 and a writing unit 412 .
  • the device 40 can be realized by hardware, software or a combination of software and hardware.
  • the receiving unit 410 is configured to receive the unilateral remote memory access RDMA write request sent by the client; the unilateral RDMA write request includes the first copy and the second copy of the data, and the first copy in the memory of the storage device The first address and the second copy are at the second address of the memory; the writing unit 412 is configured to write the first copy into the first address, and write the second copy into the second address.
  • the device 40 further includes a processing unit 414 and a reading unit 416, the reading unit 416 is used to read the first copy from the first address and read the second copy from the second address; the processing unit 414 Used to verify the read first copy and the read second copy, when it is detected that the read first copy is inconsistent with the read second copy, the data stored at the first address or the data stored at the second address Data performs a data overwrite operation.
  • Each functional module of the device 40 can also be used to implement the method described in the embodiment of FIG. 12 .
  • the receiving unit 410 and the writing unit 412 can be used to execute S3022
  • the reading unit 416 and the processing unit 414 can be used to execute S303.
  • Each functional module of the device 40 can also be used to implement the methods described in the embodiments in FIG. 3 and FIG. 11 , and for the sake of brevity in the description, details are not repeated here.
  • the embodiment of the present application also provides a device.
  • the device 50 at least includes: a processor 501 , a network card 502 and a bus 503 .
  • the processor 501 communicates with the network card 502 through the bus 503 .
  • Device 50 may be a client or a storage device as described above. It should be understood that the present application does not limit the number of processors in the device 50 .
  • the bus 503 may be a peripheral component interconnect standard (peripheral component interconnect, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus, etc.
  • PCI peripheral component interconnect
  • EISA extended industry standard architecture
  • the bus can be divided into address bus, data bus, control bus and so on. For ease of representation, only one line is used in FIG. 15 , but it does not mean that there is only one bus or one type of bus.
  • Bus 503 may include pathways for communicating information between various components of device 50 (eg, network card 502, processor 501).
  • the processor 501 may include any one or more of processors such as a central processing unit (central processing unit, CPU), a microprocessor (micro processor, MP), or a digital signal processor (digital signal processor, DSP).
  • processors such as a central processing unit (central processing unit, CPU), a microprocessor (micro processor, MP), or a digital signal processor (digital signal processor, DSP).
  • the network card 502 can be used to generate the first copy and the second copy of the data, and also be used to write to the first address of the memory of the storage device using a unilateral remote memory access RDMA method The first copy is loaded, and the second copy is written to the second address of the memory.
  • the network card 502 can be used to receive the unilateral remote memory access RDMA write request sent by the client, and the unilateral RDMA write request includes the first copy and the second copy of the data, and the first The copy is at the first address of the memory of the storage device and the second copy is at the second address of the memory; the network card 502 is also used to write the first copy to the first address, and write the second copy to the second address.
  • each module of the device 50 is used to execute the method on the client side described in the foregoing embodiment in FIG. 3 , FIG. 11 or FIG. 12 .
  • the device 50 may be one or more modules in the client executing the method shown in FIG. 12 , and the device 50 is configured to perform the following operations:
  • the network card 502 uses a unilateral remote memory access RDMA method to write the first copy to the first address of the memory of the storage device, and write the second copy to the second address of the memory.
  • the device 50 when the device 50 is the above-mentioned storage device, the device 50 further includes a memory 504, and the memory 504 may be a persistent memory (Persistent Memory, PMEM) or the like.
  • PMEM Persistent Memory
  • Each module of the device 50 may be used to execute the method on the storage device side described in the foregoing embodiment in FIG. 3 , FIG. 11 or FIG. 12 .
  • the device 50 may be one or more modules in a storage device that executes the method shown in FIG. 12 , and the device 50 is configured to perform the following operations:
  • the unilateral RDMA write request includes the first copy and the second copy of the data, and the first address and the second address of the first copy in the memory 504 of the storage device.
  • the copy is at the second address of the memory 504;
  • the first copy is written to the first address and the second copy is written to the second address via the network card 502 .
  • storage medium includes read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), programmable read-only memory (Programmable Read-only Memory, PROM), erasable programmable read-only memory ( Erasable Programmable Read Only Memory, EPROM), One-time Programmable Read-Only Memory (OTPROM), Electrically-Erasable Programmable Read-Only Memory, EEPROM, Compact Disc Read-Only Memory (CD-ROM) or other optical disk storage, magnetic disk storage, tape storage, or any other computer-readable medium that can be used to carry or store data.
  • Read-Only Memory Read-Only Memory
  • RAM Random Access Memory
  • PROM Programmable Read-only Memory
  • PROM Programmable Read-only Memory
  • EPROM Erasable Programmable Read Only Memory
  • OTPROM One-time Programmable Read-Only Memory
  • EEPROM Electrically-Erasable Programmable Read-Only Memory
  • CD-ROM Compact Disc Read-Only Memory
  • the essence of the technical solution of the present application or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of software products.
  • the computer program product is stored in a storage medium, including several instructions. So that a device (which may be a personal computer, a server, or a network device, a robot, a single-chip microcomputer, a chip, a robot, etc.) executes all or part of the steps of the methods described in the various embodiments of the present application.

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Abstract

本申请公开了一种数据处理方法及装置，该方法包括：客户端的处理器或网卡生成数据的第一副本和第二副本，由客户端的网卡使用一次单边远程内存访问RDMA方式将第一副本写入存储设备的内存的第一地址以及将第二副本写入该内存的第二地址，或者，由存储设备的网卡根据客户端发送的单边RDMA写请求将数据的第一副本和第二副本分别写入内存的第一地址和第二地址。在存储设备检测到从第一地址读取的第一副本与从第二地址读取的第二副本不一致时，对第一地址存储的数据或第二地址存储的数据执行数据覆盖操作，以使两个内存地址存储的数据相同。实施本申请，通过一次IO消耗实现了数据写入的原子性，降低了数据写入的时延，提高了存储***的性能。

Description

一种数据处理方法及装置
本申请要求于2021年9月1日提交中国知识产权局、申请号为202111022655.5、申请名称为“一种数据处理方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据存储领域，尤其涉及一种数据处理方法及装置。
背景技术
为了解决数据在写入存储介质的过程中因断电等造成的数据撕裂，即部分数据写入成功以及部分数据写入失败，提出了二次提交方式、三次提交方式等保证了数据写入的原子性，使得该次写请求携带的数据全部写入或全部未写入。
但是，二次提交方式或三次提交方式都是基于日志的方式将待写入数据在持久化存储，导致输入输出(Input/Output，IO)开销大、网络往返时间长，降低了存储***的性能。
发明内容
本申请公开了一种数据处理方法及装置，能够实现数据写入的原子性，节省IO开销，提高了存储***的性能。
第一方面，本申请提供了一种数据处理方法，该方法包括：客户端的处理器或者网卡生成数据的第一副本和第二副本；其中，处理器与网卡通信；该网卡使用一次单边远程内存访问RDMA方式向存储设备的内存的第一地址写入第一副本，向该内存的第二地址写入第二副本。
其中，客户端的网卡采用单边RDMA将数据写入存储设备的内存，避免了数据写入过程中双方操作***的接入，能够减小数据写入过程中内存的带宽、计算力的消耗，提高数据写入的效率。
上述方法中，客户端的网卡通过一次单边RDMA技术实现了数据的第一副本和第二副本在存储设备的内存中的连续双写，即将第一副本写入存储设备的内存中的第一地址，待第一副本写入第一地址之后，再将第二副本写入该内存的第二地址。如此，节省了数据写入时的IO开销，降低了数据写入的时延，有效提高了存储***的性能。
可选地，上述内存为持久化内存。
实施上述实现方式，持久化内存能提高客户端读、写数据的速度及效率，实现存储的数据的持久性。
可选地，该方法还包括：该网卡使用单边RDMA方式从第一地址读取第一副本以及从第二地址读取第二副本；该处理器或者网卡校验读取的第一副本和读取的第二副本，并从读取的第一副本和读取的第二副本中确定有效数据。
实施上述实现方式，客户端的处理器或者网卡还可以验证从第一地址读取的第一副本和从第二地址读取的第二副本的有效性或完整性，以从中取有效的数据使用。
可选地，该处理器或者网卡校验读取的第一副本和读取的第二副本，并从读取的第一副本和读取的第二副本中确定有效数据，具体是：该处理器或者网卡检测到读取的第一副本与读取的第二副本相同时，确定读取的第一副本和读取的第二副本为有效数据。
其中，读取的第一副本与读取的第二副本相同包括以下两种实施方式中的任意一种：
一具体实施中，读取的第一副本与数据的第一副本相同，且读取的第二副本与数据的第二副本相同。在此情况下，说明数据的第一副本已成功写入内存的第一地址，数据的第二副本已成功写入内存的第二地址。如此，客户端的处理器或网卡确认读取的第一副本和读取的第二副本为有效数据，确保了数据写入的原子性。
另一具体实施中，读取的第一副本与内存的第一地址存储的初始数据相同，且读取的第二副本与内存的第二地址存储的初始数据相同，其中，第一地址存储的初始数据为数据的第一副本写入内存的第一地址前该第一地址存储的数据，第二地址存储的初始数据为数据的第二副本写入内存的第二地址前该第二地址存储的数据，第一地址存储的初始数据与第二地址存储的初始数据相同。如此，客户端的处理器或网卡确认读取的第一副本和读取的第二副本为有效数据，确保了数据写入的原子性。
第二方面，本申请提供了一种数据处理方法，该方法包括：存储设备的网卡接收客户端发送的单边远程内存访问RDMA写请求；单边RDMA写请求包含数据的第一副本和第二副本，以及第一副本在存储设备的内存的第一地址和第二副本在该内存的第二地址；网卡将第一副本写入第一地址，以及将第二副本写入第二地址。
上述方法中，存储设备的网卡使用一次单边RDMA方式实现数据的第一副本和数据的第二副本在存储设备的内存中的连续双写，即将第一副本写入内存的第一地址之后再将第二副本写入内存的第二地址，不仅减少了IO消耗，还降低了数据写入的延时，有效提高了存储***的性能。
可选地，该内存为持久化内存。
实施上述实现方式，持久化内存能提高客户端读、写数据的速度及效率，实现存储的数据的持久性。
可选地，该方法还包括：存储设备的网卡或处理器从第一地址读取第一副本以及从第二地址读取第二副本；存储设备的网卡或处理器校验读取的第一副本和读取的第二副本，在检测到读取的第一副本与读取的第二副本不一致时，对第一地址存储的数据或第二地址存储的数据执行数据覆盖操作。
实施上述实现方式，存储设备的网卡或处理器在检测到读取的第一副本和读取的第二副本不一致时，可以执行数据覆盖操作以使第一地址存储的数据与第二地址存储的数据相同，从而实现了数据写入的原子性。
可选地，读取的第一副本包括第一数据和第一校验码，读取的第二副本包括第二数据和第二校验码，在满足以下至少一个条件时，读取的第一副本与读取的第二副本不一致：第一数据与第二数据不相同；或第一校验码与第二校验码不相同。
其中，第一数据与第二数据不相同是指第一数据的内容与第二数据的内容不相同。第一校验码与第二校验码不相同是指第一校验码的内容与第二校验码的内容不相同。
一具体实施中，第一数据的长度与第二数据的长度相同，第一校验码的长度与第二校验码的长度相同。
可选地，对第一地址存储的数据或第二地址存储的数据执行数据覆盖操作，包括：在基于第一校验码校验第一数据成功时，使用第一数据和第一校验码覆盖第二地址存储的数据。
实施上述实现方式，基于第一校验码校验第一数据成功说明读取的第一副本是完整、有效的，也就是说，第一地址存储的数据是完整、有效的，因此，使用第一数据和第一校验码覆盖第二地址存储的数据，以使第一地址存储的数据与第二地址存储的数据完全相同，从而实现了数据写入的原子性。
可选地，对第一地址存储的数据或第二地址存储的数据执行数据覆盖操作，包括：在基于第一校验码校验第一数据失败且基于第二校验码校验第二数据成功时，使用第二数据和第二校验码覆盖第一地址存储的数据。
实施上述实现方式，基于第一校验码校验第一数据失败说明读取的第一副本发生了数据撕裂，也就是说，第一地址存储的数据发生了数据撕裂。基于第二校验码校验第二数据成功说明读取的第二副本是完整、有效的，也就是说，第二地址存储的数据是完整、有效的，因此，使用第二数据和第二校验码覆盖第一地址存储的数据，以使第一地址存储的数据与第二地址存储的数据完全相同，从而实现了数据写入的原子性。
可选地，该方法还包括：存储设备的网卡或处理器在检测到读取的第一副本与读取的第二副本一致时，确定读取的第一副本与读取的第二副本为有效数据。
实施上述实现方式，存储设备的处理器或者网卡还可以验证从第一地址读取的第一副本和从第二地址读取的第二副本的有效性或完整性，以从中取有效的数据使用。
第三方面，本申请提供了一种数据处理装置，该装置包括：生成单元，用于生成数据的第一副本和第二副本；写入单元，用于使用一次单边远程内存访问RDMA方式向存储设备的内存的第一地址写入第一副本，向内存的第二地址写入第二副本。
可选地，该内存为持久化内存。
可选地，该装置还包括：读取单元，用于使用单边RDMA方式从第一地址读取第一副本以及从第二地址读取第二副本；校验单元，用于校验读取的第一副本和读取的第二副本，并从读取的第一副本和读取的第二副本中确定有效数据。
可选地，校验单元，具体用于：检测到读取的第一副本与读取的第二副本相同时，确定读取的第一副本和读取的第二副本为有效数据。
第四方面，本申请提供了一种数据处理装置，该装置包括：接收单元，用于接收客户端发送的单边远程内存访问RDMA写请求；RDMA写请求包含数据的第一副本和第二副本，以及第一副本在存储设备的内存的第一地址和第二副本在该内存的第二地址；
写入单元，用于将第一副本写入第一地址，以及将第二副本写入第二地址。
可选地，该内存为持久化内存。
可选地，该装置还包括：读取单元，用于从第一地址读取第一副本以及从第二地址读取第二副本；处理单元，用于校验读取的第一副本和读取的第二副本，在检测到读取的第一副本与读取的第二副本不一致时，对第一地址存储的数据或第二地址存储的数据执行数据覆盖操作。
可选地，读取的第一副本包括第一数据和第一校验码，读取的第二副本包括第二数据和第二校验码，在满足以下至少一个条件时，读取的第一副本与读取的第二副本不一致：第一数据与第二数据不相同；或第一校验码与第二校验码不相同。
可选地，处理单元，具体用于：在基于第一校验码校验第一数据成功时，使用第一数据和第一校验码覆盖第二地址存储的数据。
可选地，处理单元，具体用于：在基于第一校验码校验第一数据失败且基于第二校验码校验第二数据成功时，使用第二数据和第二校验码覆盖第一地址存储的数据。
可选地，处理单元，具体用于：在检测到读取的第一副本与读取的第二副本一致时，确定读取的第一副本与读取的第二副本为有效数据。
第五方面，本申请提供了一种装置，该装置包括至少一个处理器和网卡，其中，处理器与网卡通信；处理器或者网卡用于生成数据的第一副本和第二副本；网卡用于使用一次单边远程内存访问RDMA方式向存储设备的内存的第一地址写入第一副本，向内存的第二地址写入第二副本。
可选地，该内存为持久化内存。
可选地，网卡还用于使用单边RDMA方式从第一地址读取第一副本以及从第二地址读取第二副本；处理器或者网卡还用于校验读取的第一副本和读取的第二副本，并从读取的第一副本和读取的第二副本中确定有效数据。
可选地，处理器或者网卡还用于校验读取的第一副本和读取的第二副本，并从读取的第一副本和读取的第二副本中确定有效数据，包括：处理器或者网卡还检测到读取的第一副本与读取的第二副本相同时，确定读取的第一副本和读取的第二副本为有效数据。该装置可以是芯片或集成电路，也可以为上述第三方面所述的装置。
第六方面，本申请提供了一种装置，该装置包括网卡和内存，其中，网卡用于接收客户端发送的单边远程内存访问RDMA写请求；单边RDMA写请求包含数据的第一副本和第二副本，以及第一副本在内存的第一地址和第二副本在内存的第二地址；该网卡用于将第一副本写入第一地址，以及将第二副本写入第二地址。
可选地，该内存为持久化内存。
可选地，数据处理装置还包含处理器；该处理器与上述网卡通信；该网卡或处理器用于从第一地址读取第一副本以及从第二地址读取第二副本；网卡或处理器还用于校验读取的第一副本和读取的第二副本，在检测到读取的第一副本与读取的第二副本不一致时，对第一地址存储的数据或第二地址存储的数据执行数据覆盖操作。
可选地，读取的第一副本包括第一数据和第一校验码，读取的第二副本包括第二数据和第二校验码，在满足以下至少一个条件时，读取的第一副本与读取的第二副本不一致：第一数据与第二数据不相同；或第一校验码与第二校验码不相同。
可选地，对第一地址存储的数据或第二地址存储的数据执行数据覆盖操作，包括：在基于第一校验码校验第一数据成功时，使用第一数据和第一校验码覆盖第二地址存储的数据。
可选地，对第一地址存储的数据或第二地址存储的数据执行数据覆盖操作，包括：在基于第一校验码校验第一数据失败且基于第二校验码校验第二数据成功时，使用第二数据和第二校验码覆盖第一地址存储的数据。
可选地，该网卡或处理器还用于：检测到读取的第一副本与读取的第二副本相同时，确定读取的第一副本和读取的第二副本为有效数据。该装置可以是芯片或集成电路，也可以为上述第四方面所述的装置。
第七方面，本申请提供了一种计算机可读存储介质，包括计算机指令，当所述计算机指 令在被处理器运行时，实现上述第一方面或者第一方面的任一可能的实现方式中的方法。
第八方面，本申请提供了一种计算机可读存储介质，包括计算机指令，当所述计算机指令在被处理器运行时，实现上述第二方面或者第二方面的任一可能的实现方式中的方法。
第九方面，本申请提供了一种计算机程序产品，当该计算机程序产品被处理器执行时，实现上述第一方面或者第一方面的任一可能的实施例中的所述方法。该计算机程序产品，例如可以为一个软件安装包，在需要使用上述第一方面的任一种可能的设计提供的方法的情况下，可以下载该计算机程序产品并在处理器上执行该计算机程序产品，以实现第一方面或者第一方面的任一可能的实施例中的所述方法。
第十方面，本申请提供了一种计算机程序产品，当该计算机程序产品被处理器执行时，实现上述第二方面或者第二方面的任一可能的实施例中的所述方法。该计算机程序产品，例如可以为一个软件安装包，在需要使用上述第二方面的任一种可能的设计提供的方法的情况下，可以下载该计算机程序产品并在处理器上执行该计算机程序产品，以实现第二方面或者第二方面的任一可能的实施例中的所述方法。
附图说明
图1是一种数据写入过程发生数据撕裂的示意图；
图2是本申请实施例提供的一种***架构示意图；
图3是本申请实施例提供的一种数据处理方法的流程图；
图4是本申请实施例提供的一种数据写入第一地址之前发生中断事件的示意图；
图5是本申请实施例提供的一种数据写入第一地址的过程中发生中断事件的示意图；
图6是本申请实施例提供的一种数据正准备写入第二地址时发生中断事件的示意图；
图7是本申请实施例提供的一种数据写入第二地址的过程中发生中断事件的示意图；
图8是本申请实施例提供的一种数据写入第二地址后发生中断事件的示意图；
图9是本申请实施例提供的一种统一操作的示意图；
图10是本申请实施例提供的又一种统一操作的示意图；
图11是本申请实施例提供的又一种数据处理方法的流程图；
图12是本申请实施例提供的又一种数据处理方法的流程图；
图13是本申请本实施例提供的一种装置的功能结构示意图；
图14是本申请本实施例提供的一种装置的功能结构示意图；
图15是本申请本实施例提供的又一种设备的结构示意图。
具体实施方式
在本申请实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。本申请实施例中的说明书和权利要求书中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。
数据在写入存储介质(例如，内存、硬盘驱动器HDD)的过程中若发生了断电、宕机等事件时，导致数据的一部分写入成功，数据的另一部分写入失败，造成了存储介质中的数据的撕裂。
参见图1，图1是一种数据写入过程中发生数据撕裂的示意图，如图1所示，t1时刻存 储区域0存储有数据“1234”和校验码“CRC0”。假设在此时刻客户端欲将数据“4312”和校验码“CRC1”写入存储区域0，假设在t2时刻成功写入校验码“CRC1”和数据“43”后***发生了断电，则断电后存储区域0存储的数据变为“4334”以及存储的校验码为“CRC1”，由此可以看出，数据“4312”中仅有部分数据“43”成功写入，导致数据撕裂发生。
在客户端向存储设备的存储区域0发起远程直接内存访问(Remote Direct Memory Access,RDMA)写入操作写入数据“4312”后，若写入成功，则存储区域0存储的是数据“4312”和校验码“CRC1”，相当于数据全部写入成功；若写入失败，则期望存储区域0存储的仍然为该次写操作之前的数据，即数据“1234”和校验码“CRC0”，相当于数据全部未写入成功。如果可以保证数据全部写入成功或者数据全部未写入成功，即，不存在数据撕裂发生，就保证了数据写入的原子性。
在一种可能的实施例中，可以通过两次提交的方式解决数据写入的原子性问题，例如，应用将待写入的数据/元数据先不直接写入，而是先写入一日志文件中，该日志文件可称作日志log，在此过程中。后续第二次将该日志文件中的数据/元数据写入进行持久化写入。例如，按照预设周期触发一次目标文件中的数据/元数据的写入，这个过程叫做检查点checkpoint或者提交commit。在此过程中发生了断电或宕机，则重启后文件***可以分析日志，将日志中未成功的commit操作重新执行一遍，直至该次commit执行成功。
由此可以看出，上述解决数据写入的原子性问题的方式需要多次利用IO执行同一数据的写入，IO开销大，且在分布式内存***中应用会造成地方多次的网络往返消耗，降低了***的性能。
针对上述问题，本申请实施例提供一种数据写方法，在每次需要将数据写入存储设备的内存空间时，利用一次IO将该数据进行连续双写，通过两份内存空间实现在使用较少IO消耗的情况下确保数据写的原子性，有利于提高***的性能。
下面将结合附图，对本申请中的技术方案进行描述。
参见图2，图2示例性地给出了一种***架构示意图。该***用于实现数据的原子写。如图2所示，该***包括客户端和存储设备。其中，客户端和存储设备通过网络进行连接通信，该网络可以是广域网或局域网等，本申请实施例不做具体限定。
一具体实施中，客户端用于向存储设备发送单边RDMA写请求，单边RDMA写请求用于指示存储设备将待写入数据来连续分别地写入至存储设备的内存的两个地址。存储设备用于根据单边RDMA写请求写入待写入数据以及对两个地址中的数据进行校验等处理，以保证待写入数据写入的原子性。需要说明的是，内存可以是持久内存(Persistent Memory，PMEM)。
另一具体实施中，客户端可以采用单边RDMA方式将待写入数据写入连续分别地写入至存储设备的内存中(例如，PMEM)中的两个地址，而存储设备用于对两个地址中的数据进行校验等处理。由此可以降低数据写入的时延，提高***的性能。
在一些可能的实施例中，图2所示的***可以是分布式持久化内存***，则图2所示的客户端的数量为多个，图2所示的存储设备的数量也为多个，多个客户端中的任意一个客户端可与多个存储设备进行通信，也就是说，客户端可以向至少一个存储设备发送写指令。
需要说明的是，图2仅为示例性架构图，但不限定图2所示***包括的网元的数量。虽然图2未示出，但除图2所示的功能实体外，图2还可以包括其他功能实体。另外，本申请 实施例提供的方法可以应用于图2所示的通信***，当然本申请实施例提供的方法也可以适用其他通信***，本申请实施例对此不予限制。
在客户端向存储设备的内存的地址执行数据写入操作时，所谓保证数据写入的原子性是指：若数据写入操作执行成功，则地址中的数据为目标数据；若该数据写入操作执行失败，则地址中存储的数据仍为执行该数据写入操作的时刻之前存储的数据。基于该思想，提出一种基于尽可能少的IO消耗实现数据写的原子性的数据写方法。
参见图3，图3是本申请实施例提供的一种数据处理方法的流程图，能够基于尽可能少的IO开销实现数据写入的原子性，有利于减少网络往返的开销，提高***的性能。该方法包括但不限于以下步骤：
S101：客户端向存储设备发送单边RDMA写请求。
在本申请实施例中，存储设备的内存中的第一地址存储了第一目标数据，第二地址也存储了第一目标数据。其中，第一地址存储的数据和第二地址存储的数据是相同的。第一地址的地址与第二地址不同。
在本申请实施例中，第一目标数据包括数据1和校验码1，其中，校验码1与数据1对应，校验码1用于唯一表示数据1的完整性和正确性，基于校验码1可以校验数据1。示例性地，第一目标数据可以是“1234 CRC1”，其中，“1234”称为数据1，“CRC1”称为校验码1。
在本申请实施例中，单边RDMA写请求包含两份第二目标数据(即第一份第二目标数据和第二份第二目标数据)、第一份第二目标数据在存储设备的内存中的第一地址以及第二份第二目标数据在该内存中的第二地址。单边RDMA写请求用于指示存储设备将第一份第二目标数据写入第一地址以及将第二份第二目标数据写入第二地址。其中，两份第二目标数据是完全相同的。
在本申请实施例中，第二目标数据包括数据2和校验码2。其中，第二目标数据中的数据2与校验码2对应，换句话说，校验码2用于唯一表示数据2的正确性和完整性，基于校验码2可以校验数据2。示例性地，第二目标数据可以是“4321 CRC2”，其中，“4321”称为数据2，“CRC2”称为校验码2。
在本申请实施例中，第二目标数据的长度与第一目标数据的长度相同，但是，第二目标数据的内容与第一目标数据的内容不相同。具体地，第二目标数据的长度与第一目标数据的长度相同是指：数据2的长度与数据1的长度相等，校验码2的长度与校验码1的长度相等。第二目标数据的内容与第一目标数据的内容不相同是指，数据2的内容与数据1的内容不相同，且，校验码2的内容与校验码1的内容不相同。
在本申请实施例中，存储设备将两份第二目标数据依次分别写入存储设备的内存的第一地址和第二地址，其中，分别写入是指：将两份第二目标数据中的第一份第二目标数据写入第一地址以覆盖第一地址中的第一目标数据，将两份第二目标数据中的第二份第二目标数据写入第二地址以覆盖第二地址中的第二目标数据；依次是指：先将第一份第二目标数据写入第一地址，待第一份第二目标数据成功写入第一地址后，再将第二份第二目标数据写入第二地址。
在本申请实施例中，存储设备将第一份第二目标数据写入存储设备的第一地址的结果可能包括两种，第一种，存储设备将第一份第二目标数据写入第一地址成功，第二种，存储设 备将第一份第二目标数据写入第一地址失败。
存储设备将第一份第二目标数据写入第一地址成功是指：第一份第二目标数据完全覆盖第一地址中的第一目标数据，具体地，第一份第二目标数据中的数据2完全覆盖第一地址中的第一目标数的数据1，第一份第二目标数据中的校验码2完全覆盖第一地址中的第一目标数据中的校验码1。反之，则存储设备将第一份第二目标数据写入第一地址失败。同理，存储设备将第二份第二目标数据写入第二地址成功或者失败可分别参考存储设备将第一份第二目标数据写入第一地址成功或者失败的相关描述，在此不再赘述。
在本申请实施例中，存储设备中执行数据写入操作的具体可以是存储设备的网卡。
需要说明的是，上述例子中并不限制第二目标数据中数据2和校验码2的写入顺序。以将第一份第二目标数据写入第一地址为例，在第一份第二目标数据中，可以将数据2先于校验码2写入第一地址中，也可以将校验码2先于数据2写入第一地址中，还可以将数据2和校验码2同时写入第一地址中，本申请实施例不做具体限定。
在本申请实施例中，客户端可以对第一份第二目标数据进行复制操作获得第二份第二目标数据。
S102：存储设备检测到执行单边RDMA写请求的过程中发生中断事件。
在本申请实施例中，中断事件可以是断电事件、宕机事件以及故障事件等。
在本申请实施例中，存储设备在执行单边RDMA写请求的过程中发生中断事件时，第一地址存储的内容与第二地址存储的内容包括如下几种情况：
情况1：中断事件发生在将第一份第二目标数据写入第一地址之前。此时，第一地址存储的内容与第二地址存储的内容是相同的。具体地，存储设备接收到单边RDMA写请求后，正准备开始将第一份第二目标数据写入第一地址时，发生中断事件，此时，第一地址存储的内容和第二地址存储的内容均保持为第一目标数据。
例如，参见图4，图4是本申请实施例提供的一种数据写入第一地址之前发生中断事件的示意图。在图4中，单边RDMA写请求执行前，第一地址存储的内容为第一目标数据“1234 CRC1”，第二地址存储的内容也为第一目标数据“1234 CRC1”，在将第一份第二目标数据“4321 CRC2”写入第一地址时发生中断事件，则中断事件发生后，第一地址存储的内容仍为第一目标数据“1234 CRC1”，第二地址存储的内容也为第一目标数据“1234 CRC1”。
情况2：中断事件发生在将第一份第二目标数据写入第一地址的过程中。此时，第一地址存储的内容与第二地址存储的内容不相同。具体地，存储设备在将第一份第二目标数据中的部分写入第一地址时，发生中断事件，此时，第一地址存储的第一目标数据被部分改变，第二地址存储的内容保持为第一目标数据。
如果存储设备将第一份第二目标数据写入第一地址时，先写入数据2，然后，再写入校验码2，那么，第一地址存储的第一目标数据被部分改变可能包括以下状况：(1)数据2部分写入第一地址，校验码2未写入第一地址；(2)数据2全部写入第一地址，校验码2未写入第一地址；(3)数据2全部写入第一地址，校验码2部分写入第一地址。
如果存储设备将第一份第二目标数据写入第一地址时，先写入校验码2，然后，再写入数据2，那么，第一地址存储的第一目标数据被部分改变可能包括以下状况：(1)校验码2部分写入第一地址，数据2未写入第一地址；(2)校验码2全部写入第一地址，数据2未写入第一地址；(3)校验码2全部写入第一地址，数据2部分写入第一地址。
如果存储设备将第一份第二目标数据写入第一地址时，不限制第一份第二目标数据中数据2和校验码2的写入顺序，则除了上述情况外，还包括：数据2部分写入第一地址且校验码2部分写入第一地址这一情况。
例如，参见图5，图5是本申请实施例提供的一种数据写入第一地址的过程中发生中断事件的示意图，图5仅是一种示例，并不限定数据写入第一地址的过程中发生中断事件时仅为图5所示形式。在图5中，单边RDMA写请求执行前，第一地址存储的内容为第一目标数据“1234 CRC1”，第二地址存储的内容也为第一目标数据“1234 CRC1”，若第一份第二目标数据“4321 CRC2”写入第一地址的过程中发生中断事件，则中断事件发生后，第一地址存储的第一目标数据“1234 CRC1”被部分更改为“4334 CRC1”(即第一地址的数据1被部分改变)，第二地址存储的内容保持为第一目标数据“1234 CRC1”。
情况3：中断事件发生在将第一份第二目标数据写入第一地址之后，将第二份目标数据写入第二地址之前。此时，第一地址存储的内容与第二地址存储的内容不同。具体地，存储设备在将第一份第二目标数据成功写入第一地址后，正准备将第二份第二目标数据写入第二地址之前，发生中断事件，此时，第一地址存储的内容已更新为第二目标数据；而第二份第二目标数据未写入第二地址，则第二地址存储的内容仍为第一目标数据。
例如，参见图6，图6是本申请实施例提供的一种数据正准备写入第二地址时发生中断事件的示意图。在图6中，单边RDMA写请求执行前，第一地址存储的内容为第一目标数据“1234 CRC1”，第二地址存储的内容也为第一目标数据“1234 CRC1”，若第一份第二目标数据“4321 CRC2”成功写入第一地址后，第二份第二目标数据写入第二地址之前发生中断事件，则中断事件发生后，第一地址存储的第一目标数据“1234 CRC1”被更新为第二目标数据“4321 CRC2”，由于第二份第二目标数据未写入第二地址，故第二地址存储的内容保持为第一目标数据“1234 CRC1”。
情况4：中断事件发生在将第二份第二目标数据写入第二地址的过程中。此时，第一地址存储的内容与第二地址存储的内容不同。具体地，存储设备将第一份第二目标数据成功写入第一地址，接着将第二份第二目标数据中的部分写入第二地址时，发生中断事件，此时，第一地址存储的内容由第一目标数据更新为第二目标数据，而第二地址存储的第一目标数据被部分改变。
如果存储设备将第二份第二目标数据写入第二地址时，先写入数据2，然后，再写入校验码2，那么，第二地址存储的第二目标数据被部分改变可能包括以下状况：(1)数据2部分写入第二地址，校验码2未写入第二地址；(2)数据2全部写入第二地址，校验码2未写入第二地址；(3)数据2全部写入第二地址，校验码2部分写入第二地址。
如果存储设备将第二份第二目标数据写入第二地址时，先写入校验码2，然后，再写入数据2，那么，第二地址存储的第二目标数据被部分改变可能包括以下状况：(1)校验码2部分写入第二地址，数据2未写入第二地址；(2)校验码2全部写入第二地址，数据2未写入第二地址；(3)校验码2全部写入第二地址，数据2部分写入第二地址。
如果存储设备将第二份第二目标数据写入第二地址时，不限制第二份第二目标数据中数据2和校验码2的写入顺序，则除了上述情况外，还包括：数据2部分写入第二地址且校验码2部分写入第二地址这一情况。
例如，参见图7，图7是本申请实施例提供的一种数据写入第二地址的过程中发生中断 事件的示意图，图7仅是一种示例，并不限定数据写入第二地址的过程中发生中断事件时仅为图7所示形式。在图7中，单边RDMA写请求执行前，第一地址存储的内容为第一目标数据“1234 CRC1”，第二地址存储的内容也为第一目标数据“1234 CRC1”，若第二份第二目标数据“4321 CRC2”写入第二地址的过程中发生中断事件，则中断事件发生后，第一地址存储的第一目标数据“1234 CRC1”已被更新为第二目标数据“4321 CRC2”，第二地址存储的内容保持为第一目标数据“1234 CRC1”被部分更改为“4321 CRC1”。
情况5：中断事件发生在将第二份第二目标数据写入第二地址之后。此时，第一地址存储的内容与第二地址存储的内容是相同的。可以理解，在此情况下，两份第二目标数据均写入成功。
例如，参见图8，图8是本申请实施例提供的一种数据写入第二地址之后发生中断事件的示意图。在图8中，单边RDMA写请求执行前，第一地址存储的内容为第一目标数据“1234 CRC1”，第二地址存储的内容也为第一目标数据“1234 CRC1”，若第二份第二目标数据“4321 CRC2”写入第二地址后发生中断事件，则中断事件发生后，第一地址存储的第一目标数据“1234 CRC1”已被更新为第二目标数据“4321 CRC2”，第二地址存储的第一目标数据“1234 CRC1”也被更新为第二目标数据“4321 CRC2”，也就是说，单边RDMA写请求执行成功。
S103：存储设备对第一地址存储的内容和第二地址存储的内容进行检测。
在本申请实施例中，存储设备的处理器或网卡对第一地址存储的内容和第二地址存储的内容进行检测。
在本申请实施例中，在中断事件发生后，存储设备检测第一地址的内容与第二地址的内容是否相同，若检测到第一地址的内容与第二地址的内容相同的情况下，即表示两份第二目标数据写入的情况为上述情况1或情况5，证明保证了数据写入的原子性，不需要进行额外的处理，结束流程；若检测到第一地址存储的内容与第二地址的内容不相同，即表示两份第二目标数据写入的情况为上述情况2-情况4中的任意一种，证明没法保证数据写入的原子性，需要进行额外的处理，进入步骤S104。
在本申请实施例中，检测第一地址的内容与第二地址的内容是否相同，具体为：比较第一地址当前存储的数据与第二地址当前存储的数据是否相同，以及第一地址当前存储的校验码与第二地址当前存储的校验码是否相同。
其中，第一地址存储的内容与第二地址的内容相同是指：第一地址当前存储的数据与第二地址当前存储的数据是否相同，且，第一地址当前存储的校验码与第二地址存储的校验码相同。第一地址存储的内容与第二地址的内容不相同是指：第一地址当前存储的数据与第二地址当前存储的数据不同和/或第一地址当前存储的校验码与第二地址存储的校验码不同。
为了叙述方便，将第一地址当前存储的数据称作数据3以及将第一地址当前存储的校验码称作校验码3。将第二地址当前存储的数据称作数据4以及将第二地址当前存储的校验码称作校验码4。
针对上述情况2-情况4，即检测到第一地址存储的内容与第二地址存储的内容不同的情况下，需要进一步校验第一地址存储的内容以确定第一地址存储的内容是否发生数据撕裂：
针对S102中的情况2，即第一份第二目标数据写入第一地址的过程中发生中断事件，导致第一地址存储的第一目标数据被部分改变但第二地址存储的内容保持为第一目标数据。在此情况下，存储设备校验第一地址存储的内容，具体地，根据校验码3检验数据3，由于情 况2中第一地址存储的第一目标数据被部分改变，会发生以下任意一种情况：(1)数据3与数据1不同但校验码3与校验码1相同；(2)数据3与数据1相同但校验码3与校验码1不同；(3)数据3与数据1不同且校验码3与校验码1不同，因此，对于上述任意一种情况，根据校验码3检测数据3均失败，则说明第一地址存储的内容发生数据撕裂。可以理解，由于在情况2中第二地址存储的内容保持为第一目标数据，意味着数据4为数据1，校验码4为校验码1，因此，基于校验码4检测数据4成功，说明第二地址存储的内容未发生数据撕裂。
针对S102中的情况3，即第一份第二目标数据写入第一地址后且第二份第二目标数据写入第二地址之前发生中断事件，使得第一地址存储的内容更新为第二目标数据但第二地址的内容保持为第一目标数据。在此情况下，存储设备校验第一地址存储的内容，即根据校验码3检验数据3，由于第一地址存储的内容已更新为第二目标数据，则数据3与数据2相同且校验码3与校验码2相同，因此，根据校验码3检验数据3成功，则说明第一地址存储的内容未发生数据撕裂。
针对S102中的情况4，即第二份第二目标数据写入第二地址的过程中发生中断事件，使得第一地址存储的内容更新为第二目标数据但第二地址存储的第一目标数据被部分改变。在此情况下，存储设备校验第一地址存储的内容，即根据校验码3检验数据3，由于第一地址存储的内容更新为第二目标数据，则数据3与数据2相同且校验码3与校验码2相同，因此，根据校验码3检验数据3成功，则说明第一地址存储的内容未发生数据撕裂。
综上，存储设备在检测到第一地址存储的内容与第二地址存储的内容不同的情况下，进一步检测第一地址存储的内容是否发生数据撕裂，检测结果显示：对于S102中的情况2，第一地址存储的内容发生数据撕裂；对于S102中的情况3和情况4，第一地址存储的内容未发生数据撕裂。
S104：在检测到第一地址存储的内容与第二地址的内容不同时，存储设备对第一地址存储的内容和第二地址存储的内容执行统一操作。
在第一地址存储的内容与第二地址的内容不同时，存储设备对第一地址存储的内容和第二地址存储的内容执行统一操作，以使第一地址存储的内容与第二地址存储的内容相同，从而确保了数据写入的原子性。需要说明的是，在本申请实施例中，统一操作也可以称作数据覆盖操作。
一具体实施中，在第一地址存储的内容与第二地址的内容不同的情况下，若第一地址存储的内容发生了数据撕裂且第二地址存储的内容未发生数据撕裂，对第一地址存储的内容和第二地址存储的内容执行统一操作，具体是：将第二地址存储的内容覆盖第一地址存储的内容，且第二地址存储的内容保持为第一目标数据，则第一地址存储的内容恢复为第一目标数据，也就是说，第一地址和第二地址存储的内容均为数据1和校验码1。
例如，参见图9，图9是本申请实施例提供的一种统一操作的示意图。在图9中，假设中断事件发生后，此时第一地址存储的内容为“4334 CRC1”，即第一地址存储的第一目标数据被部分改变，第二地址存储的内容保持为第一目标数据“1234 CRC1”。由于第一地址存储的内容与第二地址存储的内容不相同，且经检测发现第一地址存储的内容发生数据撕裂，因此，执行统一操作，使用第二地址存储的内容覆盖第一地址存储的内容，则第一地址和第二地址存储的内容均为第一目标数据“1234 CRC1”。
一具体实施中，在第一地址存储的内容与第二地址的内容不同的情况下，若第一地址存储的内容未发生数据撕裂，对第一地址存储的内容和第二地址存储的内容执行统一操作，具体是：将第一地址存储的内容覆盖第二地址存储的内容，且第一地址存储的内容为第二目标数据，则第二地址存储的内容更新为第二目标数据，也就是说，第一地址和第二地址存储的内容均为数据2和校验码2。
例如，参见图10，图10是本申请实施例提供的一种统一操作的示意图。在图10中，假设中断事件发生后，此时第一地址存储的内容为“4321 CRC2”，即第一地址存储的内容已更新为第二目标数据，第二地址存储的内容为“4321 CRC1”，即第二地址存储的第一目标数据被部分改变。由于第一地址存储的内容与第二地址存储的内容不相同，且经检测发现第一地址存储的内容未发生数据撕裂，因此，执行统一操作，使用第一地址存储的内容覆盖第二地址存储的内容，则第一地址和第二地址存储的内容均为第二目标数据“4321 CRC2”。
可以看到，实施本申请实施例，基于一次IO将待写入数据在存储设备的内存的存储有相同内容的两个地址上进行连续双写，在数据写入过程被中断时，根据数据在两个地址的写入情况执行统一操作使得这两个地址存储的内容相同，从而实现了数据写入的原子性，减少了IO的消耗，有利于提高***的性能。
综上可以看出，将待写入数据串行依次写入存储设备的内存中的两个地址可实现数据写入的原子性。为了降低数据写入的时延，进一步提高数据写入的效率，还可以由客户端采用单边RDMA技术将待写入数据依次写入存储设备的内存中的两个地址。
需要说明的是，基于RDMA技术可实现利用网络将一计算机内的数据传输至另一计算机，无需双方操作***的介入，消除了数据包在用户空间和内核空间复制移动以及上下文切换的开销，减小了内存带宽、计算力的消耗。
参见图11，图11是本申请实施例提供的又一种数据处理方法的流程。相较于图3实施例，在图11中，数据写入操作是由客户端执行，而非图3实施例中的存储设备执行。图11可以独立于图3实施例。该方法包括但不限于以下步骤：
S201：客户端基于单边RDMA技术将两份第二目标数据依次写入存储设备的内存的第一地址和第二地址。
在本申请实施例中，在客户端将两份第二目标数据写入存储设备之前，存储设备的内存的第一地址存储第一目标数据且第二地址也存储第一目标数据，也就是说，第一地址存储的内容和第二地址存储的内容完全相同。需要说明的是，第一目标数据、第二目标数据具体可参考图3实施例中S101中第一目标数据、第二目标数据的相关叙述，在此不再赘述。
在本申请实施例中，第一地址与第二地址不同。
在本申请实施例中，客户端采用单边RDMA技术将两份第二目标数据依次写入存储设备的内存的第一地址和第二地址，其中，分别写入是指：客户端将两份第二目标数据中的第一份第二目标数据写入存储设备的内存的第一地址以覆盖第一地址的第一目标数据，以及将两份第二目标数据中的第二份第二目标数据写入存储设备的内存的第二地址以覆盖第二地址的第一目标数据；依次是指：客户端先将第一份第二目标数据写入第一地址，待第一份第二目标数据成功写入第一地址后，客户端再将第二份第二目标数据写入第二地址。需要说明的是，有关数据写入成功或失败等叙述具体可参考图3实施例中S101的相关叙述，在此不再赘述。
在本申请实施例中，客户端中执行数据写入操作的具体可以是客户端的网卡。
可以理解，客户端使用单边RDMA技术是指：数据的写/读操作均由客户端执行。在实际通信过程中，由客户端将数据写入存储设备的内存的目标地址中，且数据写入过程中，存储设备不需要执行任何操作。需要说明的是，客户端使用单边RDMA技术之前，客户端预先获取了存储设备的内存的两个地址(例如，第一地址和第二地址)以及这两个地址的使用权限。
一具体实施中，两份第二目标数据中的第二份第二目标数据可以是客户端对第一份第二目标数据进行复制获得的。两份第二目标数据为客户端基于一次IO消耗写入第一地址和第二地址中的。
S202：数据写入过程中发生中断事件，存储设备对第一地址存储的内容与第二地址存储的内容进行检测。
在本申请实施例中，客户端执行数据写入的过程中发生中断事件，在此情况下，两份第二目标数据在存储设备的内存的第一地址和第二地址的写入情况具体可参考上述图3实施例中S102中情况1-情况5的相关叙述，在此不再赘述。需要说明的是，与S102的区别在于数据写入的执行主体由S102中的存储设备替换为客户端。
在本申请实施例中，存储设备对第一地址的内容和第二地址的内容进行检测的过程具体可参考图3中S103的相关叙述，为了说明书的简洁，在此不再赘述。
S203：存储设备在检测到第一地址存储的内容与第二地址存储的内容不同时，对第一地址存储的内容和第二地址存储的内容执行统一操作。本步骤具体可参考图3中S104的相关叙述，为了说明书的简洁，在此不再赘述。
可以看到，实施本申请实施例，采用单边RDMA技术基于一次IO将待写入数据在存储设备的内存的两个地址进行连续双写，能有效降低数据写入的时延，提高数据的写入效率。在数据写入过程被中断时，根据数据在两个地址的写入情况进行统一操作操作使得这两个地址存储的内容相同，从而实现了数据写入的原子性，减少了IO的消耗，有利于提高***的性能。
参见图12，图12是本申请实施例提供的又一种数据处理方法的流程图。图12所描述的实施例可以独立于图3和图11实施例，也可以是对图3和图11实施例的补充。该方法包括但不限于以下步骤：
S301：客户端的处理器或者网卡生成数据的第一副本和第二副本。
在本申请实施例中，第一副本与第二副本是完全相同的。需要说明的是，此数据相当于图3或图11实施例中的第二目标数据，其中，第一副本即为图3或图11实施例中的第一份第二目标数据，第二副本即为图3或图11实施例中的第二份第二目标数据。
S302：客户端的网卡使用一次单边RDMA方式向存储设备的内存的第一地址写入第一副本，向该内存的第二地址写入第二副本。
一具体实施中，存储设备独立于客户端。
一具体实施中，该内存为持久化内存。
在本申请实施例中，客户端的网卡使用单边RDMA方式向存储设备的内存的第一地址写入第一副本以及向内存的第二地址写入第二副本，也就是说，数据写入的执行主体是客户端。 此步骤具体可参考图11实施例中S201的相关叙述，在此不再赘述。
需要说明的是，第一副本在第一地址中写入情况以及第二副本在第二地址中的写入情况具体可参考图3实施例中S102中情况1-情况6的相关描述，在此不再赘述。
在一些可能的实施例中，也可以不执行S302，执行下述S3021和S3022以替换S302。
S3021：客户端向存储设备发送单边RDMA写请求。
可选地，在S301之后，可以执行S3021。
在本申请实施例中，客户端向存储设备发送单边RDMA写请求。相应地，存储设备的网卡接收单边RDMA写请求。
其中，单边RDMA写请求包含数据的第一副本和第二副本，以及第一副本在存储设备的内存的第一地址和第二副本在内存的第二地址。可以理解，单边RDMA写请求用于指示将第一副本写入存储设备的内存的第一地址以及将第二副本写入该内存的第二地址。
S3022：存储设备的网卡根据单边RDMA写请求将第一副本写入第一地址，以及将第二副本写入第二地址。
可以理解，S3021和S3022也实现了将数据的第一副本写入内存的第一地址以及将数据的第二副本写入内存的第二地址，区别于S302，S3021和S3022中数据写入的执行主体为存储设备。此实施例具体可参考图3实施例中S101的相关叙述，在此不再赘述。
S303：存储设备的处理器或网卡从第一地址读取第一副本以及从第二地址读取第二副本，并校验读取的第一副本和读取的第二副本，在检测到读取的第一副本与读取的第二副本不一致时，对第一地址存储的数据或第二地址存储的数据执行数据覆盖操作。
在本申请实施例中，读取的第一副本包括第一数据和第一校验码，所述读取的第二副本包括第二数据和第二校验码，在满足以下至少一个条件时，读取的第一副本与读取的第二副本不一致：第一数据与第二数据不相同；或第一校验码与第二校验码不相同。导致读取的第一副本与读取的第二副本不一致的原因可参考图3实施例中S102的情况2至情况4中的任意一种。
一具体实施中，在检测到读取的第一副本与读取的第二副本不一致时，对第一地址存储的数据或第二地址存储的数据执行数据覆盖操作，可以是：在检测到读取的第一副本与读取的第二副本不一致时，若基于第一校验码校验第一数据成功时，使用第一数据和第一校验码覆盖第二地址存储的数据。此实施例与图3实施例中S104中将第一地址存储的内容覆盖第二地址的内容对应。
一具体实施中，在检测到读取的第一副本与读取的第二副本不一致时，对第一地址存储的数据或第二地址存储的数据执行数据覆盖操作，可以是：在检测到读取的第一副本与读取的第二副本不一致时，若基于第一校验码校验第一数据失败且基于第二校验码校验第二数据成功时，使用第二数据和第二校验码覆盖第一地址存储的数据。此实施例与图3实施例中S104中将第二地址存储的内容覆盖第一地址存储的内容对应。
需要说明的是，数据覆盖操作即为图3或图11实施例中的统一操作，其目的是为了使第一地址存储的数据与第二地址存储的数据完全相同。
需要说明的是，本申请实施例并不限定客户端的处理器或者网卡生成的数据的副本的数量。
一具体实施中，客户端的处理器或网卡也可以生成数据的三个副本，分别为第一副本、 第二副本和第三副本。相应地，可以由客户端的网卡使用一次单边RDMA方式向存储设备的内存的第一地址写入第一副本、向该内存的第二地址写入第二副本以及向该内存的第三地址写入第三副本，也可以由客户端向存储设备发送单边RDMA写请求以指示存储设备根据写RDMA写请求将第一副本写入内存的第一地址、将第二副本写入内存的第一地址以及将第三副本写入内存的第三地址，本申请实施例不作具体限定。存储设备的处理器或网卡从第一地址读取第一副本、从第二地址读取第二副本以及从第三地址读取第三副本，在检测到读取的第一副本、读取的第二副本和读取的第三副本中存在两个副本不一致时，对第一地址存储的数据、第二地址存储的数据或第三地址存储的数据中的至少一者执行数据覆盖操作，以使者三个地址存储的数据相同。
S304：客户端的网卡使用单边RDMA方式从第一地址读取第一副本以及从第二地址读取第二副本。
S305：客户端的处理器或网卡校验读取的第一副本和读取的第二副本，并从读取的第一副本和读取的第二副本中确定有效数据。
在本申请实施例中，客户端的处理器或者网卡检测到读取的第一副本与读取的第二副本相同时，确定读取的第一副本和读取的第二副本为有效数据。
一具体实施中，读取的第一副本与数据的第一副本相同，且读取的第二副本与数据的第二副本相同。在此情况下，说明数据的第一副本已成功写入内存的第一地址，数据的第二副本已成功写入内存的第二地址。如此，客户端的处理器或网卡确认读取的第一副本和读取的第二副本为有效数据，确保了数据写入的原子性。需要说明的是，此实施例可参考图3实施例中S102的情况5。
另一具体实施中，读取的第一副本与内存的第一地址存储的初始数据相同，且读取的第二副本与内存的第二地址存储的初始数据相同，其中，第一地址存储的初始数据为数据的第一副本写入内存的第一地址前该第一地址存储的数据，第二地址存储的初始数据为数据的第二副本写入内存的第二地址前该第二地址存储的数据，第一地址存储的初始数据与第二地址存储的初始数据相同。如此，客户端的处理器或网卡确认读取的第一副本和读取的第二副本为有效数据，确保了数据写入的原子性。需要说明的是，第一地址存储的初始数据可以是图3实施例中的第一目标数据，第二地址存储的初始数据也是图3实施例中的第一目标数据。需要说明的是，此实施例可参考图3实施例中S102的情况1。
可以看到，实施本申请实施例，采用一次单边RDMA方式将数据的两个副本写入存储设备的两个内存地址，检测到这两个内存地址中存储的数据不一致时，对相应地内存地址的数据执行数据覆盖操作使得这两个内存地址存储的数据相同，从而实现了以尽可能少的IO消耗确保数据写入的原子性，降低了数据写入的时延，有利于提高存储***的性能。
参见图13，图13是本申请实施例提供的一种装置的功能结构示意图，装置30包括生成单元310和写入单元312。该装置30可以通过硬件、软件或者软硬件结合的方式来实现。
其中，生成单元310，用于生成数据的第一副本和第二副本；写入单元312，用于使用一次单边远程内存访问RDMA方式向存储设备的内存的第一地址写入所述第一副本，向所述内存的第二地址写入所述第二副本。
在一些可能的实施例中，装置30还包括校验单元314和读取单元316，读取单元316用 于使用单边RDMA方式从第一地址读取第一副本以及从第二地址读取第二副本；校验单元314用于校验读取的第一副本和读取的第二副本，并从所读取的第一副本和读取的第二副本中确定有效数据。
该装置30的各功能模块还可用于实现图12实施例所描述的方法。在图12实施例中，生成单元310可用于执行S301，写入单元312可用于执行S302。读取单元316可用于执行S304，校验单元314可用于执行S305。该装置30的各功能模块还可用于实现图3和图11实施例所描述的方法，为了说明书的简洁，在此不再赘述。
参见图14，图14是本申请实施例提供的一种装置的功能结构示意图，装置40包括接收单元410和写入单元412。该装置40可以通过硬件、软件或者软硬件结合的方式来实现。
其中，接收单元410，用于接收客户端发送的单边远程内存访问RDMA写请求；单边RDMA写请求包含数据的第一副本和第二副本，以及第一副本在所述存储设备的内存的第一地址和第二副本在该内存的第二地址；写入单元412，用于将第一副本写入第一地址，以及将第二副本写入第二地址。
在一些可能的实施例中，装置40还包括处理单元414和读取单元416，读取单元416用于从第一地址读取第一副本以及从第二地址读取第二副本；处理单元414用于校验读取的第一副本和读取的第二副本，在检测到读取的第一副本与读取的第二副本不一致时，对第一地址存储的数据或第二地址存储的数据执行数据覆盖操作。
该装置40的各功能模块还可用于实现图12实施例所描述的方法。在图12实施例中，接收单元410和写入单元412可用于执行S3022，读取单元416和处理单元414可用于执行S303。该装置40的各功能模块还可用于实现图3和图11实施例所描述的方法，为了说明书的简洁，在此不再赘述。
本申请实施例还提供一种设备。如图15所示，设备50至少包括：处理器501、网卡502和总线503。处理器501和网卡502之间通过总线503通信。设备50可以是上述中的客户端或存储设备。应理解，本申请不限定设备50中的处理器的个数。
总线503可以是外设部件互连标准(peripheral component interconnect，PCI)总线或扩展工业标准结构(extended industry standard architecture，EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，图15中仅用一条线表示，但并不表示仅有一根总线或一种类型的总线。总线503可包括在设备50各个部件(例如，网卡502、处理器501)之间传送信息的通路。
处理器501可以包括中央处理器(central processing unit，CPU)、微处理器(micro processor，MP)或者数字信号处理器(digital signal processor，DSP)等处理器中的任意一种或多种。
在设备50为上述中的客户端时，网卡502可以用于生成数据的第一副本和第二副本，以及还用于使用一次单边远程内存访问RDMA方式向存储设备的内存的第一地址写入第一副本，向该内存的第二地址写入第二副本。在设备50为上述中的存储设备时，网卡502可以用于接收客户端发送的单边远程内存访问RDMA写请求，该单边RDMA写请求包含数据的第一副本和第二副本，以及第一副本在存储设备的内存的第一地址和第二副本在该内存的第二地址；网卡502还用于将第一副本写入第一地址，以及将第二副本写入第二地址。
一具体实施中，在该设备50为上述中的客户端时，该设备50的各个模块用于执行前述图3、图11或图12实施例描述的客户端侧的方法。
在一种可能的设计方式中，例如，设备50可为执行图12所示方法的客户端中的一个或多个模块，设备50用于执行以下操作：
通过处理器501或网卡502生成数据的第一副本和第二副本；
通过网卡502使用一次单边远程内存访问RDMA方式向存储设备的内存的第一地址写入第一副本，向内存的第二地址写入第二副本。
另一具体实施中，在该设备50为上述中的存储设备时，设备50还包括内存504，内存504可以是持久内存(Persistent Memory，PMEM)等。该设备50的各个模块可以用于执行前述图3、图11或图12实施例描述的存储设备侧的方法。
在一种可能的设计方式中，例如，设备50可为执行图12所示方法的存储设备中的一个或多个模块，设备50用于执行以下操作：
通过网卡502接收客户端发送的单边远程内存访问RDMA写请求；单边RDMA写请求包含数据的第一副本和第二副本，以及第一副本在存储设备的内存504的第一地址和第二副本在该内存504的第二地址；
通过网卡502将第一副本写入第一地址，以及将第二副本写入第二地址。
在本文上述的实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详细描述的部分，可以参见其他实施例的相关描述。
需要说明的是，本领域普通技术人员可以看到上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序可以存储于一计算机可读存储介质中，存储介质包括只读存储器(Read-Only Memory，ROM)、随机存储器(Random Access Memory，RAM)、可编程只读存储器(Programmable Read-only Memory，PROM)、可擦除可编程只读存储器(Erasable Programmable Read Only Memory，EPROM)、一次可编程只读存储器(One-time Programmable Read-Only Memory，OTPROM)、电子抹除式可复写只读存储(Electrically-Erasable Programmable Read-Only Memory，EEPROM)、只读光盘(Compact Disc Read-Only Memory，CD-ROM)或其他光盘存储器、磁盘存储器、磁带存储器、或者能够用于携带或存储数据的计算机可读的任何其他介质。
本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机程序产品存储在一个存储介质中，包括若干指令用以使得一个设备(可以是个人计算机，服务器，或者网络设备、机器人、单片机、芯片、机器人等)执行本申请各个实施例所述方法的全部或部分步骤。

Claims (30)

  1. 一种数据处理方法，其特征在于，所述方法包括：
    客户端的处理器或者网卡生成数据的第一副本和第二副本；其中，所述处理器与所述网卡通信；
    所述网卡使用一次单边远程内存访问RDMA方式向存储设备的内存的第一地址写入所述第一副本，向所述内存的第二地址写入所述第二副本。
  2. 根据权利要求1所述的方法，其特征在于，所述内存为持久化内存。
  3. 根据权利要求1或2所述的方法，其特征在于，所述方法还包括：
    所述网卡使用单边RDMA方式从所述第一地址读取所述第一副本以及从所述第二地址读取所述第二副本；
    所述处理器或者网卡校验读取的第一副本和读取的第二副本，并从所述读取的第一副本和所述读取的第二副本中确定有效数据。
  4. 根据权利要求3所述的方法，其特征在于，所述处理器或者网卡校验读取的第一副本和读取的第二副本，并从所述读取的第一副本和所述读取的第二副本中确定有效数据，包括：
    所述处理器或者网卡检测到读取的第一副本与读取的第二副本相同时，确定所述读取的第一副本和所述读取的第二副本为有效数据。
  5. 一种数据处理方法，其特征在于，所述方法包括：
    存储设备的网卡接收客户端发送的单边远程内存访问RDMA写请求；所述单边RDMA写请求包含数据的第一副本和第二副本，以及所述第一副本在所述存储设备的内存的第一地址和所述第二副本在所述内存的第二地址；
    所述网卡将所述第一副本写入所述第一地址，以及将所述第二副本写入所述第二地址。
  6. 根据权利要求5所述的方法，其特征在于，所述内存为持久化内存。
  7. 根据权利要求5或6所述的方法，其特征在于，所述方法还包括：
    所述存储设备的网卡或处理器从所述第一地址读取所述第一副本以及从所述第二地址读取所述第二副本；
    所述存储设备的网卡或处理器校验读取的第一副本和读取的第二副本，在检测到所述读取的第一副本与所述读取的第二副本不一致时，对所述第一地址存储的数据或所述第二地址存储的数据执行数据覆盖操作。
  8. 根据权利要求7所述的方法，其特征在于，所述读取的第一副本包括第一数据和第一校验码，所述读取的第二副本包括第二数据和第二校验码，在满足以下至少一个条件时，所述读取的第一副本与所述读取的第二副本不一致：
    所述第一数据与所述第二数据不相同；或
    所述第一校验码与所述第二校验码不相同。
  9. 根据权利要求8所述的方法，其特征在于，所述对所述第一地址存储的数据或所述第二地址存储的数据执行数据覆盖操作，包括：
    在基于所述第一校验码校验所述第一数据成功时，使用所述第一数据和所述第一校验码覆盖所述第二地址存储的数据。
  10. 根据权利要求8所述的方法，其特征在于，所述对所述第一地址存储的数据或所述第二地址存储的数据执行数据覆盖操作，包括：
    在基于所述第一校验码校验所述第一数据失败且基于所述第二校验码校验所述第二数据成功时，使用所述第二数据和所述第二校验码覆盖所述第一地址存储的数据。
  11. 一种数据处理装置，其特征在于，所述装置包括：
    生成单元，用于生成数据的第一副本和第二副本；
    写入单元，用于使用一次单边远程内存访问RDMA方式向存储设备的内存的第一地址写入所述第一副本，向所述内存的第二地址写入所述第二副本。
  12. 根据权利要求11所述的装置，其特征在于，所述内存为持久化内存。
  13. 根据权利要求11或12所述的装置，其特征在于，所述装置还包括：
    读取单元，用于使用单边RDMA方式从所述第一地址读取所述第一副本以及从所述第二地址读取所述第二副本；
    校验单元，用于校验读取的第一副本和读取的第二副本，并从所述读取的第一副本和所述读取的第二副本中确定有效数据。
  14. 根据权利要求13所述的装置，其特征在于，所述校验单元，具体用于：
    检测到读取的第一副本与读取的第二副本相同时，确定所述读取的第一副本和所述读取的第二副本为有效数据。
  15. 一种数据处理装置，其特征在于，所述装置包括：
    接收单元，用于接收客户端发送的单边远程内存访问RDMA写请求；所述单边RDMA写请求包含数据的第一副本和第二副本，以及所述第一副本在所述存储设备的内存的第一地址和所述第二副本在所述内存的第二地址；
    写入单元，用于将所述第一副本写入所述第一地址，以及将所述第二副本写入所述第二地址。
  16. 根据权利要求15所述的装置，其特征在于，所述内存为持久化内存。
  17. 根据权利要求15或16所述的装置，其特征在于，所述装置还包括：
    读取单元，用于从所述第一地址读取所述第一副本以及从所述第二地址读取所述第二副本；
    处理单元，用于校验读取的第一副本和读取的第二副本，在检测到所述读取的第一副本与所述读取的第二副本不一致时，对所述第一地址存储的数据或所述第二地址存储的数据执行数据覆盖操作。
  18. 根据权利要求17所述的装置，其特征在于，所述读取的第一副本包括第一数据和第一校验码，所述读取的第二副本包括第二数据和第二校验码，在满足以下至少一个条件时，所述读取的第一副本与所述读取的第二副本不一致：
    所述第一数据与所述第二数据不相同；或
    所述第一校验码与所述第二校验码不相同。
  19. 根据权利要求18所述的装置，其特征在于，所述处理单元，具体用于：
    在基于所述第一校验码校验所述第一数据成功时，使用所述第一数据和所述第一校验码覆盖所述第二地址存储的数据。
  20. 根据权利要求18所述的装置，其特征在于，所述处理单元，具体用于：
    在基于所述第一校验码校验所述第一数据失败且基于所述第二校验码校验所述第二数据成功时，使用所述第二数据和所述第二校验码覆盖所述第一地址存储的数据。
  21. 一种数据处理装置，其特征在于，所述装置包括至少一个处理器和网卡，其中，所述处理器与所述网卡通信；
    所述处理器或者网卡用于生成数据的第一副本和第二副本；
    所述网卡用于使用一次单边远程内存访问RDMA方式向存储设备的内存的第一地址写入所述第一副本，向所述内存的第二地址写入所述第二副本。
  22. 根据权利要求21所述的数据处理装置，其特征在于，所述内存为持久化内存。
  23. 根据权利要求21或22所述的数据处理装置，其特征在于，
    所述网卡还用于使用单边RDMA方式从所述第一地址读取所述第一副本以及从所述第二地址读取所述第二副本；
    所述处理器或者网卡还用于校验读取的第一副本和读取的第二副本，并从所述读取的第一副本和所述读取的第二副本中确定有效数据。
  24. 根据权利要求23所述的数据处理装置，其特征在于，所述处理器或者网卡还用于校验读取的第一副本和读取的第二副本，并从所述读取的第一副本和所述读取的第二副本中确定有效数据，包括：
    所述处理器或者网卡还检测到读取的第一副本与读取的第二副本相同时，确定所述读取的第一副本和所述读取的第二副本为有效数据。
  25. 一种数据处理装置，其特征在于，所述装置包括网卡和内存，其中，
    所述网卡用于接收客户端发送的单边远程内存访问RDMA写请求；所述单边RDMA写请求包含数据的第一副本和第二副本，以及所述第一副本在所述内存的第一地址和所述第二副本在所述内存的第二地址；
    所述网卡用于将所述第一副本写入所述第一地址，以及将所述第二副本写入所述第二地址。
  26. 根据权利要求25所述的数据处理装置，其特征在于，所述内存为持久化内存。
  27. 根据权利要求25或26所述的数据处理装置，其特征在于，所述数据处理装置还包含处理器；所述处理器与所述网卡通信；
    所述网卡或处理器用于从所述第一地址读取所述第一副本以及从所述第二地址读取所述第二副本；
    所述网卡或处理器还用于校验读取的第一副本和读取的第二副本，在检测到所述读取的第一副本与所述读取的第二副本不一致时，对所述第一地址存储的数据或所述第二地址存储的数据执行数据覆盖操作。
  28. 根据权利要求27所述的数据处理装置，其特征在于，所述读取的第一副本包括第一数据和第一校验码，所述读取的第二副本包括第二数据和第二校验码，在满足以下至少一个条件时，所述读取的第一副本与所述读取的第二副本不一致：
    所述第一数据与所述第二数据不相同；或
    所述第一校验码与所述第二校验码不相同。
  29. 根据权利要求28所述的数据处理装置，其特征在于，所述对所述第一地址存储的数据或所述第二地址存储的数据执行数据覆盖操作，包括：
    在基于所述第一校验码校验所述第一数据成功时，使用所述第一数据和所述第一校验码 覆盖所述第二地址存储的数据。
  30. 根据权利要求28所述的数据处理装置，其特征在于，所述对所述第一地址存储的数据或所述第二地址存储的数据执行数据覆盖操作，包括：
    在基于所述第一校验码校验所述第一数据失败且基于所述第二校验码校验所述第二数据成功时，使用所述第二数据和所述第二校验码覆盖所述第一地址存储的数据。
PCT/CN2022/113098 2021-09-01 2022-08-17 一种数据处理方法及装置 WO2023030013A1 (zh)

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