WO2023028792A1 - 一种显示基板及显示装置 - Google Patents

一种显示基板及显示装置 Download PDF

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Publication number
WO2023028792A1
WO2023028792A1 PCT/CN2021/115477 CN2021115477W WO2023028792A1 WO 2023028792 A1 WO2023028792 A1 WO 2023028792A1 CN 2021115477 W CN2021115477 W CN 2021115477W WO 2023028792 A1 WO2023028792 A1 WO 2023028792A1
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WIPO (PCT)
Prior art keywords
opening area
line segment
display substrate
vertical line
pixel
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PCT/CN2021/115477
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English (en)
French (fr)
Inventor
韩佳慧
梁蓬霞
方正
石戈
孙艳六
刘玉杰
吴谦
杨松
李鸿鹏
崔贤植
赵伟利
彭宽军
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/759,996 priority Critical patent/US20240186329A1/en
Priority to EP21955371.6A priority patent/EP4300181A1/en
Priority to CN202180002342.5A priority patent/CN116075772A/zh
Priority to PCT/CN2021/115477 priority patent/WO2023028792A1/zh
Publication of WO2023028792A1 publication Critical patent/WO2023028792A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/52—RGB geometrical arrangements

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • the 3D application based on ultra-high resolution is the current development trend of 3D display technology, but the current 3D solution has technical problems such as moiré, and one of the reasons for moiré is the discontinuity of pixel light emission.
  • Conventional pixel design in the related art for example, the source-drain metal line (SD line) such as the data line is straight and opaque.
  • the non-transparent area makes the pixels emit light discontinuously. In the 3D display state, the discontinuous light emission of pixels will cause moiré.
  • Embodiments of the present disclosure provide a display substrate and a display device, which can improve the continuity of light emission of pixels and improve the defect phenomenon of moiré.
  • An embodiment of the present disclosure provides a display substrate, including a base substrate, and a plurality of data lines extending along a first direction and a plurality of gate lines extending along a second direction disposed on the base substrate, the plurality of A plurality of data lines and a plurality of gate lines are intersected to define a plurality of sub-pixels, and each of the sub-pixels includes at least a first opening area and a second opening area arranged at intervals in the first direction, so The second opening area is offset in the second direction relative to the first opening area, and the offset distance is less than or equal to the width of the first opening area in the second direction.
  • the minimum distance between two adjacent first opening regions in the second direction is equal to the offset distance.
  • the first opening area and the second opening area share the same switching device, share the same data line as the signal input line, and share the same gate line as the switch control of the switching device Wire.
  • one gate line shared by the first opening area and the second opening area located in the same sub-pixel is arranged between the first opening area and the second opening area ;
  • one gate line shared by the first opening area and the second opening area located in the same sub-pixel is arranged on a side of the first opening area away from the second opening area ;
  • one gate line shared by the first opening area and the second opening area located in the same sub-pixel is arranged on a side of the second opening area away from the first opening area .
  • the data lines are arranged in the non-aperture area of the pixel in a zigzag shape.
  • the sub-pixel includes opposite first sides and second sides, and the first side and the second side are used for arranging the data lines; the data lines include sequentially along the first direction A plurality of first repeating units linked, said first repeating unit comprising:
  • the first vertical line segment is located on the first side of the first opening area and extends along the first direction, including a first end located away from the second opening area and a first end located close to the second opening area Two ends;
  • the second vertical line segment is located on the second side of the second opening area and extends along the second direction, including a third end located close to the first opening area and a third end located away from the first opening area Four ends;
  • the first oblique line segment is connected between the second end of the first vertical line segment and the third end of the second vertical line segment, and there is a first oblique line segment between the first vertical line segment and the first vertical line segment. Angle;
  • the second oblique line segment is connected to the first end of the first vertical line segment, or connected to the fourth end of the second vertical line segment, and there is a second oblique line segment between the second vertical line segment and the first vertical line segment Two included angles.
  • first vertical line segment, the second vertical line segment, the first oblique line segment and the second oblique line segment are an integral structure of the same layer and the same material;
  • first vertical line segment, the second vertical line segment, the first oblique line segment and the second oblique line segment are arranged in different layers and connected by vias.
  • the sub-pixel includes opposite first sides and second sides, and the first side and the second side are used for arranging the data lines; the data lines include sequentially along the first direction A plurality of second repeating units connected, the second repeating unit comprising:
  • a third vertical line segment is located on the first side or the second side of the first opening area, the third vertical line segment includes a first end close to the second opening area and a first end far away from the first opening area the second end of the second open area;
  • the transparent conductive line, the orthographic projection of the transparent conductive line on the base substrate at least partially coincides with the orthographic projection of the second opening area on the base substrate, and is connected to the third vertical line segment connected to the first end, and the length of the transparent conductive line in the first direction is greater than or equal to the length of the second opening area in the first direction.
  • the transparent conductive line is in the same layer as the third vertical line segment and is made of different materials
  • the transparent conductive line and the third vertical line segment are insulated from each other and connected through a via hole.
  • the third vertical line segment is a source-drain metal line
  • the transparent conductive line is an indium tin oxide conductive line.
  • the display substrate further includes a common electrode layer disposed on the base substrate, wherein the common electrode layer is an opaque conductive layer or a transparent conductive layer, and the common electrode layer is provided with an open area defining the first open area and the second open area.
  • the display substrate further includes a plurality of pixel electrodes, one pixel electrode is disposed in each sub-pixel.
  • the pixel electrode is a transparent conductive electrode, and the pixel electrode includes:
  • the shape of the first electrode block part matches the shape of the space surrounded by the data lines arranged on the first side and the second side of the corresponding first opening area.
  • the switch device is arranged at the crossing position of the gate line and the data line.
  • each sub-pixel on the display substrate is divided into at least two upper and lower pixel openings arranged at intervals in the first direction (that is, the extending direction of the data line), that is, the first opening area and the second opening area, and the second opening area is offset relative to the first opening area in the second direction (that is, the direction in which the gate line extends), and the offset distance is less than or equal to that of the first opening area in the second
  • the width in the direction that is to say, in the extending direction of the data line, the first opening area and the second opening area partially overlap, or the second opening area is offset from the first opening area by exactly one width of the first opening area, In this way, the light-emitting areas of the first opening area and the second opening area of each pixel can realize complementarity, thereby realizing continuous light emission of pixels, and improving the defect phenomenon of moiré in 3D display.
  • FIG. 1 shows a schematic diagram of transmittance curves at different positions of a single pixel in a conventional pixel structure in a display substrate in the related art
  • FIG. 2 shows a schematic structural diagram of a display substrate provided by some embodiments of the present disclosure
  • FIG. 3 shows a schematic structural view of a display substrate provided by other embodiments of the present disclosure
  • Fig. 4 is a schematic diagram showing transmittance curves of different positions of a single pixel in the display substrate in the embodiment shown in Fig. 2, wherein the common electrode layer is an opaque conductive layer;
  • FIG. 5 shows a schematic diagram of transmittance curves at different positions of a single pixel in the display substrate in the embodiment shown in FIG. 3;
  • FIG. 6 is a schematic diagram showing transmittance curves of different positions of a single pixel in the display substrate in the embodiment shown in FIG. 2 , wherein the common electrode layer is a light-transmitting conductive layer.
  • 3D display products based on ultra-high resolution have technical problems such as moiré, and one of the causes of moiré is discontinuity of pixel light emission.
  • the source-drain metal line (SD line) such as the data line is linear and opaque.
  • the transmittance at different positions of a single pixel is shown in Figure 1, and the abscissa in Figure 1 is the extension direction of the gate line.
  • the position point in the single pixel above, and the ordinate is the pixel transmittance at the same position point.
  • the transmittance at the position of the data line is 0
  • the discontinuous light emission of the pixels will cause poor moiré.
  • embodiments of the present disclosure provide a display substrate and a display device, which can improve the continuity of light emission of pixels and improve the phenomenon of moiré defects.
  • FIG. 2 and FIG. 3 are structural front views of the display substrate provided by the embodiments of the present disclosure, in which only a partial structure of the pixel array on the display substrate is shown.
  • the display substrate includes a base substrate, and a plurality of data lines 100 and a plurality of gate lines 200 arranged on the base substrate, and the data lines 100 are arranged along a first direction.
  • the gate line 200 extends along the second direction, the data line 100 and the gate line 200 are intersected
  • the display substrate includes a plurality of pixel units distributed in an array, and each pixel unit includes at least two sub-sub-pixels 300, each of the sub-pixels 300 includes at least a first opening area 310 and a second opening area 320 arranged at intervals in the first direction, and the second opening area 320 is at a distance relative to the first opening area 310
  • the second direction is offset, and the offset distance ⁇ d is less than or equal to the width L of the first opening area 310 in the second direction.
  • each sub-pixel 300 on the display substrate is divided into at least two upper and lower pixel openings arranged at intervals in the first direction (that is, the direction in which the data line 100 extends), that is, the first opening area 310 and the second opening area.
  • the second opening area 320 is offset relative to the first opening area 310 in the second direction (that is, the extending direction of the gate line 200), and the offset distance ⁇ d is less than or equal to the first opening area 310 in
  • the width L in the second direction that is, in the extending direction of the data line 100, the first opening area 310 and the second opening area 320 partially overlap, or the second opening area 320 is just offset from the first opening area 310
  • the width of a first opening area 310, the first opening area 310 and the second opening area 320 are in a dislocation and complementary relationship, so that the light emitting area of the first opening area 310 and the second opening area 320 of each sub-pixel 300 Complementarity can be realized, thereby achieving continuous light emission of the sub-pixels 300 and improving the bad phenomenon of moiré in 3D display.
  • the first opening area and the second opening area of the sub-pixel refer to the opening area on the light-shielding film layer used to define the size of the opening of the sub-pixel on the display substrate,
  • the opening pattern is designed on the pixel definition layer separately provided on the display substrate to obtain the first opening area and the second opening area; or, it may also be that the light-shielding conductive layer on the display substrate (for example, using An opening pattern is designed on the common electrode layer made of light-shielding metal, etc.) to define the first opening area and the second opening area.
  • the offset distance ⁇ d of the second opening area 320 relative to the second opening area 320 is smaller than the width L of the first opening area 310 , Therefore, the first opening area 310 and the second opening area 320 are partially overlapped in the second direction.
  • the offset distance ⁇ d of the first opening area 310 relative to the second opening area 320 is equal to that of the first opening area 310 in the second In this way, taking the direction shown in the figure as an example, the left edge of the first opening area 310 in the same sub-pixel 300 will be aligned with the right edge of the second opening area 320 .
  • the minimum distance D between two adjacent first opening regions 310 in the second direction is equal to the offset distance ⁇ d. Still taking the direction shown in FIG. 2 as an example, the right edge of the first opening area 310 in the sub-pixel 300 is aligned with the left edge of the second opening area 320 in the right adjacent sub-pixel 300, In this way, crosstalk between adjacent sub-pixels 300 can be prevented.
  • a plurality of gate lines 200 and a plurality of data lines 100 in the display substrate intersect to define a plurality of sub-pixels 300, and a switching device and a pixel electrode 500 are arranged in each sub-pixel 300, wherein the switching device It may be a thin film transistor (not shown in the figure), including a source, a drain and a gate, wherein the gate line 200 is connected to the gate, the data line 100 is connected to the source, the drain is connected to the pixel electrode 500, and the gate line 200 As a switch control line of the switching device, the data line 100 serves as a signal input line.
  • the switch device is disposed at the crossing position of the gate line 200 and the data line 100 .
  • the first opening region 310 and the second opening region 320 may share a switching device, share a data line 100 as a signal input line, and share a gate line 200 is used as a switching control line of the switching device, which can ensure that the first opening area 310 and the second opening area 320 in the same sub-pixel 300 have the same light emitting state, so as to ensure the continuity of light emission of the sub-pixel 300 .
  • the gate line 200 Since the gate line 200 needs to be connected to the switching device, the gate line 200 is arranged between the first opening area 310 and the second opening area 320. From the spatial layout, it is beneficial to the gate line 200, the switching device, the pixel electrode 500 and the data line. 100 to connect.
  • one gate line 200 shared by the first opening region 310 and the second opening region 320 located in the same sub-pixel 300 is arranged on the A side of the first opening area 310 away from the second opening area 320 .
  • one gate line 200 shared by the first opening region 310 and the second opening region 320 located in the same sub-pixel 300 is arranged in the second opening region 320 A side away from the first opening area 310 .
  • the sub-pixel 300 includes opposite first sides and second sides, and the first side and the second side are used for laying the data lines 100 .
  • the first side is the left side of the sub-sub-pixel 300
  • the second side is the right side of the sub-sub-pixel 300 .
  • the first side and the second side are respectively referred to as the left side and the right side, for the convenience of description and understanding.
  • the display substrate in the embodiment of the present disclosure as shown in FIG.
  • the non-transparent area on the second side is non-linear, and the first opening area 310 and the second opening area 320 share a data line 100 , and the data line 100 should be arranged in the non-transparent area of the sub-pixel 300 . Therefore, in some embodiments, the routing of the data line 100 can be adjusted from a straight line to a zigzag line, that is, the data line 100 is arranged in a zigzag shape in the non-opening area of the sub-pixel 300 .
  • the data line 100 includes a plurality of first repeating units 110 sequentially connected along the first direction
  • the first repeating units 110 include: a first vertical line segment 111, a second The vertical line segment 112, the first oblique line segment 113 and the second oblique line segment 114, wherein the first vertical line segment 111 is located on the first side of the first opening area 310 and extends along the first direction, including being located away from The first end of the second opening area 320 is located near the second end of the second opening area 320; the second vertical line segment 112 is located on the second side of the second opening area 320, and along the Extending in the second direction, the second vertical line segment 112 includes a third end located close to the first opening area 310 and a fourth end located away from the first opening area 310; the first oblique line segment 113 is connected to There is a first angle ⁇ between the second end of the first vertical line segment 111 and the third end of the second vertical line segment 112 ,
  • the first repeating unit 110 is roughly in the shape of an "S" shape or a substantially reverse "S" shape.
  • the first included angle ⁇ refers to the included angle between the first oblique line segment 113 and the first vertical line segment 111 , for example, the first included angle ⁇ is An obtuse angle;
  • the second included angle ⁇ refers to the included angle between the second oblique line segment 114 and the second vertical line segment 112 , for example, the second included angle ⁇ is an obtuse angle.
  • the specific angle values of the first included angle ⁇ and the second included angle ⁇ are not limited here.
  • the first included angle ⁇ is greater than 90° and less than 150°; the second included angle ⁇ is greater than 90° and less than 150°.
  • the zigzag data line 100 can prevent the aperture ratio of the sub-pixel 300 from decreasing.
  • the first vertical line segment 111 , the second vertical line segment 112 , the first oblique line segment 113 and the second oblique line segment 114 are made of the same layer and material.
  • the first vertical line segment 111, the second vertical line segment 112, the first oblique line segment 113, and the second oblique line segment 114 in the first repeating unit 110 are all source-drain metal layer patterning processes. pattern formed later.
  • At least two of the first vertical segment 111 , the second vertical segment 112 , the first oblique segment 113 and the second oblique segment 114 may be of different layers and insulated. set and connected via vias.
  • the data line 100 is connected to the drain of the switching device, therefore, a connection portion 115 for connecting the switching device should be provided on the data line 100 .
  • a connection portion 115 for connecting the switching device should be provided on the data line 100 .
  • the connecting portion 115 may be disposed on the first vertical segment 111 on.
  • the specific position of the connecting portion 115 is not limited thereto, and a reasonable position can be selected according to the specific position of the gate line 200 .
  • the data line 100 is designed in a zigzag shape to match the wiring space of the non-transmissive area.
  • the data line 100 may also be implemented by using other structures.
  • the data line 100 includes a plurality of second repeating units 120 sequentially connected along the first direction
  • the second repeating units 120 include: The third vertical line segment 121 and the transparent conductive line 122, wherein, the third vertical line segment 121 is located on the first side or the second side of the first opening area 310, and the third vertical line segment 121 includes a The first end of the opening area 320 and the second end away from the second opening area 320; the orthographic projection of the transparent conductive line 122 on the base substrate and the second opening area 320 on the base substrate
  • the above orthographic projections are at least partially overlapped, and the length of the transparent conductive line 122 in the first direction is greater than or equal to the length of the second opening area 320 in the first direction, and is identical to the length of the second opening area 320 in the first direction.
  • the first ends of the three vertical line segments 121 are connected.
  • the data line 100 may not be arranged in a zigzag shape, but is connected in a straight line with the transparent conductive line 122 through the third vertical line segment 121 to form the second repeating unit 120, wherein the third vertical line segment 121
  • the central line of the transparent conductive line 122 may be located on the same straight line, and the part of the data line 100 passing through the second opening area 320 is a light-transmitting transparent conductive line 122 , which will not affect the light transmittance of the second opening area 320 .
  • the length of the transparent conductive line 122 in the first direction is greater than or equal to the length of the second opening area 320 in the first direction, that is, the The light-transmitting conductive line covers the second opening area in the extending direction of the data line, so that the data line can ensure that the light transmittance of the second opening area will not be adversely affected.
  • the relationship between the length of the transparent conductive line and the width of the second opening area is not limited, that is, the transparent conductive line
  • the second opening area may or may not be covered in the extending direction of the gate line.
  • the transparent conductive line 122 and the third vertical line segment 121 are of the same layer and are made of different materials. That is to say, the transparent conductive line 122 and the third vertical line segment 121 may be Arranged on the same layer, in the manufacturing process of the display substrate, the patterns of the third vertical line segment 121 and the transparent conductive line 122 are respectively formed through two MASK processes (ie, two patterning processes).
  • the transparent conductive lines 122 and the transparent conductive lines 122 may also be in different layers and insulated, and connected through via holes.
  • the patterns of the third vertical line segments 121 and the transparent conductive lines 122 can be formed respectively through two MASK processes (ie, two patterning processes).
  • the third vertical line segment 121 is a source-drain metal line
  • the transparent conductive line 122 is an ITO conductive line.
  • the material of the third vertical line segment 121 and the transparent conductive line 122 is not limited thereto.
  • the data line 100 is connected to the drain of the switch device, therefore, a connection portion for connecting the switch device should be provided on the data line 100 .
  • a connection portion for connecting the switch device should be provided on the data line 100 .
  • the connection part can be arranged on the third vertical line segment 121 superior.
  • the specific position of the connecting portion is not limited thereto, and a reasonable position can be selected according to the specific setting position of the gate line 200 .
  • the display substrate further includes a common electrode layer 400 disposed on the base substrate, wherein the common electrode layer 400 is not In the light-transmitting conductive layer, an opening area 410 is provided on the common electrode layer 400 , and the opening area 410 defines the first opening area 310 and the second opening area 320 .
  • the common electrode layer 400 adopts an opaque conductive layer, and the first opening area 310 and the second opening area 320 are defined by opening the opening area 410 pattern on the common electrode layer 400, so that, due to The non-opening area 420 of the common electrode can play a light-shielding function, which is beneficial to the consistency of transmittance at different positions of the sub-pixels 300 .
  • the common electrode layer 400 can also use a light-transmitting conductive layer, and the common electrode layer 400 is provided with an opening area 410, and the opening area 410 defines the first opening area 310 and the first opening area 310.
  • the second opening area 320 is mentioned above.
  • the common electrode layer 400 uses a light-transmitting conductive layer, which may still have the problem of inconsistent light transmittance at different points in the non-light-transmitting area of the sub-pixel 300 . Therefore, in practical applications, if it is desired to improve the consistency of transmittance at different points of the sub-pixel 300, the common electrode layer 400 can be selected as an opaque conductive layer.
  • the display substrate further includes a plurality of pixel electrodes 500, and one pixel electrode 500 is arranged in each sub-pixel 300, wherein the pixel electrode 500 is connected to the source of the switching device.
  • the pixel electrode 500 is a transparent conductive electrode, and the pixel electrode 500 includes: a first electrode block part 510 located in the first opening area 310; a second electrode block part 510 located in the second opening area 320; an electrode block part 520 ; and a connection bridge part 530 connected between the first electrode block part 510 and the second electrode block part 520 .
  • the shape of the first electrode block part 510 corresponds to the first side and the second side of the first opening area 310 .
  • the shapes of the space enclosed by the data lines 100 arranged on both sides are matched.
  • Fig. 4 is a graph of the transmittance curve of the pixel structure in the display substrate in some embodiments of the present disclosure, wherein the common electrode layer in the display substrate is an opaque electrode layer, and the data lines are broken lines (such as shown in Fig. 2 Examples of display substrates).
  • the abscissa is the position in a single sub-pixel 300 along the extending direction of the gate line 200
  • the ordinate is the average value of the transmittance of the first opening area 310 and the second opening area 320 at the same position.
  • the pixel structure of the display substrate has no position where the transmittance is 0, and the continuous light emission of the sub-pixel 300 can be realized.
  • the test results show that the moiré pattern can be effectively eliminated.
  • the common electrode layer in the display substrate is an opaque electrode layer
  • the data line includes a third vertical line segment and a transparent electrode layer.
  • Conductive lines (such as the display substrate in the embodiment shown in FIG. 4 ).
  • the abscissa is the position in the single sub-pixel 300 along the extending direction of the gate line 200
  • the ordinate is the average value of the transmittance of the first opening area 310 and the second opening area 320 at the same position.
  • the pixel structure of the display substrate has no position where the transmittance is 0, and the continuous light emission of the sub-pixel 300 can be realized.
  • the test results show that the moiré pattern can be effectively eliminated.
  • FIG. 6 is a graph of the transmittance curve of the pixel structure in the display substrate in some embodiments of the present disclosure, wherein the common electrode layer in the display substrate is a light-transmitting electrode layer, and the data lines are broken lines (for example, the implementation shown in FIG. 2
  • the display substrate in the example differs from the display substrate in the embodiment shown in Fig. 4 in that the common electrode layer is a light-transmitting electrode layer.
  • the abscissa is the position point in the single sub-pixel 300 on the grid line 200 extending direction
  • the ordinate is The average value of the transmittance of the first opening area 310 and the second opening area 320 at the same position point.
  • the display substrate pixel structure has no position of transmittance of 0, which can realize continuous sub-pixels 300 Luminescence, during the moiré experimental test, the test results show that it can effectively eliminate moiré.

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Abstract

本公开提供一种显示基板及显示装置，所述显示基板包括衬底基板、及设置于所述衬底基板之上的沿第一方向延伸的多条数据线和沿第二方向延伸的多条栅线，所述显示基板包括多个像素，每个所述子像素至少包括在所述第一方向上间隔设置的第一开口区和第二开口区，所述第二开口区相对于所述第一开口区在所述第二方向上偏移，且偏移距离小于或等于所述第一开口区在所述第二方向上的宽度。本公开实施例提供的显示基板及显示装置，能够提高像素发光连续性，改善摩尔纹不良现象。

Description

一种显示基板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
基于超高分辨率的3D化应用，是当前3D显示的技术发展趋势，但当前3D方案存在摩尔纹等技术问题点，引起摩尔纹的原因之一是像素发光的不连续性。相关技术中常规像素设计，例如数据线等源漏金属走线(SD line)为直线且不透光，当显示画面时，由于源漏金属走线位置透过率低，像素之间会出现周期性的不透光区域，使得像素发光不连续，在3D显示状态时，像素发光不连续会造成摩尔纹。
发明内容
本公开实施例提供了一种显示基板及显示装置，能够提高像素发光连续性，改善摩尔纹不良现象。
本公开实施例所提供的技术方案如下：
本公开实施例提供了一种显示基板，包括衬底基板、及设置于所述衬底基板之上的沿第一方向延伸的多条数据线和沿第二方向延伸的多条栅线，多条所述数据线和多条所述栅线交叉设置而限定出多个子像素，每个所述子像素至少包括在所述第一方向上间隔设置的第一开口区和第二开口区，所述第二开口区相对于所述第一开口区在所述第二方向上偏移，且偏移距离小于或等于所述第一开口区在所述第二方向上的宽度。
示例性的，在所述第二方向上相邻的两个第一开口区之间的最小间距等于所述偏移距离。
示例性的，同一所述子像素内，所述第一开口区和所述第二开口区共用同一开关器件，共用同一条数据线作为信号输入线，共用同一条栅线作为开关器件的开关控制线。
示例性的，位于同一所述子像素内的所述第一开口区和所述第二开口区 所共用的一条所述栅线布设于所述第一开口区与所述第二开口区之间；
或者，位于同一所述子像素内的所述第一开口区和所述第二开口区所共用的一条所述栅线布设于所述第一开口区的远离所述第二开口区的一侧；
或者，位于同一所述子像素内的所述第一开口区和所述第二开口区所共用的一条所述栅线布设于所述第二开口区的远离所述第一开口区的一侧。
示例性的，所述数据线呈折线状布设于所述像素的非开口区。
示例性的，所述子像素包括相对的第一侧和第二侧，所述第一侧和所述第二侧用于布设所述数据线；所述数据线包括沿所述第一方向依次连接的多个第一重复单元，所述第一重复单元包括：
第一竖线段，位于所述第一开口区的第一侧，并沿所述第一方向延伸，包括位于远离所述第二开口区的第一端及位于靠近所述第二开口区的第二端；
第二竖线段，位于所述第二开口区的第二侧，并沿所述第二方向延伸，包括位于靠近所述第一开口区的第三端及位于远离所述第一开口区的第四端；
第一斜线段，连接在所述第一竖线段的第二端与所述第二竖线段的第三端之间，且所述第一斜线段与所述第一竖线段之间具有第一夹角；
第二斜线段，连接在所述第一竖线段的第一端、或者连接在所述第二竖线段的第四端，且所述第二斜线段与所述第一竖线段之间具有第二夹角。
示例性的，所述第一竖线段、所述第二竖线段、所述第一斜线段和所述第二斜线段为同层且同材质设置的一体结构；
或者，所述第一竖线段、所述第二竖线段、所述第一斜线段和所述第二斜线段中至少两个为不同层设置，并通过过孔连接。
示例性的，所述子像素包括相对的第一侧和第二侧，所述第一侧和所述第二侧用于布设所述数据线；所述数据线包括沿所述第一方向依次连接的多个第二重复单元，所述第二重复单元包括：
第三竖线段，所述第三竖线段位于所述第一开口区的第一侧或第二侧，所述第三竖线段包括靠近所述第二开口区的第一端和远离所述第二开口区的第二端；
及，透明导电线，所述透明导电线在衬底基板之上的正投影与所述第二开口区在所述衬底基板之上的正投影至少部分重合，并与所述第三竖线段的 第一端连接，且所述的透明导电线在所述第一方向上的长度大于或等于所述第二开口区在所述第一方向上的长度。
示例性的，所述透明导电线与所述第三竖线段同层且不同材质设置；
或者，所述透明导电线与所述第三竖线段异层绝缘设置，并通过过孔连接。
示例性的，所述第三竖线段为源漏金属线，所述透明导电线为氧化铟锡导电线。
示例性的，所述显示基板还包括设置于所述衬底基板之上的公共电极层，其中所述公共电极层为不透光导电层或透光导电层，所述公共电极层上设有开口区，所述开口区限定所述第一开口区和所述第二开口区。
示例性的，所述显示基板还包括多个像素电极，每个所述子像素内设置一个所述像素电极。
示例性的，所述像素电极为透明导电电极，所述像素电极包括：
位于所述第一开口区内的第一电极块部分；
位于所述第二开口区内的第二电极块部分；
以及连接在所述第一电极块部分和所述第二电极块部分之间的连接桥部分。
示例性的，所述第一电极块部分的形状与其所对应的第一开口区的第一侧和第二侧布设的数据线的所围设的空间形状匹配。
示例性的，所述开关器件设置于所述栅线与所述数据线交叉位置。
本公开实施例所带来的有益效果如下：
本公开实施例提供的显示基板及显示装置，将显示基板上每个子像素在第一方向(即数据线延伸方向)上至少分割为间隔设置的上、下两个像素开口，即第一开口区和第二开口区，且所述第二开口区相对于所述第一开口区在第二方向(即栅线延伸方向)上偏移，且偏移距离小于或等于第一开口区在第二方向上的宽度，也就是说，在数据线延伸方向上，第一开口区和第二开口区存在部分重合、或者第二开口区相对第一开口区正好偏移一个第一开口区的宽度，这样，每个像素的第一开口区和第二开口区发光区域可以实现互补，由此实现像素发光连续，改善3D显示中摩尔纹不良现象。
附图说明
图1表示相关技术中显示基板中常规像素结构中单一像素不同位置点的透过率曲线示意图；
图2表示本公开一些实施例提供的显示基板的结构示意图；
图3表示本公开另一些实施例提供的显示基板的结构示意图；
图4表示图2所示实施例中的显示基板中单一像素不同位置点的透过率曲线示意图，其中公共电极层为不透光导电层；
图5表示图3所示实施例中的显示基板中单一像素不同位置点的透过率曲线示意图；
图6表示图2所示实施例中的显示基板中单一像素不同位置点的透过率曲线示意图，其中公共电极层为透光导电层。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在对本公开实施例提供的显示基板及显示装置进行详细说明之前，有必要对于相关技术进行以下说明：
在相关技术中，基于超高分辨率的3D显示产品存在摩尔纹等技术问题点，引起摩尔纹现象的原因之一是像素发光的不连续性。对于常规像素设计，源漏金属线(SD line)例如数据线等为直线状，且不透光，单一像素不同位置点透过率如图1所示，图1中横坐标为栅线延伸方向上单一像素内位置点，纵坐标为同一位置点处像素透过率。当显示画面时像素之间会出现周期性的不透光区域(数据线所在位置透过率为0)，使得像素发光不连续，在3D显示状态时，像素发光不连续会造成摩尔纹不良。
为了解决上述问题，本公开实施例提供了一种显示基板及显示装置，能够能够提高像素发光连续性，改善摩尔纹不良现象。
图2和图3所示为本公开实施例所提供的显示基板的结构主视图，其中仅示意出了显示基板上像素阵列的局部结构。
如图2和图3所示，所述显示基板包括衬底基板、及设置于所述衬底基板之上的多条数据线100和多条栅线200，所述数据线100沿第一方向延伸，所述栅线200沿第二方向延伸，所述数据线100和所述栅线200交叉设置，所述显示基板包括阵列分布的多个像素单元，每个像素单元包括至少两个子子像素300，每个所述子像素300至少包括在所述第一方向上间隔设置的第一开口区310和第二开口区320，所述第二开口区320相对于所述第一开口区310在所述第二方向上偏移，且偏移距离△d小于或等于所述第一开口区310在所述第二方向上的宽度L。
上述方案中，将显示基板上每个子像素300在第一方向(即数据线100延伸方向)上至少分割为间隔设置的上、下两个像素开口，即第一开口区310和第二开口区320，且所述第二开口区320相对于所述第一开口区310在第二方向(即栅线200延伸方向)上偏移，且偏移距离△d小于或等于第一开口区310在第二方向上的宽度L，也就是说，在数据线100延伸方向上，第一开口区310和第二开口区320存在部分重合、或者第二开口区320相对第一开口区310正好偏移一个第一开口区310的宽度，所述第一开口区310和所述第二开口区320为错位互补的关系，这样，每个子像素300的第一开口 区310和第二开口区320发光区域可以实现互补，由此实现子像素300发光连续，改善3D显示中摩尔纹不良现象。
需要说明的是，上述方案中，所述子像素的第一开口区和第二开口区是指，在显示基板上用于限定所述子像素的开口尺寸大小的遮光膜层上的开口区，例如，可以是，在显示基板上单独设置的像素定义层上设计开口图案，而得到所述第一开口区和第二开口区；或者，还可以是，显示基板上的遮光导电层(例如采用遮光金属制成的公共电极层等)上设计开口图案，来限定所述第一开口区和所述第二开口区。
在一些实施例中，以图2和图3所示为例，所述第二开口区320相对所述第二开口区320的偏移距离△d小于所述第一开口区310的宽度L，因此第一开口区310和第二开口区320在第二方向上会部分重合。
在另一些实施例中，以图2和图3所示为例，所述第一开口区310相对所述第二开口区320的偏移距离△d等于所述第一开口区310在第二方向上的宽度，这样，以图所示的方向为例，同一子像素300内的所述第一开口区310的左侧边缘会与所述第二开口区320的右侧边缘对齐。
此外，在一些实施例中，如图2和图3所示，在所述第二方向上相邻的两个第一开口区310之间的最小间距D等于所述偏移距离△d。仍以图2所示的方向为例，所述子像素300内的第一开口区310的右侧边缘会和其右侧相邻子像素300内的第二开口区320的左侧边缘对齐，这样，可以防止相邻子像素300间串扰。
此外，本公开一些实施例中，所述显示基板中多条栅线200和多条数据线100交叉而限定出多个子像素300，每个子像素300内设置开关器件和像素电极500，其中开关器件可以是薄膜晶体管(图中未进行示意)，包括源极、漏极和栅极，其中栅线200与栅极连接，数据线100与源极连接，漏极与像素电极500连接，栅线200作为开关器件的开关控制线，数据线100作为信号输入线。
示例性的，所述开关器件设置于所述栅线200与所述数据线100交叉位置。
在一些示例性的实施例中，同一子像素300内，所述第一开口区310和 所述第二开口区320可以共用一个开关器件，共用一条数据线100作为信号输入线，共用一条栅线200作为开关器件的开关控制线，这样可以保证同一子像素300内的第一开口区310和第二开口区320发光状态一致，以保证子像素300发光连续性。
这里需要说明的是，相关技术中的显示基板中多条栅线200和多条数据线100交叉限定出子像素300，对于一个子像素300来说，其是位于控制该子像素300的栅线200的一侧的。但是，对于本公开实施例所提供的显示基板来说，由于一个子像素300被分割为第一开口区310和第二开口区320，且同一子像素300的第一开口区310和第二开口区320需要共用一根栅线200，因此，在一些实施例中，如图2和图3所示，位于同一所述子像素300内的所述第一开口区310和所述第二开口区320所共用的一条所述栅线200可以布设于所述第一开口区310与所述第二开口区320之间。由于栅线200需要与开关器件连接，将栅线200布设于第一开口区310与第二开口区320之间，从空间布局上，有利于栅线200、开关器件、像素电极500及数据线100之间进行连接。
当然可以理解的是，在另一些实施例中，位于同一所述子像素300内的所述第一开口区310和所述第二开口区320所共用的一条所述栅线200布设于所述第一开口区310的远离所述第二开口区320的一侧。
在另一些实施例中，位于同一所述子像素300内的所述第一开口区310和所述第二开口区320所共用的一条所述栅线200布设于所述第二开口区320的远离所述第一开口区310的一侧。
此外，本公开提供的显示基板中，所述子像素300包括相对的第一侧和第二侧，所述第一侧和所述第二侧用于布设所述数据线100。图所示为例，第一侧为子子像素300的左侧，第二侧为子子像素300的右侧。以下说明中会以左侧、右侧来分别指代第一侧和第二侧，以便于说明和理解。
本公开实施例中的显示基板，如图2所示，由于子像素300中第一开口区310与第二开口区320在第二方向上偏移错位，所述子像素300的第一侧和第二侧的非透光区会呈现非直线状，且第一开口区310与第二开口区320共用一条数据线100，而所述数据线100应布设于子像素300的非透光区。 因此，在一些实施例中，所述数据线100走线可以由直线型调整为折线型，也就是说，所述数据线100呈折线状布设于所述子像素300的非开口区。
示例性的，如图2所示，所述数据线100包括沿所述第一方向依次连接的多个第一重复单元110，所述第一重复单元110包括：第一竖线段111、第二竖线段112、第一斜线段113和第二斜线段114，其中，所述第一竖线段111位于所述第一开口区310的第一侧，并沿所述第一方向延伸，包括位于远离所述第二开口区320的第一端及位于靠近所述第二开口区320的第二端；所述第二竖线段112位于所述第二开口区320的第二侧，并沿所述第二方向延伸，所述第二竖线段112包括位于靠近所述第一开口区310的第三端及位于远离所述第一开口区310的第四端；所述第一斜线段113连接在所述第一竖线段111的第二端与所述第二竖线段112的第三端之间，且所述第一斜线段113与所述第一竖线段111之间具有第一夹角α；第二斜线段114，连接在所述第一竖线段111的第一端、或者连接在所述第二竖线段112的第四端，且所述第二斜线段114与所述第一竖线段111之间具有第二夹角β。
示例性的，所述第一重复单元110大致呈“S”型或大致反“S”型的折线状。
需要说明的是，如图2所示，所述第一夹角α是指所述第一斜线段113与所述第一竖线段111之间的夹角，例如所述第一夹角α为钝角；所述第二夹角β是指所述第二斜线段114与所述第二竖线段112之间的夹角，例如所述第二夹角β为钝角。
对于所述第一夹角α和所述第二夹角β的具体角度数值，在此不限定。
示例性的，所述第一夹角α大于90°且小于150°；所述第二夹角β大于90°且小于150°。这样，在实现数据线100呈折线状的同时，可以使折线状的数据线100不会导致子像素300开口率下降。
此外，在一些示例性的实施例中，所述第一竖线段111、所述第二竖线段112、所述第一斜线段113和所述第二斜线段114为同层且同材质设置的一体结构。例如，所述第一重复单元110中所述第一竖线段111、所述第二竖线段112、所述第一斜线段113和所述第二斜线段114均为源漏金属层图案化处理后形成的图案。
在另一些实施例中，所述第一竖线段111、所述第二竖线段112、所述第一斜线段113和所述第二斜线段114中至少两个线段还可以是不同层且绝缘设置，并通过过孔连接。
此外，在本示例性的实施例中，所述数据线100与所述开关器件的漏极连接，因此，所述数据线100上应设置一用于所述开关器件连接的连接部115。示例性的，如图2所示，当所述栅线200位于第一开口区310和第二开口区320之间的非透光区位置时，所述连接部115可以设置于第一竖线段111上。当然可以理解的是，所述连接部115的具***置不限于此，可以根据栅线200的具体设置位置而选择合理的位置。
上述示例性的实施例中，由于子像素300被分割为第一开口区310与第二开口区320，因此所述数据线100设计为折线状，以匹配非透光区的布线空间。在其他实施例中，所述数据线100还可以是采用其他结构来实现。
例如，如图3所示，在另一些示例性的实施例中，所述数据线100包括沿所述第一方向依次连接的多个第二重复单元120，所述第二重复单元120包括：第三竖线段121和透明导电线122，其中，所述第三竖线段121位于所述第一开口区310的第一侧或第二侧，所述第三竖线段121包括靠近所述第二开口区320的第一端和远离所述第二开口区320的第二端；所述透明导电线122在衬底基板之上的正投影与所述第二开口区320在所述衬底基板之上的正投影至少部分重合，且所述透明导电线122在所述第一方向上的长度大于或等于所述第二开口区320在所述第一方向上的长度，并与所述第三竖线段121的第一端连接。
上述示例性的实施例中，所述数据线100可以不设置为折线状，而是通过第三竖线段121与透明导电线122直线连接成第二重复单元120，其中所述第三竖线段121与所述透明导电线122可以是中心线位于同一直线上，数据线100经过第二开口区320的部分为透光的透明导电线122，不会影响第二开口区320的透光率。
需要说明的是，如图3所示，所述透明导电线122在第一方向上的长度大于或等于所述第二开口区320在所述第一方向上的长度，也就是说，所述透光导电线在数据线延伸方向上覆盖第二开口区，这样，可以保证所述数据 线不会对第二开口区的透光率产生不良影响。
此外，如图3所示，在所述第二方向上，所述透明导电线的长度与所述第二开口区的宽度之间的关系不受限，也就是说，所述透光导电线在栅线延伸方向上可以覆盖或不覆盖第二开口区。
在本示例性的实施例中，所述透明导电线122与所述第三竖线段121同层且不同材质设置，也就是说，所述透明导电线122与所述第三竖线段121可以是同层设置，在显示基板的制程中，通过两道MASK工艺(即两次构图工艺)而分别形成第三竖线段121和透明导电线122的图案。
此外，所述透明导电线122与所述透明导电线122还可以是异层且绝缘设置，并通过过孔连接。在显示基板的制程中，可通过两道MASK工艺(即两次构图工艺)分别形成所述第三竖线段121和所述透明导电线122的图案。
在一些示例性的实施例中，所述第三竖线段121为源漏金属线，所述透明导电线122为氧化铟锡导电线。当然可以理解的是，所述第三竖线段121和所述透明导电线122的材质不限于此。
此外，在本示例性的实施例中，所述数据线100与所述开关器件的漏极连接，因此，所述数据线100上应设置一用于所述开关器件连接的连接部。示例性的，如图3所示，当所述栅线200位于第一开口区310和第二开口区320之间的非透光区位置时，所述连接部可以设置于第三竖线段121上。当然可以理解的是，所述连接部的具***置不限于此，可以根据栅线200的具体设置位置而选择合理的位置。
此外，在一些示例性的实施例中，如图2和图3所示，所述显示基板还包括设置于所述衬底基板之上的公共电极层400，其中所述公共电极层400为不透光导电层，所述公共电极层400上设有开口区410，所述开口区410限定所述第一开口区310和所述第二开口区320。
在上述方案中，所述公共电极层400采用不透光导电层，通过在所述公共电极层400上开设开口区410图案，来限定第一开口区310和第二开口区320，这样，由于公共电极的非开口区420可以起到遮光作用，有利于各子像素300不同位置点的透过率一致性。
在另一些实施例中，所述公共电极层400还可以采用透光导电层，且所 述公共电极层400上设有开口区410，所述开口区410限定所述第一开口区310和所述第二开口区320。相较于公共电极层400采用不透光导电层的方案来说，公共电极层400选用透光导电层，可能还是会存在子像素300的非透光区不同位置点透光率不一致的问题，因此，在实际应用中，若想提高子像素300不同位置点透过率一致性，可将所述公共电极层400选用不透光导电层。
此外，在一些实施例中，如图2和图3所示，所述显示基板还包括多个像素电极500，每个所述子像素300内设置一个所述像素电极500，其中所述像素电极500与所述开关器件的源极连接。
示例性的，所述像素电极500为透明导电电极，所述像素电极500包括：位于所述第一开口区310内的第一电极块部分510；位于所述第二开口区320内的第二电极块部分520；以及连接在所述第一电极块部分510和所述第二电极块部分520之间的连接桥部分530。
此外，在一些实施例中，当所述第一竖线段111上设有所述连接部时，所述第一电极块部分510的形状与其所对应的第一开口区310的第一侧和第二侧布设的数据线100的所围设的空间形状匹配。
图4为本公开一些实施例中的显示基板中像素结构的透过率曲线图，其中该显示基板中公共电极层为不透光电极层，所述数据线为折线状(例如图2所示实施例中的显示基板)。图4中横坐标为栅线200延伸方向上单一子像素300内位置点，纵坐标为同一位置点处第一开口区310和第二开口区320透过率的平均值。根据图4的曲线可知，该显示基板像素结构无透过率为0的位置，可实现子像素300的连续发光，在进行摩尔纹实验测试时，测试结果可知，可有效消除摩尔纹。
图5为本公开另一些实施例中的显示基板中像素结构的透过率曲线图，其中该显示基板中公共电极层为不透光电极层，所述数据线为包括第三竖线段和透明导电线(例如图4所示实施例中的显示基板)。图5中横坐标为栅线200延伸方向上单一子像素300内位置点，纵坐标为同一位置点处第一开口区310和第二开口区320透过率的平均值。根据图5的曲线可知，该显示基板像素结构无透过率为0的位置，可实现子像素300的连续发光，在进行摩 尔纹实验测试时，测试结果可知，可有效消除摩尔纹。
图6为本公开一些实施例中的显示基板中像素结构的透过率曲线图，其中该显示基板中公共电极层为透光电极层，所述数据线为折线状(例如图2所示实施例中的显示基板，与图4所示实施例中显示基板区别在于公共电极层为透光电极层。图6中横坐标为栅线200延伸方向上单一子像素300内位置点，纵坐标为同一位置点处第一开口区310和第二开口区320透过率的平均值。根据图6的曲线可知，该显示基板像素结构无透过率为0的位置，可实现子像素300的连续发光，在进行摩尔纹实验测试时，测试结果可知，可有效消除摩尔纹。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (16)

  1. 一种显示基板，其特征在于，包括衬底基板、及设置于所述衬底基板之上的沿第一方向延伸的多条数据线和沿第二方向延伸的多条栅线，所述显示基板包括多个子像素，每个所述子像素至少包括在所述第一方向上间隔设置的第一开口区和第二开口区，所述第二开口区相对于所述第一开口区在所述第二方向上偏移，且偏移距离小于或等于所述第一开口区在所述第二方向上的宽度。
  2. 根据权利要求1所述的显示基板，其特征在于，
    在所述第二方向上相邻的两个第一开口区之间的最小间距等于所述偏移距离。
  3. 根据权利要求1所述的显示基板，其特征在于，
    同一所述子像素内，所述第一开口区和所述第二开口区共用同一开关器件，共用同一条数据线作为信号输入线，共用同一条栅线作为所述开关器件的开关控制线。
  4. 根据权利要求3所述的显示基板，其特征在于，
    位于同一所述子像素内的所述第一开口区和所述第二开口区所共用的一条所述栅线布设于所述第一开口区与所述第二开口区之间；
    或者，位于同一所述子像素内的所述第一开口区和所述第二开口区所共用的一条所述栅线布设于所述第一开口区的远离所述第二开口区的一侧；
    或者，位于同一所述子像素内的所述第一开口区和所述第二开口区所共用的一条所述栅线布设于所述第二开口区的远离所述第一开口区的一侧。
  5. 根据权利要求1所述的显示基板，其特征在于，
    所述数据线呈折线状布设于所述子像素的非开口区。
  6. 根据权利要求5所述的显示基板，其特征在于，
    所述子像素包括相对的第一侧和第二侧，所述第一侧和所述第二侧用于布设所述数据线；所述数据线包括沿所述第一方向依次连接的多个第一重复单元，所述第一重复单元包括：
    第一竖线段，位于所述第一开口区的第一侧，并沿所述第一方向延伸， 包括位于远离所述第二开口区的第一端及位于靠近所述第二开口区的第二端；
    第二竖线段，位于所述第二开口区的第二侧，并沿所述第二方向延伸，包括位于靠近所述第一开口区的第三端及位于远离所述第一开口区的第四端；
    第一斜线段，连接在所述第一竖线段的第二端与所述第二竖线段的第三端之间，且所述第一斜线段与所述第一竖线段之间具有第一夹角；
    第二斜线段，连接在所述第一竖线段的第一端、或者连接在所述第二竖线段的第四端，且所述第二斜线段与所述第一竖线段之间具有第二夹角。
  7. 根据权利要求6所述的显示基板，其特征在于，
    所述第一竖线段、所述第二竖线段、所述第一斜线段和所述第二斜线段为同层且同材质设置的一体结构；
    或者，所述第一竖线段、所述第二竖线段、所述第一斜线段和所述第二斜线段中至少两个为不同层设置，并通过过孔连接。
  8. 根据权利要求1所述的显示基板，其特征在于，
    所述子像素包括相对的第一侧和第二侧，所述第一侧和所述第二侧用于布设所述数据线；所述数据线包括沿所述第一方向依次连接的多个第二重复单元，所述第二重复单元包括：
    第三竖线段，所述第三竖线段位于所述第一开口区的第一侧或第二侧，所述第三竖线段包括靠近所述第二开口区的第一端和远离所述第二开口区的第二端；
    及，透明导电线，所述透明导电线在衬底基板之上的正投影与所述第二开口区在所述衬底基板之上的正投影至少部分重合，并与所述第三竖线段的第一端连接，且所述的透明导电线在所述第一方向上的长度大于或等于所述第二开口区在所述第一方向上的长度。
  9. 根据权利要求8所述的显示基板，其特征在于，
    所述透明导电线与所述第三竖线段同层且不同材质设置；
    或者，所述透明导电线与所述第三竖线段异层绝缘设置，并通过过孔连接。
  10. 根据权利要求9所述的显示基板，其特征在于，
    所述第三竖线段为源漏金属线，所述透明导电线为氧化铟锡导电线。
  11. 根据权利要求1所述的显示基板，其特征在于，
    所述显示基板还包括设置于所述衬底基板之上的公共电极层，其中所述公共电极层为不透光导电层或透光导电层，所述公共电极层上设有开口区，所述开口区限定所述第一开口区和所述第二开口区。
  12. 根据权利要求1所述的显示基板，其特征在于，
    所述显示基板还包括多个像素电极，每个所述子像素内设置一个所述像素电极。
  13. 根据权利要求12所述的显示基板，其特征在于，
    所述像素电极为透明导电电极，所述像素电极包括：
    位于所述第一开口区内的第一电极块部分；
    位于所述第二开口区内的第二电极块部分；
    以及连接在所述第一电极块部分和所述第二电极块部分之间的连接桥部分。
  14. 根据权利要求13所述的显示基板，其特征在于，
    所述第一电极块部分的形状与其所对应的第一开口区的第一侧和第二侧布设的数据线的所围设的空间形状匹配。
  15. 根据权利要求3所述的显示基板，其特征在于，
    所述开关器件设置于所述栅线与所述数据线交叉位置。
  16. 一种显示装置，其特征在于，包括如权利要求1至15任一项所述的显示基板。
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