WO2023008138A1 - Crystal oscillator and manufacturing method therefor - Google Patents

Crystal oscillator and manufacturing method therefor Download PDF

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Publication number
WO2023008138A1
WO2023008138A1 PCT/JP2022/027066 JP2022027066W WO2023008138A1 WO 2023008138 A1 WO2023008138 A1 WO 2023008138A1 JP 2022027066 W JP2022027066 W JP 2022027066W WO 2023008138 A1 WO2023008138 A1 WO 2023008138A1
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Prior art keywords
layer
crystal
recess
package
crystal element
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PCT/JP2022/027066
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French (fr)
Japanese (ja)
Inventor
貴博 植田
正明 太田
孝男 楠木
広幸 石川
和也 竺原
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京セラ株式会社
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Priority to JP2023538393A priority Critical patent/JPWO2023008138A1/ja
Publication of WO2023008138A1 publication Critical patent/WO2023008138A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Definitions

  • the present disclosure relates to crystal oscillators and manufacturing methods thereof.
  • a crystal oscillator having a crystal element, an IC (Integrated Circuit), and a package holding them is known (for example, Patent Document 1 below).
  • the crystal element has, for example, a crystal blank and excitation electrodes that overlap the crystal blank.
  • the IC includes, for example, an oscillator circuit and is electrically connected to excitation electrodes via a package.
  • the oscillating circuit vibrates the crystal blank by applying an alternating voltage to the excitation electrodes, and uses this vibration to generate an oscillating signal.
  • an IC is mounted on a package by bumps made of solder.
  • a crystal oscillator includes a crystal element, an IC, a package, a connecting member, and a first Au layer.
  • the IC has terminals.
  • the package holds the crystal element and the IC.
  • the connecting members are bumps or bonding wires made of gold and bonded to the terminals and the package.
  • the terminal has a first Au layer forming a surface of the terminal and to which the connection member is bonded.
  • FIG. 1 is an exploded perspective view showing a schematic configuration of a crystal oscillator according to a first embodiment
  • FIG. FIG. 2 is a cross-sectional view of the crystal oscillator taken along line II-II of FIG. 1
  • FIG. 2 is a plan view showing the inside of the crystal oscillator of FIG. 1
  • region IV of FIG. 2 is a flow chart showing an example of the procedure of a method for manufacturing the crystal oscillator of FIG. 1; Sectional drawing corresponding to a part of FIG. 4 which shows the structure of a comparative example.
  • FIG. 5 is a cross-sectional view showing a schematic configuration of a crystal oscillator according to a second embodiment
  • FIG. 8 is an enlarged view of region VIII of FIG.
  • FIG. 5 is a cross-sectional view showing a schematic configuration of a crystal oscillator according to a third embodiment
  • FIG. 5 is a cross-sectional view showing a schematic configuration of a crystal oscillator according to a fourth embodiment
  • FIG. 5 is a diagram showing temporal changes in the characteristics of an oscillator according to a comparative example
  • FIG. 4 is a diagram showing temporal changes in the characteristics of the oscillator according to the example
  • the drawings may be labeled with an orthogonal coordinate system D1-D2-D3 for convenience.
  • any direction may be the upper side or the lower side, but for the sake of convenience, the +D3 side may be referred to as the upper side, and terms such as the upper surface and the lower surface may be used hereinafter.
  • first insulating layer 31A and “second insulating layer 31B”
  • simply "insulating layer 31" may be indicated by a number and additional signs may be omitted to distinguish between them.
  • rectangle may include a shape with chamfered corners unless otherwise specified. The same is true for other polygons. Also, shapes other than polygons do not have to be shapes that are strictly defined by mathematics. Of course, the various shapes may be strictly mathematically defined shapes.
  • the "main component” may be, for example, a component that accounts for 50% by mass or more of the material. When two or more components are the main components, the total of the two or more components is 50% by mass or more. It should be noted that the mass % of various main components to be described later may be, for example, 80 mass % or more or 90 mass % or more upon implementation.
  • the member When the member is made of "gold" (or Au), the member may be made of metal containing 99.9% or more by mass of Au. That is, the member may contain less than 0.1% by mass of impurities. Impurities may be unavoidably mixed (unintended) or intentionally added. Impurities that are intentionally added include, for example, those that adjust the crystalline state. In addition, the mass % of Au in various members made of Au, which will be described later, may be 99.99% or more or more in practice.
  • the metal in the completed oscillator may be formed by firing a conductive paste. Therefore, even materials referred to simply as metals in the following description may include inorganic materials contained in the conductive paste.
  • FIG. 1 is an exploded perspective view showing a schematic configuration of a crystal oscillator 1 (hereinafter, "crystal” may be omitted) according to the first embodiment.
  • FIG. 2 is a cross-sectional view taken along line II--II of FIG.
  • FIG. 3 is a plan view showing the inside of the oscillator 1.
  • FIG. 2 for the sake of convenience, strictly speaking, members that are not located on the same cross section are also shown together.
  • the oscillator 1 is, for example, an electronic component that generally has a thin rectangular parallelepiped shape as a whole.
  • the dimensions of oscillator 1 are arbitrary.
  • the length of the long side and short side is 1 mm or more and 10 mm or less.
  • the thickness is 0.2 mm or more and 2 mm or less on the premise that it is smaller than the length of the short side.
  • the oscillator 1 generates an oscillation signal, for example, by being supplied with DC power of a predetermined voltage.
  • An oscillating signal is a signal whose signal level (for example, potential) oscillates at a constant period.
  • the frequency of the oscillation signal generated by the oscillator 1 is arbitrary. For example, when it is assumed that the crystal element (described later) applied to the embodiment may have various aspects (shape, vibration mode, etc.), the frequency of the oscillation signal may be 1 kHz or more and 1 GHz or less.
  • the oscillator 1 has, for example, a crystal element 3, an IC 5, and a package 7 that holds (for example, accommodates) these elements, as particularly shown in FIG. Package 7 has a base 9 and a lid 11 . Note that FIG. 3 shows the inside of the oscillator 1 by omitting the lid 11 .
  • the crystal element 3 generates natural vibration when an AC voltage is applied.
  • the IC5 includes an oscillation circuit (not shown).
  • the oscillation circuit applies a voltage to the crystal element 3 and utilizes the natural oscillation in the crystal element 3 to generate an oscillation signal.
  • the package 7 contributes to protection of the crystal element 3 and the IC 5, transmission of electrical signals to these elements, and the like.
  • the crystal element 3 and the IC 5 are mounted on the base 9 of the package 7, for example. That is, the crystal element 3 and the IC 5 are fixed to the base 9 and electrically connected.
  • a lid 11 of the package 7 is fixed to the base 9 so as to form a closed space S1 in which the crystal element 3 and the IC 5 are accommodated.
  • the closed space S1 is, for example, evacuated or filled with an appropriate gas (eg, nitrogen).
  • the crystal element 3 is fixed and electrically connected to the base 9 by two conductive adhesives 41 (FIGS. 2 and 3).
  • the IC 5 is fixed to the base 9 by an adhesive 43 (FIG. 2) and electrically connected to the base 9 by a plurality (eight in the example shown) of bonding wires 45 (FIGS. 2 and 3). It is connected to the. At least part of the IC 5 may be covered with a sealing resin 49 (see FIG. 11 described later).
  • a member (bonding wire 45 in the illustrated example) that electrically connects the IC 5 and the package 7 (base 9) is sometimes called a connection member.
  • the oscillator 1 has, for example, a new configuration regarding the bonding between the connecting member and the IC 5 .
  • Other configurations may be in various aspects, for example, may be in known aspects.
  • the structure of the crystal element 3, the structure of the IC 5 (excluding the structure related to the bonding described above), the structure of the package 7, and the mounting structure of each element (the bonding described above) shown in FIGS. ) etc. is merely an example.
  • the outer shape of the oscillator 1 does not have to be rectangular parallelepiped.
  • the description of (1) may include description of novel aspects without any particular notice. Also, the description of (1) will be made by taking the mode shown in FIGS. 1 to 3 as an example. In the explanation of (1), the crystal element 3, the IC 5, the package 7 (the base portion 9 and the lid 11), and the members involved in mounting (the conductive adhesive 41, the adhesive 43 and the bonding wire 45) are explained in order. After that, the positional relationship between the crystal element 3 and the IC 5 will be described.
  • the crystal element 3 includes, for example, a crystal blank 13 , two or more (one pair in the illustrated example) excitation electrodes 15 for applying a voltage to the crystal blank 13 , and the crystal element 3 mounted on the base 9 of the package 7 . It has two or more (one pair in the illustrated example) extraction electrodes 17 for the purpose.
  • the shape of the crystal blank 13, the excitation electrode 15, and the extraction electrode 17 is such that either of the two surfaces of the crystal element 3 may be the mounting side (-D3 side). (longitudinal direction)), and may be formed into a shape approximately 180° rotationally symmetrical with respect to a center line (not shown).
  • the shapes of the crystal blank 13, the excitation electrode 15, and the extraction electrode 17 do not have to be rotationally symmetrical.
  • the planar shape of the crystal blank 13 may be rectangular (example shown), circular, or elliptical.
  • the thickness of the crystal blank 13 may be constant or may not be constant (example shown). As an example of the latter, although not shown, a so-called mesa shape in which the central portion is thicker than the outer peripheral portion can be cited.
  • the crystal blank 13 has a relatively thin portion and a relatively thick portion.
  • a pair of excitation electrodes 15 are located in the thin portion.
  • the thick portion is located, for example, at one end (one side) of the crystal blank 13, and a pair of extraction electrodes 17 are located.
  • the thicker portions can, for example, increase the strength of the crystal blank 13 .
  • the thick portions may be formed, for example, on two sides, three sides, or four sides of the crystal blank 13 . From another point of view, the thick portion may be formed in a region where the extraction electrode 17 is not located.
  • the planar shape of the excitation electrode 15 may be a circular shape (example shown in the drawing), a rectangular shape, or an elliptical shape. Further, the planar shape of the excitation electrode 15 may be a shape similar to the planar shape of the crystal blank 13 (or the planar shape of the mesa portion), or may not be such a shape (example shown in the figure). ).
  • the former includes a rectangular-rectangular combination, a circular-circular combination, and an elliptical-elliptical combination.
  • the lead-out electrode 17 has, for example, a wiring portion extending from the excitation electrode 15 and a pad-like terminal portion connected to the tip of the wiring portion, although no particular reference numeral is attached.
  • the terminal portion is a portion that is joined to the base portion 9 of the package 7 .
  • the terminal portion included in one extraction electrode 17 has two portions located on both sides of the crystal blank 13 so that either side of the crystal element 3 can be the mounting side. are doing. These two portions are, for example, the end surface of the crystal blank 13 (the surface on the -D1 side), the side surface of the crystal blank 13 (the surface on the +D2 side or the -D2 side), and a through hole (not shown) formed in the crystal blank 13. They are connected to each other through at least one of the holes.
  • the crystal element 3 may have a configuration other than the above.
  • the crystal element 3 may be a tuning fork type element using bending vibration, a CT cut or DT cut element using contour shear vibration, or an element using SAW (surface acoustic wave).
  • Such an element also has a crystal blank 13 and two or more excitation electrodes 15 overlapping the crystal blank 13 .
  • the crystal blank layer of crystal may overlap layers of other materials.
  • the thickness of the crystal blank 13 may be set as appropriate for the crystal blank 13 that is not plate-shaped and/or the crystal blank 13 whose thickness is not a factor that determines the frequency.
  • the thickness of such a crystal blank 13 may be 5 ⁇ m or more and 30 ⁇ m or less.
  • the thickness direction of the non-platy crystal blank 13 may be reasonably determined from its overall shape. For example, in a tuning fork type, the dimension in the direction orthogonal to both the direction in which two or more arms extend in parallel and the direction in which the two or more arms are arranged is the thickness.
  • the IC 5 has a chip body 19 having various circuits inside, and a plurality of IC terminals 21 that mediate connections between the circuits and the outside of the IC 5 .
  • eight IC terminals 21 are shown as shown in FIG. In FIG. 2, only one IC terminal 21 on the -D1 side is shown. In FIG. 3, the two IC terminals on the -D1 side are hidden by the crystal element 3 and are not shown.
  • the chip body 19 has a substrate made of, for example, a semiconductor (eg, silicon). have a circuit.
  • the circuit included in the chip body 19 is, for example, the oscillation circuit described above.
  • the chip body 19 may include a temperature sensor and a temperature compensation circuit that compensates for temperature changes in the oscillation signal based on the temperature detected by the temperature sensor.
  • the IC 5 (chip body 19) may be packaged or may be a bare chip.
  • the shape of the chip body 19 is arbitrary. In general, the shape of the chip body 19 is a thin rectangular parallelepiped, as shown in the drawing. Moreover, the dimensions of the chip body 19 are also arbitrary. For example, the width (area) of the chip body 19 in plan view may be larger than the width of the crystal element 3 in plan view (example shown), may be the same, or may be smaller. The width of the crystal element 3 in plan view may be the minimum rectangular width that includes the crystal element 3 when the crystal element 3 is not plate-shaped like a tuning fork.
  • the thickness of the chip body 19 may be thicker than the thickness of the crystal element 3 (the thickness of the portion where the excitation electrode 15 overlaps, or the maximum thickness) (example shown), or may be the same. It may be fine, or it may be thin.
  • the number and roles of the IC terminals 21 may be appropriately set according to the functions required of the IC 5 (oscillator 1).
  • the IC terminals 21 may include the following terminals.
  • the IC terminals 21 may include the following terminals.
  • the IC terminal 21 is composed of, for example, a pad that overlaps one of the two main surfaces (the widest surface; front and back) of the IC 5 .
  • the planar shape, size and arrangement position of the IC terminal 21 are arbitrary.
  • the planar shape and dimensions of the plurality of IC terminals 21 may be the same (example shown) or may be different.
  • the planar shape of the IC terminal 21 may be rectangular (illustrated example), circular, or elliptical.
  • the width of one IC terminal 21 in plan view may be smaller than the width of the portion facing the -D3 side of the terminal portion of one extraction electrode 17 (example shown), or may be the same. and can be larger.
  • the plurality of IC terminals 21 may be arranged in a row generally along the outer edge of the chip body 19 (example shown), or unlike the example shown in the figure, may be arranged in a row along the outer edge. It may also include another IC terminal 21 positioned inside the plurality of IC terminals 21 .
  • the package 7 has a base 9 and a lid 11 fixed to the base 9, as described above.
  • the base 9 and the lid 11 form a sealed space S1 that accommodates the crystal element 3 and the IC5.
  • the specific shapes of the base portion 9 and the lid 11, the mounting structure of the crystal element 3 and the IC 5 with respect to the base portion 9, the relative positions of the crystal element 3 and the IC 5, and the like may be made as appropriate.
  • the base portion 9 has a first surface 9a (the bottom surface of the recess in the illustrated example) facing the +D3 side.
  • the lid 11 is fixed to the base 9 so as to form a closed space S1 on the first surface 9a.
  • the IC 5 is fixed to the first surface 9a and accommodated in the sealed space S1.
  • the crystal element 3 is accommodated in the closed space S1 at a position facing the first surface 9a through the IC5. That is, the illustrated package 7 accommodates the crystal element 3 and the IC 5 in a stacked manner on the first surface 9a. Specifically, it is as follows.
  • the base 9 has, for example, an insulating substrate 23 and various conductors (eg, metal) provided on the substrate 23 .
  • the base 23 for example, occupies most of the base 9 , and the base 9 has substantially the same shape as the base 23 .
  • Various conductors constitute, for example, pads to which the crystal element 3 and the IC 5 are electrically connected.
  • the shape, size and material of the substrate 23 are arbitrary.
  • the outer shape of the base 23 is substantially rectangular parallelepiped.
  • the base 23 includes a first recess 25 opening on the top surface, a second recess 27 opening on the bottom surface of the first recess 25, and a bottom surface of the second recess 27 opening on the bottom surface. and a third recessed portion 29 which is provided.
  • the third recess 29 accommodates the IC5.
  • the bottom surface of the third concave portion 29 (strictly speaking, a die pad 42 described later overlapping with the bottom surface) is an example of the first surface 9a described above.
  • the second recess 27 accommodates the bonding wire 45 .
  • the first recess 25 accommodates the crystal element 5 .
  • the base 23 may be regarded as having one recess. Further, assuming that the one concave portion has a first bottom surface including the bottom surface (first surface 9a) of the third concave portion 29, the first bottom surface is provided with a first pedestal (the upper surface of which is the bottom surface of the second concave portion 27). ) is formed, and the second pedestal (the upper surface of which includes the bottom surface of the first recess 25 ) is formed on the upper surface of the first pedestal.
  • the base 23 is composed of, for example, a plurality of (four in this embodiment) first insulating layers 31A to fourth insulating layers 31D.
  • the base 9 comprises a first insulating layer 31A, a second insulating layer 31B having an opening forming a third recess 29, and a second recess 27, in this order from the bottom surface of the base 9. It has a third insulating layer 31 ⁇ /b>C having an opening and a fourth insulating layer 31 ⁇ /b>D having an opening forming the first recess 25 .
  • the substrate 23 may be produced by laminating the insulating layer 31, or may be produced by a manufacturing method different from such a manufacturing method.
  • a method of laminating and firing a plurality of ceramic green sheets to be a plurality of insulating layers 31 can be used.
  • the latter method for example, there is a method of forming concave portions (25, 27 and 29) in one ceramic green sheet by pressing and firing.
  • the former manufacturing method and the latter manufacturing method may be combined.
  • the insulating layer 31 may be of convenience that is conceived based on the shape of the substrate 23 and/or the conductor layers within the substrate 23 .
  • the shape of the outer edges of the plurality of insulating layers 31 is, for example, a rectangular shape corresponding to the rectangular parallelepiped shape of the substrate 23 .
  • the planar shape of each recess (25, 27 and 29) is, for example, a rectangular shape having four sides parallel to the rectangle of the outer edge of the insulating layer 31.
  • the thickness of each insulating layer 31 (the depth of each recess) may be the same as or different from each other, and may be appropriately set according to the thicknesses of the crystal element 3 and the IC 5. .
  • the second recess 27 is, for example, smaller than the first recess 25 in at least one of the D1 direction (longitudinal direction of the base 23) and the D2 direction (lateral direction of the base 23) (the D1 direction in the illustrated example).
  • the bottom surface of the first recess 25 (the upper surface of the third insulating layer 31C) is exposed upward around the second recess 27 .
  • the bottom surface of the first recess 25 may refer to only the area around the second recess 27 (only the area excluding the area where the second recess 27 is open).
  • the bottom surface of the first concave portion 25 is used for mounting the crystal element 3, for example.
  • the third recess 29 is smaller than the second recess 27, for example, in at least one (both in the illustrated example) of the D1 direction (longitudinal direction of the base 23) and the D2 direction (lateral direction of the base 23).
  • the bottom surface of the second recess 27 (the upper surface of the second insulating layer 31B) is exposed upward around the third recess 29 .
  • the bottom surface of the second recess 27 may refer to only the area around the third recess 29 (only the area excluding the area where the third recess 29 is open).
  • the bottom surface of the second recess 27 is used, for example, for electrical connection with the IC 5 and the conductors of the base 9 .
  • the relative positions and relative sizes of the plurality of recesses (25, 27 and 29) in plan view are arbitrary. These are appropriately set in consideration of, for example, the size of the elements accommodated in each recess, and the arrangement position of a conductor layer (for example, pads connected to various elements) formed on the bottom surface of each recess. you can A specific example thereof will be described later together with the description of the conductor layer.
  • the material of the substrate 23 may be ceramic, for example.
  • the plurality of insulating layers 31 are made of ceramic, for example, and are integrally formed. Any specific type of ceramic may be used, and examples include aluminum oxide (alumina, Al 2 O 3 ), aluminum nitride (AlN), and LTCC (Low Temperature Co-fired Ceramics).
  • the coefficient of linear expansion of the material is, for example, 3 ppm/K or more and 13 ppm/K or less.
  • the Young's modulus of the material is, for example, 50 GPa or more and 350 GPa or less.
  • the material of the substrate 23 may be an insulating material other than ceramic (for example, resin).
  • a pair of crystal pads 33 are connected to two IC pads 35 via wiring conductors of the base 9 . This allows the IC 5 to apply voltage to the crystal element 3 .
  • IC pads 35 other than the two IC pads 35 are connected to external terminals 37 via, for example, wiring conductors of the base portion 9 . This allows the IC 5 to input an electric signal from outside the oscillator 1 and output an electric signal to the outside of the oscillator 1 .
  • the crystal pad 33 is positioned, for example, on the bottom surface of the first recess 25 (the area around the second recess 27).
  • the planar shape and dimensions of the bottom surface of the first recess 25 and the planar shape and dimensions of the crystal pad 33 are arbitrary, and the relative relationship between them is also arbitrary.
  • the crystal pad 33 may be positioned on any of the -D1 side (example shown), +D1 side, -D2 side and +D2 side with respect to the second concave portion 27 .
  • the second recess 27 has the same size as the first recess 25 in the D2 direction.
  • the +D1 side edge of the second recess 27 coincides with the +D1 side edge of the first recess 25 . That is, the bottom surface of the first recess 25 (the area surrounding the second recess 27) is exposed only on the -D1 side.
  • the pair of crystal pads 33 extends over the bottom surface of the first recess 25 in the D1 direction.
  • the pair of crystal pads 33 are separated from each other in the D2 direction and extend to the end of the bottom surface of the first recess 25 in the D2 direction. With such a configuration, for example, both the area of the crystal pad 33 and the area of the second recess 27 can be increased.
  • the length of the crystal pad 33 in the D1 direction may be shorter than the length of the bottom surface of the first recess 25 in the D1 direction. Further, the crystal pad 33 does not have to extend to the end of the bottom surface of the first recess 25 in the D2 direction.
  • the bottom surface of the first recess 25 (region around the second recess 27) has a portion located on the +D1 side, the ⁇ D2 side and/or the +D2 side in addition to or instead of the portion located on the ⁇ D1 side. You may have These portions may or may not overlap with the crystal element 3 in planar see-through.
  • the crystal element 3 When the crystal element 3 is supported at both ends, for example, it may be supported by the ⁇ D1 side portion and the +D1 side portion of the bottom surface of the first concave portion 25 . Also, for example, part of the second recess 27 may be located between the pair of crystal pads 33 .
  • the IC pad 35 is located, for example, on the bottom surface of the second recess 27 (region around the third recess 29).
  • the planar shape and dimensions of the bottom surface of the second recess 27 and the planar shape and dimensions of the IC pad 35 are arbitrary, and the relative relationship between them is also arbitrary.
  • the IC pad 35 may be located on the -D1 side (illustrated example), the +D1 side, the -D2 side (illustrated example), or the +D2 side (illustrated example) with respect to the third recess 29. .
  • the third recess 29 is smaller than the second recess 27 in both the D1 direction and the D2 direction. Also, the third recess 29 is biased toward the +D1 side with respect to the second recess 27 . As a result, the bottom surface of the second recess 27 (region around the third recess 29) is mainly exposed on the -D1 side, the -D2 side and the +D2 side.
  • a plurality of IC pads 35 are provided in the same number as the IC terminals 21 (eight in the illustrated example), and are arranged along the opening edge of the third recess 29 . For example, the IC pad 35 extends over the bottom surface of the second recess 27 from the inner peripheral side (the third recess 29 side) to the outer peripheral side.
  • the number of IC pads 35 may be greater than the number of IC terminals 21 . In other words, there may be dummy IC pads 35 that are not used. Further, for example, the length from the inner circumference side to the outer circumference side of the IC pad 35 may be shorter than the length from the inner circumference side to the outer circumference side of the bottom surface of the second recess 27 .
  • the bottom surface of the second recess 27 (the area surrounding the third recess 29) may have a sufficient width on the +D1 side, or conversely, may be wide enough on the -D1 side, the -D2 side and/or the +D2 side. It does not have to have a portion to be located. Also, for example, a part of the third recess 29 may be positioned between the IC pads 35 adjacent to each other along the opening edge of the third recess 29 .
  • the material of the crystal pad 33 is arbitrary.
  • the crystal pad 33 may be composed of one metal layer, or may be composed of two or more metal layers. At least part of the material of the crystal pads 33 may be the same as at least part of the material of other conductor layers (for example, the material of the IC pads 35 (described later)) of the base 9, or may be completely different. may In any case, the description of the material of the IC pads 35 to be described later may be applied to the material of the crystal pads 33 .
  • the thickness of the crystal pad 33 is also arbitrary.
  • the thickness of the crystal pad 33 may be the same as or different from the thickness of the IC pad 35 (described later). In any case, the description of the thickness of the IC pad 35 may be used for the thickness of the crystal pad 33 .
  • the plurality of external terminals 37 are composed of, for example, layered conductors (pads) located on the lower surface of the substrate 23 .
  • the oscillator 1 is mounted on the circuit board by joining the pads of the circuit board (not shown) and the external terminals 37 with solder or the like interposed therebetween. That is, the oscillator 1 in the illustrated example is of a surface mount type.
  • the number of external terminals 37, planar shape, size, position on the bottom surface, etc. are arbitrary. In the illustrated example, four external terminals 37 are positioned at four corners of the rectangular base 23 .
  • the shape of the external terminal 37 is, for example, rectangular. Note that, unlike the illustrated example, the number of external terminals 37 may be five or more. Also, the external terminal 37 may be pin-shaped. That is, the oscillator 1 does not have to be of the surface mount type.
  • the number and roles of the external terminals 37 may be appropriately set according to the functions required of the oscillator 1.
  • the plurality of external terminals 37 includes at least three external terminals 37 corresponding to the ground potential, power supply voltage and oscillation signal described in the description of the IC terminal 21 .
  • the plurality of external terminals 37 may further include external terminals 37 corresponding to control signals and the like.
  • the external terminals 37 may include dummy external terminals 37 that are used only for joining the oscillator 1 to the circuit board (not used for transmitting electrical signals).
  • the material of the external terminal 37 is arbitrary.
  • the external terminal 37 may be composed of one metal layer, or may be composed of two or more metal layers. At least part of the material of the external terminals 37 may be the same as at least part of the material of other conductor layers (for example, the material of the IC pads 35 (described later)) of the base 9, or may be completely different. good too. In any case, the description of the material of the IC pads 35 to be described later may be applied to the material of the crystal pads 33 .
  • the thickness of the external terminal 37 is also arbitrary.
  • the wiring conductor may be composed of a layered conductor (layered wiring) located on the upper surface or the lower surface of the insulating layer 31 and/or a penetrating conductor (via conductor) penetrating the insulating layer 31 .
  • any material can be used for the wiring conductor.
  • at least part of these materials may be the same as at least part of the materials of the other conductor layers of the base 9, or may be completely different.
  • the material of the portion of the wiring conductor embedded in the substrate 23 may be the same as the material of the lower layer 59 (described later) of the IC pad 35 .
  • the description of the material of the IC pads 35 may be applied to the wiring conductors as appropriate.
  • the first joining metal layer 39 is a member joined to the lid 11 by seam welding, for example.
  • the first bonding metal layer 39 is located on the upper surface of the base 23 (the portion surrounding the first recess 25 ) and extends over the entire circumference of the first recess 25 .
  • the width of the first bonding metal layer 39 is, for example, equivalent to the width of the upper surface of the base 23 . However, the former may be thinner than the latter.
  • the material and thickness of the first joining metal layer 39 may be set as appropriate.
  • the material of the first bonding metal layer 39 may be the same as or different from the material of the other conductor layers of the base 9 (for example, the material of the IC pads 35 (described later)). In any case, the description of the material of the IC pad 35 to be described later may be applied to the material of the first bonding metal layer 39 .
  • the first bonding metal layer 39 is composed of a layer made of W or Mo or an alloy containing at least one of these as a main component, a Ni layer overlapping the layer, and an Au layer overlapping the Ni layer. you can
  • the thickness of the first bonding metal layer 39 is, for example, 10 ⁇ m or more and 25 ⁇ m or less.
  • the die pad 42 is a member to which the lower surface of the IC 5 is adhered on its upper surface.
  • the die pad 42 contributes, for example, to improving the adhesive strength between the IC 5 and the base 9, improving the heat dissipation of the IC 5, and/or reducing noise.
  • Any material can be used for the die pad 42 .
  • the material of the die pad 42 may be the same as or different from the material of other conductor layers of the base 9 (for example, the material of the IC pads 35 (described later)). In any case, the description of the material of the IC pad 35 to be described later may be applied to the material of the die pad 42 . Note that the die pad 42 may not be provided.
  • the lid 11 is, for example, a plate-like member.
  • the lid 11 has, for example, a frame-shaped second bonding metal layer 47 on its lower surface.
  • the inside of the package 7 is hermetically sealed by joining the first joining metal layer 39 and the second joining metal layer 47 by seam welding or the like. That is, a closed space S1 is formed.
  • the lid 11 may be joined by a method other than seam welding.
  • the shape, material and dimensions of the lid body are arbitrary.
  • the shape and size of the outer edge of the lid body in plan view are generally the same as the shape and size of the outer edge of the upper surface of the base 9 in plan view.
  • the material of the lid body may be, for example, metal.
  • the metal may be, for example, iron, nickel or cobalt, or an alloy based on at least one of these.
  • the shape, material and dimensions of the second bonding metal layer 47 are arbitrary.
  • the shape and dimensions of the second bonding metal layer 47 are substantially the same as the shape and dimensions of the first bonding metal layer 39 .
  • the second bonding metal layer 47 is made of, for example, silver solder or gold tin.
  • the thickness of the second bonding metal layer 47 is, for example, 10 ⁇ m or more and 40 ⁇ m.
  • the mass % of Au may be, for example, 75 mass % or more and 85 mass % or less.
  • the conductive adhesive 41 has an insulating binder and conductive filler (conductive powder) dispersed in the binder.
  • the binder may be an organic material (eg, resin) or an inorganic material.
  • the resin may be, for example, a silicone resin, an epoxy resin, a polyimide resin, or a bismaleimide resin.
  • the material of the conductive filler may be metal, for example.
  • the metal may be, for example, aluminum, molybdenum, tungsten, platinum, palladium, silver, titanium, nickel or iron, or an alloy based on one or more of these.
  • the conductive adhesive 41 is interposed between the extraction electrode 17 (more specifically, its terminal portion) and the crystal pad 33 to join them together.
  • the conductive adhesive 41 is bonded, for example, to at least the area of the extraction electrode 17 facing the -D3 side.
  • the conductive adhesive 41 may be bonded to the area facing the -D1 side and/or the area facing the -D2 side or the +D2 side of the extraction electrode 17 .
  • the adhesive 43 is interposed between the bottom surface of the IC 5 and the bottom surface of the third recess 29 (the first surface 9a and the die pad 42) to bond them together.
  • the adhesive 43 spreads over substantially the entire lower surface of the IC 5, for example.
  • the material of the adhesive 43 is arbitrary.
  • the material of the adhesive 43 may be an insulating material or a conductive material.
  • the insulating material may be an organic material or an inorganic material.
  • the organic insulating material is, for example, a resin, and more specifically, may be a thermosetting resin that hardens when heated.
  • the resin may be the same as the resin forming the conductive adhesive 41, or may be different.
  • the conductive material may be, for example, a suitable metal. When the conductive material is solder, a material with a relatively high melting point may be selected so as not to be melted by an annealing treatment or the like, which will be described later.
  • Each bonding wire 45 has one end joined to the IC terminal 21 and the other end joined to the IC pad 35 . Thereby, the IC 5 is electrically connected to the package 7 (base portion 9).
  • the package 7 base portion 9
  • the bonding wires 45 may be formed by so-called ball bonding (the example shown in the figure) or may be formed by wedge bonding.
  • one end of the bonding wire 45 may be ball-shaped (dome-shaped or disk-shaped after bonding; hereinafter sometimes referred to as an enlarged diameter portion) having a diameter larger than that of the other portion. (illustrated example), but need not be such a shape. If ball bonding is used, the enlarged diameter portion may be located at the IC terminal 21 (example shown) or at the IC pad 35 .
  • enlarged diameter portions are formed at both ends of the bonding wire 45. may be configured.
  • the specific shape and dimensions of the bonding wire 45 are arbitrary.
  • the bonding wire 45 extends with a generally constant cross-section except at both ends.
  • the cross-sectional shape is, for example, circular.
  • the bonding wire 45 extends in a curved shape (loop shape) that is convex upward (+D3 side). In plan view, the bonding wire 45 extends linearly. The extending direction may be set appropriately. From another point of view, the relative positions of the IC terminals 21 and the IC pads 35 that are connected to each other are arbitrary.
  • the diameter of the portion of the bonding wire excluding both ends is, for example, 10 ⁇ m or more and 50 ⁇ m or less.
  • the diameter of the enlarged diameter portion of the bonding wire 45 in plan view (after bonding) is, for example, 70 ⁇ m or more and 100 ⁇ m or less.
  • the crystal element 3 faces the first surface 9a (bottom surface of the third recess 29) via the IC5.
  • the width, etc., where the crystal element 3 and the IC 5 overlap is arbitrary.
  • the term "IC5" may be replaced with "first surface 9a" as long as there is no contradiction.
  • a portion of the crystal element 3 overlaps the bottom surface of the first concave portion 25 and is bonded to the bottom surface with a conductive adhesive 41 . Therefore, the crystal element 3 may partially (illustrated example) or all of the remaining portion overlap the IC 5 .
  • the relative extent of the overlapping regions in the crystal element 3 is arbitrary.
  • the ratio of the area of the overlapping region to the area of the crystal element 3 may be less than 1/2 (the example shown in the figure) or may be 1/2 or more.
  • the overlapping region may occupy a part (illustrated example) or the whole of the thin portion of the crystal element 3 and may occupy a part (illustrated example) or the whole of the excitation electrode 15 .
  • the IC 5 may partially or wholly overlap the crystal element 3 .
  • the relative width of the overlapping region at IC5 is arbitrary.
  • the ratio of the area of the overlapping region to the area of the IC 5 may be less than 1/2 (the example shown in the figure) or may be 1/2 or more.
  • the position of the geometric center of the crystal element 3 in the D2 direction and the position of the geometric center of the IC 5 in the D2 direction match. Unlike the illustrated example, both may be offset from each other. Also, the width of the crystal element 3 in the D2 direction is smaller than the width of the IC 5 in the D2 direction. The width of the former is within the width of the latter. Unlike the illustrated example, the width of the former may be greater than the width of the latter, or the width of the former may protrude from the width of the latter due to this or due to the displacement of the geometric center.
  • the crystal element 3 may overlap at least a portion of at least one IC pad 35, at least a portion of at least one bonding wire 45, and/or at least a portion of at least one IC terminal 21. However, it does not have to overlap these members at all.
  • the crystal element 3 is part of the two IC pads 35 on the -D1 side, all of the two bonding wires 45 connected to the IC pads 35, and connected to the two bonding wires 45. are overlapped for all of the two IC terminals 21 connected.
  • the term “crystal element 3" may be replaced with the term "thin portion of crystal element 3" or "excitation electrode 15" as long as there is no contradiction.
  • FIG. 4 is a cross-sectional view showing an enlarged region IV of FIG.
  • a bonding wire 45 (an example of a connection member) is made of gold (Au). At least the surface (more strictly, the upper surface (+D3 side surface)) of the IC terminal 21 is made of Au. Therefore, the bonding between the bonding wire 45 and the IC terminal 21 is a Au-to-Au bonding. This reduces the possibility of voids (and cracks) occurring in the bonding wires 45, as will be described in detail later.
  • the structure related to the bonding of the bonding wire 45 may take various forms, for example, a known form, except that the surfaces of the bonding wire 45 and the IC terminal 21 are made of Au as described above. I don't mind. Of course, novel aspects may also be applied.
  • the material of the IC terminal 21 and the material of the IC pad 35 will be described below, focusing on the illustrated example.
  • the IC terminal 21 is composed of, for example, four metal layers. Specifically, in the IC terminal 21 , a first layer 51 , a second layer 53 , a third layer 55 and an Au layer 57 made of different materials are laminated in order from the chip body 19 side of the IC 5 .
  • the Au layer 57 is, as its name suggests, a layer made of Au. Since the Au layer 57 forms the upper surface of the IC terminal 21, the upper surface of the IC terminal 21 is made of Au.
  • the first layer 51 may be located below the insulating protective layer of the chip body 19, and the IC terminal 21 may be formed by a portion exposed through an opening formed in the protective layer.
  • the side surface of each layer is exposed.
  • the side surfaces of some layers on the chip body 19 side may be covered with the chip body 19 (for example, the protective layer described above).
  • the side surface of the relatively lower ( ⁇ D3 side) layer may be covered with the relatively upper (+D3 side) layer (for example, the Au layer 57).
  • the influence of the side surface is limited. Therefore, the description of the conductor layer may not distinguish between the upper surface and the front surface.
  • the materials of the first layer 51, the second layer 53 and the third layer 55 are arbitrary.
  • the first layer 51 is made of aluminum or an alloy containing aluminum as a main component.
  • the second layer 53 is made of nickel or an alloy containing nickel as a main component.
  • the third layer 55 is made of palladium or a palladium-based alloy.
  • each layer constituting the IC terminal 21 is arbitrary.
  • each layer generally has a constant thickness.
  • each layer may have a different thickness, such as being thinner on the outer edge side.
  • any of these layers may be thicker than the other layers.
  • one of the first layer 51 and the second layer 53 may be thicker than the other.
  • the third layer 55 and the Au layer 57 may be thinner than the first layer 51 and/or the second layer 53, for example. Either the third layer 55 or the Au layer 57 may be thicker than the other.
  • the thickness of each layer may be, for example, 0.05 ⁇ m or more and 10 ⁇ m or less.
  • the second layer 53 and/or the third layer 55 may be omitted. Conversely, additional layers may be added. Further, instead of the first layer 51, a through conductor (non-layered conductor) is exposed from the chip body 19, and another layer (second layer 53, third layer 55 or Au layer 57) is superimposed thereon. may The materials of the first layer 51, the second layer 53 and the third layer 55 may be other than the materials described above. For example, W, Cu, Ti or Cr, or an alloy containing at least one of these as a main component may be used.
  • the IC pad 35 is composed of, for example, two metal layers. Specifically, in the IC pad 35 , a lower layer 59 and an upper layer 61 made of different materials are laminated in order from the substrate 23 side of the base 9 . In addition, in FIG. 4, the side surface of each layer is exposed. In contrast to the illustrated example, the sides of lower layer 59 may be covered by upper layer 61 .
  • the material of the lower layer 59 and the upper layer 61 are arbitrary.
  • the material of the lower layer 59 may be Ni, W, Cu, Al, or an alloy containing at least one of these as a main component.
  • the material of the upper layer 61 may be Au, Ag, Pt, or an alloy containing at least one of these as a main component.
  • the upper layer 61 is made of Au
  • at least the surface (strictly, the upper surface (+D3 side surface)) of the IC pad 35 is made of Au. Similar to the bonding, the bonding between the connection member and the IC pad 35 is also bonding between Au.
  • the IC pad 35 may be composed of one layer of metal, or may be composed of three or more layers of metal. In a mode composed of three or more layers of metal, the above description of the material of the IC terminal 21 may be applied to the material of the IC pad 35 .
  • the thickness of the IC pad 35 and its layers are arbitrary.
  • the thickness of the IC pad 35 may be thinner than, equal to, or thicker than the thickness of the IC terminal 21 .
  • the thickness of the IC pad 35 may be, for example, 1 ⁇ m or more and 10 ⁇ m or less.
  • Top layer 61 may be thinner than bottom layer 59, for example.
  • the thickness of the lower layer 59 may be, for example, 1 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the upper layer 61 may be, for example, 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the material of the conductor layer (the excitation electrode 15 and the extraction electrode 17) of the crystal element 3 is arbitrary.
  • the conductor layer of the crystal element 3 may be composed of one metal layer, or may be composed of two or more metal layers.
  • the conductor layer of the crystal element 3 is composed of two metal layers. Specifically, a base layer 63 and a main layer 65 made of different materials are laminated in order from the crystal blank 13 side. In addition, in FIG. 4, the side surface of each layer is exposed. Unlike the illustrated example, the side surface of the underlying layer 63 may be covered with the main layer 65 .
  • the material of the underlying layer 63 may be Ni, Cr, or an alloy containing at least one of these as a main component.
  • the material of the main layer 65 may be Au, Ag, or an alloy containing at least one of these as a main component.
  • the main layer 65 is made of Au
  • at least the surface (strictly, the upper surface (+D3 side surface of the excitation electrode 15 on the +D3 side and -D3 side surface of the -D3 side excitation electrode 15)) of the excitation electrode 15 is composed of Au.
  • the surface of the excitation electrode 15, the connection member (bonding wire 45) and the surface of the IC terminal 21 are made of the same metal (Au).
  • the thickness of the conductor layer (excitation electrode 15 and extraction electrode 17) of the crystal element 3 is arbitrary.
  • the thickness of the conductor layer may be 1000 ⁇ or more and 4000 ⁇ or less.
  • the main layer 65 may occupy most of the above thickness (eg, 80% or more or 90% or more).
  • the thickness of the underlying layer 63 may be, for example, 10 ⁇ or more and 100 ⁇ or less.
  • the manufacturing method of the oscillator 1 may be the same as various manufacturing methods except for the specific materials of the connection member (bonding wire 45) and the IC terminal 21, and may be, for example, a known manufacturing method. .
  • An example of a procedure relating to packaging among the procedures of the method for manufacturing the oscillator 1 will be described below.
  • FIG. 5 is a flow chart showing an example of the procedure of the method for manufacturing the oscillator 1.
  • step ST1 the IC 5 is mounted on the base 9 of the package 7. Specifically, for example, first, the IC 5 is adhered to the first surface 9 a (die pad 42 ) of the base 9 with the adhesive 43 . Next, a bonding wire 45 is formed to electrically connect the IC terminal 21 and the IC pad 35 .
  • Bonding of the bonding wire 45 to the IC terminal 21 and the IC pad 35 is performed by, for example, applying ultrasonic waves, pressure and heat to the bonding wire 45 (and the IC terminal 21 and the IC pad 35 as necessary). done by Since ultrasonic waves are applied, Au is joined at a temperature lower than its melting point.
  • the heating temperature is, for example, 100° C. or more and less than 200° C.
  • the heating method may be various methods, for example, it may be a known method. For example, heating may be done by raising the temperature of a heating table on which the package 7 rests. As the heating temperature, the temperature of the heating means (for example, a heating table) that heats the object to be heated may be referred to. However, for the sake of convenience, the temperature of the object to be heated and the heating temperature are sometimes expressed without distinction. The matter described in this paragraph may be applied not only to heating for bonding connecting members, but also to heating in other steps (eg, ST2, ST3, ST5 and ST8).
  • steps eg., ST2, ST3, ST5 and ST8.
  • step ST2 the crystal element 3 is mounted on the base 9 of the package 7. Specifically, for example, an uncured conductive adhesive 41 is supplied to the crystal pad 33 . Next, the crystal element 3 is placed on the conductive adhesive 41 . After that, the conductive adhesive 41 is cured by heat treatment.
  • the heating temperature at this time is, for example, 200° C. or higher and 400° C. or lower. From another point of view, the heating temperature here is, for example, higher than the heating temperature when bonding the connection member (bonding wire 45).
  • the heating time is, for example, 10 minutes or more and 1 hour or less.
  • the heating temperature for the embodiment in which the type of thermosetting resin of the conductive adhesive 41 is a silicone resin is higher than the heating temperature in the embodiment in which the type of the thermosetting resin for the conductive adhesive 41 is an epoxy resin.
  • the former is about 350°C and the latter is about 200°C.
  • step ST3 heat treatment (a heat treatment different from the heat treatment for curing the conductive adhesive 41 in step ST2) is performed.
  • this heat treatment for example, the residual stress of the conductive adhesive 41 is reduced (annealing treatment) and/or the conductive adhesive 41 is degassed.
  • the heating temperature at this time is, for example, 200° C. or higher and 400° C. or lower. From another point of view, the heating temperature here is, for example, higher than the heating temperature when bonding the connection member (bonding wire 45).
  • the heating time is, for example, 1 hour or more and 5 hours or less.
  • This heat treatment may be performed, for example, under a vacuum atmosphere.
  • step ST4 the frequency of the crystal element 3 is adjusted. Specifically, for example, the crystal element 3 is excited through the pads of the base portion 9 electrically connected to the crystal element 3 to measure the frequency characteristics of the crystal element 3, and depending on the measurement result, the excitation electrode 15 is measured. Increase and/or decrease mass.
  • step ST5 heat treatment is performed.
  • the description of step ST3 may be incorporated into this step.
  • step ST6 the frequency of the crystal element 3 is adjusted.
  • the description of step ST4 may be incorporated into this step.
  • step ST7 the long sides of the lid 11 are joined to the upper surface of the base 9 by seam welding.
  • step ST8 heat treatment is performed.
  • the description of step ST3 may generally be used for this step.
  • the heating time may be equal to or less than the heating time in step ST3, and is, for example, 10 minutes or more and 1 hour or less.
  • step ST9 the short sides of the lid 11 are joined to the upper surface of the base 9 by seam welding.
  • the concave portion of the base portion 9 is sealed to form a sealed space S1.
  • seam welding is performed in an appropriate atmosphere, so that the closed space S1 is in a vacuum state or in a state in which an appropriate gas (for example, nitrogen) is enclosed.
  • the crystal oscillator 1 As described above, the crystal oscillator 1 according to the first embodiment has the crystal element 3, the IC 5, the package 7, and the connecting members (bonding wires 45).
  • IC 5 has an IC terminal 21 .
  • a package 7 holds the crystal element 3 and the IC 5 .
  • the bonding wires 45 are made of gold (Au) and are joined to the IC terminals 21 and the package 7 .
  • the IC terminal 21 has a first Au layer (Au layer 57) that constitutes the surface of the IC terminal 21 and to which the bonding wire 45 is bonded.
  • the probability of voids and/or cracks occurring in the bonding wires 45 can be reduced, and the deterioration of the characteristics of the oscillator 1 can be reduced. Specifically, for example, it is as follows.
  • FIG. 6 is a diagram showing a bonding structure between bonding wires 45 and IC terminals (first layer 51) according to a comparative example, and corresponds to part of FIG.
  • the IC terminal is composed only of the first layer 51 of the embodiment.
  • the material of the first layer 51 is, for example, Al as described in the description of the embodiment.
  • a plurality of voids V1 and/or one or more cracks C1 may be formed in a portion of the bonding wire 45 near the IC terminal. rice field.
  • the diameter of the void V1 and the width of the crack C1 are, for example, 0.1 ⁇ m or more and 3 ⁇ m or less.
  • voids V1 and cracks C1 can be reduced.
  • the applicant has confirmed the above effects by taking cross-sectional photographs as shown in FIG. 6 for prototypes according to comparative examples and examples. More specifically, voids V1 and cracks C1 seen in Comparative Examples were not observed in Examples.
  • Relatively high heat may be applied to the bonding wires 45 and IC terminals during the manufacturing process of the oscillator, the process of incorporating the oscillator into the device (for example, the reflow process), and the process of using the device.
  • the bonding wire 45 is exposed to heat of 200° C. or higher or 300° C. or higher after bonding (step ST1) (step ST2, ST3, ST5 and ST8).
  • the bonding wire 45 (Au) and the IC terminal (Al) are mutually diffused by exposure to high heat as described above. That is, an alloy layer of Au and Al grows. At this time, multiple kinds of alloys grow. More specifically, for example, AuAl 2 (9 ppm/° C.), AuAl (12 ppm/° C.), Au 2 Al (13 ppm/° C.), Au 5 Al 2 (14 ppm/° C.) and Au 4 Al (12 ppm/° C.) is formed.
  • the numerical values shown in parentheses after the above compositional formulas are the linear expansion coefficients of the respective alloys. Various alloys have different coefficients of linear expansion. After the growth of the alloy layer, if the oscillator according to the comparative example is exposed to temperature cycles during its use, etc., a difference in thermal expansion occurs between the alloys having different coefficients of linear expansion, causing voids V1 and cracks C1.
  • the bonding between the bonding wire 45 and the IC terminal 21 is Au-to-Au bonding. Therefore, even if they are exposed to high heat, the growth of an alloy layer between them is reduced, and the growth of a plurality of alloy layers having different coefficients of linear expansion is also reduced. As a result, voids V1 and cracks C1 are less likely to occur even when the oscillator 1 is exposed to temperature cycles.
  • the IC terminal 21 may have the first layer 51 , the second layer 53 and the third layer 55 .
  • the first layer 51 may be made of aluminum or an alloy containing aluminum as a main component.
  • the second layer 53 may be made of nickel or a nickel-based alloy, and may overlap the first layer on the Au layer 57 side.
  • the third layer 55 may be composed of palladium or a palladium-based alloy, and may overlap the Au layer 57 side with respect to the second layer.
  • Au layer 57 may overlay the third layer.
  • the package 7 may have a base 9 and a lid 11 .
  • the base 9 may have a first surface 9a.
  • the lid 11 may be fixed to the base 9 such that the closed space S1 is formed on the first surface 9a.
  • the IC 5 may be fixed to the first surface 9a and accommodated in the sealed space S1.
  • the crystal element 3 may be accommodated in the sealed space S1 at a position facing the first surface 9a via the IC 5, and is bonded to the base 9 with a conductive adhesive 41 made of a resin in which conductive filler is dispersed. It can be.
  • the effect of reducing the occurrence of voids V1 and cracks C1 described above is particularly effective.
  • the reason is as follows.
  • the IC 5 it is necessary to mount the IC 5 on the base portion 9 before bonding the crystal element 3 to the base portion 9 with the conductive adhesive 41 .
  • the bonding wires 45 and the IC terminals 21 are exposed to heat for annealing and/or degassing the conductive adhesive 41 . Therefore, in the case where the aforementioned comparative example has the structure as described above, various alloy layers tend to grow between the bonding wire 45 and the IC terminal (the first layer 51), which in turn causes voids.
  • the probability of occurrence of V1 and crack C1 is particularly high. However, in this embodiment, such inconvenience is reduced.
  • the crystal element 3 may have a crystal blank 13 and an excitation electrode 15 overlapping the crystal blank 13 .
  • the thickness of the portion of the crystal blank 13 where the excitation electrode 15 overlaps may be 5 ⁇ m or more and 30 ⁇ m or less.
  • the effect of reducing the occurrence of voids V1 and cracks C1 described above is particularly effective.
  • it is as follows.
  • the adhesion amount of the gas generated from the conductive adhesive 41 and adhering to the crystal element 3 increases the mass and/or volume of the excitation region of the crystal element 3. increases relative to As a result, the effect of gas adhesion on the characteristics of the crystal element 3 increases. Therefore, heating for degassing the conductive adhesive 41 is carefully performed. As a result, the probability of voids V1 and cracks C1 occurring in the bonding wires 45 is particularly high. However, in this embodiment, such inconvenience is reduced.
  • the package 7 may have pads (IC pads 35) to which connection members (bonding wires 45) are bonded.
  • the IC pad 35 may have a second Au layer (upper layer 61).
  • the upper layer 61 constitutes the surface of the IC pad 35 and may be bonded with the bonding wire 45 .
  • bonding wires 45 are Au-to-Au bonding not only to IC terminals 21 but also to IC pads 35 . Therefore, as with the IC terminal 21 side, the probability of voids V1 and cracks C1 occurring in the bonding wires 45 is reduced.
  • the crystal element 3 and IC 5 may be accommodated in the same closed space S1.
  • the excitation electrode 15 of the crystal element 3 may have a third Au layer (main layer 65 ) forming the surface of the excitation electrode 15 .
  • connection member bonding wire 45
  • surface of the IC terminal 21 the surface of the excitation electrode 15 are all made of Au.
  • the effects (dissolution and/or reduction, etc.) of any material present in the package 7 during the manufacturing process or after completion on the Au are likely to be distributed to these members.
  • the change in the characteristics of the oscillator 1 as a whole is suppressed compared to the case where the substance affects only one member, and thus the change in the characteristics of the one member becomes large.
  • the method of manufacturing the crystal oscillator 1 according to the first embodiment manufactures the oscillator 1 configured such that the connecting member (bonding wire 45) made of Au and the Au layer 57 of the IC terminal 21 are bonded as described above. . Therefore, the various effects described above are achieved.
  • the manufacturing method of the oscillator 1 includes a bonding step (see step ST1) and one or more heating steps (see steps ST2, ST3, ST5 and ST8).
  • the bonding step the connection member (bonding wire 45 ) is bonded to the first Au layer (Au layer 57 ) and the base 9 of the package 7 .
  • the heating step after the bonding step, the bonding wires 45 are exposed to a temperature higher than the temperature of the bonding wires 45 during the bonding step (which may be the temperature of the heating means for heating the bonding wires 45 as described above). .
  • the bonding wire 45 is exposed to a temperature higher than the temperature at the time of bonding after bonding, so voids V1 and cracks C1 are likely to occur due to the growth of the alloy layer as described above. In other words, the effect of reducing the occurrence of voids V1 and cracks C1 is effectively exhibited by the bonding between Au layers in this embodiment.
  • the temperature of the bonding wires 45 does not necessarily have to reach the temperature of the heating means used in the heating step.
  • FIG. 7 is a cross-sectional view showing the configuration of a crystal oscillator 201 according to the second embodiment.
  • the connecting member for electrically connecting the IC 5 and the package 7 was the bonding wire 45 .
  • the connection member is the bump 245 . Specifically, for example, it is as follows.
  • the oscillator 201 has a crystal element 3, an IC 5, and a package 207, like the oscillator 1 of the first embodiment.
  • the package 207 has a base 209 and a lid 11 that closes the recess of the base 209, like the package 7 of the first embodiment.
  • the crystal element 3 and IC 5 are accommodated in the recess.
  • the IC 5 faces the first surface 209a of the base portion 209 (the bottom surface of the recess in the illustrated example), and the crystal element 3 faces the first surface 9a through the IC 5. facing each other.
  • the specific shape of the base 209 differs from that of the first embodiment due to the difference in the mounting structure of the IC5.
  • the base 9 of the first embodiment has three recesses
  • the base 209 has two recesses, a first recess 225 and a second recess 227 opening at the bottom surface of the first recess 225.
  • the insulating substrate 223 of the base 209 is drawn as a laminate of three insulating layers (first insulating layer 31E, second insulating layer 31F and third insulating layer 31G).
  • the first concave portion 225 corresponds to the first concave portion 25 of the first embodiment. That is, the first concave portion 225 contributes to accommodation of the crystal element 3 .
  • the crystal element 3 is mounted on the bottom surface of the first concave portion 225 as in the first embodiment.
  • the second recessed portion 227 corresponds to the second recessed portion 27 and the third recessed portion 29 of the first embodiment. That is, the second concave portion 227 contributes to accommodation of the IC 5 and the connection member (bump 245).
  • the IC 5 is surface-mounted on the bottom surface of the second recess 227 (from another point of view, the bottom surface of the recess of the base 209) as the first surface 209a.
  • the base 209 has the IC pad 35 on the bottom surface of the second recess 227 .
  • the IC 5 is arranged so that the IC terminal 21 faces the IC pad 35 .
  • the IC 5 is fixed and electrically connected to the package 7 by bonding the IC pads 35 and the IC terminals 21 with the bumps 245 interposed therebetween.
  • the IC pads 35 are basically the same as the IC pads 35 of the first embodiment, except that they are provided on the first surface 209a and face the IC terminals 21 .
  • the number, planar shape and dimensions of the IC pads 35 are arbitrary, as in the first embodiment.
  • the IC pad 35 may be wider than the IC terminal 21 (the example shown in the figure), may be of the same width, or may be narrower than the IC terminal 21 when viewed through the plane.
  • the IC terminal 21 is as described in the first embodiment. However, the details may differ from the first embodiment due to the difference in connection members (bonding wires 45 and bumps 245).
  • the IC terminals 21 (as well as the bumps 245 and IC pads 35) serve to support the IC5. Therefore, the plurality of IC terminals 21 may be arranged symmetrically in each of the D1 direction and the D2 direction so as to support the IC 5 in a well-balanced manner.
  • the shape and dimensions of the bump 245 are arbitrary.
  • the side surface of the bump 245 may bulge outward (the example shown), may be recessed inward, or may have a shape that cannot be said to be either of the former.
  • Either the area where the bump 245 and the IC terminal 21 are bonded or the area where the bump 245 and the IC pad 35 are bonded may be larger.
  • An example of the diameter (for example, maximum diameter) of the bump 245 is 90 ⁇ m or more and 120 ⁇ m or less.
  • the IC 5 may be covered with a sealing resin 49 (see FIG. 11, in other words, an underfill) at least partly (for example, the surface where the IC terminals 21 are located). good.
  • a sealing resin 49 see FIG. 11, in other words, an underfill
  • FIG. 8 is an enlarged view of region VIII in FIG.
  • the bumps 245 are made of Au, like the bonding wires 45 . Therefore, in this embodiment as well, the bonding between the connection member (bump 245) and the IC terminal 21 (at least the surface of which is made of Au) is Au-to-Au bonding. Also, similarly to the first embodiment, bonding between the bumps 245 and the IC pads 35 may be performed by bonding between Au.
  • connection member is made of gold (Au)
  • the IC terminal 21 has the first Au layer (Au layer 57), as in the first embodiment.
  • the Au layer 57 constitutes the surface of the IC terminal 21, and the bump 245 is bonded thereto. Therefore, the same effects as those of the first embodiment can be obtained. Specifically, it is as follows.
  • FIG. 9 is a diagram showing a bonding structure between the bump 245 and the IC terminal (first layer 51) according to the comparative example, and corresponds to FIG.
  • the IC terminal is composed only of the first layer 51 of the embodiment, similar to the comparative example in FIG.
  • voids V1 and cracks C1 are generated in portions of the bumps 245 near the IC terminals by the same principle as the voids V1 and cracks C1 in the portions of the bonding wires 45 near the IC terminals in the comparative example of FIG.
  • a crack C1 occurs.
  • the probability of occurrence of voids V1 and cracks C1 is reduced by the same principle as in the oscillator 1 of the first embodiment.
  • FIG. 10 is a cross-sectional view showing the configuration of a crystal oscillator 301 according to the third embodiment.
  • the crystal element 3 is mounted on the package 67 in this embodiment.
  • Package 67 is mounted on package 307 .
  • the package 307 corresponds to the packages 7 and 207 of the first and second embodiments.
  • the package 307 is a package to which connection members (bumps 245 in the illustrated example) that are bonded to the IC 5 are bonded.
  • the crystal element 3 may be indirectly held by the package 307 rather than directly by the package 7 or 207 to which the connection member (bonding wire 45 or bump 245) is bonded.
  • Various modes of indirectly holding the crystal element 3 in the package 307 are possible. In the illustrated example:
  • the package 307 has a base 309 and a lid 11 as in other embodiments.
  • the insulating substrate 323 of the base portion 309 has a first recess 325 and a second recess 327 opening at the bottom surface of the first recess 325 .
  • the first concave portion 325 contributes to housing the IC5.
  • An IC pad 35 (not shown here, see FIG. 8) is provided on the bottom surface of the first recess 325 (around the opening of the second recess 327).
  • the IC 5 is provided with an IC terminal 21 (not shown here, see FIG. 8) on the surface on the -D3 side.
  • the IC 5 is mounted on the package 307 by bonding the IC terminals 21 and the IC pads 35 with the bumps 245 .
  • FIG. 8 may be taken as a cross-sectional view of the bump 245 and its surroundings in this embodiment.
  • the second recess 327 contributes to housing the package 67.
  • a pad (not shown) is formed on the bottom surface of the second recess 327 .
  • the package 67 also has terminals (not shown) on its lower surface.
  • the package 67 is mounted on the package 307 (base portion 309) by bonding the pads and terminals with the bumps 69. As shown in FIG. That is, the package 67 is fixed and electrically connected to the package 307 .
  • a combination of the crystal element 3 and the package 67 may be regarded as a crystal oscillator 68 .
  • the crystal oscillator 68 may be a general-purpose one that is not assumed to be mounted in the package 307 . From another point of view, the crystal oscillator 68 may be distributed alone. However, the crystal oscillator 68 may be one that is assumed to be mounted in the package 307 . In the illustrated example, the crystal oscillator 68 has only the crystal element 3 as an electronic element. However, the crystal oscillator 68 may have other electronic elements such as a temperature sensor.
  • the configuration of the package 67 is arbitrary.
  • the package 67 has a base portion having a recess and a lid that closes (seales) the recess, although no particular reference numerals are attached.
  • a crystal pad 33 (not shown here) is provided on the bottom surface of the recess. Then, the crystal element 3 is mounted in the package 67 by, for example, bonding the lead-out electrodes 17 (not shown here) and the crystal pads 33 with the conductive adhesive 41 in the same manner as in the first embodiment. be.
  • the package 67 may have a plate-like base (substrate) on which the crystal element 3 is mounted, and a cap-like lid that covers the base from above the crystal element 3 .
  • the package 67 may have two or more recesses like the package 307, or may be H-shaped like the package 407 (FIG. 11) described later.
  • the description of the package 7 may be appropriately applied to the package 67, except that the IC5 is not mounted inside the package 67.
  • the base may have a base made of an insulating material such as ceramic, and a conductive layer and through conductors provided on the base.
  • the lid may be a metal plate that is secured to the base by seam welding or the like.
  • the configuration of pads, bumps 69 and terminals for mounting the package 67 on the package 307 is arbitrary.
  • the description of the IC pads 35 , bumps 245 and IC terminals 21 may be incorporated into the pads, bumps 69 and terminals associated with mounting the package 67 .
  • the bonding between the pads and the bumps 69 and/or the bonding between the bumps 69 and the terminals may be Au-to-Au bonding.
  • the IC 5 may be covered with a sealing resin 49 (see FIG. 11, in other words, an underfill) at least partly (for example, the surface where the IC terminals 21 are located). good.
  • a sealing resin 49 see FIG. 11, in other words, an underfill
  • the crystal element 3 is positioned below the IC 5 (on the -D3 side).
  • the positional relationship between the IC 5 and the crystal element 3 is not limited to the configuration in which the crystal element 3 cannot be mounted unless the IC 5 is mounted.
  • the IC 5 may be positioned below the crystal element 3 as in the first or second embodiment.
  • the bump 245 is taken as an example of the connection member.
  • the bonding wire 45 may be used as the connecting member as in the first embodiment.
  • the IC 5 may be arranged so that the IC terminal 21 faces the +D3 side and fixed to the bottom surface of the first recess 325 .
  • the IC pads 35 may be provided on the bottom surface of the first recess 325 or on the top surface of a pedestal provided on the bottom surface.
  • a bonding wire 45 may be bonded to the IC terminal 21 and the IC pad 35 .
  • the connecting members are made of gold (Au)
  • the IC terminals 21 are made of the first Au layer (Au layer 57), as in the first and second embodiments. have.
  • the Au layer 57 constitutes the surface of the IC terminal 21, and the bump 245 is bonded thereto. Therefore, the same effects as those of the first and second embodiments can be obtained. For example, the probability of occurrence of voids V1 and cracks C1 is reduced.
  • the crystal element 3 is housed in the package 67 .
  • the process of heating the conductive adhesive 41 is performed before the crystal oscillator 68 and the IC 5 are mounted on the package 307 .
  • the probability and/or frequency that the connection member (bump 245) is exposed to high temperatures is reduced.
  • the same inconvenience as the inconvenience described with reference to FIG. is reduced.
  • FIG. 11 is a cross-sectional view showing the configuration of a crystal oscillator 401 according to the fourth embodiment.
  • the package 407 of the oscillator 401 is a so-called H-shaped one that exhibits an H shape in cross section. That is, the base 409 of the package 407 has a first recess 425 and a second recess 427 that opens on the side opposite to the first recess 425 .
  • the crystal element 3 is housed in the first concave portion 425 .
  • IC5 is housed in the second recess 427 .
  • the first recess 425 is sealed with the lid 11 .
  • the crystal element 3 does not have to be arranged in the same space (recess) as the IC 5 .
  • the base portion 409 has a base 423 made of an insulating material, and a conductor layer and through conductors provided on the base 423 .
  • the base 423 is integrally formed as a whole. As described in the description of the substrate 23 in the first embodiment, such a substrate 423 may be produced by stacking insulating layers, or may be produced by another method. Lid 11 may be a metal plate secured to base 409 by seam welding or the like, as in other embodiments.
  • the first recess 425 contributes to housing the crystal element 3 .
  • a crystal pad 33 (not shown here) is provided on the bottom surface of the first recess 425 . Then, the crystal element 3 is mounted in the package 407 by, for example, bonding the extraction electrodes 17 (not shown here) and the crystal pads 33 with the conductive adhesive 41 in the same manner as in the first embodiment. be.
  • the second recess 427 contributes to housing the IC5.
  • An IC pad 35 (not shown here, see FIG. 8) is provided on the bottom surface of the second recess 427 .
  • the IC 5 is provided with an IC terminal 21 (not shown here, see FIG. 8) on the +D3 side surface.
  • the IC 5 is mounted on the package 407 by bonding the IC terminals 21 and the IC pads 35 with the bumps 245 .
  • FIG. 8 can be regarded as a cross-sectional view of the bump 245 and its surroundings in this embodiment, with the sign of the D3 direction reversed.
  • the IC 5 is entirely covered with a sealing resin 49 .
  • the sealing resin 49 may be provided so that the ⁇ D3 side surface is located at any position in the range from the +D3 side surface of the IC 5 to the ⁇ D3 side surface. Also, the sealing resin 49 may not be provided.
  • the sealing resin 49 may be made of, for example, a thermosetting resin that hardens when heated.
  • thermosetting resins include silicone resins and epoxy resins.
  • the sealing resin 49 may be the same as or different from the resin forming the conductive adhesive 41 and/or the resin forming the adhesive 43 .
  • the bump 245 is taken as an example of the connection member.
  • the bonding wire 45 may be used as the connection member.
  • the IC 5 may be arranged so that the IC terminal 21 faces the ⁇ D 3 side and fixed to the bottom surface of the second recess 427 .
  • the IC pads 35 may be provided on the bottom surface of the second recess 427 or on the top surface (surface on the -D3 side) of the pedestal provided on the bottom surface. Then, the IC terminal 21 and the IC pad 35 may be bonded by the bonding wire 45 .
  • the H-shaped package has a container-shaped package similar to the package 67 shown in the third embodiment, and a circuit board bonded to the lower surface (the outer surface on the ⁇ D3 side) of the container-shaped package. you can By forming the opening in the circuit board, an H shape in a cross-sectional view may be obtained.
  • the IC 5 may be mounted on the bottom surface of the container-type package and housed in the opening.
  • the connection member (bump 245) is made of gold (Au)
  • the IC terminal 21 is made of the first Au layer (Au layer 57).
  • the Au layer 57 constitutes the surface of the IC terminal 21, and the bump 245 is bonded thereto. Therefore, the same effects as those of the first to third embodiments can be obtained. For example, the probability of occurrence of voids V1 and cracks C1 is reduced.
  • the crystal element 3 can be mounted on the package 407 before the IC 5 is mounted.
  • the process of heating the conductive adhesive 41 is performed before the IC 5 is mounted on the package 407 .
  • the probability and/or frequency that the connection member (bump 245) is exposed to high temperatures is reduced.
  • the same inconvenience as the inconvenience described with reference to FIG. is reduced.
  • the oscillator 1 may further include an insulating resin (sealing resin 49) covering at least the surface of the IC 5 where the IC terminal 21 is located (the surface on the +D3 side in this embodiment).
  • an insulating resin covering at least the surface of the IC 5 where the IC terminal 21 is located (the surface on the +D3 side in this embodiment).
  • the sealing resin 49 contributes to reducing the probability that the plurality of IC terminals 21 are short-circuited with each other and that foreign matter enters between the IC 5 and the package 7 .
  • the sealing resin 49 when the sealing resin 49 is provided, stress is applied to the IC terminals 21 due to shrinkage during curing. As a result, the void V1 or crack C1 in the bonding wire 45 may expand.
  • the probability of voids V1 and cracks C1 being generated is reduced, so naturally the probability of expansion of voids V1 and cracks C1 is also reduced. As a result, the probability that the characteristics of the oscillator 1 will deteriorate is reduced.
  • FIG. 12 is a diagram showing temporal changes in the characteristics of the oscillator according to the comparative example.
  • the horizontal axis indicates the elapsed time (unit: hours), and is on a logarithmic scale.
  • the vertical axis indicates the ratio DF/D (ppm) of the change amount DF of the frequency F with elapsed time to the initial value F of the frequency of the oscillation signal output by the oscillator.
  • a plurality of lines in the figure indicate changes over time in DF/D of a plurality of prototypes.
  • the configuration of the comparative example has been described with reference to FIG. That is, in the oscillator 1 according to the first embodiment, the IC terminals are configured only by the first layer 51 (specifically, Al).
  • a prototype according to this comparative example was produced under the same conditions as those of the manufacturing method described with reference to FIG. 5, and then exposed to an environment of 125.degree.
  • FIG. 12 shows the change over time of DF/D under the 125° C. environment.
  • the absolute value of DF/D after 1000 hours is 3 ppm or more.
  • the absolute value of DF/D after 1000 hours has passed is 10 ppm or less, and the oscillator according to the comparative example has the ability to maintain characteristics required for general oscillators.
  • FIG. 13 is a diagram showing temporal changes in the characteristics of the oscillator according to the example.
  • FIG. 12 This figure is similar to FIG. However, unlike FIG. 12, the horizontal axis does not have a logarithmic scale. Similar to the comparative example, the example also shows changes over time in DF/D of a plurality of prototypes.
  • the configuration of the oscillator according to the example is the same as the configuration of the oscillator 1 of the first embodiment.
  • the IC terminal in the comparative example is replaced with an IC terminal composed of four layers (specifically, Al/Ni/Pd/Au).
  • Other conditions are the same between the example and the comparative example.
  • the absolute value of DF/D after 1000 hours is 3 ppm or less (more specifically, less than 2 ppm). That is, the DF/D after 1000 hours in the example is smaller than the DF/D after 1000 hours in the example. As a result, it was confirmed that the ability to maintain characteristics of the examples was higher than the ability to maintain characteristics of the comparative examples.
  • the bonding wires 45 and the bumps 245 are examples of connection members.
  • the IC terminal 21 is an example of a terminal that the IC has.
  • the Au layer 57 of the IC terminal 21 is an example of the first Au layer.
  • the sealing resin 49 is an example of an insulating resin that covers the surface of the IC where the terminals are located.
  • the IC pad 35 is an example of a pad to which a connection member is bonded.
  • the upper layer 61 of the IC pad 35 is an example of the second Au layer.
  • the main layer 65 of the excitation electrode 15 is an example of the third Au layer.
  • Step ST1 is an example of a joining step.
  • Each of steps ST2, ST3, ST5 and ST8 is an example of a heating step.
  • the oscillator may be a clock oscillator, a voltage controlled oscillator (abbreviation: VCXO), a temperature compensated oscillator (abbreviation: TCXO), or a It may be an oscillator in a constant temperature oven of an oscillator (abbreviation: OCXO).
  • VCXO voltage controlled oscillator
  • TCXO temperature compensated oscillator
  • OCXO constant temperature oven of an oscillator
  • the number and arrangement of external terminals, IC pads, and IC terminals may be appropriately set according to the functions required of these oscillators.
  • the oscillator had only a crystal element and an IC as electronic elements.
  • the oscillator may have other elements.
  • a temperature sensor may be provided separately from the IC.
  • a piezoelectric device a piezoelectric oscillator, or a crystal device, which are higher concepts than crystal oscillators.
  • a piezoelectric element containing a piezoelectric material other than crystal may be used in place of the crystal element.
  • the piezoelectric and crystal devices need not be oscillators.
  • piezoelectric devices and crystal devices may be vibrators with temperature sensors instead of ICs.
  • connection member wire bonding or bump
  • IC terminal whose surface at least is made of Au.
  • the surfaces of the connecting members and the IC terminals may be made of a material other than Au (for example, Al or Cu).

Abstract

This crystal oscillator comprises a crystal element, an IC, a package and a connection member. The IC has a terminal. The package holds the crystal element and the IC. The connection member is composed of gold (Au), and is a bump or bonding wire bonded to the terminal and package. The terminal has an Au layer which constitutes the surface of the terminal and to which the connection member is bonded.

Description

水晶発振器及びその製造方法Crystal oscillator and its manufacturing method
　本開示は、水晶発振器及びその製造方法に関する。 The present disclosure relates to crystal oscillators and manufacturing methods thereof.
　水晶素子と、ＩＣ（Integrated Circuit）と、これらを保持しているパッケージとを有する水晶発振器が知られている（例えば下記特許文献１）。水晶素子は、例えば、水晶ブランクと、水晶ブランクに重なっている励振電極とを有している。ＩＣは、例えば、発振回路を含んでおり、パッケージを介して励振電極と電気的に接続されている。発振回路は、励振電極に交流電圧を印加することによって水晶ブランクを振動させ、この振動を利用して発振信号を生成する。特許文献１では、ＩＣは、半田からなるバンプによってパッケージに実装されている。 A crystal oscillator having a crystal element, an IC (Integrated Circuit), and a package holding them is known (for example, Patent Document 1 below). The crystal element has, for example, a crystal blank and excitation electrodes that overlap the crystal blank. The IC includes, for example, an oscillator circuit and is electrically connected to excitation electrodes via a package. The oscillating circuit vibrates the crystal blank by applying an alternating voltage to the excitation electrodes, and uses this vibration to generate an oscillating signal. In Patent Document 1, an IC is mounted on a package by bumps made of solder.
特開２０１７－１１８３９３号公報JP 2017-118393 A
　本開示の一態様に係る水晶発振器は、水晶素子と、ＩＣと、パッケージと、接続部材と、第１Ａｕ層と、を有している。前記ＩＣは、端子を有している。前記パッケージは、前記水晶素子及び前記ＩＣを保持している。前記接続部材は、金からなり、前記端子と前記パッケージとに接合されている、バンプ又はボンディングワイヤである。前記端子は、当該端子の表面を構成しており、前記接続部材が接合されている、第１Ａｕ層を有している。 A crystal oscillator according to one aspect of the present disclosure includes a crystal element, an IC, a package, a connecting member, and a first Au layer. The IC has terminals. The package holds the crystal element and the IC. The connecting members are bumps or bonding wires made of gold and bonded to the terminals and the package. The terminal has a first Au layer forming a surface of the terminal and to which the connection member is bonded.
第１実施形態に係る水晶発振器の概略構成を示す分解斜視図。1 is an exploded perspective view showing a schematic configuration of a crystal oscillator according to a first embodiment; FIG. 図１のII－II線における水晶発振器の断面図。FIG. 2 is a cross-sectional view of the crystal oscillator taken along line II-II of FIG. 1; 図１の水晶発振器の内部を示す平面図。FIG. 2 is a plan view showing the inside of the crystal oscillator of FIG. 1; 図２の領域IVを拡大して示す断面図。Sectional drawing which expands and shows the area|region IV of FIG. 図１の水晶発振器の製造方法の手順の一例を示すフローチャート。2 is a flow chart showing an example of the procedure of a method for manufacturing the crystal oscillator of FIG. 1; 比較例の構成を示す図４の一部に相当する断面図。Sectional drawing corresponding to a part of FIG. 4 which shows the structure of a comparative example. 第２実施形態に係る水晶発振器の概略構成を示す断面図。FIG. 5 is a cross-sectional view showing a schematic configuration of a crystal oscillator according to a second embodiment; 図７の領域VIIIの拡大図。FIG. 8 is an enlarged view of region VIII of FIG. 7; 比較例の構成を示す図８に相当する断面図。FIG. 9 is a cross-sectional view corresponding to FIG. 8 showing the configuration of a comparative example; 第３実施形態に係る水晶発振器の概略構成を示す断面図。FIG. 5 is a cross-sectional view showing a schematic configuration of a crystal oscillator according to a third embodiment; 第４実施形態に係る水晶発振器の概略構成を示す断面図。FIG. 5 is a cross-sectional view showing a schematic configuration of a crystal oscillator according to a fourth embodiment; 比較例に係る発振器の特性の経時変化を示す図。FIG. 5 is a diagram showing temporal changes in the characteristics of an oscillator according to a comparative example; 実施例に係る発振器の特性の経時変化を示す図。FIG. 4 is a diagram showing temporal changes in the characteristics of the oscillator according to the example;
　以下、本開示に係る実施形態について、図面を参照して説明する。なお、以下の説明で用いられる図は模式的なものである。従って、例えば、図面上の寸法比率等は現実のものとは必ずしも一致していない。図面同士で寸法比率等が一致していないこともある。また、一部の形状等が誇張されたり、細部が省略されたりすることがある。 Hereinafter, embodiments according to the present disclosure will be described with reference to the drawings. Note that the diagrams used in the following description are schematic. Therefore, for example, the dimensional ratios and the like on the drawings do not necessarily match the actual ones. Dimensional ratios and the like may not match between the drawings. In addition, some shapes and the like may be exaggerated, and details may be omitted.
　図面には、図面相互の関係を明確にする等の目的で、便宜的に直交座標系Ｄ１－Ｄ２－Ｄ３を付すことがある。本実施形態の水晶発振器は、いずれの方向が上方又は下方とされてもよいが、以下では、便宜的に、＋Ｄ３側を上方として、上面又は下面等の語を用いることがある。 For the purpose of clarifying the relationship between the drawings, etc., the drawings may be labeled with an orthogonal coordinate system D1-D2-D3 for convenience. In the crystal oscillator of this embodiment, any direction may be the upper side or the lower side, but for the sake of convenience, the +D3 side may be referred to as the upper side, and terms such as the upper surface and the lower surface may be used hereinafter.
　同一又は類似する構成について、「第１絶縁層３１Ａ」、「第２絶縁層３１Ｂ」のように番号及び付加符号で区別することがあり、また、単に、「絶縁層３１」のように、番号及び付加符号を省略して、これらを区別しないことがある。 The same or similar configurations may be distinguished by numbers and additional symbols such as "first insulating layer 31A" and "second insulating layer 31B", and simply "insulating layer 31" may be indicated by a number and additional signs may be omitted to distinguish between them.
　実施形態の説明において、例えば、「矩形」は、特に断りがない限り、角部が面取りされた形状を含んでよい。他の多角形についても同様である。また、多角形以外の形状についても、厳密に数学で定義されるような形状である必要はない。もちろん、各種の形状は、厳密に数学で定義されるような形状とされても構わない。 In the description of the embodiments, for example, "rectangle" may include a shape with chamfered corners unless otherwise specified. The same is true for other polygons. Also, shapes other than polygons do not have to be shapes that are strictly defined by mathematics. Of course, the various shapes may be strictly mathematically defined shapes.
　実施形態の説明において、「主成分」は、例えば、材料の５０質量％以上を占める成分とされてよい。２種以上の成分が主成分の場合は、その２種以上の成分の合計が５０質量％以上である。なお、後述する種々の主成分の質量％は、実施に際して、例えば、８０質量％以上又は９０質量％以上とされてもよい。 In the description of the embodiments, the "main component" may be, for example, a component that accounts for 50% by mass or more of the material. When two or more components are the main components, the total of the two or more components is 50% by mass or more. It should be noted that the mass % of various main components to be described later may be, for example, 80 mass % or more or 90 mass % or more upon implementation.
　部材が「金」（又はＡｕ）からなるという場合、上記部材は、Ａｕの質量％が９９．９％以上の金属とされてよい。すなわち、上記部材は、０．１質量％未満の不純物を含んでよい。不純物は、不可避に混入するもの（意図されていないもの）であってもよいし、意図的に添加されるものであってもよい。意図的に添加される不純物としては、例えば、結晶状態を調整するものが挙げられる。なお、後述するＡｕからなる種々の部材におけるＡｕの質量％は、実施に際して、９９．９９％以上若しくはそれ以上とされてもよい。 When the member is made of "gold" (or Au), the member may be made of metal containing 99.9% or more by mass of Au. That is, the member may contain less than 0.1% by mass of impurities. Impurities may be unavoidably mixed (unintended) or intentionally added. Impurities that are intentionally added include, for example, those that adjust the crystalline state. In addition, the mass % of Au in various members made of Au, which will be described later, may be 99.99% or more or more in practice.
　完成された発振器（デバイス）における金属は、導電ペーストの焼成によって形成されたものであってよい。従って、以下の説明で単に金属として言及される材料であっても、導電ペーストに含まれていた無機材料を含んでいてもよい。 The metal in the completed oscillator (device) may be formed by firing a conductive paste. Therefore, even materials referred to simply as metals in the following description may include inorganic materials contained in the conductive paste.
　第１実施形態の説明の後、他の実施形態（又は変形例等）の説明においては、基本的に先に説明された実施形態（又は変形例等）との相違点について述べる。特に言及がない事項については、先に説明された実施形態等と同様とされたり、先に説明された実施形態等から類推されたりしてよい。 After the description of the first embodiment, in the description of other embodiments (or modifications, etc.), differences from the previously described embodiments (or modifications, etc.) will be basically described. Matters not particularly mentioned may be the same as those of the previously described embodiments, etc., or may be inferred from the previously described embodiments, etc.
＜第１実施形態＞
　図１は、第１実施形態に係る水晶発振器１（以下、「水晶」は省略することがある。）の概略構成を示す分解斜視図である。図２は、図１のII－II線における断面図である。図３は、発振器１の内部を示す平面図である。なお、図２では、便宜上、厳密には同一断面に位置していない部材同士も共に示されている。 <First embodiment>
FIG. 1 is an exploded perspective view showing a schematic configuration of a crystal oscillator 1 (hereinafter, "crystal" may be omitted) according to the first embodiment. FIG. 2 is a cross-sectional view taken along line II--II of FIG. FIG. 3 is a plan view showing the inside of the oscillator 1. FIG. In addition, in FIG. 2, for the sake of convenience, strictly speaking, members that are not located on the same cross section are also shown together.
　発振器１は、例えば、全体として、概略、薄型の直方体状とされる電子部品である。発振器１の寸法は任意である。例えば、長辺及び短辺の長さは、１ｍｍ以上１０ｍｍ以下である。厚さは、短辺の長さよりも小さいことを前提として、０．２ｍｍ以上２ｍｍ以下である。 The oscillator 1 is, for example, an electronic component that generally has a thin rectangular parallelepiped shape as a whole. The dimensions of oscillator 1 are arbitrary. For example, the length of the long side and short side is 1 mm or more and 10 mm or less. The thickness is 0.2 mm or more and 2 mm or less on the premise that it is smaller than the length of the short side.
　発振器１は、例えば、所定の電圧の直流電力が供給されることによって発振信号を生成する。発振信号は、一定の周期で信号レベル（例えば電位）が振動する信号である。発振器１が生成する発振信号の周波数は任意である。例えば、実施形態に適用される水晶素子（後述）の態様（形状及び振動モード等）が種々のものであり得ると仮定した場合において、発振信号の周波数は、１ｋＨｚ以上１ＧＨｚ以下とされてよい。 The oscillator 1 generates an oscillation signal, for example, by being supplied with DC power of a predetermined voltage. An oscillating signal is a signal whose signal level (for example, potential) oscillates at a constant period. The frequency of the oscillation signal generated by the oscillator 1 is arbitrary. For example, when it is assumed that the crystal element (described later) applied to the embodiment may have various aspects (shape, vibration mode, etc.), the frequency of the oscillation signal may be 1 kHz or more and 1 GHz or less.
　発振器１は、例えば、図１において特に示されているように、水晶素子３と、ＩＣ５と、これらの素子を保持（例えば収容）するパッケージ７とを有している。パッケージ７は、基部９及び蓋１１を有している。なお、図３では、蓋１１が省略されることによって、発振器１の内部が示されている。 The oscillator 1 has, for example, a crystal element 3, an IC 5, and a package 7 that holds (for example, accommodates) these elements, as particularly shown in FIG. Package 7 has a base 9 and a lid 11 . Note that FIG. 3 shows the inside of the oscillator 1 by omitting the lid 11 .
　水晶素子３は、交流電圧が印加されると固有振動を生じる。ＩＣ５は、不図示の発振回路を含んで構成されている。当該発振回路は、水晶素子３に電圧を印加して、水晶素子３内の固有振動を利用して発振信号を生成する。パッケージ７は、水晶素子３及びＩＣ５の保護、及びこれらの素子に対する電気信号の伝達等に寄与する。 The crystal element 3 generates natural vibration when an AC voltage is applied. The IC5 includes an oscillation circuit (not shown). The oscillation circuit applies a voltage to the crystal element 3 and utilizes the natural oscillation in the crystal element 3 to generate an oscillation signal. The package 7 contributes to protection of the crystal element 3 and the IC 5, transmission of electrical signals to these elements, and the like.
　パッケージ７の基部９は、例えば、水晶素子３及びＩＣ５が実装される。すなわち、水晶素子３及びＩＣ５は、基部９に固定されるとともに電気的に接続される。パッケージ７の蓋１１は、水晶素子３及びＩＣ５が収容される密閉空間Ｓ１が構成されるように基部９に固定される。密閉空間Ｓ１は、例えば、真空状態とされ、又は、適宜なガス（例えば窒素）が封入されている。 The crystal element 3 and the IC 5 are mounted on the base 9 of the package 7, for example. That is, the crystal element 3 and the IC 5 are fixed to the base 9 and electrically connected. A lid 11 of the package 7 is fixed to the base 9 so as to form a closed space S1 in which the crystal element 3 and the IC 5 are accommodated. The closed space S1 is, for example, evacuated or filled with an appropriate gas (eg, nitrogen).
　水晶素子３は、２つの導電性接着剤４１（図２及び図３）によって基部９に対して固定されるとともに電気的に接続されている。ＩＣ５は、接着剤４３（図２）によって基部９に対して固定されているとともに、複数（図示の例では８本）のボンディングワイヤ４５（図２及び図３）によって基部９に対して電気的に接続されている。なお、ＩＣ５は、少なくとも一部が封止樹脂４９（後述する図１１参照）によって覆われていてもよい。 The crystal element 3 is fixed and electrically connected to the base 9 by two conductive adhesives 41 (FIGS. 2 and 3). The IC 5 is fixed to the base 9 by an adhesive 43 (FIG. 2) and electrically connected to the base 9 by a plurality (eight in the example shown) of bonding wires 45 (FIGS. 2 and 3). It is connected to the. At least part of the IC 5 may be covered with a sealing resin 49 (see FIG. 11 described later).
　なお、図２では、８本のボンディングワイヤ４５のうち、II－II線に位置する１本のみが示されている。また、図３では、８本のボンディングワイヤ４５のうち２本は、水晶素子３に隠れて不図示となっている。 Note that FIG. 2 shows only one of the eight bonding wires 45 located on line II-II. 3, two of the eight bonding wires 45 are hidden behind the crystal element 3 and are not shown.
　ＩＣ５とパッケージ７（基部９）とを電気的に接続する部材（図示の例ではボンディングワイヤ４５）を接続部材ということがある。発振器１は、例えば、接続部材とＩＣ５との接合に関して新たな構成を有している。他の構成は、種々の態様とされてよく、例えば、公知の態様とされても構わない。換言すれば、図１～図３に示されている、水晶素子３の構成、ＩＣ５の構成（上記の接合に係る構成を除く）、パッケージ７の構成、並びに各素子の実装構造（上記の接合に係る構成を除く）等は、一例に過ぎない。例えば、既述の説明とは異なり、発振器１の外形は、直方体状でなくても構わない。 A member (bonding wire 45 in the illustrated example) that electrically connects the IC 5 and the package 7 (base 9) is sometimes called a connection member. The oscillator 1 has, for example, a new configuration regarding the bonding between the connecting member and the IC 5 . Other configurations may be in various aspects, for example, may be in known aspects. In other words, the structure of the crystal element 3, the structure of the IC 5 (excluding the structure related to the bonding described above), the structure of the package 7, and the mounting structure of each element (the bonding described above) shown in FIGS. ) etc. is merely an example. For example, unlike the above description, the outer shape of the oscillator 1 does not have to be rectangular parallelepiped.
　以下では、概ね、下記の順に説明を行う。
　（１）種々の態様（公知の態様を含む）とされて構わない構成の概要（図１～図３）
　（２）接続部材（ボンディングワイヤ４５）の接合に係る構成（図４）
　（３）水晶素子３における導体の材料（図４）
　（４）発振器１の製造方法（図５）
　（５）第１実施形態のまとめ In the following, the description will generally be given in the following order.
(1) Overview of configurations that may be in various modes (including known modes) (Figs. 1 to 3)
(2) Configuration related to bonding of connecting member (bonding wire 45) (Fig. 4)
(3) Conductor material in crystal element 3 (Fig. 4)
(4) Manufacturing method of oscillator 1 (Fig. 5)
(5) Summary of the first embodiment
　（１）の説明は、特に断りなく、新規な態様の説明を含むことがある。また、（１）の説明は、図１～図３に示された態様を例にとって行う。（１）の説明では、水晶素子３、ＩＣ５、パッケージ７（基部９及び蓋１１）、及び実装に係る部材（導電性接着剤４１、接着剤４３及びボンディングワイヤ４５）、のそれぞれについて順に説明を行い、その後、水晶素子３及びＩＣ５等の位置関係について説明する。 The description of (1) may include description of novel aspects without any particular notice. Also, the description of (1) will be made by taking the mode shown in FIGS. 1 to 3 as an example. In the explanation of (1), the crystal element 3, the IC 5, the package 7 (the base portion 9 and the lid 11), and the members involved in mounting (the conductive adhesive 41, the adhesive 43 and the bonding wire 45) are explained in order. After that, the positional relationship between the crystal element 3 and the IC 5 will be described.
（水晶素子）
　水晶素子３は、例えば、水晶ブランク１３と、水晶ブランク１３に電圧を印加するための２以上（図示の例では１対）の励振電極１５と、水晶素子３をパッケージ７の基部９に実装するための２以上（図示の例では１対）の引出電極１７とを有している。 (crystal element)
The crystal element 3 includes, for example, a crystal blank 13 , two or more (one pair in the illustrated example) excitation electrodes 15 for applying a voltage to the crystal blank 13 , and the crystal element 3 mounted on the base 9 of the package 7 . It has two or more (one pair in the illustrated example) extraction electrodes 17 for the purpose.
　水晶素子３は、例えば、厚み滑り振動を利用するものである。このような水晶素子３においては、水晶ブランク１３は、例えば、板状に構成されている。水晶ブランク１３のカット角は、例えば、ＡＴカット又はＢＴカットである。１対の励振電極１５は、板状の水晶ブランク１３の両面に重なっている。１対の引出電極１７は、１対の励振電極１５に個別に接続されている。水晶ブランク１３、励振電極１５及び引出電極１７のより具体的な構成（平面形状等）は適宜に設定されてよい。 The crystal element 3 uses, for example, thickness-shear vibration. In such a crystal element 3, the crystal blank 13 is configured in a plate shape, for example. The cut angle of the crystal blank 13 is, for example, AT cut or BT cut. A pair of excitation electrodes 15 overlaps both surfaces of the plate-like crystal blank 13 . A pair of extraction electrodes 17 are individually connected to a pair of excitation electrodes 15 . A more specific configuration (planar shape, etc.) of the crystal blank 13, the excitation electrode 15, and the extraction electrode 17 may be appropriately set.
　例えば、水晶ブランク１３、励振電極１５及び引出電極１７の形状は、水晶素子３の両面のいずれが実装側（－Ｄ３側）とされてもよいように、Ｄ１方向（図示の例では水晶素子３の長手方向）に延びる不図示の中心線に対して概略１８０°回転対称の形状に形成されてよい。ただし、図示の例とは異なり、水晶ブランク１３、励振電極１５及び引出電極１７の形状は、回転対称の形状でなくてもよい。 For example, the shape of the crystal blank 13, the excitation electrode 15, and the extraction electrode 17 is such that either of the two surfaces of the crystal element 3 may be the mounting side (-D3 side). (longitudinal direction)), and may be formed into a shape approximately 180° rotationally symmetrical with respect to a center line (not shown). However, unlike the illustrated example, the shapes of the crystal blank 13, the excitation electrode 15, and the extraction electrode 17 do not have to be rotationally symmetrical.
　また、例えば、水晶ブランク１３の平面形状は、矩形状（図示の例）、円形状又は楕円形状とされてよい。また、水晶ブランク１３の厚さは、一定であってもよいし、一定でなくてもよい（図示の例）。後者の例としては、特に図示しないが、中央部分が外周部分よりも厚い、いわゆるメサ型を挙げることができる。 Further, for example, the planar shape of the crystal blank 13 may be rectangular (example shown), circular, or elliptical. Also, the thickness of the crystal blank 13 may be constant or may not be constant (example shown). As an example of the latter, although not shown, a so-called mesa shape in which the central portion is thicker than the outer peripheral portion can be cited.
　図示の例では、水晶ブランク１３は、相対的に薄い部分と、相対的に厚い部分とを有している。薄い部分には１対の励振電極１５が位置している。厚い部分は、例えば、水晶ブランク１３の一端（１辺）に位置しており、また、１対の引出電極１７が位置している。励振電極１５が位置している部分が薄くされていることによって、発振信号の周波数を高くすることができる。その一方で、厚い部分によって、例えば、水晶ブランク１３の強度を向上させることができる。なお、厚い部分は、図示の例とは異なり、例えば、水晶ブランク１３の２辺、３辺又は４辺に形成されてもよい。別の観点では、厚い部分は、引出電極１７が位置しない領域に形成されてもよい。 In the illustrated example, the crystal blank 13 has a relatively thin portion and a relatively thick portion. A pair of excitation electrodes 15 are located in the thin portion. The thick portion is located, for example, at one end (one side) of the crystal blank 13, and a pair of extraction electrodes 17 are located. By thinning the portion where the excitation electrode 15 is located, the frequency of the oscillation signal can be increased. On the other hand, the thicker portions can, for example, increase the strength of the crystal blank 13 . In addition, unlike the illustrated example, the thick portions may be formed, for example, on two sides, three sides, or four sides of the crystal blank 13 . From another point of view, the thick portion may be formed in a region where the extraction electrode 17 is not located.
　また、例えば、励振電極１５の平面形状は、円形状（図示の例）であってもよいし、矩形状であってもよいし、楕円形状であってもよい。また、励振電極１５の平面形状は、水晶ブランク１３の平面形状（又はメサ部の平面形状）に対して類似する形状であってもよいし、そのような形状でなくてもよい（図示の例）。前者としては、矩形状－矩形状の組み合わせ、円形状‐円形状の組み合わせ、楕円形状‐楕円形状の組み合わせを挙げることができる。 Further, for example, the planar shape of the excitation electrode 15 may be a circular shape (example shown in the drawing), a rectangular shape, or an elliptical shape. Further, the planar shape of the excitation electrode 15 may be a shape similar to the planar shape of the crystal blank 13 (or the planar shape of the mesa portion), or may not be such a shape (example shown in the figure). ). The former includes a rectangular-rectangular combination, a circular-circular combination, and an elliptical-elliptical combination.
　１対の引出電極１７は、例えば、励振電極１５から水晶ブランク１３の一端側へ引き出されている。従って、引出電極１７がパッケージ７の基部９に接合されると、水晶素子３は、片持ち梁状に支持される。ただし、１対の引出電極１７は、水晶ブランク１３の両端へ引き出され、水晶素子３の両端支持に寄与してもよい。 A pair of extraction electrodes 17 are extracted from the excitation electrode 15 to one end side of the crystal blank 13, for example. Therefore, when the extraction electrode 17 is joined to the base portion 9 of the package 7, the crystal element 3 is supported in a cantilever manner. However, the pair of lead electrodes 17 may be led out to both ends of the crystal blank 13 and contribute to supporting both ends of the crystal element 3 .
　引出電極１７は、より詳細には、例えば、特に符号を付さないが、励振電極１５から延びる配線部と、配線部の先端に接続されているパッド状の端子部とを有している。端子部は、パッケージ７の基部９に接合される部分である。１つの引出電極１７が含む端子部は、既述のように、水晶素子３の両面のいずれが実装側となってもよいように、水晶ブランク１３の両面に位置している２つの部分を有している。この２つの部分は、例えば、水晶ブランク１３の端面（－Ｄ１側の面）、水晶ブランク１３の側面（＋Ｄ２側の面又は‐Ｄ２側の面）、水晶ブランク１３に形成された不図示の貫通穴の少なくとも１つを介して、互いに接続されている。 More specifically, the lead-out electrode 17 has, for example, a wiring portion extending from the excitation electrode 15 and a pad-like terminal portion connected to the tip of the wiring portion, although no particular reference numeral is attached. The terminal portion is a portion that is joined to the base portion 9 of the package 7 . As described above, the terminal portion included in one extraction electrode 17 has two portions located on both sides of the crystal blank 13 so that either side of the crystal element 3 can be the mounting side. are doing. These two portions are, for example, the end surface of the crystal blank 13 (the surface on the -D1 side), the side surface of the crystal blank 13 (the surface on the +D2 side or the -D2 side), and a through hole (not shown) formed in the crystal blank 13. They are connected to each other through at least one of the holes.
　厚み滑り振動を利用する水晶素子３においては、水晶ブランク１３の厚さ（特に断りがない限り、励振電極１５が重なっている部分における厚さ。以下、同様。）は、発振信号の周波数を決定する因子となっている。例えば、公知のように、ＡＴカットの水晶素子においては、基本的には、ｆ＝１．６７×ｎ／ｔの関係が成り立つ。ここで、ｆは周波数（ＭＨｚ）、ｎは利用される振動の次数、ｔ（ｍｍ）は厚さである。既述のように、発振信号の周波数は任意であり、ひいては、水晶ブランク１３の厚さも任意である。例えば、水晶ブランク１３の厚さは、５μｍ以上３０μｍ以下とされてよい。この厚さは、基本波（ｎ＝１）を利用する発振器１において、概ね、５０ＭＨｚ以上３００ＭＨｚ以下に対応する。 In the crystal element 3 that utilizes thickness-shear vibration, the thickness of the crystal blank 13 (unless otherwise specified, the thickness at the portion where the excitation electrode 15 overlaps; the same shall apply hereinafter) determines the frequency of the oscillation signal. It is a factor that For example, as is well known, in an AT-cut crystal element, a relationship of f=1.67×n/t is basically established. where f is the frequency (MHz), n is the order of vibration used, and t (mm) is the thickness. As mentioned above, the frequency of the oscillation signal is arbitrary, and the thickness of the crystal blank 13 is also arbitrary. For example, the thickness of the crystal blank 13 may be 5 μm or more and 30 μm or less. This thickness generally corresponds to 50 MHz or more and 300 MHz or less in the oscillator 1 using the fundamental wave (n=1).
　水晶素子３は、上記以外の構成とされてもよい。例えば、水晶素子３は、屈曲振動を利用する音叉型の素子、輪郭すべり振動を利用するＣＴカット若しくはＤＴカットの素子、又はＳＡＷ（surface acoustic wave）を利用する素子であってもよい。なお、このような素子も、水晶ブランク１３と、水晶ブランク１３に重なる２以上の励振電極１５とを有している。ＳＡＷを利用する素子においては、水晶ブランク（水晶の層）は、他の材料からなる層と重なっていてもよい。 The crystal element 3 may have a configuration other than the above. For example, the crystal element 3 may be a tuning fork type element using bending vibration, a CT cut or DT cut element using contour shear vibration, or an element using SAW (surface acoustic wave). Such an element also has a crystal blank 13 and two or more excitation electrodes 15 overlapping the crystal blank 13 . In devices utilizing SAW, the crystal blank (layer of crystal) may overlap layers of other materials.
　板状でない水晶ブランク１３、及び／又は厚さが周波数を決定する因子となっていない水晶ブランク１３において、水晶ブランク１３の厚さは適宜に設定されてよい。例えば、そのような水晶ブランク１３における厚さは、上記の５μｍ以上３０μｍ以下とされてよい。板状でない水晶ブランク１３の厚さ方向は、その全体的な形状から合理的に決定されてよい。例えば、音叉型においては、並列に延びる２以上の腕が延びる方向、及び上記２以上の腕の並び方向の双方に直交する方向の寸法が厚さである。 The thickness of the crystal blank 13 may be set as appropriate for the crystal blank 13 that is not plate-shaped and/or the crystal blank 13 whose thickness is not a factor that determines the frequency. For example, the thickness of such a crystal blank 13 may be 5 μm or more and 30 μm or less. The thickness direction of the non-platy crystal blank 13 may be reasonably determined from its overall shape. For example, in a tuning fork type, the dimension in the direction orthogonal to both the direction in which two or more arms extend in parallel and the direction in which the two or more arms are arranged is the thickness.
（ＩＣ）
　ＩＣ５は、内部に種々の回路を有しているチップ本体１９と、上記の回路とＩＣ５の外部との接続を仲介する複数のＩＣ端子２１とを有している。なお、図示の例では、図１に示されているように、８つのＩＣ端子２１が示されている。図２では、－Ｄ１側の１つのＩＣ端子２１のみが示されている。図３では、－Ｄ１側の２つのＩＣ端子は、水晶素子３に隠れて不図示となっている。 (IC)
The IC 5 has a chip body 19 having various circuits inside, and a plurality of IC terminals 21 that mediate connections between the circuits and the outside of the IC 5 . In the illustrated example, eight IC terminals 21 are shown as shown in FIG. In FIG. 2, only one IC terminal 21 on the -D1 side is shown. In FIG. 3, the two IC terminals on the -D1 side are hidden by the crystal element 3 and are not shown.
　チップ本体１９は、特に図示しないが、例えば、半導体（例えばシリコン）からなる基板を有しており、当該基板に対して、不純物がドーピングされたり、導電層が形成されたりすることによって、適宜な回路を有している。チップ本体１９が有している回路としては、例えば、既述の発振回路が挙げられる。チップ本体１９は、温度センサ、及び、温度センサの検出した温度に基づいて発振信号の温度変化を補償する温度補償回路を含んでいてもよい。ＩＣ５（チップ本体１９）は、パッケージングされたものであってもよいし、ベアチップであってもよい。 Although not shown, the chip body 19 has a substrate made of, for example, a semiconductor (eg, silicon). have a circuit. The circuit included in the chip body 19 is, for example, the oscillation circuit described above. The chip body 19 may include a temperature sensor and a temperature compensation circuit that compensates for temperature changes in the oscillation signal based on the temperature detected by the temperature sensor. The IC 5 (chip body 19) may be packaged or may be a bare chip.
　チップ本体１９の形状は任意である。一般には、チップ本体１９の形状は、図示の例のように、薄型の直方体状である。また、チップ本体１９の寸法も任意である。例えば、チップ本体１９の平面視における広さ（面積）は、水晶素子３の平面視における広さに対して、大きくてもよいし（図示の例）、同等でもよいし、小さくてもよい。なお、上記の水晶素子３の平面視における広さは、水晶素子３が音叉型のように板状でない場合においては、水晶素子３を包含する最小の矩形の広さとされてよい。また、例えば、チップ本体１９の厚さは、水晶素子３の厚さ（励振電極１５が重なる部分の厚さ、又は最大厚さ）に対して、厚くてもよいし（図示の例）、同等でもよいし、薄くてもよい。 The shape of the chip body 19 is arbitrary. In general, the shape of the chip body 19 is a thin rectangular parallelepiped, as shown in the drawing. Moreover, the dimensions of the chip body 19 are also arbitrary. For example, the width (area) of the chip body 19 in plan view may be larger than the width of the crystal element 3 in plan view (example shown), may be the same, or may be smaller. The width of the crystal element 3 in plan view may be the minimum rectangular width that includes the crystal element 3 when the crystal element 3 is not plate-shaped like a tuning fork. Further, for example, the thickness of the chip body 19 may be thicker than the thickness of the crystal element 3 (the thickness of the portion where the excitation electrode 15 overlaps, or the maximum thickness) (example shown), or may be the same. It may be fine, or it may be thin.
　ＩＣ端子２１の数及び役割は、ＩＣ５（発振器１）に要求される機能等に応じて適宜に設定されてよい。例えば、ＩＣ端子２１は、以下の端子を含んでよい。基準電位であるグランド電位をＩＣ５に供給するための１つのＩＣ端子２１。電源電圧（基準電位とは異なる電位）をＩＣ５に供給するための１つのＩＣ端子２１。水晶素子３に電圧を印加するための２つのＩＣ端子２１。生成した発振信号を出力するための１つの端子２１。さらに、ＩＣ端子２１は、以下の端子を含んでもよい。発振信号の周波数を調整する制御信号をＩＣ５に入力するための１つのＩＣ端子２１。発振信号の生成又は停止を指示するイネーブル・ディセーブル信号をＩＣ５に入力するためのＩＣ端子２１。 The number and roles of the IC terminals 21 may be appropriately set according to the functions required of the IC 5 (oscillator 1). For example, the IC terminals 21 may include the following terminals. One IC terminal 21 for supplying a ground potential, which is a reference potential, to the IC 5 . One IC terminal 21 for supplying a power supply voltage (potential different from the reference potential) to the IC 5 . Two IC terminals 21 for applying voltage to the crystal element 3 . One terminal 21 for outputting the generated oscillation signal. Furthermore, the IC terminals 21 may include the following terminals. One IC terminal 21 for inputting a control signal for adjusting the frequency of the oscillation signal to IC5. An IC terminal 21 for inputting an enable/disable signal to the IC 5 to instruct generation or stop of the oscillation signal.
　ＩＣ端子２１は、例えば、ＩＣ５の２つの主面（最も広い面。表裏）のうちの一方の面に重なるパッドによって構成されている。ＩＣ端子２１の平面形状、寸法及び配置位置は任意である。例えば、複数のＩＣ端子２１の平面形状及び寸法は、互いに同一であってもよいし（図示の例）、互いに異なっていてもよい。ＩＣ端子２１の平面形状は、矩形状（図示の例）、円形状又は楕円形状とされてよい。１つのＩＣ端子２１の平面視における広さは、１つの引出電極１７の端子部の－Ｄ３側に面する部分の広さに対して、小さくてもよいし（図示の例）、同等でもよいし、大きくてもよい。また、複数のＩＣ端子２１は、概ねチップ本体１９の外縁に沿って１列に配列されていてもよいし（図示の例）、図示の例とは異なり、外縁に沿って１列に配列された複数のＩＣ端子２１の内側に位置する他のＩＣ端子２１を含んでいてもよい。 The IC terminal 21 is composed of, for example, a pad that overlaps one of the two main surfaces (the widest surface; front and back) of the IC 5 . The planar shape, size and arrangement position of the IC terminal 21 are arbitrary. For example, the planar shape and dimensions of the plurality of IC terminals 21 may be the same (example shown) or may be different. The planar shape of the IC terminal 21 may be rectangular (illustrated example), circular, or elliptical. The width of one IC terminal 21 in plan view may be smaller than the width of the portion facing the -D3 side of the terminal portion of one extraction electrode 17 (example shown), or may be the same. and can be larger. Also, the plurality of IC terminals 21 may be arranged in a row generally along the outer edge of the chip body 19 (example shown), or unlike the example shown in the figure, may be arranged in a row along the outer edge. It may also include another IC terminal 21 positioned inside the plurality of IC terminals 21 .
（パッケージ）
　パッケージ７は、既述のように、基部９と、基部９に固定される蓋１１とを有している。基部９及び蓋１１は、水晶素子３及びＩＣ５を収容する密閉空間Ｓ１を構成している。基部９及び蓋１１の具体的な形状、水晶素子３及びＩＣ５の基部９に対する実装構造、及び水晶素子３及びＩＣ５の相対位置等は、適宜なものとされてよい。 (package)
The package 7 has a base 9 and a lid 11 fixed to the base 9, as described above. The base 9 and the lid 11 form a sealed space S1 that accommodates the crystal element 3 and the IC5. The specific shapes of the base portion 9 and the lid 11, the mounting structure of the crystal element 3 and the IC 5 with respect to the base portion 9, the relative positions of the crystal element 3 and the IC 5, and the like may be made as appropriate.
　図示の例では、基部９は、＋Ｄ３側に面している第１面９ａ（図示の例では凹部の底面）を有している。蓋１１は、第１面９ａ上に密閉空間Ｓ１が構成されるように基部９に固定されている。ＩＣ５は、第１面９ａに固定されて密閉空間Ｓ１に収容されている。水晶素子３は、ＩＣ５を介して第１面９ａに対向する位置にて密閉空間Ｓ１に収容されている。すなわち、図示の例のパッケージ７は、第１面９ａ上に水晶素子３及びＩＣ５を積層的に収容している。具体的には、以下のとおりである。 In the illustrated example, the base portion 9 has a first surface 9a (the bottom surface of the recess in the illustrated example) facing the +D3 side. The lid 11 is fixed to the base 9 so as to form a closed space S1 on the first surface 9a. The IC 5 is fixed to the first surface 9a and accommodated in the sealed space S1. The crystal element 3 is accommodated in the closed space S1 at a position facing the first surface 9a through the IC5. That is, the illustrated package 7 accommodates the crystal element 3 and the IC 5 in a stacked manner on the first surface 9a. Specifically, it is as follows.
（パッケージの基部）
　基部９は、例えば、絶縁性の基体２３と、基体２３に設けられた各種の導体（例えば金属）とを有している。基体２３は、例えば、基部９の大部分を占めており、基部９の形状は、基体２３の形状と概ね同等である。各種の導体は、例えば、水晶素子３及びＩＣ５が電気的に接続されるパッド等を構成している。 (base of package)
The base 9 has, for example, an insulating substrate 23 and various conductors (eg, metal) provided on the substrate 23 . The base 23 , for example, occupies most of the base 9 , and the base 9 has substantially the same shape as the base 23 . Various conductors constitute, for example, pads to which the crystal element 3 and the IC 5 are electrically connected.
（基部の基体）
　基体２３の形状、寸法及び材料は任意である。図示の例では、基体２３の外形は、概略直方体状である。また、図示の例では、基体２３は、上面に開口している第１凹部２５と、第１凹部２５の底面に開口している第２凹部２７と、第２凹部２７の底面に開口している第３凹部２９とを有している。第３凹部２９は、ＩＣ５を収容している。第３凹部２９の底面（厳密には当該底面に重なる後述するダイパッド４２）は、上述した第１面９ａの一例となっている。第２凹部２７は、ボンディングワイヤ４５を収容している。第１凹部２５は、水晶素子５を収容している。 (base substrate)
The shape, size and material of the substrate 23 are arbitrary. In the illustrated example, the outer shape of the base 23 is substantially rectangular parallelepiped. In the illustrated example, the base 23 includes a first recess 25 opening on the top surface, a second recess 27 opening on the bottom surface of the first recess 25, and a bottom surface of the second recess 27 opening on the bottom surface. and a third recessed portion 29 which is provided. The third recess 29 accommodates the IC5. The bottom surface of the third concave portion 29 (strictly speaking, a die pad 42 described later overlapping with the bottom surface) is an example of the first surface 9a described above. The second recess 27 accommodates the bonding wire 45 . The first recess 25 accommodates the crystal element 5 .
　なお、特に符号を付さないが、基体２３は、１つの凹部を有していると捉えられてもよい。また、上記１つの凹部として、第３凹部２９の底面（第１面９ａ）を含む第１底面を有するものを想定し、当該第１底面に第１台座（その上面は第２凹部２７の底面を含む）が形成され、第１台座の上面に第２台座（その上面は第１凹部２５の底面を含む）が形成されていると捉えられてもよい。 Although not specifically numbered, the base 23 may be regarded as having one recess. Further, assuming that the one concave portion has a first bottom surface including the bottom surface (first surface 9a) of the third concave portion 29, the first bottom surface is provided with a first pedestal (the upper surface of which is the bottom surface of the second concave portion 27). ) is formed, and the second pedestal (the upper surface of which includes the bottom surface of the first recess 25 ) is formed on the upper surface of the first pedestal.
　基体２３は、例えば、複数（本実施形態では４つ）の第１絶縁層３１Ａ～第４絶縁層３１Ｄによって構成されている。具体的には、例えば、基部９は、基部９の下面側から順に、第１絶縁層３１Ａと、第３凹部２９を構成する開口を有する第２絶縁層３１Ｂと、第２凹部２７を構成する開口を有する第３絶縁層３１Ｃと、第１凹部２５を構成する開口を有する第４絶縁層３１Ｄとを有している。 The base 23 is composed of, for example, a plurality of (four in this embodiment) first insulating layers 31A to fourth insulating layers 31D. Specifically, for example, the base 9 comprises a first insulating layer 31A, a second insulating layer 31B having an opening forming a third recess 29, and a second recess 27, in this order from the bottom surface of the base 9. It has a third insulating layer 31</b>C having an opening and a fourth insulating layer 31</b>D having an opening forming the first recess 25 .
　なお、基体２３は、絶縁層３１を積層して作製されてもよいし、そのような製造方法とは異なる製造方法によって作製されてもよい。前者としては、例えば、複数の絶縁層３１となる複数のセラミックグリーンシートを積層して焼成する方法が挙げられる。後者としては、例えば、１つのセラミックグリーンシートにプレスによって凹部（２５、２７及び２９）を形成して焼成する方法が挙げられる。前者の製造方法と後者の製造方法とは組み合わされてもよい。後者の製造方法から理解されるように、絶縁層３１は、基体２３の形状及び／又は基体２３内の導体層に基づいて概念される便宜上のものであってよい。 Note that the substrate 23 may be produced by laminating the insulating layer 31, or may be produced by a manufacturing method different from such a manufacturing method. As the former method, for example, a method of laminating and firing a plurality of ceramic green sheets to be a plurality of insulating layers 31 can be used. As the latter method, for example, there is a method of forming concave portions (25, 27 and 29) in one ceramic green sheet by pressing and firing. The former manufacturing method and the latter manufacturing method may be combined. As will be understood from the latter manufacturing method, the insulating layer 31 may be of convenience that is conceived based on the shape of the substrate 23 and/or the conductor layers within the substrate 23 .
　複数の絶縁層３１の外縁の形状は、例えば、基体２３の外形が直方体状であることに対応して矩形状である。各凹部（２５、２７及び２９）の平面形状は、例えば、絶縁層３１の外縁の矩形と平行な４辺を有する矩形状である。各絶縁層３１の厚さ（各凹部の深さ）は、互いに同一であってもよいし、互いに異なっていてもよく、水晶素子３及びＩＣ５の厚さ等に応じて適宜に設定されてよい。 The shape of the outer edges of the plurality of insulating layers 31 is, for example, a rectangular shape corresponding to the rectangular parallelepiped shape of the substrate 23 . The planar shape of each recess (25, 27 and 29) is, for example, a rectangular shape having four sides parallel to the rectangle of the outer edge of the insulating layer 31. As shown in FIG. The thickness of each insulating layer 31 (the depth of each recess) may be the same as or different from each other, and may be appropriately set according to the thicknesses of the crystal element 3 and the IC 5. .
　第２凹部２７は、例えば、Ｄ１方向（基体２３の長手方向）及びＤ２方向（基体２３の短手方向）の少なくとも一方（図示の例ではＤ１方向）において、第１凹部２５よりも小さい。これにより、第１凹部２５の底面（第３絶縁層３１Ｃの上面）は、第２凹部２７の周囲にて上方に露出している。なお、以下において、第１凹部２５の底面は、第２凹部２７の周囲の領域のみ（第２凹部２７が開口している領域を除く領域のみ）を指すことがある。第１凹部２５の底面は、例えば、水晶素子３の実装に利用される。 The second recess 27 is, for example, smaller than the first recess 25 in at least one of the D1 direction (longitudinal direction of the base 23) and the D2 direction (lateral direction of the base 23) (the D1 direction in the illustrated example). As a result, the bottom surface of the first recess 25 (the upper surface of the third insulating layer 31C) is exposed upward around the second recess 27 . In the following, the bottom surface of the first recess 25 may refer to only the area around the second recess 27 (only the area excluding the area where the second recess 27 is open). The bottom surface of the first concave portion 25 is used for mounting the crystal element 3, for example.
　第３凹部２９は、例えば、Ｄ１方向（基体２３の長手方向）及びＤ２方向（基体２３の短手方向）の少なくとも一方（図示の例では双方）において、第２凹部２７よりも小さい。これにより、第２凹部２７の底面（第２絶縁層３１Ｂの上面）は、第３凹部２９の周囲にて上方に露出している。なお、以下において、第２凹部２７の底面は、第３凹部２９の周囲の領域のみ（第３凹部２９が開口している領域を除く領域のみ）を指すことがある。第２凹部２７の底面は、例えば、ＩＣ５との基部９の導体との電気的接続に利用される。 The third recess 29 is smaller than the second recess 27, for example, in at least one (both in the illustrated example) of the D1 direction (longitudinal direction of the base 23) and the D2 direction (lateral direction of the base 23). As a result, the bottom surface of the second recess 27 (the upper surface of the second insulating layer 31B) is exposed upward around the third recess 29 . In the following, the bottom surface of the second recess 27 may refer to only the area around the third recess 29 (only the area excluding the area where the third recess 29 is open). The bottom surface of the second recess 27 is used, for example, for electrical connection with the IC 5 and the conductors of the base 9 .
　平面視における複数の凹部（２５、２７及び２９）の相対位置及び相対的な大きさは任意である。これらは、例えば、各凹部に収容される素子の大きさ、及び各凹部の底面に形成される導体層（例えば各種の素子と接続されるパッド）の配置位置等を考慮して適宜に設定されてよい。その具体例については、導体層の説明とともに後述する。 The relative positions and relative sizes of the plurality of recesses (25, 27 and 29) in plan view are arbitrary. These are appropriately set in consideration of, for example, the size of the elements accommodated in each recess, and the arrangement position of a conductor layer (for example, pads connected to various elements) formed on the bottom surface of each recess. you can A specific example thereof will be described later together with the description of the conductor layer.
　既に触れたように、基体２３の材料は、例えば、セラミックとされてよい。複数の絶縁層３１は、例えば、セラミックからなり、一体的に形成されている。セラミックの具体的な種類は任意であり、例として、酸化アルミニウム（アルミナ、Ａｌ２Ｏ３）、窒化アルミニウム（ＡｌＮ）、及びＬＴＣＣ（Low Temperature Co-fired Ceramics）を挙げることができる。上記材料の線膨張率は、例えば、３ｐｐｍ／Ｋ以上１３ｐｐｍ／Ｋ以下である。上記材料のヤング率は、例えば、５０ＧＰａ以上３５０ＧＰａ以下である。ただし、基体２３の材料は、セラミック以外の絶縁材料（例えば樹脂）であっても構わない。 As already mentioned, the material of the substrate 23 may be ceramic, for example. The plurality of insulating layers 31 are made of ceramic, for example, and are integrally formed. Any specific type of ceramic may be used, and examples include aluminum oxide (alumina, Al 2 O 3 ), aluminum nitride (AlN), and LTCC (Low Temperature Co-fired Ceramics). The coefficient of linear expansion of the material is, for example, 3 ppm/K or more and 13 ppm/K or less. The Young's modulus of the material is, for example, 50 GPa or more and 350 GPa or less. However, the material of the substrate 23 may be an insulating material other than ceramic (for example, resin).
（基部の導体）
　基部９の導体は、例えば、以下のものを含んでいる。水晶素子３（より詳細には引出電極１７）に電気的に接続される１対の水晶用パッド３３。ＩＣ５（より詳細にはＩＣ端子２１）に電気的に接続される複数（図示の例では８つ）のＩＣ用パッド３５。発振器１を不図示の回路基板等に電気的に接続するための複数（図示の例では４つ）の外部端子３７。上記の導体（３３、３５及び３７）を互いに接続する不図示の配線導体。蓋１１を基部９に接合するための第１接合用金属層３９。ＩＣ５が固定されるダイパッド４２。なお、４つの外部端子３７のうち、１つは、いずれの図面においても基体２３に隠れて不図示である。 (base conductor)
The conductors of base 9 include, for example: A pair of crystal pads 33 electrically connected to the crystal element 3 (more specifically, the extraction electrodes 17). A plurality of (eight in the illustrated example) IC pads 35 electrically connected to the IC 5 (more specifically, the IC terminal 21). A plurality of (four in the illustrated example) external terminals 37 for electrically connecting the oscillator 1 to a circuit board or the like (not shown). Wiring conductors (not shown) connecting the above conductors (33, 35 and 37) to each other. A first bonding metal layer 39 for bonding the lid 11 to the base 9 . A die pad 42 to which the IC5 is fixed. One of the four external terminals 37 is hidden behind the base 23 and not shown in any of the drawings.
　１対の水晶用パッド３３は、基部９の配線導体を介して、２つのＩＣ用パッド３５と接続されている。これにより、ＩＣ５は、水晶素子３に電圧を印加可能となっている。また、上記の２つのＩＣ用パッド３５以外のＩＣ用パッド３５は、例えば、基部９の配線導体を介して外部端子３７と接続されている。これにより、ＩＣ５は、発振器１の外部からの電気信号の入力、及び発振器１の外部への電気信号の出力が可能となっている。 A pair of crystal pads 33 are connected to two IC pads 35 via wiring conductors of the base 9 . This allows the IC 5 to apply voltage to the crystal element 3 . IC pads 35 other than the two IC pads 35 are connected to external terminals 37 via, for example, wiring conductors of the base portion 9 . This allows the IC 5 to input an electric signal from outside the oscillator 1 and output an electric signal to the outside of the oscillator 1 .
（水晶用パッド）
　水晶用パッド３３は、例えば、第１凹部２５の底面（第２凹部２７の周囲の領域）に位置している。第１凹部２５の底面の平面形状及び寸法、並びに水晶用パッド３３の平面形状及び寸法は任意であり、両者の相対関係も任意である。また、水晶用パッド３３は、第２凹部２７に対して、－Ｄ１側（図示の例）、＋Ｄ１側、－Ｄ２側及び＋Ｄ２側のいずれに位置してもよい。 (Crystal pad)
The crystal pad 33 is positioned, for example, on the bottom surface of the first recess 25 (the area around the second recess 27). The planar shape and dimensions of the bottom surface of the first recess 25 and the planar shape and dimensions of the crystal pad 33 are arbitrary, and the relative relationship between them is also arbitrary. Also, the crystal pad 33 may be positioned on any of the -D1 side (example shown), +D1 side, -D2 side and +D2 side with respect to the second concave portion 27 .
　図示の例では、第２凹部２７は、Ｄ２方向において第１凹部２５との同等の大きさを有している。また、第２凹部２７の＋Ｄ１側の縁部は、第１凹部２５の＋Ｄ１側の縁部に一致している。すなわち、第１凹部２５の底面（第２凹部２７の周囲の領域）は、－Ｄ１側においてのみ露出している。１対の水晶用パッド３３は、第１凹部２５の底面に対してＤ１方向の全体に広がっている。また、１対の水晶用パッド３３は、Ｄ２方向において互いに離れており、かつ第１凹部２５の底面に対してＤ２方向の端部にまで広がっている。このような構成では、例えば、水晶用パッド３３の面積と、第２凹部２７の面積との双方を大きくできる。 In the illustrated example, the second recess 27 has the same size as the first recess 25 in the D2 direction. The +D1 side edge of the second recess 27 coincides with the +D1 side edge of the first recess 25 . That is, the bottom surface of the first recess 25 (the area surrounding the second recess 27) is exposed only on the -D1 side. The pair of crystal pads 33 extends over the bottom surface of the first recess 25 in the D1 direction. The pair of crystal pads 33 are separated from each other in the D2 direction and extend to the end of the bottom surface of the first recess 25 in the D2 direction. With such a configuration, for example, both the area of the crystal pad 33 and the area of the second recess 27 can be increased.
　図示の例とは異なり、例えば、水晶用パッド３３のＤ１方向の長さは、第１凹部２５の底面のＤ１方向の長さよりも短くてもよい。また、水晶用パッド３３は、第１凹部２５の底面のＤ２方向の端部にまで広がっていなくてもよい。第１凹部２５の底面（第２凹部２７の周囲の領域）は、－Ｄ１側に位置する部分に加えて、又は代えて、＋Ｄ１側、－Ｄ２側及び／又は＋Ｄ２側に位置する部分を有していてもよい。これらの部分は、平面透視において、水晶素子３と重なっていてもよいし、重なっていなくてもよい。なお、水晶素子３が両端支持される構成である場合においては、例えば、第１凹部２５の底面のうちの、－Ｄ１側の部分と＋Ｄ１側の部分とに支持されてよい。また、例えば、１対の水晶用パッド３３の間に第２凹部２７の一部が位置していてもよい。 Unlike the illustrated example, for example, the length of the crystal pad 33 in the D1 direction may be shorter than the length of the bottom surface of the first recess 25 in the D1 direction. Further, the crystal pad 33 does not have to extend to the end of the bottom surface of the first recess 25 in the D2 direction. The bottom surface of the first recess 25 (region around the second recess 27) has a portion located on the +D1 side, the −D2 side and/or the +D2 side in addition to or instead of the portion located on the −D1 side. You may have These portions may or may not overlap with the crystal element 3 in planar see-through. When the crystal element 3 is supported at both ends, for example, it may be supported by the −D1 side portion and the +D1 side portion of the bottom surface of the first concave portion 25 . Also, for example, part of the second recess 27 may be located between the pair of crystal pads 33 .
（ＩＣ用パッド）
　ＩＣ用パッド３５は、例えば、第２凹部２７の底面（第３凹部２９の周囲の領域）に位置している。第２凹部２７の底面の平面形状及び寸法、並びにＩＣ用パッド３５の平面形状及び寸法は任意であり、両者の相対関係も任意である。ＩＣ用パッド３５は、第３凹部２９に対して、－Ｄ１側（図示の例）、＋Ｄ１側、－Ｄ２側（図示の例）及び＋Ｄ２側（図示の例）のいずれに位置してもよい。 (IC pad)
The IC pad 35 is located, for example, on the bottom surface of the second recess 27 (region around the third recess 29). The planar shape and dimensions of the bottom surface of the second recess 27 and the planar shape and dimensions of the IC pad 35 are arbitrary, and the relative relationship between them is also arbitrary. The IC pad 35 may be located on the -D1 side (illustrated example), the +D1 side, the -D2 side (illustrated example), or the +D2 side (illustrated example) with respect to the third recess 29. .
　図示の例では、第３凹部２９は、Ｄ１方向及びＤ２方向の双方において、第２凹部２７よりも小さい。また、第３凹部２９は、第２凹部２７に対して＋Ｄ１側に偏っている。これにより、第２凹部２７の底面（第３凹部２９の周囲の領域）は、主として、－Ｄ１側、－Ｄ２側及び＋Ｄ２側において露出している。複数のＩＣ用パッド３５は、ＩＣ端子２１と同数（図示の例では８個）で設けられ、第３凹部２９の開口縁部に沿って配列されている。ＩＣ用パッド３５は、例えば、第２凹部２７の底面に対して内周側（第３凹部２９側）から外周側への全体に広がっている。 In the illustrated example, the third recess 29 is smaller than the second recess 27 in both the D1 direction and the D2 direction. Also, the third recess 29 is biased toward the +D1 side with respect to the second recess 27 . As a result, the bottom surface of the second recess 27 (region around the third recess 29) is mainly exposed on the -D1 side, the -D2 side and the +D2 side. A plurality of IC pads 35 are provided in the same number as the IC terminals 21 (eight in the illustrated example), and are arranged along the opening edge of the third recess 29 . For example, the IC pad 35 extends over the bottom surface of the second recess 27 from the inner peripheral side (the third recess 29 side) to the outer peripheral side.
　図示の例とは異なり、例えば、ＩＣ用パッド３５の数は、ＩＣ端子２１の数よりも多くてもよい。換言すれば、使用されないダミーのＩＣ用パッド３５が存在してよい。また、例えば、ＩＣ用パッド３５の内周側から外周側への長さは、第２凹部２７の底面の内周側から外周側への長さよりも短くてもよい。第２凹部２７の底面（第３凹部２９の周囲の領域）は、＋Ｄ１側に十分な広さを有していてもよいし、逆に、－Ｄ１側、－Ｄ２側及び／又は＋Ｄ２側に位置する部分を有していなくてもよい。また、例えば、第３凹部２９の開口縁部に沿って互いに隣り合うＩＣ用パッド３５の間それぞれに、第３凹部２９の一部が位置していてもよい。 Unlike the illustrated example, for example, the number of IC pads 35 may be greater than the number of IC terminals 21 . In other words, there may be dummy IC pads 35 that are not used. Further, for example, the length from the inner circumference side to the outer circumference side of the IC pad 35 may be shorter than the length from the inner circumference side to the outer circumference side of the bottom surface of the second recess 27 . The bottom surface of the second recess 27 (the area surrounding the third recess 29) may have a sufficient width on the +D1 side, or conversely, may be wide enough on the -D1 side, the -D2 side and/or the +D2 side. It does not have to have a portion to be located. Also, for example, a part of the third recess 29 may be positioned between the IC pads 35 adjacent to each other along the opening edge of the third recess 29 .
　水晶用パッド３３の材料は任意である。水晶用パッド３３は、１層の金属層から構成されてもよいし、２層以上の金属層から構成されてもよい。水晶用パッド３３の材料の少なくとも一部は、基部９が有する他の導体層の材料（例えばＩＣ用パッド３５の材料（後述））の少なくとも一部と同じであってもよいし、全く異なっていてもよい。いずれにせよ、後述するＩＣ用パッド３５の材料の説明は、水晶用パッド３３の材料に援用されてよい。 The material of the crystal pad 33 is arbitrary. The crystal pad 33 may be composed of one metal layer, or may be composed of two or more metal layers. At least part of the material of the crystal pads 33 may be the same as at least part of the material of other conductor layers (for example, the material of the IC pads 35 (described later)) of the base 9, or may be completely different. may In any case, the description of the material of the IC pads 35 to be described later may be applied to the material of the crystal pads 33 .
　水晶用パッド３３の厚さも任意である。水晶用パッド３３の厚さは、ＩＣ用パッド３５の厚さ（後述）と同じであってもよいし、異なっていてもよい。ずれにせよ、ＩＣ用パッド３５の厚さの説明は、水晶用パッド３３の厚さに援用されてよい。 The thickness of the crystal pad 33 is also arbitrary. The thickness of the crystal pad 33 may be the same as or different from the thickness of the IC pad 35 (described later). In any case, the description of the thickness of the IC pad 35 may be used for the thickness of the crystal pad 33 .
（外部端子）
　複数の外部端子３７は、例えば、基体２３の下面に位置する層状の導体（パッド状）によって構成されている。発振器１は、不図示の回路基板のパッドと外部端子３７とが、その間に介在する半田等によって接合されることによって、上記回路基板に実装される。すなわち、図示の例の発振器１は、表面実装型のものである。 (external terminal)
The plurality of external terminals 37 are composed of, for example, layered conductors (pads) located on the lower surface of the substrate 23 . The oscillator 1 is mounted on the circuit board by joining the pads of the circuit board (not shown) and the external terminals 37 with solder or the like interposed therebetween. That is, the oscillator 1 in the illustrated example is of a surface mount type.
　外部端子３７の数、平面形状、寸法及び下面における位置等は任意である。図示の例では、４つの外部端子３７が矩形状の基体２３の４隅に位置している。外部端子３７の形状は、例えば、矩形状である。なお、図示の例とは異なり、外部端子３７の数は、５以上とされてもよい。また、外部端子３７は、ピン状とされてもよい。すなわち、発振器１は、表面実装型のものでなくてもよい。 The number of external terminals 37, planar shape, size, position on the bottom surface, etc. are arbitrary. In the illustrated example, four external terminals 37 are positioned at four corners of the rectangular base 23 . The shape of the external terminal 37 is, for example, rectangular. Note that, unlike the illustrated example, the number of external terminals 37 may be five or more. Also, the external terminal 37 may be pin-shaped. That is, the oscillator 1 does not have to be of the surface mount type.
　外部端子３７の数及び役割は、発振器１に要求される機能に応じて適宜に設定されてよい。例えば、複数の外部端子３７は、少なくとも、ＩＣ端子２１の説明で述べたグランド電位、電源電圧及び発振信号に対応する３つの外部端子３７を含んでいる。複数の外部端子３７は、さらに、制御信号等に対応する外部端子３７を含んでよい。また、外部端子３７は、発振器１を回路基板に接合するためのみに利用される（電気信号の伝達に利用されない）ダミーの外部端子３７を含んでいてもよい。 The number and roles of the external terminals 37 may be appropriately set according to the functions required of the oscillator 1. For example, the plurality of external terminals 37 includes at least three external terminals 37 corresponding to the ground potential, power supply voltage and oscillation signal described in the description of the IC terminal 21 . The plurality of external terminals 37 may further include external terminals 37 corresponding to control signals and the like. Moreover, the external terminals 37 may include dummy external terminals 37 that are used only for joining the oscillator 1 to the circuit board (not used for transmitting electrical signals).
　外部端子３７の材料は任意である。外部端子３７は、１層の金属層から構成されてもよいし、２層以上の金属層から構成されてもよい。外部端子３７の材料の少なくとも一部は、基部９が有する他の導体層の材料（例えばＩＣ用パッド３５の材料（後述））の少なくとも一部と同じであってもよいし、全く異なっていてもよい。いずれにせよ、後述するＩＣ用パッド３５の材料の説明は、水晶用パッド３３の材料に援用されてよい。外部端子３７の厚さも任意である。 The material of the external terminal 37 is arbitrary. The external terminal 37 may be composed of one metal layer, or may be composed of two or more metal layers. At least part of the material of the external terminals 37 may be the same as at least part of the material of other conductor layers (for example, the material of the IC pads 35 (described later)) of the base 9, or may be completely different. good too. In any case, the description of the material of the IC pads 35 to be described later may be applied to the material of the crystal pads 33 . The thickness of the external terminal 37 is also arbitrary.
（基部の配線導体）
　基部９の配線導体（不図示）の構成は適宜なものとされてよい。例えば、配線導体は、絶縁層３１の上面又は下面に位置する層状導体（層状配線）、及び／又は絶縁層３１を貫通する貫通導体（ビア導体）によって構成されてよい。 (base wiring conductor)
The configuration of the wiring conductors (not shown) of the base 9 may be made appropriate. For example, the wiring conductor may be composed of a layered conductor (layered wiring) located on the upper surface or the lower surface of the insulating layer 31 and/or a penetrating conductor (via conductor) penetrating the insulating layer 31 .
　配線導体の材料は任意である。例えば、これらの材料の少なくとも一部は、基部９が有する他の導体層の材料の少なくとも一部と同じであってもよいし、全く異なっていてもよい。例えば、配線導体のうち、基体２３に埋設されている部分の材料は、ＩＣ用パッド３５の下層５９（後述）の材料と同じとされてよい。いずれにせよ、ＩＣ用パッド３５の材料（後述）の説明は、適宜に配線導体に援用されてよい。 Any material can be used for the wiring conductor. For example, at least part of these materials may be the same as at least part of the materials of the other conductor layers of the base 9, or may be completely different. For example, the material of the portion of the wiring conductor embedded in the substrate 23 may be the same as the material of the lower layer 59 (described later) of the IC pad 35 . In any case, the description of the material of the IC pads 35 (described later) may be applied to the wiring conductors as appropriate.
（第１接合用金属層）
　第１接合用金属層３９は、例えば、シーム溶接によって蓋１１に接合される部材である。第１接合用金属層３９は、基体２３の上面（第１凹部２５の周囲の部分）に位置しているとともに、第１凹部２５の全周に亘って延びている。第１接合用金属層３９の幅は、例えば、基体２３の上面の幅と同等である。ただし、前者は後者よりも細くてもよい。 (First bonding metal layer)
The first joining metal layer 39 is a member joined to the lid 11 by seam welding, for example. The first bonding metal layer 39 is located on the upper surface of the base 23 (the portion surrounding the first recess 25 ) and extends over the entire circumference of the first recess 25 . The width of the first bonding metal layer 39 is, for example, equivalent to the width of the upper surface of the base 23 . However, the former may be thinner than the latter.
　第１接合用金属層３９の材料及び厚さは適宜に設定されてよい。例えば、第１接合用金属層３９の材料は、基部９が有する他の導体層の材料（例えばＩＣ用パッド３５の材料（後述））と同じであってもよいし、異なっていてもよい。いずれにせよ、後述するＩＣ用パッド３５の材料の説明は第１接合用金属層３９の材料に援用されてよい。また、第１接合用金属層３９は、Ｗ若しくはＭｏ又はこれらの少なくとも１つを主成分として含む合金からなる層と、当該層に重なるＮｉ層と、当該Ｎｉ層に重なるＡｕ層とによって構成されてよい。第１接合用金属層３９の厚さは、例えば、１０μｍ以上２５μｍ以下である。 The material and thickness of the first joining metal layer 39 may be set as appropriate. For example, the material of the first bonding metal layer 39 may be the same as or different from the material of the other conductor layers of the base 9 (for example, the material of the IC pads 35 (described later)). In any case, the description of the material of the IC pad 35 to be described later may be applied to the material of the first bonding metal layer 39 . The first bonding metal layer 39 is composed of a layer made of W or Mo or an alloy containing at least one of these as a main component, a Ni layer overlapping the layer, and an Au layer overlapping the Ni layer. you can The thickness of the first bonding metal layer 39 is, for example, 10 μm or more and 25 μm or less.
（ダイパッド）
　ダイパッド４２は、その上面にＩＣ５の下面が接着される部材である。ダイパッド４２は、例えば、ＩＣ５と基部９との接着強度の向上、ＩＣ５の放熱性の向上及び／又はノイズ低減に寄与する。ダイパッド４２の材料は任意である。例えば、ダイパッド４２の材料は、基部９が有する他の導体層の材料（例えばＩＣ用パッド３５の材料（後述））と同じであってもよいし、異なっていてもよい。いずれにせよ、後述するＩＣ用パッド３５の材料の説明はダイパッド４２の材料に援用されてよい。なお、ダイパッド４２は、設けられなくても構わない。 (die pad)
The die pad 42 is a member to which the lower surface of the IC 5 is adhered on its upper surface. The die pad 42 contributes, for example, to improving the adhesive strength between the IC 5 and the base 9, improving the heat dissipation of the IC 5, and/or reducing noise. Any material can be used for the die pad 42 . For example, the material of the die pad 42 may be the same as or different from the material of other conductor layers of the base 9 (for example, the material of the IC pads 35 (described later)). In any case, the description of the material of the IC pad 35 to be described later may be applied to the material of the die pad 42 . Note that the die pad 42 may not be provided.
（蓋）
　蓋１１は、例えば、板状の部材である。蓋１１は、例えば、下面に、枠状に形成された第２接合用金属層４７を有している。第１接合用金属層３９及び第２接合用金属層４７がシーム溶接等によって接合されることにより、パッケージ７の内部は密閉される。すなわち、密閉空間Ｓ１が構成される。なお、蓋１１の接合は、シーム溶接以外の方法によって実現されても構わない。 (lid)
The lid 11 is, for example, a plate-like member. The lid 11 has, for example, a frame-shaped second bonding metal layer 47 on its lower surface. The inside of the package 7 is hermetically sealed by joining the first joining metal layer 39 and the second joining metal layer 47 by seam welding or the like. That is, a closed space S1 is formed. Note that the lid 11 may be joined by a method other than seam welding.
　蓋本体（蓋１１のうちの第２接合用金属層４７を除く部分）の形状、材料及び寸法は任意である。例えば、蓋本体の平面視における外縁の形状及び寸法は、概ね、基部９の上面の平面視における外縁の形状及び寸法と同様である。蓋本体の材料は、例えば、金属とされてよい。金属は、例えば、鉄、ニッケル若しくはコバルト、又はこれらの少なくとも１つを主成分とする合金とされてよい。 The shape, material and dimensions of the lid body (the portion of the lid 11 excluding the second bonding metal layer 47) are arbitrary. For example, the shape and size of the outer edge of the lid body in plan view are generally the same as the shape and size of the outer edge of the upper surface of the base 9 in plan view. The material of the lid body may be, for example, metal. The metal may be, for example, iron, nickel or cobalt, or an alloy based on at least one of these.
　第２接合用金属層４７の形状、材料及び寸法は任意である。例えば、平面視において、第２接合用金属層４７の形状及び寸法は、第１接合用金属層３９の形状及び寸法と概ね同様とされている。第２接合用金属層４７は、例えば、銀ロウ又は金錫によって構成されている。第２接合用金属層４７の厚さは、例えば、１０μｍ以上４０μｍである。金錫の場合、Ａｕの質量％は、例えば、７５質量％以上８５質量％以下とされてよい。 The shape, material and dimensions of the second bonding metal layer 47 are arbitrary. For example, in plan view, the shape and dimensions of the second bonding metal layer 47 are substantially the same as the shape and dimensions of the first bonding metal layer 39 . The second bonding metal layer 47 is made of, for example, silver solder or gold tin. The thickness of the second bonding metal layer 47 is, for example, 10 μm or more and 40 μm. In the case of gold and tin, the mass % of Au may be, for example, 75 mass % or more and 85 mass % or less.
（導電性接着剤）
　導電性接着剤４１は、特に図示しないが、絶縁性のバインダーと、当該バインダーに分散されている導電性フィラー（導電性粉末）とを有している。バインダーは、有機材料（例えば樹脂）であってもよいし、無機材料であってもよい。樹脂は、例えば、シリコーン樹脂、エポキシ樹脂、ポリイミド樹脂又はビスマレイミド樹脂とされてよい。導電性フィラーの材料は、例えば、金属とされてよい。金属は、例えば、アルミニウム、モリブデン、タングステン、白金、パラジウム、銀、チタン、ニッケル若しくは鉄、又はこれらの１つ以上を主成分とする合金とされてよい。 (Conductive adhesive)
Although not shown, the conductive adhesive 41 has an insulating binder and conductive filler (conductive powder) dispersed in the binder. The binder may be an organic material (eg, resin) or an inorganic material. The resin may be, for example, a silicone resin, an epoxy resin, a polyimide resin, or a bismaleimide resin. The material of the conductive filler may be metal, for example. The metal may be, for example, aluminum, molybdenum, tungsten, platinum, palladium, silver, titanium, nickel or iron, or an alloy based on one or more of these.
　導電性接着剤４１は、引出電極１７（より詳細にはその端子部）と、水晶用パッド３３との間に介在して両者を接合する。導電性接着剤４１は、例えば、少なくとも引出電極１７のうち－Ｄ３側に面している領域に接合されている。この他、導電性接着剤４１は、引出電極１７のうち、－Ｄ１側に面している領域、及び／又は－Ｄ２側若しくは＋Ｄ２側に面している領域に接合されていてもよい。 The conductive adhesive 41 is interposed between the extraction electrode 17 (more specifically, its terminal portion) and the crystal pad 33 to join them together. The conductive adhesive 41 is bonded, for example, to at least the area of the extraction electrode 17 facing the -D3 side. In addition, the conductive adhesive 41 may be bonded to the area facing the -D1 side and/or the area facing the -D2 side or the +D2 side of the extraction electrode 17 .
（接着剤及びボンディングワイヤ）
　接着剤４３は、ＩＣ５の下面と第３凹部２９の底面（第１面９ａ、ダイパッド４２）との間に介在して両者を接合する。接着剤４３は、例えば、ＩＣ５の下面の概ね全面に亘って広がっている。 (adhesive and bonding wire)
The adhesive 43 is interposed between the bottom surface of the IC 5 and the bottom surface of the third recess 29 (the first surface 9a and the die pad 42) to bond them together. The adhesive 43 spreads over substantially the entire lower surface of the IC 5, for example.
　接着剤４３の材料は任意である。例えば、接着剤４３の材料は、絶縁材料であってもよいし、導電材料であってもよい。絶縁材料は、有機材料であってもよいし、無機材料であってもよい。有機絶縁材料は、例えば、樹脂であり、より詳細には、例えば、加熱されることによって硬化する熱硬化性樹脂とされてよい。当該樹脂は、導電性接着剤４１を構成する樹脂と同一のものであってもよいし、異なるものであってもよい。導電材料は、例えば、適宜な金属とされてよい。導電材料がはんだの場合においては、後述するアニール処理等によって溶融しないように、融点が比較的高いものが選択されてよい。 The material of the adhesive 43 is arbitrary. For example, the material of the adhesive 43 may be an insulating material or a conductive material. The insulating material may be an organic material or an inorganic material. The organic insulating material is, for example, a resin, and more specifically, may be a thermosetting resin that hardens when heated. The resin may be the same as the resin forming the conductive adhesive 41, or may be different. The conductive material may be, for example, a suitable metal. When the conductive material is solder, a material with a relatively high melting point may be selected so as not to be melted by an annealing treatment or the like, which will be described later.
　各ボンディングワイヤ４５は、一端がＩＣ端子２１に接合されているとともに、他端がＩＣ用パッド３５に接合されている。これにより、ＩＣ５は、パッケージ７（基部９）と電気的に接続されている。なお、以下の説明においては、図４（後述）も適宜に参照されたい。 Each bonding wire 45 has one end joined to the IC terminal 21 and the other end joined to the IC pad 35 . Thereby, the IC 5 is electrically connected to the package 7 (base portion 9). In the following description, please also refer to FIG. 4 (described later) as appropriate.
　ボンディングワイヤ４５は、いわゆるボールボンディングによって形成されるものであってもよいし（図示の例）、ウェッジボンディングによって形成されるものであってもよい。換言すれば、ボンディングワイヤ４５の一端は、他の部分の径よりも大きい径を有するボール状（接合後はドーム状又は円盤状。以下、拡径部ということがある。）であってもよいし（図示の例）、そのような形状でなくてもよい。ボールボンディングが行われる場合、拡径部は、ＩＣ端子２１に位置してもよいし（図示の例）、ＩＣ用パッド３５に位置してもよい。特に図示しないが、例えば、２ｎｄボンドがなされるパッド（図示の例ではＩＣ用パッド３５）上に、１ｓｔボンドの前にボンダによってバンプを形成することによって、ボンディングワイヤ４５の両端に拡径部が構成されてもよい。 The bonding wires 45 may be formed by so-called ball bonding (the example shown in the figure) or may be formed by wedge bonding. In other words, one end of the bonding wire 45 may be ball-shaped (dome-shaped or disk-shaped after bonding; hereinafter sometimes referred to as an enlarged diameter portion) having a diameter larger than that of the other portion. (illustrated example), but need not be such a shape. If ball bonding is used, the enlarged diameter portion may be located at the IC terminal 21 (example shown) or at the IC pad 35 . Although not shown in particular, for example, by forming bumps with a bonder on the pad (IC pad 35 in the illustrated example) to which the second bond is made, before the first bond, enlarged diameter portions are formed at both ends of the bonding wire 45. may be configured.
　ボンディングワイヤ４５の具体的な形状及び寸法は任意である。例えば、ボンディングワイヤ４５は、両端を除いて概ね一定の断面で延びている。断面形状は、例えば、円形である。また、ボンディングワイヤ４５は、上方（＋Ｄ３側）に凸となる曲線状（ループ状）に延びている。平面視において、ボンディングワイヤ４５は直線状に延びている。その延びる方向は適宜に設定されてよい。別の観点では、互いに接続されるＩＣ端子２１及びＩＣ用パッド３５の相対位置は任意である。ボンディングワイヤの両端を除く部分の直径は、例えば、１０μｍ以上５０μｍ以下である。ボンディングワイヤ４５の拡径部の平面視における直径（接合後）は、例えば、７０μｍ以上１００μｍ以下である。 The specific shape and dimensions of the bonding wire 45 are arbitrary. For example, the bonding wire 45 extends with a generally constant cross-section except at both ends. The cross-sectional shape is, for example, circular. Further, the bonding wire 45 extends in a curved shape (loop shape) that is convex upward (+D3 side). In plan view, the bonding wire 45 extends linearly. The extending direction may be set appropriately. From another point of view, the relative positions of the IC terminals 21 and the IC pads 35 that are connected to each other are arbitrary. The diameter of the portion of the bonding wire excluding both ends is, for example, 10 μm or more and 50 μm or less. The diameter of the enlarged diameter portion of the bonding wire 45 in plan view (after bonding) is, for example, 70 μm or more and 100 μm or less.
（水晶素子及びＩＣ等の位置関係）
　既述のように、図示の例では、水晶素子３は、ＩＣ５を介して第１面９ａ（第３凹部２９の底面）と対向している。水晶素子３とＩＣ５とが重なる広さ等は任意である。例えば、以下のとおりである。なお、重なりに関する以下の説明において、「ＩＣ５」の語は、矛盾等が生じない限り、「第１面９ａ」に置換されてよい。 (Positional relationship between crystal element and IC, etc.)
As described above, in the illustrated example, the crystal element 3 faces the first surface 9a (bottom surface of the third recess 29) via the IC5. The width, etc., where the crystal element 3 and the IC 5 overlap is arbitrary. For example: In addition, in the following description of overlapping, the term "IC5" may be replaced with "first surface 9a" as long as there is no contradiction.
　水晶素子３の一部（図示の例では－Ｄ１側の一部）は、第１凹部２５の底面に対して重なって導電性接着剤４１によって上記底面に接合される。従って、水晶素子３は、残りの部分のうちの一部（図示の例）又は全部がＩＣ５に重なってよい。前者の場合において、重なる領域の水晶素子３における相対的な広さは任意である。例えば、重なる領域の面積が水晶素子３の面積に占める割合は、１／２未満であってもよいし（図示の例）、１／２以上であってもよい。また、重なる領域は、水晶素子３の薄い部分の一部（図示の例）又は全部を占めてよく、励振電極１５の一部（図示の例）又は全部を占めてよい。 A portion of the crystal element 3 (a portion on the -D1 side in the illustrated example) overlaps the bottom surface of the first concave portion 25 and is bonded to the bottom surface with a conductive adhesive 41 . Therefore, the crystal element 3 may partially (illustrated example) or all of the remaining portion overlap the IC 5 . In the former case, the relative extent of the overlapping regions in the crystal element 3 is arbitrary. For example, the ratio of the area of the overlapping region to the area of the crystal element 3 may be less than 1/2 (the example shown in the figure) or may be 1/2 or more. Moreover, the overlapping region may occupy a part (illustrated example) or the whole of the thin portion of the crystal element 3 and may occupy a part (illustrated example) or the whole of the excitation electrode 15 .
　また、ＩＣ５は、その一部又は全部が水晶素子３に重なってよい。前者の場合において、重なる領域のＩＣ５における相対的な広さは任意である。例えば、重なる領域の面積がＩＣ５の面積に占める割合は、１／２未満であってもよいし（図示の例）、１／２以上であってもよい。 Also, the IC 5 may partially or wholly overlap the crystal element 3 . In the former case, the relative width of the overlapping region at IC5 is arbitrary. For example, the ratio of the area of the overlapping region to the area of the IC 5 may be less than 1/2 (the example shown in the figure) or may be 1/2 or more.
　図示の例では、平面視において、水晶素子３の幾何中心のＤ２方向の位置と、ＩＣ５の幾何中心のＤ２方向の位置とは一致している。図示の例とは異なり、両者は互いにずれていてもよい。また、水晶素子３のＤ２方向の幅は、ＩＣ５のＤ２方向の幅よりも小さい。そして、前者の幅は、後者の幅に収まっている。図示の例とは異なり、前者の幅は後者の幅よりも大きくされてもよいし、これにより、又は幾何中心のずれにより、前者の幅が後者の幅からはみ出していてもよい。 In the illustrated example, in plan view, the position of the geometric center of the crystal element 3 in the D2 direction and the position of the geometric center of the IC 5 in the D2 direction match. Unlike the illustrated example, both may be offset from each other. Also, the width of the crystal element 3 in the D2 direction is smaller than the width of the IC 5 in the D2 direction. The width of the former is within the width of the latter. Unlike the illustrated example, the width of the former may be greater than the width of the latter, or the width of the former may protrude from the width of the latter due to this or due to the displacement of the geometric center.
　水晶素子３は、少なくとも１つのＩＣ用パッド３５の少なくとも一部、少なくとも１つのボンディングワイヤ４５の少なくとも一部、及び／又は少なくとも１つのＩＣ端子２１の少なくとも一部に対して、重なっていてもよいし、これらの部材に対して全く重なっていなくてもよい。図示の例では、水晶素子３は、－Ｄ１側の２つのＩＣ用パッド３５の一部、当該ＩＣ用パッド３５に接続される２つのボンディングワイヤ４５の全部、及び当該２つのボンディングワイヤ４５に接続される２つのＩＣ端子２１の全部に対して重なっている。なお、本段落において、「水晶素子３」の語は、矛盾等が生じない限り、「水晶素子３の薄い部分」又は「励振電極１５」の語に置換されてよい。 The crystal element 3 may overlap at least a portion of at least one IC pad 35, at least a portion of at least one bonding wire 45, and/or at least a portion of at least one IC terminal 21. However, it does not have to overlap these members at all. In the illustrated example, the crystal element 3 is part of the two IC pads 35 on the -D1 side, all of the two bonding wires 45 connected to the IC pads 35, and connected to the two bonding wires 45. are overlapped for all of the two IC terminals 21 connected. In this paragraph, the term "crystal element 3" may be replaced with the term "thin portion of crystal element 3" or "excitation electrode 15" as long as there is no contradiction.
（接続部材の接合）
　図４は、図２の領域IVを拡大して示す断面図である。 (Joining connection members)
FIG. 4 is a cross-sectional view showing an enlarged region IV of FIG.
　ボンディングワイヤ４５（接続部材の一例）は、金（Ａｕ）によって構成されている。また、ＩＣ端子２１は、少なくとも表面（より厳密には上面（＋Ｄ３側の面））がＡｕによって構成されている。従って、ボンディングワイヤ４５及びＩＣ端子２１の接合は、Ａｕ同士の接合となっている。これにより、後に詳述するように、ボンディングワイヤ４５にボイド（さらにはクラック）が生じる蓋然性が低減される。 A bonding wire 45 (an example of a connection member) is made of gold (Au). At least the surface (more strictly, the upper surface (+D3 side surface)) of the IC terminal 21 is made of Au. Therefore, the bonding between the bonding wire 45 and the IC terminal 21 is a Au-to-Au bonding. This reduces the possibility of voids (and cracks) occurring in the bonding wires 45, as will be described in detail later.
　ボンディングワイヤ４５の接合に係る構成は、上記のようにボンディングワイヤ４５及びＩＣ端子２１の表面がＡｕによって構成される点を除いて、種々の態様とされてよく、例えば、公知の態様とされても構わない。もちろん、新規な態様が適用されてもよい。以下では、図示の例を中心に、ＩＣ端子２１の材料及びＩＣ用パッド３５の材料について説明する。 The structure related to the bonding of the bonding wire 45 may take various forms, for example, a known form, except that the surfaces of the bonding wire 45 and the IC terminal 21 are made of Au as described above. I don't mind. Of course, novel aspects may also be applied. The material of the IC terminal 21 and the material of the IC pad 35 will be described below, focusing on the illustrated example.
（ＩＣ端子の材料）
　ＩＣ端子２１は、例えば、４層の金属層から構成されている。具体的には、ＩＣ端子２１においては、ＩＣ５のチップ本体１９側から順に、互いに異なる材料からなる第１層５１、第２層５３、第３層５５及びＡｕ層５７が積層されている。Ａｕ層５７は、その名のとおり、Ａｕからなる層である。Ａｕ層５７がＩＣ端子２１の上面を構成していることによって、ＩＣ端子２１の上面はＡｕによって構成されている。 (Material of IC terminal)
The IC terminal 21 is composed of, for example, four metal layers. Specifically, in the IC terminal 21 , a first layer 51 , a second layer 53 , a third layer 55 and an Au layer 57 made of different materials are laminated in order from the chip body 19 side of the IC 5 . The Au layer 57 is, as its name suggests, a layer made of Au. Since the Au layer 57 forms the upper surface of the IC terminal 21, the upper surface of the IC terminal 21 is made of Au.
　なお、図４では、全ての層がチップ本体１９上に位置している。図示の例とは異なり、少なくともチップ本体１９側の一部の層は、Ｄ３方向において、チップ本体１９の上面（＋Ｄ３側の面）に対して、同じ位置又は下方に位置してもよい。例えば、第１層５１は、チップ本体１９が有している絶縁性の保護層よりも下方に位置し、保護層に形成された開口から露出する部分によってＩＣ端子２１を構成していてよい。 It should be noted that all layers are located on the chip body 19 in FIG. Unlike the illustrated example, at least some layers on the chip body 19 side may be located at the same position or below the top surface of the chip body 19 (+D3 side surface) in the D3 direction. For example, the first layer 51 may be located below the insulating protective layer of the chip body 19, and the IC terminal 21 may be formed by a portion exposed through an opening formed in the protective layer.
　また、図４では、各層の側面が露出している。図示の例とは異なり、少なくともチップ本体１９側の一部の層の側面は、チップ本体１９（例えば上述の保護層）によって覆われていてもよい。また、相対的に下方（－Ｄ３側）の層の側面は、相対的に上方（＋Ｄ３側）の層（例えばＡｕ層５７）によって覆われていてよい。なお、導体層において、側面の影響は限定的である。従って、導体層の説明では、上面と表面とを区別しないことがある。 Also, in FIG. 4, the side surface of each layer is exposed. Unlike the illustrated example, at least the side surfaces of some layers on the chip body 19 side may be covered with the chip body 19 (for example, the protective layer described above). Also, the side surface of the relatively lower (−D3 side) layer may be covered with the relatively upper (+D3 side) layer (for example, the Au layer 57). In addition, in the conductor layer, the influence of the side surface is limited. Therefore, the description of the conductor layer may not distinguish between the upper surface and the front surface.
　第１層５１、第２層５３及び第３層５５の材料は任意である。例えば、第１層５１は、アルミニウム又はアルミニウムを主成分とする合金からなる。第２層５３は、ニッケル又はニッケルを主成分とする合金からなる。第３層５５は、パラジウム又はパラジウムを主成分とする合金からなる。 The materials of the first layer 51, the second layer 53 and the third layer 55 are arbitrary. For example, the first layer 51 is made of aluminum or an alloy containing aluminum as a main component. The second layer 53 is made of nickel or an alloy containing nickel as a main component. The third layer 55 is made of palladium or a palladium-based alloy.
　ＩＣ端子２１を構成する各層の厚さは任意である。例えば、各層は、概略、一定の厚さで構成されている。ただし、各層は、外縁側において薄くなるなど、厚さが変化していても構わない。また、例えば、これらのいずれが他の層よりも厚くてもよい。例えば、第１層５１及び第２層５３は、いずれが他方よりも厚くてもよい。第３層５５及びＡｕ層５７は、例えば、第１層５１及び／又は第２層５３よりも薄くされてよい。第３層５５及びＡｕ層５７は、いずれが他方よりも厚くてもよい。各層の厚さは、例えば、０．０５μｍ以上１０μｍ以下とされてよい。 The thickness of each layer constituting the IC terminal 21 is arbitrary. For example, each layer generally has a constant thickness. However, each layer may have a different thickness, such as being thinner on the outer edge side. Also, for example, any of these layers may be thicker than the other layers. For example, one of the first layer 51 and the second layer 53 may be thicker than the other. The third layer 55 and the Au layer 57 may be thinner than the first layer 51 and/or the second layer 53, for example. Either the third layer 55 or the Au layer 57 may be thicker than the other. The thickness of each layer may be, for example, 0.05 μm or more and 10 μm or less.
　図示の例とは異なり、例えば、第２層５３及び／又は第３層５５が省略されてもよい。逆に、さらに他の層が追加されてもよい。また、第１層５１に代えて、貫通導体（層状でない導体）がチップ本体１９から露出し、その上に、他の層（第２層５３、第３層５５又はＡｕ層５７）が重なっていてもよい。第１層５１、第２層５３及び第３層５５の材料は、上述した材料以外とされてもよい。例えば、Ｗ、Ｃｕ、Ｔｉ若しくはＣｒ、又はこれらの少なくとも１つを主成分とする合金が用いられてもよい。 Unlike the illustrated example, for example, the second layer 53 and/or the third layer 55 may be omitted. Conversely, additional layers may be added. Further, instead of the first layer 51, a through conductor (non-layered conductor) is exposed from the chip body 19, and another layer (second layer 53, third layer 55 or Au layer 57) is superimposed thereon. may The materials of the first layer 51, the second layer 53 and the third layer 55 may be other than the materials described above. For example, W, Cu, Ti or Cr, or an alloy containing at least one of these as a main component may be used.
（ＩＣ用パッドの材料）
　ＩＣ用パッド３５は、例えば、２層の金属層から構成されている。具体的には、ＩＣ用パッド３５においては、基部９の基体２３側から順に、互いに異なる材料からなる下層５９及び上層６１が積層されている。なお、図４では、各層の側面が露出している。図示の例とは異なり、下層５９の側面は、上層６１によって覆われていてもよい。 (Material for IC pads)
The IC pad 35 is composed of, for example, two metal layers. Specifically, in the IC pad 35 , a lower layer 59 and an upper layer 61 made of different materials are laminated in order from the substrate 23 side of the base 9 . In addition, in FIG. 4, the side surface of each layer is exposed. In contrast to the illustrated example, the sides of lower layer 59 may be covered by upper layer 61 .
　下層５９及び上層６１の材料は任意である。例えば、下層５９の材料は、Ｎｉ、Ｗ、Ｃｕ若しくはＡｌ、又はこれらの少なくとも１つを主成分として含む合金とされてよい。上層６１の材料は、Ａｕ、Ａｇ若しくはＰｔ又はこれらの少なくとも１つを主成分とする合金とされてよい。 Materials for the lower layer 59 and the upper layer 61 are arbitrary. For example, the material of the lower layer 59 may be Ni, W, Cu, Al, or an alloy containing at least one of these as a main component. The material of the upper layer 61 may be Au, Ag, Pt, or an alloy containing at least one of these as a main component.
　上層６１がＡｕからなる場合、ＩＣ用パッド３５は、少なくとも表面（厳密には上面（＋Ｄ３側の面）がＡｕによって構成される。この場合、接続部材（ボンディングワイヤ４５）とＩＣ端子２１との接合と同様に、接続部材とＩＣ用パッド３５との接合も、Ａｕ同士の接合となる。 When the upper layer 61 is made of Au, at least the surface (strictly, the upper surface (+D3 side surface)) of the IC pad 35 is made of Au. Similar to the bonding, the bonding between the connection member and the IC pad 35 is also bonding between Au.
　図示の例とは異なり、ＩＣ用パッド３５は、１層の金属によって構成されていてもよいし、３層以上の金属によって構成されていてもよい。３層以上の金属によって構成される態様においては、上述したＩＣ端子２１の材料の説明がＩＣ用パッド３５の材料に援用されてよい。 Unlike the illustrated example, the IC pad 35 may be composed of one layer of metal, or may be composed of three or more layers of metal. In a mode composed of three or more layers of metal, the above description of the material of the IC terminal 21 may be applied to the material of the IC pad 35 .
　ＩＣ用パッド３５及びその各層の厚さ（本段落では次段落で述べる薄くなっている部分は考慮外とする。）は任意である。例えば、ＩＣ用パッド３５の厚さは、ＩＣ端子２１の厚さに対して、薄くてもよいし、同等でもよいし、厚くてもよい。ＩＣ用パッド３５の厚さは、例えば、１μｍ以上１０μｍ以下とされてよい。上層６１は、例えば、下層５９よりも薄くされてよい。下層５９の厚さは、例えば、１μｍ以上１０μｍ以下とされてよい。上層６１の厚さは、例えば、０．１μｍ以上２μｍ以下とされてよい。 The thickness of the IC pad 35 and its layers (thinned portions described in the next paragraph are excluded from consideration in this paragraph) are arbitrary. For example, the thickness of the IC pad 35 may be thinner than, equal to, or thicker than the thickness of the IC terminal 21 . The thickness of the IC pad 35 may be, for example, 1 μm or more and 10 μm or less. Top layer 61 may be thinner than bottom layer 59, for example. The thickness of the lower layer 59 may be, for example, 1 μm or more and 10 μm or less. The thickness of the upper layer 61 may be, for example, 0.1 μm or more and 2 μm or less.
（水晶素子における導体の材料）
　水晶素子３の導体層（励振電極１５及び引出電極１７）の材料は任意である。水晶素子３の導体層は、１層の金属層から構成されてもよいし、２層以上の金属層から構成されてもよい。 (Conductor material in crystal element)
The material of the conductor layer (the excitation electrode 15 and the extraction electrode 17) of the crystal element 3 is arbitrary. The conductor layer of the crystal element 3 may be composed of one metal layer, or may be composed of two or more metal layers.
　図示の例では、水晶素子３の導体層は、２層の金属層から構成されている。具体的には、水晶ブランク１３側から順に、互いに異なる材料からなる下地層６３及び主層６５が積層されている。なお、図４では、各層の側面が露出している。図示の例とは異なり、下地層６３の側面は、主層６５によって覆われていてもよい。 In the illustrated example, the conductor layer of the crystal element 3 is composed of two metal layers. Specifically, a base layer 63 and a main layer 65 made of different materials are laminated in order from the crystal blank 13 side. In addition, in FIG. 4, the side surface of each layer is exposed. Unlike the illustrated example, the side surface of the underlying layer 63 may be covered with the main layer 65 .
　下地層６３及び主層６５の材料は任意である。例えば、下地層６３の材料は、Ｎｉ若しくはＣｒ、又はこれらの少なくとも１つを主成分として含む合金とされてよい。主層６５の材料は、Ａｕ若しくはＡｇ、又はこれらの少なくとも１つを主成分とする合金とされてよい。 Any material can be used for the base layer 63 and the main layer 65 . For example, the material of the underlying layer 63 may be Ni, Cr, or an alloy containing at least one of these as a main component. The material of the main layer 65 may be Au, Ag, or an alloy containing at least one of these as a main component.
　主層６５がＡｕからなる場合、励振電極１５は、少なくとも表面（厳密には上面（＋Ｄ３側の励振電極１５の＋Ｄ３側の面及び－Ｄ３側の励振電極１５の－Ｄ３側の面））がＡｕによって構成される。この場合、励振電極１５の表面、接続部材（ボンディングワイヤ４５）及びＩＣ端子２１の表面は、同一の金属（Ａｕ）で構成されている。 When the main layer 65 is made of Au, at least the surface (strictly, the upper surface (+D3 side surface of the excitation electrode 15 on the +D3 side and -D3 side surface of the -D3 side excitation electrode 15)) of the excitation electrode 15 is composed of Au. In this case, the surface of the excitation electrode 15, the connection member (bonding wire 45) and the surface of the IC terminal 21 are made of the same metal (Au).
　水晶素子３の導体層（励振電極１５及び引出電極１７）の厚さは任意である。例えば、導体層の厚さは、１０００Å以上４０００Å以下とされてよい。主層６５は、上記の厚さの大部分（例えば８割以上又は９割以上）を占めてよい。下地層６３の厚さは、例えば、１０Å以上１００Å以下とされてよい。 The thickness of the conductor layer (excitation electrode 15 and extraction electrode 17) of the crystal element 3 is arbitrary. For example, the thickness of the conductor layer may be 1000 Å or more and 4000 Å or less. The main layer 65 may occupy most of the above thickness (eg, 80% or more or 90% or more). The thickness of the underlying layer 63 may be, for example, 10 Å or more and 100 Å or less.
（発振器の製造方法）
　発振器１の製造方法は、接続部材（ボンディングワイヤ４５）及びＩＣ端子２１の具体的な材料を除いて、種々の製造方法と同様とされてよく、例えば、公知の製造方法とされても構わない。以下では、発振器１の製造方法の手順のうち、パッケージングに係る手順の例を示す。 (Oscillator manufacturing method)
The manufacturing method of the oscillator 1 may be the same as various manufacturing methods except for the specific materials of the connection member (bonding wire 45) and the IC terminal 21, and may be, for example, a known manufacturing method. . An example of a procedure relating to packaging among the procedures of the method for manufacturing the oscillator 1 will be described below.
　図５は、発振器１の製造方法の手順の一例を示すフローチャートである。 FIG. 5 is a flow chart showing an example of the procedure of the method for manufacturing the oscillator 1. FIG.
　ステップＳＴ１では、ＩＣ５がパッケージ７の基部９に実装される。具体的には、例えば、まず、接着剤４３によってＩＣ５を基部９の第１面９ａ（ダイパッド４２）に接着する。次に、ボンディングワイヤ４５を形成して、ＩＣ端子２１とＩＣ用パッド３５とを電気的に接続する。 In step ST1, the IC 5 is mounted on the base 9 of the package 7. Specifically, for example, first, the IC 5 is adhered to the first surface 9 a (die pad 42 ) of the base 9 with the adhesive 43 . Next, a bonding wire 45 is formed to electrically connect the IC terminal 21 and the IC pad 35 .
　ボンディングワイヤ４５のＩＣ端子２１及びＩＣ用パッド３５に対する接合は、例えば、ボンディングワイヤ４５（並びに必要に応じてＩＣ端子２１及びＩＣ用パッド３５）に対して、超音波、圧力及び熱を付与することによって行われる。超音波が付与されることから、Ａｕ同士は、その融点よりも低い温度で接合される。加熱温度は、例えば、１００℃以上２００℃未満である。 Bonding of the bonding wire 45 to the IC terminal 21 and the IC pad 35 is performed by, for example, applying ultrasonic waves, pressure and heat to the bonding wire 45 (and the IC terminal 21 and the IC pad 35 as necessary). done by Since ultrasonic waves are applied, Au is joined at a temperature lower than its melting point. The heating temperature is, for example, 100° C. or more and less than 200° C.
　加熱方法は、種々の方法とされてよく、例えば、公知の方法とされて構わない。例えば、パッケージ７が載置される加熱テーブルの温度を上昇させることによって加熱がなされてよい。加熱温度としては、加熱される対象物を加熱する加熱手段（例えば加熱テーブル）の温度が参照されてよい。ただし、便宜上、加熱される対象物の温度と、加熱温度とを区別せずに表現することがある。本段落で述べた事項は、接続部材の接合のための加熱だけでなく、他のステップ（例えばＳＴ２、ＳＴ３、ＳＴ５及びＳＴ８）における加熱に援用されてよい。 The heating method may be various methods, for example, it may be a known method. For example, heating may be done by raising the temperature of a heating table on which the package 7 rests. As the heating temperature, the temperature of the heating means (for example, a heating table) that heats the object to be heated may be referred to. However, for the sake of convenience, the temperature of the object to be heated and the heating temperature are sometimes expressed without distinction. The matter described in this paragraph may be applied not only to heating for bonding connecting members, but also to heating in other steps (eg, ST2, ST3, ST5 and ST8).
　ステップＳＴ２では、水晶素子３がパッケージ７の基部９に実装される。具体的には、例えば、未硬化状態の導電性接着剤４１が水晶用パッド３３に供給される。次に、水晶素子３が導電性接着剤４１の上に載置される。その後、加熱処理によって導電性接着剤４１が硬化される。このときの加熱温度は、例えば、２００℃以上４００℃以下である。別の観点では、ここでの加熱温度は、例えば、接続部材（ボンディングワイヤ４５）を接合するときの加熱温度よりも高い。加熱時間は、例えば、１０分以上１時間以下である。 In step ST2, the crystal element 3 is mounted on the base 9 of the package 7. Specifically, for example, an uncured conductive adhesive 41 is supplied to the crystal pad 33 . Next, the crystal element 3 is placed on the conductive adhesive 41 . After that, the conductive adhesive 41 is cured by heat treatment. The heating temperature at this time is, for example, 200° C. or higher and 400° C. or lower. From another point of view, the heating temperature here is, for example, higher than the heating temperature when bonding the connection member (bonding wire 45). The heating time is, for example, 10 minutes or more and 1 hour or less.
　なお、導電性接着剤４１の熱硬化性樹脂の種類がシリコーン樹脂である態様の加熱温度は、導電性接着剤４１の熱硬化性樹脂の種類がエポキシ樹脂である態様の加熱温度よりも高くなりやすい。例えば、前者は、３５０℃程度であり、後者は、２００℃程度である。 Note that the heating temperature for the embodiment in which the type of thermosetting resin of the conductive adhesive 41 is a silicone resin is higher than the heating temperature in the embodiment in which the type of the thermosetting resin for the conductive adhesive 41 is an epoxy resin. Cheap. For example, the former is about 350°C and the latter is about 200°C.
　ステップＳＴ３では、加熱処理（ステップＳＴ２の導電性接着剤４１の硬化のための加熱処理とは別の加熱処理）が行われる。この加熱処理によって、例えば、導電性接着剤４１の残留応力の低減（アニール処理）、及び／又は導電性接着剤４１からの脱ガスが行われる。このときの加熱温度は、例えば、２００℃以上４００℃以下である。別の観点では、ここでの加熱温度は、例えば、接続部材（ボンディングワイヤ４５）を接合するときの加熱温度よりも高い。加熱時間は、例えば、１時間以上５時間以下である。この加熱処理は、例えば、真空雰囲気下で行われてよい。 In step ST3, heat treatment (a heat treatment different from the heat treatment for curing the conductive adhesive 41 in step ST2) is performed. By this heat treatment, for example, the residual stress of the conductive adhesive 41 is reduced (annealing treatment) and/or the conductive adhesive 41 is degassed. The heating temperature at this time is, for example, 200° C. or higher and 400° C. or lower. From another point of view, the heating temperature here is, for example, higher than the heating temperature when bonding the connection member (bonding wire 45). The heating time is, for example, 1 hour or more and 5 hours or less. This heat treatment may be performed, for example, under a vacuum atmosphere.
　ステップＳＴ４では、水晶素子３の周波数の調整が行われる。具体的には、例えば、水晶素子３に電気的に接続されている基部９のパッドを介して水晶素子３を励振してその周波数特性を計測し、その計測結果に応じて、励振電極１５の質量を増加及び／又は減少させる。 In step ST4, the frequency of the crystal element 3 is adjusted. Specifically, for example, the crystal element 3 is excited through the pads of the base portion 9 electrically connected to the crystal element 3 to measure the frequency characteristics of the crystal element 3, and depending on the measurement result, the excitation electrode 15 is measured. Increase and/or decrease mass.
　ステップＳＴ５では、加熱処理が行われる。ステップＳＴ３の説明は、本ステップに援用されてよい。 In step ST5, heat treatment is performed. The description of step ST3 may be incorporated into this step.
　ステップＳＴ６では、水晶素子３の周波数の調整が行われる。ステップＳＴ４の説明は、本ステップに援用されてよい。 At step ST6, the frequency of the crystal element 3 is adjusted. The description of step ST4 may be incorporated into this step.
　ステップＳＴ７では、蓋１１の長辺が基部９の上面に対してシーム溶接によって接合される。 In step ST7, the long sides of the lid 11 are joined to the upper surface of the base 9 by seam welding.
　ステップＳＴ８では、加熱処理が行われる。ステップＳＴ３の説明は、概ね、本ステップに援用されてよい。ただし、加熱時間は、ステップＳＴ３における加熱時間以下とされてよく、例えば、１０分以上１時間以下である。 In step ST8, heat treatment is performed. The description of step ST3 may generally be used for this step. However, the heating time may be equal to or less than the heating time in step ST3, and is, for example, 10 minutes or more and 1 hour or less.
　ステップＳＴ９では、蓋１１の短辺が基部９の上面に対してシーム溶接によって接合される。これにより、基部９の凹部が密閉され、密閉空間Ｓ１が構成される。なお、このとき、適宜な雰囲気下でシーム溶接が行われることによって、密閉空間Ｓ１は、真空状態又は適宜なガス（例えば窒素）が封入された状態となる。 In step ST9, the short sides of the lid 11 are joined to the upper surface of the base 9 by seam welding. As a result, the concave portion of the base portion 9 is sealed to form a sealed space S1. At this time, seam welding is performed in an appropriate atmosphere, so that the closed space S1 is in a vacuum state or in a state in which an appropriate gas (for example, nitrogen) is enclosed.
（第１実施形態のまとめ）
　以上のとおり、第１実施形態に係る水晶発振器１は、水晶素子３と、ＩＣ５と、パッケージ７と、接続部材（ボンディングワイヤ４５）と、を有している。ＩＣ５は、ＩＣ端子２１を有している。パッケージ７は、水晶素子３及びＩＣ５を保持している。ボンディングワイヤ４５は、金（Ａｕ）からなり、ＩＣ端子２１とパッケージ７とに接合されている。ＩＣ端子２１は、当該ＩＣ端子２１の表面を構成しており、ボンディングワイヤ４５が接合されている、第１Ａｕ層（Ａｕ層５７）を有している。 (Summary of the first embodiment)
As described above, the crystal oscillator 1 according to the first embodiment has the crystal element 3, the IC 5, the package 7, and the connecting members (bonding wires 45). IC 5 has an IC terminal 21 . A package 7 holds the crystal element 3 and the IC 5 . The bonding wires 45 are made of gold (Au) and are joined to the IC terminals 21 and the package 7 . The IC terminal 21 has a first Au layer (Au layer 57) that constitutes the surface of the IC terminal 21 and to which the bonding wire 45 is bonded.
　従って、例えば、ボンディングワイヤ４５にボイド及び／又はクラックが発生する蓋然性を低減でき、ひいては、発振器１の特性低下を低減できる。具体的には、例えば、以下のとおりである。 Therefore, for example, the probability of voids and/or cracks occurring in the bonding wires 45 can be reduced, and the deterioration of the characteristics of the oscillator 1 can be reduced. Specifically, for example, it is as follows.
　図６は、比較例に係るボンディングワイヤ４５とＩＣ端子（第１層５１）との接合構造を示す図であり、図４の一部に相当している。 FIG. 6 is a diagram showing a bonding structure between bonding wires 45 and IC terminals (first layer 51) according to a comparative example, and corresponds to part of FIG.
　この比較例では、ＩＣ端子は、実施形態の第１層５１のみで構成されている。第１層５１の材料は、例えば、実施形態の説明で述べたように、Ａｌである。出願人の鋭意検討の結果、このような接合構造においては、ボンディングワイヤ４５のうちＩＣ端子の近くの部分に複数のボイドＶ１及び／又は１以上のクラックＣ１が形成されることがあることが分かった。なお、ボイドＶ１の直径及びクラックＣ１の幅は、例えば、０．１μｍ以上３μｍ以下である。 In this comparative example, the IC terminal is composed only of the first layer 51 of the embodiment. The material of the first layer 51 is, for example, Al as described in the description of the embodiment. As a result of diligent investigation by the applicant, it has been found that in such a bonding structure, a plurality of voids V1 and/or one or more cracks C1 may be formed in a portion of the bonding wire 45 near the IC terminal. rice field. The diameter of the void V1 and the width of the crack C1 are, for example, 0.1 μm or more and 3 μm or less.
　しかし、本実施形態のように、ＩＣ端子２１の少なくとも表面をＡｕにすることによって、ボイドＶ１及びクラックＣ１を低減することができる。出願人は、比較例及び実施例に係る試作品について図６のような断面写真を撮影し、上記の効果を確認している。より詳細には、実施例では、比較例で見られたボイドＶ１及びクラックＣ１は確認されなかった。 However, by forming at least the surface of the IC terminal 21 with Au as in the present embodiment, voids V1 and cracks C1 can be reduced. The applicant has confirmed the above effects by taking cross-sectional photographs as shown in FIG. 6 for prototypes according to comparative examples and examples. More specifically, voids V1 and cracks C1 seen in Comparative Examples were not observed in Examples.
　そして、ボイドＶ１及びクラックＣ１が低減されることによって、これらに起因する特性低下を低減できる。出願人は、比較例及び実施例に係る試作品の特性を調べることによって、当該効果を確認している。これについては、後に例を示す。 Further, by reducing voids V1 and cracks C1, it is possible to reduce deterioration in characteristics caused by them. The applicant confirmed this effect by investigating the characteristics of prototypes according to comparative examples and examples. An example of this will be given later.
　本実施形態における接合構造によって、ボイドＶ１及びクラックＣ１を低減できる理由としては、例えば、以下のものが挙げられる。 Reasons why the voids V1 and cracks C1 can be reduced by the bonding structure of the present embodiment include, for example, the following.
　ボンディングワイヤ４５及びＩＣ端子には、発振器の製造過程、発振器をデバイスに組み込む過程（例えばリフロー工程）、上記デバイスの使用過程において、比較的高い熱が加えられることがある。例えば、図５を参照して説明したように、発振器の製造過程においては、ボンディングワイヤ４５は、その接合（ステップＳＴ１）の後、２００℃以上又は３００℃以上の熱に晒される（ステップＳＴ２、ＳＴ３、ＳＴ５及びＳＴ８）。 Relatively high heat may be applied to the bonding wires 45 and IC terminals during the manufacturing process of the oscillator, the process of incorporating the oscillator into the device (for example, the reflow process), and the process of using the device. For example, as described with reference to FIG. 5, in the manufacturing process of the oscillator, the bonding wire 45 is exposed to heat of 200° C. or higher or 300° C. or higher after bonding (step ST1) (step ST2, ST3, ST5 and ST8).
　比較例においては、ボンディングワイヤ４５（Ａｕ）とＩＣ端子（Ａｌ）とは、上記のように高熱に晒されることによって相互に拡散する。すなわち、ＡｕとＡｌとの合金層が成長する。このとき、複数種類の合金が成長する。より具体的には、例えば、ＡｕＡｌ２（９ｐｐｍ／℃）、ＡｕＡｌ（１２ｐｐｍ／℃）、Ａｕ２Ａｌ（１３ｐｐｍ／℃）、Ａｕ５Ａｌ２（１４ｐｐｍ／℃）及びＡｕ４Ａｌ（１２ｐｐｍ／℃）が形成される。上記の組成式の後の括弧内に示した数値は、各合金の線膨張係数である。種々の合金は、互いに線膨張係数が異なっている。合金層の成長後、比較例に係る発振器がその使用過程等において温度サイクルに晒されると、線膨張係数が互いに異なる合金の間に熱膨張差が生じ、ボイドＶ１及びクラックＣ１が発生する。 In the comparative example, the bonding wire 45 (Au) and the IC terminal (Al) are mutually diffused by exposure to high heat as described above. That is, an alloy layer of Au and Al grows. At this time, multiple kinds of alloys grow. More specifically, for example, AuAl 2 (9 ppm/° C.), AuAl (12 ppm/° C.), Au 2 Al (13 ppm/° C.), Au 5 Al 2 (14 ppm/° C.) and Au 4 Al (12 ppm/° C.) is formed. The numerical values shown in parentheses after the above compositional formulas are the linear expansion coefficients of the respective alloys. Various alloys have different coefficients of linear expansion. After the growth of the alloy layer, if the oscillator according to the comparative example is exposed to temperature cycles during its use, etc., a difference in thermal expansion occurs between the alloys having different coefficients of linear expansion, causing voids V1 and cracks C1.
　一方、実施形態に係る発振器１では、ボンディングワイヤ４５とＩＣ端子２１との接合は、Ａｕ同士の接合となっている。従って、これらが高熱に晒されても、両者の間の合金層の成長は低減され、ひいては、線膨張係数が互いに異なる複数の合金層の成長も低減される。その結果、発振器１が温度サイクルに晒されても、ボイドＶ１及びクラックＣ１が発生しにくい。 On the other hand, in the oscillator 1 according to the embodiment, the bonding between the bonding wire 45 and the IC terminal 21 is Au-to-Au bonding. Therefore, even if they are exposed to high heat, the growth of an alloy layer between them is reduced, and the growth of a plurality of alloy layers having different coefficients of linear expansion is also reduced. As a result, voids V1 and cracks C1 are less likely to occur even when the oscillator 1 is exposed to temperature cycles.
　実施形態に係る発振器１において、ＩＣ端子２１は、第１層５１、第２層５３及び第３層５５を有してよい。第１層５１は、アルミニウム又はアルミニウムを主成分とする合金から構成されてよい。第２層５３は、ニッケル又はニッケルを主成分とする合金から構成されてよく、また、前記第１層に対してＡｕ層５７の側に重なってよい。第３層５５は、パラジウム又はパラジウムを主成分とする合金から構成されてよく、また、第２層に対してＡｕ層５７の側に重なってよい。Ａｕ層５７は、第３層に重なってよい。 In the oscillator 1 according to the embodiment, the IC terminal 21 may have the first layer 51 , the second layer 53 and the third layer 55 . The first layer 51 may be made of aluminum or an alloy containing aluminum as a main component. The second layer 53 may be made of nickel or a nickel-based alloy, and may overlap the first layer on the Au layer 57 side. The third layer 55 may be composed of palladium or a palladium-based alloy, and may overlap the Au layer 57 side with respect to the second layer. Au layer 57 may overlay the third layer.
　この場合、例えば、Ａｕ層５７と第１層５１（Ａｌ）との間で、比較例におけるボンディングワイヤ４５（Ａｕ）とＩＣ端子（Ａｌ）との間において生じる上記の現象と類似した現象が生じる蓋然性が低減される。具体的には、例えば、第３層５５（Ｐｄ）によって、Ａｕ層５７のＩＣ端子２１側への拡散が低減される。また、第２層５３（Ｎｉ）によって、例えば、第１層５１と第３層５５との接合強度が向上する。 In this case, for example, between the Au layer 57 and the first layer 51 (Al), a phenomenon similar to the above phenomenon occurring between the bonding wire 45 (Au) and the IC terminal (Al) in the comparative example occurs. Probability is reduced. Specifically, for example, diffusion of the Au layer 57 to the IC terminal 21 side is reduced by the third layer 55 (Pd). Also, the bonding strength between the first layer 51 and the third layer 55 is improved by the second layer 53 (Ni), for example.
　パッケージ７は、基部９と、蓋１１と、を有してよい。基部９は、第１面９ａを有してよい。蓋１１は、第１面９ａ上に密閉空間Ｓ１が構成されるように基部９に固定されてよい。ＩＣ５は、第１面９ａに固定されて密閉空間Ｓ１に収容されていてよい。水晶素子３は、ＩＣ５を介して第１面９ａと対向する位置にて密閉空間Ｓ１に収容されてよく、かつ導電性フィラーが分散されている樹脂からなる導電性接着剤４１によって基部９に接合されていてよい。 The package 7 may have a base 9 and a lid 11 . The base 9 may have a first surface 9a. The lid 11 may be fixed to the base 9 such that the closed space S1 is formed on the first surface 9a. The IC 5 may be fixed to the first surface 9a and accommodated in the sealed space S1. The crystal element 3 may be accommodated in the sealed space S1 at a position facing the first surface 9a via the IC 5, and is bonded to the base 9 with a conductive adhesive 41 made of a resin in which conductive filler is dispersed. It can be.
　この場合、例えば、上述したボイドＶ１及びクラックＣ１の発生が低減される効果が特に有効である。その理由は、以下のとおりである。上記のような構造においては、水晶素子３を導電性接着剤４１によって基部９に接合する前に、ＩＣ５を基部９に実装する必要がある。その結果、ボンディングワイヤ４５及びＩＣ端子２１は、導電性接着剤４１のアニール処理及び／又は脱ガスのための熱に晒されることになる。従って、既述の比較例が上記のような構造を有している場合においては、ボンディングワイヤ４５とＩＣ端子（第１層５１）との間で種々の合金層が成長しやすく、ひいては、ボイドＶ１及びクラックＣ１が発生する蓋然性が特に高くなる。しかし、本実施形態では、そのような不都合は低減される。 In this case, for example, the effect of reducing the occurrence of voids V1 and cracks C1 described above is particularly effective. The reason is as follows. In the structure as described above, it is necessary to mount the IC 5 on the base portion 9 before bonding the crystal element 3 to the base portion 9 with the conductive adhesive 41 . As a result, the bonding wires 45 and the IC terminals 21 are exposed to heat for annealing and/or degassing the conductive adhesive 41 . Therefore, in the case where the aforementioned comparative example has the structure as described above, various alloy layers tend to grow between the bonding wire 45 and the IC terminal (the first layer 51), which in turn causes voids. The probability of occurrence of V1 and crack C1 is particularly high. However, in this embodiment, such inconvenience is reduced.
　水晶素子３は、水晶ブランク１３と、水晶ブランク１３に重なっている励振電極１５と、を有してよい。水晶ブランク１３の励振電極１５が重なっている部分の厚さは、５μｍ以上３０μｍ以下とされてよい。 The crystal element 3 may have a crystal blank 13 and an excitation electrode 15 overlapping the crystal blank 13 . The thickness of the portion of the crystal blank 13 where the excitation electrode 15 overlaps may be 5 μm or more and 30 μm or less.
　この場合、例えば、上述したボイドＶ１及びクラックＣ１の発生が低減される効果が特に有効である。具体的には、例えば、以下のとおりである。上記のように水晶ブランク１３が比較的薄い場合においては、例えば、導電性接着剤４１から発生して水晶素子３に付着するガスの付着量が、水晶素子３の励振領域における質量及び／又は体積に対して大きくなる。ひいては、ガスの付着が水晶素子３の特性に及ぼす影響が大きくなる。従って、導電性接着剤４１の脱ガスのための加熱が入念に行われることになる。その結果、ボンディングワイヤ４５にボイドＶ１及びクラックＣ１が生じる蓋然性が特に高くなる。しかし、本実施形態では、そのような不都合は低減される。 In this case, for example, the effect of reducing the occurrence of voids V1 and cracks C1 described above is particularly effective. Specifically, for example, it is as follows. When the crystal blank 13 is relatively thin as described above, for example, the adhesion amount of the gas generated from the conductive adhesive 41 and adhering to the crystal element 3 increases the mass and/or volume of the excitation region of the crystal element 3. increases relative to As a result, the effect of gas adhesion on the characteristics of the crystal element 3 increases. Therefore, heating for degassing the conductive adhesive 41 is carefully performed. As a result, the probability of voids V1 and cracks C1 occurring in the bonding wires 45 is particularly high. However, in this embodiment, such inconvenience is reduced.
　パッケージ７は、接続部材（ボンディングワイヤ４５）が接合されているパッド（ＩＣ用パッド３５）を有してよい。ＩＣ用パッド３５は、第２Ａｕ層（上層６１）を有してよい。上層６１は、ＩＣ用パッド３５の表面を構成しており、ボンディングワイヤ４５が接合されてよい。 The package 7 may have pads (IC pads 35) to which connection members (bonding wires 45) are bonded. The IC pad 35 may have a second Au layer (upper layer 61). The upper layer 61 constitutes the surface of the IC pad 35 and may be bonded with the bonding wire 45 .
　この場合、例えば、ボンディングワイヤ４５は、ＩＣ端子２１だけでなく、ＩＣ用パッド３５に対しても、Ａｕ同士の接合がなされる。従って、ＩＣ端子２１側と同様に、ボンディングワイヤ４５にボイドＶ１及びクラックＣ１が発生する蓋然性が低減される。 In this case, for example, bonding wires 45 are Au-to-Au bonding not only to IC terminals 21 but also to IC pads 35 . Therefore, as with the IC terminal 21 side, the probability of voids V1 and cracks C1 occurring in the bonding wires 45 is reduced.
　水晶素子３及びＩＣ５は、同一の密閉空間Ｓ１に収容されてよい。水晶素子３の励振電極１５は、当該励振電極１５の表面を構成している第３Ａｕ層（主層６５）を有してよい。 The crystal element 3 and IC 5 may be accommodated in the same closed space S1. The excitation electrode 15 of the crystal element 3 may have a third Au layer (main layer 65 ) forming the surface of the excitation electrode 15 .
　この場合、接続部材（ボンディングワイヤ４５）、ＩＣ端子２１の表面及び励振電極１５の表面が共にＡｕによって構成されていることになる。その結果、例えば、製造過程又は完成後にパッケージ７内に存在する何らかの物質がＡｕに及ぼす影響（溶解及び／又は還元等）が、これらの部材に分散されやすい。上記物質が１つの部材に対してのみ影響を及ぼし、ひいては、当該１つの部材の特性変化が大きくなる場合に比較すれば、発振器１全体としての特性変化が抑制される。 In this case, the connection member (bonding wire 45), the surface of the IC terminal 21, and the surface of the excitation electrode 15 are all made of Au. As a result, for example, the effects (dissolution and/or reduction, etc.) of any material present in the package 7 during the manufacturing process or after completion on the Au are likely to be distributed to these members. The change in the characteristics of the oscillator 1 as a whole is suppressed compared to the case where the substance affects only one member, and thus the change in the characteristics of the one member becomes large.
　第１実施形態に係る水晶発振器１の製造方法は、上記のような、Ａｕからなる接続部材（ボンディングワイヤ４５）と、ＩＣ端子２１のＡｕ層５７とが接合される構成の発振器１を製造する。従って、上述した種々の効果が奏される。 The method of manufacturing the crystal oscillator 1 according to the first embodiment manufactures the oscillator 1 configured such that the connecting member (bonding wire 45) made of Au and the Au layer 57 of the IC terminal 21 are bonded as described above. . Therefore, the various effects described above are achieved.
　発振器１の製造方法は、接合ステップ（ステップＳＴ１を参照）と、１つ以上の加熱ステップ（ステップＳＴ２、ＳＴ３、ＳＴ５及びＳＴ８を参照）とを有している。接合ステップでは、第１Ａｕ層（Ａｕ層５７）とパッケージ７の基部９とに接続部材（ボンディングワイヤ４５）が接合される。加熱ステップでは、接合ステップの後、接合ステップにおけるボンディングワイヤ４５の温度（既述のようにボンディングワイヤ４５を加熱する加熱手段の温度であってよい。）よりも高い温度にボンディングワイヤ４５が晒される。 The manufacturing method of the oscillator 1 includes a bonding step (see step ST1) and one or more heating steps (see steps ST2, ST3, ST5 and ST8). In the bonding step, the connection member (bonding wire 45 ) is bonded to the first Au layer (Au layer 57 ) and the base 9 of the package 7 . In the heating step, after the bonding step, the bonding wires 45 are exposed to a temperature higher than the temperature of the bonding wires 45 during the bonding step (which may be the temperature of the heating means for heating the bonding wires 45 as described above). .
　この場合、例えば、ボンディングワイヤ４５は、接合後に、接合時の温度よりも高い温度に晒されるから、既述のように合金層の成長に起因して、ボイドＶ１及びクラックＣ１が発生しやすい。裏を返せば、本実施形態における、Ａｕ同士の接合によってボイドＶ１及びクラックＣ１の発生を低減する効果が有効に奏される。なお、加熱ステップにおいて、ボンディングワイヤが所定の温度に晒されるというとき、ボンディングワイヤ４５の温度は、必ずしもその加熱ステップにおいて用いられている加熱手段の温度に達していなくてもよい。 In this case, for example, the bonding wire 45 is exposed to a temperature higher than the temperature at the time of bonding after bonding, so voids V1 and cracks C1 are likely to occur due to the growth of the alloy layer as described above. In other words, the effect of reducing the occurrence of voids V1 and cracks C1 is effectively exhibited by the bonding between Au layers in this embodiment. When it is said that the bonding wires are exposed to a predetermined temperature in the heating step, the temperature of the bonding wires 45 does not necessarily have to reach the temperature of the heating means used in the heating step.
＜第２実施形態＞
　図７は、第２実施形態に係る水晶発振器２０１の構成を示す断面図である。 <Second embodiment>
FIG. 7 is a cross-sectional view showing the configuration of a crystal oscillator 201 according to the second embodiment.
　第１実施形態では、ＩＣ５とパッケージ７とを電気的に接続する接続部材はボンディングワイヤ４５であった。これに対して、第２実施形態では、接続部材がバンプ２４５となっている。具体的には、例えば、以下のとおりである。 In the first embodiment, the connecting member for electrically connecting the IC 5 and the package 7 was the bonding wire 45 . In contrast, in the second embodiment, the connection member is the bump 245 . Specifically, for example, it is as follows.
　発振器２０１は、第１実施形態の発振器１と同様に、水晶素子３と、ＩＣ５と、パッケージ２０７とを有している。パッケージ２０７は、第１実施形態のパッケージ７と同様に、基部２０９と、基部２０９の凹部を塞ぐ蓋１１とを有している。水晶素子３及びＩＣ５は、上記凹部に収容されている。また、第１実施形態と同様に、ＩＣ５は、基部２０９の第１面２０９ａ（図示の例では凹部の最下面）に対向しており、水晶素子３は、ＩＣ５を介して第１面９ａに対向している。 The oscillator 201 has a crystal element 3, an IC 5, and a package 207, like the oscillator 1 of the first embodiment. The package 207 has a base 209 and a lid 11 that closes the recess of the base 209, like the package 7 of the first embodiment. The crystal element 3 and IC 5 are accommodated in the recess. As in the first embodiment, the IC 5 faces the first surface 209a of the base portion 209 (the bottom surface of the recess in the illustrated example), and the crystal element 3 faces the first surface 9a through the IC 5. facing each other.
　ただし、基部２０９の具体的な形状は、ＩＣ５の実装構造の相違に伴って、第１実施形態のものとは異なっている。例えば、第１実施形態の基部９は、３つの凹部を有していたところ、基部２０９は、第１凹部２２５と、第１凹部２２５の底面に開口する第２凹部２２７と、の２つの凹部を有している。また、これに伴い、図７では、基部２０９の絶縁性の基体２２３は、３つの絶縁層（第１絶縁層３１Ｅ、第２絶縁層３１Ｆ及び第３絶縁層３１Ｇ）の積層体として描かれている。 However, the specific shape of the base 209 differs from that of the first embodiment due to the difference in the mounting structure of the IC5. For example, while the base 9 of the first embodiment has three recesses, the base 209 has two recesses, a first recess 225 and a second recess 227 opening at the bottom surface of the first recess 225. have. 7, the insulating substrate 223 of the base 209 is drawn as a laminate of three insulating layers (first insulating layer 31E, second insulating layer 31F and third insulating layer 31G). there is
　第１凹部２２５は、第１実施形態の第１凹部２５に相当する。すなわち、第１凹部２２５は、水晶素子３の収容に寄与している。そして、第１実施形態と同様に、水晶素子３は、第１凹部２２５の底面に実装されている。 The first concave portion 225 corresponds to the first concave portion 25 of the first embodiment. That is, the first concave portion 225 contributes to accommodation of the crystal element 3 . The crystal element 3 is mounted on the bottom surface of the first concave portion 225 as in the first embodiment.
　第２凹部２２７は、第１実施形態の第２凹部２７及び第３凹部２９に相当する。すなわち、第２凹部２２７は、ＩＣ５及び接続部材（バンプ２４５）の収容に寄与している。ただし、第１実施形態とは異なり、ＩＣ５は、第１面２０９ａとしての第２凹部２２７の底面（別の観点では基部２０９の凹部の最下面）に表面実装されている。 The second recessed portion 227 corresponds to the second recessed portion 27 and the third recessed portion 29 of the first embodiment. That is, the second concave portion 227 contributes to accommodation of the IC 5 and the connection member (bump 245). However, unlike the first embodiment, the IC 5 is surface-mounted on the bottom surface of the second recess 227 (from another point of view, the bottom surface of the recess of the base 209) as the first surface 209a.
　具体的には、基部２０９は、第２凹部２２７の底面にＩＣ用パッド３５を有している。ＩＣ５は、ＩＣ端子２１をＩＣ用パッド３５に対向させるように配置される。ＩＣ用パッド３５とＩＣ端子２１とがその間に介在するバンプ２４５によって接合されることによって、ＩＣ５は、パッケージ７に固定されるとともに電気的に接続される。 Specifically, the base 209 has the IC pad 35 on the bottom surface of the second recess 227 . The IC 5 is arranged so that the IC terminal 21 faces the IC pad 35 . The IC 5 is fixed and electrically connected to the package 7 by bonding the IC pads 35 and the IC terminals 21 with the bumps 245 interposed therebetween.
　ＩＣ用パッド３５は、第１面２０９ａに設けられ、かつＩＣ端子２１に対向している点を除いて、基本的に、第１実施形態のＩＣ用パッド３５と同様のものである。ＩＣ用パッド３５の数、平面形状及び寸法は、第１実施形態と同様に、任意である。例えば、ＩＣ用パッド３５は、平面透視において、ＩＣ端子２１に対して、広くてもよいし（図示の例）、同等の広さであってもよいし、狭くてもよい。 The IC pads 35 are basically the same as the IC pads 35 of the first embodiment, except that they are provided on the first surface 209a and face the IC terminals 21 . The number, planar shape and dimensions of the IC pads 35 are arbitrary, as in the first embodiment. For example, the IC pad 35 may be wider than the IC terminal 21 (the example shown in the figure), may be of the same width, or may be narrower than the IC terminal 21 when viewed through the plane.
　ＩＣ端子２１については、第１実施形態で説明したとおりである。ただし、接続部材（ボンディングワイヤ４５及びバンプ２４５）の相違に伴って、第１実施形態とは細部が異なっていても構わない。例えば、本実施形態では、ＩＣ端子２１（並びにバンプ２４５及びＩＣ用パッド３５）は、ＩＣ５を支持する役割を担う。そこで、複数のＩＣ端子２１は、ＩＣ５をバランスよく支持できるように、Ｄ１方向及びＤ２方向それぞれにおいて対称配置されてよい。 The IC terminal 21 is as described in the first embodiment. However, the details may differ from the first embodiment due to the difference in connection members (bonding wires 45 and bumps 245). For example, in this embodiment, the IC terminals 21 (as well as the bumps 245 and IC pads 35) serve to support the IC5. Therefore, the plurality of IC terminals 21 may be arranged symmetrically in each of the D1 direction and the D2 direction so as to support the IC 5 in a well-balanced manner.
　バンプ２４５の形状及び寸法は任意である。例えば、バンプ２４５の側面は、外側に膨らんでいてもよいし（図示の例）、内側に凹んでいてもよいし、前者のいずれとも言えない形状であってもよい。バンプ２４５とＩＣ端子２１とが接合されている面積と、バンプ２４５とＩＣ用パッド３５とが接合されている面積とは、いずれが大きくてもよい。バンプ２４５の直径（例えば最大径）の例を挙げると、９０μｍ以上１２０μｍ以下である。 The shape and dimensions of the bump 245 are arbitrary. For example, the side surface of the bump 245 may bulge outward (the example shown), may be recessed inward, or may have a shape that cannot be said to be either of the former. Either the area where the bump 245 and the IC terminal 21 are bonded or the area where the bump 245 and the IC pad 35 are bonded may be larger. An example of the diameter (for example, maximum diameter) of the bump 245 is 90 μm or more and 120 μm or less.
　なお、特に図示しないが、ＩＣ５は、その少なくとも一部（例えばＩＣ端子２１が位置している面）が封止樹脂４９（後述する図１１参照。換言すればアンダーフィル）によって覆われていてもよい。 Although not shown, the IC 5 may be covered with a sealing resin 49 (see FIG. 11, in other words, an underfill) at least partly (for example, the surface where the IC terminals 21 are located). good.
　図８は、図７の領域VIIIの拡大図である。 FIG. 8 is an enlarged view of region VIII in FIG.
　バンプ２４５は、ボンディングワイヤ４５と同様に、Ａｕによって構成されている。従って、本実施形態においても、接続部材（バンプ２４５）とＩＣ端子２１（少なくとも表面がＡｕからなる）との接合は、Ａｕ同士の接合となっている。また、第１実施形態と同様に、バンプ２４５とＩＣ用パッド３５との接合もＡｕ同士の接合とされてよい。 The bumps 245 are made of Au, like the bonding wires 45 . Therefore, in this embodiment as well, the bonding between the connection member (bump 245) and the IC terminal 21 (at least the surface of which is made of Au) is Au-to-Au bonding. Also, similarly to the first embodiment, bonding between the bumps 245 and the IC pads 35 may be performed by bonding between Au.
　以上の実施形態によれば、第１実施形態と同様に、接続部材（バンプ２４５）は、金（Ａｕ）からなり、また、ＩＣ端子２１は、第１Ａｕ層（Ａｕ層５７）を有している。Ａｕ層５７は、ＩＣ端子２１の表面を構成しており、バンプ２４５が接合されている。従って、第１実施形態と同様の効果が奏される。具体的には、以下のとおりである。 According to the above embodiment, the connection member (bump 245) is made of gold (Au), and the IC terminal 21 has the first Au layer (Au layer 57), as in the first embodiment. there is The Au layer 57 constitutes the surface of the IC terminal 21, and the bump 245 is bonded thereto. Therefore, the same effects as those of the first embodiment can be obtained. Specifically, it is as follows.
　図９は、比較例に係るバンプ２４５とＩＣ端子（第１層５１）との接合構造を示す図であり、図８に相当している。 FIG. 9 is a diagram showing a bonding structure between the bump 245 and the IC terminal (first layer 51) according to the comparative example, and corresponds to FIG.
　この比較例では、ＩＣ端子は、図４の比較例と同様に、実施形態の第１層５１のみで構成されている。この場合、図４の比較例においてボンディングワイヤ４５のうちＩＣ端子の近くの部分にボイドＶ１及びクラックＣ１が発生した原理と同様の原理によって、バンプ２４５のうちＩＣ端子の近くの部分にボイドＶ１及びクラックＣ１が発生する。そして、実施形態に係る発振器２０１では、第１実施形態の発振器１と同様の原理によって、ボイドＶ１及びクラックＣ１が発生する蓋然性が低減される。 In this comparative example, the IC terminal is composed only of the first layer 51 of the embodiment, similar to the comparative example in FIG. In this case, voids V1 and cracks C1 are generated in portions of the bumps 245 near the IC terminals by the same principle as the voids V1 and cracks C1 in the portions of the bonding wires 45 near the IC terminals in the comparative example of FIG. A crack C1 occurs. Further, in the oscillator 201 according to the embodiment, the probability of occurrence of voids V1 and cracks C1 is reduced by the same principle as in the oscillator 1 of the first embodiment.
＜第３実施形態＞
　図１０は、第３実施形態に係る水晶発振器３０１の構成を示す断面図である。 <Third Embodiment>
FIG. 10 is a cross-sectional view showing the configuration of a crystal oscillator 301 according to the third embodiment.
　本実施形態では、水晶素子３は、パッケージ６７に実装されている。パッケージ６７は、パッケージ３０７に実装されている。パッケージ３０７は、第１及び第２実施形態のパッケージ７及び２０７に相当する。換言すれば、パッケージ３０７は、ＩＣ５に接合される接続部材（図示の例ではバンプ２４５）が接合されるパッケージである。 The crystal element 3 is mounted on the package 67 in this embodiment. Package 67 is mounted on package 307 . The package 307 corresponds to the packages 7 and 207 of the first and second embodiments. In other words, the package 307 is a package to which connection members (bumps 245 in the illustrated example) that are bonded to the IC 5 are bonded.
　このように、水晶素子３は、接続部材（ボンディングワイヤ４５又はバンプ２４５）が接合されるパッケージ７又は２０７に直接的に保持されるのではなく、間接的にパッケージ３０７に保持されてよい。水晶素子３がパッケージ３０７に間接的に保持される態様は、種々可能である。図示の例では、以下のとおりである。 Thus, the crystal element 3 may be indirectly held by the package 307 rather than directly by the package 7 or 207 to which the connection member (bonding wire 45 or bump 245) is bonded. Various modes of indirectly holding the crystal element 3 in the package 307 are possible. In the illustrated example:
　パッケージ３０７は、他の実施形態と同様に、基部３０９と、蓋１１とを有している。基部３０９の絶縁性の基体３２３は、第１凹部３２５と、第１凹部３２５の底面に開口する第２凹部３２７とを有している。 The package 307 has a base 309 and a lid 11 as in other embodiments. The insulating substrate 323 of the base portion 309 has a first recess 325 and a second recess 327 opening at the bottom surface of the first recess 325 .
　第１凹部３２５は、ＩＣ５を収容することに寄与している。第１凹部３２５の底面（第２凹部３２７の開口の周囲）には、ＩＣ用パッド３５（ここでは不図示。図８参照）が設けられている。ＩＣ５は、－Ｄ３側の面にＩＣ端子２１（ここでは不図示。図８参照）が設けられている。そして、第２実施形態と同様に、ＩＣ５は、ＩＣ端子２１とＩＣ用パッド３５とがバンプ２４５によって接合されることによって、パッケージ３０７に実装されている。図８は、本実施形態におけるバンプ２４５及びその周囲の断面図として捉えられてよい。 The first concave portion 325 contributes to housing the IC5. An IC pad 35 (not shown here, see FIG. 8) is provided on the bottom surface of the first recess 325 (around the opening of the second recess 327). The IC 5 is provided with an IC terminal 21 (not shown here, see FIG. 8) on the surface on the -D3 side. As in the second embodiment, the IC 5 is mounted on the package 307 by bonding the IC terminals 21 and the IC pads 35 with the bumps 245 . FIG. 8 may be taken as a cross-sectional view of the bump 245 and its surroundings in this embodiment.
　第２凹部３２７は、パッケージ６７を収容することに寄与している。第２凹部３２７の底面には、不図示のパッドが形成されている。また、パッケージ６７は、その下面に不図示の端子を有している。そして、上記のパッドと端子とがバンプ６９によって接合されることによって、パッケージ６７はパッケージ３０７（基部３０９）に実装されている。すなわち、パッケージ６７は、パッケージ３０７に固定されるとともに電気的に接続される。 The second recess 327 contributes to housing the package 67. A pad (not shown) is formed on the bottom surface of the second recess 327 . The package 67 also has terminals (not shown) on its lower surface. The package 67 is mounted on the package 307 (base portion 309) by bonding the pads and terminals with the bumps 69. As shown in FIG. That is, the package 67 is fixed and electrically connected to the package 307 .
　水晶素子３とパッケージ６７との組み合わせは、水晶振動子６８と捉えられてよい。水晶振動子６８は、パッケージ３０７に実装されることが前提とされていない汎用のものとされてよい。別の観点では、水晶振動子６８は、それ単体で流通されるものであってよい。ただし、水晶振動子６８は、パッケージ３０７に実装されることが前提とされたものであっても構わない。図示の例では、水晶振動子６８は、電子素子として、水晶素子３のみを有している。ただし、水晶振動子６８は、温度センサ等の他の電子素子を有していても構わない。 A combination of the crystal element 3 and the package 67 may be regarded as a crystal oscillator 68 . The crystal oscillator 68 may be a general-purpose one that is not assumed to be mounted in the package 307 . From another point of view, the crystal oscillator 68 may be distributed alone. However, the crystal oscillator 68 may be one that is assumed to be mounted in the package 307 . In the illustrated example, the crystal oscillator 68 has only the crystal element 3 as an electronic element. However, the crystal oscillator 68 may have other electronic elements such as a temperature sensor.
　パッケージ６７の構成は任意である。図示の例では、パッケージ６７は、特に符号を付さないが、凹部を有する基部と、上記凹部を塞ぐ（密閉する）蓋とを有している。凹部の底面には、水晶用パッド３３（ここでは不図示）が設けられている。そして、水晶素子３は、例えば、第１実施形態と同様に、引出電極１７（ここでは不図示）と水晶用パッド３３とが導電性接着剤４１によって接合されることによって、パッケージ６７に実装される。 The configuration of the package 67 is arbitrary. In the illustrated example, the package 67 has a base portion having a recess and a lid that closes (seales) the recess, although no particular reference numerals are attached. A crystal pad 33 (not shown here) is provided on the bottom surface of the recess. Then, the crystal element 3 is mounted in the package 67 by, for example, bonding the lead-out electrodes 17 (not shown here) and the crystal pads 33 with the conductive adhesive 41 in the same manner as in the first embodiment. be.
　パッケージ６７は、図示の例以外にも種々可能である。例えば、パッケージ６７は、水晶素子３が実装される板状の基部（基板）と、水晶素子３の上から基部に被せられるキャップ状の蓋とを有する構成であってもよい。また、例えば、パッケージ６７は、パッケージ３０７のように２段以上の凹部を有するものであってもよいし、後述するパッケージ４０７（図１１）のようにＨ型のものであってもよい。 Various packages 67 are possible other than the illustrated example. For example, the package 67 may have a plate-like base (substrate) on which the crystal element 3 is mounted, and a cap-like lid that covers the base from above the crystal element 3 . Also, for example, the package 67 may have two or more recesses like the package 307, or may be H-shaped like the package 407 (FIG. 11) described later.
　パッケージ７（又は２０７）の説明は、ＩＣ５がパッケージ６７の内部に実装されない点を除いて、適宜にパッケージ６７に援用されて構わない。例えば、基部は、セラミック等の絶縁材料からなる基体と、当該基体に設けられた導電層及び貫通導体とを有してよい。蓋は、シーム溶接等によって基部に固定される金属板とされてよい。 The description of the package 7 (or 207) may be appropriately applied to the package 67, except that the IC5 is not mounted inside the package 67. For example, the base may have a base made of an insulating material such as ceramic, and a conductive layer and through conductors provided on the base. The lid may be a metal plate that is secured to the base by seam welding or the like.
　パッケージ３０７に対するパッケージ６７の実装に係る、パッド、バンプ６９及び端子の構成は任意である。例えば、ＩＣ用パッド３５、バンプ２４５及びＩＣ端子２１の説明は、パッケージ６７の実装に係る、パッド、バンプ６９及び端子に援用されてよい。例えば、パッケージ６７の実装において、パッドとバンプ６９との接合、及び／又はバンプ６９と端子との接合は、Ａｕ同士の接合とされてよい。 The configuration of pads, bumps 69 and terminals for mounting the package 67 on the package 307 is arbitrary. For example, the description of the IC pads 35 , bumps 245 and IC terminals 21 may be incorporated into the pads, bumps 69 and terminals associated with mounting the package 67 . For example, in mounting the package 67, the bonding between the pads and the bumps 69 and/or the bonding between the bumps 69 and the terminals may be Au-to-Au bonding.
　なお、特に図示しないが、ＩＣ５は、その少なくとも一部（例えばＩＣ端子２１が位置している面）が封止樹脂４９（後述する図１１参照。換言すればアンダーフィル）によって覆われていてもよい。 Although not shown, the IC 5 may be covered with a sealing resin 49 (see FIG. 11, in other words, an underfill) at least partly (for example, the surface where the IC terminals 21 are located). good.
　本実施形態では、第１及び第２実施形態とは逆に、ＩＣ５に対して水晶素子３が下方（－Ｄ３側）に位置している。このように、ＩＣ５と水晶素子３との位置関係は、ＩＣ５を実装しなければ水晶素子３を実装できない構成に限定されない。ただし、水晶素子３がパッケージ６７を介してパッケージ３０７に実装される態様において、第１又は第２実施形態と同様に、ＩＣ５が水晶素子３の下方に位置してもよい。 In this embodiment, contrary to the first and second embodiments, the crystal element 3 is positioned below the IC 5 (on the -D3 side). As described above, the positional relationship between the IC 5 and the crystal element 3 is not limited to the configuration in which the crystal element 3 cannot be mounted unless the IC 5 is mounted. However, in a mode where the crystal element 3 is mounted on the package 307 via the package 67, the IC 5 may be positioned below the crystal element 3 as in the first or second embodiment.
　図示の例では、接続部材として、バンプ２４５を例に取った。ただし、水晶素子３がパッケージ６７を介してパッケージ３０７に実装される態様において、第１実施形態と同様に、接続部材として、ボンディングワイヤ４５が用いられてもよい。例えば、ＩＣ５は、＋Ｄ３側にＩＣ端子２１が面するように配置され、第１凹部３２５の底面に固定されてよい。第１凹部３２５の底面又は当該底面に設けられた台座部の上面にＩＣ用パッド３５が設けられてよい。そして、ＩＣ端子２１とＩＣ用パッド３５とにボンディングワイヤ４５が接合されてよい。 In the illustrated example, the bump 245 is taken as an example of the connection member. However, in a mode where the crystal element 3 is mounted on the package 307 via the package 67, the bonding wire 45 may be used as the connecting member as in the first embodiment. For example, the IC 5 may be arranged so that the IC terminal 21 faces the +D3 side and fixed to the bottom surface of the first recess 325 . The IC pads 35 may be provided on the bottom surface of the first recess 325 or on the top surface of a pedestal provided on the bottom surface. A bonding wire 45 may be bonded to the IC terminal 21 and the IC pad 35 .
　以上の実施形態によれば、第１及び第２実施形態と同様に、接続部材（バンプ２４５）は、金（Ａｕ）からなり、また、ＩＣ端子２１は、第１Ａｕ層（Ａｕ層５７）を有している。Ａｕ層５７は、ＩＣ端子２１の表面を構成しており、バンプ２４５が接合されている。従って、第１及び第２実施形態と同様の効果が奏される。例えば、ボイドＶ１及びクラックＣ１が発生する蓋然性が低減される。 According to the above embodiments, the connecting members (bumps 245) are made of gold (Au), and the IC terminals 21 are made of the first Au layer (Au layer 57), as in the first and second embodiments. have. The Au layer 57 constitutes the surface of the IC terminal 21, and the bump 245 is bonded thereto. Therefore, the same effects as those of the first and second embodiments can be obtained. For example, the probability of occurrence of voids V1 and cracks C1 is reduced.
　また、本実施形態では、水晶素子３は、パッケージ６７に収容されている。この場合、例えば、導電性接着剤４１を加熱する処理は、水晶振動子６８及びＩＣ５がパッケージ３０７に実装される前に行われる。ひいては、接続部材（バンプ２４５）が高温に晒される蓋然性及び／又は頻度が低減される。その結果、例えば、Ａｕ同士の接合となっていない接合部（接合部材とＩＣ端子２１との接合部以外のいずれかの接合部）において、図６等を参照して説明した不都合と同様の不都合が生じる蓋然性が低減される。 Also, in this embodiment, the crystal element 3 is housed in the package 67 . In this case, for example, the process of heating the conductive adhesive 41 is performed before the crystal oscillator 68 and the IC 5 are mounted on the package 307 . As a result, the probability and/or frequency that the connection member (bump 245) is exposed to high temperatures is reduced. As a result, for example, the same inconvenience as the inconvenience described with reference to FIG. is reduced.
＜第４実施形態＞
　図１１は、第４実施形態に係る水晶発振器４０１の構成を示す断面図である。 <Fourth Embodiment>
FIG. 11 is a cross-sectional view showing the configuration of a crystal oscillator 401 according to the fourth embodiment.
　発振器４０１のパッケージ４０７は、断面視においてＨ形状を呈する、いわゆるＨ型のものとなっている。すなわち、パッケージ４０７の基部４０９は、第１凹部４２５と、第１凹部４２５とは反対側に開口している第２凹部４２７とを有している。水晶素子３は、第１凹部４２５に収容されている。ＩＣ５は、第２凹部４２７に収容されている。第１凹部４２５は、蓋１１によって密閉されている。このように、水晶素子３は、ＩＣ５と同一の空間（凹部）に配置されていなくてもよい。 The package 407 of the oscillator 401 is a so-called H-shaped one that exhibits an H shape in cross section. That is, the base 409 of the package 407 has a first recess 425 and a second recess 427 that opens on the side opposite to the first recess 425 . The crystal element 3 is housed in the first concave portion 425 . IC5 is housed in the second recess 427 . The first recess 425 is sealed with the lid 11 . Thus, the crystal element 3 does not have to be arranged in the same space (recess) as the IC 5 .
　Ｈ型パッケージの具体的な構成は種々可能である。図示の例では、以下のとおりである。 Various specific configurations of the H-type package are possible. In the illustrated example:
　基部４０９は、絶縁材料からなる基体４２３と、基体４２３に設けられた導体層及び貫通導体を有している。基体４２３は、その全体が一体的に形成されている。なお、第１実施形態の基体２３の説明で述べたように、このような基体４２３は、絶縁層の積層によって作製されてもよいし、他の方法によって作製されてもよい。蓋１１は、他の実施形態と同様に、シーム溶接等によって基部４０９に固定される金属板とされてよい。 The base portion 409 has a base 423 made of an insulating material, and a conductor layer and through conductors provided on the base 423 . The base 423 is integrally formed as a whole. As described in the description of the substrate 23 in the first embodiment, such a substrate 423 may be produced by stacking insulating layers, or may be produced by another method. Lid 11 may be a metal plate secured to base 409 by seam welding or the like, as in other embodiments.
　第１凹部４２５は、水晶素子３を収容することに寄与している。第１凹部４２５の底面には、水晶用パッド３３（ここでは不図示）が設けられている。そして、水晶素子３は、例えば、第１実施形態と同様に、引出電極１７（ここでは不図示）と水晶用パッド３３とが導電性接着剤４１によって接合されることによって、パッケージ４０７に実装される。 The first recess 425 contributes to housing the crystal element 3 . A crystal pad 33 (not shown here) is provided on the bottom surface of the first recess 425 . Then, the crystal element 3 is mounted in the package 407 by, for example, bonding the extraction electrodes 17 (not shown here) and the crystal pads 33 with the conductive adhesive 41 in the same manner as in the first embodiment. be.
　第２凹部４２７は、ＩＣ５を収容することに寄与している。第２凹部４２７の底面には、ＩＣ用パッド３５（ここでは不図示。図８参照）が設けられている。ＩＣ５は、＋Ｄ３側の面にＩＣ端子２１（ここでは不図示。図８参照）が設けられている。そして、第２実施形態と同様に、ＩＣ５は、ＩＣ端子２１とＩＣ用パッド３５とがバンプ２４５によって接合されることによって、パッケージ４０７に実装されている。図８は、Ｄ３方向の正負を逆にして、本実施形態におけるバンプ２４５及びその周囲の断面図として捉えられてよい。 The second recess 427 contributes to housing the IC5. An IC pad 35 (not shown here, see FIG. 8) is provided on the bottom surface of the second recess 427 . The IC 5 is provided with an IC terminal 21 (not shown here, see FIG. 8) on the +D3 side surface. As in the second embodiment, the IC 5 is mounted on the package 407 by bonding the IC terminals 21 and the IC pads 35 with the bumps 245 . FIG. 8 can be regarded as a cross-sectional view of the bump 245 and its surroundings in this embodiment, with the sign of the D3 direction reversed.
　図示の例では、ＩＣ５は、その全体が封止樹脂４９によって覆われている。ただし、封止樹脂４９は、－Ｄ３側の面がＩＣ５の＋Ｄ３側の面から－Ｄ３側の面までの範囲のいずれかの位置に位置するように設けられてよい。また、封止樹脂４９は、設けられなくてもよい。 In the illustrated example, the IC 5 is entirely covered with a sealing resin 49 . However, the sealing resin 49 may be provided so that the −D3 side surface is located at any position in the range from the +D3 side surface of the IC 5 to the −D3 side surface. Also, the sealing resin 49 may not be provided.
　封止樹脂４９は、例えば、加熱されることによって硬化する熱硬化性樹脂によって構成されてよい。熱硬化性樹脂としては、例えば、シリコーン樹脂及びエポキシ樹脂を挙げることができる。封止樹脂４９は、導電性接着剤４１を構成する樹脂及び／又は接着剤４３を構成する樹脂と同一のものであってもよいし、異なるものであってもよい。 The sealing resin 49 may be made of, for example, a thermosetting resin that hardens when heated. Examples of thermosetting resins include silicone resins and epoxy resins. The sealing resin 49 may be the same as or different from the resin forming the conductive adhesive 41 and/or the resin forming the adhesive 43 .
　図示の例では、接続部材として、バンプ２４５を例に取った。ただし、パッケージ４０７がＨ型のものである場合において、接続部材として、ボンディングワイヤ４５が用いられてもよい。例えば、ＩＣ５は、－Ｄ３側にＩＣ端子２１が面するように配置され、第２凹部４２７の底面に固定されてよい。第２凹部４２７の底面又は当該底面に設けられた台座部の上面（－Ｄ３側の面）にＩＣ用パッド３５が設けられてよい。そして、ＩＣ端子２１とＩＣ用パッド３５とがボンディングワイヤ４５によって接合されてよい。 In the illustrated example, the bump 245 is taken as an example of the connection member. However, when the package 407 is of H type, the bonding wire 45 may be used as the connection member. For example, the IC 5 may be arranged so that the IC terminal 21 faces the −D 3 side and fixed to the bottom surface of the second recess 427 . The IC pads 35 may be provided on the bottom surface of the second recess 427 or on the top surface (surface on the -D3 side) of the pedestal provided on the bottom surface. Then, the IC terminal 21 and the IC pad 35 may be bonded by the bonding wire 45 .
　Ｈ型のパッケージは、図示の例以外にも種々可能である。例えば、Ｈ型のパッケージは、第３実施形態に示したパッケージ６７と類似した容器型のパッケージと、当該容器型のパッケージの下面（－Ｄ３側の外面）に接合される回路基板とを有してよい。そして、回路基板に開口が形成されることによって、断面視においてＨ形状が得られてよい。ＩＣ５は、容器型のパッケージの下面に実装され、上記の開口に収容されてよい。 Various types of H-type packages are possible other than the example shown in the figure. For example, the H-shaped package has a container-shaped package similar to the package 67 shown in the third embodiment, and a circuit board bonded to the lower surface (the outer surface on the −D3 side) of the container-shaped package. you can By forming the opening in the circuit board, an H shape in a cross-sectional view may be obtained. The IC 5 may be mounted on the bottom surface of the container-type package and housed in the opening.
　以上の実施形態によれば、第１～第３実施形態と同様に、接続部材（バンプ２４５）は、金（Ａｕ）からなり、また、ＩＣ端子２１は、第１Ａｕ層（Ａｕ層５７）を有している。Ａｕ層５７は、ＩＣ端子２１の表面を構成しており、バンプ２４５が接合されている。従って、第１～第３実施形態と同様の効果が奏される。例えば、ボイドＶ１及びクラックＣ１が発生する蓋然性が低減される。 According to the above embodiments, as in the first to third embodiments, the connection member (bump 245) is made of gold (Au), and the IC terminal 21 is made of the first Au layer (Au layer 57). have. The Au layer 57 constitutes the surface of the IC terminal 21, and the bump 245 is bonded thereto. Therefore, the same effects as those of the first to third embodiments can be obtained. For example, the probability of occurrence of voids V1 and cracks C1 is reduced.
　また、本実施形態では、水晶素子３は、ＩＣ５よりも先にパッケージ４０７に実装可能である。この場合、例えば、導電性接着剤４１を加熱する処理は、ＩＣ５がパッケージ４０７に実装される前に行われる。ひいては、接続部材（バンプ２４５）が高温に晒される蓋然性及び／又は頻度が低減される。その結果、例えば、Ａｕ同士の接合となっていない接合部（接合部材とＩＣ端子２１との接合部以外のいずれかの接合部）において、図６等を参照して説明した不都合と同様の不都合が生じる蓋然性が低減される。 Also, in this embodiment, the crystal element 3 can be mounted on the package 407 before the IC 5 is mounted. In this case, for example, the process of heating the conductive adhesive 41 is performed before the IC 5 is mounted on the package 407 . As a result, the probability and/or frequency that the connection member (bump 245) is exposed to high temperatures is reduced. As a result, for example, the same inconvenience as the inconvenience described with reference to FIG. is reduced.
　発振器１は、ＩＣ５のうち少なくともＩＣ端子２１が位置している面（本実施形態では＋Ｄ３側の面）を覆っている絶縁性の樹脂（封止樹脂４９）を更に有してよい。 The oscillator 1 may further include an insulating resin (sealing resin 49) covering at least the surface of the IC 5 where the IC terminal 21 is located (the surface on the +D3 side in this embodiment).
　この場合、例えば、ボイドＶ１及びクラックＣ１の発生が低減されることによって、発振器１の特性が低下する蓋然性が低減されるという効果が特に有効である。具体的には、例えば、以下のとおりである。まず、封止樹脂４９は、複数のＩＣ端子２１が互いに短絡する蓋然性を低減したり、異物がＩＣ５とパッケージ７との間に侵入する蓋然性を低減したりすることに寄与する。一方、封止樹脂４９を設けると、硬化時の収縮によってＩＣ端子２１に応力が加えられる。その結果、ボンディングワイヤ４５のボイドＶ１又はクラックＣ１が拡大する可能性がある。しかし、本実施形態では、ボイドＶ１及びクラックＣ１が発生する蓋然性が低減されるから、当然に、ボイドＶ１及びクラックＣ１が拡大する蓋然性も低減される。ひいては、発振器１の特性が低下する蓋然性が低減される。 In this case, for example, it is particularly effective to reduce the possibility of deterioration of the characteristics of the oscillator 1 by reducing the generation of voids V1 and cracks C1. Specifically, for example, it is as follows. First, the sealing resin 49 contributes to reducing the probability that the plurality of IC terminals 21 are short-circuited with each other and that foreign matter enters between the IC 5 and the package 7 . On the other hand, when the sealing resin 49 is provided, stress is applied to the IC terminals 21 due to shrinkage during curing. As a result, the void V1 or crack C1 in the bonding wire 45 may expand. However, in the present embodiment, the probability of voids V1 and cracks C1 being generated is reduced, so naturally the probability of expansion of voids V1 and cracks C1 is also reduced. As a result, the probability that the characteristics of the oscillator 1 will deteriorate is reduced.
＜実施例＞
　比較例及び実施例に係る発振器を試作し、熱が発振器の特性低下に及ぼす影響を調べた。その結果、接続部材（ここではボンディングワイヤ４５）とＩＣ端子２１との接合をＡｕ同士の接合とすることによって、特性低下が低減されることが確認された。具体的には、以下のとおりである。 <Example>
Oscillators according to the comparative example and the working example were prototyped, and the influence of heat on deterioration of oscillator characteristics was investigated. As a result, it was confirmed that deterioration in characteristics was reduced by joining the connection member (bonding wire 45 in this case) and the IC terminal 21 to the Au-to-Au joint. Specifically, it is as follows.
（比較例）
　図１２は、比較例に係る発振器の特性の経時変化を示す図である。 (Comparative example)
FIG. 12 is a diagram showing temporal changes in the characteristics of the oscillator according to the comparative example.
　この図において、横軸は、経過時間（単位：時間）を示しており、また、対数スケールとなっている。縦軸は、発振器が出力する発振信号の周波数の初期値Ｆに対する、経過時間に伴う周波数Ｆの変化量ＤＦとの比ＤＦ／Ｄ（ｐｐｍ）を示している。図中の複数の線は、複数の試作品のＤＦ／Ｄの経時変化を示している。 In this figure, the horizontal axis indicates the elapsed time (unit: hours), and is on a logarithmic scale. The vertical axis indicates the ratio DF/D (ppm) of the change amount DF of the frequency F with elapsed time to the initial value F of the frequency of the oscillation signal output by the oscillator. A plurality of lines in the figure indicate changes over time in DF/D of a plurality of prototypes.
　比較例の構成は、図６を参照して説明したものである。すなわち、第１実施形態に係る発振器１において、ＩＣ端子を第１層５１（具体的にはＡｌ）のみによって構成したものである。この比較例に係る試作品を図５を参照して説明した製造方法の条件と同様の条件で作製し、その後、１２５℃の環境下に晒した。図１２は、その１２５℃の環境下におけるＤＦ／Ｄの経時変化を示している。 The configuration of the comparative example has been described with reference to FIG. That is, in the oscillator 1 according to the first embodiment, the IC terminals are configured only by the first layer 51 (specifically, Al). A prototype according to this comparative example was produced under the same conditions as those of the manufacturing method described with reference to FIG. 5, and then exposed to an environment of 125.degree. FIG. 12 shows the change over time of DF/D under the 125° C. environment.
　この図に示されているように、１０００時間経過後のＤＦ／Ｄは、絶対値で３ｐｐｍ以上となっている。なお、１０００時間経過後のＤＦ／Ｄは、絶対値で１０ｐｐｍ以下であり、比較例に係る発振器は、一般的な発振器に要求される程度の特性維持の能力は有している。 As shown in this figure, the absolute value of DF/D after 1000 hours is 3 ppm or more. The absolute value of DF/D after 1000 hours has passed is 10 ppm or less, and the oscillator according to the comparative example has the ability to maintain characteristics required for general oscillators.
（実施例）
　図１３は、実施例に係る発振器の特性の経時変化を示す図である。 (Example)
FIG. 13 is a diagram showing temporal changes in the characteristics of the oscillator according to the example.
　この図は、図１２と同様の図である。ただし、図１２とは異なり、横軸は、対数スケールとはなっていない。比較例と同様に、実施例についても、複数の試作品のＤＦ／Ｄの経時変化が示されている。 This figure is similar to FIG. However, unlike FIG. 12, the horizontal axis does not have a logarithmic scale. Similar to the comparative example, the example also shows changes over time in DF/D of a plurality of prototypes.
　実施例に係る発振器の構成は、第１実施形態の発振器１の構成と同様である。換言すれば、実施例の構成は、比較例において、ＩＣ端子を４層（具体的にはＡｌ／Ｎｉ／Ｐｄ／Ａｕ）からなるＩＣ端子に置換したものである。他の条件は、実施例と比較例とで同様である。 The configuration of the oscillator according to the example is the same as the configuration of the oscillator 1 of the first embodiment. In other words, in the configuration of the example, the IC terminal in the comparative example is replaced with an IC terminal composed of four layers (specifically, Al/Ni/Pd/Au). Other conditions are the same between the example and the comparative example.
　図１３に示されているように、実施例では、１０００時間経過後のＤＦ／Ｄは、絶対値で３ｐｐｍ以下（より具体的には２ｐｐｍ未満）となっている。すなわち、実施例における１０００時間経過後のＤＦ／Ｄは、実施例における１０００時間経過後のＤＦ／Ｄよりも小さい。これにより、実施例の特性維持の能力が比較例の特性維持の能力よりも高いことが確認できた。 As shown in FIG. 13, in the example, the absolute value of DF/D after 1000 hours is 3 ppm or less (more specifically, less than 2 ppm). That is, the DF/D after 1000 hours in the example is smaller than the DF/D after 1000 hours in the example. As a result, it was confirmed that the ability to maintain characteristics of the examples was higher than the ability to maintain characteristics of the comparative examples.
　なお、以上の実施形態において、ボンディングワイヤ４５及びバンプ２４５は、それぞれ接続部材の一例である。ＩＣ端子２１は、ＩＣが有している端子の一例である。ＩＣ端子２１のＡｕ層５７は、第１Ａｕ層の一例である。封止樹脂４９は、ＩＣの端子が位置している面を覆う絶縁性の樹脂の一例である。ＩＣ用パッド３５は、接続部材が接合されているパッドの一例である。ＩＣ用パッド３５の上層６１は、第２Ａｕ層の一例である。励振電極１５の主層６５は、第３Ａｕ層の一例である。ステップＳＴ１は、接合ステップの一例である。ステップＳＴ２、ＳＴ３、ＳＴ５及びＳＴ８は、それぞれ加熱ステップの一例である。 It should be noted that in the above embodiments, the bonding wires 45 and the bumps 245 are examples of connection members. The IC terminal 21 is an example of a terminal that the IC has. The Au layer 57 of the IC terminal 21 is an example of the first Au layer. The sealing resin 49 is an example of an insulating resin that covers the surface of the IC where the terminals are located. The IC pad 35 is an example of a pad to which a connection member is bonded. The upper layer 61 of the IC pad 35 is an example of the second Au layer. The main layer 65 of the excitation electrode 15 is an example of the third Au layer. Step ST1 is an example of a joining step. Each of steps ST2, ST3, ST5 and ST8 is an example of a heating step.
　本開示に係る技術は、以上の実施形態に限定されず、種々の態様で実施されてよい。 The technology according to the present disclosure is not limited to the above embodiments, and may be implemented in various aspects.
　発振器の用途乃至は機能は適宜に設定されてよい。例えば、発振器は、クロック用発振器であってもよいし、電圧制御型発振器（略語：ＶＣＸＯ）であってもよいし、温度補償型発振器（略語：ＴＣＸＯ）であってもよいし、恒温槽付発振器(略語：ＯＣＸＯ)の恒温槽内の発振器であってもよい。既述のように、外部端子、ＩＣ用パッド及びＩＣ端子の数及びその配置は、これらの発振器に要求される機能に応じて適宜に設定されてよい。 The usage or function of the oscillator may be set as appropriate. For example, the oscillator may be a clock oscillator, a voltage controlled oscillator (abbreviation: VCXO), a temperature compensated oscillator (abbreviation: TCXO), or a It may be an oscillator in a constant temperature oven of an oscillator (abbreviation: OCXO). As described above, the number and arrangement of external terminals, IC pads, and IC terminals may be appropriately set according to the functions required of these oscillators.
　実施形態では、発振器は、電子素子として、水晶素子及びＩＣのみを有した。ただし、発振器は、これ以外の素子を有していてもよい。例えば、ＩＣとは別個に温度センサを有していてもよい。 In the embodiment, the oscillator had only a crystal element and an IC as electronic elements. However, the oscillator may have other elements. For example, a temperature sensor may be provided separately from the IC.
　なお、本開示からは、水晶発振器よりも上位概念の圧電デバイス、圧電発振器又は水晶デバイスを抽出可能である。圧電デバイス及び圧電発振器においては、水晶素子に代えて、水晶以外の圧電体を含む圧電素子が用いられてよい。また、圧電デバイス及び水晶デバイスは、発振器でなくてよい。例えば、圧電デバイス及び水晶デバイスは、ＩＣに代えて温度センサを有する振動子とされてよい。 From the present disclosure, it is possible to extract a piezoelectric device, a piezoelectric oscillator, or a crystal device, which are higher concepts than crystal oscillators. In the piezoelectric device and piezoelectric oscillator, a piezoelectric element containing a piezoelectric material other than crystal may be used in place of the crystal element. Also, the piezoelectric and crystal devices need not be oscillators. For example, piezoelectric devices and crystal devices may be vibrators with temperature sensors instead of ICs.
　実施形態の説明では、Ａｕからなる接続部材（ワイヤボンディング又はバンプ）と、少なくとも表面がＡｕからなるＩＣ端子との接合に着目した。ただし、本開示からは、他の構成に着目した発明が抽出されてもよい。この場合、接続部材及びＩＣ端子の表面は、Ａｕ以外の材料（例えばＡｌ又はＣｕ）によって構成されていても構わない。 In the description of the embodiment, attention was paid to the bonding between the connection member (wire bonding or bump) made of Au and the IC terminal whose surface at least is made of Au. However, inventions focusing on other configurations may be extracted from the present disclosure. In this case, the surfaces of the connecting members and the IC terminals may be made of a material other than Au (for example, Al or Cu).
１…水晶発振器、３…水晶素子、５…ＩＣ、７…パッケージ、２１…ＩＣ端子（端子）、…、４５…ボンディングワイヤ（接続部材）、５７…Ａｕ層（第１Ａｕ層）。 DESCRIPTION OF SYMBOLS 1... Crystal oscillator, 3... Crystal element, 5... IC, 7... Package, 21... IC terminal (terminal),..., 45... Bonding wire (connection member), 57... Au layer (first Au layer).

Claims (10)

  1. 　水晶素子と、
    　端子を有しているＩＣと、
    　前記水晶素子及び前記ＩＣを保持しているパッケージと、
    　金からなり、前記端子と前記パッケージとに接合されている、バンプ又はボンディングワイヤである、接続部材と、
    　を有しており、
    　前記端子は、当該端子の表面を構成しており、前記接続部材が接合されている、第１Ａｕ層を有している
    　水晶発振器。     a crystal element;
    an IC having terminals;
    a package holding the crystal element and the IC;
    a connection member, which is a bump or a bonding wire, made of gold and bonded to the terminal and the package;
    and
    The terminal comprises a first Au layer forming a surface of the terminal and to which the connecting member is bonded.
  2. 　前記端子は、
    　　アルミニウム又はアルミニウムを主成分とする合金からなる第１層と、
    　　ニッケル又はニッケルを主成分とする合金からなり、前記第１層に対して前記第１Ａｕ層の側に重なる第２層と、
    　　パラジウム又はパラジウムを主成分とする合金からなり、前記第２層に対して前記第１Ａｕ層の側に重なる第３層と、を更に有しており、
    　前記第１Ａｕ層は、前記第３層に重なっている
    　請求項１に記載の水晶発振器。     The terminal is
    a first layer made of aluminum or an alloy containing aluminum as a main component;
    a second layer made of nickel or an alloy containing nickel as a main component and overlapping the first layer on the side of the first Au layer;
    a third layer made of palladium or an alloy containing palladium as a main component and overlapping the second layer on the side of the first Au layer;
    The crystal oscillator according to claim 1, wherein the first Au layer overlaps the third layer.
  3. 　前記パッケージは、
    　　第１面を有している基部と、
    　　前記第１面上に密閉空間が構成されるように前記基部に固定されている蓋と、を有しており、
    　前記ＩＣは、前記第１面に固定されて前記密閉空間に収容されており、
    　前記水晶素子は、前記ＩＣを介して前記第１面と対向する位置にて前記密閉空間に収容されており、かつ導電性フィラーが分散されている樹脂からなる導電性接着剤によって前記基部に接合されている
    　請求項１又は２に記載の水晶発振器。     The package includes:
    a base having a first surface;
    a lid secured to the base such that an enclosed space is defined on the first surface;
    The IC is fixed to the first surface and housed in the sealed space,
    The crystal element is accommodated in the sealed space at a position facing the first surface via the IC, and is bonded to the base by a conductive adhesive made of a resin in which a conductive filler is dispersed. 3. The crystal oscillator according to claim 1 or 2.
  4. 　前記パッケージは、
    　　第１凹部と、当該第１凹部とは反対側に開口する第２凹部とを有している基部と、
    　　前記第１凹部を塞ぐ蓋と、を有しており、
    　前記水晶素子は、前記第１凹部に収容されており、
    　前記ＩＣは、前記第２凹部に収容されている
    　請求項１又は２に記載の水晶発振器。     The package includes:
    a base having a first recess and a second recess opening on the side opposite to the first recess;
    and a lid that closes the first recess,
    The crystal element is accommodated in the first recess,
    3. The crystal oscillator according to claim 1, wherein said IC is accommodated in said second recess.
  5. 　前記水晶素子は、
    　　水晶ブランクと、
    　　前記水晶ブランクに重なっている励振電極と、を有しており、
    　前記水晶ブランクの前記励振電極が重なっている部分の厚さは、５μｍ以上３０μｍ以下である
    　請求項３に記載の水晶発振器。     The crystal element is
    a crystal blank;
    an excitation electrode overlying the crystal blank;
    4. The crystal oscillator according to claim 3, wherein the thickness of the portion of the crystal blank where the excitation electrodes overlap is 5 [mu]m or more and 30 [mu]m or less.
  6. 　前記ＩＣのうち少なくとも前記端子が位置している面を覆っている絶縁性の樹脂を更に有している
    　請求項１～５のいずれか１項に記載の水晶発振器。     The crystal oscillator according to any one of claims 1 to 5, further comprising an insulating resin covering at least a surface of the IC on which the terminals are located.
  7. 　前記パッケージは、前記接続部材が接合されているパッドを有しており、
    　前記パッドは、当該パッドの表面を構成しており、前記接続部材が接合されている第２Ａｕ層を有している
    　請求項１～６のいずれか１項に記載の水晶発振器。     The package has a pad to which the connection member is bonded,
    The crystal oscillator according to any one of claims 1 to 6, wherein the pad has a second Au layer that constitutes the surface of the pad and to which the connection member is bonded.
  8. 　前記水晶素子及び前記ＩＣは、同一の密閉空間に収容されており、
    　前記水晶素子は、
    　　水晶ブランクと、
    　　前記水晶ブランクに重なる励振電極と、を有しており、
    　前記励振電極は、当該励振電極の表面を構成している第３Ａｕ層を有している
    　請求項１～７のいずれか１項に記載の水晶発振器。     The crystal element and the IC are housed in the same sealed space,
    The crystal element is
    a crystal blank;
    and an excitation electrode overlapping the crystal blank,
    8. The crystal oscillator according to claim 1, wherein the excitation electrode has a third Au layer forming a surface of the excitation electrode.
  9. 　請求項１～８のいずれか１項に記載の水晶発振器の製造方法。 A method for manufacturing the crystal oscillator according to any one of claims 1 to 8.
  10. 　前記第１Ａｕ層と前記パッケージが有する基部とに前記接続部材を接合する接合ステップと、
    　前記接合ステップの後、前記接合ステップにおける前記接続部材の温度よりも高い温度に前記接続部材が晒される１つ以上の加熱ステップと、
    　を有している請求項９に記載の水晶発振器の製造方法。     a bonding step of bonding the connection member to the first Au layer and a base portion of the package;
    after the bonding step, one or more heating steps in which the connecting member is exposed to a temperature higher than the temperature of the connecting member during the bonding step;
    10. The method of manufacturing a crystal oscillator according to claim 9, comprising:
PCT/JP2022/027066 2021-07-30 2022-07-08 Crystal oscillator and manufacturing method therefor WO2023008138A1 (en)

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JP2012090203A (en) * 2010-10-22 2012-05-10 Seiko Epson Corp Piezoelectric oscillator
JP2013207686A (en) * 2012-03-29 2013-10-07 Nippon Dempa Kogyo Co Ltd Crystal oscillator
JP2017130823A (en) * 2016-01-21 2017-07-27 京セラ株式会社 Piezoelectric oscillator and manufacturing method of the same
JP2018074350A (en) * 2016-10-28 2018-05-10 株式会社大真空 Surface-mount type piezoelectric oscillator and mounting structure to circuit board
JP2020136999A (en) * 2019-02-22 2020-08-31 京セラ株式会社 Crystal element, crystal device, and electronic apparatus

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012090203A (en) * 2010-10-22 2012-05-10 Seiko Epson Corp Piezoelectric oscillator
JP2013207686A (en) * 2012-03-29 2013-10-07 Nippon Dempa Kogyo Co Ltd Crystal oscillator
JP2017130823A (en) * 2016-01-21 2017-07-27 京セラ株式会社 Piezoelectric oscillator and manufacturing method of the same
JP2018074350A (en) * 2016-10-28 2018-05-10 株式会社大真空 Surface-mount type piezoelectric oscillator and mounting structure to circuit board
JP2020136999A (en) * 2019-02-22 2020-08-31 京セラ株式会社 Crystal element, crystal device, and electronic apparatus

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