WO2023000657A1 - 半导体结构及其制备方法 - Google Patents
半导体结构及其制备方法 Download PDFInfo
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- WO2023000657A1 WO2023000657A1 PCT/CN2022/076312 CN2022076312W WO2023000657A1 WO 2023000657 A1 WO2023000657 A1 WO 2023000657A1 CN 2022076312 W CN2022076312 W CN 2022076312W WO 2023000657 A1 WO2023000657 A1 WO 2023000657A1
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- layer
- conductive layer
- bit line
- mask
- semiconductor structure
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims description 38
- 229920002120 photoresistant polymer Polymers 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 7
- 230000000717 retained effect Effects 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 abstract description 9
- 230000015572 biosynthetic process Effects 0.000 abstract description 8
- 230000005540 biological transmission Effects 0.000 abstract description 6
- 239000011800 void material Substances 0.000 abstract 1
- 238000005137 deposition process Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 239000004020 conductor Substances 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical class [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical class [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Definitions
- the present disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
- Dynamic random access memory (Dynamic random access memory, referred to as DRAM) is a semiconductor memory that writes and reads data at high speed and randomly, and is widely used in data storage devices or devices.
- DRAM generally includes a plurality of repeated storage cells, each of which includes a transistor and a capacitor, wherein the gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line through the bit line contact, and the drain is electrically connected to the bit line through the
- the storage node contact is electrically connected to the capacitor, and the word line voltage on the word line can control the on and off of the transistor, so that the data information stored in the capacitor can be read or written into the capacitor through the bit line.
- bit line contact when the bit line contact is formed, the bit line contact tends to form voids, which increase the resistance of the bit line contact and reduce the transmission performance of the semiconductor structure.
- a first aspect of an embodiment of the present disclosure provides a method for preparing a semiconductor structure, which includes the following steps:
- the thickness of the sacrificial layer being 10nm-20nm;
- the retained first initial conductive layer constitutes the first conductive layer, and the thickness of the first conductive layer accounts for 2/5 to 3/5 of the thickness of the first initial conductive layer;
- a second conductive layer is formed in the bit line contact area, and the second conductive layer fills the bit line contact area.
- the bit line contact region has a depth of 34nm ⁇ 42nm.
- the step of forming a first mask layer with a pattern on the sacrificial layer includes:
- the first mask pattern includes a plurality of first opening regions arranged at intervals and for separating a first shielding area for each of the first opening areas;
- the first mask layer exposed in the first opening area is removed to form a pattern in the first mask layer.
- the step of forming the second conductive layer in the bit line contact region includes:
- the second initial conductive layer extends outside the bit line contact area and covers the first conductive layer
- the remaining second initial conductive layer constitutes a second conductive layer
- the second conductive layer is integrally connected with the first conductive layer to form a bit line contact layer .
- a chemical mechanical polishing process is used to remove part of the thickness of the second initial conductive layer.
- the first mask layer includes a first hard mask layer and a first silicon oxynitride layer sequentially stacked, and the first hard mask layer is disposed on the sacrificial layer.
- the preparation method further includes:
- a first insulating layer is formed on the substrate.
- the first conductive layer and the second conductive layer are made of the same material, including polysilicon.
- the material of the sacrificial layer includes silicon oxide; the material of the first insulating layer includes silicon nitride.
- the preparation method also includes:
- bit line contact layer forming a bit line conductive layer and a patterned second mask layer sequentially stacked on the bit line contact layer
- bit line contact layer Using the second mask layer with a pattern as a mask, removing part of the bit line conductive layer and the bit line contact layer, the remaining bit line conductive layer constitutes a bit line, and the retained bit line The line contact layer constitutes a bit line contact.
- the step of forming a sequentially stacked bit line conductive layer and a second mask layer with a pattern on the bit line contact includes:
- the second mask pattern includes a plurality of second opening regions arranged at intervals and for separating a second shielding area for each of the second opening areas;
- the second mask layer exposed in the second opening area is removed to form a pattern in the second mask layer.
- the second mask layer includes an amorphous carbon layer, a second silicon oxynitride layer, a second hard mask layer, and a third silicon oxynitride layer that are sequentially stacked, and the amorphous carbon layer set on the bit line conductive layer.
- the bit line conductive layer includes a first bit line conductive layer and a second bit line conductive layer stacked, and the first bit line conductive layer is disposed on the bit line contact layer.
- the step of forming a sequentially stacked bit line conductive layer and a second mask layer with a pattern on the bit line contact layer includes:
- a second insulating layer is formed on the bit line conductive layer.
- a second aspect of the embodiments of the present disclosure provides a semiconductor structure, which is manufactured by the method for manufacturing a semiconductor structure as described above.
- FIG. 1 is a structural schematic diagram 1 of a semiconductor structure provided in the related art
- FIG. 2 is a structural schematic diagram II of a semiconductor structure provided in the related art
- FIG. 3 is a flowchart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
- FIG. 4 is a schematic structural view of forming a first initial conductive layer, a sacrificial layer, a first mask layer, and a patterned first photoresist layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
- FIG. 5 is a schematic structural diagram of forming a bit line contact region in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
- FIG. 6 is a schematic diagram of the structure of the second initial conductive layer formed in the method for preparing the semiconductor structure provided by the embodiment of the present disclosure
- FIG. 7 is a schematic structural diagram of forming a bit line contact layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
- FIG. 8 is a schematic structural diagram of forming a bit line conductive layer, a second insulating layer, a second mask layer, and a patterned second photoresist layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
- FIG. 9 is a schematic structural diagram of forming a bit line and a bit line contact in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
- Isolation structure 20: The first insulating layer
- 40 sacrificial layer
- 50 first mask layer
- 51 the first hard mask layer
- 52 the first silicon oxynitride layer
- bit line contact layer 90: bit line contact layer; 91: bit line contact;
- bit line conductive layer 100: bit line conductive layer; 101: first bit line conductive layer;
- 110 the second mask layer
- 120 the second photoresist layer
- the bit line contact in the semiconductor structure has the problem of voids, which will increase the resistance of the bit line contact and reduce the transmission performance of the semiconductor structure.
- the reason for this problem is that the depth of the bit line contact area is large, and the process of forming the bit line contact in the bit line contact area is limited by the deposition process, and voids are easily formed in the bit line contact.
- the thickness of the sacrificial layer is reduced by controlling the thickness ratio of the sacrificial layer to the thickness of the first initial conductive layer, so that when the sacrificial layer and the first initial conductive layer are etched subsequently , while etching all the sacrificial layer, it is also possible to remove the part of the thickness of the first initial conductive layer originally covered by the sacrificial layer, so that the thickness of the remaining first initial conductive layer is reduced, reducing the contact area of the bit line When the second conductive layer is deposited on the bit line contact area, the formation of voids in the second conductive layer can be avoided, thereby reducing the resistance of the bit line contact and improving the transmission performance of the semiconductor structure.
- Fig. 3 is a flowchart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
- Figs. 4-9 are schematic diagrams of various stages of a method for preparing a semiconductor structure. The method for preparing a semiconductor structure will be described in detail below in conjunction with Figs. 3-9 introduction.
- This embodiment does not limit the semiconductor structure.
- the semiconductor structure will be described below as an example of a dynamic random access memory (DRAM). However, this embodiment is not limited to this.
- the semiconductor structure in this embodiment can also be other structures. .
- the method for preparing a semiconductor structure includes the following steps:
- Step S100 providing a substrate.
- the substrate 10 is used as a supporting component of the DRAM for supporting other components disposed thereon, wherein the substrate 10 can be made of a semiconductor material, and the semiconductor material can be silicon, germanium, One or more of silicon-germanium compounds and silicon-carbon compounds.
- each active region 11 There are a plurality of active regions 11 arranged at intervals in the substrate 10, and an isolation structure 12 for separating each active region 11, wherein the plurality of active regions 11 can be arranged in a rectangular arrangement, and the active regions 11 are used Used to form semiconductor devices such as transistors or word lines.
- the first insulating layer 20 can be deposited on the substrate 10 through a deposition process, and the first insulating layer 20 is used to realize the isolation between the active region 11 in the substrate 10 and the subsequently formed first initial conductive layer.
- the material of the first insulating layer 20 may include insulating materials such as silicon nitride.
- Step S200 forming a first initial conductive layer and a sacrificial layer sequentially stacked on the substrate, and the thickness of the sacrificial layer is 10nm-20nm.
- the first initial conductive layer 30 and the sacrificial layer 40 can be formed on the substrate 10 by a deposition process, wherein the deposition process can be an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process.
- the material of the first initial conductive layer 30 may include conductive materials such as polysilicon, and the sacrificial layer 40 may include insulating materials such as silicon oxide.
- the first initial conductive layer 30 needs to be disposed on the first insulating layer 20 .
- Step S300 forming a first mask layer with a pattern on the sacrificial layer.
- a first photoresist layer 60 is formed on the first mask layer 50 .
- the first photoresist layer 60 can be formed on the first mask layer 50 by coating.
- the first photoresist layer 60 is patterned by exposure, development or etching to form a first mask pattern in the first photoresist layer 60.
- the first mask pattern includes a plurality of first mask patterns arranged at intervals. An opening area 62 and a first shielding area 61 for separating each first opening area 62 .
- the first mask layer 50 exposed in the first opening region 62 is removed by using etching solution or etching gas, so as to form a pattern in the first mask layer 50 .
- the first mask layer 50 may be a single film layer, or may be a laminated layer.
- the mask layer 51 and the first silicon oxynitride layer 52 , the first hard mask layer 51 are disposed on the sacrificial layer 40 .
- the accuracy of the transfer process of the pattern on the first photoresist layer 60 can be ensured, and the accuracy of the subsequent formation of the bit line contact region can be improved.
- Step S400 Using the first mask layer as a mask, remove the sacrificial layer and part of the first initial conductive layer and the substrate, so as to form a bit line contact region in the first initial conductive layer and the substrate, and the remaining first initial conductive layer
- the conductive layer constitutes the first conductive layer, and the thickness of the first conductive layer accounts for 2/5-3/5 of the thickness of the first initial conductive layer, and its structure is shown in FIG. 5 .
- the thickness of the sacrificial layer 40 is 10 nm to 20 nm, compared with the related art, the thickness of the sacrificial layer 40 is Compared with 48nm-52nm, the thickness of the sacrificial layer 40 is reduced, so that when the sacrificial layer 40 is patterned, the sacrificial layer 40 originally covered by the first mask layer 50 will also be removed, so that the entire sacrificial layer 40 will be completely etched away; when continuing to etch the first initial conductive layer 30, the first initial conductive layer 30 originally blocked by the first mask layer 50 will also be removed by a certain thickness, so that the first initial conductive layer is finally formed
- the thickness of 31 accounts for 2/5-3/5 of the thickness of the first initial conductive layer 30, which can reduce the depth of the bit line contact area, so as to prevent the formation of gaps when the second conductive layer is subsequently formed in the bit
- bit line contact region 70 is used to expose the active region 11 , so as to facilitate the electrical connection between the subsequently formed bit line contact and the active region 11 .
- the depth of the bit line contact region 70 is greater than 42nm, the depth of the bit line contact region will be excessively increased.
- the second conductive layer is subsequently formed, voids are likely to be formed in the second conductive layer, which affects the semiconductor.
- the transmission performance of the structure if the depth of the bit line contact area is less than 34nm, the depth of the bit line contact area will be reduced, thereby reducing the height of the subsequent formation of the second conductive layer, affecting the electrical connection between the bit line and the active area, and reducing the semiconductor structure. Therefore, in this embodiment, the depth of the bit line contact region is between 34nm and 52nm, which can prevent the formation of voids in the second conductive layer and ensure the transmission performance of the semiconductor structure.
- Step S500 Form a second conductive layer in the bit line contact area, and the second conductive layer fills the bit line contact area.
- a conductive material can be deposited into the bit line contact region 70 through a deposition process, and the conductive material can fill the bit line contact region 70.
- the conductive material constitutes the second conductive layer 81, wherein the material of the second conductive layer 81 is the same as that of the first conductive layer.
- the materials of the layers 31 are the same, and may all include conductive materials such as polysilicon.
- a second initial conductive layer 80 can be formed in the bit line contact region 70 by a chemical vapor deposition process or a physical vapor deposition process, and the second initial conductive layer 80 extends to the bit line contact region 70 outside, and cover the first conductive layer 31.
- the second initial conductive layer 80 with a partial thickness can be removed by a chemical mechanical polishing process, and the second initial conductive layer 80 that remains forms a second conductive layer 81, and the second conductive layer 81 is connected with the first conductive layer 80.
- the conductive layer 31 is connected to form a bit line contact layer 90 as a whole.
- the top surface of the second initial conductive layer 80 is planarized by the chemical mechanical polishing process, the top surface of the bit line contact layer 90 formed by the first conductive layer 31 and the second conductive layer 81 is in contact with the The horizontal planes are parallel to each other, which can prevent the subsequent formation of the bit line on the bit line contact layer from having a height difference and ensure the performance of the bit line.
- top surface of the bit line contact layer 90 formed in this embodiment may be higher than the top surface of the first conductive layer 31 , or may be flush with the top surface of the first conductive layer 31 .
- the preparation method also includes:
- bit line conductive layer 100 and a patterned second mask layer 110 are sequentially formed on the bit line contact layer 90 .
- the bit line conductive layer 100 can be formed on the bit line contact layer 90 by a deposition process, for example, the stacked first bit line conductive layer 101 and the second bit line conductive layer 101 can be sequentially formed on the bit line contact layer 90 Layer 102 , the first bitline conductive layer 101 is disposed on the bitline contact layer 90 .
- the material of the first bit line conductive layer 101 may include titanium nitride, and the material of the second bit line conductive layer 102 may include tungsten.
- the first bit line conductive layer 101 has a conductive function, It also has a blocking function, which can prevent the conductive material in the second bit line conductive layer 102 from diffusing into the substrate 10 or the bit line contact layer 90, so as to ensure the conductivity of the subsequently formed bit line.
- a second mask layer 110 may be formed on the bit line conductive layer 100 through a deposition process.
- the second mask layer 110 can be a single film layer, or a laminated layer.
- the second mask layer 110 can include an amorphous carbon layer 111, The second silicon oxynitride layer 112 , the second hard mask layer 113 , the third silicon oxynitride layer 114 , and the amorphous carbon layer 111 are disposed on the bit line conductive layer 100 .
- the second photoresist layer 120 can be formed on the second mask layer 110 , for example, the second photoresist layer 120 can be formed on the second mask layer 110 by coating.
- the second photoresist layer 120 is patterned by exposure, development or etching to form a second mask pattern in the second photoresist layer 120.
- the second mask pattern includes a plurality of second mask patterns arranged at intervals.
- the opening area 121 and the second shielding area 122 for separating each second opening area 121 .
- the second mask layer 110 exposed in the second opening region 121 is removed by using etching solution or etching gas, so as to form a pattern in the second mask layer 110 .
- the second mask layer 110 is designed as a stack, so that the second mask pattern of the second photoresist layer 120 can be transferred to the third silicon oxynitride layer 114 first, and then transferred to the second hard silicon oxide layer 114 in turn.
- the mask layer 113 , the second silicon oxynitride layer 112 and the amorphous carbon layer 111 can ensure the accuracy of pattern transfer on the second photoresist layer 120 and improve the accuracy of subsequent bit line formation.
- the second mask layer 110 with a pattern is used as a mask to remove part of the bit line conductive layer 100 and the bit line contact layer 90, which are retained.
- the lower bit line conductive layer 100 forms the bit line 103
- the remaining bit line contact layer 90 forms the bit line contact 91 .
- bit line contact 91 is provided at the bottom of each bit line 103, a part of the bit line contact 91 is in contact with the active region 11 in the substrate 10, and another part of the bit line contact 91 is in contact with the active region 11 in the substrate 10.
- the active area 11 is not in contact.
- the vertical distance between the top surface of each bit line formed in this step and the top surface of the substrate is constant, that is, That is to say, the top surface of each bit line is flush, which ensures the performance of the bit line.
- the method for preparing the semiconductor structure includes: using a deposition process to deposit the bit line conductive layer 100
- the second insulating layer 130 is formed on the second insulating layer 130 , and the material of the second insulating layer 130 includes silicon nitride, so as to prevent the electrical connection between the bit line conductive layer 100 and other devices subsequently formed on the second insulating layer 130 .
- the embodiment of the present invention also provides a semiconductor structure, which is obtained by using the method for preparing the semiconductor structure in the above embodiment, so the semiconductor structure has the beneficial effects of the above embodiment, and this embodiment will not be repeated here.
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Abstract
本公开提供一种半导体结构及其制备方法,涉及半导体技术领域,该半导体结构制备方法包括提供基底,在基底上形成依次层叠设置的第一初始导电层、牺牲层以及具有图案的第一掩膜层,牺牲层的厚度为10nm~20nm;以第一掩膜层作为掩膜版,刻蚀第一初始导电层和基底,以形成位线接触区。本公开通过降低牺牲层的厚度,在后续刻蚀牺牲层和第一初始导电层时,在将全部的牺牲层刻蚀的同时,也能够去除原本被牺牲层遮挡住部分厚度的第一初始导电层,使得被保留下来的第一初始导电层的厚度降低,进而降低位线接触区的深度,当向位线接触区沉积第二导电层时,可以避免第二导电层内形成空隙,降低位线接触的电阻,提高半导体结构的传输性能。
Description
本公开要求于2021年07月19日提交中国专利局、申请号为202110811874.5、申请名称为“半导体结构及其制备方法”的中国专利申请的优先权,其全部内容通过引用结合在本公开中。
本公开涉及半导体技术领域,尤其涉及一种半导体结构及其制备方法。
动态随机存储器(Dynamic random access memory,简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器,被广泛地应用到数据存储设备或装置中。
动态随机存储器通常包括多个重复的储存单元,每个存储单元包括一个晶体管和一个电容器,其中,晶体管的栅极与字线电连接、源极通过位线接触与位线电连接、漏极通过存储节点接触与电容器电连接,字线上的字线电压能够控制晶体管的开启与关闭,从而通过位线能够读取存储在电容器中的数据信息,或者将数据信息写入到电容器中。
但是在形成位线接触时,位线接触易形成空隙,该空隙增加位线接触的电阻,降低半导体结构的传输性能。
发明内容
本公开实施例的第一方面提供一种半导体结构的制备方法,其包括如下步骤:
提供基底;
在所述基底上形成依次层叠设置的第一初始导电层和牺牲层,所述牺牲层的厚度为10nm-20nm;
在所述牺牲层上形成具有图案的第一掩膜层;
以所述第一掩膜层作为掩膜版,去除所述牺牲层以及部分所述第一初始导电层和部分所述基底,以在所述第一初始导电层和所述基底内形成位线接触区,被保留下来的第一初始导电层构成第一导电层,所述第一导电层的厚度占所述第一初始导电层厚度的2/5~3/5;
在所述位线接触区内形成第二导电层,所述第二导电层填充满所述位线接触区。
在一些实施例中,所述位线接触区的深度为34nm~42nm。
在一些实施例中,在所述牺牲层上形成具有图案的第一掩膜层的步骤中,包括:
在所述第一掩膜层上形成第一光刻胶层;
图形化所述第一光刻胶层,以在所述第一光刻胶层内形成第一掩膜图案,所述第一掩膜图案包括间隔设置的多个第一开口区以及用于分隔各个所述第一开口区的第一遮挡区;
去除暴露在所述第一开口区内的第一掩膜层,以在所述第一掩膜层内形成图案。
在一些实施例中,在所述位线接触区内形成第二导电层的步骤中,包括:
在所述位线接触区内形成第二初始导电层,所述第二初始导电层延伸至所述位线接触区外,并覆盖所述第一导电层上;
去除部分厚度的所述第二初始导电层,被保留下来的所述第二初始导电层构成第二导电层,所述第二导电层与所述第一导电层连接成整体构成位线接触层。
在一些实施例中,采用化学机械抛光工艺去除部分厚度的所述第二初始导电层。
在一些实施例中,所述第一掩膜层包括依次层叠设置的第一硬掩膜层和第一氮氧化硅层,所述第一硬掩膜层设置在所述牺牲层上。
在一些实施例中,在提供基底的步骤之后,在所述基底上形成依层叠设置的第一初始导电层和牺牲层的步骤之前,所述制备方法还包括:
在所述基底上形成第一绝缘层。
在一些实施例中,所述第一导电层和第二导电层的材质相同,均包括多晶硅。
在一些实施例中,所述牺牲层的材质包括氧化硅;所述第一绝缘层的材质包括氮化硅。
在一些实施例中,去除部分厚度第二初始导电层,被保留下来的所述第二初始导电层构成第二导电层,所述第二导电层与所述第一导电层连接成整体构成位线接触层的步骤之后,所述制备方法还包括:
在所述位线接触层上形成依次层叠设置的位线导电层和具有图案的第二掩膜层;
以具有图案的第二掩膜层作为掩膜版,去除部分所述位线导电层和所述位线接触层,被保留下来所述位线导电层构成位线,被保留下来的所述位线接触层构成位线接触。
在一些实施例中,在所述位线接触上形成依次层叠设置的位线导电层和具有图案的第二掩膜层的步骤中,包括:
在所述第二掩膜层上形成第二光刻胶层;
图形化所述第二光刻胶层,以在所述第二光刻胶层内形成第二掩膜图案,所述第二掩膜图案包括间隔设置的多个第二开口区以及用于分隔各个所述第二开口区的第二遮挡区;
去除暴露在所述第二开口区内的第二掩膜层,以在所述第二掩膜层内形成图案。
在一些实施例中,所述第二掩膜层包括依次层叠设置的非晶碳层、第二氮氧化硅层、第二硬掩膜层和第三氮氧化硅层,所述非晶碳层设置在所述位线导电层上。
在一些实施例中,所述位线导电层包括层叠设置的第一位线导电层和第二位线导电层,所述第一位线导电层设置在所述位线接触层上。
在一些实施例中,在所述位线接触层上形成依次层叠设置的位线导电层和具有图案的第二掩膜层的步骤中,包括:
在所述位线导电层上形成第二绝缘层。
本公开实施例的第二方面提供一种半导体结构,所述半导体结构通过如上所述的半导体结构的制备方法制得。
除了上面所描述的本公开实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外,本公开实施例提供的半导体结构及其制备方法所能解决的其他技术问题、技术方案中 包含的其他技术特征以及这些技术特征带来的有益效果,将在具体实施方式中作出进一步详细的说明。
为了更清楚地说明本公开实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍,显而易见地,下面描述中的附图是本公开的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为相关技术中提供的半导体结构的结构示意图一;
图2为相关技术中提供的半导体结构的结构示意图二;
图3为本公开实施例提供的半导体结构的制备方法的流程图;
图4为本公开实施例提供的半导体结构的制备方法中形成第一初始导电层、牺牲层、第一掩膜层以及具有图案的第一光刻胶层的结构示意图;
图5为本公开实施例提供的半导体结构的制备方法中形成位线接触区的结构示意图;
图6为本公开实施例提供的半导体结构的制备方法中形成第二初始导电层结构示意图;
图7为本公开实施例提供的半导体结构的制备方法中形成位线接触层的结构示意图;
图8为本公开实施例提供的半导体结构的制备方法中形成位线导电层、第二绝缘层、第二掩膜层以及具有图案的第二光刻胶层的结构示意图;
图9为本公开实施例提供的半导体结构的制备方法中形成位线和位线接触的结构示意图。
附图标记:
10:基底; 11:有源区;
12:隔离结构; 20:第一绝缘层;
30:第一初始导电层; 31:第一导电层;
40:牺牲层; 50:第一掩膜层;
51:第一硬掩膜层; 52:第一氮氧化硅层;
60:第一光刻胶层; 61:第一遮挡区;
62:第一开口区; 70:位线接触区;
80:第二初始导电层; 81:第二导电层;
90:位线接触层; 91:位线接触;
100:位线导电层; 101:第一位线导电层;
102:第二位线导电层; 103:位线;
110:第二掩膜层; 120:第二光刻胶层;
121:第二开口区; 122:第二遮挡区;
130:第二绝缘层。
正如背景技术描述,如图1和图2所示,半导体结构中的位线接触存在空隙的问题,该空隙会增加位线接触的电阻,降低半导体结构的传输性能,经发明人研究发现,出现这种问题的原因在于,位线接触区的深度较大,在位线接触区内形成位线接触的过程,受沉积工艺的限制,位线接触内易形成空隙。
针对上述的技术问题,在本公开实施例中,通过控制牺牲层的厚度与第一初始导电层的厚度比,以降低牺牲层的厚度,这样在后续刻蚀牺牲层和第一初始导电层时,在将全部的牺牲层刻蚀的同时,也能够去除原本被牺牲层遮挡住部分厚度的第一初始导电层,使得被保留下来的第一初始导电层的厚度降低,降低位线接触区的深度,当向位线接触区沉积第二导电层时,可以避免第二导电层内形成空隙,进而降低位线接触的电阻,提高半导体结构的传输性能。
为了使本公开实施例的上述目的、特征和优点能够更加明显易懂,下面将结合本公开实施例中的附图,对本公开实施例中的技术方案进行清楚、完整地描述。显然,所描述的实施例仅仅是本公开的一部分实施例,而不是全部的实施例。基于本公开中的实施例,本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例,均属于本公开保护的范围。
图3为本公开实施例提供的半导体结构的制备方法的流程图,图4-图9为半导体结构的制备方法的各个阶段的示意图,下面结合图3-图9对半导体结构的制备方法进行详细的介绍。
本实施例对半导体结构不作限制,下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍,但本实施例并不以此为限,本实施例中的半导体结构还可以为其他的结构。
如图3所示,本公开实施例提供的半导体结构的制备方法,包括如下的步骤:
步骤S100:提供基底。
示例性地,如图4所示,基底10作为动态随机存储器的支撑部件,用于支撑设在其上的其他部件,其中,基底10可以由半导体材料制成,半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。
基底10内具有间隔设置的多个有源区11,以及用于分隔各个有源区11的隔离结构12,其中,多个有源区11可以呈矩形陈列排布,且有源区11内用于形成晶体管或者字线等半导体器件。
在本实施例中,可以通过沉积工艺在基底10上沉积第一绝缘层20,该第一绝缘层20用于实现基底10内的有源区11与后续形成的第一初始导电层的绝缘设置,其中,第一绝缘层20的材质可以包括氮化硅等绝缘材质。
步骤S200:在基底上形成依次层叠设置的第一初始导电层和牺牲层,牺牲层的厚度为10nm~20nm。
示例性地,如图4所示,可以通过沉积工艺在基底10上形成第一初始导电层30和牺牲层40,其中沉积工艺可以为原子层沉积工艺、化学气相沉积工艺或者物理气相沉积工艺。
其中,第一初始导电层30的材质可以包括多晶硅等导电材质,牺牲层40可以包括氧化硅等绝缘材质。
需要说明的是,当基底10上设置有第一绝缘层20时,第一初始导电层30需要设置在第一绝缘层20上。
步骤S300:在牺牲层上形成具有图案的第一掩膜层。
示例性地,在第一掩膜层50上形成第一光刻胶层60。
可以通过涂覆的方式,在第一掩膜层50上形成第一光刻胶层60。
然后,利用曝光、显影或者刻蚀的方式图形化第一光刻胶层60,以在第一光刻胶层60内形成第一掩膜图案,第一掩膜图案包括间隔设置的多个第一开口区62以及用于分隔各个第一开口区62的第一遮挡区61。
之后,利用刻蚀液或者刻蚀气体去除暴露在第一开口区62内的第一掩膜层50,以在第一掩膜层50内形成图案。
在本实施例中,第一掩膜层50可以单一膜层,也可以为叠层,当第一掩膜层50为叠层时,第一掩膜层50可以包括依次层叠设置的第一硬掩膜层51和第一氮氧化硅层52,第一硬掩膜层51设置在牺牲层40上。
本实施例通过将第一掩膜层50设置成叠层结构,可以保证第一光刻胶层60上图形在转移过程中的准确性,提高了后续形成位线接触区的准确性。
步骤S400:以第一掩膜层作为掩膜版,去除牺牲层以及部分第一初始导电层和基底,以在第一初始导电层和基底内形成位线接触区,被保留下来的第一初始导电层构成第一导电层,第一导电层的厚度占第一初始导电层厚度的2/5~3/5,其结构图5所示。
在此步骤中,以第一掩膜层50作为掩膜版,并利用刻蚀气体去除牺牲层40时,由于牺牲层40的厚度为10nm~20nm,与相关技术中,牺牲层40的厚度为48nm~52nm相比,降低了牺牲层40的厚度,这样在图形化牺牲层40时,原本被第一掩膜层50遮挡住的牺牲层40也会被去除掉,使得整层的牺牲层40会被完全刻蚀掉;当继续蚀刻第一初始导电层30时,原本被第一掩膜层50遮挡住的第一初始导电层30也会被去除一定的厚度,使得最终形成第一导电层31的厚度占第一初始导电层30厚度的2/5~3/5,这样可以降低位线接触区的深度,以防止后续在位线接触区形成第二导电层时形成空隙,降低位线接触的电阻的同时,提高了半导体结构的传输性能。
需要说明的是,在本实施例中,位线接触区70用于暴露出有源区11,便于后续形成的位线接触与有源区11之间形成电连接。
经过发明人反复地进行论证,若是位线接触区70的深度大于42nm,会过度增大位线接触区的深度,在后续形成第二导电层时,第二导电层内易形成空隙,影响半导体结构的传输性能;若是,位线接触区的深度小于34nm,会降低位线接触区的深度,进而降低后续形成第二导电层的高度,影响位线与有源区的电连接,降低半导体结构的传输性能,因此,本实施例通过使位线接触区的深度位于34nm~52nm之间,既可以防止第二导电层内形成空隙,也可以保证半导体结构的传输性能。
步骤S500:在位线接触区内形成第二导电层,第二导电层填充满位线 接触区。
可以通过沉积工艺向位线接触区70内沉积导电材料,该导电材料可以填充满位线接触区70,该导电材料构成第二导电层81,其中,第二导电层81的材质与第一导电层31的材质相同,可以均包括多晶硅等导电材质。
如图6所示,示例性地,可以通过化学气相沉积工艺或者物理气相沉积工艺,在位线接触区70内形成第二初始导电层80,第二初始导电层80延伸至位线接触区70外,并覆盖第一导电层31上。
之后,如图7所示,可以利用化学机械抛光工艺去除部分厚度的第二初始导电层80,被保留下来的第二初始导电层80构成第二导电层81,第二导电层81与第一导电层31连接成整体构成位线接触层90。
在本实施例中,由于通过化学机械抛光工艺对第二初始导电层80的顶面进行平坦化处理,使得第一导电层31和第二导电层81形成的位线接触层90的顶面与水平面相互平行,这样可以防止后续在位线接触层上形成位线存在高度差,保证位线的性能。
需要说明的是,在本实施例中形成的位线接触层90的顶面可以高于第一导电层31的顶面,也可以与第一导电层31的顶面平齐。
在一些实施例中,去除部分厚度的第二初始导电层,被保留下来的第二初始导电层构成第二导电层,第二导电层与第一导电层连接成整体构成位线接触层的步骤之后,制备方法还包括:
如图8所示,在位线接触层90上形成依次层叠设置的位线导电层100和具有图案的第二掩膜层110。
示例性地,可以通过沉积工艺在位线接触层90上形成位线导电层100,例如,可以在位线接触层90上依次形成层叠设置的第一位线导电层101和第二位线导电层102,第一位线导电层101设置在位线接触层90上。
其中,第一位线导电层101的材质可以包括氮化钛,第二位线导电层102的材质可以包括钨,在本实施例中,第一位线导电层101在具有导电功能的同时,也具有阻挡功能,可以防止第二位线导电层102中导电材质向基底10或者位线接触层90内扩散,保证后续形成的位线的导电性能。
待形成位线导电层100之后,可以通过沉积工艺在位线导电层100上形成第二掩膜层110。其中,第二掩膜层110可以为单一膜层,也可以为叠层,当第二掩膜层110为叠层时,第二掩膜层110可以包括依次层叠设 置的非晶碳层111、第二氮氧化硅层112、第二硬掩膜层113和第三氮氧化硅层114,非晶碳层111设置在位线导电层100上。
之后,可以在第二掩膜层110上形成第二光刻胶层120,例如,可以通过涂覆的方式,在第二掩膜层110上形成第二光刻胶层120。
再利用曝光、显影或者刻蚀的方式图形化第二光刻胶层120,以在第二光刻胶层120内形成第二掩膜图案,第二掩膜图案包括间隔设置的多个第二开口区121以及用于分隔各个第二开口区121的第二遮挡区122。
最后,利用刻蚀液或者刻蚀气体去除暴露在第二开口区121内的第二掩膜层110,以在第二掩膜层110内形成图案。
本实施例将第二掩膜层110设计为叠层,这样第二光刻胶层120的第二掩膜图案,可以先转移至第三氮氧化硅层114,然后再依次转移至第二硬掩膜层113、第二氮氧化硅层112以及非晶碳层111,这样可以保证第二光刻胶层120上图形在转移过程中的准确性,提高了后续形成位线的准确性。
如图9所示,待形成具有图案的第二掩膜层110之后,以具有图案的第二掩膜层110作为掩膜版,去除部分位线导电层100和位线接触层90,被保留下来位线导电层100构成位线103,被保留下来的位线接触层90构成位线接触91。
需要说明的是,每条位线103的底部均设置有一条位线接触91,该位线接触91的部分与基底10内的有源区11接触,另一部分位线接触91与基底10内的有源区11不接触。
在本实施例中,由于上述的工艺中对第二初始导电层进行了平坦化处理,使得在此步骤所形成每条位线的顶面距离基底的顶面的垂直距离为定值,也就是说,每条位线的顶面平齐,保证了位线的性能。
在一些实施例中,在位线接触层上形成依次层叠设置的位线导电层和具有图案的第二掩膜层的步骤中,半导体结构的制备方法包括:利用沉积工艺在位线导电层100上形成第二绝缘层130,第二绝缘层130的材质包括氮化硅,这样可以防止位线导电层100与后续在第二绝缘层130上形成其他器件之间的电连接。
本发明实施例还提供了一种半导体结构,该半导体结构采用上述实施例中半导体结构的制备方法得到,因此该半导体结构具有上述实施例中的 有益效果,本实施例在此不再多加赘述。
本说明书中各实施例或实施方式采用递进的方式描述,每个实施例重点说明的都是与其他实施例的不同之处,各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中,参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中,对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且,描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是:以上各实施例仅用以说明本公开的技术方案,而非对其限制;尽管参照前述各实施例对本公开进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
Claims (15)
- 一种半导体结构的制备方法,包括如下步骤:提供基底;在所述基底上形成依次层叠设置的第一初始导电层和牺牲层,所述牺牲层的厚度为10nm~20nm;在所述牺牲层上形成具有图案的第一掩膜层;以所述第一掩膜层作为掩膜版,去除所述牺牲层以及部分所述第一初始导电层和部分所述基底,以在所述第一初始导电层和所述基底内形成位线接触区,被保留下来的第一初始导电层构成第一导电层,所述第一导电层的厚度占所述第一初始导电层厚度的2/5~3/5;在所述位线接触区内形成第二导电层,所述第二导电层填充满所述位线接触区。
- 根据权利要求1所述的半导体结构的制备方法,其中,所述位线接触区的深度为34nm~42nm。
- 根据权利要求2所述的半导体结构的制备方法,其中,在所述牺牲层上形成具有图案的第一掩膜层的步骤中,包括:在所述第一掩膜层上形成第一光刻胶层;图形化所述第一光刻胶层,以在所述第一光刻胶层内形成第一掩膜图案,所述第一掩膜图案包括间隔设置的多个第一开口区以及用于分隔各个所述第一开口区的第一遮挡区;去除暴露在所述第一开口区内的第一掩膜层,以在所述第一掩膜层内形成图案。
- 根据权利要求3所述的半导体结构的制备方法,其中,在所述位线接触区内形成第二导电层的步骤中,包括:在所述位线接触区内形成第二初始导电层,所述第二初始导电层延伸至所述位线接触区外,并覆盖所述第一导电层上;去除部分厚度的所述第二初始导电层,被保留下来的所述第二初始导电层构成第二导电层,所述第二导电层与所述第一导电层连接成整体构成位线接触层。
- 根据权利要求4所述的半导体结构的制备方法,其中,采用化学机 械抛光工艺去除部分厚度的所述第二初始导电层。
- 根据权利要求1-5任一项所述的半导体结构的制备方法,其中,所述第一掩膜层包括依次层叠设置的第一硬掩膜层和第一氮氧化硅层,所述第一硬掩膜层设置在所述牺牲层上。
- 根据权利要求6所述的半导体结构的制备方法,其中,在提供基底的步骤之后,在所述基底上形成依层叠设置的第一初始导电层和牺牲层的步骤之前,所述制备方法还包括:在所述基底上形成第一绝缘层。
- 根据权利要求7所述的半导体结构的制备方法,其中,所述第一导电层和第二导电层的材质相同,均包括多晶硅。
- 根据权利要求8所述的半导体结构的制备方法,其中,所述牺牲层的材质包括氧化硅;所述第一绝缘层的材质包括氮化硅。
- 根据权利要求4所述的半导体结构的制备方法,其中,去除部分厚度的第二初始导电层,被保留下来的所述第二初始导电层构成第二导电层,所述第二导电层与所述第一导电层连接成整体构成位线接触层的步骤之后,所述制备方法还包括:在所述位线接触层上形成依次层叠设置的位线导电层和具有图案的第二掩膜层;以具有图案的第二掩膜层作为掩膜版,去除部分所述位线导电层和所述位线接触层,被保留下来所述位线导电层构成位线,被保留下来的所述位线接触层构成位线接触。
- 根据权利要求10所述的半导体结构的制备方法,其中,在所述位线接触上形成依次层叠设置的位线导电层和具有图案的第二掩膜层的步骤中,包括:在所述第二掩膜层上形成第二光刻胶层;图形化所述第二光刻胶层,以在所述第二光刻胶层内形成第二掩膜图案,所述第二掩膜图案包括间隔设置的多个第二开口区以及用于分隔各个所述第二开口区的第二遮挡区;去除暴露在所述第二开口区内的第二掩膜层,以在所述第二掩膜层内形成图案。
- 根据权利要求11所述的半导体结构的制备方法,其中,所述第二 掩膜层包括依次层叠设置的非晶碳层、第二氮氧化硅层、第二硬掩膜层和第三氮氧化硅层,所述非晶碳层设置在所述位线导电层上。
- 根据权利要求12所述的半导体结构的制备方法,其中,所述位线导电层包括层叠设置的第一位线导电层和第二位线导电层,所述第一位线导电层设置在所述位线接触层上。
- 根据权利要求13所述的半导体结构的制备方法,其中,在所述位线接触层上形成依次层叠设置的位线导电层和具有图案的第二掩膜层的步骤中,还包括:在所述位线导电层上形成第二绝缘层。
- 一种半导体结构,所述半导体结构通过如权利要求1-14任一项所述的半导体结构的制备方法制得。
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