WO2022266987A1 - 一种半导体器件、封装结构及电子设备 - Google Patents

一种半导体器件、封装结构及电子设备 Download PDF

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Publication number
WO2022266987A1
WO2022266987A1 PCT/CN2021/102300 CN2021102300W WO2022266987A1 WO 2022266987 A1 WO2022266987 A1 WO 2022266987A1 CN 2021102300 W CN2021102300 W CN 2021102300W WO 2022266987 A1 WO2022266987 A1 WO 2022266987A1
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Prior art keywords
isolation
semiconductor device
corner
region
isolation groove
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PCT/CN2021/102300
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English (en)
French (fr)
Inventor
简中祥
徐向明
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华为技术有限公司
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Priority to PCT/CN2021/102300 priority Critical patent/WO2022266987A1/zh
Priority to CN202180099748.XA priority patent/CN117581378A/zh
Publication of WO2022266987A1 publication Critical patent/WO2022266987A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Definitions

  • the present application relates to the technical field of electronic equipment, in particular to a semiconductor device, a packaging structure and electronic equipment.
  • the application provides a semiconductor device, a packaging structure and electronic equipment, so as to improve the yield and reliability of the semiconductor device.
  • the present application provides a semiconductor device
  • the semiconductor device may include a semiconductor substrate, a first well region is disposed above the semiconductor substrate, and the first well region may be doped with a first type of impurity.
  • a source diffusion region and a drain diffusion region which are spaced apart are arranged in the first well region, and the source diffusion region and the drain diffusion region can be doped with second type impurities respectively.
  • a first insulating layer is arranged above the first well region, and the first insulating layer is located between the source diffusion region and the drain diffusion region, and a gate is arranged above the first insulating layer, and the gate can be used to control the source and the drain.
  • the on-off state between the drain may further include a first isolation trench, which is disposed in the first well region, and is used to reduce electrical interference between the semiconductor device and surrounding devices.
  • the first isolation groove may also be provided with a relief structure for stress relief.
  • the stress of the first isolation groove during the process can be relieved by setting the relief structure, the risk of failure of the first isolation groove can be reduced, and the good performance of the semiconductor device can be improved. rate and reliability.
  • first sidewalls may be provided around the gate, and the first sidewalls may isolate the gate from the source diffusion region and the drain diffusion region, thereby preventing leakage between electrodes.
  • the first isolation groove may be an annular structure, and the source diffusion region and the drain diffusion region are located in the annular region defined by the first isolation groove.
  • the first isolation trench can form a continuous isolation structure on the peripheral side of the first well region, which is beneficial to improve the isolation effect of the semiconductor device.
  • first isolation grooves there may be multiple first isolation grooves, and the plurality of first isolation grooves may be sequentially arranged at intervals along a direction away from the gate.
  • the number of the first isolation slots may be 3-6.
  • the first isolation groove may be a rectangular ring structure
  • the relief structure may be a chamfer structure provided at each corner of the first isolation groove.
  • the chamfer structure can realize a smooth transition at the corner of the first isolation groove, thereby relieving the stress of the corner of the first isolation groove during processing.
  • the first isolation groove may be a rectangular ring structure
  • the relief structure may be a rounded structure provided at each corner of the first isolation groove.
  • the rounded corner structure can connect the adjacent sides of the first isolation groove through a circular arc, so as to realize a smooth transition at the corner of the first isolation groove, and relieve the stress of the corner of the first isolation groove during processing.
  • the above-mentioned relief structure may be a partition. In this way, when forming the first isolation groove, the stress of the first isolation groove during the process can be relieved by interrupting at the location of the partition, reducing Risk of failure of the first isolation slot.
  • the first isolation groove can be a rectangular ring structure, and the first isolation groove can include a first corner, a second corner, a third corner and a fourth corner, wherein the first corner and the third corner form Diagonally arranged, the second corner and the fourth corner are arranged diagonally. Since the stress gathering points of the first isolation groove are mainly concentrated at the four corners, in order to relieve the stress at the corners, the partition part may be specifically arranged at one or more corners of the first isolation groove.
  • the partition part of one of the first isolation grooves when there are multiple first isolation grooves, among two adjacent first isolation grooves, the partition part of one of the first isolation grooves can be arranged at the first corner, and the partition part of the other first isolation groove The partition part of an isolation groove may be disposed at at least one of the second corner part, the third corner part and the fourth corner part.
  • the partition parts of two adjacent first isolation grooves can be misplaced, so that the entire isolation structure formed by a plurality of first isolation grooves can achieve effective isolation at any circumferential position, and then in Under the premise of not affecting the isolation effect of the first isolation groove, the stress of the first isolation groove during the process of processing is relieved, and the yield rate and service reliability of the semiconductor device are improved.
  • each first isolation groove when there are multiple first isolation grooves, each first isolation groove can be provided with two partitions respectively, and in two adjacent first isolation grooves, one of the first isolation grooves
  • the two partitions of the slot can be respectively arranged at the first corner and the third corner thereof, and the two partitions of another first isolation slot can be respectively arranged at the second corner and the fourth corner thereof.
  • This arrangement can also make the partition portions of two adjacent first isolation grooves misaligned, so that the entire isolation structure formed by the plurality of first isolation grooves can achieve effective isolation at any circumferential position.
  • the depth of the first isolation trench can be greater than the depth of the first well region, so that the bottom of the first isolation trench can extend into the semiconductor substrate, which is conducive to maintaining the high resistance characteristics of the semiconductor substrate , thereby reducing the substrate loss of the semiconductor device and improving the linearity of the semiconductor device.
  • the depth of the first isolation groove may be 4-6 um.
  • the semiconductor device may further include an epitaxial layer, the epitaxial layer may be disposed above the semiconductor substrate, and the first well region may be disposed above the epitaxial layer.
  • the semiconductor device can obtain a more excellent and controllable crystal structure, which helps to improve the performance of the semiconductor device.
  • the semiconductor device may further include a second isolation trench, the second isolation trench is disposed in the first well region, and the depth of the second isolation trench is greater than the thickness of the epitaxial layer, so that the second isolation trench can be avoided There is an epitaxial layer material under the substrate to form a low-resistance leakage channel, so that the advantages of the high-resistance semiconductor substrate can be effectively maintained and the substrate loss of the semiconductor device can be reduced.
  • the second isolation groove may also be in an annular structure, and the source diffusion region and the drain diffusion region are also located in the annular region defined by the second isolation groove.
  • a continuous isolation structure can also be formed on the peripheral side of the first well region in the second isolation groove, which is beneficial to improve the isolation effect on the semiconductor device.
  • the second isolation trench may coincide with an end of the first isolation trench facing away from the semiconductor substrate.
  • first isolation grooves when there are multiple first isolation grooves, under the second isolation grooves, between two adjacent first isolation grooves may have the same intrinsic characteristics as the semiconductor substrate, That is to say, the silicon material between the two adjacent first isolation grooves maintains the same doping condition as that of the semiconductor substrate, which is conducive to maintaining the high resistance characteristics of the semiconductor substrate, thereby reducing the substrate loss of the semiconductor device.
  • a guard ring may be provided on the edge of the first well region, and the first and second isolation trenches may be located between the active region and the guard ring.
  • the first type of impurity can be doped in the guard ring, and the first guard ring can be grounded or connected to a power supply.
  • the guard ring can reduce the parasitic resistance of the semiconductor substrate and enhance the isolation effect on the MOS transistor.
  • the first isolation trench may be filled with silicon dioxide and polysilicon in sequence, and the second isolation trench may be filled with silicon dioxide.
  • the polysilicon in the first isolation trench can be used to maintain the potential of the first isolation trench and prevent parasitic leakage caused by the unstable potential of the first isolation trench.
  • the first isolation trench may specifically be a deep trench isolation (DTI) structure
  • the second isolation trench may specifically be a shallow trench isolation (STI) structure.
  • DTI deep trench isolation
  • STI shallow trench isolation
  • the semiconductor device may specifically be a BiCMOS device.
  • the SiGe base region of the SiGe HBT can be set above the epitaxial layer, and the collector region doped with the second type of impurities is arranged in the epitaxial layer, and the collector region is located on both sides of the SiGe base region; the SiGe base region An emitter and a base are arranged above the region, the base is arranged on both sides of the emitter, and a second insulating layer may be arranged between the emitter and the base.
  • the material of the emitter and the base can be polysilicon
  • the material of the second insulating layer can be silicon dioxide.
  • a second side wall can be provided on the side of the emitter
  • a third side wall can be provided on the side of the base
  • the second side wall can isolate the emitter from the base and the collector
  • the third side wall can separate the The base is isolated from the collector to prevent leakage between the poles.
  • a buried layer can also be provided under the epitaxial layer, and N-type impurities can be doped in the buried layer, and the collector regions on both sides can be electrically connected to the buried layer respectively, so as to reduce the density of the collector region. resistor in series and provides a low resistance path for current flow to the collector.
  • the edge of the SiGe HBT can also be provided with an annular third isolation groove, which can be specifically arranged on the periphery of the collector region, and the third isolation groove can be sequentially filled with silicon dioxide with polysilicon.
  • the third isolation groove can reduce the electrical interference between the HBT and surrounding devices, and improve the working reliability of the HBT.
  • the first type of impurity can be a P-type impurity, at this time, the second type of impurity can be an N-type impurity; or, the first type of impurity can be an N-type impurity, at this time, the second type of impurity
  • the impurities are P-type impurities.
  • the present application provides a semiconductor device, which may include a semiconductor substrate, a first well region is disposed above the semiconductor substrate, and the first well region may be doped with first type impurities.
  • a source diffusion region and a drain diffusion region which are spaced apart are arranged in the first well region, and the source diffusion region and the drain diffusion region can be doped with second type impurities respectively.
  • a first insulating layer is arranged above the first well region, and the first insulating layer is located between the source diffusion region and the drain diffusion region, and a gate is arranged above the first insulating layer, and the gate can be used to control the source and the drain. The on-off state between the drain.
  • the conductor device may further include a first isolation groove, which is disposed in the first well region, and is used to reduce electrical interference between the semiconductor device and surrounding devices.
  • the depth of the first isolation trench can be greater than the depth of the first well region, so that the bottom of the first isolation trench can extend into the semiconductor substrate, thereby helping to maintain the high-resistance characteristics of the semiconductor substrate, thereby reducing the Substrate loss of semiconductor devices, and improving the linearity of semiconductor devices.
  • the present application also provides a packaging structure, which includes a substrate, leads, and the semiconductor device in any of the aforementioned possible implementations, wherein the semiconductor device is arranged on one side of the substrate, and the leads are arranged on the substrate and On the same side of the semiconductor device, the lead is arranged around the semiconductor device, and one end of the lead is electrically connected to the semiconductor device.
  • the semiconductor substrate of the semiconductor device can maintain high resistance characteristics, so the substrate loss of the semiconductor device can be reduced, and the linearity of the semiconductor device can be improved.
  • the stress of the first isolation groove during the process can be effectively relieved, thereby improving the yield and reliability of the semiconductor device, and further improving the packaging efficiency. structural reliability.
  • the present application also provides an electronic device, which may include a circuit board and the packaging structure in the foregoing embodiments, the packaging structure may be fixed on the circuit board by means of welding, etc., and the circuit board avoids the packaging structure
  • Signal pins can also be set in the area, and the signal pins can be connected to the other end of the lead, so that the package structure can be connected to other devices through the traces on the circuit board, thereby realizing the connection between the semiconductor device and the external circuit. Because the semiconductor device has the advantages of low loss, high linearity, etc., and the yield and reliability of the semiconductor device are high, the performance stability of the electronic device is improved.
  • FIG. 1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • Fig. 3 is a schematic cross-sectional structure diagram of the semiconductor device shown in Fig. 2 at A-A;
  • FIG. 4 is a schematic diagram of another cross-sectional structure of the semiconductor device shown in FIG. 2 at A-A;
  • FIG. 5 is a schematic diagram of another cross-sectional structure of the semiconductor device shown in FIG. 2 at A-A;
  • FIG. 6 is a schematic diagram of another cross-sectional structure of the semiconductor device shown in FIG. 2 at A-A;
  • FIG. 7 is a flow chart of a manufacturing method of the semiconductor device shown in FIG. 2;
  • FIG. 8 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a packaging structure provided by an embodiment of the present application.
  • 100-semiconductor device 10-semiconductor substrate; 20-epitaxial layer; 21-first well region; 31-active region;
  • MOS transistors Transistors with a metal-oxide-semiconductor (MOS) structure are referred to as MOS transistors for short, and MOS transistors are divided into P-type MOS transistors and N-type MOS transistors, that is, PMOS transistors and NMOS transistors.
  • An integrated circuit composed of MOS transistors is called a MOS integrated circuit, and a complementary MOS integrated circuit composed of a PMOS transistor and an NMOS transistor is called a CMOS-IC (complementary MOS integrated circuit).
  • the MOS transistor is a unipolar semiconductor device whose electric field effect controls the current. It basically does not take current or the current is very small at its input terminal. It has the characteristics of high input impedance, low noise, good thermal stability, and simple manufacturing process. It is often used in In large-scale and very large-scale integrated circuits.
  • a bipolar junction transistor commonly known as a triode, is an electronic device with three terminals, made of three semiconductors with different doping degrees.
  • the charge flow in the transistor is mainly due to the carrier in the PN Diffusion and drift motion at the (PN junction) junction.
  • the operation of this type of transistor involves the flow of both electrons and holes, and is therefore called a bipolar transistor.
  • BJT can amplify signals, and has better power control, high-speed operation and durability. It is often used to form amplifier circuits, drive speakers or motors and other equipment.
  • BiCMOS technology is a process technology that integrates BJT and CMOS on the same chip.
  • BiCMOS combines the advantages of BJT and CMOS devices, and is used for the development of high-speed and high-performance VLSI for various communications, information processing and digital communications. Opened up a new path.
  • SiGe silicon-germanium alloy
  • SiGe heterojunction bipolar transistor is the core of SiGe BiCMOS process technology.
  • SiGe HBT is to add a small amount of germanium to the base area of silicon-based BJT.
  • the base area is made of SiGe material, which can significantly improve the performance of the device. Performance, so that SiGe HBT has excellent characteristics such as low noise, high gain, high linearity and high breakdown voltage, which is more suitable for the design of low noise amplifiers and power amplifiers.
  • WIFI wireless communication technology
  • SOI silicon-on-insulator
  • SiGe BiCMOS is formed on bulk silicon (bulk Si), and the device and substrate There is no dielectric layer between them as isolation, and the substrate loss will inevitably occur during the operation of the device. Therefore, how to obtain a low insertion loss and high linearity radio frequency switching device has become a key problem to be solved urgently in the field of radio frequency.
  • FIG. 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application.
  • the semiconductor device 100 provided by the embodiment of the present application may specifically be a MOS transistor.
  • the semiconductor device 100 may include a semiconductor substrate 10.
  • the semiconductor substrate 10 may specifically be a silicon substrate, and the semiconductor substrate 10 may be doped with Mixed with the first type of impurities.
  • the first type impurity can be N-type impurity or P-type impurity, understandably, if the first type impurity is N-type impurity, then the formed semiconductor substrate 10 is an N-type semiconductor substrate; if the first type impurity is P-type impurities, the formed semiconductor substrate 10 is a P-type semiconductor substrate.
  • the first well region 21 can be formed on the semiconductor substrate 10 through an ion implantation process, and the ions implanted in the first well region 21 can specifically be first-type impurities. It can be understood that if the first-type impurities are P-type impurities, then The formed first well region is a P-well (P-WELL), and if the first type impurity is an N-type impurity, the formed first well region 21 is an N-well (N-WELL).
  • An active region 31 of a MOS transistor is disposed in the first well region 21, a source diffusion region 32 and a drain diffusion region 33 are disposed in the active region 31, and the source diffusion region 32 and the drain diffusion region 33 are arranged at intervals, and The source diffusion region 32 and the drain diffusion region 33 are respectively doped with second type impurities.
  • a first insulating layer 34 is disposed above the active region 31 , the first insulating layer 34 is located between the source diffusion region 32 and the drain diffusion region 33 , and a gate 35 is disposed above the first insulating layer 34 .
  • a first spacer 36 may be provided around the gate 35 , and the first sidewall 36 may isolate the gate 35 from the source diffusion region 32 and the drain diffusion region 33 .
  • the material of the gate 35 can be specifically polysilicon
  • the material of the first insulating layer 34 can be specifically silicon dioxide
  • the material of the first sidewall 36 can be specifically silicon dioxide
  • the second The side wall 36 can also be made of silicon dioxide at the bottom and silicon nitride at the top.
  • the source diffusion region 32 and the drain diffusion region 33 are respectively N diffusion regions.
  • N-type conductive channel, the MOS transistor formed at this time is NMOS.
  • the source diffusion region 32 and the drain diffusion region 33 are respectively P diffusion regions.
  • P-type conduction channel, the MOS transistor formed at this time is PMOS.
  • first well regions 21 may be multiple, and these first well regions 21 may include P wells or N wells, so that a plurality of NMOS and NW wells are formed on the semiconductor substrate 10
  • Multiple PMOS, NMOS and PMOS can be connected in a specific way to form various CMOS circuits. Since the CMOS circuit is a common and well-known circuit structure in the art, the specific arrangement form thereof will not be repeated here.
  • the edge of the first well region 21 may also be provided with a guard ring 40 , and the guard ring 40 may be doped with first type impurities.
  • the guard ring 40 can be electrically connected to the first well region 21 and grounded through the first well region 21 .
  • the guard ring 40 can be connected to the power supply voltage (VDD) through the first well region 21 .
  • VDD power supply voltage
  • the guard ring 40 can reduce the parasitic resistance of the semiconductor substrate 10 and enhance the isolation effect on the MOS transistor, thereby reducing the risk of latch-up effect.
  • the semiconductor device may further include an epitaxial layer 20 disposed between the semiconductor substrate 10 and the first well region 21 . That is, the epitaxial layer 20 can be disposed above the semiconductor substrate 10 , and the first well region 21 is disposed in the epitaxial layer 20 , and the depth of the first well region 21 can be greater than the thickness of the epitaxial layer 20 .
  • the doping type of the impurity in the epitaxial layer 20 and the semiconductor substrate 10 may be the same, that is, the epitaxial layer 20 may also be doped with the first type of impurity.
  • the doping concentration of the first type impurity in the epitaxial layer 20 may be different from the doping concentration of the first type impurity in the semiconductor substrate 10, for example, the doping concentration of the first type impurity in the epitaxial layer 20 may be lower than that of the semiconductor substrate 10.
  • the epitaxial layer 20 and the semiconductor substrate 10 may also be doped with different types of impurities, for example, the epitaxial layer 20 may be doped with a second type of impurity.
  • the second type of impurities can also be N-type impurities or P-type impurities.
  • the first type of impurities are N-type impurities
  • the second type of impurities are P-type impurities
  • the first type of impurities are P-type impurities
  • the second type impurity is N-type impurity.
  • the doping concentration of the second-type impurity in the epitaxial layer 20 can be designed with reference to the aforementioned scheme for doping the first-type impurity, and will not be repeated here.
  • a first isolation trench 50 may also be provided on the periphery of the active region 31, and the first isolation trench 50 may specifically be It is located between the active region 31 and the guard ring 40 to isolate the active region 31 from the guard ring 40 .
  • the first isolation groove 50 is filled with silicon dioxide and polysilicon in sequence, that is, the end of the first isolation groove 50 near the bottom is filled with silicon dioxide. , the end close to the notch is filled with polysilicon.
  • the polysilicon filled in the first isolation trench 50 can be used to maintain the potential in the first isolation trench 50 and prevent parasitic leakage caused by the unstable potential of the first isolation trench 50 .
  • the first isolation trench 50 can be roughly in the form of a ring structure, and the first isolation trench 50 is arranged on the periphery of the active region of the MOS transistor, that is, the active region 31 is located in the annular structure defined by the first isolation trench 50. In the region, a continuous isolation structure can be formed on the peripheral side of the active region 31, which is beneficial to improve the isolation effect on the MOS transistor.
  • the depth of the first isolation trench 50 may be greater than the depth of the first well region 21, and since the depth of the first well region 21 is greater than the thickness of the epitaxial layer 20, in the embodiment of the present application, the bottom of the first isolation trench 50 It can extend into the semiconductor substrate 10 , this design is beneficial to maintain the high resistance characteristic of the semiconductor substrate 10 , thereby reducing the substrate loss of the semiconductor device 100 and improving the linearity of the semiconductor device 100 .
  • the depth of the first isolation groove 50 may be between 4-6 um, for example, the depth of the first isolation groove may be 4 um, 5 um or 6 um, and so on.
  • the number of the first isolation trenches 50 may be multiple, so as to improve the isolation effect between adjacent MOS transistors.
  • a plurality of first isolation trenches 50 are sequentially arranged at intervals in a direction away from the active region 31 . That is, on the periphery of the active region 31 , a plurality of first isolation trenches 50 are radially arranged.
  • the number of the first isolation grooves 50 may be 3-6. Exemplarily, the number of the first isolation grooves 50 may be 3, 4, 5 or 6, which is not specifically limited in the present application.
  • FIG. 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • a second isolation trench 60 may be provided between the active region 31 and the guard ring 40 .
  • the second isolation groove 60 can also be an annular structure, and the second isolation groove 60 can be filled with silicon dioxide.
  • the depth of the second isolation trench 60 is smaller than the depth of the first isolation trench 50, therefore, the isolation formed by the first isolation trench 50 can also be called deep trench isolation (Deep Trench Isolation, DTI),
  • the isolation formed by the second isolation trench 60 may also be called shallow trench isolation (Shallow Trench Isolation, STI).
  • the second isolation groove 60 may coincide with the end of the first isolation groove 50 away from the semiconductor substrate.
  • the depth of the second isolation groove 60 can be greater than the thickness of the epitaxial layer 20. Compared with the scheme in which the depth of the second isolation groove 60 is smaller than the thickness of the epitaxial layer 20, this design can avoid the epitaxial layer existing under the second isolation groove 60.
  • the material of the layer 20 is called a low-resistance leakage channel, so that the advantages of the high-resistance semiconductor substrate 10 can be more effectively maintained, the substrate loss of the semiconductor device 100 can be reduced, and the linearity of the semiconductor device 100 can be improved.
  • FIG. 3 is a schematic cross-sectional structure diagram at A-A of the semiconductor device shown in FIG. 2 .
  • the region between two adjacent first isolation trenches 50 can be avoided during ion implantation into the first well region 21, so that the second isolation Below the groove 60, between the two adjacent first isolation grooves 50 may have the same doping conditions as the semiconductor substrate 10, that is, maintain the same intrinsic characteristics as the semiconductor substrate 10, such setting is also conducive to maintaining the semiconductor substrate 10.
  • the high resistance characteristic of the substrate 10 further reduces the substrate loss of the semiconductor device 100 and improves the linearity of the semiconductor device 100 .
  • the first isolation groove 50 can be provided with a relief structure, which can relieve the stress of the first isolation groove 50 during the process and reduce the failure of the first isolation groove 50. risk, which in turn can improve the yield and reliability of semiconductor devices.
  • the relief structure may be a partition 51.
  • the stress during the process can be relieved by interrupting the location of the partition 51, thereby reducing the stress of the second isolation groove 50. A risk of isolation trench 50 failure.
  • the first isolation groove 50 can be substantially a rectangular ring structure, and at this time, the second isolation groove 60 can also be a rectangular ring, and the aspect ratio of the second isolation groove 60 is the same as that of the first isolation groove 50. substantially equal, so that a relatively uniform isolation structure can be formed on the four sides of the active region 31 .
  • the stress accumulation points of the first isolation groove 50 are mainly concentrated at the four corners, so in order to relieve the stress at the corners,
  • the above-mentioned partition portion 51 may be specifically arranged at a corner of the first isolation groove 50 , and at this time, the partition portion 51 is approximately in an L-shaped structure.
  • the four corners of the first isolation groove 50 can be respectively the first corner 501, the second corner 502, the third corner 503 and the fourth corner 504, wherein the first corner 501 and the third corner The corners 503 are arranged diagonally, and the second corner 502 and the fourth corner 504 are arranged diagonally.
  • the first corners 501 of each first isolation groove 50 are arranged in opposite positions, or it can be understood that the first corners 501 of each first isolation groove 50
  • the corners 501 are the corners pointing in the same direction, and the same applies to the second corner 502 , the third corner 503 and the fourth corner 504 , which will not be described one by one here.
  • At least one corner of the first isolation groove 50 can be provided with the above-mentioned partition 51.
  • a partition 51 is provided at the corner 501 .
  • the partition portion 51 of the first isolation groove 50 may be arranged at other corners except the first corner portion 501, For example, one of the second corner 502, the third corner 503 and the fourth corner 504, or two of the second corner 502, the third corner 503 and the fourth corner 504, of course Partitions may also be provided at the second corner 502 , the third corner 503 and the fourth corner 504 respectively.
  • the two adjacent first isolation grooves 50 can be provided with partitions 51 at the corners of different directions, so that the partitions 51 of the two adjacent first isolation grooves 50 are misaligned, so that from a plurality of first isolation grooves 50
  • the dislocation design of the partition portion 51 of each first isolation groove 50 enables the isolation structure as a whole to achieve effective isolation at any circumferential position, so as not to affect the first isolation structure.
  • the stress of each first isolation trench 50 during the process can be relieved, thereby improving the yield rate and service reliability of the semiconductor device 100 .
  • FIG. 4 is a schematic diagram of another cross-sectional structure at A-A of the semiconductor device shown in FIG. 2 .
  • the first isolation groove 50 can be provided with two partitions 51, and the two partitions 51 can be respectively arranged at a pair of opposite corners of the first isolation groove 50, and adjacent to each other.
  • the two partitions 51 of one of the first isolation slots 50 can be respectively arranged at the first corner 501 and the third corner 503, and the two partitions of the other first isolation slot 50 51 may be disposed at the second corner 502 and the fourth corner 504, respectively.
  • This arrangement can also make the partitions of two adjacent first isolation grooves 50 misaligned, so that the entire isolation structure formed by a plurality of first isolation grooves 50 can achieve effective isolation at any circumferential position. Under the premise of not affecting the isolation effect of the first isolation trenches 50 , the stress of each first isolation trench 50 during the process can be relieved, thereby improving the yield rate and service reliability of the semiconductor device 100 .
  • FIG. 5 is a schematic diagram of another cross-sectional structure at A-A of the semiconductor device shown in FIG. 2 .
  • the relief structure can be a chamfer structure 52 arranged at the corner of the first isolation groove 50.
  • This design allows two adjacent sides of the first isolation groove 50 to pass through a The hypotenuse is connected, and the angle between the hypotenuse and two adjacent sides is an obtuse angle.
  • the chamfer structure 52 can realize a gentle transition at the corner of the first isolation groove 50, Therefore, the stress of the corners of the first isolation trench 50 during the process can be relieved.
  • the four corners of the first isolation groove 50 can be designed as chamfered structures 52 , so as to further relieve the stress of the first isolation groove 50 during processing and reduce the risk of failure of the first isolation groove 50 .
  • FIG. 6 is a schematic diagram of another cross-sectional structure at A-A of the semiconductor device shown in FIG. 2 .
  • the relief structure can be a rounded corner structure 53 arranged at the corner of the first isolation groove 50.
  • This design allows two adjacent sides of the first isolation groove 50 to pass through a The arcs are connected, so that a smooth transition can be realized at the corners of the first isolation groove 50 , and the stress of the corners of the first isolation groove 50 during the process can be relieved.
  • the four corners of the first isolation groove 50 can be designed as rounded corners 53 , so as to further relieve the stress of the first isolation groove 50 during processing and reduce the risk of failure of the first isolation groove 50 .
  • FIG. 7 is a flowchart of a manufacturing method of the semiconductor device shown in FIG. 2 .
  • the manufacturing method of the semiconductor device 100 provided in the embodiment of the present application includes the following steps:
  • the semiconductor substrate 10 may specifically be a silicon substrate, and the semiconductor substrate 10 may be doped with first type impurities.
  • the epitaxial layer 20 may be doped with the first type of impurity, and may also be doped with the second type of impurity, which is not limited in the present application.
  • Step 103 on the side of the epitaxial layer 20 facing away from the semiconductor substrate 10 , an annular first isolation trench 50 is formed by etching through a mask patterning process, and the first isolation trench 50 is filled with silicon dioxide and polysilicon in sequence.
  • the depth of the first isolation trench 50 may be greater than the thickness of the epitaxial layer 20 .
  • the number of the first isolation grooves 50 may be multiple, and the plurality of first isolation grooves 50 may be arranged radially.
  • Step 104 on the side of the epitaxial layer 20 facing away from the semiconductor substrate 10 , an annular second isolation trench 60 is formed by etching through a mask patterning process, and silicon dioxide is filled in the second isolation trench 60 .
  • the inner side of the first isolation trench 50 is the defined active region 31 of the semiconductor device 100 .
  • the depth of the second isolation trench 60 is smaller than that of the first isolation trench 50 , and the second isolation trench 60 may coincide with an end of the first isolation trench 50 away from the semiconductor substrate 10 .
  • the depth of the first isolation groove 50 can be greater than the thickness of the epitaxial layer 20, which can avoid the formation of a low-resistance leakage channel due to the existence of the material of the epitaxial layer 20 under the second isolation groove 50, thereby maintaining the high-resistance semiconductor substrate more effectively. 10, reducing the substrate loss of the semiconductor device 100, and improving the linearity of the semiconductor device 100.
  • Step 105 performing ion implantation on the side of the epitaxial layer 20 facing away from the semiconductor substrate 10 through a mask patterning process to form a first well region 21 doped with a first type of impurity.
  • the region where the first isolation trench 50 and the second isolation trench 60 are located can be avoided during ion implantation, so that under the second isolation trench 60, two adjacent first isolation trenches 50 can be separated.
  • this design is also conducive to maintaining the high resistance characteristics of the semiconductor substrate 10 .
  • the depth of the first well region 21 may be greater than the thickness of the epitaxial layer 20 and less than the depth of the first isolation trench 50, so that the bottom of the first isolation trench 50 can extend into the semiconductor substrate 10. This design is beneficial The high resistance characteristic of the semiconductor substrate 10 is maintained, thereby reducing the substrate loss of the semiconductor device 100 and improving the linearity of the semiconductor device 100 .
  • Step 106 forming a first insulating layer 34 on the active region 31 through a mask patterning process, and forming a gate 35 on the first insulating layer 34 through a mask patterning process.
  • the material of the first insulating layer 34 may specifically be silicon dioxide, and the material of the gate 35 may specifically be polysilicon.
  • Step 107 forming first sidewalls 36 around the gate 35 .
  • the material of the first side wall 36 can be silicon dioxide, or the lower part can be made of silicon dioxide, and the upper part can be made of silicon nitride.
  • Step 108 Perform ion implantation in the active region 31 through a mask patterning process to form the source diffusion region 32 and the drain diffusion region 33 doped with the second type of impurities, and the source diffusion region 32 and the drain diffusion region 33 respectively located on both sides of the first insulating layer.
  • FIG. 8 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • the semiconductor device provided in this embodiment may specifically be a SiGe BiCMOS device, and the semiconductor device may also include a semiconductor substrate 10 and an epitaxial layer 20 disposed on the semiconductor substrate 10.
  • the epitaxial layer 20 On the epitaxial layer 20, besides MOS transistors, one or more SiGe HBTs may also be formed.
  • MOS transistors besides MOS transistors, one or more SiGe HBTs may also be formed.
  • the collector electrode 71 of the SiGe HBT can be formed in the epitaxial layer 20 by an ion implantation process, and the collector electrode 71 can be doped with a second type of impurity. Taking the second type of impurity as an N-type impurity as an example, The formed collector 71 is an N-type collector. In this embodiment, the epitaxial layer 20 can reduce the resistance of the collector 71 , thereby improving the DC characteristics and radio frequency characteristics of the HBT device.
  • a SiGe base region 72 is disposed above the epitaxial layer 20 , and the SiGe base region 72 is located between the two collector electrodes 71 .
  • An emitter 73 and a base 74 are arranged above the SiGe base region 72, the emitter 73 is arranged between the two bases 74, and the left and right sides of the emitter 73 can extend above the two bases 74, and the emitter 73
  • a second insulating layer 75 is provided between the base electrode 74 .
  • a second sidewall 76 can be provided on the peripheral side of the emitter 73, and the second sidewall 76 can isolate the emitter 73 from the base 74 and the collector 71; similarly, the peripheral side of the base 74 can be provided The third side wall 77 can isolate the base electrode 74 from the collector electrode 71 .
  • the material of the emitter 73 and the base 74 can be specifically polysilicon
  • the material of the second insulating layer 75 can be specifically silicon dioxide
  • the material of the second side wall 76 and the third side wall 77 Specifically, the material may be silicon dioxide, or, the lower part of the second side wall 76 and the third side wall 77 may be made of silicon dioxide, and the upper part may be made of silicon nitride.
  • an N-type buried layer 78 may also be provided under the epitaxial layer 20, and the collectors 71 on both sides may be electrically connected to the N-type buried layer respectively, so as to reduce the series resistance of the collector 71 and provide Electrode 71 provides a low resistance path for electrical current.
  • the periphery of the collector electrode 71 can also be provided with an annular third isolation groove 80.
  • Silicon dioxide and polysilicon may be filled in sequence, that is, the end of the third isolation trench 80 near the bottom is filled with silicon dioxide, and the end near the slot opening is filled with polysilicon.
  • the third isolation groove 80 can reduce the electrical interference between the HBT and surrounding devices, and improve the working reliability of the HBT.
  • the MOS transistor and the HBT are integrated on the same chip, and by controlling the depths of the first isolation trench 50 and the second isolation trench 60 on the periphery of the MOS transistor, the advantages of the high-resistance semiconductor substrate 10 are effectively maintained, and the semiconductor substrate 10 is reduced. substrate loss of the device 100, and improve the linearity of the semiconductor device 100.
  • the stress of each first isolation groove 50 during the process can be effectively relieved without affecting the isolation effect of the first isolation grooves 50. , thereby improving the yield and reliability of the semiconductor device 100 .
  • the embodiment of the present application also provides a packaging structure, which may include a substrate 200, leads 300, and the semiconductor device 100 in any of the foregoing possible embodiments, and the semiconductor device 100 may be disposed on the substrate 200 On one side of the substrate 200 , the lead 300 is disposed on the same side as the semiconductor device 100 , and the lead 300 is disposed around the semiconductor device 100 , and one end of the lead 300 is electrically connected to the semiconductor device 100 .
  • the semiconductor device 100 may specifically be a MOS transistor or a SiGe BiCMOS device.
  • the semiconductor substrate of the semiconductor device can maintain high resistance characteristics, so the substrate loss of the semiconductor device can be reduced, and the linearity of the semiconductor device can be improved.
  • the stress of the first isolation groove during the process can be effectively relieved, thereby improving the yield rate and reliability of the semiconductor device, and further improving the packaging performance. structural reliability.
  • the embodiment of the present application also provides an electronic device, which may be a communication device, a server, a supercomputer, or a router, a switch, and other devices in the prior art.
  • the electronic device may include a circuit board and the package structure in the foregoing embodiments, the package structure may be fixed on the circuit board by means of welding, etc., signal pins may be provided on the circuit board avoiding the package structure, and the signal pins may be connected to the leads
  • the other end of the semiconductor device is electrically connected, so that the packaging structure can be connected to other devices through the traces on the circuit board, thereby realizing the connection between the semiconductor device and the external circuit. Because the semiconductor device has the advantages of low loss, high linearity, etc., and the yield and reliability of the semiconductor device are high, the performance stability of the electronic device is improved.

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Abstract

本申请公开了一种半导体器件、封装结构及电子设备，以降低半导体器件的***损耗，以及提高半导体器件的线性度。半导体器件包括半导体衬底，半导体衬底上方设置有掺杂第一类型杂质的第一阱区，第一阱区内设置有掺杂第二类型杂质的源极扩散区和漏极扩散区，第一阱区的上方设置有位于源极扩散区与漏极扩散区之间的第一绝缘层，第一绝缘层的上方设置有栅极；还包括第一隔离槽，第一隔离槽设置于第一阱区，第一隔离槽设置有用于缓解应力的缓解结构。

Description

一种半导体器件、封装结构及电子设备 技术领域
本申请涉及电子设备技术领域，尤其涉及一种半导体器件、封装结构及电子设备。
背景技术
芯片的多个功能模块的集成随着摩尔定律的演进和通信技术的标准的推进，在光电和微波高频等技术应用中发挥越来越重要的作用。
考虑到芯片的低成本、高集成度的要求，通常需要将多个功能模块比如低噪声放大器(low noise amplifier，LNA)、功率放大器(power amplifier，PA)以及开关电路全部集成于同一芯片，因此如何获得低***损耗、高线性度的指标的芯片功能的半导体器件成为当前亟待解决的一个关键问题。
发明内容
本申请提供了一种半导体器件、封装结构及电子设备，以提高半导体器件的良率及使用可靠性。
第一方面，本申请提供了一种半导体器件，该半导体器件可包括半导体衬底，半导体衬底的上方设置有第一阱区，第一阱区内可掺杂有第一类型杂质。第一阱区内设置有相间隔的源极扩散区和漏极扩散区，源极扩散区和漏极扩散区内可分别掺杂有第二类型杂质。第一阱区的上方设置有第一绝缘层，该第一绝缘层位于源极扩散区和漏极扩散区之间，第一绝缘层的上方设置有栅极，栅极可用于控制源极和漏极之间的通断状态。该半导体器件还可以包括第一隔离槽，第一隔离槽设置于第一阱区内，用以减小该半导体器件与周围器件之间的电学干扰。另外，第一隔离槽还可设置用于缓解应力的缓解结构。
上述方案中的半导体器件，在形成第一隔离槽时，通过设置缓解结构可以缓解第一隔离槽在工艺加工过程中的应力，减小第一隔离槽失效的风险，进而可以提高半导体器件的良率及使用可靠性。
在一些可能的实施方案中，栅极的周侧还可以设置第一侧墙，第一侧墙可以将栅极与源极扩散区及漏极扩散区隔离，从而防止各极之间漏电。
在具体设置第一隔离槽时，第一隔离槽可以为环形结构，源极扩散区和漏极扩散区位于第一隔离槽所界定的环形区域内。这样第一隔离槽在第一阱区的周侧可以形成连续的隔离结构，从而有利于提高对半导体器件的隔离效果。
为了提高相邻的半导体器件之间的隔离效果，第一隔离槽的数量可以为多个，多个第一隔离槽可沿远离栅极的方向依次间隔设置。具体设置时，第一隔离槽的数量可以为3～6个。
在一些可能的实施方案中，第一隔离槽可以为矩形环结构，上述缓解结构可以为设置于第一隔离槽的各个角部的倒角结构。相较于直角结构，采用倒角结构可以在第一隔离槽的角部实现平缓过渡，从而可以缓解第一隔离槽的角部在工艺加工中的应力。
在一些可能的实施方案中，第一隔离槽可以为矩形环结构，上述缓解结构可以为设置 于第一隔离槽的各个角部的圆角结构。圆角结构可以将第一隔离槽相邻的边通过圆弧进行连接，从而在第一隔离槽的角部实现平缓过渡，缓解第一隔离槽的角部在工艺加工中的应力。
在一些可能的实施方案中，上述缓解结构可以为隔断部，这样，在形成第一隔离槽时，通过在隔断部的位置进行中断可以缓解第一隔离槽在工艺加工过程中的应力，减小第一隔离槽失效的风险。
具体设置时，第一隔离槽可以为矩形环结构，第一隔离槽可包括第一角部、第二角部、第三角部及第四角部，其中，第一角部与第三角部呈对角设置，第二角部与第四角部呈对角设置。由于第一隔离槽的应力聚集点主要集中在四个角部的位置，为了缓解角部的应力，上述隔断部具体可以设置在第一隔离槽的其中一个或多个角部。
在一个具体的实施方案中，第一隔离槽的数量为多个时，相邻的两个第一隔离槽中，其中一个第一隔离槽的隔断部可设置在第一角部，另外一个第一隔离槽的隔断部可设置在第二角部、第三角部及第四角部中的至少一个角部。采用这种设计，相邻的两个第一隔离槽的隔断部能够相错位，从而使多个第一隔离槽所构成的隔离结构整体在任意周向的位置都能够实现有效的隔离，进而在不影响第一隔离槽的隔离效果的前提下，缓解第一隔离槽在工艺加工过程中的应力，提高半导体器件的良率及使用可靠性。
在另一个具体的实施方案中，第一隔离槽的数量为多个时，每个第一隔离槽可分别设置两个隔断部，相邻的两个第一隔离槽中，其中一个第一隔离槽的两个隔断部可分别设置在其第一角部和第三角部，另外一个第一隔离槽的两个隔断部可分别设置在其第二角部和第四角部。这种设置方式也可以使得相邻的两个第一隔离槽的隔断部相错位，从而使多个第一隔离槽所构成的隔离结构整体在任意周向的位置都能够实现有效的隔离。
在一些可能的实施方案中，第一隔离槽的深度可以大于第一阱区的深度，这样，第一隔离槽的底部可以延伸到半导体衬底内，从而有利于保持半导体衬底的高阻特性，进而可以降低半导体器件的衬底损耗，以及提高半导体器件的线性度。具体设置时，第一隔离槽的深度可以为4～6um。
在一些可能的实施方案中，半导体器件还可以包括外延层，外延层可以设置于半导体衬底的上方，第一阱区则可以设置外延层的上方。通过设置外延层可以使半导体器件获得更加优异、可控的晶体结构，有助于提高半导体器件的性能。
在一些可能的实施方案中，半导体器件还可以包括第二隔离槽，第二隔离槽设置于第一阱区，且第二隔离槽的深度大于外延层的厚度，这样可以避免由于第二隔离槽的下方存在外延层材料而构成低阻漏电通道，从而可以有效地保持高阻半导体衬底的优势，降低半导体器件的衬底损耗。
在具体设置第二隔离槽时，第二隔离槽也可以为环形结构，源极扩散区和漏极扩散区同样位于第二隔离槽所界定的环形区域内。这样在第二隔离槽在第一阱区的周侧也可以形成连续的隔离结构，从而有利于提高对半导体器件的隔离效果。
在一些可能的实施方案中，第二隔离槽可与第一隔离槽背离半导体衬底的一端重合。
在一些可能的实施方案中，第一隔离槽的数量为多个时，在第二隔离槽的下方，相邻的两个第一隔离槽之间可以具有与半导体衬底相同的本征特性，也就是说，相邻的两个第一隔离槽之间的硅材料保持与半导体衬底相同的掺杂条件，从而有利于保持半导体衬底的高阻特性，进而可以降低半导体器件的衬底损耗。
在一些可能的实施方案中，第一阱区的边缘可设置有保护环，上述第一隔离槽与第二隔离槽可位于有源区与保护环之间。保护环内可掺杂有第一类型杂质，且第一保护环可接地或者接电源设置。保护环可以降低半导体衬底的寄生电阻，增强对MOS晶体管的隔离效果。
在一些可能的实施方案中，第一隔离槽内可依次填充有二氧化硅与多晶硅，第二隔离槽内可填充有二氧化硅。其中，第一隔离槽内的多晶硅可用于维持第一隔离槽的电位，防止由于第一隔离槽的电位不稳而导致寄生漏电现象。
在一些可能的实施方案中，上述第一隔离槽具体可以为深槽隔离(DTI)结构，第二隔离槽具体可以为浅槽隔离(STI)结构。
在一些可能的实施方案中，半导体器件具体可以为BiCMOS器件。在避开MOS晶体管的区域，外延层的上方可设置SiGe HBT的SiGe基区，外延层内设置掺杂有第二类型杂质的集电区，集电区位于SiGe基区的两侧；SiGe基区的上方设置有发射极和基极，基极设置在发射极的两侧，且发射极与基极之间可设置有第二绝缘层。示例性地，发射极与基极的材质可以为多晶硅，第二绝缘层的材质可以为二氧化硅。
另外，发射极的周侧可以设置第二侧墙，基极的周侧可以设置第三侧墙，第二侧墙可以将发射极与基极以及集电极之间隔离，第三侧墙可以将基极与集电极之间隔离，从而防止各极之间漏电。
在一些可能的实施方案中，外延层的下方还可以设置埋层，埋层内可掺杂N型杂质，两侧的集电区可分别与埋层电性连接，以减小集电区的串联电阻，并为集电区提供电流低阻通道。
在一些可能的实施方案中，SiGe HBT的边缘还可设置有环形的第三隔离槽，该第三隔离槽具体可设置在集电区的***，第三隔离槽内可依次填充有二氧化硅与多晶硅。第三隔离槽可以减小HBT与周围器件之间的电学干扰，提高HBT的工作可靠性。
在一些可能的实施方案中，第一类型杂质可以为P型杂质，此时，第二类型杂质则可以为N型杂质；或者，第一类型杂质可以为N型杂质，此时，第二类型杂质则为P型杂质。
第二方面，本申请提供了一种半导体器件，该半导体器件可包括半导体衬底，半导体衬底的上方设置有第一阱区，第一阱区内可掺杂有第一类型杂质。第一阱区内设置有相间隔的源极扩散区和漏极扩散区，源极扩散区和漏极扩散区内可分别掺杂有第二类型杂质。第一阱区的上方设置有第一绝缘层，该第一绝缘层位于源极扩散区和漏极扩散区之间，第一绝缘层的上方设置有栅极，栅极可用于控制源极和漏极之间的通断状态。导体器件还可以包括第一隔离槽，第一隔离槽设置于第一阱区内，用以减小该半导体器件与周围器件之间的电学干扰。具体设置时，第一隔离槽的深度可以大于第一阱区的深度，这样，第一隔离槽的底部可以延伸到半导体衬底内，从而有利于保持半导体衬底的高阻特性，进而可以降低半导体器件的衬底损耗，以及提高半导体器件的线性度。
第三方面，本申请还提供了一种封装结构，该封装结构包括基板、引线以及前述任一可能的实施方案中的半导体器件，其中，半导体器件设置在基板的一面，引线设置在基板上与半导体器件同侧的一面，且引线围绕半导体器件设置，引线的一端与半导体器件电性连接。半导体器件的半导体衬底可以保持高阻特性，因此可以降低半导体器件的衬底损耗，并提高半导体器件的线性度。另外，通过在对半导体器件的第一隔离槽的结构进行改进， 使得第一隔离槽在工艺加工过程中的应力得以有效缓解，从而可以提高半导体器件的良率及使用可靠性，进而可以提高封装结构的可靠性。
第四方面，本申请还提供了一种电子设备，该电子设备可以包括电路板以及前述实施方案中的封装结构，封装结构可以通过焊接等方式固定于电路板上，电路板上避开封装结构的区域还可以设置信号管脚，信号管脚可以与引线的另一端连接，以使封装结构能够通过电路板上的走线与其它器件相连接，进而实现半导体器件与外部电路的连接。由于半导体器件具有低损耗、高线性度等优点，且半导体器件的良率及使用可靠性较高，因此该电子设备的性能稳定性得以提升。
附图说明
图1为本申请实施例提供的一种半导体器件的结构示意图；
图2为本申请实施例提供的另一种半导体器件的结构示意图；
图3为图2中所示的半导体器件在A-A处的一种截面结构示意图；
图4为图2中所示的半导体器件在A-A处的另一种截面结构示意图；
图5为图2中所示的半导体器件在A-A处的另一种截面结构示意图；
图6为图2中所示的半导体器件在A-A处的另一种截面结构示意图；
图7为图2中所示的半导体器件的制作方法流程图；
图8为本申请实施例提供的又一种半导体器件的结构示意图；
图9为本申请实施例提供的封装结构的结构示意图。
附图标记：
100-半导体器件；10-半导体衬底；20-外延层；21-第一阱区；31-有源区；
32-源极扩散区；33-漏极扩散区；34-第一绝缘层；35-栅极；36-第一侧墙；40-保护环；
50-第一隔离槽；60-第二隔离槽；51-隔断部；501-第一角部；502-第二角部；
503-第三角部；504-第四角部；52-倒角结构；53-圆角结构；71-集电极；72-基区；
73-发射极；74-基极；75-第二绝缘层；76-第二侧墙；77-第三侧墙；78-埋层；
80-第三隔离槽；200-基板；300-引线。
具体实施方式
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步地详细描述。
金属-氧化物-半导体(metal-oxide-semiconductor，MOS)结构的晶体管简称MOS晶体管，MOS晶体管有P型MOS管和N型MOS之分，即PMOS管和NMOS管。由MOS管构成的集成电路称为MOS集成电路，而由PMOS管和NMOS管共同构成的互补型MOS集成电路即为CMOS-IC(complementary MOS integrated circuit)。MOS晶体管是电场效应控制电流大小的单极型半导体器件，在其输入端基本不取电流或电流极小，具有输入阻抗高、噪声低、热稳定性好、制造工艺简单等特点，常应用于大规模和超大规模集成电路中。
双极性晶体管(bipolar junction transistor，BJT)俗称三极管，是一种具有三个终端的电子器件，由三部分掺杂程度不同的半导体制成，晶体管中的电荷流动主要是由于载流子在PN(PN junction)结处的扩散作用和漂移运动。这种晶体管在工作时会涉及电子和空穴两 种载流子的流动，也因此被称为双极性晶体管。BJT能够放大信号，并且具有较好的功率控制、高速工作以及耐久能力，常被用来构成放大器电路、驱动扬声器或者电动机等设备。
BiCMOS技术是将BJT和CMOS集成在同一块芯片上的工艺技术，BiCMOS集中了BJT和CMOS两种器件的优点，为发展高速、高性能的各种通信、信息处理、数字通信用超大规模集成电路开辟了一条崭新的道路。随着第五代移动通信技术(5th generation mobile communication technology，5G)通信逐渐普及，硅锗合金(SiGe)BiCMOS工艺在光电和微波高频应用中发挥着越来越重要的作用。SiGe异质结双极晶体管(heterojunction bipolar transistor，HBT)是SiGe BiCMOS制程技术的核心关键，SiGe HBT是在硅基BJT的基区加入少量的锗成分，基区采用SiGe材料，可以显著提高器件的性能，使SiGe HBT具有低噪声、高增益、高线性度以及高的击穿电压等优异特性，较为适合低噪声放大器与功率放大器的设计。
在无线通信技术(WIFI)射频前端领域中，WIFI芯片在成本以及产品集成度等方面具有较高的要求，在设计时往往会将低噪声放大器、功率放大器以及开关电路等全部集成在同一芯片上，因此不可避免地会产生***损耗；此外，相较于绝缘沉底上的硅(silicon-on-insulator，SOI)技术，SiGe BiCMOS是在体硅(bulk Si)上形成的，器件与衬底之间没有介质层作为隔离，器件在工作过程中不可避免地产生衬底损耗。因此，如何获得低***损耗、高线性度的射频开关器件，成为射频领域亟待解决的关键性问题。
图1为本申请实施例提供的一种半导体器件的结构示意图。参考图1所示，本申请实施例提供的半导体器件100具体可以为MOS管，该半导体器件100可以包括半导体衬底10，半导体衬底10具体可以为硅衬底，半导体衬底10中可掺杂有第一类型杂质。第一类型杂质可以为N型杂质或者P型杂质，可以理解的，若第一类型杂质为N型杂质，则所形成的半导体衬底10即为N型半导体衬底；若第一类型杂质为P型杂质，则所形成的半导体衬底10即为P型半导体衬底。
半导体衬底10上可通过离子注入工艺形成第一阱区21，第一阱区21内所注入的离子具体可以为第一类型杂质，可以理解的，若第一类型杂质为P型杂质，则所形成的第一阱区为P阱(P-WELL)，若第一类型杂质为N型杂质，则所形成的第一阱区21为N阱(N-WELL)。
第一阱区21内设置有MOS晶体管的有源区31，有源区31内设置有源极扩散区32和漏极扩散区33，源极扩散区32与漏极扩散区33间隔设置，且源极扩散区32与漏极扩散区33内分别掺杂有第二类型杂质。有源区31的上方还设置有第一绝缘层34，该第一绝缘层34位于源极扩散区32与漏极扩散区33之间，第一绝缘层34的上方设置有栅极35。另外，栅极35的周侧还可以设置第一侧墙36，第一侧墙36可以将栅极35与源极扩散区32以及漏极扩散区33之间进行隔离。示例性地，本申请实施例中，栅极35的材质具体可以为多晶硅，第一绝缘层34的材质具体可以为二氧化硅，第一侧墙36的材质具体可以为二氧化硅，或者第一侧墙36也可以下部为二氧化硅材质，上部为氮化硅材质。
当第一阱区21为P阱时，源极扩散区32与漏极扩散区33分别为N扩散区，当MOS晶体管导通时，源极扩散区32与漏极扩散区33之间可形成N型导电沟道，此时所形成的MOS晶体管即为NMOS。当第一阱区21为N阱时，源极扩散区32与漏极扩散区33分别为P扩散区，当MOS晶体管导通时，源极扩散区32与漏极扩散区33之间可形成P型导电沟道，此时所形成的MOS晶体管即为PMOS。
需要说明的是，第一阱区21的数量可以为多个，这些第一阱区21中既可以包括有P阱，也可以包括有N阱，从而在半导体衬底10上形成多个NMOS和多个PMOS，NMOS与PMOS可通过特定的方式连接构成各种CMOS电路。由于CMOS电路为本领域常见且公知的电路结构，故对其内具体设置形式不在进行赘述。
另外，第一阱区21的边缘还可以设置有保护环40，保护环40内可掺杂有第一类型杂质。当第一阱区21为P阱时，该保护环40可与第一阱区21电性连接，并通过第一阱区21接地设置。当第一阱区21为N阱时，该保护环40则可通过第一阱区21与电源电压(VDD)连接。保护环40可以降低半导体衬底10的寄生电阻，增强对MOS晶体管的隔离效果，从而降低产生闩锁效应的风险。
可以理解的，在一些实施例中，半导体器件还可以包括设置于半导体衬底10与第一阱区21之间的外延层20。也即，外延层20可设置于半导体衬底10的上方，第一阱区21则设置于外延层20中，且第一阱区21的深度可大于外延层20的厚度。其中，外延层20与半导体衬底10中杂质的掺杂类型可以相同，也即外延层20中也可掺杂有第一类型杂质。具体实施时，外延层20中第一类型杂质的掺杂浓度与半导体衬底10中第一类型杂质的掺杂浓度可以不同，例如外延层20中第一类型杂质的掺杂浓度可以小于半导体衬底10中第一类型杂质的掺杂浓度。
在其它一些实施例中，外延层20与半导体衬底10中也可掺杂不同类型的杂质，比如外延层20中可掺杂有第二类型杂质。应当理解的是，第二类型杂质也可以为N型杂质或者P型杂质，当第一类型杂质为N型杂质时，第二类型杂质则为P型杂质；当第一类型杂质为P型杂质时，第二类型杂质则为N型杂质。外延层20中第二类型杂质的掺杂浓度可以参考前述掺杂第一类型杂质时的方案进行设计，此处不再进行赘述。
继续参考图1，在本申请实施例中，为了减小相邻的MOS晶体管之间的电学干扰，有源区31的***还可设置有第一隔离槽50，该第一隔离槽50具体可位于有源区31与保护环40之间，以将有源区31与保护环40进行隔离。具体设置时，从第一隔离槽50的底部至槽口的方向，第一隔离槽50内依次填充有二氧化硅与多晶硅，也即，第一隔离槽50靠近底部的一端填充有二氧化硅，靠近槽口的一端填充有多晶硅。其中，第一隔离槽50内所填充的多晶硅可用于维持第一隔离槽50内的电位，防止由于第一隔离槽50的电位不稳而导致寄生漏电现象。
在具体设计时，第一隔离槽50可大致为环形结构，且第一隔离槽50设置在MOS晶体管的有源区的***，也即，有源区31位于第一隔离槽50所界定的环形区域内，从而使有源区31的周侧可以形成连续的隔离结构，有利于提高对MOS晶体管的隔离效果。第一隔离槽50的深度可大于第一阱区21的深度，而由于第一阱区21的深度要大于外延层20的厚度，因此，在本申请实施例中，第一隔离槽50的底部可以延伸至半导体衬底10内，这种设计有利于保持半导体衬底10的高阻特性，进而降低半导体器件100的衬底损耗，以及提高半导体器件100的线性度。具体实施时，第一隔离槽50的深度可以在4～6um之间，示例性地，第一隔离槽的深度可以为4um，5um或者6um，等等。
需要说明的是，在本申请实施例中，第一隔离槽50的数量可以为多个，以提高相邻的MOS晶体管之间的隔离效果。具体实施时，多个第一隔离槽50在远离有源区31的方向依次间隔设置。也即，在有源区31的***，多个第一隔离槽50呈辐射状排布。第一隔离槽50的数量可以为3～6个，示例性地，第一隔离槽50的数量可以为3个，4个，5个 或者6个，本申请对此不作具体限制。
图2为本申请实施例提供的另一种半导体器件的结构示意图。参考图2所示，为了进一步提高相邻的MOS晶体管之间的隔离效果，除第一隔离槽50之外，有源区31与保护环40之间还可以设置有第二隔离槽60。该第二隔离槽60也可以为环形结构，第二隔离槽60内可填充二氧化硅。在本申请实施例中，第二隔离槽60的深度小于第一隔离槽50的深度，因此，由第一隔离槽50所形成的隔离还可以称为深槽隔离(Deep Trench Isolation，DTI)，由第二隔离槽60所形成的隔离还可以称为浅槽隔离(Shallow Trench Isolation，STI)。具体设置时，第二隔离槽60可与第一隔离槽50的背离半导体衬底的一端重合。另外，第二隔离槽60的深度可以大于外延层20的厚度，相较于第二隔离槽60的深度小于外延层20的厚度的方案，这种设计可以避免第二隔离槽60下方存在的外延层20材料称为低阻漏电通道，从而可以更有效地保持高阻半导体衬底10的优势，降低半导体器件100的衬底损耗，以及提高半导体器件100的线性度。
图3为图2中所示的半导体器件在A-A处的一种截面结构示意图。一并参考图2和图3所示，在一些实施例中，在对第一阱区21离子注入时可以避开相邻的两个第一隔离槽50之间的区域，从而在第二隔离槽60下方，相邻的两个第一隔离槽50之间可以具有与半导体衬底10相同的掺杂条件，也即与半导体衬底10保持相同的本征特性，这样设置同样有利于保持半导体衬底10的高阻特性，进而降低半导体器件100的衬底损耗，以及提高半导体器件100的线性度。
请继续参考图3，在本申请实施例中，第一隔离槽50可以设置有缓解结构，利用缓解结构可以缓解第一隔离槽50在工艺加工过程中的应力，减小第一隔离槽50失效的风险，进而可以提高半导体器件的良率及使用可靠性。
在一个具体的实施方案中，缓解结构可以为隔断部51，这样，在形成第一隔离槽50时，通过在隔断部51的位置进行中断就可以缓解工艺加工过程中的应力，进而减小第一隔离槽50失效的风险。
具体设置时，第一隔离槽50可大致为矩形环结构，此时，第二隔离槽60也可以为矩形环，且第二隔离槽60的长宽比与第一隔离槽50的长宽比大致相等，这样可以在有源区31的四侧形成较为均匀的隔离结构。可以理解的，对于矩形环状的第一隔离槽50来说，在工艺加工过程中，第一隔离槽50的应力聚集点主要集中在四个角部的位置，因此为了缓解角部的应力，上述隔断部51具体可设置在第一隔离槽50的角部，这时，隔断部51大致呈L形结构。
具体设计时，第一隔离槽50的四个角部可分别为第一角部501、第二角部502、第三角部503和第四角部504，其中，第一角部501与第三角部503呈对角设置，第二角部502与第四角部504呈对角设置。应当说明的是，本申请实施例的多个第一隔离槽50中，各个第一隔离槽50的第一角部501分别对位设置，或者可以理解为，各个第一隔离槽50的第一角部501分别为指向同一方向的角部，同理第二角部502、第三角部503及第四角部504，此处不再一一说明。
在一个具体的实施例中，第一隔离槽50的至少一个角部可设置有上述隔断部51，例如，在图3所示的实施例中，最外侧的第一隔离槽50可以在第一角部501处设置隔断部51。这时，对于与最外侧的第一隔离槽50相邻的第一隔离槽50来说，该第一隔离槽50的隔断部51可以设置在除第一角部501之外的其它角部，例如第二角部502、第三角部 503与第四角部504中的其中一个角部，或者第二角部502、第三角部503与第四角部504中的其中两个角部，当然也可以在第二角部502、第三角部503与第四角部504分别设置隔断部。也即，相邻的两个第一隔离槽50可分别在不同指向的角部设置隔断部51，从而使相邻的两个第一隔离槽50的隔断部51相错位，这样从多个第一隔离槽50所构成的隔离结构整体来看，各个第一隔离槽50的隔断部51的错位设计使得隔离结构整体在任意周向的位置都能够实现有效的隔离，从而可以在不影响第一隔离槽50的隔离效果的前提下，缓解各个第一隔离槽50在工艺加工过程中的应力，进而可以提高半导体器件100的良率及使用可靠性。
图4为图2中所示的半导体器件在A-A处的另一种截面结构示意图。参考图4所示，在该实施例中，第一隔离槽50可以设置两个隔断部51，这两个隔断部51可分别设置在第一隔离槽50的一对对角处，且相邻的两个第一隔离槽50中，其中一个第一隔离槽50的两个隔断部51可分别设置在第一角部501和第三角部503，另外一个第一隔离槽50的两个隔断部51可分别设置在第二角部502和第四角部504。这种设置方式也可以使得相邻的两个第一隔离槽50的隔断部相错位，从而使多个第一隔离槽50所构成的隔离结构整体在任意周向的位置都能够实现有效的隔离，在不影响第一隔离槽50的隔离效果的前提下，缓解各个第一隔离槽50在工艺加工过程中的应力，进而可以提高半导体器件100的良率及使用可靠性。
图5为图2中所示的半导体器件在A-A处的另一种截面结构示意图。参考图5所示，在该实施例中，缓解结构可以为设置在第一隔离槽50的角部的倒角结构52，这种设计使得第一隔离槽50相邻的两条边可以通过一斜边进行连接，且该斜边与相邻的两条边之间的夹角均为钝角，相较于直角结构，采用倒角结构52可以在第一隔离槽50的角部实现平缓过渡，从而可以缓解第一隔离槽50的角部在工艺加工中的应力。示例性地，第一隔离槽50的四个角部均可以设计为倒角结构52，从而可以进一步缓解第一隔离槽50在工艺加工中的应力，减小第一隔离槽50失效的风险。
图6为图2中所示的半导体器件在A-A处的另一种截面结构示意图。参考图6所示，在该实施例中，缓解结构可以为设置在第一隔离槽50的角部的圆角结构53，这种设计使得第一隔离槽50相邻的两条边可以通过一个圆弧进行连接，从而可以在第一隔离槽50的角部实现平缓过渡，缓解第一隔离槽50的角部在工艺加工中的应力。类似地，第一隔离槽50的四个角部均可以设计为圆角结构53，从而可以进一步缓解第一隔离槽50在工艺加工中的应力，减小第一隔离槽50失效的风险。
图7为图2中所示的半导体器件的制作方法流程图。一并参考图2和图7所示，在本申请实施例提供的半导体器件100的制备方法，包括以下步骤：
步骤101、形成半导体衬底10。半导体衬底10具体可以为硅衬底，且半导体衬底10中可掺杂有第一类型杂质。
步骤102、在半导体衬底10之上形成外延层20。外延层20中可掺杂有第一类型杂质，也可掺杂有第二类型杂质，本申请对此不作限制。
步骤103、在外延层20背向半导体衬底10的一侧，通过掩膜构图工艺刻蚀形成环形的第一隔离槽50，并在第一隔离槽50内依次填充二氧化硅与多晶硅。第一隔离槽50的深度可以大于外延层20的厚度。另外，第一隔离槽50的数量可以为多个，多个第一隔离槽50可以以辐射状排布。
步骤104、在外延层20背向半导体衬底10的一侧，通过掩膜构图工艺刻蚀形成环形的第二隔离槽60，并在第二隔离槽60内填充二氧化硅。第一隔离槽50的内侧即为界定出的半导体器件100的有源区31。具体设置时，第二隔离槽60的深度小于第一隔离槽50的深度，第二隔离槽60可与第一隔离槽50的背离半导体衬底10的一端重合。另外，第一隔离槽50的深度可大于外延层20的厚度，这样可以避免由于第二隔离槽50下方存在外延层20材料而构成低阻漏电通道，从而可以更有效地保持高阻半导体衬底10的优势，降低半导体器件100的衬底损耗，以及提高半导体器件100的线性度。
步骤105、在外延层20的背向半导体衬底10的一侧，通过掩膜构图工艺进行离子注入，形成掺杂有第一类型杂质的第一阱区21。需要说明的是，在进行离子注入时可以避开第一隔离槽50及第二隔离槽60所在的区域，这样在第二隔离槽60下方，相邻的两个第一隔离槽50之间可以具有与半导体衬底10相同的掺杂条件，也即与半导体衬底10保持相同的本征特性，这种设计同样有利于保持半导体衬底10的高阻特性。另外，第一阱区21的深度可以大于外延层20的厚度，并小于第一隔离槽50的深度，从而使第一隔离槽50的底部可以延伸至半导体衬底10内，这种设计有利于保持半导体衬底10的高阻特性，进而降低半导体器件100的衬底损耗，以及提高半导体器件100的线性度。
步骤106、在有源区31之上通过掩模构图工艺形成第一绝缘层34，以及在第一绝缘层34之上通过掩模构图工艺形成栅极35。第一绝缘层34的材质具体可以为二氧化硅，栅极35的材质具体可以为多晶硅。
步骤107、在栅极35的周侧形成第一侧墙36。第一侧墙36的材质可以为二氧化硅，或者也可以下部为二氧化硅材质，上部为氮化硅材质。
步骤108、在有源区31内通过掩模构图工艺进行离子注入，形成掺杂有第二类型杂质的源极扩散区32和漏极扩散区33，源极扩散区32与漏极扩散区33分别位于第一绝缘层的两侧。
图8为本申请实施例提供的又一种半导体器件的结构示意图。参考图8所示，本实施例提供的半导体器件具体可以为SiGe BiCMOS器件，该半导体器件同样可以包括半导体衬底10以及设置于半导体衬底10之上的外延层20。在外延层20上，除MOS晶体管之外，还可形成有一个或多个SiGe HBT。其中，半导体衬底10、外延层20以及MOS晶体管的具体结构可以参阅上述实施例的设置方式，这里不再赘述。
在避开MOS晶体管的区域，外延层20中可通过离子注入工艺形成SiGe HBT的集电极71，集电极71内可掺杂有第二类型杂质，以第二类型杂质为N型杂质为例，所形成的集电极71即为N型集电极。在本实施例中，外延层20可以降低集电极71的电阻，从而提升HBT器件的直流特性和射频特性。
外延层20的上方设置有SiGe基区72，SiGe基区72位于两个集电极71之间。SiGe基区72的上方设置有发射极73和基极74，发射极73设置在两个基极74之间，且发射极73的左右两侧可延伸至两个基极74上方，发射极73与基极74之间设置有第二绝缘层75。另外，发射极73的周侧可以设置第二侧墙76，第二侧墙76可以将发射极73与基极74以及集电极71之间进行隔离；同理，基极74的周侧可以设置第三侧墙77，第三侧墙77可以将基极74与集电极71之间进行隔离。示例性地，本申请实施例中，发射极73与基极74的材质具体可以为多晶硅，第二绝缘层75的材质具体可以为二氧化硅，第二侧墙76及 第三侧墙77的材质具体可以为二氧化硅，或者，第二侧墙76及第三侧墙77也可以下部为二氧化硅材质，上部为氮化硅材质。
需要说明的是，外延层20的下方还可以设置N型埋层78，两侧的集电极71可分别与该N型埋层电性连接，以减小集电极71的串联电阻，并为集电极71提供电流低阻通道。
另外，在本申请实施例中，集电极71的***还可设置有环形的第三隔离槽80，具体设置时，从第三隔离槽80的底部至槽口的方向，第三隔离槽80内可依次填充有二氧化硅与多晶硅，也即，第三隔离槽80靠近底部的一端填充有二氧化硅，靠近槽口的一端填充有多晶硅。第三隔离槽80可以减小HBT与周围器件之间的电学干扰，提高HBT的工作可靠性。
本实施例将MOS晶体管和HBT集成在同一芯片上，通过对MOS晶体管***的第一隔离槽50及第二隔离槽60的深度进行控制，有效地保持高阻半导体衬底10的优势，降低半导体器件100的衬底损耗，以及提高半导体器件100的线性度。另外，通过对第一隔离槽50的角部进行隔断或者进行结构优化，可以在不影响第一隔离槽50的隔离效果的前提下，有效缓解各个第一隔离槽50在工艺加工过程中的应力，进而可以提高半导体器件100的良率及使用可靠性。
参考图9所示，本申请实施例还提供了一种封装结构，该封装结构可以包括基板200、引线300以及前述任一可能的实施例中的半导体器件100，半导体器件100可以设置于基板200的其中一面，引线300设置于基板200上与半导体器件100同侧的一面，且引线300围绕半导体器件100设置，引线300的一端与半导体器件100电性连接。在一些实施例中，半导体器件100具体可以为MOS晶体管或者SiGe BiCMOS器件。半导体器件的半导体衬底可以保持高阻特性，因此可以降低半导体器件的衬底损耗，并提高半导体器件的线性度。另外，通过在对半导体器件的第一隔离槽的结构进行改进，使得第一隔离槽在工艺加工过程中的应力得以有效缓解，从而可以提高半导体器件的良率及使用可靠性，进而可以提高封装结构的可靠性。
本申请实施例还提供了一种电子设备，该电子设备可以为现有技术中的通讯设备、服务器、超级计算机或者路由器、交换机等设备。电子设备可以包括电路板以及前述实施例中的封装结构，封装结构可以通过焊接等方式固定于电路板上，电路板上避开封装结构的区域则可以设置信号管脚，信号管脚可以与引线的另一端电性连接，以使封装结构能够通过电路板上的走线与其它器件相连接，进而实现半导体器件与外部电路的连接。由于半导体器件具有低损耗、高线性度等优点，且半导体器件的良率及使用可靠性较高，因此该电子设备的性能稳定性得以提升。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (25)

  1. 一种半导体器件，其特征在于，包括半导体衬底，所述半导体衬底上方设置有掺杂第一类型杂质的第一阱区，所述第一阱区内设置有掺杂第二类型杂质的源极扩散区和漏极扩散区，所述第一阱区的上方设置有位于所述源极扩散区与所述漏极扩散区之间的第一绝缘层，所述第一绝缘层的上方设置有栅极；
    还包括第一隔离槽，所述第一隔离槽设置于所述第一阱区，所述第一隔离槽设置有用于缓解应力的缓解结构。
  2. 如权利要求1所述的半导体器件，其特征在于，所述第一隔离槽为环形结构，所述源极扩散区和所述漏极扩散区位于所述第一隔离槽界定的环形区域内。
  3. 如权利要求2所述的半导体器件，其特征在于，所述第一隔离槽的数量为多个，多个所述第一隔离槽沿远离所述栅极的方向依次间隔设置。
  4. 如权利要求2或3所述的半导体器件，其特征在于，所述第一隔离槽为矩形环结构，所述缓解结构为设置于所述第一隔离槽的各个角部的倒角结构。
  5. 如权利要求2或3所述的半导体器件，其特征在于，所述第一隔离槽为矩形环结构，所述缓解结构为设置于所述第一隔离槽的各个角部的圆角结构。
  6. 如权利要求2或3所述的半导体器件，其特征在于，所述缓解结构为隔断部。
  7. 如权利要求6所述的半导体器件，其特征在于，所述第一隔离槽为矩形环结构，多个所述第一隔离槽分别包括第一角部、第二角部、第三角部和第四角部，所述第一角部与第三角部呈对角设置，所述第二角部与第四角部呈对角设置；
    所述第一隔离槽的至少一个角部设置有所述隔断部。
  8. 如权利要求7所述的半导体器件，其特征在于，所述第一隔离槽的数量为多个时，相邻的两个所述第一隔离槽中，其中一个所述第一隔离槽的第一角部设置有所述隔断部，另外一个所述第一隔离槽的第二角部、第三角部及第四角部中的至少一个角部设置有所述隔断部。
  9. 如权利要求7所述的半导体器件，其特征在于，所述第一隔离槽的数量为多个时，相邻的两个所述第一隔离槽中，其中一个所述第一隔离槽的第一角部和第三角部分别设置有所述隔断部，另外一个所述隔离槽的第二角部和第四角部分别设置有所述隔断部。
  10. 如权利要求1～9任一项所述的半导体器件，其特征在于，所述第一隔离槽的深度大于所述第一阱区的深度。
  11. 如权利要求10所述的半导体器件，其特征在于，所述第一隔离槽的深度为4～6um。
  12. 如权利要求1～11任一项所述的半导体器件，其特征在于，所述第一隔离槽的数量为3～6个。
  13. 如权利要求1～12任一项所述的半导体器件，其特征在于，所述半导体器件还包括外延层，所述外延层设置于所述半导体衬底的上方，所述第一阱区设置于所述外延层的上方。
  14. 如权利要求13所述的半导体器件，其特征在于，所述半导体器件还包括第二隔离槽，所述第二隔离槽设置于所述第一阱区，且所述第二隔离槽的深度大于所述外延层的厚度。
  15. 如权利要求14所述的半导体器件，其特征在于，所述第二隔离槽为环形结构，所 述源极扩散区和所述漏极扩散区位于所述第二隔离槽界定的环形区域内。
  16. 如权利要求14或15所述的半导体器件，其特征在于，所述第二隔离槽与所述第一隔离槽背离所述半导体衬底的一端重合。
  17. 如权利要求14～16任一项所述的半导体器件，其特征在于，所述第一隔离槽的数量为多个时，在所述第二隔离槽的底部朝向所述半导体衬底的一侧，相邻的两个所述第一隔离槽之间的材料具有与所述半导体衬底相同的本征特性。
  18. 如权利要求14～17任一项所述的半导体器件，其特征在于，所述第一阱区的边缘设置有保护环，所述保护环内掺杂有所述第一类型杂质，且所述保护环接地或接电源设置；
    所述第一隔离槽与所述第二隔离槽位于所述保护环的内侧。
  19. 如权利要求14～18任一项所述的半导体器件，其特征在于，所述第一隔离槽内填充有二氧化硅与多晶硅，所述第二隔离槽内填充有二氧化硅。
  20. 如权利要求14～19任一项所述的半导体器件，其特征在于，所述第一隔离槽为深槽隔离(DTI)结构，所述第二隔离槽为浅槽隔离(STI)结构。
  21. 如权利要求13～20任一项所述的半导体器件，其特征在于，所述外延层的上方设置有硅锗合金异质结双极晶体管(SiGe HBT)的基区，所述外延层内设置有掺杂有所述第二类型杂质的集电极，所述集电极分别设置于所述基区的两侧；
    所述基区的上方设置有发射极以及基极，所述基极设置于所述发射极的两侧，且所述基极与所述发射极之间设置有第二绝缘层。
  22. 如权利要求21所述的半导体器件，其特征在于，所述集电极的***设置有环形的第三隔离槽，所述第三隔离槽内填充有二氧化硅与多晶硅。
  23. 如权利要求1～22任一项所述的半导体器件，其特征在于，所述第一类型杂质为P型杂质，所述第二类型杂质为N型杂质；
    或者，所述第一类型杂质为N型杂质，所述第二类型杂质为P型杂质。
  24. 一种封装结构，其特征在于，包括基板以及如权利要求1～23任一项所述的半导体器件，其中：
    所述半导体器件设置于所述基板上。
  25. 一种电子设备，其特征在于，包括电路板以及如权利要求24所述的封装结构，所述封装结构设置于所述电路板上。
PCT/CN2021/102300 2021-06-25 2021-06-25 一种半导体器件、封装结构及电子设备 WO2022266987A1 (zh)

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Citations (4)

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US20140061715A1 (en) * 2012-08-31 2014-03-06 Freescale Semiconductor, Inc. Zener diode device and fabrication
US9293527B1 (en) * 2014-12-03 2016-03-22 Force Mos Technology Co., Ltd. Super-junction trench MOSFET structure
US20180323187A1 (en) * 2017-05-05 2018-11-08 Newport Fab, LLC dba Jazz Semiconductor, Inc. Substrate Isolation For Low-Loss Radio Frequency (RF) Circuits
CN111933640A (zh) * 2020-07-28 2020-11-13 杭州士兰微电子股份有限公司 高压集成电路及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140061715A1 (en) * 2012-08-31 2014-03-06 Freescale Semiconductor, Inc. Zener diode device and fabrication
US9293527B1 (en) * 2014-12-03 2016-03-22 Force Mos Technology Co., Ltd. Super-junction trench MOSFET structure
US20180323187A1 (en) * 2017-05-05 2018-11-08 Newport Fab, LLC dba Jazz Semiconductor, Inc. Substrate Isolation For Low-Loss Radio Frequency (RF) Circuits
CN111933640A (zh) * 2020-07-28 2020-11-13 杭州士兰微电子股份有限公司 高压集成电路及其制造方法

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