WO2022257075A1 - 源漏接触金属的工艺方法、器件及其制备方法 - Google Patents

源漏接触金属的工艺方法、器件及其制备方法 Download PDF

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WO2022257075A1
WO2022257075A1 PCT/CN2021/099381 CN2021099381W WO2022257075A1 WO 2022257075 A1 WO2022257075 A1 WO 2022257075A1 CN 2021099381 W CN2021099381 W CN 2021099381W WO 2022257075 A1 WO2022257075 A1 WO 2022257075A1
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silicon germanium
target
layer
fin
epitaxial layer
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PCT/CN2021/099381
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English (en)
French (fr)
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陈鲲
徐敏
张卫
杨静雯
王晨
徐赛生
吴春蕾
尹睿
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上海集成电路制造创新中心有限公司
复旦大学
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Priority to PCT/CN2021/099381 priority Critical patent/WO2022257075A1/zh
Publication of WO2022257075A1 publication Critical patent/WO2022257075A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • the present invention relates to the field of semiconductors, and in particular to a process method of a source-drain contact metal, a device and a preparation method thereof.
  • a transistor device can be understood as a switch structure made of semiconductor materials, and one of the transistor devices is a gate-all-around device, which can also be understood as a GAA device or GAAFET. Among them, the full name of GAA is: Gate-All-Around, which means a wrap-around gate technology.
  • the height of the GAAFET device is relatively high.
  • the height of the fins formed during the preparation of the device is also relatively high.
  • the source-drain SiGe body layer i.e. SiGe source and drain
  • the source-drain SiGe body layer is formed based on the epitaxial silicon germanium material of the fin.
  • the thickness of the SiGe epitaxy also needs to increase synchronously. Due to its intrinsic characteristics of epitaxial growth, the germanium of the source and drain The lateral width of the bulk silicon layer also increases simultaneously. Furthermore, an excessively large lateral width will adversely affect the performance of the device.
  • the invention provides a process method of a source-drain contact metal, a device and a preparation method thereof, so as to solve the problem that excessive lateral width will adversely affect the performance of the device.
  • a process method for source-drain contact metal including:
  • the first silicon germanium part includes the first connection angle, the a second silicon germanium portion including the second junction angle;
  • a contact connection between the silicide layer and the metal is formed.
  • etching away the first silicon germanium part and the second silicon germanium part in the target silicon germanium epitaxial layer to form a silicon germanium bulk layer for source and drain including:
  • the target SiGe epitaxial layer is etched to form the SiGe bulk layer.
  • etching away the first silicon germanium part and the second silicon germanium part in the target silicon germanium epitaxial layer to form a silicon germanium bulk layer for source and drain including:
  • the dielectric material and the target SiGe epitaxial layer are etched to form the SiGe bulk layer.
  • the target fin includes stacked sacrificial layers and channel layers; wherein, the number of channel layers in the target fin is N layers.
  • the target SiGe epitaxial layer further includes a third connection angle located on the top side of the fin.
  • the first connection angle and the second connection angle are symmetrically distributed on both sides of the target fin along the channel direction.
  • the width of the SiGe bulk layer along the channel direction is less than or equal to a specified width
  • the specified width matches the width of a specific silicon germanium epitaxial layer epitaxially grown from a specific height fin, and the number of channel layers in the specific height fin is less than the number of channel layers in the target fin;
  • the thickness of the sacrificial layer in the specific height fin matches the thickness of the sacrificial layer in the target fin
  • the thickness of the channel layer in the specific height fin matches the thickness of the channel layer in the target fin
  • the width of the target fin along the corresponding channel direction matches the width of the specific height fin along the corresponding channel direction.
  • the number of channel layers in the fins with a specific height is one or two.
  • a device manufacturing method including the process method of the source-drain contact metal involved in the first aspect and its alternative solutions.
  • a device is provided, which is prepared by using the device preparation method involved in the second aspect and its alternatives.
  • the grown silicon-germanium epitaxial layer will form the first connection angle and the second connection angle, in the present invention, by etching away the first silicon germanium part containing the first connection angle and the second silicon germanium part containing the second connection angle in the target silicon germanium epitaxial layer, the formation of excessive Wide silicon germanium body layer, so as to avoid the influence caused by it, wherein, by etching the first connection angle and the second connection angle, the surface area of the body contact layer after etching can be smaller than the surface before unetching The area can reduce the contact resistance, thereby greatly reducing the parasitic resistance, and at the same time, the parasitic capacitance can be improved due to the reduction of the area.
  • Fig. 1a is a structural schematic diagram 1 of raised silicon germanium different from the technology of the present invention.
  • Fig. 1b is a structural schematic diagram 2 of raised silicon germanium in the technology different from the present invention.
  • Fig. 1c is a structural schematic diagram 3 of raised silicon germanium different from the technology of the present invention.
  • Fig. 2a is a structural schematic diagram of embedded silicon germanium different from the technology of the present invention.
  • Fig. 2b is a structural schematic diagram 2 of embedded silicon germanium in a technology different from that of the present invention
  • Fig. 2c is a structural schematic diagram three of embedded silicon germanium different from the technology of the present invention.
  • Fig. 3 is a schematic diagram of the curve of the current parameter Idsat of the device and the number of layers in the device in an example;
  • Fig. 4 is a schematic diagram of the curve of the capacitance parameter Cgg of the device and the number of layers in the device in an example
  • Fig. 5 is a schematic diagram of the curve of the conversion delay reduction rate (inverter delay reduction) of the device and the number of layers in the device in an example;
  • FIG. 6 is a schematic flow chart of a process method of a source-drain contact metal in an embodiment of the present invention.
  • FIG. 7 is a first schematic flow diagram of step S13 in an embodiment of the present invention.
  • FIG. 8 is a second schematic flow diagram of step S13 in an embodiment of the present invention.
  • Fig. 9 is a schematic structural diagram after step S11 in an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram after step S12 in an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram after step S131 in an embodiment of the present invention.
  • FIG. 12 is a schematic structural diagram after step S132 in an embodiment of the present invention.
  • Fig. 13 is a schematic structural diagram after step S133 in an embodiment of the present invention.
  • Fig. 14 is a schematic diagram of the structure after removing the mask in an embodiment of the present invention.
  • Fig. 15 is a schematic structural diagram after step S134 in an embodiment of the present invention.
  • FIG. 16 is a schematic structural diagram after step S135 in an embodiment of the present invention.
  • Fig. 17 is a schematic structural diagram after step S136 in an embodiment of the present invention.
  • Fig. 18 is a schematic structural diagram after step S137 in an embodiment of the present invention.
  • Fig. 19 is a schematic structural diagram after step S14 in an embodiment of the present invention.
  • first and second are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • a plurality means a plurality, such as two, three, four, etc., unless otherwise specifically defined.
  • connection and other terms should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection , can also be electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction relationship between two components.
  • connection and other terms should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection , can also be electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction relationship between two components.
  • the source-drain contact metal processing method provided by the embodiment of the present invention is mainly realized based on the scheme of SiGe source-drain epitaxy on the GAAFET device.
  • the structure of Figure 1a to Figure 1c can be regarded as a partial structure of raised silicon germanium (ie Raised SiGe), and the structure of Figure 2a to Figure 2c can be regarded as a partial structure of embedded silicon germanium (ie embedded SiGe), wherein, As the height of the device increases, the thickness of SiGe epitaxy also needs to increase synchronously. Due to the intrinsic characteristics of epitaxial crystal growth, the lateral width will also increase synchronously, forming a diamond-shaped structure (also can be understood as a diamond-shaped structure, corresponding to Refer to the following The structural form of the silicon germanium epitaxial layer 305 in FIG. 10 herein is understood).
  • the structure on the right side of the marking line L1 and marking line L2 shown in the figure is usually an invalid structure, and this part of the structure will increase the parasitic capacitance and resistance of the device.
  • the simulation results shown in Figures 3 to 5 show that the 8-layer height The GAA devices have been unable to provide any performance gains.
  • the embodiment of the present invention when the embodiment of the present invention performs etching on part or all of the structures on the right side of the marking line L1 and the marking line L2, the performance of the device will not be affected, and the corresponding parasitic capacitance and resistance can also be reduced. Improve contact performance.
  • SiGe bulk layer mentioned herein can be understood or characterized as SiGe source and drain.
  • the process method of source-drain contact metal includes:
  • S12 epitaxially epitaxial germanium silicon material on the target fin, forming a target germanium silicon epitaxial layer surrounding the target fin;
  • the process of forming fins on the substrate in step S11 may be any existing or improved scheme for forming fins.
  • a specific example is provided below, and it should be considered that the actual processing process is not limited to this example.
  • the sacrificial layer material and the channel layer material can be epitaxially stacked on the substrate in sequence to obtain the epitaxial layer, and then the epitaxial layer and the substrate are etched to form the stacked channel layer 302 and the sacrificial layer.
  • layer 301 , an oxide layer 304 can also be formed on the remaining silicon 311 , and then, the laminated channel layer 302 and sacrificial layer 301 , and the remaining silicon 311 after etching can form the target fin 303 .
  • the material of the sacrificial layer is SiGe
  • the material of the channel layer is Si.
  • the thicknesses of the epitaxial sacrificial layer materials may be the same or different, and the thicknesses of the epitaxial channel layer materials may be the same or different.
  • the material of the sacrificial layer and the channel layer can also be changed arbitrarily according to requirements, and at the same time, the thickness can also be changed arbitrarily according to requirements.
  • step S12 please refer to FIG. 10 , which shows the target fin 302 and the target silicon germanium epitaxial layer 305; wherein epitaxy can be understood as an EPI (ie Epitaxy) process, and the target silicon germanium epitaxial layer 305 in step S12 includes The first connection angle 3051 and the second connection angle 3052 are located on two sides (both sides along the channel direction) of the target fin.
  • EPI ie Epitaxy
  • the target silicon germanium epitaxial layer 305 also includes a third connection angle 3053 located on the top side of the fin, which can be regarded as a connection angle formed by a surface and a surface, or as a connection angle formed by a line and a line or a line and a line.
  • the first connection angle 3051 , the second connection angle 3052 and the third connection angle 3053 may be acute angles.
  • the first connection angle 3051, the second connection angle 3052, and the third connection angle 3053 can also be understood as: taking a plane parallel to the channel direction and perpendicular to the upper surface of the substrate as the cross-section, the target SiGe epitaxial layer 305
  • the first connection angle 3051 , the second connection angle 3052 , and the third connection angle 3053 can be formed in the outline of the section.
  • first connection angle 3051 , the second connection angle 3052 , and the third connection angle 3053 can be understood as sharp angles, or can be understood as structures that have been chamfered to a certain extent.
  • connection angle 3051 and the second connection angle 3052 are symmetrically distributed on both sides of the target fin 303 along the channel direction, ie, the left side and the right side shown in the figure.
  • SiGe epitaxial layer forming the three connection angles can be understood to be diamond-shaped or rhombus-shaped.
  • the first silicon germanium portion in step S13 includes the first connection angle
  • the second silicon germanium portion includes the second connection angle
  • the formation of an excessively wide silicon germanium bulk layer can be avoided.
  • the surface area of the body contact layer after etching can be smaller than the surface area before etching, thereby reducing the contact resistance , thereby greatly reducing the parasitic resistance, and at the same time improving the parasitic capacitance due to the reduction of the area.
  • a wrap-around source-drain contact (that is, wrap-around contact) can be formed relatively perfectly.
  • the width of the SiGe bulk layer 308 along the channel direction is less than or equal to the specified width.
  • the specified width may match the width of a specific silicon germanium epitaxial layer epitaxially grown in a fin of a specific height, and the number of channel layers in the fin of the specific height is less than the number of channel layers in the target fin;
  • the thickness of the sacrificial layer in the specific height fin matches the thickness of the sacrificial layer in the target fin
  • the thickness of the channel layer in the specific height fin matches the thickness of the channel layer in the target fin
  • the width of the target fin along the corresponding channel direction matches the width of the specific height fin along the corresponding channel direction.
  • the part on the right side of the marking line L1 and the marking line L2 can be understood as the part to be etched away.
  • the specified width can be characterized by referring to d1 and d2 shown in the figure (for example, the specified width can be equal to double d1 and double d2).
  • the specific height of the fin can be, for example, the width of the SiGe bulk layer 201 (ie, the specific SiGe epitaxial layer) formed outside the fin including only one channel layer 202 in FIG. 1a and FIG. 2a , which can be Characterized by the illustrated D1 and D2 (for example: the width of a specific germanium-silicon epitaxial layer can be equal to twice the D1 and twice the D2), and then, the number of channel layers in the fin with a specific height can be one layer, In other examples, it can also be two layers. On this basis, there are: D1 ⁇ d1, D2 ⁇ d2.
  • the epitaxy process of the target SiGe epitaxial layer on the target fin can be matched with the epitaxial process of a specific SiGe epitaxial layer on a specific fin.
  • the width of the silicon germanium body layer (i.e. SiGe source and drain) along the channel direction also needs to be greater than the specified minimum width, and the specified minimum width is greater than the width of the channel layer along the channel direction. Further, it can also make: the silicon germanium body
  • the layer can surround the fin, which can also be understood as: the diamond shape (or rhombus) needs to surround the fin (or all the channel layers 202).
  • step S13 An implementation manner of step S13 will be described below with reference to FIG. 7 , FIG. 11 , FIG. 12 , FIG. 13 , and FIG. 14 .
  • step S13 may include:
  • S132 Fabricate a mask on the anti-reflective coating, and pattern the mask, so that the mask facing the first silicon germanium part and the second silicon germanium part is removed;
  • the anti-reflection coating 306 can also be characterized as a BARC coating, wherein the BARC is specifically: Bottom Anti-Reflection Coating, that is, the bottom anti-reflection coating, which can be realized by using organic or inorganic anti-reflection materials (such as TiN materials).
  • BARC is specifically: Bottom Anti-Reflection Coating, that is, the bottom anti-reflection coating, which can be realized by using organic or inorganic anti-reflection materials (such as TiN materials).
  • a mask 307 can be fabricated, and based on the patterned mask 307, the anti-reflection coating 306 and the target silicon-germanium epitaxial layer 305 can be etched, thereby obtaining the structure in FIG. 13 to form silicon-germanium body layer 308 .
  • the remaining part of the anti-reflection coating 306 and the mask 307 may be removed, thereby forming the structure shown in FIG. 14 .
  • step S13 An implementation manner of step S13 will be described below with reference to FIG. 8 , FIG. 15 , FIG. 16 , FIG. 17 and FIG. 18 .
  • S135 Remove part of the dielectric material, so as to expose the SiGe material in a designated area, where the designated area is an area for forming the SiGe bulk layer;
  • the dielectric material 310 can also be characterized as Dielectric. Through the formation and partial removal of the dielectric material 310, a protective cover 311 can be formed for the SiGe bulk layer in a targeted manner. The protective cover 311 can avoid Arbitrary material whose structure is etched.
  • the processing process of the above scheme can be regarded as a specific example of the self-alignment etching (i.e. Self-Align Etch) route process, in which, the self-alignment protection cap structure is obtained through the selective growth technology, and then the cap-like structure is used Trim the silicon germanium bulk layer (ie SiGe source and drain).
  • Self-Align Etch the self-alignment etching route process, in which, the self-alignment protection cap structure is obtained through the selective growth technology, and then the cap-like structure is used Trim the silicon germanium bulk layer (ie SiGe source and drain).
  • the silicide layer formed in step S14 can be the silicide layer 309 shown in FIG. 19 , and specifically, the silicide layer 309 can be deposited by selective deposition.
  • the metal may be partially or completely surrounded by the silicide layer.
  • steps S11 to S15 in addition to steps S11 to S15, other structures such as dummy gates can also be formed outside the fins, and other steps other than steps S11 to S15 can be added arbitrarily according to the requirements of the process.
  • An embodiment of the present invention also provides a device manufacturing method, including the source-drain contact metal process method involved in the above optional solution.
  • the embodiment of the present invention also provides a device, which is prepared by using the device preparation method involved in the above optional solutions.

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Abstract

本发明提供了一种源漏接触金属的工艺方法、器件及其制备方法，源漏接触金属的工艺方法，包括：在基底上制作目标鳍片；在所述目标鳍片外外延锗硅材料，形成包围所述目标鳍片的目标锗硅外延层；所述目标锗硅外延层包括位于所述目标鳍片两侧的第一连接角与第二连接角；刻蚀掉所述目标锗硅外延层中的第一锗硅部分与第二锗硅部分，形成源漏的锗硅体层；所述第一锗硅部分包括所述第一连接角，所述第二锗硅部分包括所述第二连接角；在所述锗硅体层外沉积一层硅化物层；形成所述硅化物层与金属的接触连接。

Description

源漏接触金属的工艺方法、器件及其制备方法 技术领域
本发明涉及领域半导体领域，尤其涉及一种源漏接触金属的工艺方法、器件及其制备方法。
背景技术
晶体管器件，可理解为用半导体材料制作的开关结构，其中一种晶体管器件为环栅器件，也可理解为GAA器件、GAAFET。其中，GAA的全称为：Gate-All-Around，表示一种环绕式栅极技术。
现有相关技术中，GAAFET器件的高度比较高，对应的，在制备器件过程中，所形成的鳍片的高度也较高，GAAFET器件上SiGe源漏外延的方案中，源漏的锗硅体层(即SiGe源漏)是基于鳍片外延锗硅材料从而形成的，随着鳍片高度的增加，SiGe外延的厚度也需要同步增加，由于其外延晶向生长本征特性，源漏的锗硅体层的横向宽度也会同步增加。进而，过大的横向宽度将会对器件的性能带来不利影响。
发明内容
本发明提供一种源漏接触金属的工艺方法、器件及其制备方法，以解决过大的横向宽度将会对器件的性能带来不利影响的问题。
根据本发明的第一方面，提供了一种源漏接触金属的工艺方法，包括：
在基底上制作目标鳍片；
在所述目标鳍片外外延锗硅材料，形成包围所述目标鳍片的目标锗硅外延层；所述目标锗硅外延层包括位于所述目标鳍片两侧的第一连接角与第二连接角；
刻蚀掉所述目标锗硅外延层中的第一锗硅部分与第二锗硅部分，形成源漏的锗硅体层；所述第一锗硅部分包括所述第一连接角，所述第二锗硅部分包括所述第二连接角；
在所述锗硅体层外沉积一层硅化物层；
形成所述硅化物层与金属的接触连接。
可选的，刻蚀掉所述目标锗硅外延层中的第一锗硅部分与第二锗硅部分，形成源漏的锗硅体层，包括：
在所述目标锗硅外延层外制作抗反射涂层；
在所述抗反射涂层上制作掩膜，并图案化所述掩膜，以使得正对所述第一锗硅部分与所述第二锗硅部分的掩膜被去除；
基于所述掩膜，刻蚀所述目标锗硅外延层，形成所述锗硅体层。
可选的，刻蚀掉所述目标锗硅外延层中的第一锗硅部分与第二锗硅部分，形成源漏的锗硅体层，包括：
在所述目标锗硅外延层外形成介电材料；
去除部分所述介电材料，以对外露出指定区域的锗硅材料，所述指定区域为用于形成所述锗硅体层的区域；
在所述指定区域上制作保护盖；
基于所述保护盖，对所述介电材料与所述目标锗硅外延层进行刻蚀，形成所述锗硅体层。
可选的，所述目标鳍片包括层叠的牺牲层与沟道层；其中，所述目标鳍片中沟道层的数量为N层。
可选的，所述目标锗硅外延层还包括位于所述鳍片顶侧的第三连接角。
可选的，所述第一连接角与所述第二连接角对称分布于所述目标鳍片的沿沟道方向的两侧。
可选的，所述锗硅体层沿沟道方向的宽度小于或等于指定宽度；
所述指定宽度匹配于特定高度鳍片外外延出的特定锗硅外延层的宽度，所述特定高度鳍片中沟道层的数量少于所述目标鳍片中沟道层的数量；
所述特定高度鳍片中牺牲层的厚度匹配于所述目标鳍片中牺牲层的厚度，所述特定高度鳍片中沟道层的厚度匹配于所述目标鳍片中沟道层的厚度，所述目标鳍片沿对应沟道方向的宽度匹配于所述特定高度鳍片沿对应沟道方向的宽度。
可选的，所述特定高度鳍片中沟道层的数量为一层或两层。
根据本发明的第二方面，提供了一种器件制备方法，包括第一方面及其可选方案涉及的源漏接触金属的工艺方法。
根据本发明的第三方面，提供了一种器件，利用第二方面及其可选方案涉及的器件制备方法制备而成。
本发明提供的源漏接触金属的工艺方法、器件及其制备方法中，基于对锗硅外延的工艺研究，由于其外延晶向生长本征特性，生长的锗硅外延层将形成第一连接角与第二连接角，本发明中通过刻蚀掉所述目标锗硅外延层中包含第一连接角的第一锗硅部分，以及包含第二连接角的第二锗硅部分，可避免形成过宽的锗硅体层，从而避免因此而带来的影响，其中，通过对第一连接角、第二连接角的刻蚀，刻蚀后体接触层的表面面积可小于未刻蚀前的表面面积，进而可降低接触电阻，从而大大减小寄生电阻，同时因为面积的减小从而改善寄生电容。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1a是区别于本发明的技术中抬升式锗硅的结构示意图一；
图1b是区别于本发明的技术中抬升式锗硅的结构示意图二；
图1c是区别于本发明的技术中抬升式锗硅的结构示意图三；
图2a是区别于本发明的技术中嵌入式锗硅的结构示意图一；
图2b是区别于本发明的技术中嵌入式锗硅的结构示意图二；
图2c是区别于本发明的技术中嵌入式锗硅的结构示意图三；
图3是一种举例中器件的电流参数Idsat与器件中层数的曲线示意图；
图4是一种举例中器件的电容参数Cgg与器件中层数的曲线示意图；
图5是一种举例中器件的转换延时降低率(inverter delay reduction)与器件中层数的曲线示意图；
图6是本发明一实施例中源漏接触金属的工艺方法的流程示意图；
图7是本发明一实施例中步骤S13的流程示意图一；
图8是本发明一实施例中步骤S13的流程示意图二；
图9是本发明一实施例中步骤S11之后的结构示意图；
图10是本发明一实施例中步骤S12之后的结构示意图；
图11是本发明一实施例中步骤S131之后的结构示意图；
图12是本发明一实施例中步骤S132之后的结构示意图；
图13是本发明一实施例中步骤S133之后的结构示意图；
图14是本发明一实施例中去除掩膜后的结构示意图；
图15是本发明一实施例中步骤S134之后的结构示意图；
图16是本发明一实施例中步骤S135之后的结构示意图；
图17是本发明一实施例中步骤S136之后的结构示意图；
图18是本发明一实施例中步骤S137之后的结构示意图；
图19是本发明一实施例中步骤S14之后的结构示意图。
附图标记说明：
201-锗硅体层；
202-沟道层；
301-牺牲层；
302-沟道层；
303-目标鳍片；
304-氧化层；
305-目标锗硅外延层；
306-抗反射涂层；
307-掩膜；
308-锗硅体层；
309-硅化物层；
310-介电材料；
311-硅。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明说明书的描述中，需要理解的是，术语“上部”、“下部”、“上端”、“下端”、“下表面”、“上表面”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明说明书的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。
在本发明的描述中，“多个”的含义是多个，例如两个，三个，四个等，除非另有明确具体的限定。
在本发明说明书的描述中，除非另有明确的规定和限定，术语“连接”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接或可以互相通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
下面以具体地实施例对本发明的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
本发明实施例提供的源漏接触金属的工艺方法，主要基于GAAFET器件上SiGe源漏外延的方案实现。
为了能够说明本发明实施例的方案的改进，以下将结合图1a至图c、图2a至图2c、图3至图5对区别于本发明实施例的技术进行阐述。
其中，图1a至图1c的结构可视作抬升式锗硅(即Raised SiGe)的部分结构，图2a至图2c的结构可视作嵌入式锗硅(即embedded SiGe)的部分结构，其中，随着器件高度的增加，SiGe外延的厚度也需要同步增加，由于其外延晶向生长本征特性，横向宽度也会同步增加，形成为钻石型结构(也可理解为菱形结构，对应可参照后文中的图10中锗硅外延层305的结构形式理解)。
图中所示标线L1、标线L2右侧的结构通常会属于无效结构，该部分结构会增加器件的寄生电容和电阻，与此同时，通过图3至图5仿真结果显示，8层高度的GAA器件已经无法提供任何性能提升。
基于此，本发明实施例对标线L1、标线L2右侧的部分或全部结构进行刻蚀等处理时，并不会影响器件的性能，还可有助于降低对应的寄生电容和电阻，提高接触性能。
本文所提及的锗硅体层，均可理解或表征为SiGe源漏。
本发明实施例中，请参考图6，源漏接触金属的工艺方法，包括：
S11：在基底上制作目标鳍片；
S12：在所述目标鳍片外外延锗硅材料，形成包围所述目标鳍片的目标锗硅外延层；
S13：刻蚀掉所述目标锗硅外延层中的第一锗硅部分与第二锗硅部分，形成源漏的锗硅体层；
S14：在所述锗硅体层外沉积一层硅化物层；
S15：形成所述硅化物层与金属的接触连接。
步骤S11中在基底上制作鳍片的过程可以是任意已有或改进的形成鳍片的方案。以下提供一种具体的举例，应认为，实际的处理过程并不限于该举例。
该具体举例中，请参考图9，可在基底上依次外延层叠的牺牲层材料与沟道层材料，得到外延层，然后对外延层与基底进行刻蚀，形成层叠的沟道层302与牺牲层301，还可可在剩余的硅311上制作氧化层304，进而，层叠的沟道层302与牺牲层301，以及刻蚀后的剩余的硅311可形成目标鳍片303。
一种举例中，所述牺牲层材料为SiGe，所述沟道层材料为Si。外延的各层牺牲层材料的厚度可以是相同的，也可以是不同的，外延的各层沟道层材料的厚度可以是相同的，也可以是不同的。其他举例中，牺牲层、沟道层的材料也可根据需求任意变化，同时，厚度也可根据需求任意变化。
步骤S12中，请参考图10，其中示意了目标鳍片302与目标锗硅外延层305；其中外延可理解为EPI(即Epitaxy)工艺，步骤S12中的所述目标锗硅外延层305，包括位于所述目标鳍片两侧(沿沟道方向的两侧)的第一 连接角3051与第二连接角3052。
进一步的，所述目标锗硅外延层305还包括位于所述鳍片顶侧的第三连接角3053，其可以视作面与面形成的连接角，也可以视作线与线或或线与面的形成的连接角。其中的第一连接角3051、第二连接角3052、第三连接角3053可以为锐角。
其中的第一连接角3051、第二连接角3052、第三连接角3053，也可理解为：以平行于沟道方向，且垂直于基底上表面的平面为剖面，目标锗硅外延层305的剖面的轮廓线条中，可形成该第一连接角3051、第二连接角3052、第三连接角3053。
此外，其中的第一连接角3051、第二连接角3052、第三连接角3053可理解为尖角，也可理解为已形成一定倒角的结构。
其中，所述第一连接角3051与所述第二连接角3052对称分布于所述目标鳍片303的沿沟道方向的两侧，即图中所示的左侧与右侧。进而，形成该三个连接角的锗硅外延层可理解为呈钻石形或菱形。
对应的，步骤S13中的第一锗硅部分包括所述第一连接角，所述第二锗硅部分包括所述第二连接角。
其中，通过刻蚀掉所述目标锗硅外延层中包含第一连接角的第一锗硅部分，以及包含第二连接角的第二锗硅部分，可避免形成过宽的锗硅体层，从而避免因此而带来的影响，其中，通过对第一连接角、第二连接角的刻蚀，刻蚀后体接触层的表面面积可小于未刻蚀前的表面面积，进而可降低接触电阻，从而大大减小寄生电阻，同时因为面积的减小从而改善寄生电容。进而，可比较完美地形成完美形成包裹式源漏接触(即wrap-around contact)。
其中一种实施方式中，请参考图19并结合其他结构的附图，所述锗硅体层308沿沟道方向(即图中所示的左右方向)的宽度小于或等于指定宽度。
所述指定宽度可以匹配于特定高度鳍片外外延出的特定锗硅外延层的宽度，所述特定高度鳍片中沟道层的数量少于所述目标鳍片中沟道层的数量；
所述特定高度鳍片中牺牲层的厚度匹配于所述目标鳍片中牺牲层的厚度，所述特定高度鳍片中沟道层的厚度匹配于所述目标鳍片中沟道层的厚度，所述目标鳍片沿对应沟道方向的宽度匹配于所述特定高度鳍片沿对应沟 道方向的宽度。
以图1a、图1b、图1c、图2a、图2b、图2c为例，标线L1与标线L2右侧的部分可理解为将要刻蚀掉的部分，进而，一种举例中，其中指定宽度可参照于图示的d1与d2表征(例如：指定宽度可等于两倍的d1、两倍的d2)。
与之相对应的，特定高度鳍片可例如图1a与图2a中仅包含一个沟道层202的鳍片外所形成的锗硅体层201(即特定锗硅外延层)的宽度，其可通过图示的D1、D2表征(例如：特定锗硅外延层的宽度可等于两倍的D1、两倍的D2)，进而，所述特定高度鳍片中沟道层的数量可以为一层，其他举例中，也可以为两层，在此基础上，则有：D1≥d1，D2≥d2。
此外，目标鳍片外外延出目标锗硅外延层的工艺可与特定鳍片外外延出特定锗硅外延层的工艺相匹配。
所述锗硅体层(即SiGe源漏)沿沟道方向的宽度还需大于指定最小宽度，该指定最小宽度大于沟道层沿沟道方向的宽度，进一步的，还可使得：锗硅体层能包围鳍片，也可理解为：钻石形(或菱形)需包围住鳍片(或者所有沟道层202)。
以下将结合图7、图11、图12、图13、图14对步骤S13的一种实施方式进行说明。
其中一种实施方式中，步骤S13可以包括：
S131：在所述目标锗硅外延层外制作抗反射涂层；
S132：在所述抗反射涂层上制作掩膜，并图案化所述掩膜，以使得正对所述第一锗硅部分与所述第二锗硅部分的掩膜被去除；
S133：基于所述掩膜，刻蚀所述目标锗硅外延层，形成所述锗硅体层。
其中的抗反射涂层306也可表征为BARC涂层，其中的BARC具体为：Bottom Anti-Reflection Coating，即底部抗反射涂层，具体可以采用有机或无机抗反射物质实现(例如TiN材料)。
基于抗反射涂层306，可制作掩膜307，基于图案化之后的掩膜307，可对抗反射涂层306与目标锗硅外延层305进行刻蚀，从而得到图13中的结构，形成锗硅体层308。形成之后(即步骤S133之后)，可去除抗反射涂层306的剩余部分，以及掩膜307，从而形成图14所示的结构。
以下将结合图8、图15、图16、图17与图18对步骤S13的一种实施方式进行说明。
S134：在所述目标锗硅外延层外形成介电材料；
S135：去除部分所述介电材料，以对外露出指定区域的锗硅材料，所述指定区域为用于形成所述锗硅体层的区域；
S136：在所述指定区域上制作保护盖；
S137：基于所述保护盖，对所述介电材料与所述目标锗硅外延层进行刻蚀，形成所述锗硅体层。
其中的介电材料310也可表征为Dielectric，通过对介电材料310的形成与部分去除，可有针对性地为锗硅体层部分形成保护盖311，该保护盖311可以为能够避免其下结构被刻蚀的任意材质。
以上方案的处理过程可视作自对准刻蚀(即Self-Align Etch)路线工艺的一种具体举例，其中，通过选择性生长技术生存自对准保护得帽装结构,然后利用帽子状结构修剪锗硅体层(即SiGe源漏)。
不论采用何种工艺实现刻蚀，均可作为本发明实施例的一种可选方案。
步骤S14中所形成的硅化物层即可如图19所示的硅化物层309，具体可通过选择性沉积的方式沉积该硅化物层309。
步骤S15的具体举例中，金属可部分或全部包围在硅化物层外。
此外，除了步骤S11至步骤S15，还可在鳍片之外形成伪栅极等其他结构，根据工艺的需求，可任意添加步骤S11至步骤S15之外的其他步骤。
本发明实施例还提供了一种器件制备方法，包括以上可选方案涉及的源漏接触金属的工艺方法。
本发明实施例还提供了一种器件，利用以上可选方案涉及的器件制备方法制备而成。
在本说明书的描述中，参考术语“一种实施方式”、“一种实施例”、“具体实施过程”、“一种举例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

  1. 一种源漏接触金属的工艺方法，其特征在于，包括：
    在基底上制作目标鳍片；
    在所述目标鳍片外外延锗硅材料，形成包围所述目标鳍片的目标锗硅外延层；所述目标锗硅外延层包括位于所述目标鳍片两侧的第一连接角与第二连接角；
    刻蚀掉所述目标锗硅外延层中的第一锗硅部分与第二锗硅部分，形成源漏的锗硅体层；所述第一锗硅部分包括所述第一连接角，所述第二锗硅部分包括所述第二连接角；
    在所述锗硅体层外沉积一层硅化物层；
    形成所述硅化物层与金属的接触连接。
  2. 根据权利要求1所述的工艺方法，其特征在于，刻蚀掉所述目标锗硅外延层中的第一锗硅部分与第二锗硅部分，形成源漏的锗硅体层，包括：
    在所述目标锗硅外延层外制作抗反射涂层；
    在所述抗反射涂层上制作掩膜，并图案化所述掩膜，以使得正对所述第一锗硅部分与所述第二锗硅部分的掩膜被去除；
    基于所述掩膜，刻蚀所述目标锗硅外延层，形成所述锗硅体层。
  3. 根据权利要求1所述的工艺方法，其特征在于，刻蚀掉所述目标锗硅外延层中的第一锗硅部分与第二锗硅部分，形成源漏的锗硅体层，包括：
    在所述目标锗硅外延层外形成介电材料；
    去除部分所述介电材料，以对外露出指定区域的锗硅材料，所述指定区域为用于形成所述锗硅体层的区域；
    在所述指定区域上制作保护盖；
    基于所述保护盖，对所述介电材料与所述目标锗硅外延层进行刻蚀，形成所述锗硅体层。
  4. 根据权利要求1至3任一项所述的工艺方法，其特征在于，所述目标鳍片包括层叠的牺牲层与沟道层；其中，所述目标鳍片中沟道层的数量为N层。
  5. 根据权利要求4所述的工艺方法，其特征在于，所述目标锗硅外延层还包括位于所述鳍片顶侧的第三连接角。
  6. 根据权利要求1至3任一项所述的工艺方法，其特征在于，所述第一连接角与所述第二连接角对称分布于所述目标鳍片的沿沟道方向的两侧。
  7. 根据权利要求4所述的工艺方法，其特征在于，所述锗硅体层沿沟道方向的宽度小于或等于指定宽度；
    所述指定宽度匹配于特定高度鳍片外外延出的特定锗硅外延层的宽度，所述特定高度鳍片中沟道层的数量少于所述目标鳍片中沟道层的数量；
    所述特定高度鳍片中牺牲层的厚度匹配于所述目标鳍片中牺牲层的厚度，所述特定高度鳍片中沟道层的厚度匹配于所述目标鳍片中沟道层的厚度，所述目标鳍片沿对应沟道方向的宽度匹配于所述特定高度鳍片沿对应沟道方向的宽度。
  8. 根据权利要求7所述的工艺方法，其特征在于，所述特定高度鳍片中沟道层的数量为一层或两层。
  9. 一种器件制备方法，其特征在于，包括权利要求1至8任一项所述的源漏接触金属的工艺方法。
  10. 一种器件，其特征在于，利用权利要求9所述的器件制备方法制备而成。
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