WO2022252654A1 - 逆导型横向绝缘栅双极型晶体管 - Google Patents
逆导型横向绝缘栅双极型晶体管 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
Definitions
- the present application relates to the technical field of semiconductor devices, in particular to a reverse conduction lateral insulated gate bipolar transistor.
- Lateral Insulated-Gate Bipolar Transistor is a transistor that combines the advantages of MOS transistors and bipolar transistors.
- Silicon on Insulator (SOI) technology is widely used in the manufacture of power integrated circuits due to its ideal dielectric isolation performance.
- SOI-LIGBT device is a LIGBT device manufactured based on SOI technology.
- Intelligent power modules are widely used in motor drives and motor drives. Under medium power conditions, fully integrated SOI-LIGBTs are often used as their power switching devices, and LIGBT parallel high-voltage freewheeling diodes (FWD) are the most Classic switching device structure.
- FWD parallel high-voltage freewheeling diodes
- the patent document CN111816699A proposes an adaptive SOI LIGBT device, which mainly integrates a Zener diode, because the Zener diode will adaptively reverse breakdown and conduction with the increase of the collector voltage.
- the collector structure is a collector NMOS structure
- the N-type buffer layer also has The second P-type well region, P+ well potential region, N+ collector region and collector groove gate; the P+ potential region and the P+ well potential region are short-circuited, so that the potential difference between the collector electrode and the P+ well potential region is also small, which cannot be achieved in the second P-type well region.
- the inversion layer is formed in the P well region, which leads to the blocking of the conductive path between the N+ collector region and the N-type buffer layer, and the device cannot enter the unipolar conduction mode, thereby eliminating the snap-back effect when the device is conducting forward.
- the structure of this patent document introduces a Zener diode.
- the Zener diode generally has a Zener-type tunnel breakdown, when it is used as a freewheeling diode in a reverse-conducting LIGBT, it is used in the reverse breakdown It will be relatively limited under high voltage or ultra-high voltage conditions; and, although the Zener diode in this patent document has a certain effect in suppressing the snap-back effect of forward conduction, it cannot achieve faster recovery characteristics, due to its The setting of the collector structure, the turn-off rate of the switch in the reverse recovery stage of LIGBT still needs to be improved.
- a reverse conduction lateral IGBT is provided.
- a reverse conduction lateral insulated gate bipolar transistor comprising: a drift region formed on a substrate, a gate located on the drift region, an emitter located on the drift region and close to the gate side a pole region, and a collector region located on the drift region and away from the gate side;
- Two or more N well regions arranged at intervals are provided on the side where the collector region of the drift region is located;
- a P well region is provided between two or more N well regions arranged at intervals;
- a P+ contact region is arranged on the N well region
- An N+ contact region is arranged on the P well region
- Both the P+ contact area and the N+ contact area are conductively connected to the collector terminal.
- the two or more N well regions arranged at intervals at least include a first N well region and a second N well region; the P well region at least includes The first P well region between the second N well regions; the areas of the first N well region and the second N well region are equal, and the first N well region and the second N well region regions are distributed symmetrically with respect to the first P-well region.
- the periphery of the N+ contact region is covered by the P well region.
- the N+ contact region includes a first portion and a second portion; the first portion includes a sidewall portion and a bottom portion, and the sidewall portion extends in a direction perpendicular to the plane where the substrate is located , the bottom part is connected to the side wall part on a side close to the substrate; the second part is connected to the side wall part on a side away from the substrate; the depth of the side wall part is greater than that of the first part The depth of the second part.
- the depth of the sidewall portion is greater than the depth of the P+ contact region.
- a trench is formed in the P-well region; the sidewall portion and the bottom of the first portion are respectively doped by doping the side surface and the bottom surface of the trench And formed.
- a filling structure is formed in the trench; the second portion is located on the filling structure.
- the material of the filling structure includes insulating material and/or polysilicon.
- the number of the P well regions is multiple, and the multiple N+ contact regions are located in the multiple P well regions respectively; the multiple N+ contact regions are parallel to the P+ contact regions. staggered distribution on the plane where the substrate is located.
- more than two N well regions arranged at intervals and a plurality of P well regions are alternately distributed on a plane parallel to the substrate.
- FIG. 1 is a schematic cross-sectional view of a common lateral insulated gate bipolar transistor
- FIG. 2 is a schematic cross-sectional view of a reverse conduction lateral IGBT transistor provided in a related embodiment
- FIG. 3 is a schematic cross-sectional view of a reverse conduction lateral IGBT transistor provided in the first embodiment
- FIG. 4 is a schematic cross-sectional view of a reverse conduction lateral IGBT transistor provided in the second embodiment
- 5a-5c are schematic top views of the collector region of the reverse conduction lateral IGBT in an alternative embodiment.
- FIG. 1 is a schematic cross-sectional view of a common lateral insulated gate bipolar transistor.
- the lateral insulated gate bipolar transistor includes: an SOI substrate (including a bottom silicon layer 100, a buried oxide layer 110 and a top silicon layer 120), located in the drift region 121 of the top silicon layer 120, the field oxide layer 130, the gate 140, the polysilicon field plate 150 at the collector, the emitter region on the drift region 121 and close to the gate side, and the drift region 121 and away from the collector region on the side of the gate.
- the emitter region is provided with a channel region 161, and the channel region 161 is specifically a P well region, which is used as a conduction channel of a lateral MOS in LIGBT; a substrate ohmic contact region 171 and a source
- the pole ohmic contact region 172, and the substrate ohmic contact region 171 and the source ohmic contact region 172 are all conductively connected to the emitter terminal.
- the collector region is provided with an N-type buffer zone (hereinafter referred to as the N-well region 162), and the P+ contact region 173 is arranged on the N-well region 162; both the P+ contact region 173 and the polysilicon field plate 150 are conductively connected to the collector terminal.
- the LIGBT needs to be connected in parallel with the FWD; when the LIGBT is forward-conducting, hole injection forms a large current conduction, driving the inductive load to work normally; when the LIGBT is turned off, the inductive load needs a loop because the current cannot change suddenly. At this time, the FWD connected in parallel will play the role of continuous flow. When the gate of LIGBT is turned on in the next stage, the FWD will return to the cut-off state after reverse recovery, and a working cycle ends.
- LIGBT and FWD are two different types of devices, a high degree of matching is required to ensure normal switching characteristics during operation. Therefore, how to integrate independent FWD and LIGBT has become an important research direction in this field.
- the present application firstly proposes a A related embodiment, the related embodiment provides a reverse conduction lateral insulated gate bipolar transistor, by improving the structure of the collector of the LIGBT, the switching characteristics of the LIGBT are improved. Please refer to FIG. 2 for details.
- an N+ contact region 174 is also provided in the N well region 162, that is, an N+ contact region is added in the collector region.
- the lower end of the N+ contact region 174 is surrounded by the P well region 163 . Therefore, when the LIGBT is normally turned on, the holes in the P+ contact region 173 are injected into the N well region 162 and the drift region 121 to generate a conductance modulation effect, and the current rises sharply after triggering the PNP transistor, and the LIGBT enters forward conduction work. At this time The N+ contact region 174 and the P well region 163 are in a reverse bias state, and electrons cannot pass through the depletion layer to form an LDMOS, so the normal turn-on operation is not affected when the forward LIGBT is turned on. When the LIGBT is reversely turned off, the collector of the LIGBT loses the voltage and becomes zero potential.
- the inductive load current driven cannot change suddenly and flows in through the P+ of the emitter (please refer to the substrate ohmic contact area 171 in FIG. 2 ),
- the N+ contact region 174 in the structure provided by this related embodiment there is a current path that can pass back to the coil during freewheeling, so there is no need to additionally connect FWD in parallel for freewheeling , the layout area can be greatly saved when the module is working, and the reliability of LIGBT is also improved.
- the P+ contact region 173, the N+ contact region 174 and the P well region 163 are all arranged on the same N well region 162, and the minority carrier holes need to be transported during the LIGBT reverse recovery.
- the reverse conduction lateral insulated gate bipolar transistor includes: a drift region formed on the substrate, a gate located on the drift region, and a gate located on the drift region and close to the gate. an emitter region, and a collector region on the side of the drift region away from the gate; where,
- Two or more N well regions arranged at intervals are arranged on the side where the collector region of the drift region is located;
- a P well region is provided between two or more N well regions arranged at intervals;
- a P+ contact region is provided on the N well region
- An N+ contact region is provided on the P well region
- Both the P+ contact area and the N+ contact area are conductively connected to the collector terminal.
- the embodiments of the present application improve the structure of the LIGBT collector region, which not only makes the improved device structure unnecessary to additionally connect FWD in parallel for freewheeling, but also greatly saves the layout area when the module is working. Improve the reliability of LIGBT, and because of the spaced arrangement of N well regions, the P well region is set between the spaced N well regions, thereby further improving the switch turn-off rate of LIGBT in the reverse recovery stage, and improving the overall device switching characteristics.
- FIG. 3 is a schematic cross-sectional view of a reverse conduction lateral insulated gate bipolar transistor provided in the first embodiment of the present application; as shown in the figure, the reverse conduction lateral insulated gate bipolar transistor includes: Silicon layer 100 , buried oxide layer 110 and top silicon layer 120 .
- the bottom silicon layer 100 has a first conductivity type, specifically, for example, the P type, that is, the bottom silicon layer 100 is a P-type substrate (Psub).
- Psub P-type substrate
- Its material is silicon; of course, the embodiment of the present application is not limited thereto, materials commonly used in this field, such as silicon carbide, gallium arsenide, indium phosphide or silicon germanium, etc., can also be used as the SOI substrate in the embodiment of the present application material of the underlying substrate.
- the buried oxide layer 110 is located on the bottom silicon layer 100 and its material is usually silicon oxide, such as silicon dioxide.
- the buried oxide layer 110 is generally named (BOX) in terms of function, and is specifically an insulating layer, and its material may also be other insulating materials not limited to silicon dioxide.
- the top silicon layer 120 is located on the buried oxide layer 110, specifically, it may be an epitaxial layer with the second conductivity type, which is used as a layer for fabricating devices.
- the top silicon layer 120 acts as a drift region (indicated by drift region 121 in the figure) in the LIGBT device.
- the second conductivity type may be N-type, as a drift region, having a conductivity type opposite to that of the bottom silicon layer 100 .
- the drift region 121 is specifically an N-region.
- the material of the top silicon layer 120 is silicon; of course, the embodiment of the present application is not limited thereto, materials commonly used in this field, such as silicon carbide, gallium arsenide, indium phosphide or silicon germanium, etc., can also be used as the embodiment of the present application
- the top substrate material of the SOI substrate can also be used as the embodiment of the present application.
- the field oxide layer 130 is formed on the drift region 121, and the material of the field oxide layer 130 may be silicon oxide, such as silicon dioxide.
- the field oxide layer 130 is the field region of the LIGBT, serving as the lateral isolation of the device.
- a gate 140 is formed on the field oxide layer 130, and the material of the gate 140 is, for example, polysilicon, and serves as a gate of the LIGBT.
- a polysilicon field plate 150 at the collector which acts as a polysilicon field plate at the collector of the LIGBT.
- Both the channel region 161 and the N well region 162 are located on the drift region 121 , and they are arranged at intervals along the first direction in the figure.
- the channel region 161 is located on a side close to the gate 140 ; the channel region 161 has a first conductivity type, specifically, for example, a P-well.
- the channel region 161 forms a conduction channel of the lateral MOS.
- the N well region 162 is located on a side away from the gate 140 .
- the N well region 162 is in the collector region of the LIGBT and serves as an N-type buffer layer of the LIGBT to prevent punch through.
- a substrate ohmic contact region 171 having a first conductivity type and a source ohmic contact region 172 having a second conductivity type are disposed in the channel region 161 .
- the substrate ohmic contact region 171 is specifically a P+ type region, which is drawn out as the substrate.
- the source ohmic contact region 172 is specifically an N+ type region, serving as a source ohmic contact of the MOS.
- the source ohmic contact region 172 is in contact with the channel region 161 on a side facing the gate 140 to induce a channel in the channel region 161 .
- the N-well region acts as a buffer for the LIGBT.
- the buffer area is divided into two or more N-well regions arranged at intervals, so as to independently become a LIGBT unit.
- a P+ contact region 173 is provided on the N well region, and the P+ contact region 173 can also be called a collector ohmic contact region, which serves as a collector ohmic contact of LIGBT and provides electrode extraction.
- each N well region can be provided with an independent P+ contact region; each P+ contact region can be located in each corresponding N well region as shown in Figure 3, and the sides and bottom of the P+ contact region are covered by the N well region. Covering; each P+ contact region can also be located on each corresponding N well region, and only the bottom is covered by the N well region.
- a P well region 163 is provided between two or more N well regions arranged at intervals (for example, between the first N well region 1621 and the second N well region 1622 );
- An N+ contact region 174 is provided on the P well region 163; the N+ contact region 174 is used as the N+ lead of the collector terminal of the LIGBT, and is the cathode of a diode generated during reverse conduction.
- both the P+ contact region 173 and the N+ contact region 174 are electrically connected to the collector terminal.
- the direction perpendicular to the plane where the substrate is located is defined as the third direction, that is, the stacking direction of each layer structure.
- Two first and second directions perpendicular to each other are defined on a plane parallel to the substrate.
- the entire N well region 162 in the related embodiment is separated and becomes several independent ones (Fig. type N-well region), so that not only no additional parallel FWD is needed for freewheeling, but also the turn-off rate of the switch during the LIGBT reverse recovery stage can be improved.
- the N+ contact region 174 (specifically, for example, a part other than the upper surface) is in direct contact with at least a part of the P well region 163; a PN junction is formed between the two, and is specifically P/N+. At least a part of the P well region 163 (at least including the part where the lower surface is located) is in direct contact with the drift region 121; a PN junction is formed between the two, and is specifically P/N-.
- the potential barrier between the P well region 163 and the drift region 121 is obviously lower than the potential barrier between the P well region 163 and the N well region 162 in the related embodiment.
- more than two N well regions arranged at intervals include at least the first N well region 1621 and the second N well region 1622 ; the P well region 163 includes at least the first N well region 1621 and the second N well region The first P well region between regions 1622 (because there is only one P well region in the section shown in FIG. 3 , so refer to the P well region 163 in the figure); The areas are equal, and the first N well region 1621 and the second N well region 1622 are distributed symmetrically with respect to the first P well region.
- the areas of the first N well region and the second N well region are equal, and the first N well region and the second N well region are symmetrically distributed relative to the first P well region, when the device is conducting forward, The current can flow more evenly to each P+ contact area of the collector area, making the conduction characteristics of the device more stable; on the contrary, if the distribution is asymmetrical or non-uniform, it is easy to cause the device to advance before the PNP stage. When turned on, the entire device loses the conductance modulation effect and becomes an LDMOS. The same problem will also occur during reverse freewheeling.
- the freewheeling characteristics of the reverse conduction type diode will decrease, the resistance will become larger and it will not be easy to recover quickly; while the first N well region and the second N well region When the areas are equal and symmetrically distributed, the freewheeling characteristics are better and the recovery is faster.
- the first N well region 1621 , the first P well region and the second N well region 1622 are sequentially arranged, for example, along the first direction. This first direction is also the direction from the emitter region to the collector region.
- the first N-well region 1621 , the first P-well region and the second N-well region 1622 may be sequentially adjacent to save area.
- the N+ contact region 174 Along the direction parallel to the plane where the substrate is located, the surroundings of the N+ contact region 174 are covered by the P well region 163 . It can be understood that after the P well region 163 covers the N+ contact region 174, there will be no snap-back phenomenon like common LIGBTs at the initial stage of LIGBT turn-on (that is, when the forward voltage reaches a certain level, the current increases and the voltage decreases instead. ), because the N+ contact region 174 does not participate in the work when the LIGBT is turned on in the forward direction. Part of the minority carriers will pass through the PN junction barrier formed by the N+ contact region 174 and the P well region 163 and recombine with the N+ contact region 174, thereby reducing LIGBT tailing and turn-off loss.
- FIG. 4 is a schematic cross-sectional view of a reverse conduction lateral IGBT provided in the second embodiment.
- the N+ contact region 174 includes a first portion 1742 and a second portion 1744;
- the first portion 1742 includes a sidewall portion and a bottom portion, and the sidewall portion extends along a direction perpendicular to the plane where the substrate is located, The bottom is connected to the side wall on the side close to the substrate;
- the second part 1744 is connected to the side wall on the side away from the substrate; the depth of the side wall is greater than the depth of the second part 1744 .
- the bottom of the second part 1744 and the first part 1742 can be used as the horizontal N+ lead-out of the LIGBT collector terminal; and the side wall of the first part 1742 can be used as the longitudinal N+ lead-out of the LIGBT collector terminal; the above are generated during reverse conduction cathode of the diode.
- This second embodiment further achieves the following beneficial effects: on the one hand, the contact area of N+ is increased in the collector region, i.e., the lateral N+ and the vertical N+, and then the upper surface of the N+ contact region is electrically contacted; because the N+ The contact area is large, so the role of N+ as a reverse diode can be maximized, which greatly enhances the reverse flow capability of the reverse conduction LIGBT; at the same time, when it is used as a diode for reverse recovery, the minority carrier holes move along the side wall The number is greater than the number moving along the upper surface, so the path of minority carrier movement is shorter, which can further improve the efficiency of hole recombination, increase the reverse recovery time trr, and reduce the peak current Irr during reverse recovery.
- the area of the LIGBT collector region can also be greatly reduced, because the pitch (that is, the pitch) of the structure forming the first part 1742 (specifically, the trench structure) can be designed to be very small, and in the case of the same depth The area of N+ injection will not be reduced, so the overall area of LIGBT can be reduced by reducing the area of the collector region.
- the above-mentioned first part 1742 can be formed by first forming a trench in the P well region 163, doping the side surface and the bottom surface of the trench; then, filling the trench, and forming The second portion 1744 described above is formed.
- the doping is performed by, for example, ion implantation and other processes.
- a trench is formed in the P-well region 163; the sidewall portion and the bottom of the first portion 1742 are formed by doping the side surface and the bottom surface of the trench, respectively.
- the cross-sectional shape of the first portion 1742 may be similar to the shape of the groove formed, for example, U-shaped.
- a filling structure 180 is formed in the trench; the second portion 1744 is located on the filling structure 180 .
- the material of the filling structure 180 includes insulating material and/or polysilicon.
- the material of the filling structure 180 includes an insulating material, such as silicon oxide; and polysilicon may be further filled on the insulating material, thereby forming the second portion 1744 in the polysilicon.
- polysilicon can be directly filled in the trench, and the second portion 1744 is formed on the upper surface of the polysilicon.
- At least a filling material is included.
- the depth of the sidewall portion of the first portion 1742 is, for example, greater than the depth of the P+ contact region 173 .
- 5a-5c are schematic top views of the collector region of the reverse conduction lateral IGBT in an alternative embodiment.
- the number of the above-mentioned P well regions can be multiple, and the multiple N+ contact regions are respectively located in the multiple P well regions; the multiple N+ contact regions and the P+ contact regions are alternately distributed on a plane parallel to the substrate. .
- the P+ contact region is not explicitly shown, it can be understood that there is a P+ contact region between two adjacent N+ contact regions no matter along the first direction or along the second direction. Further, there is a P+ contact region between two adjacent N+ contact regions, and there is an N+ contact region between two adjacent P+ contact regions.
- FIG. 5 b shows a possible situation, that is, the P+ contact region is located between each N+ contact region, and specifically is located between each P well region.
- the P+ contact regions are connected as a whole, and the P well regions and the N+ contact regions located in the corresponding P well regions are similarly distributed in the P+ contact regions in an island shape.
- the staggered distribution structure is more suitable for high current density; high current LIGBT is prone to snap-back phenomenon in the emitter region, and N+
- the staggered layout with P+ can greatly eliminate the snap-back condition of the device, making the PN junction not easy to conduct, thereby improving the safe working area of LIGBT.
- FIG. 5 a and FIG. 5 b do not show the situation inside the device (inside the top silicon layer 120 ), the dotted line in FIG. 5 c indicates the N well region inside the top silicon layer 120 . As shown in FIG. 5c, more than two N-well regions arranged at intervals may be alternately distributed with multiple P-well regions on a plane parallel to the substrate.
- a plurality of N well regions and a plurality of P well regions are arranged in the manner of "N well region-P well region-N well region"; along the second direction, the plurality of The N well regions and the multiple P well regions are also arranged in the manner of "N well region-P well region-N well region".
- the N well regions should be arranged at intervals below the P+ contact regions.
- the N-well region may be adjacent to the P-well region; of course, the present application does not exclude the situation that there is a gap between them.
- the P well region On the upper surface of the top silicon layer 120, the P well region should have an exposed portion; while the N well region may not be exposed.
- the upper surface mentioned in each embodiment of the present application should be understood as the surface of the corresponding structure away from the substrate; correspondingly, the lower surface should be understood as the surface of the corresponding structure close to the substrate.
- embodiments of the present application should not be limited to the particular shapes of regions shown herein but are to include deviations in shapes that result, for example, from manufacturing techniques.
- an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region.
- a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation was performed.
- the regions shown in the figures are schematic in nature and their shapes do not indicate the actual shape of a region of a device and are not intended to limit the scope of the application.
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Abstract
Description
Claims (15)
- 一种逆导型横向绝缘栅双极型晶体管,包括:形成于衬底中的漂移区,位于所述漂移区上的栅极,位于所述漂移区上且靠近所述栅极一侧的发射极区域,以及位于所述漂移区上且远离所述栅极一侧的集电极区域;其中,在所述漂移区的所述集电极区域所在的一侧设置有两个以上间隔布置的N阱区;在两个以上间隔布置的所述N阱区之间设置有P阱区;在所述N阱区上设置有P+接触区;在所述P阱区上设置有N+接触区;所述P+接触区和所述N+接触区均与集电极引出端导电连接。
- 根据权利要求1所述的逆导型横向绝缘栅双极型晶体管,其中两个以上间隔设置的所述N阱区至少包括第一N阱区和第二N阱区;所述P阱区至少包括设置在所述第一N阱区和所述第二N阱区之间的第一P阱区;所述第一N阱区和所述第二N阱区的面积相等,且所述第一N阱区和所述第二N阱区相对于所述第一P阱区对称分布。
- 根据权利要求2所述的逆导型横向绝缘栅双极型晶体管,其中从所述发射极区域到所述集电极区域的方向,所述第一N阱区、所述第一P阱区和所述第二N阱区依次布置。
- 根据权利要求1所述的逆导型横向绝缘栅双极型晶体管,其中沿平行于所述衬底所在平面的方向上,所述N+接触区的四周被所述P阱区包覆。
- 根据权利要求1所述的逆导型横向绝缘栅双极型晶体管,其中所述N+接触区包括第一部分和第二部分;所述第一部分包括侧壁部和底部,所述侧壁部沿垂直于所述衬底所在平面的方向上延伸,所述底部在靠近所述衬底的一面连接所述侧壁部;所述第二部分在远离所述衬底的一面连接所述侧壁部;所述侧壁部的深度大于所述第二部分的深度。
- 根据权利要求5所述的逆导型横向绝缘栅双极型晶体管,其中所述侧壁部的深度大于所述P+接触区的深度。
- 根据权利要求5所述的逆导型横向绝缘栅双极型晶体管,其中在所述P阱区内形成有沟槽;所述第一部分的所述侧壁部和所述底部分别通过对所述沟槽的侧表面和底表面进行掺杂而形成。
- 根据权利要求7所述的逆导型横向绝缘栅双极型晶体管,其中在所述沟槽内形成有填充结构;所述第二部分位于所述填充结构上。
- 根据权利要求8所述的逆导型横向绝缘栅双极型晶体管,其中所述填充结构的材料包括绝缘材料和/或多晶硅。
- 根据权利要求1所述的逆导型横向绝缘栅双极型晶体管,其中所述P阱区的数量为多个,多个N+接触区分别位于多个所述P阱区内;多个N+接触区与所述P+接触区在平行于所述衬底所在的平面上交错分布。
- 根据权利要求10所述的逆导型横向绝缘栅双极型晶体管,其中两个以上间隔设置的所述N阱区与多个所述P阱区在平行于所述衬底所在的平面上交错分布。
- 根据权利要求1所述的逆导型横向绝缘栅双极型晶体管,其中所述P阱区与所述漂移区之间的势垒低于所述P阱区与所述N阱区之间的势垒。
- 根据权利要求1所述的逆导型横向绝缘栅双极型晶体管,其中还包括位于所述漂移区上且靠近所述栅极所在的一侧的沟道区,所述沟道区形成导电沟道;其中,所述N阱区与所述沟道区间隔设置,以作为所述逆导型横向绝缘栅双极型晶体管的N型缓冲层。
- 根据权利要求13所述的逆导型横向绝缘栅双极型晶体管,其中在所述沟道区内设置有具有第一导电类型的衬底欧姆接触区和具有第二导电类型的源极欧姆接触区,所述源极欧姆接触区在朝向所述栅极的一侧与所述沟道区接触,以在所述沟道区内感生出沟道。
- 根据权利要求1所述的逆导型横向绝缘栅双极型晶体管,其中还包括形成于所述漂移区和所述栅极之间的场氧化层,所述场氧化层作为所述漂移区和所述栅极之间的隔离场区。
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CN101969050A (zh) * | 2010-08-27 | 2011-02-09 | 东南大学 | 一种绝缘体上硅可集成大电流n型组合半导体器件 |
CN103413824A (zh) * | 2013-07-17 | 2013-11-27 | 电子科技大学 | 一种rc-ligbt器件及其制作方法 |
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