WO2022252229A1 - 量化器、∑-δ调制器及噪声整形方法 - Google Patents

量化器、∑-δ调制器及噪声整形方法 Download PDF

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WO2022252229A1
WO2022252229A1 PCT/CN2021/098441 CN2021098441W WO2022252229A1 WO 2022252229 A1 WO2022252229 A1 WO 2022252229A1 CN 2021098441 W CN2021098441 W CN 2021098441W WO 2022252229 A1 WO2022252229 A1 WO 2022252229A1
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signal
quantization error
capacitor
integrator
period
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PCT/CN2021/098441
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English (en)
French (fr)
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王琨玉
周莉
陈杰
陈明辉
陈鸣
徐文静
张成彬
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中国科学院微电子研究所
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Priority to US17/422,050 priority Critical patent/US11611353B2/en
Priority to PCT/CN2021/098441 priority patent/WO2022252229A1/zh
Publication of WO2022252229A1 publication Critical patent/WO2022252229A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/438—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path
    • H03M3/44—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path with provisions for rendering the modulator inherently stable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/344—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/464—Details of the digital/analogue conversion in the feedback path
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step

Definitions

  • the present disclosure relates to the electrical field, and in particular to a quantizer for a ⁇ - ⁇ modulator, a ⁇ - ⁇ modulator and a noise shaping method.
  • the traditional ⁇ - ⁇ modulator usually adopts the method of cascading multiple analog integrators to achieve high-order suppression of quantization noise, thereby reducing the power of quantization noise and improving its signal-to-noise ratio.
  • the stability of the loop will gradually deteriorate, and the power consumption of the system will further increase.
  • a quantizer with a noise shaping function is usually introduced into the ⁇ - ⁇ modulator, but the above-mentioned ⁇ - ⁇ modulator is difficult to Enables high-order noise shaping at lower power consumption.
  • the present disclosure provides a quantizer for a sigma-delta modulator, a sigma-delta modulator and a noise shaping method.
  • a quantizer for a sigma-delta modulator comprising: an integrator, used for the K-th sampling period according to the internal signal, the quantization error signal of the K-1th period, The quantization error signal filtered in the K-1 cycle and the filtered quantization error signal in the K-2 cycle generate the quantization error signal of the K cycle; where K is a positive integer greater than 1; the integral capacitor is used for Save the quantization error signal of the Kth period and use it to weight the internal signal in the K+1 sampling period; a passive low-pass filter is used to collect the quantization error signal of the Kth period in the Kth discharge period, And generate a filtered quantization error signal accordingly, and feed back the filtered quantization error signal to the integrator at the K+1 sampling period and the K+2 sampling period; and a comparator for discharging at the K The cycle quantizes the quantization error signal of the Kth cycle to output a digital code.
  • the passive low-pass filter includes: a first passive low-pass filter and a second passive low-pass filter; wherein, the first passive low-pass filter is coupled to the positive-phase input port of the integrator and the positive-phase output port; the second passive low-pass filter is coupled to the negative-phase input port and the negative-phase output port of the integrator; the first passive low-pass filter and the second passive low-pass filter include: a first capacitor, used Collecting the quantization error signal of the Kth period in the Kth discharge period, and generating a filtered quantization error signal accordingly, and feeding back the filtered quantization error signal to the integrator in the K+1 sampling period; and The second capacitor and the third capacitor are respectively used to collect the quantization error signals of the odd period and the even period, and generate a filtered quantization error signal accordingly, and feed back the filtered quantization error signal to the integrator in the K+2 sampling period Signal.
  • a sigma-delta modulator including: a quantizer, the quantizer is the above quantizer; a front part, the front part includes a front input port and a front output port, respectively for The input signal is received and the internal signal is output, and the front section is used for generating the internal signal according to the input signal.
  • the front section includes a first analog integrator, a second analog integrator and a second digital-to-analog converter; the second digital-to-analog converter is coupled to the output port of the quantizer and the second feedback of the first analog integrator Between the port and the third feedback port of the second analog integrator, it is used to convert the digital code output by the quantizer, and accordingly provide the second feedback signal; the first analog integrator is used to receive the input signal and the second feedback signal , and generate the first integral signal accordingly; the second analog integrator is used to receive the input signal, the second feedback signal and the first integral signal, and generate an internal signal accordingly.
  • the front part also includes a first digital-to-analog converter, which is used to convert the digital code output by the quantizer, and accordingly provides a first feedback signal;
  • the quantizer also includes a first feedback port, coupled to the positive input port of the integrator The negative input port and the output port of the first digital-to-analog converter are used to receive the first feedback signal;
  • the integrator also integrates the internal signal according to the first feedback signal.
  • the sigma-delta modulator further includes a digital integrator, coupled to the output port of the quantizer, for integrating the digital code output by the quantizer to provide the integrated digital code.
  • a digital integrator coupled to the output port of the quantizer, for integrating the digital code output by the quantizer to provide the integrated digital code.
  • the front section includes a first analog integrator, a second analog integrator and a second digital-to-analog converter; the second digital-to-analog converter is coupled to the output port of the digital integrator and the second analog integrator of the first analog integrator.
  • the second analog integrator Between the feedback port and the third feedback port of the second analog integrator, it is used to convert the digital code output by the digital integrator, and accordingly provide the second feedback signal; the first analog integrator is used to receive the input signal and the second Feedback signal, and generate the first integral signal accordingly;
  • the second analog integrator also includes a fourth feedback port, coupled to the output port of the first digital-to-analog converter, for receiving the first feedback signal;
  • the second analog integrator also An internal signal is generated according to the input signal, the first integrated signal, the second feedback signal and the first feedback signal.
  • the first analog integrator includes four capacitors, wherein: the fourth capacitor and the fifth capacitor are used to collect the input signal and the second feedback signal, and save the difference between the input signal and the second feedback signal; the sixth capacitor and the seventh capacitor, for receiving the difference between the input signal and the second feedback signal, and generating the first integrated signal accordingly.
  • the second analog integrator includes six capacitors, wherein: the eighth capacitor and the ninth capacitor are used to collect the first integrated signal and store the first integrated signal; the tenth capacitor and the eleventh capacitor are used to collect The input signal and the second feedback signal, and save the difference between the input signal and the second feedback signal; the twelfth capacitor and the thirteenth capacitor are used to receive the first integral signal and the difference between the input signal and the second feedback signal, And generate internal signals accordingly.
  • the second analog integrator includes six capacitors, wherein: the eighth capacitor and the ninth capacitor are used to collect the first integral signal and the first feedback signal, and save the difference between the first integral signal and the first feedback signal ; The tenth capacitor and the eleventh capacitor are used to collect the input signal and the second feedback signal, and save the difference between the input signal and the second feedback signal; the twelfth capacitor and the thirteenth capacitor are used to receive the first integral The difference between the input signal and the first feedback signal and the difference between the input signal and the second feedback signal are used to generate an internal signal.
  • a noise shaping method comprising:
  • the internal signal is collected by the integrator, the quantization error signal of the K-1th period stored on the integrating capacitor, and the quantization of the K-1th period filtered by the passive low-pass filter feedback
  • the error signal and the quantization error signal filtered in the K-2th cycle are used to generate the quantization error signal of the Kth cycle; wherein, the quantization error signal of the Kth cycle is stored on the integral capacitor, and the K+ 1 sampling period weighted internal signal; where K is a positive integer greater than 1;
  • the quantization error signal of the K-th cycle is collected through a passive low-pass filter, and a filtered quantization error signal is generated accordingly, so that the K+1 sampling cycle and the K+2-th sampling cycle feeds back the filtered quantization error signal to the integrator for sampling periods;
  • the quantization error signal of the Kth period is quantized by a comparator to output a digital code.
  • the quantization error signal of the Kth cycle is collected through a passive low-pass filter, and a filtered quantization error signal is generated accordingly to integrate to the K+1 sampling cycle and the K+2 sampling cycle
  • the encoder feeds back a filtered quantization error signal consisting of:
  • FIG. 1A and FIG. 1B show a schematic structural diagram of a quantizer for a sigma-delta modulator according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic structural diagram of a sigma-delta modulator according to an embodiment of the present disclosure
  • Fig. 3 shows a schematic structural diagram of a sigma-delta modulator according to another embodiment of the present disclosure
  • FIG. 4 shows a schematic diagram of a circuit structure of a first analog integrator according to an embodiment of the present disclosure
  • FIG. 5 shows a schematic circuit structure diagram of a second analog integrator according to an embodiment of the present disclosure
  • FIG. 6 shows a schematic circuit structure diagram of a quantizer for a sigma-delta modulator according to an embodiment of the present disclosure
  • Fig. 7 shows the working timing diagram of the quantizer circuit in Fig. 6 in the sampling period and the discharging period
  • Fig. 8 shows the working timing diagram of the passive low-pass filter in Fig. 6;
  • FIG. 9 shows a flowchart of a noise shaping method according to an embodiment of the present disclosure.
  • FIG. 1A shows a schematic structural diagram of a quantizer for a sigma-delta modulator according to an embodiment of the present disclosure.
  • the quantizer used for the ⁇ - ⁇ modulator specifically includes: signal input terminals IN1 and IN2, an integrator 101, a comparator 102, two integrating capacitors Cf, a first passive low-pass filter 103, The second passive low-pass filter 104 and the signal output terminal OUT1.
  • the signal input terminals IN1 and IN2 are used to collect internal signals in the Kth sampling period.
  • the internal signal is specifically generated by the front-end part of the sigma-delta modulator according to the input signal.
  • the front-end part can, for example, perform first-order noise shaping on the input signal, and then generate the internal signal. This will be described in detail later.
  • Integrator 101 is used in the Kth sampling period based on the internal signal, the quantization error signal of the K-1th period, the filtered quantization error signal of the K-1th period, and the filtered quantization error of the K-2th period Signal to generate the quantization error signal of the Kth period, where K is a positive integer greater than 1.
  • Two integrating capacitors Cf are respectively coupled to the integrator 101, and the integrating capacitor Cf is used to store the quantization error signal of the Kth period, and is used for weighting the internal signal in the K+1th sampling period.
  • the input port and the output port of the first passive low-pass filter 103 are, for example, respectively coupled to the non-inverting input port and the non-inverting output port of the integrator 101
  • the input port and the output port of the second passive low-pass filter 104 are, for example, respectively coupled to The negative input port and the negative output port of the integrator 101 .
  • Both the first passive low-pass filter 103 and the second passive low-pass filter 104 are used to collect the quantization error signal of the Kth cycle in the Kth discharge cycle, and generate a filtered quantization error signal accordingly, and The filtered quantization error signal is fed back to the integrator at the K+1 sampling period and the K+2 sampling period.
  • the comparator 102 is connected to the signal output terminal OUT1, and the comparator 102 is used for quantizing the quantization error signal of the Kth cycle in the Kth discharge cycle, outputting a digital code and providing a discharge time for the discharge cycle.
  • the digital code output by the comparator 102 is output to the outside through the signal output terminal OUT1.
  • the internal signal is input to the quantizer through the signal input terminals IN1 and IN2.
  • the first passive low-pass filter 103 and the second passive low-pass filter 104 respectively filter the quantization error signal of the K-1th cycle and the quantization error signal of the K-2th cycle Feedback to the input of the quantizer and summed with the internal signal.
  • the above three signals are superimposed by the integrator 101 with the quantization error signal of the K-1th period stored on the integrating capacitor Cf to generate the quantization error signal of the Kth period.
  • the integrating capacitor Cf saves the quantization error signal of the Kth period, and is used to weight the internal signals collected by the input terminals IN1 and IN2 and the first passive low-pass filter 103 and the second passive low-pass filter 103 in the K+1th sampling period
  • a passive low pass filter 104 feeds back the filtered quantization error signal at the input of the quantizer.
  • the comparator 102 quantizes the quantization error signal of the Kth period, and at the same time the integrating capacitor Cf starts to discharge.
  • the comparator 102 detects that the level relationship of the output port of the integrator 101 is reversed, the discharge of the integrating capacitor Cf ends, and the quantization ends at the same time.
  • the comparison cycle experienced before the comparator 102 detects the reversal is the output result of the quantizer .
  • the comparator 102 quantizes the error and outputs a digital code through the signal output terminal OUT1.
  • the integral capacitor Cf in the last half cycle of the clock of the comparator 102, can be reversely charged for half a comparison cycle, so that the quantization error signal on the capacitor Cf can be reduced to half of the original value, and more can be obtained. Good noise shaping effect.
  • the first passive low-pass filter 103 and the second passive low-pass filter 104 respectively collect the quantization error signal of the Kth cycle stored on the integrating capacitor Cf, and generate The filtered quantization error signal is fed back to the integrator 101 at the K+1 sampling period and the K+2 sampling period.
  • FIG. 1B shows a schematic structural diagram of a quantizer for a sigma-delta modulator according to another embodiment of the present disclosure.
  • the quantizer for the ⁇ - ⁇ modulator specifically includes: signal input terminals IN1 and IN2, an integrator 101, a comparator 102, two integrating capacitors Cf, a first passive low-pass filter 103, The second passive low-pass filter 104, the first feedback port 105 and the signal output port OUT1.
  • the signal input terminals IN1 and IN2, the integrator 101, the comparator 102, two integrating capacitors Cf, the first passive low-pass filter 103, the second passive low-pass filter 104 and the signal output terminal OUT1 are the same as those described above have the same or similar functions, and the repeated parts will not be repeated.
  • the first feedback port 105 is coupled to the positive input port and the negative input port of the integrator 101, and the first feedback port 105 is used to receive the first feedback signal fed back from the previous part in the Kth sampling period, and The first feedback signal is fed back to the integrator 101, and the integrator 101 also integrates internal signals according to the first feedback signal.
  • the integrator 101 is based on the internal signal, the first feedback signal, the quantization error signal of the K-1th cycle, the filtered quantization error signal of the K-1th cycle, and the filtered
  • the quantization error signal of the K-th cycle is generated by the quantization error signal, the process is similar to the process described above, and will not be repeated here.
  • the first passive low-pass filter and the second passive low-pass filter include: a first capacitor, a second capacitor and a third capacitor.
  • the first capacitor is used to collect the quantization error signal of the Kth cycle in the Kth discharge cycle, and generate a filtered quantization error signal accordingly, and feed back the filtered quantization error signal to the integrator in the K+1 sampling cycle Quantization error signal.
  • the second capacitor and the third capacitor are used to collect the quantization error signals of the odd period and the even period respectively, and generate a filtered quantization error signal accordingly, and feed back the filtered quantization error signal to the integrator in the K+2 sampling period Signal.
  • the first passive low-pass filter 103 and the second passive low-pass filter 104 each include a first capacitor, a second capacitor and a third capacitor (not shown in FIG. 1 ).
  • the first capacitor is used to collect the quantization error signal of the Kth cycle in the Kth discharge cycle, and generate a filtered quantization error signal accordingly, and feed back the filtered quantization error signal to the integrator in the K+1 sampling cycle Quantization error signal.
  • the second capacitor and the third capacitor are used to collect the quantization error signals of the odd period and the even period respectively, and generate a filtered quantization error signal accordingly, and feed back the filtered quantization error signal to the integrator in the K+2 sampling period Signal.
  • the quantizer in the embodiments of the present disclosure has second-order noise shaping capability will be described below.
  • the quantization error signal introduced by the Kth period comparator 102 after quantization is eq(z).
  • the digital signal D(z) output by the quantizer and the input signal X(z) satisfy the following relationship:
  • D(z) is the digital signal output by the Kth period quantizer
  • X(z) is the input signal of the Kth period ⁇ - ⁇ modulator
  • (1-z -1 )z - 1 eq(z) is the sum of the filtered quantization error signal of the K-1th cycle and the filtered quantization error signal of the K-2th cycle fed back by the passive low-pass filter
  • z -1 eq(z ) is the quantization error signal of the K-1th period saved on the integrating capacitor
  • eq(z) is the quantization error signal introduced by the comparator 102 after quantization of the Kth period.
  • the quantizer in the embodiment of the present disclosure uses a passive low-pass filter structure to feed back the quantization error signal to the input end of the quantizer, thereby realizing second-order noise shaping.
  • the passive low-pass filter is composed of passive components, and its sampling signal is the output signal of the discharge cycle of the quantizer (that is, the quantization error signal), it does not consume additional energy. Therefore, the quantizer in the present disclosure is enhancing system noise shaping capability without causing a significant increase in system power consumption. Since the passive low-pass filter has almost no energy consumption, it will be more energy-efficient when the number of quantized effective bits of the modulator is the same, which can effectively solve the problem of large power consumption in the traditional second-order noise-shaping integral quantizer.
  • Embodiments of the present disclosure provide a sigma-delta modulator including a quantizer and a front-end part.
  • the front part includes a front input port and a front output port, which are respectively used for receiving input signals and outputting internal signals, and the front part is used for generating internal signals according to the input signals.
  • the quantizer in the sigma-delta modulator has the same or similar structure and working process as the quantizer described above, and the repeated parts will not be described in detail.
  • the quantizer includes an integrator, an integrating capacitor, a passive low-pass filter and a comparator.
  • the integrator is used to generate the Kth sampling period according to the internal signal, the quantized signal of the K-1th period, the filtered quantized signal of the K-1th period, and the filtered quantized signal of the K-2th period A quantized signal of periods, where K is a positive integer greater than 1.
  • the integral capacitor is used to store the quantized signal of the Kth cycle, and is used to weight the internal signal in the K+1th sampling cycle.
  • the passive low-pass filter is used to collect the quantized signal of the K-th cycle in the K-th discharge cycle, and generate a filtered quantized signal based on it, and send it to the K+1 sampling cycle and the K+2 sampling cycle.
  • the integrator feeds back the filtered quantized signal.
  • the comparator is used to quantize the quantized signal of the Kth period in the Kth discharge period to output digital codes.
  • the passive low pass filter includes a first passive low pass filter and a second passive low pass filter.
  • the first passive low-pass filter is coupled to the positive-phase input port and the positive-phase output port of the integrator
  • the second passive low-pass filter is coupled to the negative-phase input port and negative-phase output port of the integrator.
  • the first passive low-pass filter and the second passive low-pass filter include: a first capacitor, a second capacitor and a third capacitor. The first capacitor is used to collect the quantized signal of the Kth period in the Kth discharge period, and generate a filtered quantized signal accordingly, and feed back the filtered quantized signal to the integrator in the K+1th sampling period.
  • the second capacitor and the third capacitor are respectively used to collect quantized signals of odd and even periods, and generate filtered quantized signals accordingly, and feed back the filtered quantized signals to the integrator at the K+2 sampling period.
  • the quantizer has the capability of second-order noise shaping.
  • the quantizer in the embodiment of the present disclosure adopts a passive low-pass filter structure to feed back the quantization error signal collected in the discharge cycle to the input end of the quantizer, so as to realize second-order noise shaping. Since the passive low-pass filter is composed of passive components, and its sampling signal is the output signal of the discharge cycle of the quantizer (that is, the quantization error signal), it does not consume additional energy. Therefore, the quantizer in the present disclosure is enhancing system noise shaping capability without causing a significant increase in system power consumption.
  • the passive low-pass filter Since the passive low-pass filter has almost no energy consumption, it will be more energy-saving when the quantization effective number of digits of the ⁇ - ⁇ modulator is the same, which can effectively reduce the power consumption of the quantizer, thereby reducing the power consumption of the ⁇ - ⁇ modulator. power consumption.
  • FIG. 2 shows a schematic structural diagram of a sigma-delta modulator according to an embodiment of the present disclosure.
  • the sigma-delta modulator includes a front section 21, a quantizer 22, and a signal output port OUT.
  • Quantizer 22 includes an integrator, an integrating capacitor, a passive low-pass filter and a comparator. Wherein, the structure and working process of the integrator, integrating capacitor, passive low-pass filter and comparator are the same or similar to those described above, and will not be repeated here.
  • the front section 21 includes a signal input port IN, a first analog integrator 211 , a second analog integrator 212 and a second digital-to-analog converter 213 .
  • the input port IN is used to receive input signals.
  • the second digital-to-analog converter 213 is coupled between the output port of the quantizer 22 and the second feedback port of the first analog integrator 211 and the third feedback port of the second analog integrator 212, for converting the output of the quantizer 22 digital code, and provide a second feedback signal accordingly.
  • the first analog integrator 211 is coupled between the signal input port IN and the input port of the second analog integrator 212 for receiving the input signal and the second feedback signal, and generating the first integrated signal accordingly.
  • the input port of the second analog integrator 212 is also coupled to the signal input port 1N, and the second analog integrator 212 is used to receive the input signal, the second feedback signal and the first integration signal, and generate an internal signal accordingly.
  • the first analog integrator 211 includes four capacitors, wherein the fourth capacitor and the fifth capacitor are used to collect the input signal and the second feedback signal, and store the input signal and the second feedback signal difference.
  • the sixth capacitor and the seventh capacitor are used to receive the difference between the input signal and the second feedback signal, and generate the first integrated signal accordingly.
  • Using the above four capacitors can implement first-order noise shaping on the input signal and the signal fed back by the second digital-to-analog converter.
  • the second analog integrator 212 includes six capacitors, wherein the eighth capacitor and the ninth capacitor are used to collect the first integrated signal and save the first integrated signal; the tenth capacitor and the tenth capacitor A capacitor is used to collect the input signal and the second feedback signal, and save the difference between the input signal and the second feedback signal; the twelfth capacitor and the thirteenth capacitor are used to receive the first integration signal and the input signal and the second feedback signal , and generate an internal signal accordingly.
  • Using the above six capacitors can implement first-order noise shaping on the input signal, the integrated signal output by the first analog integrator, and the signal fed back by the second digital-to-analog converter.
  • the process of performing quantization noise shaping is the same as the process described above, and will not be repeated here.
  • Fig. 3 shows a schematic structural diagram of a sigma-delta modulator according to another embodiment of the present disclosure.
  • the sigma-delta modulator includes a front section 31, a quantizer 32, a digital integrator 33 and a signal output port OUT.
  • the quantizer 32 includes an integrator, an integrating capacitor, a passive low-pass filter, a comparator and a first feedback port.
  • the structure and working process of the integrator, integrating capacitor, passive low-pass filter, comparator and first feedback port are the same as or similar to those described above, and will not be repeated here.
  • the front section 31 includes a signal input port IN, a first analog integrator 311 , a second analog integrator 312 , a first digital-to-analog converter 314 and a second digital-to-analog converter 313 .
  • the input port lN is used to receive input signals.
  • the first digital-to-analog converter 314 is coupled between the output port of the quantizer 32 and the fourth feedback port of the second analog integrator 312, and is used to convert the digital code output by the quantizer 32 and provide a first feedback signal accordingly .
  • the second digital-to-analog converter 313 is coupled between the output port of the digital integrator 33 and the second feedback port of the first analog integrator 311 and the third feedback port of the second analog integrator 312, for converting the digital integrator 33 output digital code, and provide the second feedback signal accordingly.
  • the first analog integrator 311 is coupled between the signal input port 1N and the input port of the second analog integrator 312 for receiving the input signal and the second feedback signal, and generating the first integrated signal accordingly.
  • the first analog integrator 311 includes four capacitors, wherein the fourth capacitor and the fifth capacitor are used to collect the input signal and the second feedback signal, and store the input signal and the second feedback signal difference.
  • the sixth capacitor and the seventh capacitor are used to receive the difference between the input signal and the second feedback signal, and generate the first integrated signal accordingly.
  • the input port of the second analog integrator 312 is also coupled to the signal input port 1N.
  • the second analog integrator 312 is used to receive the input signal, the first integrated signal, the second feedback signal and the first feedback signal, and generate an internal signal accordingly.
  • the second analog integrator 312 includes six capacitors, wherein the eighth capacitor and the ninth capacitor are used to collect the first integrated signal and the first feedback signal, and store the first integrated signal and the second The difference value of a feedback signal; the tenth capacitor and the eleventh capacitor are used to collect the input signal and the second feedback signal, and store the difference between the input signal and the second feedback signal; the twelfth capacitor and the thirteenth capacitor are used It is used to receive the difference between the first integrated signal and the first feedback signal and the difference between the input signal and the second feedback signal, and generate an internal signal accordingly.
  • the process of performing quantization noise shaping is the same as the process described above, and will not be repeated here.
  • the digital integrator 33 is coupled to the output port of the quantizer 32 for integrating the digital code output by the quantizer 32 to provide the integrated digital code.
  • the digital integrator is essentially an adder, which can accumulate received digital codes such as 3bit digital codes to obtain such as 5bit digital codes, and then transmit them to the signal output port OUT as the system output.
  • the input signal of the quantizer 32 becomes the output signal of the second analog integrator 312 in this cycle and the output signal of the previous cycle
  • the second analog integrator 312 outputs the difference of the signals. Due to the structural characteristics of the ⁇ - ⁇ modulator, the sampling frequency is much higher than the bandwidth of the input signal, and the maximum value of the signal difference of the integration channel will be much smaller than the maximum value of the output signal of the integration channel, so a digital integrator 33 and a first digital-to-analog converter are added The stability of the sigma-delta modulator will be improved after the 314 feedback path.
  • STF is a signal transfer function, which is approximately 1 in this embodiment.
  • the quantization error signal of the K-1th period will be saved on the integral capacitor, and will be fed back to the input terminal of the quantizer after being filtered by a passive low-pass filter.
  • the quantization error of the K-1th cycle, the quantization error of the K-2th cycle, and the quantization error of the K-th cycle can be obtained:
  • eq(z) is the quantization error of the Kth cycle introduced by the comparator quantization.
  • the ⁇ - ⁇ modulator of the embodiment of the present disclosure completes the fourth-order noise shaping of the quantization noise.
  • the quantizer in the ⁇ - ⁇ modulator uses a passive low-pass filter structure to feed back the quantization error signal collected during the discharge cycle to the input of the quantizer. Since the passive low-pass filter is composed of passive components, its The sampling signal is the output signal of the discharge cycle of the quantizer (i.e., the quantization error signal), so it does not consume additional energy. Therefore, the quantizer in the present disclosure does not cause system power consumption while enhancing the system noise shaping capability. A significant increase.
  • the passive low-pass filter Since the passive low-pass filter has almost no energy consumption, it will be more energy-saving when the quantization effective number of digits of the sigma-delta modulator is the same, which can effectively reduce the power consumption of the quantizer, thereby reducing the energy consumption of the sigma-delta modulator. power consumption. That is to say, the sigma-delta modulator in the embodiments of the present disclosure can implement fourth-order noise shaping with low power consumption.
  • FIG. 4 and Fig. 5 respectively show the schematic diagram of the circuit structure of the first analog integrator and the second analog integrator according to the embodiment of the present disclosure
  • Fig. 6 shows the circuit structure used for the sigma-delta modulator according to the embodiment of the present disclosure
  • the schematic diagram of the circuit structure of the quantizer FIG. 7 shows the working timing diagram of the quantizer circuit in FIG. 6 in the sampling period and the discharging period
  • FIG. 8 shows the working timing diagram of the passive low-pass filter in FIG. 6 .
  • the specific working process of the first analog integrator, the second analog integrator and the quantizer in Fig. 3 will be described in detail below with reference to Fig. 4 to Fig. 8 by taking the structure of the ⁇ - ⁇ modulator in Fig. 3 as an example.
  • the first analog integrator 311 (shown in Figure 3) includes signal input ports IN3 and IN4, signal output ports OUT2 and OUT3, capacitor C1 (ie the fourth capacitor), C2 (ie the fifth capacitor) , C3 (that is, the sixth capacitor) and C4 (that is, the seventh capacitor), the second feedback port 401 , the fully differential operational amplifier 402 , switches 1 to 12 and so on.
  • the working mode of the first analog integrator 311 includes a reset phase, a sampling phase and an operation phase.
  • the first analog integrator 311 After the circuit is started, the first analog integrator 311 first enters the reset phase. At this time, the 9th, 10th, 11th, and 12th switches are closed, and the other switches are disconnected. Capacitors C3 and C4 are reset until the charges on the capacitors are 0. The purpose of this processing is to prevent the residual charge from the last signal processing from affecting the current signal processing process. Generally speaking, the reset phase is only used once during signal processing, and then the first analog integrator 311 will continuously cycle through both the sampling phase and the computing phase.
  • the circuit of the first analog integrator 311 After the circuit of the first analog integrator 311 is reset, it enters the sampling phase. At this time, the switches 1, 3, 4, and 6 are closed, and the other switches are disconnected.
  • the current input signal is input through the signal input ports IN3 and IN4 , and the second feedback signal fed back by the second digital-to-analog converter 313 is input through the second feedback port 401 .
  • the voltage difference between the current input signal and the second feedback signal will be stored on the capacitors C1 and C2 (equivalent to completing the difference operation).
  • the switches 2, 5, 7, 8 are closed, and the other switches are opened.
  • the charges stored on the capacitors C1 and C2 are transferred to the capacitors C3 and C4 according to the law of charge conservation through the fully differential operational amplifier 402 to realize first-order noise shaping.
  • the first integrated signal is then output from the signal output ports OUT2 and OUT3.
  • first-order noise shaping implemented by the first analog integrator will be described below by taking the capacitance values of capacitor C1 and capacitor C2 to be equal, and the capacitance values of capacitor C3 and capacitor C4 to be equal.
  • the current input signal is sampled and stored on capacitors C1 and C2, and the total charge is recorded as C 1,2 V in (N).
  • the capacitors C3 and C4 store the voltage signal transferred in the N-1th cycle operation stage, and the total charge is recorded as C 3, 4 V out (N-1), and the capacitors C1 and C2 are The charge of is delayed to C 1,2 V in (N-1).
  • the charge stored on the capacitor is transferred and redistributed.
  • the charge transfer equation can be expressed as:
  • the ratio of capacitors C1 to C3 can be set to 0.2 to 0.5, for example, if the ratio of capacitors C1 to C3 is set to 0.2, the input signal can be reduced to 0.2 times of the original, and at the same time Performs first-order noise shaping on the input signal.
  • the numerical values shown above are only for those skilled in the art to understand the technical solutions of the present disclosure, and are not intended to limit the protection scope of the present disclosure.
  • the ratio of capacitors C1 and C3 can be set according to actual needs, so as to achieve different degrees of reduction or amplification of different input signals, and to complete the first-order noise shaping, which is not limited here.
  • the second analog integrator 312 (shown in FIG. 3) includes signal input ports IN3' and IN4', signal output ports OUT4 and OUT5, capacitor C1' (ie the eighth capacitor), C2' (ie ninth capacitor), C3' (that is, the twelfth capacitor), C4' (that is, the thirteenth capacitor), C5 (that is, the tenth capacitor) and C6 (that is, the eleventh capacitor), the third feedback port 501 , the fourth Feedback port 502, fully differential operational amplifier 503, switches 1'-16 and so on.
  • capacitor C1' ie the eighth capacitor
  • C2' ie ninth capacitor
  • C3' that is, the twelfth capacitor
  • C4' that is, the thirteenth capacitor
  • C5 that is, the tenth capacitor
  • C6 that is, the eleventh capacitor
  • the working mode and principle of the second analog integrator 312 are similar to those of the first analog integrator 311 , which will be briefly described here.
  • the working mode of the second analog integrator 312 includes a reset phase, a sampling phase and an operation phase.
  • the second analog integrator 312 first enters the reset phase after the circuit starts. At this time, the 9', 10', 11', and 12' switches are closed, and the other switches are disconnected. Capacitors C3' and C4' are reset to 0 charges on the capacitors. The purpose of this processing is to prevent the residual charge from the last signal processing from affecting the signal processing process this time. Generally speaking, the reset phase is only used once during signal processing, and then the second analog integrator 312 will cycle through both the sampling phase and the computing phase.
  • the circuit of the second analog integrator 312 After the circuit of the second analog integrator 312 is reset, it enters the sampling phase. At this time, the closed switches 1', 3', 4', 6', 13, 15, and other switches are disconnected.
  • the first integrated signal output by the first analog integrator 311 is input from the signal input ports IN3' and IN4', and the first feedback signal fed back by the first digital-to-analog converter 314 is input from the third feedback port 501.
  • the current input signal is input from the signal input ports IN5 and IN6
  • the second feedback signal fed back by the second digital-to-analog converter 313 is input from the fourth feedback port 502 .
  • capacitors C1' and C2' will store the voltage difference between the first integral signal and the first feedback signal
  • capacitors C5 and C6 will store the voltage difference between the current input signal and the second feedback signal.
  • the switches 2, 5, 7, 8, 14, 16 are closed, and the other switches are opened.
  • the charge stored on the capacitors C1', C2', C5 and C6 will be transferred to the capacitors C3' and C4' according to the charge conservation law through the fully differential operational amplifier 503 to realize the first-order noise shaping, and then the internal signal is output from the output port OUT4 and OUT5 are output to the quantizer 32.
  • the function principle of the second analog integrator is similar to that of the first analog integrator.
  • the capacitance values of capacitor C1' and capacitor C2' are equal
  • the capacitance values of capacitor C3' and C4' are equal
  • the capacitance value of capacitor C5 is equal to that of the first analog integrator.
  • the principle that the second analog integrator implements first-order noise shaping is described by taking the capacitance equal to that of C6 as an example.
  • the difference between the first integral signal and the first feedback signal is stored on the capacitors C1' and C2', and the total charge is recorded as C 1', 2' V out1 (N), the current input signal
  • the difference with the second feedback signal is stored on capacitors C5 and C6, and the total charge is denoted as C 5,6 V in (N).
  • the capacitors C3' and C4' store the voltage signal transferred in the N-1th cycle operation stage, and the total charge is recorded as C 3', 4' V out (N-1), and the capacitor
  • the charges on C1' and C2' become C 1', 2' V out1 (N-1) after a delay
  • the charges on capacitors C5 and C6 become C 5, 6 V in (N-1) after a delay.
  • the charge stored on the capacitor is transferred and redistributed.
  • the charge transfer equation can be expressed as:
  • the ratio of capacitors C1' to C5 can be set to, for example, 0.4 to 0.6.
  • the ratio of capacitors C1' to C5 is set to 0.5.
  • the ratio of the capacitors C5 and C3' is set to 0.5, the input signal can be reduced to 0.5 times of the original, and at the same time, the first-order noise shaping of the input signal can be completed.
  • the numerical values shown above are only for those skilled in the art to understand the technical solutions of the present disclosure, and are not intended to limit the protection scope of the present disclosure.
  • the ratio of capacitors C5 to C1' and the ratio of capacitors C5 to C3' can be set according to actual needs, so as to achieve different degrees of reduction or amplification of different input signals and complete the first-order noise shaping , without limitation here.
  • FIG. 6 shows a schematic circuit structure diagram of a quantizer used in a sigma-delta modulator according to an embodiment of the present disclosure.
  • the quantizer mainly includes signal input terminals IN1 and IN2, an integrator 601, a comparator 602, two integrating capacitors Cf, a first passive low-pass filter 603, and a second passive low-pass filter 604 , the first feedback port 605 .
  • the first passive low-pass filter 603 and the second passive low-pass filter 604 have the same structure and principle of action.
  • the first passive low-pass filter 603 will be used as an example to The working process of passive low-pass filter will be explained.
  • the first passive low-pass filter 603 includes capacitors C11, C7, C8 and corresponding control switches. E.g, Corresponding to the control capacitor C7, Corresponding to the control capacitor C8 (the dotted line part " ⁇ 2" in Fig. 6 indicates that C7 and C8 have corresponding control circuits respectively).
  • Capacitor C11 is equivalent to the first capacitor, which is used to collect the quantization error signal of the K-th cycle in the K-th discharge cycle, and generate a filtered quantization error signal based on it, and feed it back to the integrator in the K+1 sampling cycle
  • the capacitors C7 and C8 are respectively equivalent to the second capacitor and the third capacitor, which are respectively used to collect the quantization error signal of the odd cycle and the even cycle, and generate the filtered quantization error signal accordingly, and in the K+2 sampling periods feed back the filtered quantization error signal to the integrator.
  • FIG. 7 shows the working timing diagram of the quantizer circuit in FIG. 6 in the sampling period and the discharging period
  • FIG. 8 shows the working timing diagram of the passive low-pass filter in FIG. 6 .
  • the working process of the circuit in FIG. 6 will be described in detail below in conjunction with FIG. 7 and FIG. 8 .
  • the working modes of the quantizer 32 include a reset period, a sampling period and a discharge period.
  • the reset period of the quantizer is similar to the reset phase of the first analog integrator 311, and its main purpose is to clear the residual charge on the capacitor, so as to avoid the influence of the residual charge in the last signal processing on the current signal processing process .
  • the reset period is only applied once during signal processing, after which the quantizer 32 cycles continuously in both the sampling period and the discharging period (the timing signals ⁇ s and ⁇ d shown in FIG. 7 represent the sampling period and the discharging period, respectively).
  • the passive low-pass filter (including the first passive low-pass filter 603 and the second passive low-pass filter 604) whose transfer function is (1-z -1 ) will also transfer the K-1th cycle
  • the filtered quantization error signal (for example, the quantization error signal of the K-1 cycle fed back by capacitors C11 and C12), the quantization error signal of the K-2 cycle filtered (such as the one fed back by capacitors C7 and C9
  • the filtered quantization error signal of the K-2 period) is fed back to the input of the quantizer.
  • the quantization error signal of K cycles is stored on the capacitor Cf.
  • the quantizing error signal of the Kth period is stored on the integrating capacitor Cf.
  • the comparator 602 quantizes the quantization error signal of the Kth cycle.
  • the discharge direction can be determined by the comparator 602, open or Set to 1 (shown in Figure 6), at this time the discharge of the integrating capacitor Cf begins.
  • the working cycle of the comparator 602 is shown as the square wave 720 in Figure 7.
  • the comparator 602 performs multiple comparisons in the discharge cycle. In this stage, the comparator 602 is in the working state alternately. For pulses 721[1], 722[2 ], 723[3], 724[n], each pulse makes the comparator 602 quantize the input signal and generate a digital code.
  • the working sequence of the first passive low-pass filter 603 is shown in FIG. 8 .
  • Figure 8 and Represent the switch corresponding to the capacitor C11 in Figure 6 and working timing, and Respectively represent the switch corresponding to the capacitor C7 and working timing, and Respectively represent the switch corresponding to the capacitor C8 and working timing.
  • control and closed pulse signals 820 and 860 as shown in Figure 8
  • other switches are turned off, the quantization error signal of the Kth cycle saved on the capacitor C11 is fed back to the input terminal of the quantizer, and the K-th cycle saved on the capacitor C8
  • the quantization error signal of one period is fed back to the input terminal of the quantizer (that is, the quantization error signal stored on the capacitor C8 is delayed by one period and then fed back to the input terminal of the quantizer).
  • control and Closed pulse signals 811 and 850 as shown in FIG. 8
  • other switches are turned off.
  • the capacitors C11 and C8 respectively collect and hold the quantization error signal of the K+1th period on the integrating capacitor Cf.
  • control and Closed pulse signals 821 and 840 as shown in Figure 8
  • other switches are disconnected, the quantization error signal of the K+1th cycle saved on the capacitor C11 is fed back to the input terminal of the quantizer, and the quantization error signal saved on the capacitor C7
  • the quantization error signal of K cycles is fed back to the input terminal of the quantizer (that is, the quantization error signal stored on the capacitor C7 is delayed by one cycle and then fed back to the input terminal of the quantizer).
  • capacitor C11 in the passive low-pass filter directly feeds back the collected quantization error signal to the input terminal of the quantizer in the next sampling period, while capacitors C7 and C8 work alternately to convert the collected quantization error signal The error signal is fed back to the input of the quantizer after a period of delay.
  • the quantizer in the embodiments of the present disclosure adopts the above-mentioned passive low-pass filter structure to feed back the quantization error signal collected in the discharge cycle to the input end of the quantizer, so as to realize second-order noise shaping. Since the passive low-pass filter is composed of passive components, and its sampling signal is the output signal of the discharge cycle of the quantizer (that is, the quantization error signal), it does not consume additional energy. Therefore, the quantizer in the present disclosure is enhancing system noise shaping capability without causing a significant increase in system power consumption.
  • the passive low-pass filter Since the passive low-pass filter has almost no energy consumption, it will be more energy-saving when the quantization effective number of digits of the ⁇ - ⁇ modulator is the same, which can effectively reduce the power consumption of the quantizer, thereby reducing the power consumption of the ⁇ - ⁇ modulator. power consumption.
  • FIG. 9 shows a flowchart of a noise shaping method according to an embodiment of the present disclosure.
  • the noise shaping method includes operations S910-S930.
  • the internal signal is collected by the integrator, the quantization error signal of the K-1th period stored on the integrating capacitor, and the K-1th period of the passive low-pass filter feedback
  • the filtered quantization error signal and the filtered quantization error signal of the K-2th cycle are used to generate the Kth cycle of the quantization error signal.
  • the quantization error signal of the Kth cycle is stored on the integrating capacitor to weight the internal signal in the K+1th sampling cycle, where K is a positive integer greater than 1.
  • the quantization error signal of the Kth cycle is collected through a passive low-pass filter, and a filtered quantization error signal is generated accordingly, for the K+1th sampling cycle and The K+2 sampling period feeds back the filtered quantization error signal to the integrator.
  • the quantization error signal of the K-th period is quantized by the comparator to output a digital code.
  • the quantization error signal of the K-th period is collected through a passive low-pass filter, and a filtered quantization error signal is generated accordingly for the K+1-th sampling Feedback of the filtered quantization error signal to the integrator in the period and the K+2th sampling period further includes operations S921-S922.
  • the first capacitor is used to collect the quantization error signal of the Kth period, and a filtered quantization error signal is generated accordingly, and the filtered quantization error signal is fed back to the integrator in the K+1th sampling period.

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Abstract

本公开提出了一种用于∑-Δ调制器的量化器、∑-Δ调制器及噪声整形方法。该量化器包括：积分器，用于在第K个采样周期依据内部信号、第K-1个周期的量化信号、第K-1个周期经过过滤的量化信号、第K-2个周期经过过滤的量化信号而产生第K个周期的量化信号；其中K为大于1的正整数；积分电容，用于保存第K个周期的量化信号，并在第K+1个采样周期用以加权内部信号；无源低通滤波器，用于在第K个放电周期采集第K个周期的量化信号，并据以产生经过过滤的量化信号，并在第K+1个采样周期以及第K+2个采样周期向积分器反馈经过过滤的量化信号；以及比较器，用于在第K个放电周期对第K个周期的量化信号进行量化，以输出数字码。

Description

量化器、∑-Δ调制器及噪声整形方法 技术领域
本公开涉及电学领域，具体涉及一种用于∑-Δ调制器的量化器、∑-Δ调制器及噪声整形方法。
背景技术
传统的∑-Δ调制器通常采用级联多个模拟积分器的方式，实现对量化噪声的高阶抑制，从而降低量化噪声的功率，提高其信噪比。然而，随着模拟积分器个数的增加，环路的稳定性会逐渐变差，***的功耗也会进一步增大。
相关技术中，为了降低∑-Δ调制器的功耗以及保证环路的稳定性，通常会将带有噪声整形功能的量化器引入∑-Δ调制器中，但是，上述∑-Δ调制器难以在功耗较低的情况下实现高阶噪声整形。
发明内容
本公开提供了一种用于∑-Δ调制器的量化器、∑-Δ调制器及噪声整形方法。
根据本公开的一方面，提供了一种用于∑-Δ调制器的量化器，包括：积分器，用于在第K个采样周期依据内部信号、第K-1个周期的量化误差信号、第K-1个周期经过过滤的量化误差信号、第K-2个周期经过过滤的量化误差信号而产生第K个周期的量化误差信号；其中K为大于1的正整数；积分电容，用于保存第K个周期的量化误差信号，并在第K+1个采样周期用以加权内部信号；无源低通滤波器，用于在第K个放电周期采集第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+1个采样周期以及第K+2个采样周期向积分器反馈经过过滤的量化误差信号；以及比较器，用于在第K个放电周期对第K 个周期的量化误差信号进行量化，以输出数字码。
优选地，无源低通滤波器包括：第一无源低通滤波器和第二无源低通滤波器；其中，第一无源低通滤波器耦合于积分器的正相输入端口和正相输出端口；第二无源低通滤波器耦合于积分器的负相输入端口和负相输出端口；第一无源低通滤波器和第二无源低通滤波器包括：第一电容，用于在第K个放电周期采集第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+1个采样周期向积分器反馈经过过滤的量化误差信号；以及第二电容和第三电容，分别用于采集奇数周期和偶数周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+2个采样周期向积分器反馈经过过滤的量化误差信号。
根据本公开的另一方面，提供了一种∑-Δ调制器，包括：量化器，所述量化器为如上的量化器；前段部分，前段部分包括前段输入端口及前段输出端口，分别用于接收输入信号和输出内部信号，且前段部分用于依据输入信号而产生内部信号。
优选地，前段部分包括第一模拟积分器、第二模拟积分器和第二数模转换器；第二数模转换器，耦接于量化器的输出端口与第一模拟积分器的第二反馈端口、第二模拟积分器的第三反馈端口之间，用于转换量化器输出的数字码，并据以提供第二反馈信号；第一模拟积分器，用于接收输入信号和第二反馈信号，并据以产生第一积分信号；第二模拟积分器，用于接收输入信号、第二反馈信号和第一积分信号，并据以产生内部信号。
优选地，前段部分还包括第一数模转换器，用于转换量化器输出的数字码，并据以提供第一反馈信号；量化器还包括第一反馈端口，耦合于积分器的正输入端口和负输入端口以及第一数模转换器的输出端口，用于接收第一反馈信号；积分器还依据第一反馈信号积分内部信号。
优选地，∑-Δ调制器还包括数字积分器，耦合于量化器的输出端口，用于积分量化器输出的数字码，以提供积分后的数字码。
优选地，前段部分包括第一模拟积分器、第二模拟积分器和第二数模转换器；第二数模转换器，耦接于数字积分器的输出端口与第一模拟 积分器的第二反馈端口、第二模拟积分器的第三反馈端口之间，用于转换数字积分器输出的数字码，并据以提供第二反馈信号；第一模拟积分器，用于接收输入信号和第二反馈信号，并据以产生第一积分信号；第二模拟积分器还包括第四反馈端口，耦合于第一数模转换器的输出端口，用于接收第一反馈信号；第二模拟积分器还依据输入信号、第一积分信号、第二反馈信号和第一反馈信号产生内部信号。
优选地，第一模拟积分器包括四个电容，其中：第四电容和第五电容，用于采集输入信号和第二反馈信号，并保存输入信号和第二反馈信号的差值；第六电容和第七电容，用于接收输入信号和第二反馈信号的差值，并据以产生第一积分信号。
优选地，第二模拟积分器包括六个电容，其中：第八电容和第九电容，用于采集第一积分信号，并保存第一积分信号；第十电容和第十一电容，用于采集输入信号和第二反馈信号，并保存输入信号和第二反馈信号的差值；第十二电容和第十三电容，用于接收第一积分信号以及输入信号和第二反馈信号的差值，并据以产生内部信号。
优选地，第二模拟积分器包括六个电容，其中：第八电容和第九电容，用于采集第一积分信号和第一反馈信号，并保存第一积分信号和第一反馈信号的差值；第十电容和第十一电容，用于采集输入信号和第二反馈信号，并保存输入信号和第二反馈信号的差值；第十二电容和第十三电容，用于接收第一积分信号和第一反馈信号的差值以及输入信号和第二反馈信号的差值，并据以产生内部信号。
根据本公开的另一方面，提供了一种噪声整形方法，包括：
在第K个采样周期内，通过积分器采集内部信号、存储于积分电容上的第K-1个周期的量化误差信号、无源低通滤波器反馈的第K-1个周期经过过滤的量化误差信号和第K-2个周期经过过滤的量化误差信号，并据以产生第K个周期的量化误差信号；其中，第K个周期的量化误差信号保存于积分电容上，以在第K+1个采样周期加权内部信号；其中K为大于1的正整数；
在第K个放电周期内，通过无源低通滤波器采集第K个周期的量化 误差信号，并据以产生经过过滤的量化误差信号，以在第K+1个采样周期以及第K+2个采样周期向积分器反馈经过过滤的量化误差信号；以及
通过比较器对第K个周期的量化误差信号进行量化，以输出数字码。
优选地，通过无源低通滤波器采集第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，以在第K+1个采样周期以及第K+2个采样周期向积分器反馈经过过滤的量化误差信号，包括：
利用第一电容采集第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+1个采样周期向积分器反馈经过过滤的量化误差信号；以及
利用第二电容和第三电容分别采集奇数周期和偶数周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+2个采样周期向积分器反馈经过过滤的量化误差信号。
附图说明
附图用于更好地理解本方案，不构成对本公开的限定。其中：
图1A和图1B示出了根据本公开实施例的用于∑-Δ调制器的量化器的结构示意图；
图2示出了根据本公开实施例的∑-Δ调制器的结构示意图；
图3示出了根据本公开另一实施例的∑-Δ调制器的结构示意图；
图4示出了根据本公开实施例的第一模拟积分器的电路结构示意图；
图5示出了根据本公开实施例的第二模拟积分器的电路结构示意图；
图6示出了根据本公开实施例的用于∑-Δ调制器的量化器的电路结构示意图；
图7示出了图6中的量化器电路在采样周期与放电周期的工作时序图；
图8示出了图6中的无源低通滤波器的工作时序图；
图9示出了根据本公开实施例的噪声整形方法的流程图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开作进一步的详细说明。
图1A示出了根据本公开实施例的用于∑-Δ调制器的量化器的结构示意图。
如图1A所示，用于∑-Δ调制器的量化器具体包括：信号输入端IN1和IN2、积分器101、比较器102、两个积分电容Cf、第一无源低通滤波器103、第二无源低通滤波器104以及信号输出端OUT1。
信号输入端IN1和IN2用于在第K个采样周期采集内部信号。
在本公开实施例中，内部信号具体是由∑-Δ调制器的前段部分依据输入信号而产生，具体地，该前段部分例如可以实现对输入信号进行一阶噪声整形，进而产生该内部信号，对此将在后续进行详细说明。
积分器101的负相输入端口和正相输入端口例如分别耦合到信号输入端IN1和IN2，积分器101的正相输出端口和负相输出端口例如分别耦合到比较器102的负相输入端口。积分器101用于在第K个采样周期依据内部信号、第K-1个周期的量化误差信号、第K-1个周期经过过滤的量化误差信号、第K-2个周期经过过滤的量化误差信号而产生第K个周期的量化误差信号，其中K为大于1的正整数。
两个积分电容Cf分别耦合于积分器101，积分电容Cf用于保存第K个周期的量化误差信号，并在第K+1个采样周期用以加权内部信号。
第一无源低通滤波器103的输入端口和输出端口例如分别耦合到积分器101的正相输入端口和正相输出端口，第二无源低通滤波器104输入端口和输出端口例如分别耦合到积分器101的负相输入端口和负相输出端口。第一无源低通滤波器103和第二无源低通滤波器104均用于在第K个放电周期采集第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+1个采样周期以及第K+2个采样周期向积分器反馈经过过滤的量化误差信号。
比较器102与信号输出端OUT1连接，比较器102用于在第K个放电周期对第K个周期的量化误差信号进行量化，并输出数字码以及为放 电周期提供放电时间。比较器102输出的数字码通过信号输出端OUT1对外输出。
在本公开实施例中，上述量化器的具体工作过程如下：
在第K个采样周期，内部信号通过信号输入端IN1和IN2输入量化器。与此同时，第一无源低通滤波器103和第二无源低通滤波器104分别将第K-1个周期经过过滤的量化误差信号和第K-2个周期经过过滤的量化误差信号反馈回量化器的输入端，并与内部信号叠加。上述三路信号通过积分器101与积分电容Cf上保存的第K-1个周期的量化误差信号进行叠加，以产生第K个周期的量化误差信号。其中，积分电容Cf保存该第K个周期的量化误差信号，并在第K+1个采样周期用以加权输入端IN1和IN2采集的内部信号以及第一无源低通滤波器103和第二无源低通滤波器104反馈回量化器输入端的经过过滤的量化误差信号。
在第K个放电周期，比较器102对第K个周期的量化误差信号进行量化，同时积分电容Cf开始放电。当比较器102检测到积分器101输出端口的电平大小关系发生反转时，积分电容Cf放电结束，同时量化结束，比较器102检测到反转之前所经历的比较周期为量化器的输出结果。此时，比较器102量化误差，并通过信号输出端OUT1输出数字码。在一些实施例中，可以在比较器102时钟的最后半个周期，向积分电容Cf反充电半个比较周期，这样可以使电容Cf上的量化误差信号减小为原来的一半，进而可以获取更好地噪声整形效果。
在上述第K个放电周期内，第一无源低通滤波器103和第二无源低通滤波器104分别采集保存于积分电容Cf上的第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+1个采样周期以及第K+2个采样周期向积分器101反馈经过过滤的量化误差信号。
图1B示出了根据本公开另一实施例的用于∑-Δ调制器的量化器的结构示意图。
如图1B所示，用于∑-Δ调制器的量化器具体包括：信号输入端IN1和IN2、积分器101、比较器102、两个积分电容Cf、第一无源低通滤波器103、第二无源低通滤波器104、第一反馈端口105以及信号输出 端OUT1。其中，信号输入端IN1和IN2、积分器101、比较器102、两个积分电容Cf、第一无源低通滤波器103、第二无源低通滤波器104和信号输出端OUT1与以上描述的内容具有相同或相似的功能，重复的部分将不再赘述。
在本公开实施例中，第一反馈端口105耦合于积分器101的正输入端口和负输入端口，第一反馈端口105用于在第K个采样周期接收前段部分反馈的第一反馈信号，并将该第一反馈信号反馈至积分器101，积分器101还依据该第一反馈信号积分内部信号。
积分器101在第K个采样周期依据内部信号、第一反馈信号、第K-1个周期的量化误差信号、第K-1个周期经过过滤的量化误差信号、第K-2个周期经过过滤的量化误差信号而产生第K个周期的量化误差信号，该过程与以上描述的过程类似，在此不再赘述。
在本公开的一些实施例中，第一无源低通滤波器和第二无源低通滤波器包括：第一电容、第二电容和第三电容。其中，第一电容用于在第K个放电周期采集第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+1个采样周期向积分器反馈经过过滤的量化误差信号。第二电容和第三电容分别用于采集奇数周期和偶数周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+2个采样周期向积分器反馈经过过滤的量化误差信号。
在本公开实施例中，第一无源低通滤波器103和第二无源低通滤波器104例如均包括第一电容、第二电容和第三电容(图1中未示出)。其中，第一电容用于在第K个放电周期采集第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+1个采样周期向积分器反馈经过过滤的量化误差信号。第二电容和第三电容分别用于采集奇数周期和偶数周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+2个采样周期向积分器反馈经过过滤的量化误差信号。采用上述反馈方式将量化误差信号反馈给量化器的输入端，即采用第一电容在下一个采样周期将经过过滤的量化误差信号直接反馈到量化器输入端与输入的内部信号叠加，采用第二电容或第三电容将量化误差信号经过 一个周期的延时后再反馈到量化器的输入端与输入的内部信号叠加，三条通路共同工作可以形成传输函数H(z)＝1-z -1的无源低通滤波器，进而使得整个量化器具有二阶噪声整形的能力。
下面将对本公开实施例中的量化器具有二阶噪声整形能力进行说明。
例如在第K个周期，假设量化器输出的数字信号为D(z)，∑-Δ调制器的输入信号为X(z)(∑-Δ调制器的前段部分依据该输入信号而产生内部信号)，第K个周期比较器102量化后引入的量化误差信号为eq(z)。其中，量化器输出的数字信号D(z)与输入信号X(z)满足如下关系：
D(z)＝X(z)-(1-z -1)z -1eq(z)-z -1eq(z)+eq(z)       (1)
上述公式(1)中，D(z)为第K个周期量化器输出的数字信号，X(z)为第K个周期∑-Δ调制器的输入信号，(1-z -1)z -1eq(z)为无源低通滤波器反馈的第K-1个周期的经过过滤的量化误差信号以及第K-2个周期的经过过滤的量化误差信号之和，z -1eq(z)为积分电容上保存的第K-1个周期的量化误差信号，eq(z)为第K个周期比较器102量化后引入的量化误差信号。
由公式(1)进而可得：
D(z)＝X(z)+(1-z -1) 2eq(z)     (2)
通过公式(2)可知，本公开实施例中的量化器通过采用无源低通滤波器结构将量化误差信号反馈回量化器的输入端，从而实现二阶噪声整形。由于无源低通滤波器由无源元件组成，其采样信号为量化器放电周期的输出信号(即量化误差信号)，故其并不会额外消耗能量，因此，本公开中的量化器在增强***噪声整形能力的同时并不会引起***功耗的显著增加。由于无源低通滤波器几乎没有能量消耗，在要求调制器的量化有效位数相同的情况下会更节能，从而可以有效解决传统二阶噪声整形积分量化器中功耗较大的问题。
本公开的实施例提供了一种∑-Δ调制器，该∑-Δ调制器包括量化器以及前段部分。其中，前段部分包括前段输入端口及前段输出端口，分 别用于接收输入信号和输出内部信号，且前段部分用于依据输入信号而产生内部信号。∑-Δ调制器中的量化器与以上描述的量化器的结构和工作过程相同或类似，重复的部分将不再详细赘述。
在本公开的实施例中，量化器包括积分器、积分电容、无源低通滤波器和比较器。
积分器用于在第K个采样周期依据内部信号、第K-1个周期的量化信号、第K-1个周期经过过滤的量化信号、第K-2个周期经过过滤的量化信号而产生第K个周期的量化信号，其中K为大于1的正整数。
积分电容用于保存第K个周期的量化信号，并在第K+1个采样周期用以加权内部信号。
无源低通滤波器用于在第K个放电周期采集第K个周期的量化信号，并据以产生经过过滤的量化信号，并在第K+1个采样周期以及第K+2个采样周期向积分器反馈经过过滤的量化信号。
比较器用于在第K个放电周期对第K个周期的量化信号进行量化，以输出数字码。
在一些实施例中，无源低通滤波器包括第一无源低通滤波器和第二无源低通滤波器。其中，第一无源低通滤波器耦合于积分器的正相输入端口和正相输出端口，第二无源低通滤波器耦合于积分器的负相输入端口和负相输出端口。第一无源低通滤波器和第二无源低通滤波器包括：第一电容、第二电容和第三电容。其中第一电容用于在第K个放电周期采集第K个周期的量化信号，并据以产生经过过滤的量化信号，并在第K+1个采样周期向积分器反馈经过过滤的量化信号。第二电容和第三电容分别用于采集奇数周期和偶数周期的量化信号，并据以产生经过过滤的量化信号，并在第K+2个采样周期向积分器反馈经过过滤的量化信号。通过采用无源低通滤波器结构将放电周期采集的量化误差信号反馈回量化器的输入端，可以形成传输函数H(z)＝1-z -1的无源低通滤波器，进而使得整个量化器具有二阶噪声整形的能力。
本公开的实施例中的量化器采用无源低通滤波器结构将放电周期采集的量化误差信号反馈回量化器的输入端，可以实现二阶噪声整形。 由于无源低通滤波器由无源元件组成，其采样信号为量化器放电周期的输出信号(即量化误差信号)，故其并不会额外消耗能量，因此，本公开中的量化器在增强***噪声整形能力的同时并不会引起***功耗的显著增加。由于无源低通滤波器几乎没有能量消耗，在要求∑-Δ调制器的量化有效位数相同的情况下会更节能，从而可以有效降低量化器的功耗，进而降低∑-Δ调制器的功耗。
图2示出了根据本公开实施例的∑-Δ调制器的结构示意图。
如图2所示，∑-Δ调制器包括前段部分21、量化器22和信号输出端口OUT。量化器22包括积分器、积分电容、无源低通滤波器和比较器。其中，积分器、积分电容、无源低通滤波器和比较器与以上描述的结构和工作过程相同或类似，在此将不再赘述。
前段部分21包括信号输入端口IN、第一模拟积分器211、第二模拟积分器212和第二数模转换器213。
输入端口IN用于接收输入信号。
第二数模转换器213耦接于量化器22的输出端口与第一模拟积分器211的第二反馈端口、第二模拟积分器212的第三反馈端口之间，用于转换量化器22输出的数字码，并据以提供第二反馈信号。
第一模拟积分器211耦接于信号输入端口IN和第二模拟积分器212的输入端口之间，用于接收输入信号和第二反馈信号，并据以产生第一积分信号。
第二模拟积分器212的输入端口还耦合到信号输入端口lN，第二模拟积分器212用于接收输入信号、第二反馈信号和第一积分信号，并据以产生内部信号。
在本公开的一些实施例中，第一模拟积分器211包括四个电容，其中，第四电容和第五电容用于采集输入信号和第二反馈信号，并保存输入信号和第二反馈信号的差值。第六电容和第七电容则用于接收输入信号和第二反馈信号的差值，并据以产生第一积分信号。采用上述四个电容可以实现对输入信号和第二数模转换器反馈的信号进行一阶噪声整形。
在本公开的一些实施例中，第二模拟积分器212包括六个电容，其中，第八电容和第九电容用于采集第一积分信号，并保存第一积分信号；第十电容和第十一电容用于采集输入信号和第二反馈信号，并保存输入信号和第二反馈信号的差值；第十二电容和第十三电容用于接收第一积分信号以及输入信号和第二反馈信号的差值，并据以产生内部信号。采用上述六个电容可以实现对输入信号、第一模拟积分器输出的积分信号和第二数模转换器反馈的信号进行一阶噪声整形。
在本公开实施例中，量化器22接收内部信号后，进行量化噪声整形的过程与以上描述的过程相同，在此不再赘述。
图3示出了根据本公开另一实施例的∑-Δ调制器的结构示意图。
如图3所示，∑-Δ调制器包括前段部分31、量化器32、数字积分器33和信号输出端口OUT。量化器32包括积分器、积分电容、无源低通滤波器、比较器和第一反馈端口。其中，积分器、积分电容、无源低通滤波器、比较器和第一反馈端口与以上描述的结构和工作过程相同或类似，在此将不再赘述。
前段部分31包括信号输入端口IN、第一模拟积分器311、第二模拟积分器312、第一数模转换器314和第二数模转换器313。
输入端口lN用于接收输入信号。
第一数模转换器314耦接于量化器32的输出端口和第二模拟积分器312的第四反馈端口之间，用于转换量化器32输出的数字码，并据以提供第一反馈信号。
第二数模转换器313耦接于数字积分器33的输出端口与第一模拟积分器311的第二反馈端口、第二模拟积分器312的第三反馈端口之间，用于转换数字积分器33输出的数字码，并据以提供第二反馈信号。
第一模拟积分器311耦接于信号输入端口lN和第二模拟积分器312的输入端口之间，用于接收输入信号和第二反馈信号，并据以产生第一积分信号。
在本公开的一些实施例中，第一模拟积分器311包括四个电容，其中，第四电容和第五电容用于采集输入信号和第二反馈信号，并保存输 入信号和第二反馈信号的差值。第六电容和第七电容则用于接收输入信号和第二反馈信号的差值，并据以产生第一积分信号。
第二模拟积分器312的输入端口还耦合到信号输入端口lN。第二模拟积分器312用于接收输入信号、第一积分信号、第二反馈信号和第一反馈信号，并据以产生内部信号。
在本公开的一些实施例中，第二模拟积分器312包括六个电容，其中，第八电容和第九电容用于采集第一积分信号和第一反馈信号，并保存第一积分信号和第一反馈信号的差值；第十电容和第十一电容用于采集输入信号和第二反馈信号，并保存输入信号和第二反馈信号的差值；第十二电容和第十三电容，用于接收第一积分信号和第一反馈信号的差值以及输入信号和第二反馈信号的差值，并据以产生内部信号。
在本公开实施例中，量化器32接收内部信号和第一反馈信号后，进行量化噪声整形的过程与以上描述的过程相同，在此不再赘述。
在本公开实施例中，数字积分器33耦合于量化器32的输出端口，用于积分量化器32输出的数字码，以提供积分后的数字码。
数字积分器本质上相当于一个加法器，可以将接受到的数字码例如3bit数字码累加得到例如5bit数字码，然后传输至信号输出端口OUT作为***输出。
本公开实施例的∑-Δ调制器在加入数字积分器33以及第一数模转换器314反馈通路后，量化器32的输入信号变为本周期第二模拟积分器312输出信号与上一周期第二模拟积分器312输出信号的差。由于∑-Δ调制器结构特性，采样频率远高于输入信号带宽，积分通路信号差值的最大值会远小于积分通路输出信号的最大值，所以加入数字积分器33以及第一数模转换器314反馈通路后会提升∑-Δ调制器的稳定性。
下面将对本公开实施例中的量化器改变∑-Δ调制器的环路传输函数的原理进行简单说明。
例如在第K(K为大于1的正整数)个周期，假设∑-Δ调制器的环路传输函数为H’(z)，∑-Δ调制器的输入信号为X(z)，由于量化器作用加入到∑-Δ调制器中的经过滤波的量化误差信号为Q(z)。在本公开实施例 中，由于积分通路采用二级积分负反馈结构，∑-Δ调制器的环路传输函数满足如下关系：
H′(z)＝STF·X(z)+(1-z -1) 2Q(z)        (3)
其中，STF为信号传输函数，在本实施例中约为1。
由于第K-1个周期的量化误差信号会在积分电容上保存，并且还会经过无源低通滤波器滤波后反馈回量化器输入端。将第K-1个周期的量化误差、第K-2个周期的量化误差与第K个周期的量化误差叠加可得：
Q(z)＝(1-2z -1+z -2)eq(z)        (4)
上述公式(4)中，eq(z)为比较器量化引入的第K个周期的量化误差。
将Q(z)有量化噪声表示可得：
H′(z)＝STF·X(z)+(1-z -1) 4eq(z)       (5)
由公式(5)可知，本公开实施例的∑-Δ调制器完成了对量化噪声的四阶噪声整形。另外，∑-Δ调制器中的量化器采用了无源低通滤波器结构将放电周期采集的量化误差信号反馈回量化器的输入端，由于无源低通滤波器由无源元件组成，其采样信号为量化器放电周期的输出信号(即量化误差信号)，故其并不会额外消耗能量，因此，本公开中的量化器在增强***噪声整形能力的同时并不会引起***功耗的显著增加。由于无源低通滤波器几乎没有能量消耗，在要求∑-Δ调制器的量化有效位数相同的情况下会更节能，从而可以有效降低量化器的功耗，进而降低了∑-Δ调制器的功耗。也就是说，本公开实施例中的∑-Δ调制器可以在低功耗的情况下实现四阶噪声整形。
图4和图5分别示出了根据本公开实施例的第一模拟积分器和第二模拟积分器的电路结构示意图，图6示出了根据本公开实施例的用于∑-Δ调制器的量化器的电路结构示意图，图7示出了图6中的量化器电路在采样周期与放电周期的工作时序图，图8示出了图6中的无源低通滤波器的工作时序图。下面将以图3中的∑-Δ调制器结构为例，结合图4至图8对图3中的第一模拟积分器、第二模拟积分器和量化器的具体工作 过程进行详细说明。
应当理解，图4至图8中示出的内容仅是为了便于本领域技术人员理解本公开的技术方案，并非用以限定本公开的保护范围。
如图4所示，第一模拟积分器311(图3中示出)包括信号输入端口IN3和IN4、信号输出端口OUT2和OUT3、电容C1(即第四电容)、C2(即第五电容)、C3(即第六电容)和C4(即第七电容)、第二反馈端口401、全差分运算放大器402以及开关1～12等。
第一模拟积分器311的工作模式包括复位阶段、采样阶段和运算阶段。
在电路启动后第一模拟积分器311首先进入复位阶段。此时闭合第9、10、11、12开关，其他开关断开。电容C3和C4复位至电容上电荷为0，这样处理的目的是为了防止上一次信号处理时残余的电荷对此次信号处理的过程产生影响。通常来说，复位阶段只在信号处理时作用一次，之后第一模拟积分器311会在采样阶段和运算阶段两者中不断循环。
第一模拟积分器311电路复位之后，进入采样阶段。此时闭合开关1、3、4、6，其他开关断开。当前输入信号从信号输入端口IN3和IN4输入，第二数模转换器313反馈的第二反馈信号从第二反馈端口401输入。当前输入信号与第二反馈信号的电压差将保存在电容C1和C2上(相当于完成作差运算)。
在运算阶段，闭合开关2、5、7、8，其他开关断开。通过全差分运算放大器402将保存在电容C1和C2上的电荷将依据电荷守恒定律转移到电容C3和C4上，实现一阶噪声整形。之后从信号输出端口OUT2和OUT3输出第一积分信号。
为了便于说明和理解，下面将以电容C1和电容C2的电容值相等、电容C3和电容C4的电容值相等为例来对第一模拟积分器实现一阶噪声整形的原理进行说明。
在第N个周期的采样阶段，当前输入信号经采样保存在电容C1和C2上，总电荷记为C 1，2V in(N)。在第N个周期的运算阶段，电容C3和C4上保存有第N-1个周期运算阶段转移的电压信号，总电荷记为 C 3，4V out(N-1)，电容C1和C2上的电荷经过延迟变为C 1，2V in(N-1)。在第N个周期的运算阶段，根据电荷守恒定律，储存在电容上的电荷发生转移并重新分配，该电荷转移方程可表示为：
C 3，4V out(N)＝C 1，2V in(N-1)+C 3，4V out(N-1)      (6)
对其做z变换，可得：
C 3，4V out(z)＝C 1，2V in(z)z -1+C 3，4V out(z)z -1     (7)
做简单的变换后，可得到第一模拟积分器的转移函数：
Figure PCTCN2021098441-appb-000001
在本实施例中，电容C1和C3的比值例如可以设定为0.2～0.5，例如，将电容C1和C3的比值设定为0.2，便可以实现将输入信号缩小为原来的0.2倍，同时完成对输入信号进行一阶噪声整形。应当理解，上述示出的数值仅是为了便于本领域技术人员理解本公开的技术方案，并非用以限定本公开的保护范围。在其他一些实施例中，可以根据实际需要，设定电容C1和C3的比值，以实现对不同输入信号进行不同程度的缩小或放大，并完成一阶噪声整形，在此不做限制。
如图5所示，第二模拟积分器312(图3中示出)包括信号输入端口IN3’和IN4’、信号输出端口OUT4和OUT5、电容C1’(即第八电容)、C2’(即第九电容)、C3’(即第十二电容)、C4’(即第十三电容)、C5(即第十电容)和C6(即第十一电容)、第三反馈端口501、第四反馈端口502、全差分运算放大器503以及开关1’～16等。
第二模拟积分器312与第一模拟积分器311的工作模式和作用原理相似，在此作简要描述。
第二模拟积分器312的工作模式包括复位阶段、采样阶段和运算阶段。
在电路启动后第二模拟积分器312首先进入复位阶段。此时闭合第9’、10’、11’、12’开关，其他开关断开。电容C3’和C4’复位至电容上电荷为0，这样处理的目的是为了防止上一次信号处理时残余的电荷对此 次信号处理的过程产生影响。通常来说，复位阶段只在信号处理时作用一次，之后第二模拟积分器312会在采样阶段和运算阶段两者中不断循环。
第二模拟积分器312电路复位之后，进入采样阶段。此时闭合开关1’、3’、4’、6’、13、15，其他开关断开。第一模拟积分器311输出的第一积分信号从信号输入端口IN3’和IN4’输入，第一数模转换器314反馈的第一反馈信号从第三反馈端口501输入。当前输入信号从信号输入端口IN5和IN6输入，第二数模转换器313反馈的第二反馈信号从第四反馈端口502输入。此时，电容C1’和C2’将保存第一积分信号与第一反馈信号的电压差，电容C5和C6将存储当前输入信号与第二反馈信号的电压差。
在运算阶段，闭合开关2、5、7、8、14、16，其他开关断开。通过全差分运算放大器503将保存于电容C1’、C2’、C5和C6上的电荷将依据电荷守恒定律转移到电容C3’和C4’，实现一阶噪声整形，之后将内部信号从输出端口OUT4和OUT5输出至量化器32。
第二模拟积分器与第一模拟积分器的作用原理类似，为了便于说明和理解，下面将以电容C1’和电容C2’的电容值相等、电容C3’和C4’的电容值相等、电容C5和C6的电容值相等为例来对第二模拟积分器实现一阶噪声整形的原理进行说明。
在第N个周期的采样阶段，第一积分信号与第一反馈信号的差值保存在电容C1’和C2’上，总电荷记为C 1’，2’V out1(N)，当前输入信号与第二反馈信号的差值保存在电容C5和C6上，总电荷记为C 5，6V in(N)。在第N个周期的运算阶段，电容C3’和C4’上保存有第N-1个周期运算阶段转移的电压信号，总电荷记为C 3’，4’V out(N-1)，电容C1’和C2’上的电荷经过延迟变为C 1’，2’V out1(N-1)，电容C5和C6上的电荷经过延迟变为C 5，6V in(N-1)。在第N个周期的运算阶段，根据电荷守恒定律，储存在电容上的电荷发生转移并重新分配，该电荷转移方程可表示为：
C 3′，4′V out(N)＝C 1′，2′V out1(N-1)+C 5，6V in(N-1)+C 3′，4′V out(N-1)      (9)
对其做z变换，可得：
C 3′，4′V out(z)＝C 1′，2′V out1(z)z -1+C 5，6V in(z)z -1+C 3′，4′V out(z)z -1       (10)
在本实施例中，电容C1’和C5的比值例如可以设定为0.4～0.6，例如将电容C1’和C5的比值设定为0.5，做简单的变换后，可得到第二模拟积分器的转移函数：
Figure PCTCN2021098441-appb-000002
在本实施例中，例如设定将电容C5和C3’的比值设定为0.5，便可以实现将输入信号缩小为原来的0.5倍，同时完成对输入信号进行一阶噪声整形。应当理解，上述示出的数值仅是为了便于本领域技术人员理解本公开的技术方案，并非用以限定本公开的保护范围。在其他一些实施例中，可以根据实际需要，设定电容C5和C1’的比值以及电容C5和C3’的比值，以实现对不同输入信号进行不同程度的缩小或放大，并完成一阶噪声整形，在此不做限制。
图6示出了本公开实施例的用于∑-Δ调制器的量化器的电路结构示意图。
如图6所示，量化器主要包括信号输入端IN1和IN2、积分器601、比较器602、两个积分电容Cf、第一无源低通滤波器603、第二无源低通滤波器604、第一反馈端口605。其中，第一无源低通滤波器603和第二无源低通滤波器604具有相同的结构和作用原理，在本实施例中，将以第一无源低通滤波器603为例来对无源低通滤波器的工作过程进行说明。
第一无源低通滤波器603包括电容C11、C7、C8以及对应的控制开关。例如，
Figure PCTCN2021098441-appb-000003
对应控制电容C7，
Figure PCTCN2021098441-appb-000004
对应控制电容C8(图6中虚线部分“×2”表示C7和C8分别有对应的控制电路)。电容C11相当于第一电容，用于在第K个放电周期采集第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+1个采样周期向积分器反馈经过过滤的量化误差信号；电容C7、C8分别相当于第二电容和第三电容，分别用于采集奇数周期和偶数周期的量化误差信号， 并据以产生经过过滤的量化误差信号，并在第K+2个采样周期向积分器反馈经过过滤的量化误差信号。
图7示出了图6中的量化器电路在采样周期与放电周期的工作时序图，图8示出了图6中的无源低通滤波器的工作时序图。下面将结合图7和图8对图6中的电路的工作过程进行详细说明。
量化器32的工作模式包括复位周期、采样周期和放电周期。其中，量化器的复位周期与第一模拟积分器311的复位阶段类似，其主要目的是为了清除电容上残余的电荷，以避免上一次信号处理时残余的电荷对此次信号处理的过程产生影响。通常，复位周期只在信号处理时作用一次，之后量化器32会在采样周期和放电周期(图7中示出的定时信号φs和φd分别表示采样周期和放电周期)两者中不断循环。
在第K个采样周期φs，内部信号会从信号输入端口IN1和IN2输入，与此同时，第一数模转换器314反馈的第一反馈信号会从第一反馈端口605输入。此外，传输函数为(1-z -1)的无源低通滤波器(包括第一无源低通滤波器603和第二无源低通滤波器604)还会将第K-1个周期经过过滤的量化误差信号(例如由电容C11和C12反馈的第K-1个周期经过过滤的量化误差信号)、第K-2个周期经过过滤的量化误差信号(例如由电容C7和C9反馈的第K-2个周期经过过滤的量化误差信号)反馈到量化器的输入端。上述信号在电容Cs上叠加后，经过积分器601进行积分处理，并与电容Cf上保存的第K-1个周期的量化误差信号进行叠加而产生第K个周期的量化误差信号，并将第K个周期的量化误差信号保存在电容Cf上。图7中示出的曲线710表示积分电容Cf的输出电压Vout(Vout＝Vop-Von)，如图7所示，在采样周期φs，积分电容Cf上会保存第K个周期的量化误差信号。
第K个放电周期φd，比较器602对第K个周期的量化误差信号进行量化。可以由比较器602决定放电方向，开启
Figure PCTCN2021098441-appb-000005
或
Figure PCTCN2021098441-appb-000006
置1(图6中示出)，此时积分电容Cf放电开始。
比较器602的工作周期如图7中方波720所示，比较器602在放电周期内进行多次比较，此阶段内，比较器602交替处于工作状态，对于 脉冲721[1]、722[2]、723[3]、724[n]中的每一次脉冲，都使得比较器602对输输入的信号进行量化，生成数字码。
如图7所示，在积分电容Cf放电的过程中(图7中示出的
Figure PCTCN2021098441-appb-000007
表示积分电容Cf的放电时间)，积分电容Cf的输出电压Vout的绝对值会逐渐减小(图7中示出的曲线710)。当比较器602检测到Vop与Von大小关系发生反转时，放电结束，
Figure PCTCN2021098441-appb-000008
置0。此时量化过程结束，比较器602反转之前所经历的比较周期数为量化器的输出结果，此时量化误差，输出数字码。在比较器602时钟最后半个比较周期(图7中示出的
Figure PCTCN2021098441-appb-000009
阶段)，对积分电容Cf反充电半个比较周期(图7中示出的711过程)，以使电容Cf上量化误差信号减小为原来的一半。
第一无源低通滤波器603的工作时序如图8所示。图8中的
Figure PCTCN2021098441-appb-000010
和
Figure PCTCN2021098441-appb-000011
分别表示图6中与电容C11对应的开关
Figure PCTCN2021098441-appb-000012
和
Figure PCTCN2021098441-appb-000013
的工作时序，
Figure PCTCN2021098441-appb-000014
和
Figure PCTCN2021098441-appb-000015
分别表示与电容C7对应的开关
Figure PCTCN2021098441-appb-000016
和
Figure PCTCN2021098441-appb-000017
的工作时序，
Figure PCTCN2021098441-appb-000018
和
Figure PCTCN2021098441-appb-000019
分别表示与电容C8对应的开关
Figure PCTCN2021098441-appb-000020
和
Figure PCTCN2021098441-appb-000021
的工作时序。
如图8所示，在第K个放电周期，控制
Figure PCTCN2021098441-appb-000022
和
Figure PCTCN2021098441-appb-000023
闭合(如图8中示出的脉冲信号810和830)，其他开关断开，此时电容C11和C7分别采集积分电容Cf上的第K个周期的量化误差信号并保持。
在第K+1个采样周期，控制
Figure PCTCN2021098441-appb-000024
和
Figure PCTCN2021098441-appb-000025
闭合(如图8中示出的脉冲信号820和860)，其他开关断开，电容C11上保存的第K个周期的量化误差信号反馈至量化器的输入端，电容C8上保存的第K-1个周期的量化误差信号反馈至量化器的输入端(即电容C8上保存的量化误差信号延时了一个周期再反馈给量化器的输入端)。
在第K+1个放电周期，控制
Figure PCTCN2021098441-appb-000026
和
Figure PCTCN2021098441-appb-000027
闭合(如图8中示出的脉冲信号811和850)，其他开关断开，此时电容C11和C8分别采集积分电容Cf上的第K+1个周期的量化误差信号并保持。
在第K+2个采样周期，控制
Figure PCTCN2021098441-appb-000028
和
Figure PCTCN2021098441-appb-000029
闭合(如图8中示出的脉冲信号821和840)，其他开关断开，电容C11上保存的第K+1个周期的量化误差信号反馈至量化器的输入端，电容C7上保存的第K个周期的量化误差信号反馈至量化器的输入端(即电容C7上保存的量化误差信 号延时了一个周期再反馈给量化器的输入端)。
在本公开实施例中，无源低通滤波器中的电容C11直接将采集到的量化误差信号在下一采样周期反馈到量化器的输入端，而电容C7和C8交替工作，将采集到的量化误差信号经过一个周期的延时后再反馈给量化器的输入端。通过上述方式，可以形成传输函数为(1-z -1)的无源低通滤波器。
本公开的实施例中的量化器采用上述无源低通滤波器结构将放电周期采集的量化误差信号反馈回量化器的输入端，可以实现二阶噪声整形。由于无源低通滤波器由无源元件组成，其采样信号为量化器放电周期的输出信号(即量化误差信号)，故其并不会额外消耗能量，因此，本公开中的量化器在增强***噪声整形能力的同时并不会引起***功耗的显著增加。由于无源低通滤波器几乎没有能量消耗，在要求∑-Δ调制器的量化有效位数相同的情况下会更节能，从而可以有效降低量化器的功耗，进而降低∑-Δ调制器的功耗。
图9示出了根据本公开实施例的噪声整形方法的流程图。
如图9所示，噪声整形方法包括操作S910～S930。
在操作S910，在第K个采样周期内，通过积分器采集内部信号、存储于积分电容上的第K-1个周期的量化误差信号、无源低通滤波器反馈的第K-1个周期经过过滤的量化误差信号和第K-2个周期经过过滤的量化误差信号，并据以产生第K个周期的量化误差信号。其中，第K个周期的量化误差信号保存于积分电容上，以在第K+1个采样周期加权内部信号，其中K为大于1的正整数。
在操作S920，在第K个放电周期内，通过无源低通滤波器采集第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，以在第K+1个采样周期以及第K+2个采样周期向积分器反馈经过过滤的量化误差信号。
在操作S930，通过比较器对第K个周期的量化误差信号进行量化，以输出数字码。
在本公开的一些实施例中，上述操作S920中，通过无源低通滤波 器采集第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，以在第K+1个采样周期以及第K+2个采样周期向积分器反馈经过过滤的量化误差信号还包括操作S921～S922。
在操作S921，利用第一电容采集第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+1个采样周期向积分器反馈经过过滤的量化误差信号。
在操作S922，利用第二电容和第三电容分别采集奇数周期和偶数周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+2个采样周期向积分器反馈经过过滤的量化误差信号。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。本公开的范围由所附权利要求及其等同物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (12)

  1. 一种用于∑-Δ调制器的量化器，其特征在于，包括：
    积分器，用于在第K个采样周期依据内部信号、第K-1个周期的量化误差信号、第K-1个周期经过过滤的量化误差信号、第K-2个周期经过过滤的量化误差信号而产生第K个周期的量化误差信号；其中K为大于1的正整数；
    积分电容，用于保存所述第K个周期的量化误差信号，并在第K+1个采样周期用以加权所述内部信号；
    无源低通滤波器，用于在第K个放电周期采集所述第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+1个采样周期以及第K+2个采样周期向所述积分器反馈所述经过过滤的量化误差信号；以及
    比较器，用于在第K个放电周期对所述第K个周期的量化误差信号进行量化，以输出数字码。
  2. 根据权利要求1所述的用于∑-Δ调制器的量化器，其特征在于，
    所述无源低通滤波器包括：第一无源低通滤波器和第二无源低通滤波器；其中，所述第一无源低通滤波器耦合于所述积分器的正相输入端口和正相输出端口；所述第二无源低通滤波器耦合于所述积分器的负相输入端口和负相输出端口；
    所述第一无源低通滤波器和所述第二无源低通滤波器包括：
    第一电容，用于在第K个放电周期采集所述第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+1个采样周期向所述积分器反馈所述经过过滤的量化误差信号；以及
    第二电容和第三电容，分别用于采集奇数周期和偶数周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+2个采样周期向所述积分器反馈经过过滤的量化误差信号。
  3. 一种∑-Δ调制器，其特征在于，包括：
    量化器，所述量化器为权利要求1或2中所述的量化器；
    前段部分，所述前段部分包括前段输入端口及前段输出端口，分别 用于接收输入信号和输出内部信号，且所述前段部分用于依据所述输入信号而产生所述内部信号。
  4. 根据权利要求3所述的∑-Δ调制器，其特征在于，
    所述前段部分包括第一模拟积分器、第二模拟积分器和第二数模转换器；
    第二数模转换器，耦接于所述量化器的输出端口与所述第一模拟积分器的第二反馈端口、所述第二模拟积分器的第三反馈端口之间，用于转换所述量化器输出的数字码，并据以提供第二反馈信号；
    第一模拟积分器，用于接收所述输入信号和所述第二反馈信号，并据以产生第一积分信号；
    第二模拟积分器，用于接收所述输入信号、所述第二反馈信号和所述第一积分信号，并据以产生所述内部信号。
  5. 根据权利要求3所述的∑-Δ调制器，其特征在于，
    所述前段部分还包括第一数模转换器，用于转换所述量化器输出的数字码，并据以提供第一反馈信号；
    所述量化器还包括第一反馈端口，耦合于所述积分器的正输入端口和负输入端口以及所述第一数模转换器的输出端口，用于接收所述第一反馈信号；
    所述积分器还依据所述第一反馈信号积分所述内部信号。
  6. 根据权利要求5所述的∑-Δ调制器，其特征在于，
    所述∑-Δ调制器还包括数字积分器，耦合于所述量化器的输出端口，用于积分所述量化器输出的数字码，以提供积分后的数字码。
  7. 根据权利要求6所述的∑-Δ调制器，其特征在于，
    所述前段部分包括第一模拟积分器、第二模拟积分器和第二数模转换器；
    第二数模转换器，耦接于所述数字积分器的输出端口与所述第一模拟积分器的第二反馈端口、所述第二模拟积分器的第三反馈端口之间，用于转换所述数字积分器输出的数字码，并据以提供第二反馈信号；
    第一模拟积分器，用于接收所述输入信号和所述第二反馈信号，并 据以产生第一积分信号；
    第二模拟积分器还包括第四反馈端口，耦合于所述第一数模转换器的输出端口，用于接收第一反馈信号；
    所述第二模拟积分器还依据所述输入信号、所述第一积分信号、所述第二反馈信号和第一反馈信号产生所述内部信号。
  8. 根据权利要求4或7所述的∑-Δ调制器，其特征在于，
    所述第一模拟积分器包括四个电容，其中：
    第四电容和第五电容，用于采集所述输入信号和所述第二反馈信号，并保存所述输入信号和所述第二反馈信号的差值；
    第六电容和第七电容，用于接收所述输入信号和所述第二反馈信号的差值，并据以产生第一积分信号。
  9. 根据权利要求4所述的∑-Δ调制器，其特征在于，
    所述第二模拟积分器包括六个电容，其中：
    第八电容和第九电容，用于采集所述第一积分信号，并保存所述第一积分信号；
    第十电容和第十一电容，用于采集所述输入信号和所述第二反馈信号，并保存所述输入信号和所述第二反馈信号的差值；
    第十二电容和第十三电容，用于接收所述第一积分信号以及所述输入信号和所述第二反馈信号的差值，并据以产生所述内部信号。
  10. 根据权利要求7所述的∑-Δ调制器，其特征在于，
    所述第二模拟积分器包括六个电容，其中：
    第八电容和第九电容，用于采集所述第一积分信号和所述第一反馈信号，并保存所述第一积分信号和所述第一反馈信号的差值；
    第十电容和第十一电容，用于采集所述输入信号和所述第二反馈信号，并保存所述输入信号和所述第二反馈信号的差值；
    第十二电容和第十三电容，用于接收所述第一积分信号和所述第一反馈信号的差值以及所述输入信号和所述第二反馈信号的差值，并据以产生所述内部信号。
  11. 一种噪声整形方法，其特征在于，包括：
    在第K个采样周期内，通过积分器采集内部信号、存储于积分电容上的第K-1个周期的量化误差信号、无源低通滤波器反馈的第K-1个周期经过过滤的量化误差信号和第K-2个周期经过过滤的量化误差信号，并据以产生第K个周期的量化误差信号；其中，所述第K个周期的量化误差信号保存于积分电容上，以在第K+1个采样周期加权所述内部信号；其中K为大于1的正整数；
    在第K个放电周期内，通过所述无源低通滤波器采集所述第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，以在第K+1个采样周期以及第K+2个采样周期向所述积分器反馈所述经过过滤的量化误差信号；以及
    通过比较器对所述第K个周期的量化误差信号进行量化，以输出数字码。
  12. 根据权利要求11所述的噪声整形方法，其特征在于，
    所述通过所述无源低通滤波器采集所述第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，以在第K+1个采样周期以及第K+2个采样周期向所述积分器反馈所述经过过滤的量化误差信号，包括：
    利用第一电容采集所述第K个周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+1个采样周期向所述积分器反馈所述经过过滤的量化误差信号；以及
    利用第二电容和第三电容分别采集奇数周期和偶数周期的量化误差信号，并据以产生经过过滤的量化误差信号，并在第K+2个采样周期向所述积分器反馈所述经过过滤的量化误差信号。
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