WO2022252092A1 - 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路和显示装置 Download PDF

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WO2022252092A1
WO2022252092A1 PCT/CN2021/097512 CN2021097512W WO2022252092A1 WO 2022252092 A1 WO2022252092 A1 WO 2022252092A1 CN 2021097512 W CN2021097512 W CN 2021097512W WO 2022252092 A1 WO2022252092 A1 WO 2022252092A1
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Prior art keywords
node
control
circuit
level
transistor
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PCT/CN2021/097512
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English (en)
French (fr)
Inventor
商广良
刘利宾
卢江楠
冯宇
殷新社
史世明
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京东方科技集团股份有限公司
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Priority to US17/781,133 priority Critical patent/US20240185937A1/en
Priority to CN202180001368.8A priority patent/CN115715411A/zh
Priority to PCT/CN2021/097512 priority patent/WO2022252092A1/zh
Priority to PCT/CN2022/077692 priority patent/WO2022252710A1/zh
Priority to CN202280000279.6A priority patent/CN115699155A/zh
Priority to US18/019,987 priority patent/US20230282170A1/en
Publication of WO2022252092A1 publication Critical patent/WO2022252092A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • Embodiments of the present disclosure relate to a shift register unit, a driving method thereof, a gate driving circuit, and a display device.
  • a pixel array of a liquid crystal display panel or an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel usually includes multiple rows of gate scanning signal lines and multiple columns of data lines interleaved with the gate scanning signal lines.
  • the driving of the gate scanning signal line can be realized by a bound integrated driving circuit.
  • the gate scanning signal line driver circuit can also be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to control the gate. Pole scanning signal line for driving.
  • a GOA including a plurality of cascaded shift register units may be used to provide switch state voltage signals (scanning signals) for multiple rows of gate scanning signal lines of the pixel array, so as to control multiple rows of gate scanning signal lines to sequentially conduct
  • the data lines provide data signals to the pixel units in the corresponding row in the pixel array, so as to form gray voltages required for each gray scale of the displayed image in each pixel unit, and then display a frame of image.
  • At least one embodiment of the present disclosure provides a shift register unit, including: an input circuit, a first control circuit, an output circuit, an output noise reduction circuit, and a reset circuit; the input circuit is connected to the input terminal and configured to respond to the The input signal input from the input terminal controls the level of the first node; the first control circuit is connected to the first node, the second node and the first clock signal terminal, and is configured to be at the first node Under the control of the level of the first clock signal and the first clock signal provided by the first clock signal terminal, the level of the second node is controlled; the output circuit is connected to the output terminal, and is configured to be at the second node Under the control of the level of the first node, an output signal is output at the output terminal; the output noise reduction circuit is connected to the output terminal, and is configured to, under the control of the level of the first node, output the output signal to the output terminal Noise reduction: the reset circuit is connected to the total reset terminal and the first voltage terminal, and is configured to respond to the total reset signal provided by the total
  • the shift register unit provided in at least one embodiment of the present disclosure further includes a second control circuit, the second control circuit is connected to the first node, the third node and the second clock signal terminal, and is configured to Under the control of the level of the first node and the second clock signal provided by the second clock signal terminal, the level of the third node is controlled; the output noise reduction circuit is also connected with the third node connected, and configured to output an inactive level of the output signal at the output terminal in response to the level of the third node.
  • the reset circuit is further connected to the third node, and is configured to respond to the total reset signal provided by the total reset terminal, The three nodes are reset so that the output noise reduction circuit is turned off.
  • the second control circuit includes a first subcircuit; the first subcircuit is connected to the first node, the second clock signal terminal and The third node is connected and configured to control the level of the third node under the control of the level of the first node.
  • the second control circuit further includes a second subcircuit; the second subcircuit is connected to the second voltage terminal, the first node and the first The control node is connected and configured to control the level of the first control node in response to the second voltage provided by the second voltage terminal; the first sub-circuit is also connected to the first control node and configured to The level of the third node is controlled in response to the level of the first control node.
  • the shift register unit provided in at least one embodiment of the present disclosure further includes a third control circuit, the third control circuit is connected to the second node, the fourth node and the second clock signal terminal, and configured The level of the fourth node is controlled under the control of the level of the second node and the second clock signal provided by the second clock signal terminal.
  • the third control circuit includes a third subcircuit and a fourth subcircuit; Two control nodes are connected, and configured to control the level of the second control node under the control of the level of the second node; the fourth sub-circuit is connected to the second clock signal terminal, the first The second control node is connected to the fourth node and configured to control the level of the fourth node in response to the second clock signal provided by the second clock signal terminal.
  • the third control circuit further includes a fifth subcircuit, and the fifth subcircuit is connected to the second voltage terminal, the second node, and the third The control node is connected and configured to control the level of the third control node in response to the second voltage provided by the second voltage terminal; the third sub-circuit is also connected to the third control node and configured to The level of the second control node is controlled in response to the level of the third control node.
  • the second control circuit further includes a sixth subcircuit, and the sixth subcircuit is connected to the second control node, the first voltage terminal and the The first sub-circuit is connected, and is configured to control the level of the first control node to be stable in response to the level of the second control node.
  • the shift register unit provided in at least one embodiment of the present disclosure further includes a fourth control circuit, the fourth control circuit is connected to the first node, the first voltage terminal and the fourth node, and configured The level of the fourth node is controlled in response to the level of the first node.
  • the shift register unit provided in at least one embodiment of the present disclosure further includes a fifth control circuit, the fifth control circuit is connected to the second control node, the third node and the first voltage terminal, and It is configured to control the level of the third node in response to the level of the second control node.
  • the shift register unit provided in at least one embodiment of the present disclosure further includes a sixth control circuit, the sixth control circuit is connected to the total reset terminal, the first voltage terminal and the first node, and configured To reset the first node under the control of the reset signal provided by the general reset terminal.
  • the input circuit includes an input transistor, the gate of the input transistor is connected to the first clock signal terminal to receive the first clock signal, A first pole of the input transistor is connected to the input terminal to receive the input signal, and a second pole of the input transistor is connected to the first node.
  • the reset circuit includes a reset transistor, the gate of the reset transistor is connected to the general reset terminal to receive the general reset signal, and the reset The first pole of the transistor is connected to the first voltage terminal to receive the first voltage, and the second pole of the reset transistor is connected to the third node.
  • the output noise reduction circuit includes an output noise reduction transistor, the gate of the output noise reduction transistor is connected to the third node, and the output noise reduction transistor The first pole of the noise transistor is connected to the second voltage terminal to receive the second voltage, and the second pole of the output noise reduction transistor is connected to the output terminal.
  • the output noise reduction circuit further includes an output noise reduction capacitor, the first pole of the output noise reduction capacitor is connected to the second voltage terminal to receive For the second voltage, the second pole of the output noise reduction capacitor is connected to the third node.
  • the output circuit includes an output transistor and an output capacitor; the gate of the output transistor is connected to the fourth node, and the first The pole is connected to the output terminal, the second pole of the output transistor is connected to the first voltage terminal to receive the first voltage; the first pole of the output capacitor is connected to the fourth node, and the output capacitor The second pole of the first voltage terminal is connected to receive the first voltage.
  • the first subcircuit includes a first control transistor, a second control transistor, and a first control capacitor; the gate of the first control transistor and the The first control node is connected, the first pole of the first control transistor is connected to the second clock signal terminal to receive the second clock signal, the second pole of the first control transistor is connected to the first The first pole of the control capacitor is connected; the second pole of the first control capacitor is connected to the first control node; the gate and the first pole of the second control transistor are connected to each other, and both are connected to the first The control node is connected, and the second electrode of the second control transistor is connected to the third node.
  • the second subcircuit includes a third control transistor, the gate of the third control transistor is connected to the second voltage terminal, and the first The first poles of the three control transistors are connected to the first node, and the second poles of the third control transistor are connected to the first control node.
  • the sixth subcircuit includes a fourth control transistor; the gate of the fourth control transistor is connected to the second control node, and the first The first poles of the four control transistors are connected to the first voltage terminal to receive the first voltage, and the second poles of the fourth control transistor are connected to the first pole of the first control capacitor.
  • the sixth control circuit includes a fifth control transistor; the gate of the fifth control transistor is connected to the total reset terminal to receive the total reset signal, the first pole of the fifth control transistor is connected to the first voltage terminal to receive the first voltage, and the second pole of the fifth control transistor is connected to the first node.
  • the first control circuit includes a sixth control transistor and a seventh control transistor; the gate of the sixth control transistor is connected to the first node , the first pole of the sixth control transistor is connected to the first clock signal terminal to receive the first clock signal, and the second pole of the sixth control transistor is connected to the second node; the first The gate of the seventh control transistor is connected to the first clock signal terminal to receive the first clock signal, the first electrode of the seventh control transistor is connected to the second voltage terminal to receive the second voltage, and the seventh control transistor is connected to the second voltage terminal to receive the second voltage.
  • the second pole of the control transistor is connected to the second node.
  • the third subcircuit includes an eighth control transistor and a third control capacitor
  • the fourth subcircuit includes a ninth control transistor
  • the fifth The sub-circuit includes a tenth control transistor; the gate of the tenth control transistor is connected to the second voltage terminal to receive the second voltage, and the first pole of the tenth control transistor is connected to the second node , the second pole of the tenth control transistor is connected to the third control node; the first pole of the third control capacitor is connected to the third control node, and the second pole of the third control capacitor is connected to The second control node is connected; the gate of the eighth control transistor is connected to the third control node, and the first pole of the eighth control transistor is connected to the second clock signal terminal to receive the first Two clock signals, the second pole of the eighth control transistor is connected to the second control node; the gate of the ninth control transistor is connected to the second clock signal terminal to receive the second clock signal, The first pole of the ninth control transistor is connected to the
  • the fourth control circuit includes an eleventh control transistor, the gate of the eleventh control transistor is connected to the first node, and the A first electrode of the eleventh control transistor is connected to the fourth node, and a second electrode of the eleventh control transistor is connected to the first voltage terminal to receive the first voltage.
  • the fifth control circuit includes a twelfth control transistor, and the gate of the twelfth control transistor is connected to the second control node, so The first electrode of the twelfth control transistor is connected to the third node, and the second electrode of the twelfth control transistor is connected to the first voltage terminal to receive the first voltage.
  • At least one embodiment of the present disclosure further provides a gate driving circuit, including a plurality of cascaded shift register units provided by any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure also provides a driving method for a shift register unit, including a first operation stage and a second operation stage; in the first operation stage, the driving method includes a first sub-stage, a second sub-stage Phase and third sub-phase: in the first sub-phase, the input circuit controls the level of the first node in response to the active level of the input signal input at the input terminal; the first control circuit Under the control of the level of the first node and the first clock signal provided by the first clock signal terminal, the level of the second node is controlled; in the second sub-phase, the output circuit Under the control of the level of the second node, the output signal is output at the output terminal; in the third sub-stage, the output noise reduction circuit is controlled by the level of the first node, Noise reduction at the output terminal; in the second operation phase, the driving method includes at least one reset phase, and in the at least one reset phase, the effective level of the total reset signal is applied to the total reset terminal, and the active level of the total reset signal is applied to all An in
  • the shift register unit further includes a second control circuit, wherein the second control circuit is connected to the first node and the third node connected to the second clock signal terminal, and configured to control the level of the third node under the control of the level of the first node and the second clock signal provided by the second clock signal terminal;
  • the output noise reduction circuit is also connected to the third node, and is configured to output the invalid level of the output signal at the output terminal in response to the level of the third node;
  • the reset phase also includes: applying an inactive level of the second clock signal to the second clock signal terminal, and the reset circuit resets the third node in response to the active level of the overall reset signal, so that the output The noise reduction circuit is turned off in response to the level of the third node.
  • At least one embodiment of the present disclosure further provides a display device including the gate driving circuit provided by any embodiment of the present disclosure.
  • FIG. 1 is a schematic block diagram of a shift register unit provided by at least one embodiment of the present disclosure
  • Fig. 2 is a schematic block diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • Fig. 3 is a schematic block diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • Fig. 4 is a schematic block diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • Fig. 5 is a schematic block diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • Fig. 6 is a schematic block diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • Fig. 7 is a schematic block diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • Fig. 8 is a schematic block diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 9 is a circuit diagram of a specific implementation of the shift register unit shown in FIG. 7 in some examples.
  • FIG. 10 is a circuit diagram of a specific implementation of the shift register unit shown in FIG. 7 in other examples.
  • FIG. 11 is a circuit diagram of a specific implementation of the shift register unit shown in FIG. 8 in some examples.
  • FIG. 12 is a circuit diagram of a specific implementation of the shift register unit shown in FIG. 2 in some examples;
  • FIG. 13 is a circuit diagram of a specific implementation of the shift register unit shown in FIG. 5 when the second subcircuit and the sixth subcircuit are not included;
  • FIG. 14 is a circuit diagram of a specific implementation of the shift register unit shown in FIG. 7 in some other examples.
  • FIG. 15A shows a signal timing diagram when the shift register unit 10 shown in FIG. 14 works
  • FIG. 15B shows a signal timing diagram when the shift register unit 10 shown in FIG. 11 works
  • FIG. 16 is a schematic diagram of a gate driving circuit provided by at least one embodiment of the present disclosure.
  • Fig. 17 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • Oxide semiconductors have the characteristics of ultra-low leakage to meet this demand.
  • the gate drive circuit drives multiple rows of sub-pixel units in a display panel
  • the blanking phase it is necessary to turn on the reset transistors of each shift register unit in the gate drive circuit to reset and reduce noise at the output terminal, so as to output the invalid level of the gate scanning signal in the blanking phase.
  • the reset transistor is continuously turned on for a long time, it will affect the ability of output reset and noise reduction, thereby affecting the service life of the gate drive circuit.
  • At least one embodiment of the present disclosure provides a shift register unit, including: an input circuit, a first control circuit, an output circuit, an output noise reduction circuit, and a reset circuit; the input circuit is connected to the input terminal and is configured to respond to input The input signal of the first node controls the level of the first node; the first control circuit is connected with the first node, the second node and the first clock signal terminal, and is configured to provide the level of the first node and the first clock signal terminal Under the control of the first clock signal, the level of the second node is controlled; the output circuit is connected to the output terminal, and configured to output an output signal at the output terminal under the control of the level of the second node; the output noise reduction circuit connected to the output terminal, and configured to denoise the output terminal under the control of the level of the first node; the reset circuit is connected to the total reset terminal and the first voltage terminal, and configured to respond to the total reset provided by the total reset terminal signal, so that the output noise reduction circuit is cut off, and the total reset signal is at an in
  • Some embodiments of the present disclosure also provide a gate driving circuit, a display device, and a driving method corresponding to the above-mentioned shift register unit.
  • the shift register unit provided by the embodiment of the present disclosure resets the output noise reduction circuit through the reset circuit in the second operation stage, so as to avoid affecting the output reset of the output noise reduction circuit due to the long-term continuous conduction of the transistor in the output noise reduction circuit and noise reduction capability, thereby prolonging the service life of the shift register unit and improving the display quality of the display panel.
  • the definition of "one frame”, “every frame” or “a certain frame” includes the first operation stage and the second operation stage in sequence, for example, the first The operation phase is a display period, and the second operation phase is a blanking phase, which is not limited in the embodiments of the present disclosure.
  • the following takes the first operation stage as a display period and the second operation stage as a blanking period as an example for illustration, which is not limited in embodiments of the present disclosure.
  • the gate drive circuit outputs the active level of the gate drive signal, and the active level of the gate drive signal can drive multiple rows of sub-pixel units in the display panel to complete a complete cycle from the first row to the last row.
  • the gate driving circuit outputs the invalid level of the gate driving signal in the blanking phase, so as to avoid abnormal display of the panel.
  • Fig. 1 is a schematic block diagram of a shift register unit provided by at least one embodiment of the present disclosure.
  • the shift register unit 10 may include an input circuit 110 , a first control circuit 120 , an output noise reduction circuit 130 , an output circuit 140 and a reset circuit 150 .
  • a gate drive circuit can be obtained by cascading a plurality of shift register units 10, and the gate drive circuit is used to drive a display panel, and sequentially provide scanning signals for a plurality of gate lines of the display panel, thereby displaying a frame on the display panel Progressive or interlaced scanning is performed during the period of the screen.
  • the input circuit 110 is connected to the input terminal IN and is configured to control the level of the first node P1 in response to an input signal input from the input terminal IN.
  • the input circuit 110 is connected to the input terminal IN, the first clock signal terminal CK and the first node P1, and is configured to be turned on under the control of the first clock signal provided by the first clock signal terminal CK, so that The input terminal IN is connected to the first node P1, so that the input signal provided by the input terminal IN is input to the first node P1, and the potential of the first node P1 is charged to the working potential (for example, it is possible to make the signal connected to the first node P1 The potential at which the transistor turns on).
  • the input circuit 110 may be connected to the input terminal IN and the first node P1, configured to conduct under the control of the input signal provided by the input terminal IN, so that the input terminal IN is connected to the first node P1, Therefore, the input signal provided by the input terminal IN is input to the first node P1, and the potential of the first node P1 is pulled up to the working potential. It should be noted that as long as the first node P1 can be charged at a corresponding stage, the embodiment of the present disclosure does not limit this.
  • the first control circuit 120 is connected to the first node P1, the second node P2, and the first clock signal terminal CK, and is configured to be at the level of the first node P1 and the level of the first clock signal provided by the first clock signal terminal CK. Under control, the level of the second node P2 is controlled.
  • the first control circuit 120 is connected to the first node P1, the second node P2, the second voltage terminal VGL and the first clock signal terminal CK, and is configured to be at the level of the first node P1 and the first Under the control of the first clock signal provided by the clock signal terminal CK, the second node P2 is connected to the second voltage terminal VGL to receive the second voltage or connected to the first clock signal terminal CK to receive the first clock signal, so that Controlling the level of the second node P2 is realized.
  • the output circuit 140 is connected to the output terminal OUT, and is configured to output an output signal at the output terminal OUT under the control of the level of the second node P2.
  • the output circuit 140 is connected to the output terminal OUT, the fourth node P4, and the first voltage terminal VGH, and is configured to be turned on under the control of the level of the fourth node P4, so that the first voltage terminal VGH The provided first voltage is output to the output terminal OUT as an output signal.
  • the fourth node P4 is connected to the second node P2 through the third control circuit 170, that is, the output circuit 140 is indirectly connected to the second node P2, that is, indirectly controlled by the second node P2, so it can also be configured as the second node P2 It is turned on under the control of the level, so that the first voltage provided by the first voltage terminal VGH is output to the output terminal OUT as an output signal.
  • under the control of the level of the second node may mean that the second node indirectly controls the output circuit, that is, whether the output circuit is turned on or not can be related to the level of the second node.
  • the control of the level that is, the level of the fourth node P4 output by other circuits related to the level (for example, the third control circuit) may also be directly controlled by the level of the second node P2.
  • Embodiments of the present disclosure There is no limit to this. The following embodiments are similar to this and will not be repeated here.
  • the output noise reduction circuit 130 is connected to the output terminal OUT, and is configured to reduce noise on the output terminal OUT under the control of the level of the first node P1.
  • the output noise reduction circuit 130 is connected to the second voltage terminal VGL, the third node P3 and the output terminal OUT, and is configured to be turned on under the control of the level of the third node P3, so that the output terminal OUT It is connected to the second voltage terminal VGL, so that the second voltage VGL can be used to pull down (for example, discharge) the output terminal OUT to achieve noise reduction.
  • the third node P3 is connected to the first node P1 through the second control circuit 160, that is, the output noise reduction circuit 130 is indirectly connected to the first node P1, that is, indirectly controlled by the first node P1, so it can also be configured as the first node P1 is turned on under the control of the level, so that the second voltage provided by the second voltage terminal VGL is output to the output terminal OUT, so as to achieve noise reduction.
  • the reset circuit 150 is connected to the overall reset terminal RST and the first voltage terminal VGH, and is configured to respond to the overall reset signal provided by the overall reset terminal RST so that the output noise reduction circuit 130 is turned off.
  • the overall reset signal is an inactive level in the first operation phase, and includes at least a section of an active level (eg, a level that enables the transistor to be turned on) in the second operation phase.
  • the reset circuit 150 is connected to the third node P3, the total reset terminal RST and the first voltage terminal VGH, and is configured to respond to the total reset signal provided by the total reset terminal RST, so that the first voltage terminal VGH is connected to the third node P3 , to reset the third node P3, so that the output noise reduction circuit 130 is turned off in response to the level of the third node P3.
  • the total reset signal includes at least one section of active level, so that the reset circuit 150 can be turned on in response to at least one section of the active level of the total reset signal during the blanking period, and the third node P3 is reset to the first voltage at least once, so that the output noise reduction circuit 130 is turned off at least once in response to the level of the third node P3, so that the transistors included in the output noise reduction circuit 130 can be prevented from being continuously turned on for a long time during the blanking phase. Affecting the performance of the transistor affects the output reset and denoising capabilities of the output noise reduction circuit 130 , thereby prolonging the service life of the circuit and ensuring the display quality of the display panel.
  • the transistor in the output noise reduction circuit will not always be on, for example, in the phase of the output circuit outputting the output signal in the display phase, the output noise reduction circuit is cut off, so , in the display stage, the reset signal is at an inactive level, thereby ensuring the normal operation of the shift register unit.
  • the shift register unit 10 further includes a second control circuit 160, for example, the second control circuit 160 is connected to the first node P1, the third node P3 and the second clock signal terminal CB, and It is configured to control the level of the third node P3 under the control of the level of the first node P1 and the second clock signal provided by the second clock signal terminal CB.
  • the second control circuit 160 is connected to the first node P1, the third node P3 and the second clock signal terminal CB, and It is configured to control the level of the third node P3 under the control of the level of the first node P1 and the second clock signal provided by the second clock signal terminal CB.
  • the second control circuit 160 is connected to the first node P1, the third node P3 and the second clock signal terminal CB, and is configured to make the third node P3 is connected to the second clock signal terminal CB, so as to provide the second clock signal provided by the second clock signal terminal CB to the third node P3, so as to control the level of the third node P3.
  • the output noise reduction circuit 130 is also connected to the third node P3, and is configured to output an inactive level of the output signal at the output terminal OUT (for example, making the transistor turn off) in response to the level of the third node P3. Level).
  • the reset circuit is also connected to the third node P3, and is configured to reset the third node P3 in response to a general reset signal provided by the general reset terminal RST, so that the output noise reduction circuit 130 is turned off.
  • a specific introduction please refer to the above introduction about the output noise reduction circuit 130 and the reset circuit 150 , which will not be repeated here.
  • the shift register unit 10 further includes a third control circuit 170, and the third control circuit 170 is connected to the second node P2, the fourth node P4 and the second clock signal terminal CB connected, and configured to control the level of the fourth node P4 under the control of the level of the second node P2 and the second clock signal provided by the second clock signal terminal CB.
  • the third control circuit 170 is connected to the second node P2, the fourth node P4 and the second clock signal terminal CB, and is configured to provide Under the control of the second clock signal, the fourth node P4 is connected to the second node P2, so as to provide the level of the second node P2 to the fourth node P4, so as to control the level of the fourth node P4.
  • Fig. 2 is a schematic block diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • the second control circuit 160 includes a first subcircuit 161; for example, the first subcircuit 161 is connected to the first node P1, the second clock signal terminal CB and the third node P3, and is configured to Under the control of the level of the first node P1, the level of the third node P3 is controlled.
  • the first sub-circuit 161 is connected to the first node P1, the second clock signal terminal CB and the third node P3, and is configured to make the second clock
  • the signal terminal CB is connected to the third node P3, so as to control the level of the third node P3.
  • Fig. 3 is a schematic block diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • the second control circuit 160 further includes a second sub-circuit 162; the second sub-circuit 162 is connected to the second voltage terminal VGL, the first node P1 and the first control node P11, and is configured to respond to The second voltage provided by the second voltage terminal VGL controls the level of the first control node P11; the first sub-circuit 161 is also connected to the first control node P11, and is configured to control the level of the first control node P11 in response to the level of the first control node P11. The level of the third node P3.
  • the second sub-circuit 162 is turned on in response to the second voltage provided by the second voltage terminal VGL, so that the first node P1 and the first control node P11 are connected, so that the level of the first control node P11 The same level as the first node P1; in this example, the first sub-circuit 161 is turned on in response to the level of the first control node P11, so that the second clock signal terminal CB is connected to the third node P3, thereby controlling the first The level of the three-node P3.
  • Fig. 4 is a schematic block diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • the second control circuit 160 further includes a sixth sub-circuit 163 .
  • the sixth sub-circuit 163 is connected to the second control node P21, the first voltage terminal VGH and the first sub-circuit 161, and is configured to control the level of the first control node P11 in response to the level of the second control node P21 keep it steady.
  • the sixth sub-circuit 163 is turned on in response to the level of the second control node P21, so that the first voltage terminal VGH is connected to the first sub-circuit 161, so that the connection with the first sub-circuit 161 can be avoided.
  • the second clock signal provided by the second clock signal terminal CB changes, it affects the level of the first control node P11, thereby affecting the normal operation of the shift register unit.
  • Fig. 5 is a schematic block diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • the third control circuit includes a third subcircuit 171 and a fourth subcircuit 172;
  • the third subcircuit 171 is connected to the second clock signal terminal CB and the second control node P21, and is configured to Under the control of the level of the second node P2, the level of the second control node P21 is controlled;
  • the fourth sub-circuit 172 is connected to the second clock signal terminal CB, the second control node P21 and the fourth node P4, and is configured to respond to The second clock signal provided by the second clock signal terminal CB controls the level of the fourth node P4.
  • the third sub-circuit 171 is turned on under the control of the level of the second node P2, so that the second clock signal terminal CB is connected to the second control node P21, thereby providing the second clock signal terminal CB with The second clock signal of the second control node P21 is provided to the second control node P21 to control the level of the second control node P21; the fourth sub-circuit 172 is turned on in response to the second clock signal provided by the second clock signal terminal CB, so that the second control The node P21 is connected to the fourth node P4, so that the level of the second control node P21 is input to the fourth node P4 to control the level of the fourth node P4.
  • Fig. 6 is a schematic block diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • the third control circuit 170 further includes a fifth sub-circuit 173, for example, the third sub-circuit 173 is connected to the second voltage terminal VGL, the second node P2 and the third control node P31, and is configured as In response to the second voltage provided by the second voltage terminal VGL, the level of the third control node P31 is controlled; the third sub-circuit 173 is also connected to the third control node P31, and configured to respond to the level of the third control node P31 , to control the level of the second control node P21.
  • the third sub-circuit 173 is also connected to the third control node P31, and configured to respond to the level of the third control node P31 , to control the level of the second control node P21.
  • the fifth sub-circuit 173 is turned on in response to the second voltage provided by the second voltage terminal VGL, and inputs the level of the second node P2 to the third control node P31 to control the third control node P31
  • the third sub-circuit 173 is configured to be turned on in response to the level of the third control node P31, so that the second clock signal terminal CB is connected to the second control node P21, so that the second clock signal The second clock signal provided by the terminal CB is provided to the second control node P21 to control the level of the second control node P21.
  • Fig. 7 is a schematic block diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • the shift register unit 10 further includes a fourth control circuit 180 .
  • the fourth control circuit 180 is connected to the first node P1, the first voltage terminal VGH and the fourth node P4, and is configured to control the level of the fourth node P4 in response to the level of the first node P1.
  • the fourth control circuit 180 is turned on in response to the level of the first node P1, so that the first voltage terminal VGH is connected to the fourth node P4, so that the first voltage provided by the first voltage terminal VGH input to the fourth node P4, so as to control the level of the fourth node P4.
  • the shift register unit 10 further includes a fifth control circuit 190 .
  • the fifth control circuit 190 is connected to the second control node P21, the third node P3 and the first voltage terminal VGH, and is configured to control the level of the third node P3 in response to the level of the second control node P21 .
  • the fifth control circuit 190 is configured to be turned on in response to the level of the second control node P21, so that the third node P3 is connected to the first voltage terminal VGH to receive the first voltage, thereby realizing the control of the third The level of node P3 is controlled.
  • Fig. 8 is a schematic block diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • the shift register unit further includes a sixth control circuit 200, for example, the sixth control circuit 200 is connected to the total reset terminal RST, the first voltage terminal VGH It is connected to the first node P1 and configured to reset the first node P1 under the control of the reset signal provided by the general reset terminal RST.
  • the sixth control circuit 200 is configured to be turned on in response to the reset signal provided by the general reset terminal RST, so that the first node P1 is connected to the first voltage terminal VGH to receive the first voltage, thereby implementing the first Node P1 is reset.
  • the first node P1 is reset, so that the first control circuit 120, the second control circuit 160 and the fourth control circuit 180 are turned off, so that they include Transistors T2, T4, T5 and T8 (as shown in FIG. 9 ) recover for a short time, so that the state of the shift register unit can be further stabilized and the service life of the circuit can be extended.
  • FIG. 9 is a circuit diagram of a specific implementation of the shift register unit shown in FIG. 7 in some examples.
  • the shift register unit 10 shown in FIG. 7 can be implemented as the circuit structure shown in FIG. 9 .
  • the shift register unit 10 includes: an input transistor M1 to a tenth control transistor M14 , a third control capacitor C1 , an output capacitor C2 , an output noise reduction capacitor C3 and a first control capacitor C4 .
  • the transistors shown in FIG. 9 are all described by taking P-type transistors as an example, and the embodiment of the present disclosure does not limit this.
  • at least some transistors in the shift register unit 10 may also use N-type transistors. .
  • FIG. 10 is a circuit diagram of a specific implementation of the shift register unit shown in FIG. 7 in some examples, that is, in the example shown in FIG. 9 Basically, a fourth control transistor T16 is also included.
  • the specific implementation of the shift register unit shown in FIG. 7 will be described in detail below with reference to FIGS. 9 and 10 .
  • the input circuit 110 includes an input transistor T1, the gate of the input transistor T1 is connected to the first clock signal terminal CK to receive the first clock signal, and the first pole of the input transistor T1 is connected to the input terminal IN To receive an input signal, the second pole of the input transistor T1 is connected to the first node P1.
  • both the gate and the first electrode of the input transistor T1 may also be connected to the input terminal IN to receive the input signal, so that when turned on in response to the input signal, the input signal is input to the first node P1.
  • the reset circuit 150 includes a reset transistor T12, the gate of the reset transistor T12 is connected to the general reset terminal RST to receive the general reset signal, and the first pole of the reset transistor T12 is connected to the first voltage terminal VGH to receive The first voltage, the second pole of the reset transistor T12 is connected to the third node P3.
  • the output noise reduction circuit 130 includes an output noise reduction transistor T10, the gate of the output noise reduction transistor T10 is connected to the third node P3, and the first pole of the output noise reduction transistor T10 is connected to the second voltage terminal VGL to receive the second voltage , the second pole of the output noise reduction transistor T10 is connected to the output terminal OUT.
  • the output noise reduction circuit 130 further includes an output noise reduction capacitor C3, the first pole of the output noise reduction capacitor C3 is connected to the second voltage terminal VGL to receive the second voltage, and the second pole of the output noise reduction capacitor C3 is connected to the third node P3 connection.
  • the output noise reduction circuit 130 may not include the output noise reduction capacitor C3.
  • the size of T10 is relatively large, and its own parasitic capacitance C31 is also relatively large, so the parasitic capacitance C31 can serve as the output noise reduction capacitor C3, for example, the capacitance value of the parasitic capacitance C31 is less than or equal to the capacitance value of the output noise reduction capacitor, and the output noise reduction circuit 130 Reducing the capacitance value of the capacitor can improve the reset speed, and the reset speed of the third node P3 will also be faster, and can increase the fluctuation margin of the threshold voltage Vth of the output transistor T10, which is beneficial to prolong the service life of the shift register unit; At the same time, the occupied area and size of the shift register unit can be reduced, which is beneficial to realize narrow frame.
  • the output circuit 140 includes an output transistor T9 and an output capacitor C2; for example, the gate of the output transistor T9 is connected to the fourth node P4, the first pole of the output transistor T9 is connected to the output terminal OUT, and the output transistor T9
  • the second pole of T9 is connected to the first voltage terminal VGH to receive the first voltage
  • the first pole of the output capacitor C2 is connected to the fourth node P4, and the second pole of the output capacitor is connected to the first voltage terminal VGH to receive the first voltage. receiving the first voltage.
  • the first sub-circuit 161 includes a first control transistor T4, a second control transistor T5, and a first control capacitor C4; the gate of the first control transistor T4 is connected to the first control node P11, and the first The first pole of the control transistor T4 is connected to the second clock signal terminal CB to receive the second clock signal, the second pole of the first control transistor T4 is connected to the first pole of the first control capacitor C4; the first pole of the first control capacitor C4 The two poles are connected to the first control node P11; the gate and the first pole of the second control transistor T5 are connected to each other and both are connected to the first control node P11, and the second pole of the second control transistor T5 is connected to the third node P3 .
  • the second sub-circuit 162 includes a third control transistor T13, the gate of the third control transistor T13 is connected to the second voltage terminal VGL, the first electrode of the third control transistor T13 is connected to the first node P1, and the third control transistor T13 The second pole of T13 is connected to the first control node P11.
  • the sixth sub-circuit 163 includes a fourth control transistor T16; the gate of the fourth control transistor T16 is connected to the second control node P21, and the first pole of the fourth control transistor T16 is connected to the first voltage terminal VGH is connected to receive the first voltage, and the second pole of the fourth control transistor T16 is connected to the first pole of the first control capacitor C4, so that when the second control node P21 is at an active level, the first control capacitor C4
  • the voltage of the first pole is stabilized at the first voltage, avoiding that when the level of the second clock signal provided by the second clock signal terminal CB connected to the first control transistor T4 jumps, due to the charge conservation of the first control capacitor C4
  • the principle is to make the level of the first control node P11 jump with the jump of the second clock signal, thereby avoiding the influence of the second clock signal terminal CB on the level of the first control node P11, thereby affecting the output noise reduction transistor T10
  • the leakage current reduces the noise when outputting high level.
  • the first control circuit 120 includes a sixth control transistor T2 and a seventh control transistor T3; the gate of the sixth control transistor T2 is connected to the first node P1, and the first electrode of the sixth control transistor T2 It is connected to the first clock signal terminal CK to receive the first clock signal, the second pole of the sixth control transistor T2 is connected to the first node P1; the gate of the seventh control transistor T3 is connected to the first clock signal terminal CK to receive the first clock signal A clock signal, the first terminal of the seventh control transistor T3 is connected to the second voltage terminal VGL to receive the second voltage, and the second terminal of the seventh control transistor T3 is connected to the second node P2.
  • the third subcircuit 171 includes an eighth control transistor T6 and a third control capacitor C1
  • the fourth subcircuit includes a ninth control transistor T7
  • the fifth subcircuit includes a tenth control transistor T14;
  • the gate of the tenth control transistor T14 is connected to the second voltage terminal VGL to receive the second voltage, the first pole of the tenth control transistor T14 is connected to the second node P2, the second pole of the tenth control transistor T14 is connected to the second node P2
  • the third control node P31 is connected; the first pole of the third control capacitor C1 is connected to the third control node P31, and the second pole of the third control capacitor C1 is connected to the second control node P21; the gate of the eighth control transistor T6 is connected to the second control node P21.
  • the third control node P31 is connected, the first pole of the eighth control transistor T6 is connected to the second clock signal terminal CB to receive the second clock signal, the second pole of the eighth control transistor T6 is connected to the second control node P21; the ninth control transistor T6 is connected to the second control node P21; The gate of the transistor T7 is connected to the second clock signal terminal CB to receive the second clock signal, the first pole of the ninth control transistor T7 is connected to the second control node P2, and the second pole of the ninth control transistor T9 is connected to the fourth node P4 connection.
  • the third control transistor T13 can reduce the leakage current of the first control node P11, and the tenth control transistor T14 can reduce the leakage current of the third control node P31, so that the response speed of the gate driving signal output is faster.
  • the fourth control circuit 180 includes an eleventh control transistor T8, the gate of the eleventh control transistor T8 is connected to the first node P1, the first electrode of the eleventh control transistor T8 is connected to the fourth node P4, and the gate of the eleventh control transistor T8 is connected to the fourth node P4.
  • a second terminal of a control transistor T8 is connected to the first voltage terminal VGH to receive the first voltage.
  • the fifth control circuit 190 includes a twelfth control transistor T11, the gate of the twelfth control transistor T11 is connected to the second control node P21, the first pole of the twelfth control transistor T11 is connected to the third node P3, and the gate of the twelfth control transistor T11 is connected to the third node P3.
  • the second electrode of the twelve control transistor P21 is connected to the first voltage terminal VGH to receive the first voltage.
  • FIG. 11 is a circuit diagram of a specific implementation of the shift register unit shown in FIG. 8 in some examples.
  • the shift register unit 10 shown in FIG. 8 can be implemented as shown in FIG. 11 circuit structure.
  • the shift register unit 10 further includes: a fifth control transistor T15 .
  • the circuit structure shown in FIG. 11 is basically the same as the circuit structure shown in FIG. 9 .
  • the sixth control circuit 200 includes a fifth control transistor T15; the gate of the fifth control transistor T15 is connected to the total reset terminal RST to receive the total reset signal, and the first pole of the fifth control transistor T15 and The first voltage terminal VGH is connected to receive the first voltage, and the second electrode of the fifth control transistor T15 is connected to the first node P1.
  • FIG. 12 is a circuit diagram of a specific implementation of the shift register unit shown in FIG. 2 in some examples.
  • the shift register unit 10 shown in FIG. 2 can be implemented as shown in FIG. 12 circuit structure.
  • the second control circuit 160 of the shift register unit 10 only includes the first subcircuit, that is, on the basis of the example shown in FIG. 9, does not include The third control transistor T13.
  • the circuit structure shown in FIG. 12 is basically the same as the circuit structure shown in FIG. 9 , and for specific description, refer to the introduction in FIG. 9 , which will not be repeated here.
  • FIG. 13 is a circuit diagram of a specific implementation of the shift register unit shown in FIG. 5 when the second subcircuit and the sixth subcircuit are not included.
  • the shift register shown in FIG. 5 The unit 10 can be implemented as the circuit structure shown in FIG. 13 when the second sub-circuit and the sixth sub-circuit are not included.
  • the second control circuit 160 of the shift register unit 10 only includes the first subcircuit
  • the third control circuit 170 only includes the third subcircuit and the fourth subcircuit.
  • the sub-circuit that is, on the basis of the example shown in FIG. 9, does not include the third control transistor T13 and the tenth control transistor T14.
  • circuit structure shown in FIG. 13 is basically the same as the circuit structure shown in FIG. 9 , and the specific description may refer to the introduction in FIG. 9 , which will not be repeated here.
  • the third control capacitor C1 can be used to maintain the potential at the second control node P21, and the output capacitor C2 can be used to maintain the potential at the fourth node P4,
  • the potential at the third node P3 is maintained by the output noise reduction capacitor C3 or the parasitic capacitor C31 , and the potential at the first control node P11 is maintained by the first control capacitor C4 .
  • the third control capacitor C1, the output capacitor C2, the output noise reduction capacitor C3, and the first control capacitor C4 can be capacitive devices manufactured through a process, for example, by making special capacitive electrodes to realize the capacitive device, and each electrode of the capacitor can be passed through metal layer, semiconductor layer (such as doped polysilicon), etc., or in some examples, by designing circuit wiring parameters so that the third control capacitor C1, the output capacitor C2, the output noise reduction capacitor C3 and the first control capacitor C4 can also pass through The parasitic capacitance between the various devices is realized.
  • connection method of the third control capacitor C1, the output capacitor C2, the output noise reduction capacitor C3 and the first control capacitor C4 is not limited to the method described above, and can also be other applicable connection methods, as long as it can store and write to the second control The levels of the node P21, the fourth node P4, the third node P3 and the first control node P11 are sufficient.
  • VGH indicates both the first voltage terminal and the first voltage
  • VGL indicates both the second voltage terminal and the second voltage.
  • the first voltage VGH is, for example, a high level
  • the second voltage VGL is, for example, a low level.
  • the first voltage VGH is greater than the second voltage VGL.
  • the high level and the low level are relative terms.
  • the high level indicates a higher voltage range (for example, 5V, 10V or other suitable voltage can be used for the high level), and multiple high levels can be the same or different.
  • the low level represents a lower voltage range (for example, the low level can adopt 0V, -5V, -10V or other suitable voltages), and multiple low levels can be the same or different.
  • the minimum value of the high level is greater than the maximum value of the low level.
  • controlling the level of a node includes charging the node to pull up the level of the node, or charging the node Discharge to pull down the level of the node.
  • a capacitor for example, the above-mentioned capacitors C1-C4 that is electrically connected to the node can be set, charging the node means charging the capacitor electrically connected to the node; similarly, discharging the node means Discharge the capacitance electrically connected to the node; the high level or low level of the node can be maintained through the capacitance.
  • CK represents both the first clock signal terminal and the first clock signal
  • CB represents the second clock signal terminal and the second clock signal.
  • pulse-up means charging a node or an electrode of a transistor so that the absolute level of the node or the electrode The value increases, thereby realizing the operation of the corresponding transistor (such as turning on);
  • pulse-down means discharging a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode decreases, thereby realizing the corresponding Operation of transistors (e.g. cut off).
  • pulse-up means to discharge a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode decreases, thereby realizing the corresponding transistor
  • Pull-down refers to charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode rises, thereby realizing the operation of the corresponding transistor (such as cut-off) .
  • the control node P31 does not represent an actually existing component, but represents a confluence point of relevant electrical connections in the circuit diagram.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking thin film transistors as examples.
  • the source and drain of the transistor used here may be symmetrical in structure, so there may be no difference in structure between the source and drain.
  • transistors in order to distinguish the two poles of the transistor except the gate, it is directly described that one pole is the first pole and the other pole is the second pole.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltage)
  • the cut-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage );
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage)
  • the cut-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltage).
  • the transistors in the embodiments of the present disclosure are described by taking a P-type transistor as an example.
  • the first pole of the transistor is a drain
  • the second pole is a source.
  • the present disclosure includes but is not limited to this.
  • one or more transistors in the shift register unit 10 provided by the embodiments of the present disclosure may also use N-type transistors.
  • the first pole of the transistor is the source
  • the second pole is the drain.
  • the poles of transistors of a certain type are connected correspondingly with reference to the poles of the corresponding transistors in the embodiments of the present disclosure, and the corresponding voltage terminals can provide corresponding high levels or low levels.
  • ITZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Poly Silicon
  • amorphous silicon such as hydrogenated amorphous Crystalline silicon
  • FIG. 15A shows a signal timing diagram when the shift register unit 10 shown in FIG. 14 works.
  • the driving method includes a first operation stage S1 and a second operation stage S2; in the first operation stage S1, the driving method includes a first sub-stage t1, a second sub-stage t2 and a third Sub-stage t3.
  • a frame includes a first operation stage S1 (that is, a display stage) and a second operation stage S2 (that is, a blanking stage).
  • the display stage is used to drive the display panel to display, and the blanking stage is the display stage of the current frame and the next frame. Shows the phases between phases.
  • the signal levels in the signal timing diagram shown in Fig. 15A are only schematic and do not represent real level values.
  • the input circuit 110 controls the level of the first node P1 in response to the active level of the input signal input at the input terminal IN; the first control circuit 120 controls the level of the first node P1 and the first Under the control of the first clock signal provided by the clock signal terminal CK, the level of the second node P2 is controlled.
  • the output circuit 140 In the second sub-phase t2, the output circuit 140 outputs an output signal at the output terminal OUT under the control of the level of the second node P2.
  • the output noise reduction circuit 130 reduces noise on the output terminal OUT under the control of the level of the first node P1.
  • the driving method further includes a fourth sub-stage t4, a fifth sub-stage t5 and a sixth sub-stage t6.
  • the first sub-phase t1 is the input phase t1
  • the second sub-phase t2 is the output phase t2
  • the third sub-phase t3 is the reset phase t3
  • the fourth sub-phase t4 is the first holding period t4
  • the fifth sub-phase t5 is the second holding time period t5
  • the sixth sub-phase t6 is the third holding time period t6.
  • the general reset signal terminal RST provides a high level
  • the reset transistor T12 is turned off in response to the high level of the general reset signal.
  • the first clock signal terminal CK provides a low level
  • the second clock signal terminal CB provides a high level
  • the input terminal IN provides a high level
  • the input transistor T1 is turned on in response to the low level of the first clock signal
  • the third control transistor T13 is turned on in response to the second voltage provided by the second voltage terminal VGL
  • the potential of the first node P1 is high level
  • the potential of the first control node P11 is high level
  • the second control transistor T5 is turned off in response to the high level of the first control node P11
  • the sixth control transistor T2 is turned off in response to the high level of the first node P1
  • the seventh control transistor T3 is turned off in response to the low level of the first clock signal is turned on
  • the tenth control transistor T14 is turned on in response to the second voltage provided by the second voltage terminal VGL
  • the potential of the second node P2 is low level
  • the potential of the third control node P31 is low level
  • the first clock signal terminal CK provides a high level
  • the second clock signal terminal CB provides a low level
  • the input terminal IN provides a low level
  • the input transistor T1 is turned off
  • the third control transistor T13 is turned on
  • the first The potentials of the node P1 and the first control node P11 are maintained at a high level
  • the first control transistor T4 is turned off
  • the second control transistor T5 is turned off
  • the sixth control transistor T2 and the seventh control transistor T3 are turned off
  • the potential of the second node P2 is maintained is low level
  • the eighth control transistor T6 is turned on
  • the low level provided by the second clock signal terminal CB is input to the second control node P21
  • the second control node P21 changes from high level to low level, according to the The charge conservation principle of the third control capacitor C1, the potential of the third control node P31 is further pulled down by the third control capacitor C1, the ninth control transistor T7 is turned on, the eighth control transistor T8 is turned off, and the twel
  • the first clock signal terminal CK provides a low level
  • the second clock signal terminal CB provides a high level
  • the input terminal IN provides a low level
  • the input transistor T1 is turned on
  • the third control transistor T13 is turned on
  • the potential of the first control node P11 is pulled down
  • the second control transistor T5 is turned on
  • the potential of the third node P3 is pulled down
  • the output noise reduction transistor T10 responds to the voltage of the third node P3
  • the level is turned on, and the second voltage provided by the second voltage terminal VGL is output to the output terminal OUT, and the output terminal OUT outputs a low level, thereby realizing the noise reduction of the output terminal OUT
  • the sixth control transistor T2 and the seventh control transistor T3 is turned on, the potential of the second node P2 is low level
  • the tenth control transistor T14 is turned on
  • the eighth control transistor T6 is turned on
  • the second control node P21 becomes the high level provided by the second
  • the first clock signal terminal CK provides a high level
  • the second clock signal terminal CB provides a low level
  • the input terminal IN provides a low level
  • the input transistor T1 is turned off
  • the first node The potential of P1 is maintained at low level
  • the third control transistor T13 is turned on
  • the first control transistor T4 is turned on
  • the second clock signal terminal CB pulls down the potential of the first control node P11 through the first control capacitor C4, and the second control
  • the transistor T5 is turned on, so that the potential of the third node P3 is kept lower than VGL+Vth
  • Vth is the threshold voltage of the output noise reduction transistor T10, so that the output noise reduction transistor T10 is turned on, and then the gate of the output terminal OUT is driven
  • the potential of the signal is maintained at the second voltage, that is, maintained at a low level, and is not affected by noise interference; the seventh control transistor T3 is turned off, the sixth control transistor T2 is turned on, and the potential of the second node P
  • the first clock signal terminal CK provides a low level
  • the second clock signal terminal CB provides a high level
  • the input terminal IN provides a low level
  • the input transistor T1 is turned on
  • the first The potential of node P1 is at low level
  • the third control transistor T13 is turned on
  • the first control node P11 is at low level
  • the first control transistor T4 is turned on in response to the low level of the first control node P11
  • the second clock signal The potential of the input clock signal provided by the terminal CB increases, according to the charge conservation principle of the first control capacitor C4, thereby pulling up the potential of the first control node P11, the second control transistor T5 is turned off, and does not affect the potential of the third node P3,
  • the potential of the third node P3 is kept lower than VGL+Vth, and Vth is the threshold voltage of the output noise reduction transistor T10, so that the output noise reduction transistor T10 is turned on, so that the potential of the gate driving signal output from the output terminal OUT
  • the potential of the third control node P31 is low level, the eighth control transistor T6 is turned on, the potential of the second control node P21 is high level, the ninth control transistor T7 is turned off, the eighth control transistor T8 is turned off, and the fourth node P4 The potential remains at a high level, and the ninth transistor T9 is turned off.
  • the first clock signal terminal CK provides a high level
  • the second clock signal terminal CB provides a low level
  • the input terminal IN provides a low level
  • the input transistor T1 is turned off
  • the first node The potential of P1 is maintained at a low level
  • the first control transistor T4 is turned on
  • the second clock signal terminal CB pulls down the potential of the first control node P11 through the first control capacitor C4
  • the second control transistor T5 is turned on, thereby making the first
  • the potential of the three-node P3 is kept lower than VGL+Vth
  • Vth is the threshold voltage of the output noise reduction transistor T10, so that the output noise reduction transistor T10 is turned on, so that the potential of the gate drive signal output from the output terminal OUT is maintained at the second voltage , that is, low level, not affected by noise interference
  • the seventh control transistor T3 is turned off
  • the sixth control transistor T2 is turned on
  • the potential of the second node P2 is high level
  • the potential of the third node P1 can be maintained to be lower than VGL+Vth, Vth is the threshold voltage of the output noise reduction transistor T10, so that the output noise reduction transistor T10 is turned on, so that the gate drive signal output from the output terminal OUT is The potential is maintained at the second voltage and is not affected by noise interference.
  • the first control transistor T4, the first control capacitor C4, and the second control transistor T5 form a charge pump structure.
  • the charge pump is a structure similar to a water pump in the circuit, mainly through Capacitor, clock signal and diode rectification structure (in Fig. 9-14, the second control transistor T5 adopts diode connection mode) realizes the redistribution of charge and realizes the purpose of stepping up (or stepping down).
  • the driving method of the shift register unit includes at least one reset stage t7. Only one reset phase t7 is shown in FIG. 15A , which is not limited by the embodiments of the present disclosure.
  • the active level (for example, low level) of the general reset signal is applied to the general reset terminal RST, and the inactive level (for example, high level) of the first clock signal is applied to the first clock signal terminal CLK. level).
  • the reset circuit 150 turns off the output noise reduction circuit 130 in response to the active level of the overall reset signal.
  • the second control circuit 160 is connected to the first node P1, the third node P3 and the second clock signal terminal CB, and is configured to be at the first node Under the control of the level of P1 and the second clock signal provided by the second clock signal terminal CB, the level of the third node P3 is controlled; the output noise reduction circuit 130 is also connected to the third node P3, and is configured to respond to the third node P3 The level of the three nodes P3, output the invalid level of the output signal at the output terminal OUT; the reset stage t7 also includes: applying the invalid level of the second clock signal to the second clock signal terminal CB, and the reset circuit 150 responds to the overall reset signal The active level of the third node P3 is reset, so that the output noise reduction circuit 130 is turned off in response to the level of the third node P3.
  • the first clock signal terminal CK provides a high level
  • the second clock signal terminal CB provides a high level
  • the input terminal IN provides a low level
  • the total reset terminal RST provides a low level
  • the input transistor T1 is turned off, the potential of the first node P1 is maintained at a low level
  • the third control transistor T13 is turned on
  • the first control node P11 is at a low level
  • the first control transistor T4 responds to the low level of the first control node P11 flat conduction
  • the potential of the input clock signal provided by the second clock signal terminal CB rises, and according to the principle of charge conservation of the first control capacitor C4, the potential of the first control node P11 is pulled up
  • the second control transistor T5 is turned off.
  • the reset transistor T12 is turned on in response to the low level of the general reset signal, so that the first voltage terminal VGH is connected to the third node P3, thereby pulling up the voltage of the third node P3, and the output noise reduction transistor T10 is turned off, so that the output noise reduction transistor T10 is cut off in at least one reset phase t7 of the second operation phase S2, so that the output noise reduction transistor T10 can be prevented from being turned on all the time in the second operation phase S2, which affects the output reset and noise reduction capabilities of the output noise reduction circuit 130, so that it can be The service life of the shift register unit is extended, and the display quality of the display panel is improved.
  • the sixth control transistor T2 is turned on, and the seventh control transistor T3 is turned off, so that the second node P2 is connected to the first clock signal terminal CK, and the potential of the second node P2 is at the high level of the first clock signal terminal CK.
  • the tenth control transistor T14 is turned on, the potential of the third control node P31 is at a high level
  • the eighth control transistor T6 is turned off, the potential of the second control node P21 is kept at a high level
  • the ninth control transistor T7 is turned off
  • the eighth control transistor T7 is turned off.
  • the transistor T8 is turned on, the potential of the fourth node P4 remains at a high level
  • the ninth transistor T9 is turned off.
  • FIG. 15B shows a signal timing diagram when the shift register unit 10 shown in FIG. 11 works.
  • the working process of the shift register unit shown in FIG. 11 is similar to that of the shift register unit shown in FIG.
  • the high level of the signal is turned on, so that the first node P1 is connected to the first voltage terminal VGH, so that the level of the first node P1 is high level, and the third control transistor T13 is turned on, so that the first control node P11 It is connected to the first node P1, so that the level of the first control node P11 is at a high level, and other processes may refer to the introduction in FIG. 15A , which will not be repeated here.
  • At least one embodiment of the present disclosure also provides a gate drive circuit 20.
  • the gate drive circuit 20 includes a plurality of cascaded shift register units 10, any one or more of which The unit 10 may adopt the structure of the shift register unit 10 provided by any embodiment of the present disclosure or its variants.
  • At least one embodiment of the present disclosure further provides a display device 1 , as shown in FIG. 17 , the display device 1 includes the gate driving circuit 20 provided by the embodiment of the present disclosure and a plurality of sub-pixel units 410 arranged in an array.
  • the display device 1 further includes a display panel 40 , and a pixel array formed by a plurality of sub-pixel units 410 is disposed in the display panel 40 .
  • each shift register unit 10 in the gate driving circuit 20 is electrically connected to the sub-pixel units 410 of each row, for example, the gate driving circuit 20 is electrically connected to the sub-pixel units 410 through the gate line GL.
  • the gate driving circuit 20 is used for providing a driving signal to the pixel array, for example, the driving signal can drive the scanning transistor and the sensing transistor in the sub-pixel unit 410 .
  • the display device 1 may further include a data driving circuit 30 for providing data signals to the pixel array.
  • the data driving circuit 30 is electrically connected to the sub-pixel unit 410 through the data line DL.
  • the display device 1 in this embodiment can be any display device such as a liquid crystal panel, a liquid crystal TV, a monitor, an OLED panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. A product or part with a display function.

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Abstract

公开了一种移位寄存器单元及其驱动方法、栅极驱动电路和显示装置。移位寄存器单元包括：输入电路（110）、第一控制电路（120）、输出电路（140）、输出降噪电路（130）和复位电路（150）；输入电路（110）与输入端（IN）连接，且配置为响应于输入端（IN）输入的输入信号对第一节点(P1)的电平进行控制；第一控制电路（120）与第一节点(P1)、第二节点(P2)和第一时钟信号端(CK)连接，且配置为在第一节点(P1)的电平和第一时钟信号端(CK)提供的第一时钟信号的控制下，对第二节点(P2)的电平进行控制；输出电路(140)与输出端(OUT)连接，且配置为在第二节点(P2)的电平的控制下，在输出端(OUT)输出输出信号；输出降噪电路（130）与输出端(OUT)连接，且配置为在第一节点(P1)的电平的控制下，对输出端(OUT)降噪；复位电路（150）与总复位端(RST)和第一电压端(VGH)连接，且配置为响应于总复位端(RST)提供的总复位信号，使得输出降噪电路（130）截止，总复位信号在第一操作阶段为无效电平，在第二操作阶段包括至少一段有效电平。移位寄存器单元可以避免因输出降噪电路（130）中的晶体管长时间连续导通而影响输出降噪电路的输出复位和降噪能力，从而可以延长移位寄存器单元的使用寿命，提高显示面板的显示质量。

Description

移位寄存器单元及其驱动方法、栅极驱动电路和显示装置 技术领域
本公开的实施例涉及一种移位寄存器单元及其驱动方法、栅极驱动电路和显示装置。
背景技术
在显示技术领域，例如液晶显示面板或有机发光二极管(Organic Light Emitting Diode,OLED)显示面板的像素阵列通常包括多行栅极扫描信号线和与栅极扫描信号线交错的多列数据线。对栅极扫描信号线的驱动可以通过绑定的集成驱动电路实现。近几年随着非晶硅薄膜晶体管或氧化物薄膜晶体管制备工艺的不断提高，也可以将栅极扫描信号线驱动电路直接集成在薄膜晶体管阵列基板上形成GOA(Gate driver On Array)来对栅极扫描信号线进行驱动。例如，可以采用包括多个级联的移位寄存器单元的GOA为像素阵列的多行栅极扫描信号线提供开关态电压信号(扫描信号)，从而例如控制多行栅极扫描信号线依序导通，并且同时由数据线向像素阵列中对应行的像素单元提供数据信号，以在各像素单元形成显示图像的各灰阶所需要的灰度电压，进而显示一帧图像。
发明内容
本公开至少一实施例提供一种移位寄存器单元，包括：输入电路、第一控制电路、输出电路、输出降噪电路和复位电路；所述输入电路与输入端连接，且配置为响应于所述输入端输入的输入信号对第一节点的电平进行控制；所述第一控制电路与所述第一节点、第二节点和第一时钟信号端连接，且配置为在所述第一节点的电平和所述第一时钟信号端提供的第一时钟信号的控制下，对所述第二节点的电平进行控制；所述输出电路与输出端连接，且配置为在所述第二节点的电平的控制下，在所述输出端输出输出信号；所述输出降噪电路与所述输出端连接，且配置为在所述第一节点的电平的控制下，对所述输出端降噪；所述复位电路与总复位端和第一电压端连接，且配置为响应于所述总复位端提供的总复位信号，使得所述输出降噪电路截止，其中，所述总复位信号在第一操作阶段为无效电平，在第二操作阶段包括至少一段有效电平。
例如，本公开至少一实施例提供的移位寄存器单元，还包括第二控制电路，所述第二控制电路与所述第一节点、第三节点和第二时钟信号端连接，且配置为在所述第一节点的电平和所述第二时钟信号端提供的第二时钟信号的控制下，对所述第三节点的电平进行控制；所述输出降噪电路还与所述第三节点连接，且配置为响应于所述第三节点的电平，在所述输出端输出所述输出信号的无效电平。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述复位电路还与所述第三节点连接，且配置为响应于所述总复位端提供的总复位信号，对所述第三节点进行复位，以使得所述输出降噪电路截止。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第二控制电路包括第一子电路；所述第一子电路与所述第一节点、所述第二时钟信号端和所述第三节点连接，且配置为在所述第一节点的电平的控制下，控制所述第三节点的电平。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第二控制电路还包括第二子电路；所述第二子电路与第二电压端、所述第一节点和第一控制节点连接，且配置为响应于所述第二电压端提供的第二电压，控制所述第一控制节点的电平；所述第一子电路还与所述第一控制节点连接，且配置为响应于所述第一控制节点的电平，控制所述第三节点的电平。
例如，本公开至少一实施例提供的移位寄存器单元，还包括第三控制电路，所述第三控制电路与所述第二节点、第四节点和所述第二时钟信号端连接，且配置为在所述第二节点的电平和所述第二时钟信号端提供的第二时钟信号的控制下，对所述第四节点的电平进行控制。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第三控制电路包括第三子电路和第四子电路；所述第三子电路与所述第二时钟信号端和第二控制节点连接，且配置为在所述第二节点的电平的控制下，控制所述第二控制节点的电平；所述第四子电路与所述第二时钟信号端、所述第二控制节点和所述第四节点连接，且配置为响应于所述第二时钟信号端提供的第二时钟信号，控制所述第四节点的电平。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第三控制电路还包括第五子电路，所述第五子电路与第二电压端、所述第二节点和第三控制节点连接，且配置为响应于所述第二电压端提供的第二电压，控制所述第三控制节点的电平；所述第三子电路还与所述第三控制节点连接，且配置为响应于所述第三控制节点的电平，控制所述第二控制节点的电平。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第二控制电路还包括第六子电路，所述第六子电路与所述第二控制节点、第一电压端和所述第一子电路连接，且配置为响应于所述第二控制节点的电平，控制所述第一控制节点的电平保持稳定。
例如，本公开至少一实施例提供的移位寄存器单元还包括第四控制电路，所述第四控制电路与所述第一节点、所述第一电压端和所述第四节点连接，且配置为响应于所述第一节点的电平，对所述第四节点的电平进行控制。
例如，本公开至少一实施例提供的移位寄存器单元还包括第五控制电路，所述第五控制电路与所述第二控制节点、所述第三节点和所述第一电压端连接，且配置为响应于所述第二控制节点的电平，对所述第三节点的电平进行控制。
例如，本公开至少一实施例提供的移位寄存器单元还包括第六控制电路，所述第六控制电路与所述总复位端、所述第一电压端和所述第一节点连接，且配置为在所述总复位端提供的复位信号的控制下，对所述第一节点进行复位。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述输入电路包括输入晶体管， 所述输入晶体管的栅极和所述第一时钟信号端连接以接收所述第一时钟信号，所述输入晶体管的第一极和所述输入端连接以接收所述输入信号，所述输入晶体管的第二极和所述第一节点连接。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述复位电路包括复位晶体管，所述复位晶体管的栅极与所述总复位端连接以接收所述总复位信号，所述复位晶体管的第一极和所述第一电压端连接以接收第一电压，所述复位晶体管的第二极和所述第三节点连接。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述输出降噪电路包括输出降噪晶体管，所述输出降噪晶体管的栅极和所述第三节点连接，所述输出降噪晶体管的第一极和第二电压端连接以接收第二电压，所述输出降噪晶体管的第二极和所述输出端连接。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述输出降噪电路还包括输出降噪电容，所述输出降噪电容的第一极和所述第二电压端连接以接收所述第二电压，所述输出降噪电容的第二极和所述第三节点连接。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述输出电路包括输出晶体管和输出电容；所述输出晶体管的栅极和所述第四节点连接，所述输出晶体管的第一极和所述输出端连接，所述输出晶体管的第二极和所述第一电压端连接以接收第一电压；所述输出电容的第一极和所述第四节点连接，所述输出电容的第二极和所述第一电压端连接以接收所述第一电压。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第一子电路包括第一控制晶体管、第二控制晶体管和第一控制电容；所述第一控制晶体管的栅极和所述第一控制节点连接，所述第一控制晶体管的第一极和所述第二时钟信号端连接以接收所述第二时钟信号，所述第一控制晶体管的第二极和所述第一控制电容的第一极连接；所述第一控制电容的第二极和所述第一控制节点连接；所述第二控制晶体管的栅极和第一极彼此连接，且均与所述第一控制节点连接，所述第二控制晶体管的第二极和所述第三节点连接。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第二子电路包括第三控制晶体管，所述第三控制晶体管的栅极和所述第二电压端连接，所述第三控制晶体管的第一极和所述第一节点连接，所述第三控制晶体管的第二极和所述第一控制节点连接。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第六子电路包括第四控制晶体管；所述第四控制晶体管的栅极和所述第二控制节点连接，所述第四控制晶体管的第一极和所述第一电压端连接以接收第一电压，所述第四控制晶体管的第二极和所述第一控制电容的第一极连接。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第六控制电路包括第五控制晶体管；所述第五控制晶体管的栅极和所述总复位端连接以接收所述总复位信号，所述第五控制晶体管的第一极和所述第一电压端连接以接收第一电压，所述第五控制晶体管的第二极和所述第一节点连接。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第一控制电路包括第六控制晶体管和第七控制晶体管；所述第六控制晶体管的栅极和所述第一节点连接，所述第六控制晶体管的第一极和所述第一时钟信号端连接以接收所述第一时钟信号，所述第六控制晶体管的第二极和所述第二节点连接；所述第七控制晶体管的栅极和所述第一时钟信号端连接以接收所述第一时钟信号，所述第七控制晶体管的第一极和第二电压端连接以接收第二电压，所述第七控制晶体管的第二极和所述第二节点连接。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第三子电路包括第八控制晶体管和第三控制电容，所述第四子电路包括第九控制晶体管，所述第五子电路包括第十控制晶体管；所述第十控制晶体管的栅极和所述第二电压端连接以接收所述第二电压，所述第十控制晶体管的第一极和所述第二节点连接，所述第十控制晶体管的第二极和所述第三控制节点连接；所述第三控制电容的第一极和所述第三控制节点连接，所述第三控制电容的第二极和所述第二控制节点连接；所述第八控制晶体管的栅极和所述第三控制节点连接，所述第八控制晶体管的第一极和所述第二时钟信号端连接以接收所述第二时钟信号，所述第八控制晶体管的第二极和所述第二控制节点连接；所述第九控制晶体管的栅极和所述第二时钟信号端连接以接收所述第二时钟信号，所述第九控制晶体管的第一极和所述第二控制节点连接，所述第九控制晶体管的第二极和所述第四节点连接。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第四控制电路包括第十一控制晶体管，所述第十一控制晶体管的栅极和所述第一节点连接，所述第十一控制晶体管的第一极和所述第四节点连接，所述第十一控制晶体管的第二极和所述第一电压端连接以接收第一电压。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第五控制电路包括第十二控制晶体管，所述第十二控制晶体管的栅极和所述第二控制节点连接，所述第十二控制晶体管的第一极和所述第三节点连接，所述第十二控制晶体管的第二极和所述第一电压端连接以接收第一电压。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的本公开任一实施例提供的移位寄存器单元。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，包括第一操作阶段和第二操作阶段；在所述第一操作阶段，所述驱动方法包括第一子阶段、第二子阶段和第三子阶段：在所述第一子阶段，所述输入电路响应于所述输入端输入的输入信号的有效电平，对第一节点的电平进行控制；所述第一控制电路在所述第一节点的电平和所述第一时钟信号端提供的第一时钟信号的控制下，对所述第二节点的电平进行控制；在所述第二子阶段，所述输出电路在所述第二节点的电平的控制下，在所述输出端输出输出信号；在所述第三子阶段，所述输出降噪电路在所述第一节点的电平的控制下，对所述输出端降噪；在所述第二操作阶段，所述驱动方法包括至少一个复位阶段，在所述至少一个复位阶段，向所述总复位端施加总复位信号的有效电平，向所述第一时钟信号端施加所述第一时钟信号的无效电平，所 述复位电路响应于所述总复位信号的有效电平，使得所述输出降噪电路截止。
例如，在本公开至少一实施例提供的驱动方法中，在所述移位寄存器单元还包括第二控制电路的情形下，其中，所述第二控制电路与所述第一节点、第三节点和第二时钟信号端连接，且配置为在所述第一节点的电平和所述第二时钟信号端提供的第二时钟信号的控制下，对所述第三节点的电平进行控制；所述输出降噪电路还与所述第三节点连接，且配置为响应于所述第三节点的电平，在所述输出端输出所述输出信号的无效电平；所述复位阶段还包括：向所述第二时钟信号端施加所述第二时钟信号的无效电平，所述复位电路响应于所述总复位信号的有效电平，对所述第三节点进行复位，以使得所述输出降噪电路响应于所述第三节点的电平截止。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例提供的栅极驱动电路。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一实施例提供的一种移位寄存器单元的示意框图；
图2为本公开至少一实施例提供的另一种移位寄存器单元的示意框图；
图3为本公开至少一实施例提供的另一种移位寄存器单元的示意框图；
图4为本公开至少一实施例提供的另一种移位寄存器单元的示意框图；
图5为本公开至少一实施例提供的另一种移位寄存器单元的示意框图；
图6为本公开至少一实施例提供的另一种移位寄存器单元的示意框图；
图7为本公开至少一实施例提供的另一种移位寄存器单元的示意框图；
图8为本公开至少一实施例提供的另一种移位寄存器单元的示意框图；
图9为图7所示的移位寄存器单元在一些示例中的具体实现方式的电路图；
图10为图7所示的移位寄存器单元在另一些示例中的具体实现方式的电路图；
图11为图8所示的移位寄存器单元在一些示例中的具体实现方式的电路图；
图12为图2所示的移位寄存器单元在一些示例中的具体实现方式的电路图；
图13为图5所示的移位寄存器单元在不包括第二子电路和第六子电路时的具体实现方式的电路图；
图14为图7所示的移位寄存器单元在又一些示例中的具体实现方式的电路图；
图15A示出了图14所示的移位寄存器单元10工作时的信号时序图；
图15B示出了图11所示的移位寄存器单元10工作时的信号时序图；
图16为本公开至少一实施例提供的一种栅极驱动电路的示意图；
图17为本公开至少一实施例提供的一种显示装置的示意图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。
为了保持像素亮度波动在合理的范围内，静态画面时仍然需要刷新数据，因为控制像素亮度的电压会由于晶体管的漏电而随时间变化。为了降低显示面板的功耗，可以降低其刷新频率，同时为了保证显示面板的显示质量不受影响，就需要降低晶体管的漏电速度，而氧化物半导体具有超低漏电的特性，满足这种需求。
在栅极驱动电路驱动一个显示面板中的多行子像素单元时，需要在显示阶段逐行输出栅极扫描驱动信号的有效电平以逐行驱动多行子像素单元发光，同时为了保证显示面板的正常显示，在消隐阶段，需要开启栅极驱动电路中各个移位寄存器单元的复位晶体管以对输出端进行复位和降噪，从而在消隐阶段输出栅极扫描信号的无效电平。但是，在消隐阶段，特别是低频驱动显示面板时，由于复位晶体管长时间连续开启会影响输出复位和降噪的能力，从而影响栅极驱动电路的使用寿命。
本公开至少一实施例提供一种移位寄存器单元，包括：输入电路、第一控制电路、输出电路、输出降噪电路和复位电路；输入电路与输入端连接，且配置为响应于输入端输入的输入信号对第一节点的电平进行控制；第一控制电路与第一节点、第二节点和第一时钟信号端连接，且配置为在第一节点的电平和第一时钟信号端提供的第一时钟信号的控制下，对第二节点的电平进行控制；输出电路与输出端连接，且配置为在第二节点的电平的控制下，在输出端输出输出信号；输出降噪电路与输出端连接，且配置为在第一节点的电平的控制下，对输出端降噪；复位电路与总复位端和第一电压端连接，且配置为响应于总复位端提供的总复位信号，使得输出降噪电路截止，总复位信号在第一操作阶段为无效电平，在第二操作阶段包括至少一段有效电平。
本公开一些实施例还提供对应于上述移位寄存器单元的栅极驱动电路、显示装置及驱 动方法。
本公开实施例提供的移位寄存器单元在第二操作阶段通过复位电路对输出降噪电路进行复位，从而避免因输出降噪电路中的晶体管长时间连续导通而影响输出降噪电路的输出复位和降噪能力，从而可以延长移位寄存器单元的使用寿命，提高显示面板的显示质量。
另外，在本公开的实施例中，为了表示清楚、简洁，定义“一帧”、“每帧”或“某一帧”包括依次进行的第一操作阶段和第二操作阶段，例如，第一操作阶段为显示时段，第二操作阶段为消隐阶段，本公开的实施例对此不作限制。下面以第一操作阶段为显示时段，第二操作阶段为消隐阶段为例进行说明，本公开的实施例对此不作限制。例如在显示时段中栅极驱动电路输出栅极驱动信号的有效电平，该栅极驱动信号的有效电平可以驱动显示面板中的多行子像素单元从第一行到最后一行完成完整的一幅图像的扫描显示，在消隐阶段中栅极驱动电路输出栅极驱动信号的无效电平，从而避免实现面板的显示异常。
下面结合附图对本公开的实施例及其示例进行详细说明。
图1为本公开至少一实施例提供的一种移位寄存器单元的示意框图。如图1所示，在一些示例中，该移位寄存器单元10可以包括输入电路110、第一控制电路120、输出降噪电路130、输出电路140和复位电路150。通过级联多个该移位寄存器单元10可以得到栅极驱动电路，该栅极驱动电路用于驱动显示面板，为显示面板的多条栅线依序提供扫描信号，从而在显示面板显示一帧画面的期间进行逐行或隔行扫描等。
例如，如图1所示，输入电路110与输入端IN连接，且配置为响应于输入端IN输入的输入信号对第一节点P1的电平进行控制。例如，在一些示例中，输入电路110与输入端IN、第一时钟信号端CK和第一节点P1连接，配置为在第一时钟信号端CK提供的第一时钟信号的控制下导通，使得输入端IN和第一节点P1连接，从而使输入端IN提供的输入信号被输入到第一节点P1，将第一节点P1的电位充电至工作电位(例如，可以使得与第一节点P1连接的晶体管导通的电位)。例如，在另一些示例中，输入电路110可以与输入端IN和第一节点P1连接，配置为在输入端IN提供的输入信号的控制下导通，使输入端IN和第一节点P1连接，从而使输入端IN提供的输入信号被输入到第一节点P1，将第一节点P1的电位上拉到工作电位。需要注意的是，只要满足在相应的阶段可以对第一节点P1进行充电即可，本公开的实施例对此不作限制。
例如，第一控制电路120与第一节点P1、第二节点P2和第一时钟信号端CK连接，且配置为在第一节点P1的电平和第一时钟信号端CK提供的第一时钟信号的控制下，对第二节点P2的电平进行控制。例如，在一些示例中，第一控制电路120与第一节点P1、第二节点P2、第二电压端VGL和第一时钟信号端CK连接，且配置为在第一节点P1的电平和第一时钟信号端CK提供的第一时钟信号的控制下导通，使得第二节点P2与第二电压端VGL连接以接收第二电压或者与第一时钟信号端CK连接以接收第一时钟信号，从而实现对第二节点P2的电平的控制。
例如，输出电路140与输出端OUT连接，且配置为在第二节点P2的电平的控制下， 在输出端OUT输出输出信号。例如，在一些示例中，该输出电路140与输出端OUT、第四节点P4、第一电压端VGH连接，且配置为第四节点P4的电平的控制下导通，使得第一电压端VGH提供的第一电压作为输出信号输出至输出端OUT。第四节点P4例如通过第三控制电路170与第二节点P2连接，即输出电路140间接与第二节点P2连接，即间接受第二节点P2的控制，从而也可以配置为第二节点P2的电平的控制下导通，使得第一电压端VGH提供的第一电压作为输出信号输出至输出端OUT。
需要注意的是，在本公开的实施例中，“在第二节点的电平的控制下”可以表示第二节点间接控制输出电路，即输出电路的导通与否可以和与第二节点的电平相关的其他电路(例如，第三控制电路)输出的电平(即第四节点P4的电平)的控制，当然也可以直接受第二节点P2的电平控制，本公开的实施例对此不作限制。下面的实施例与此类似，不再赘述。
例如，输出降噪电路130与输出端OUT连接，且配置为在第一节点P1的电平的控制下，对输出端OUT降噪。例如，在一些示例中，输出降噪电路130与第二电压端VGL第三节点P3和输出端OUT连接，且配置为在第三节点P3的电平的控制下导通时，使得输出端OUT和第二电压端VGL连接，从而可以利用第二电压VGL对输出端OUT进行下拉(例如，放电)，以实现降噪。第三节点P3例如通过第二控制电路160与第一节点P1连接，即输出降噪电路130间接与第一节点P1连接，即间接受第一节点P1的控制，从而也可以配置为第一节点P1的电平的控制下导通，使得第二电压端VGL提供的第二电压输出至输出端OUT，以实现降噪。
复位电路150与总复位端RST和第一电压端VGH连接，且配置为响应于总复位端RST提供的总复位信号，使得输出降噪电路130截止。例如，总复位信号在第一操作阶段为无效电平，在第二操作阶段包括至少一段有效电平(例如，使得晶体管导通的电平)。例如，复位电路150与第三节点P3、总复位端RST和第一电压端VGH连接，且配置为响应于总复位端RST提供的总复位信号，使得第一电压端VGH与第三节点P3连接，以对第三节点P3进行复位，从而使得输出降噪电路130响应于第三节点P3的电平截止。
例如，在第二操作阶段，即消隐阶段，总复位信号包括至少一段有效电平，从而可以使得复位电路150在消隐阶段响应总复位信号的至少一段有效电平导通，对第三节点P3至少一次复位至第一电压，使得输出降噪电路130响应于第三节点P3的电平至少一次截止，从而可以避免输出降噪电路130中包括的晶体管在消隐阶段长时间连续导通而影响晶体管的性能以影响输出降噪电路130输出复位和去噪能力，从而可以延长电路的使用寿命，保证显示面板的显示质量。
需要注意的是，在第一操作阶段，即显示阶段，输出降噪电路中的晶体管不会一直导通，例如，在显示阶段中输出电路输出输出信号的阶段，该输出降噪电路截止，因此，在该显示阶段，该复位信号为无效电平，从而可以保证移位寄存器单元的正常工作。
例如，如图1所示，该移位寄存器单元10还包括第二控制电路160，例如，该第二控制电路160与第一节点P1、第三节P3和第二时钟信号端CB连接，且配置为在第一节点P1 的电平和第二时钟信号端CB提供的第二时钟信号的控制下，对第三节点P3的电平进行控制。例如，在一些示例中，该第二控制电路160与第一节点P1、第三节P3和第二时钟信号端CB连接，且配置为在第一节点P1的电平控制下，使得第三节点P3和第二时钟信号端CB连接，以将第二时钟信号端CB提供的第二时钟信号提供至第三节点P3，从而实现对第三节点P3的电平进行控制。
例如，在该示例中，输出降噪电路130还与第三节点P3连接，且配置为响应于第三节点P3的电平，在输出端OUT输出输出信号的无效电平(例如，使得晶体管截止的电平)。例如，复位电路还与所述第三节点P3连接，且配置为响应于总复位端RST提供的总复位信号，对第三节点P3进行复位，以使得输出降噪电路130截止。具体介绍可参开上面关于输出降噪电路130和复位电路150的介绍，在此不再赘述。
例如，如图1所示，在另一些示例中，该移位寄存器单元10还包括第三控制电路170，第三控制电路170与第二节点P2、第四节点P4和第二时钟信号端CB连接，且配置为在第二节点P2的电平和第二时钟信号端CB提供的第二时钟信号的控制下，对第四节点P4的电平进行控制。例如，在一些示例中，该第三控制电路170与第二节点P2、第四节点P4和第二时钟信号端CB连接，且配置为在第二节点P2的电平和第二时钟信号端CB提供的第二时钟信号控制下，使得第四节点P4和第二节点P2连接，以将第二节点P2的电平提供至第四节点P4，从而实现对第四节点P4的电平进行控制。
图2为本公开至少一实施例提供的另一种移位寄存器单元的示意框图。例如，如图2所示，第二控制电路160包括第一子电路161；例如，第一子电路161与第一节点P1、第二时钟信号端CB和第三节点P3连接，且配置为在第一节点P1的电平的控制下，控制第三节点P3的电平。例如，在一些示例中，第一子电路161与第一节点P1、第二时钟信号端CB和第三节点P3连接，且配置为在第一节点P1的电平的控制下，使得第二时钟信号端CB与第三节点P3连接，从而控制第三节点P3的电平。
图3为本公开至少一实施例提供的另一种移位寄存器单元的示意框图。例如，如图3所示，第二控制电路160还包括第二子电路162；第二子电路162与第二电压端VGL、第一节点P1和第一控制节点P11连接，且配置为响应于第二电压端VGL提供的第二电压，控制第一控制节点P11的电平；第一子电路161还与第一控制节点P11连接，且配置为响应于第一控制节点P11的电平，控制第三节点P3的电平。例如，在一些示例中，第二子电路162响应于第二电压端VGL提供的第二电压导通，使得第一节点P1和第一控制节点P11连接，从而使得第一控制节点P11的电平与第一节点P1的电平相同；在该示例中，第一子电路161响应于第一控制节点P11的电平导通，使得第二时钟信号端CB与第三节点P3连接，从而控制第三节点P3的电平。
图4为本公开至少一实施例提供的另一种移位寄存器单元的示意框图。例如，如图4所示，第二控制电路160还包括第六子电路163。例如，第六子电路163与第二控制节点P21、第一电压端VGH和第一子电路161连接，且配置为响应于第二控制节点P21的电平，控制 第一控制节点P11的电平保持稳定。例如，在一些示例中，第六子电路163响应于第二控制节点P21的电平导通，使得第一电压端VGH与第一子电路161连接，从而可以避免与第一子电路161连接的第二时钟信号端CB提供的第二时钟信号变化时对第一控制节点P11的电平产生影响，从而影响移位寄存器单元的正常工作。
图5为本公开至少一实施例提供的另一种移位寄存器单元的示意框图。例如，如图5所示，第三控制电路包括第三子电路171和第四子电路172；第三子电路171与第二时钟信号端CB和第二控制节点P21连接，且配置为在第二节点P2的电平的控制下，控制第二控制节点P21的电平；第四子电路172与第二时钟信号端CB、第二控制节点P21和第四节点P4连接，且配置为响应于第二时钟信号端CB提供的第二时钟信号，控制第四节点P4的电平。例如，在一些示例中，第三子电路171在第二节点P2的电平的控制下导通，使得第二时钟信号端CB与第二控制节点P21连接，从而将第二时钟信号端CB提供的第二时钟信号提供至第二控制节点P21，以控制第二控制节点P21的电平；第四子电路172响应于第二时钟信号端CB提供的第二时钟信号导通，使得第二控制节点P21与第四节点P4连接，从而将第二控制节点P21的电平输入至第四节点P4，以控制第四节点P4的电平。
图6为本公开至少一实施例提供的另一种移位寄存器单元的示意框图。例如，如图6所示，第三控制电路170还包括第五子电路173，例如，第三子电路173与第二电压端VGL、第二节点P2和第三控制节点P31连接，且配置为响应于第二电压端VGL提供的第二电压，控制第三控制节点P31的电平；第三子电路173还与第三控制节点P31连接，且配置为响应于第三控制节点P31的电平，控制第二控制节点P21的电平。例如，在一些示例中，第五子电路173响应于第二电压端VGL提供的第二电压导通，将第二节点P2的电平输入至第三控制节点P31，以控制第三控制节点P31的电平；在该示例中，第三子电路173配置为响应于第三控制节点P31的电平导通，使得第二时钟信号端CB与第二控制节点P21连接，从而将第二时钟信号端CB提供的第二时钟信号提供至第二控制节点P21，以控制第二控制节点P21的电平。
图7为本公开至少一实施例提供的另一种移位寄存器单元的示意框图。例如，如图7所示，在图6所示的示例的基础上，该移位寄存器单元10还包括第四控制电路180。例如，第四控制电路180与第一节点P1、第一电压端VGH和第四节点P4连接，且配置为响应于第一节点P1的电平，对第四节点P4的电平进行控制。例如，在一些示例中，该第四控制电路180响应于第一节点P1的电平导通，使得第一电压端VGH与第四节点P4连接，从而将第一电压端VGH提供的第一电压输入至第四节点P4，以实现对第四节点P4的电平进行控制。
例如，如图7所示，该移位寄存器单元10还包括第五控制电路190。例如，第五控制电路190与第二控制节点P21、第三节点P3和第一电压端VGH连接，且配置为响应于第二控制节点P21的电平，对第三节点P3的电平进行控制。例如，在一些示例中，第五控制电路190配置为响应于第二控制节点P21的电平导通，使得第三节点P3与第一电压端VGH 连接以接收第一电压，从而实现对第三节点P3的电平进行控制。
图8为本公开至少一实施例提供的另一种移位寄存器单元的示意框图。例如，如图8所示，在图7所示的示例的基础上，该移位寄存器单元还包括第六控制电路200，例如，第六控制电路200与总复位端RST、第一电压端VGH和第一节点P1连接，且配置为在总复位端RST提供的复位信号的控制下，对第一节点P1进行复位。例如，在一些示例中，第六控制电路200配置为响应于总复位端RST提供的复位信号导通，使得第一节点P1与第一电压端VGH连接以接收第一电压，从而实现对第一节点P1进行复位。
例如，在该示例中，在消隐阶段，当复位信号为有效电平时，复位第一节点P1，从而使得第一控制电路120、第二控制电路160和第四控制电路180截止，使得其包括的晶体管T2、T4、T5和T8(如图9所示)短时恢复，从而可以进一步稳定移位寄存器单元的状态，延长电路的使用寿命。
本领域技术人员可以理解，尽管图1-图8中示出了多个控制电路和多个复位电路，然而上述示例并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不使用上述各电路中的一个或多个，基于前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
在图7所示的移位寄存器单元不包括第六子电路163时，图9为图7所示的移位寄存器单元在一些示例中的具体实现方式的电路图，在本公开的一些实施例中，图7中所示的移位寄存器单元10可以实现为图9所示的电路结构。如图9所示，该移位寄存器单元10包括：输入晶体管M1至第十控制晶体管M14、第三控制电容C1、输出电容C2、输出降噪电容C3以及第一控制电容C4。需要说明的是，在图9中所示的晶体管均以P型晶体管为例进行说明，本公开的实施例对此不作限制，例如移位寄存器单元10中的至少部分晶体管也可以采用N型晶体管。
在图7所示的移位寄存器单元包括第六子电路163时，图10为图7所示的移位寄存器单元在一些示例中的具体实现方式的电路图，即在图9所示的示例的基础上，还包括第四控制晶体管T16。下面结合图9和图10对图7所示的移位寄存器单元的具体实现方式进行详细地介绍。
例如，如图9所示，该输入电路110包括输入晶体管T1，输入晶体管T1的栅极和第一时钟信号端CK连接以接收第一时钟信号，输入晶体管T1的第一极和输入端IN连接以接收输入信号，输入晶体管T1的第二极和第一节点P1连接。
例如，在另一些实施例中，输入晶体管T1的栅极和第一极也可以均与输入端IN连接以接收输入信号，从而在响应于输入信号导通时，将输入信号输入至第一节点P1。
例如，如图9所示，复位电路150包括复位晶体管T12，复位晶体管T12的栅极与总复位端RST连接以接收总复位信号，复位晶体管T12的第一极和第一电压端VGH连接以接收第一电压，复位晶体管T12的第二极和第三节点P3连接。
例如，输出降噪电路130包括输出降噪晶体管T10，输出降噪晶体管T10的栅极和第 三节点P3连接，输出降噪晶体管T10的第一极和第二电压端VGL连接以接收第二电压，输出降噪晶体管T10的第二极和输出端OUT连接。
例如，输出降噪电路130还包括输出降噪电容C3，输出降噪电容C3的第一极和第二电压端VGL连接以接收第二电压，输出降噪电容C3的第二极和第三节点P3连接。
例如，在一些示例中，输出降噪电路130也可以不包括输出降噪电容C3，如图14所示，通过输出降噪晶体管T10的寄生电容C31充当输出降噪电容C3，由于输出降噪晶体管T10的尺寸比较大，本身的寄生电容C31也比较大，因此寄生电容C31可以充当输出降噪电容C3，例如，寄生电容C31的电容值小于等于输出降噪电容的电容值，输出降噪电路130的电容值降低可以提高复位速度，对第三节点P3的复位的速度也会变快，并且可以增大输出晶体管T10的阈值电压Vth的波动余量，有利于延长移位寄存器单元的使用寿命；同时还可以减少移位寄存器单元的占用面积和尺寸，有利于实现窄边框。
例如，如图9所示，输出电路140包括输出晶体管T9和输出电容C2；例如，输出晶体管T9的栅极和第四节点P4连接，输出晶体管T9的第一极和输出端OUT连接，输出晶体管T9的第二极和第一电压端VGH连接以接收第一电压；输出电容C2的第一极和第四节点P4连接，所述输出电容的第二极和所述第一电压端VGH连接以接收所述第一电压。
例如，如图9所示，第一子电路161包括第一控制晶体管T4、第二控制晶体管T5和第一控制电容C4；第一控制晶体管T4的栅极和第一控制节点P11连接，第一控制晶体管T4的第一极和第二时钟信号端CB连接以接收第二时钟信号，第一控制晶体管T4的第二极和第一控制电容C4的第一极连接；第一控制电容C4的第二极和第一控制节点P11连接；第二控制晶体管T5的栅极和第一极彼此连接，且均与第一控制节点P11连接，第二控制晶体管T5的第二极和第三节点P3连接。
例如，第二子电路162包括第三控制晶体管T13，第三控制晶体管T13的栅极和第二电压端VGL连接，第三控制晶体管T13的第一极和第一节点P1连接，第三控制晶体管T13的第二极和第一控制节点P11连接。
例如，如图10所示，第六子电路163包括第四控制晶体管T16；第四控制晶体管T16的栅极和第二控制节点P21连接，第四控制晶体管T16的第一极和第一电压端VGH连接以接收第一电压，第四控制晶体管T16的第二极和第一控制电容C4的第一极连接,，从而可以在第二控制节点P21为有效电平时，使得第一控制电容C4的第一极的电压稳定在第一电压，避免因与第一控制晶体管T4连接的第二时钟信号端CB提供的第二时钟信号的电平发生跳变时，由于第一控制电容C4的电荷守恒原理，使得第一控制节点P11的电平随第二时钟信号的跳变而跳变，从而避免第二时钟信号端CB对第一控制节点P11的电平产生影响，进而影响输出降噪晶体管T10的漏电，减少输出高电平时的噪声。
例如，如图9所示，第一控制电路120包括第六控制晶体管T2和第七控制晶体管T3；第六控制晶体管T2的栅极和第一节点P1连接，第六控制晶体管T2的第一极和第一时钟信号端CK连接以接收第一时钟信号，第六控制晶体管T2的第二极和第一节点P1连接；第 七控制晶体管T3的栅极和第一时钟信号端CK连接以接收第一时钟信号，第七控制晶体管T3的第一极和第二电压端VGL连接以接收第二电压，第七控制晶体管T3的第二极和第二节点P2连接。
例如，如图9-11所示，第三子电路171包括第八控制晶体管T6和第三控制电容C1，所述第四子电路包括第九控制晶体管T7，第五子电路包括第十控制晶体管T14；第十控制晶体管T14的栅极和第二电压端VGL连接以接收第二电压，第十控制晶体管T14的第一极和第二节点P2连接，第十控制晶体管T14的第二极和第三控制节点P31连接；第三控制电容C1的第一极和第三控制节点P31连接，第三控制电容C1的第二极和第二控制节点P21连接；第八控制晶体管T6的栅极和第三控制节点P31连接，第八控制晶体管T6的第一极和第二时钟信号端CB连接以接收第二时钟信号，第八控制晶体管T6的第二极和第二控制节点P21连接；第九控制晶体管T7的栅极和第二时钟信号端CB连接以接收第二时钟信号，第九控制晶体管T7的第一极和第二控制节点P2连接，第九控制晶体管T9的第二极和第四节点P4连接。
例如，第三控制晶体管T13以降低第一控制节点P11漏电，第十控制晶体管T14可以降低第三控制P31漏电，从而使得栅极驱动信号输出的响应速度更快。
例如，第四控制电路180包括第十一控制晶体管T8，第十一控制晶体管T8的栅极和第一节点P1连接，第十一控制晶体管T8的第一极和第四节点P4连接，第十一控制晶体管T8的第二极和第一电压端VGH连接以接收第一电压。
例如，第五控制电路190包括第十二控制晶体管T11，第十二控制晶体管T11的栅极和第二控制节点P21连接，第十二控制晶体管T11的第一极和第三节点P3连接，第十二控制晶体管P21的第二极和第一电压端VGH连接以接收第一电压。
图11为图8所示的移位寄存器单元在一些示例中的具体实现方式的电路图，在本公开的一些实施例中，图8中所示的移位寄存器单元10可以实现为图11所示的电路结构。如图11所示，在图9所示示例的基础上，该移位寄存器单元10还包括：第五控制晶体管T15。需要说明的是，在图11所示的电路结构和图9所示的电路结构基本相同，具体介绍可参考图9中的介绍，在此不再赘述。
例如，如图11所示，第六控制电路200包括第五控制晶体管T15；第五控制晶体管T15的栅极和总复位端RST连接以接收总复位信号，第五控制晶体管T15的第一极和第一电压端VGH连接以接收第一电压，第五控制晶体管T15的第二极和第一节点P1连接。
图12为图2所示的移位寄存器单元在一些示例中的具体实现方式的电路图，在本公开的一些实施例中，图2中所示的移位寄存器单元10可以实现为图12所示的电路结构。如图12所示，在图9所示示例的基础上，该移位寄存器单元10的第二控制电路160仅包括第一子电路，即，在图9所示的示例的基础上，不包括第三控制晶体管T13。需要说明的是，图12所示的电路结构和图9所示的电路结构基本相同，具体描述可参考图9中的介绍，在此不再赘述。
图13为图5所示的移位寄存器单元在不包括第二子电路和第六子电路时的具体实现方式的电路图，在本公开的一些实施例中，图5中所示的移位寄存器单元10在不包括第二子电路和第六子电路时可以实现为图13所示的电路结构。如图13所示，在图9所示示例的基础上，该移位寄存器单元10的第二控制电路160仅包括第一子电路，第三控制电路170仅包括第第三子电路和第四子电路，即，在图9所示的示例的基础上，不包括第三控制晶体管T13和第十控制晶体管T14，在该示例中，不仅不影响移位寄存器单元的功能，还有利于实现窄边框。需要说明的是，图13所示的电路结构和图9所示的电路结构基本相同，具体描述可参考图9中的介绍，在此不再赘述。
如前所述，在本公开的实施例提供的移位寄存器单元10中，可以利用第三控制电容C1维持第二控制节点P21处的电位，利用输出电容C2维持第四节点P4处的电位，利用输出降噪电容C3或寄生电容C31维持第三节点P3处的电位，利用第一控制电容C4维持第一控制节点P11处的电位。第三控制电容C1、输出电容C2、输出降噪电容C3和第一控制电容C4可以是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，或者在一些示例中，通过设计电路布线参数使得第三控制电容C1、输出电容C2、输出降噪电容C3和第一控制电容C4也可以通过各个器件之间的寄生电容实现。第三控制电容C1、输出电容C2、输出降噪电容C3和第一控制电容C4的连接方式不局限于上面描述的方式，也可以为其他适用的连接方式，只要能存储写入到第二控制节点P21、第四节点P4、第三节点P3和第一控制节点P11的电平即可。
需要说明的是，在本公开的一些实施例中，VGH即表示第一电压端又表示第一电压，VGL即表示第二电压端又表示第二电压。第一电压VGH例如为高电平，第二电压VGL例如为低电平，例如，第一电压VGH大于第二电压VGL，以下各实施例与此相同，不再赘述。
另外，需要说明的是，在本公开的一些实施例中，高电平和低电平是相对而言的。高电平表示一个较高的电压范围(例如，高电平可以采用5V、10V或其他合适的电压)，且多个高电平可以相同也可以不同。类似地，低电平表示一个较低的电压范围(例如，低电平可以采用0V、-5V、-10V或其他合适的电压)，且多个低电平可以相同也可以不同。例如，高电平的最小值比低电平的最大值大。
需要说明的是，在本公开的一些实施例中，对一个节点(例如第一节点P1等)的电平进行控制，包括对该节点进行充电以拉高该节点的电平，或者对该节点进行放电以拉低该节点的电平。例如，可以设置一个与该节点电连接的电容(例如，上述电容C1-C4)，对该节点进行充电即表示对与该节点电连接的电容进行充电；类似地，对该节点进行放电即表示对与该节点电连接的电容进行放电；通过该电容可以维持该节点的高电平或低电平。
需要说明的是，CK即表示第一时钟信号端又表示第一时钟信号，CB即表示第二时钟信号端又表示第二时钟信号，以下实施例与此相同，不再赘述。
在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。
又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。
需要注意的是，在本公开的各个实施例的说明中，第一节点P1、第二节点P2、第三节点P3、第四节点P4、第一控制节点P11、第二控制节点P21和第三控制节点P31并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，截止电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，截止电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。
另外，本公开的实施例中的晶体管均以P型晶体管为例进行说明，此时，晶体管的第一极是漏极，第二极是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元10中的一个或多个晶体管也可以采用N型晶体管，此时，晶体管第一极是源极，第二极是漏极，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电平或低电平即可。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法。图15A示出了图14所示的移位寄存器单元10工作时的信号时序图。
例如，如图15A所示，该驱动方法包括第一操作阶段S1和第二操作阶段S2；在所第一操作阶段S1，该驱动方法包括第一子阶段t1、第二子阶段t2和第三子阶段t3。一帧包括第一操作阶段S1(即显示阶段)和第二操作阶段S2(即，消隐阶段)，显示阶段用于驱动显示面板显示，消隐阶段为当前帧的显示阶段和下一帧的显示阶段之间的阶段。图15A所示 的信号时序图中的信号电平只是示意性的，不代表真实电平值。
在第一子阶段t1，输入电路110响应于输入端IN输入的输入信号的有效电平，对第一节点P1的电平进行控制；第一控制电路120在第一节点P1的电平和第一时钟信号端CK提供的第一时钟信号的控制下，对第二节点P2的电平进行控制。
在第二子阶段t2，输出电路140在第二节点P2的电平的控制下，在输出端OUT输出输出信号。
在第三子阶段t3，输出降噪电路130在第一节点P1的电平的控制下，对输出端OUT降噪。
在另一些示例中，该驱动方法还包括第四子阶段t4、第五子阶段t5和第六子阶段t6。
下面结合图15A和图14对本公开至少一实施例提供的移位寄存器单元10的工作方法进行详细地描述。例如，第一子阶段t1为输入阶段t1、第二子阶段t2为输出阶段t2和第三子阶段t3为复位阶段t3，第四子阶段t4为第一保持时间段t4、第五子阶段t5为第二保持时间段t5，第六子阶段t6为第三保持时间段t6。在第一操作阶段S1，总复位信号端RST提供高电平，复位晶体管T12响应于该总复位信号的高电平截止。
在输入阶段t1，第一时钟信号端CK提供低电平，第二时钟信号端CB提供高电平，输入端IN提供高电平，输入晶体管T1响应于第一时钟信号的低电平导通，第三控制晶体管T13响应于第二电压端VGL提供的第二电压导通，第一节点P1的电位为高电平，第一控制节点P11的电位为高电平，第一控制晶体管T4和第二控制晶体管T5响应于第一控制节点P11的高电平均截止；第六控制晶体管T2响应于第一节点P1的高电平截止，第七控制晶体管T3响应于第一时钟信号的低电平导通，第十控制晶体管T14响应于第二电压端VGL提供的第二电压导通，第二节点P2的电位为低电平，第三控制节点P31的电位为低电平，第八控制晶体管T6响应于第三控制节点P31的低电平导通，第二控制节点P21的电位为高电平，第九控制晶体管T7响应于第二时钟信号的高电平截止，第八控制晶体管T8响应于第一节点的高电平截止，第十二控制晶体管T11响应于第二控制节点P21的高电平截止，第三节点P3的电位维持为高电平，第四节点P4的电位维持为高电平，输出降噪晶体管T10响应于第三节点的高电平截止，第九晶体管T9响应于第四节点P4的低电平截止，输出端OUT输出低电平。
在输出阶段t2，第一时钟信号端CK提供高电平，第二时钟信号端CB提供低电平，输入端IN提供低电平，输入晶体管T1截止，第三控制晶体管T13导通，第一节点P1和第一控制节点P11的电位维持为高电平；第一控制晶体管T4截止，第二控制晶体管T5截止，第六控制晶体管T2和第七控制晶体管T3截止，第二节点P2的电位维持为低电平，第八控制晶体管T6导通，将第二时钟信号端CB提供的低电平输入至第二控制节点P21，第二控制节点P21由高电平变为低电平，根据第三控制电容C1的电荷守恒原理，第三控制节点P31的电位被第三控制电容C1进一步拉低，第九控制晶体管T7导通，第八控制晶体管T8截止，第十二控制晶体管T11响应于第二控制节点P21的低电平导通，第四节点P4的电位 为低电平，第三节点P3的电位依然为高电平，因此，第九晶体管T9导通，输出降噪晶体管T10截止，输出端OUT输出第一电压端VGH提供的高电平。
在复位阶段t3，第一时钟信号端CK提供低电平，第二时钟信号端CB提供高电平，输入端IN提供低电平，输入晶体管T1导通，第一节点P1的电位被拉低，第三控制晶体管T13导通，第一控制节点P11的电位被拉低，第二控制晶体管T5导通，第三节点P3的电位被拉低；输出降噪晶体管T10响应于第三节点P3的电平导通，将第二电压端VGL提供的第二电压输出至输出端OUT，输出端OUT输出低电平，从而实现对输出端OUT的降噪；第六控制晶体管T2和第七控制晶体管T3导通，第二节点P2的电位为低电平，第十控制晶体管T14导通，第八控制晶体管T6导通，第二控制节点P21变为第二时钟信号端CB提供的高电平，第三控制节点P3的电位根据第三控制电容的电荷守恒原理被拉高，第九控制晶体管T7截止；第八控制晶体管T8响应于第一节点的低电平导通，并第四节点P4的电位被拉高，第九晶体管T9截止。
在保持阶段包括的第一保持时间段t4，第一时钟信号端CK提供高电平，第二时钟信号端CB提供低电平，输入端IN提供低电平，输入晶体管T1截止，第一节点P1的电位维持为低电平，第三控制晶体管T13导通，第一控制晶体管T4导通，第二时钟信号端CB通过第一控制电容C4拉低第一控制节点P11的电位，第二控制晶体管T5导通，进而使得第三节点P3的电位维持为低于VGL+Vth，Vth为输出降噪晶体管T10的阈值电压，使得输出降噪晶体管T10开启，进而使得输出端OUT输出的栅极驱动信号的电位维持为第二电压，即维持在低电平，不受噪声干扰影响；第七控制晶体管T3截止，第六控制晶体管T2导通，第二节点P2的电位为第一时钟信号端CK提供的高电平，第十控制晶体管T14导通，第三控制节点P31的电位为高电平，第二控制节点P21的电位为高电平，第九控制晶体管T7导通，第八控制晶体管T8导通，第四节点P4的电位为高电平，第九晶体管T9截止。
在保持阶段包括的第二保持时间段t5，第一时钟信号端CK提供低电平，第二时钟信号端CB提供高电平，输入端IN提供低电平，输入晶体管T1导通，第一节点P1的电位为低电平，第三控制晶体管T13导通，第一控制节点P11为低电平，第一控制晶体管T4响应于第一控制节点P11的低电平导通，第二时钟信号端CB提供的输入时钟信号的电位升高，根据第一控制电容C4的电荷守恒原理，从而拉升第一控制节点P11的电位，第二控制晶体管T5截止，不影响第三节点P3的电位，使得第三节点P3的电位维持为低于VGL+Vth，Vth为输出降噪晶体管T10的阈值电压，使得输出降噪晶体管T10开启，进而使得输出端OUT输出的栅极驱动信号的电位维持为第二电压，即低电平，不受噪声干扰影响；第七控制晶体管T3导通，第二节点P2的电位为低电平，第六控制晶体管T2导通，第十控制晶体管T14导通，第三控制节点P31的电位为低电平，第八控制晶体管T6导通，第二控制节点P21的电位为高电平，第九控制晶体管T7截止，第八控制晶体管T8截止，第四节点P4的电位保持为高电平，第九晶体管T9截止。
在保持阶段包括的第三保持时间段t6，第一时钟信号端CK提供高电平，第二时钟信号 端CB提供低电平，输入端IN提供低电平，输入晶体管T1截止，第一节点P1的电位维持为低电平，第一控制晶体管T4导通，第二时钟信号端CB通过第一控制电容C4拉低第一控制节点P11的电位，第二控制晶体管T5导通，进而使得第三节点P3的电位维持为低于VGL+Vth，Vth为输出降噪晶体管T10的阈值电压，使得输出降噪晶体管T10开启，进而使得输出端OUT输出的栅极驱动信号的电位维持为第二电压，即低电平，不受噪声干扰影响；第七控制晶体管T3截止，第六控制晶体管T2导通，第二节点P2的电位为高电平，第十控制晶体管T14导通，第三控制节点P31的电位为高电平，第八控制晶体管T6截止，第二控制节点P21的电位为高电平，第九控制晶体管T7导通，第八控制晶体管T8导通，第四节点P4的电位为高电平，第九晶体管T9截止。
在保持阶段，第三节点P1的电位可以维持为低于VGL+Vth，Vth为输出降噪晶体管T10的阈值电压，使得输出降噪晶体管T10开启，进而使得输出端OUT输出的栅极驱动信号的电位维持为第二电压，不受噪声干扰影响。
在图9-14所示的移位寄存器单元中，第一控制晶体管T4、第一控制电容C4、第二控制晶体管T5组成电荷泵结构，电荷泵是电路中一种类似水泵的结构，主要通过电容、时钟信号和二极管整流结构(在图9-14中，第二控制晶体管T5采用二极管连接方式)，实现对电荷的再分配，实现升压(或降压)的目的。
例如，如图15A所示，在第二操作阶段S2，该移位寄存器单元的驱动方法包括至少一个复位阶段t7。图15A中仅示出了1个复位阶段t7，本公开的实施例对此不作限制。
例如，在至少一个复位阶段t7，向总复位端RST施加总复位信号的有效电平(例如，低电平)，向第一时钟信号端CLK施加第一时钟信号的无效电平(例如，高电平)。复位电路150响应于总复位信号的有效电平，使得输出降噪电路130截止。
例如，在移位寄存器单元10还包括第二控制电路160的情形下，第二控制电路160与第一节点P1、第三节点P3和第二时钟信号端CB连接，且配置为在第一节点P1的电平和第二时钟信号端CB提供的第二时钟信号的控制下，对第三节点P3的电平进行控制；输出降噪电路130还与第三节点P3连接，且配置为响应于第三节点P3的电平，在输出端OUT输出输出信号的无效电平；复位阶段t7还包括：向第二时钟信号端CB施加第二时钟信号的无效电平，复位电路150响应于总复位信号的有效电平，对第三节点P3进行复位，以使得输出降噪电路130响应于第三节点P3的电平截止。
如图15A所示，在复位阶段t7，第一时钟信号端CK提供高电平，第二时钟信号端CB提供高电平，输入端IN提供低电平，总复位端RST提供低电平，输入晶体管T1截止，第一节点P1的电位维持为低电平，第三控制晶体管T13导通，第一控制节点P11为低电平，第一控制晶体管T4响应于第一控制节点P11的低电平导通，第二时钟信号端CB提供的输入时钟信号的电位升高，根据第一控制电容C4的电荷守恒原理，从而拉升第一控制节点P11的电位，第二控制晶体管T5截止，由于复位晶体管T12响应于总复位信号的低电平导通，使得第一电压端VGH与第三节点P3连接，从而拉高第三节点P3的电压，输出降噪晶 体管T10截止，使得输出降噪晶体管T10在该第二操作阶段S2的至少一个复位阶段t7截止，从而可以避免输出降噪晶体管T10在第二操作阶段S2一直导通而影响输出降噪电路130的输出复位和降噪能力，从而可以延长移位寄存器单元的使用寿命，提高显示面板的显示质量。在此阶段，第六控制晶体管T2导通，第七控制晶体管T3截止，使得第二节点P2与第一时钟信号端CK连接，第二节点P2的电位为第一时钟信号端CK高电平，第十控制晶体管T14导通，第三控制节点P31的电位为高电平，第八控制晶体管T6截止，第二控制节点P21的电位保持为高电平，第九控制晶体管T7截止，第八控制晶体管T8导通，第四节点P4的电位保持为高电平，第九晶体管T9截止。
需要注意的是，其他电路(例如，图9-10、12-13所示的电路)的驱动方法与图14所示电路的驱动方法类似，可参考图14和图15A中的驱动方法的描述，在此不再赘述。
图15B示出了图11所示的移位寄存器单元10工作时的信号时序图。参见图15所示，图11所示的移位寄存器单元的工作过程与图14所示的移位寄存器单元的工作过程类似，区别仅在于：在复位阶段t7，第五控制晶体管T15响应于复位信号的高电平导通，使得第一节点P1和第一电压端VGH连接，从而使得第一节点P1的电平为高电平，由于第三控制晶体管T13导通，使得第一控制节点P11和第一节点P1连接，从而使得第一控制节点P11的电平为高电平，其余过程可参考图15A的介绍，在此不再赘述。
本公开的至少一实施例还提供一种栅极驱动电路20，如图16所示，该栅极驱动电路20包括多个级联的移位寄存器单元10，其中任意一个或多个移位寄存器单元10可以采用本公开任一实施例提供的移位寄存器单元10的结构或其变型。
本公开至少一实施例还提供一种显示装置1，如图17所示，该显示装置1包括本公开实施例提供的栅极驱动电路20以及多个呈阵列排布的子像素单元410。例如，该显示装置1还包括显示面板40，多个子像素单元410构成的像素阵列设置在显示面板40中。
栅极驱动电路20中的每一个移位寄存器单元10中的输出端OUT分别和个行的子像素单元410电连接，例如，栅极驱动电路20通过栅线GL与子像素单元410电连接。栅极驱动电路20用于提供驱动信号至像素阵列，例如该驱动信号可以驱动子像素单元410中的扫描晶体管和感测晶体管。
例如，该显示装置1还可以包括数据驱动电路30，该数据驱动电路30用于提供数据信号至像素阵列。例如，数据驱动电路30通过数据线DL与子像素单元410电连接。
需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的实施例提供的显示装置1的技术效果可以参考上述实施例中关于栅极驱动电路20的相应描述，这里不再赘述。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常 设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (29)

  1. 一种移位寄存器单元，包括：输入电路、第一控制电路、输出电路、输出降噪电路和复位电路；其中，
    所述输入电路与输入端连接，且配置为响应于所述输入端输入的输入信号对第一节点的电平进行控制；
    所述第一控制电路与所述第一节点、第二节点和第一时钟信号端连接，且配置为在所述第一节点的电平和所述第一时钟信号端提供的第一时钟信号的控制下，对所述第二节点的电平进行控制；
    所述输出电路与输出端连接，且配置为在所述第二节点的电平的控制下，在所述输出端输出输出信号；
    所述输出降噪电路与所述输出端连接，且配置为在所述第一节点的电平的控制下，对所述输出端降噪；
    所述复位电路与总复位端和第一电压端连接，且配置为响应于所述总复位端提供的总复位信号，使得所述输出降噪电路截止，其中，所述总复位信号在第一操作阶段为无效电平，在第二操作阶段包括至少一段有效电平。
  2. 根据权利要求1所述的移位寄存器单元，还包括第二控制电路，其中，
    所述第二控制电路与所述第一节点、第三节点和第二时钟信号端连接，且配置为在所述第一节点的电平和所述第二时钟信号端提供的第二时钟信号的控制下，对所述第三节点的电平进行控制；
    所述输出降噪电路还与所述第三节点连接，且配置为响应于所述第三节点的电平，在所述输出端输出所述输出信号的无效电平。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述复位电路还与所述第三节点连接，且配置为响应于所述总复位端提供的总复位信号，对所述第三节点进行复位，以使得所述输出降噪电路截止。
  4. 根据权利要求2或3所述的移位寄存器单元，其中，所述第二控制电路包括第一子电路；
    所述第一子电路与所述第一节点、所述第二时钟信号端和所述第三节点连接，且配置为在所述第一节点的电平的控制下，控制所述第三节点的电平。
  5. 根据权利要求4所述的移位寄存器单元，其中，所述第二控制电路还包括第二子电路；
    所述第二子电路与第二电压端、所述第一节点和第一控制节点连接，且配置为响应于所述第二电压端提供的第二电压，控制所述第一控制节点的电平；
    所述第一子电路还与所述第一控制节点连接，且配置为响应于所述第一控制节点的电平，控制所述第三节点的电平。
  6. 根据权利要求2-5任一所述的移位寄存器单元，还包括第三控制电路，其中，所述第三控制电路与所述第二节点、第四节点和所述第二时钟信号端连接，且配置为在所述第二节点的电平和所述第二时钟信号端提供的第二时钟信号的控制下，对所述第四节点的电平进行控制。
  7. 根据权利要求6所述的移位寄存器单元，其中，所述第三控制电路包括第三子电路和第四子电路；
    所述第三子电路与所述第二时钟信号端和第二控制节点连接，且配置为在所述第二节点的电平的控制下，控制所述第二控制节点的电平；
    所述第四子电路与所述第二时钟信号端、所述第二控制节点和所述第四节点连接，且配置为响应于所述第二时钟信号端提供的第二时钟信号，控制所述第四节点的电平。
  8. 根据权利要求7所述的移位寄存器单元，其中，所述第三控制电路还包括第五子电路，
    所述第五子电路与第二电压端、所述第二节点和第三控制节点连接，且配置为响应于所述第二电压端提供的第二电压，控制所述第三控制节点的电平；
    所述第三子电路还与所述第三控制节点连接，且配置为响应于所述第三控制节点的电平，控制所述第二控制节点的电平。
  9. 根据权利要求8所述的移位寄存器单元，其中，所述第二控制电路还包括第六子电路，
    所述第六子电路与所述第二控制节点、第一电压端和所述第一子电路连接，且配置为响应于所述第二控制节点的电平，控制所述第一控制节点的电平保持稳定。
  10. 根据权利要求7-9任一所述的移位寄存器单元，还包括第四控制电路，其中，所述第四控制电路与所述第一节点、所述第一电压端和所述第四节点连接，且配置为响应于所述第一节点的电平，对所述第四节点的电平进行控制。
  11. 根据权利要求8或9所述的移位寄存器单元，还包括第五控制电路，其中，所述第五控制电路与所述第二控制节点、所述第三节点和所述第一电压端连接，且配置为响应于所述第二控制节点的电平，对所述第三节点的电平进行控制。
  12. 根据权利要求1-11任一所述的移位寄存器单元，还包括第六控制电路，其中，所述第六控制电路与所述总复位端、所述第一电压端和所述第一节点连接，且配置为在所述总复位端提供的复位信号的控制下，对所述第一节点进行复位。
  13. 根据权利要求1-12任一所述的移位寄存器单元，其中，所述输入电路包括输入晶体管，
    所述输入晶体管的栅极和所述第一时钟信号端连接以接收所述第一时钟信号，所述输入晶体管的第一极和所述输入端连接以接收所述输入信号，所述输入晶体管的第二极和所述第一节点连接。
  14. 根据权利要求3所述的移位寄存器单元，其中，所述复位电路包括复位晶体管，
    所述复位晶体管的栅极与所述总复位端连接以接收所述总复位信号，所述复位晶体管的第一极和所述第一电压端连接以接收第一电压，所述复位晶体管的第二极和所述第三节点连接。
  15. 根据权利要求3所述的移位寄存器单元，其中，所述输出降噪电路包括输出降噪晶体管，
    所述输出降噪晶体管的栅极和所述第三节点连接，所述输出降噪晶体管的第一极和第二电压端连接以接收第二电压，所述输出降噪晶体管的第二极和所述输出端连接。
  16. 根据权利要求15所述的移位寄存器单元，其中，所述输出降噪电路还包括输出降噪电容，
    所述输出降噪电容的第一极和所述第二电压端连接以接收所述第二电压，所述输出降噪电容的第二极和所述第三节点连接。
  17. 根据权利要求2-16任一所述的移位寄存器单元，其中，所述输出电路包括输出晶体管和输出电容；
    所述输出晶体管的栅极和所述第四节点连接，所述输出晶体管的第一极和所述输出端连接，所述输出晶体管的第二极和所述第一电压端连接以接收第一电压；
    所述输出电容的第一极和所述第四节点连接，所述输出电容的第二极和所述第一电压端连接以接收所述第一电压。
  18. 根据权利要求9所述的移位寄存器单元，其中，所述第一子电路包括第一控制晶体管、第二控制晶体管和第一控制电容；
    所述第一控制晶体管的栅极和所述第一控制节点连接，所述第一控制晶体管的第一极和所述第二时钟信号端连接以接收所述第二时钟信号，所述第一控制晶体管的第二极和所述第一控制电容的第一极连接；
    所述第一控制电容的第二极和所述第一控制节点连接；
    所述第二控制晶体管的栅极和第一极彼此连接，且均与所述第一控制节点连接，所述第二控制晶体管的第二极和所述第三节点连接。
  19. 根据权利要求18所述的移位寄存器单元，其中，所述第二子电路包括第三控制晶体管，
    所述第三控制晶体管的栅极和所述第二电压端连接，所述第三控制晶体管的第一极和所述第一节点连接，所述第三控制晶体管的第二极和所述第一控制节点连接。
  20. 根据权利要求18或19所述的移位寄存器单元，其中，所述第六子电路包括第四控制晶体管；
    所述第四控制晶体管的栅极和所述第二控制节点连接，所述第四控制晶体管的第一极和所述第一电压端连接以接收第一电压，所述第四控制晶体管的第二极和所述第一控制电容的第一极连接。
  21. 根据权利要求12所述的移位寄存器单元，其中，所述第六控制电路包括第五控制 晶体管；
    所述第五控制晶体管的栅极和所述总复位端连接以接收所述总复位信号，所述第五控制晶体管的第一极和所述第一电压端连接以接收第一电压，所述第五控制晶体管的第二极和所述第一节点连接。
  22. 根据权利要求1-21任一所述的移位寄存器单元，其中，所述第一控制电路包括第六控制晶体管和第七控制晶体管；
    所述第六控制晶体管的栅极和所述第一节点连接，所述第六控制晶体管的第一极和所述第一时钟信号端连接以接收所述第一时钟信号，所述第六控制晶体管的第二极和所述第二节点连接；
    所述第七控制晶体管的栅极和所述第一时钟信号端连接以接收所述第一时钟信号，所述第七控制晶体管的第一极和第二电压端连接以接收第二电压，所述第七控制晶体管的第二极和所述第二节点连接。
  23. 根据权利要求9所述的移位寄存器单元，其中，所述第三子电路包括第八控制晶体管和第三控制电容，所述第四子电路包括第九控制晶体管，所述第五子电路包括第十控制晶体管；
    所述第十控制晶体管的栅极和所述第二电压端连接以接收所述第二电压，所述第十控制晶体管的第一极和所述第二节点连接，所述第十控制晶体管的第二极和所述第三控制节点连接；
    所述第三控制电容的第一极和所述第三控制节点连接，所述第三控制电容的第二极和所述第二控制节点连接；
    所述第八控制晶体管的栅极和所述第三控制节点连接，所述第八控制晶体管的第一极和所述第二时钟信号端连接以接收所述第二时钟信号，所述第八控制晶体管的第二极和所述第二控制节点连接；
    所述第九控制晶体管的栅极和所述第二时钟信号端连接以接收所述第二时钟信号，所述第九控制晶体管的第一极和所述第二控制节点连接，所述第九控制晶体管的第二极和所述第四节点连接。
  24. 根据权利要求10所述的移位寄存器单元，其中，所述第四控制电路包括第十一控制晶体管，
    所述第十一控制晶体管的栅极和所述第一节点连接，所述第十一控制晶体管的第一极和所述第四节点连接，所述第十一控制晶体管的第二极和所述第一电压端连接以接收第一电压。
  25. 根据权利要求11所述的移位寄存器单元，其中，所述第五控制电路包括第十二控制晶体管，
    所述第十二控制晶体管的栅极和所述第二控制节点连接，所述第十二控制晶体管的第一极和所述第三节点连接，所述第十二控制晶体管的第二极和所述第一电压端连接以接收 第一电压。
  26. 一种栅极驱动电路，包括多个级联的如权利要求1-25任一所述的移位寄存器单元。
  27. 一种如权利要求1所述的移位寄存器单元的驱动方法，包括第一操作阶段和第二操作阶段；
    其中，在所述第一操作阶段，所述驱动方法包括第一子阶段、第二子阶段和第三子阶段：
    在所述第一子阶段，所述输入电路响应于所述输入端输入的输入信号的有效电平，对第一节点的电平进行控制；
    所述第一控制电路在所述第一节点的电平和所述第一时钟信号端提供的第一时钟信号的控制下，对所述第二节点的电平进行控制；
    在所述第二子阶段，所述输出电路在所述第二节点的电平的控制下，在所述输出端输出输出信号；
    在所述第三子阶段，所述输出降噪电路在所述第一节点的电平的控制下，对所述输出端降噪；
    在所述第二操作阶段，所述驱动方法包括至少一个复位阶段，
    在所述至少一个复位阶段，向所述总复位端施加总复位信号的有效电平，向所述第一时钟信号端施加所述第一时钟信号的无效电平，
    所述复位电路响应于所述总复位信号的有效电平，使得所述输出降噪电路截止。
  28. 根据权利要求27所述的驱动方法，其中，在所述移位寄存器单元还包括第二控制电路的情形下，其中，所述第二控制电路与所述第一节点、第三节点和第二时钟信号端连接，且配置为在所述第一节点的电平和所述第二时钟信号端提供的第二时钟信号的控制下，对所述第三节点的电平进行控制；
    所述输出降噪电路还与所述第三节点连接，且配置为响应于所述第三节点的电平，在所述输出端输出所述输出信号的无效电平；
    所述复位阶段还包括：向所述第二时钟信号端施加所述第二时钟信号的无效电平，
    所述复位电路响应于所述总复位信号的有效电平，对所述第三节点进行复位，以使得所述输出降噪电路响应于所述第三节点的电平截止。
  29. 一种显示装置，包括如权利要求26所述的栅极驱动电路。
PCT/CN2021/097512 2021-05-31 2021-05-31 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置 WO2022252092A1 (zh)

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