WO2022247369A1 - 一种高可靠性片内电源切换电路 - Google Patents

一种高可靠性片内电源切换电路 Download PDF

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Publication number
WO2022247369A1
WO2022247369A1 PCT/CN2022/077864 CN2022077864W WO2022247369A1 WO 2022247369 A1 WO2022247369 A1 WO 2022247369A1 CN 2022077864 W CN2022077864 W CN 2022077864W WO 2022247369 A1 WO2022247369 A1 WO 2022247369A1
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WIPO (PCT)
Prior art keywords
switch
power
low
terminal
output
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PCT/CN2022/077864
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English (en)
French (fr)
Chinese (zh)
Inventor
江向阳
林玲
王文泽
丁燕
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杭州万高科技股份有限公司
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Priority to KR1020227042860A priority Critical patent/KR20230100700A/ko
Publication of WO2022247369A1 publication Critical patent/WO2022247369A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/263—Arrangements for using multiple switchable power supplies, e.g. battery and AC
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the invention relates to a power switching circuit, in particular to a high-reliability on-chip power switching circuit.
  • the power structure of the main control chip is divided into two parts, one is the main power domain, and most functional modules such as CPU, storage, and peripherals are placed in this area; the other is the RTC power domain, which mainly houses the crystal oscillator clock, RTC modules, etc. circuit.
  • the main power domain In addition to entering the RTC-Only mode, the main power domain is always powered. When it is powered by the mains, it is powered by the mains. When there is no mains, it is switched to the battery. Usually, this switching is done outside the chip. Referring to Figure 3, in order to prevent backflow, the mains power (generally passed through the rectifier bridge and then converted by the LDO for power supply) and the battery are each connected in series with a diode to supply the chip power input VDD.
  • the mains power is higher than the battery voltage, so it will be powered by the mains under normal circumstances.
  • this structure also has an irreversible disadvantage, that is, the conduction voltage drop of the diode, which will significantly reduce the battery voltage. of durability.
  • the technical problem to be solved by the present invention is to provide a high-reliability on-chip power switching circuit for the deficiencies of the prior art.
  • the present invention discloses a high-reliability on-chip power switching circuit, including a power detection circuit, a low-power control module, a main power control module, a low-power power switch, a main power switch, Loads in low power consumption areas and loads in main power areas;
  • the input end of the power detection circuit is respectively connected to the mains power supply VDD and the battery power supply BATRTC, and detects the two kinds of power supplies;
  • the power detection circuit has two outputs, one of which is connected to the input terminal of the low-power control module, the output of the low-power control module is connected to the input terminal of the low-power switch, and the output of the low-power switch is connected to the low-power switch. consumption area load;
  • the other output of the power detection circuit is connected to the input end of the main power control module, the output of the main power control module is connected to the input end of the main power switch, and the output of the main power switch is connected to the load in the main power area.
  • the power detection circuit of the present invention includes a first resistor R0, a second resistor R1 and a comparator COMP;
  • the positive terminal of the first resistor R0 is connected to the commercial power supply VDD, and the negative terminal is connected to the positive input terminal of the comparator COMP;
  • the positive terminal of the second resistor R1 is connected to the battery power supply BATRTC, and the negative terminal is connected to the negative input terminal of the comparator COMP.
  • the low power consumption control module of the present invention includes a first inverter INV to generate a non-overlapping control signal;
  • the input end of the first inverter INV is connected to the output end of the comparator COMP, and the output end of the first inverter INV is connected to the low power consumption switch.
  • the main power control module of the present invention includes a two-phase non-overlapping timing generator S1, a second inverter INV1, and a third inverter INV2;
  • the input terminal of the two-phase non-overlapping timing generator S1 is connected to the output terminal LP_SEL of the comparator, and the output of the two-phase non-overlapping timing generator S1 is connected to the input terminals of the second inverter INV1 and the third inverter INV2 ;
  • the output end of the second inverter is connected to the third switch SW2;
  • the output end of the third inverter is connected to the fourth switch SW3.
  • the low power consumption power switching switch of the present invention includes a first switch SW0 and a second switch SW1;
  • the gate terminal of the first switch SW0 is connected to the output terminal of the comparator COMP, the source terminal of the first switch SW0 is connected to the battery power supply BATRTC, the substrate and the drain terminal of the first switch SW0 are connected to the low power consumption area load and the second switch SW1 The drain and substrate;
  • the gate terminal of the second switch SW1 is connected to the output terminal of the first inverter INV, and the source terminal of the second switch SW1 is connected to the commercial power supply VDD.
  • the switching switch of the main power supply in the present invention includes a third switch SW2 and a fourth switch SW3;
  • the gate terminal of the third switch SW2 is connected to the output terminal of the main power control module, the source terminal of the third switch SW2 is connected to the battery power supply BATRTC, and the substrate and drain terminal of the third switch SW2 are connected to the main power area load and the drain terminal of SW3 and Substrate;
  • the gate terminal of the fourth switch SW3 is connected to the main power control module, and the source terminal of the fourth switch SW3 is connected to the commercial power supply VDD.
  • the low power consumption area load of the present invention includes a minimum system working reference voltage generation circuit BGR, a low power consumption reference circuit LPVERF, a clock generation module CLK_GEN and a power-on reset POR module;
  • the load in the main power area includes a main voltage regulator MainLDO, an input and output IO, an analog-to-digital converter ADC and a phase-locked loop PLL module.
  • the first switch SW0 and the second switch SW1 in the present invention are MOS switches
  • the size of the first switch SW0 and the second switch SW1 is set according to the current, so that the on-resistance of the switches is the largest when the load in the low power consumption region works normally.
  • the control signals of the first switch SW0 and the second switch SW1 in the present invention are non-overlapping signals, which are generated by the low power consumption control module.
  • the first resistor R0 and the second resistor R1 are electrostatic protection ESD resistors to prevent the gate terminal of the comparator COMP from being damaged.
  • the high-reliability on-chip power switching circuit proposed by the present invention does not require external diodes for power switching, and the power switching circuit is completed in the chip, reducing BOM costs;
  • the high-reliability on-chip power switching circuit proposed by the present invention does not have an external diode, and the battery’s durability will not be reduced due to the voltage drop of the diode;
  • the internal high-current switch adopts non-overlapping control sequence to ensure that the high-current switches will not be turned on at the same time, avoiding the large current backflow of VDD to the battery, thereby avoiding the reduction of battery life , and the internal needs to be normally open, etc. to ensure that the smallest system part adopts an either-or design to ensure the reliability of internal conduction.
  • Fig. 1 is a schematic diagram of the circuit module of the present invention.
  • Fig. 2 is a schematic circuit diagram of the present invention.
  • FIG. 3 is a schematic diagram of a traditional power switching circuit.
  • FIG. 4 is a schematic diagram of an existing on-chip power switching circuit.
  • Fig. 5 is a schematic circuit diagram of the main electric control module.
  • the invention divides the system power supply into two voltage domains, a low power consumption area and a high power consumption area. Place the power switching module and modules such as the bandgap reference-BGR, power-on reset-POR, and RCOSC in the low power domain ), and put those high-power, power insensitive main voltage regulator (Main low dropout regulator-MAIN LDO), input and output PAD (Input/Output-IO), phase-locked loop (Phase Locked Loop-PLL) and other modules in the Main Power Domain.
  • the power switching module and modules such as the bandgap reference-BGR, power-on reset-POR, and RCOSC in the low power domain ), and put those high-power, power insensitive main voltage regulator (Main low dropout regulator-MAIN LDO), input and output PAD (Input/Output-IO), phase-locked loop (Phase Locked Loop-PLL) and other modules in the Main Power Domain.
  • the main power supply is input to VDD, and the battery is input to BATRTC to generate a low power consumption power supply VDDLP through MOS switches SW1 and SW0.
  • the size of the switch SW0 and the switch SW1 is designed according to the magnitude of the current.
  • control signals LP_SEL and LP_SELN of SW0 and SW1 are designed to be non-overlapping, so that no matter what the output result of the comparator COMP is, All the way power supply is selected.
  • R0 and R1 are ESD protection resistors to prevent the gate terminal (GATE) of the comparator COMP from being damaged.
  • the two-phase non-overlapping control signals LP_SEL and LP_SELN are directly generated by an inverter INV.
  • the above-mentioned generating circuit is only one implementation manner, and non-overlapping control logic can be generated in other implementation manners.
  • the comparator output LP_SEL is high level and LPSELN is low level, SW1 is turned on, SW0 is turned off, and the Low Power part is powered through VDD; when VDD ⁇ BATRTC, the comparator output is low, SW0 is turned on, SW1 is closed, and the Low Power part is powered through BATRTC. Because the two phases of LP_SEL and LP_SELN are non-overlapping, when the control logic changes, LP_SEL and LP_SELN are low at the same time, and SW0 and SW1 are turned on at the same time to ensure the reliability of the control logic.
  • the on-resistance of the switches SW0 and SW1 is relatively large, the current poured by the main power supply to the battery is relatively small, and the loss to the battery is relatively small. Because the current in the Mian area is relatively large, the design requires that the on-resistance of SW2 and SW3 be as small as possible. If SW2 and SW3 are turned on at the same time, a very large backflow current will be generated.
  • the function of Control Logic is to realize the two-phase overlapping clock, so that SW2 and SW3 will not be turned on at the same time, so as to avoid the large current backflow of VDD to BATRTC.
  • VDD>BATRTC the output of the comparator is high, SW3 is turned on, SW2 is turned off, and power is supplied to the Main Power part through VDD; Main Power is partially powered.
  • a high-reliability on-chip power switching circuit includes a power detection circuit, a low-power control module, a main power control module, a low-power power switch, a main power switch, and a low-power area Load and load in the main power area; wherein, the input terminals of the power detection circuit are respectively connected to the mains power supply VDD and the battery power supply BATRTC, and detect the two power sources; the power detection circuit has two outputs, one of which is connected to the low-power The input terminal of the control module and the output of the low-power control module are connected to the input terminal of the low-power power switch, and the output of the low-power switch is connected to the load in the low-power area; the other output of the power detection circuit is connected to the main power control The input end of the module and the output of the main power control module are connected to the input end of the main power switch, and the output of the main power switch is connected to the load in the main power area.
  • the power detection circuit includes a first resistor R0, a second resistor R1, and a comparator COMP; wherein, the positive terminal of the first resistor R0 is connected to the commercial power supply VDD, and the negative terminal is connected to the positive terminal of the comparator COMP. Input terminal; the positive terminal of the second resistor R1 is connected to the battery power supply BATRTC, and the negative terminal is connected to the negative input terminal of the comparator COMP.
  • the low power consumption control module includes a first inverter INV to generate a non-overlapping control signal; wherein, the input terminal of the first inverter INV is connected to the output terminal of the comparator COMP, and the output terminal of the first inverter INV Connect a low-power power toggle switch.
  • the main power control module includes a two-phase non-overlapping timing generator S1, a second inverter INV1 and a third inverter INV2; wherein, the input of the two-phase non-overlapping timing generator S1 terminal is connected to the output terminal LP_SEL of the comparator, the output SELN of the two-phase non-overlapping timing generator S1 is connected to the input terminal of the second inverter INV1, and the other output SEL of S1 is connected to the input terminal of the third inverter INV2;
  • the output terminal MAIN-SEL of the second inverter is connected to the third switch SW2; the output terminal MAIN-SELN of the third inverter is connected to the fourth switch SW3.
  • the low power consumption power switch includes a first switch SW0 and a second switch SW1; wherein, the gate terminal of the first switch SW0 is connected to the output terminal of the comparator COMP, the source terminal of the first switch SW0 is connected to the battery power supply BATRTC, and the first switch SW0 is connected to the battery power supply BATRTC.
  • the substrate and drain of the switch SW0 are connected to the load in the low power consumption area and the drain and the substrate of the second switch SW1; the gate of the second switch SW1 is connected to the output terminal LP_SELN of the first inverter INV, and the second switch SW1
  • the source terminal is connected to the commercial power supply VDD.
  • the main power supply switching switch includes a third switch SW2 and a fourth switch SW3; wherein the gate terminal of the third switch SW2 is connected to the output terminal of the main power control module, the source terminal of the third switch SW2 is connected to the battery power supply BATRTC, and the third switch SW2
  • the substrate and drain of SW2 are connected to the load in the main power area and the drain and substrate of SW3; the gate of the fourth switch SW3 is connected to the main power control module, and the source of the fourth switch SW3 is connected to the commercial power supply VDD.
  • the low-power area load includes the minimum system operating reference voltage generation circuit BGR, the low-power reference circuit LPVERF, the clock generation module CLK_GEN, and the power-on reset POR module;
  • the main power area load includes the main voltage regulator MainLDO, input and output IO, analog-to-digital converter ADC and phase-locked loop PLL module.
  • the first switch SW0 and the second switch SW1 are MOS switches; the size of the first switch SW0 and the second switch SW1 is set according to the current, so that the on-resistance of the switches is the largest when the load in the low power consumption region works normally.
  • the control signals of the first switch SW0 and the second switch SW1 are non-overlapping signals, which are generated by the low power consumption control module.
  • the first resistor R0 and the second resistor R1 in the circuit are electrostatic protection ESD resistors to prevent the gate terminal of the comparator COMP from being damaged.
  • the present invention provides an idea and method of a high-reliability on-chip power switching circuit. There are many methods and approaches for realizing the technical solution. The above description is only a preferred implementation mode of the present invention. Those of ordinary skill may make some improvements and modifications without departing from the principle of the present invention, and these improvements and modifications shall also be regarded as the protection scope of the present invention. All components that are not specified in this embodiment can be realized by existing technologies.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Direct Current Feeding And Distribution (AREA)
  • Dc-Dc Converters (AREA)
PCT/CN2022/077864 2021-12-28 2022-02-25 一种高可靠性片内电源切换电路 WO2022247369A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103647528A (zh) * 2013-12-06 2014-03-19 杭州士兰微电子股份有限公司 非交叠时钟产生电路
CN108092403A (zh) * 2017-12-28 2018-05-29 上海胤祺集成电路有限公司 电源自动切换电路及智能电表微控制芯片
CN110838847A (zh) * 2019-11-29 2020-02-25 湖南国科微电子股份有限公司 一种动态比较器及其控制方法
CN112003368A (zh) * 2020-09-22 2020-11-27 杭州万高科技股份有限公司 一种电源切换电路
US11011981B1 (en) * 2020-09-02 2021-05-18 Psemi Corporation Differential clock level translator for charge pumps

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090055661A1 (en) * 2007-08-20 2009-02-26 Kuo Kuo-Hsien Always-on system
CN103326458B (zh) * 2013-07-09 2015-11-25 深圳市汇顶科技股份有限公司 一种外部电源和电池供电的电源切换电路
CN205407406U (zh) * 2016-03-31 2016-07-27 大唐贵州发耳发电有限公司 一种cems的双电源切换控制***

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103647528A (zh) * 2013-12-06 2014-03-19 杭州士兰微电子股份有限公司 非交叠时钟产生电路
CN108092403A (zh) * 2017-12-28 2018-05-29 上海胤祺集成电路有限公司 电源自动切换电路及智能电表微控制芯片
CN110838847A (zh) * 2019-11-29 2020-02-25 湖南国科微电子股份有限公司 一种动态比较器及其控制方法
US11011981B1 (en) * 2020-09-02 2021-05-18 Psemi Corporation Differential clock level translator for charge pumps
CN112003368A (zh) * 2020-09-22 2020-11-27 杭州万高科技股份有限公司 一种电源切换电路

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