WO2022244293A1 - Analog/digital conversion circuit, solid-state image sensing device, and method for controlling analog/digital conversion circuit - Google Patents

Analog/digital conversion circuit, solid-state image sensing device, and method for controlling analog/digital conversion circuit Download PDF

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Publication number
WO2022244293A1
WO2022244293A1 PCT/JP2021/048865 JP2021048865W WO2022244293A1 WO 2022244293 A1 WO2022244293 A1 WO 2022244293A1 JP 2021048865 W JP2021048865 W JP 2021048865W WO 2022244293 A1 WO2022244293 A1 WO 2022244293A1
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analog
reset
signal
digital
reset code
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PCT/JP2021/048865
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French (fr)
Japanese (ja)
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尚人 長城
宣明 遠藤
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2022244293A1 publication Critical patent/WO2022244293A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type

Definitions

  • This technology relates to analog-to-digital conversion circuits.
  • the present invention relates to an analog-to-digital conversion circuit that performs processing for suppressing noise, a solid-state imaging device, and a control method for the analog-to-digital conversion circuit.
  • ADCs Analog to Digital Converters
  • pixel signals output from pixels into digital signals.
  • an imaging device has been proposed in which an ADC is arranged for each column and different random noise is applied for each column to a reset level before AD (Analog to Digital) conversion (see, for example, Patent Document 1).
  • random noise is applied to each column to suppress fixed pattern noise caused by quantization errors and linearity deterioration.
  • the conventional technology described above may not be able to sufficiently suppress noise.
  • the random noise applied to the analog reset level must be generated by an analog circuit, and a certain fixed pattern noise may occur in the row direction or the like due to manufacturing variations. This noise may degrade the signal quality of the pixel signal.
  • This technology was created in view of this situation, and aims to suppress deterioration in signal quality in circuits that perform AD conversion.
  • the present technology has been made to solve the above-described problems, and a first aspect thereof includes a comparator that generates a comparison result from an input analog signal and a predetermined reference signal, and a comparator that generates the reference signal.
  • a digital-to-analog converter to supply a digital-to-analog converter, a successive approximation logic circuit that initializes the reference signal with a predetermined reset code and then updates the reference signal based on the comparison result, and a reset control that controls the value of the reset code. and a control method thereof. This brings about the effect of reducing fixed pattern noise.
  • a pixel array section in which a plurality of pixels each generating the analog signal are arranged in a two-dimensional lattice, and rows in the pixel array section are sequentially driven to output the analog signal.
  • the reset control unit may update the reset code to a value different from the previous value each time the vertical scanning circuit drives the row. This has the effect of further reducing fixed pattern noise.
  • the reset control section may control the reset code to a value different from the previous value each time the analog signal is input. This has the effect of further reducing fixed pattern noise.
  • a plurality of SARADCs (Successive Approximation Register Analog to Digital Converter) are arranged, and the comparator, the digital-to-analog converter and the successive approximation logic circuit are arranged in each of the plurality of SARADCs,
  • the reset control unit may control reset codes of the plurality of SAR ADCs to different values. This has the effect of further reducing fixed pattern noise.
  • the first aspect may further include a capacitive multiplexer that holds a plurality of analog signals in capacitive elements, sequentially selects one of the held plurality of analog signals, and inputs the analog signals to the comparator. This has the effect of allowing multiple columns to share a capacitive multiplexer.
  • the first aspect may further include a column amplifier that obtains a difference between a predetermined reset level and a signal level corresponding to the amount of exposure and supplies it as the analog signal. This brings about the effect of reducing noise at the time of resetting.
  • a pre-processing unit that obtains a correction amount based on the reset code
  • a reset code processing unit that performs reset code processing on the digital signal from the successive approximation logic circuit based on the correction amount.
  • the reset control unit supplies a code obtained by performing a predetermined operation on a code of a predetermined initial value as the reset code
  • the pre-processing unit calculates the correction amount according to the reset code.
  • the digital signal may be supplied to the reset code processing unit, and the successive approximation logic circuit may generate the digital signal based on a predetermined number of the comparison results. This brings about the effect of processing the reset code of the digital signal.
  • the calculation may include addition of dither signals. This brings about the effect of applying a dither signal.
  • the above calculation may include a process of adding or subtracting a predetermined value to or from the previous value. This brings about the effect of simplifying the calculation.
  • a second aspect of the present technology includes a pixel that generates an analog signal, a comparator that generates a comparison result from the analog signal and a predetermined reference signal, a digital-to-analog converter that supplies the reference signal, a predetermined
  • a solid-state imaging device comprising: a successive approximation logic circuit that initializes the reference signal by the reset code of and then updates the reference signal based on the comparison result; and a reset control unit that controls the value of the reset code be.
  • 5 is a timing chart showing an example of control of a capacitance multiplexer and SARADC in a comparative example; It is a figure for explaining reset code processing in a 1st embodiment of this art.
  • 6 is a graph showing noise characteristics in a comparative example and the first embodiment of the present technology; It is a flow chart which shows an example of operation of a solid-state image sensing device in a 1st embodiment of this art. It is a block diagram showing an example of composition of an analog digital conversion part and a digital signal processing part in a 2nd embodiment of this art.
  • 9 is a timing chart showing a control example of a reset code of SAR ADC in the second embodiment of the present technology
  • 9 is a timing chart showing an example of control of reset codes of adjacent SAR ADCs in the second embodiment of the present technology
  • It is a figure showing an example of the noise characteristic in a 2nd embodiment of this art.
  • 9 is a timing chart showing another control example of the reset code according to the second embodiment of the present technology
  • 1 is a block diagram showing a schematic configuration example of a vehicle control system
  • FIG. FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit
  • FIG. 1 is a block diagram showing a configuration example of an imaging device 100 according to the first embodiment of the present technology.
  • This imaging device 100 is a device for capturing image data, and includes an optical section 110 , a solid-state imaging device 200 and a DSP (Digital Signal Processing) circuit 120 .
  • the imaging device 100 further includes a display section 130 , an operation section 140 , a bus 150 , a frame memory 160 , a storage section 170 and a power supply section 180 .
  • a digital camera such as a digital still camera, a smart phone, a personal computer, an in-vehicle camera, and the like having an imaging function are assumed.
  • the optical unit 110 collects light from a subject and guides it to the solid-state imaging device 200 .
  • the solid-state imaging device 200 generates image data by photoelectric conversion in synchronization with the vertical synchronization signal VSYNC.
  • the vertical synchronizing signal VSYNC is a periodic signal with a predetermined frequency that indicates the timing of imaging.
  • the solid-state imaging device 200 supplies the generated image data to the DSP circuit 120 via the signal line 209 .
  • the DSP circuit 120 executes predetermined signal processing on the image data from the solid-state imaging device 200 .
  • the DSP circuit 120 outputs the processed image data to the frame memory 160 or the like via the bus 150 .
  • the display unit 130 displays image data.
  • a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed.
  • the operation unit 140 generates an operation signal according to user's operation.
  • the bus 150 is a common path through which the optical unit 110, the solid-state imaging device 200, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170, and the power supply unit 180 exchange data with each other.
  • the frame memory 160 holds image data.
  • the storage unit 170 stores various data such as image data.
  • the power supply unit 180 supplies power to the solid-state imaging device 200, the DSP circuit 120, the display unit 130, and the like.
  • FIG. 2 is a diagram showing an example of the layered structure of the solid-state imaging device 200 according to the first embodiment of the present technology.
  • This solid-state imaging device 200 comprises a circuit chip 202 and a light receiving chip 201 laminated on the circuit chip 202 . These chips are electrically connected through connections such as vias. In addition to vias, Cu--Cu bonding or bumps may be used for connection.
  • FIG. 3 is a block diagram showing one configuration example of the solid-state imaging device 200 according to the first embodiment of the present technology.
  • This solid-state imaging device 200 includes a vertical scanning circuit 211 , a timing control circuit 212 , a pixel array section 220 , an analog-to-digital conversion section 300 and a digital signal processing section 240 .
  • a plurality of pixels 230 are arranged in a two-dimensional grid in the pixel array section 220 .
  • a set of pixels 230 arranged in the horizontal direction will be referred to as a "row”
  • a set of pixels 230 arranged in the direction perpendicular to the row will be referred to as a "column”.
  • the pixel array section 220 is arranged in the light receiving chip 201, for example. Also, the vertical scanning circuit 211, the timing control circuit 212, the analog-to-digital converter 300, and the digital signal processor 240 are arranged on the circuit chip 202, for example.
  • the vertical scanning circuit 211 sequentially selects and drives rows to output pixel signals.
  • the pixels 230 generate analog pixel signals and output them to the analog-to-digital converter 300 .
  • the analog-to-digital conversion section 300 performs AD conversion on the pixel signal of each column and supplies the digital signal to the digital signal processing section 240 .
  • the digital signal processing section 240 performs predetermined signal processing on the digital signal. Data obtained by arranging the digital signals after signal processing is supplied to the DSP circuit 120 as image data.
  • FIG. 4 is a circuit diagram showing one configuration example of the pixel 230 according to the first embodiment of the present technology.
  • This pixel 230 includes a photoelectric conversion element 231 , a transfer transistor 232 , a reset transistor 233 , a floating diffusion layer 234 , an amplification transistor 235 and a selection transistor 236 .
  • the photoelectric conversion element 231 generates charges by photoelectric conversion of incident light.
  • the transfer transistor 232 transfers charges from the photoelectric conversion element 231 to the floating diffusion layer 234 according to the transfer signal TRG from the vertical scanning circuit 211 .
  • the reset transistor 233 initializes the floating diffusion layer 234 according to the reset signal RST from the vertical scanning circuit 211 .
  • the floating diffusion layer 234 generates a voltage corresponding to the transferred charge amount.
  • the amplification transistor 235 amplifies the voltage of the floating diffusion layer 234 .
  • the selection transistor 236 outputs the amplified voltage analog signal as the pixel signal VSL to the analog-to-digital converter 300 via the vertical signal line 229 in accordance with the selection signal SEL from the vertical scanning circuit 211 .
  • the pixel signal VSL of the m-th (m is an integer) column is hereinafter referred to as VSLm.
  • the level of the pixel signal VSLm when the floating diffusion layer 234 is initialized by the reset signal RST is called “reset level” or “P phase”.
  • the level of the pixel signal VSLm when the charge is transferred by the transfer signal TRG is referred to as “signal level” or "D phase”.
  • FIG. 5 is a block diagram showing a configuration example of the analog-to-digital converter 300 according to the first embodiment of the present technology.
  • This analog-to-digital converter 300 includes a plurality of column amplifiers 310 , a plurality of capacitive multiplexers 400 and a plurality of SAR ADCs 320 .
  • a column amplifier 310 is arranged for each column. When the number of columns is M (M is an integer), M column amplifiers 310 are arranged. Multiple columns also share one capacitive multiplexer 400 . When the capacitance multiplexers 400 are shared by two columns, M/2 capacitance multiplexers 400 are arranged. Also, multiple columns share one SAR ADC 320 . When the SAR ADC 320 is shared by 8 columns, M/8 SAR ADCs 320 are arranged.
  • the number of columns that share the capacitive multiplexer 400 and the SAR ADC 320 is not limited to 2 columns or 8 columns. However, the number of columns sharing the SAR ADC 320 is greater than or equal to the number of columns sharing the capacitance multiplexer 400 . Note that the SARADC 320 can also be arranged for each column. In this case, the capacitive multiplexer 400 may not be provided.
  • the column amplifier 310 performs analog CDS processing to obtain the difference between the reset level and the signal level of the pixel signal VSLm of the corresponding column. Analog CDS processing provides a net signal level.
  • the column amplifier 310 supplies the pixel signal after analog CDS processing to the capacitance multiplexer 400 .
  • the pixel signals VSL0 and VSL4 of the 0th and 4th columns are input to the 0th capacitance multiplexer 400 .
  • Pixel signals VSL1 and VSL5 of the first and fifth columns are input to the first capacitive multiplexer 400 .
  • Pixel signals VSL2 and VSL6 of the second and sixth columns are input to the second capacitive multiplexer 400 .
  • Pixel signals VSL3 and VSL7 of the third and seventh columns are input to the third capacitive multiplexer 400 .
  • Pixel signals for two columns are similarly input to the capacitance multiplexer 400 for the eighth column and beyond.
  • These pixel signals VSLm are single-ended signals.
  • the column amplifier 310 performs analog CDS processing
  • a circuit subsequent to the SAR ADC 320 can perform digital CDS processing instead of analog CDS processing. In this case, the column amplifier 310 does not need to perform analog CDS processing.
  • the capacitive multiplexer 400 holds pixel signals of a plurality of columns in capacitive elements (not shown), selects those pixel signals in order, and inputs them to the SAR ADC 320 .
  • the SAR ADC 320 converts an analog pixel signal into a digital signal Dout by a successive approximation method, and supplies the digital signal Dout to the digital signal processing section 240 .
  • the SAR ADC 320 also includes a CDAC (Capacitor DAC), and performs AD conversion after initializing the CDAC according to a reset code RC from the digital signal processing unit 240 .
  • CDAC Capacitor DAC
  • FIG. 6 is a circuit diagram showing a configuration example of the column amplifier 310 according to the first embodiment of the present technology.
  • This column amplifier 310 includes an amplifier 311 , switches 312 , 313 and 316 , and capacitive elements 314 and 315 .
  • a non-inverting input terminal (+) of the amplifier 311 is connected to the vertical signal line 229 and receives the pixel signal VSLm from the pixel array section 220 . Also, the output terminal of the amplifier 311 is connected to the capacitance multiplexer 400 .
  • the switch 312 opens and closes the path between the output terminal of the amplifier 311 and the inverting input terminal ( ⁇ ) according to the control signal Sp from the timing control circuit 212 .
  • the switch 313 opens and closes the path between the output terminal of the amplifier 311 and the capacitive element 314 according to the control signal SD from the timing control circuit 212 .
  • Capacitive elements 314 and 315 are connected in series between switch 313 and a reference potential (eg, ground), and their connection node is connected to the inverting input terminal ( ⁇ ) of amplifier 311 .
  • the switch 316 operates between the connection node of the switch 313 and the capacitive element 314 and the local reference voltage VR that defines the zero voltage of the output of the column amplifier 310 at the reference potential. It opens and closes the path of
  • the timing control circuit 212 controls only the switches 312 and 316 to the closed state to cause the capacitive elements 314 and 315 to hold the reset level.
  • the timing control circuit 212 also closes only the switch 313 when the signal level is input. Feedback is applied so that the voltage at the connection node of capacitive elements 314 and 315 has the same value as the signal level.
  • the amplifier 311 outputs a signal obtained by amplifying the difference between the reset level and the signal level as the pixel signal VSLm'. In this manner, the column amplifier 310 performs analog CDS processing for obtaining the difference between the reset level (P phase) and the signal level (D phase).
  • FIG. 7 is a circuit diagram showing a configuration example of the capacitive multiplexer 400 according to the first embodiment of the present technology.
  • This capacitive multiplexer 400 comprises sample and hold blocks 410 , 430 and 450 .
  • the sample and hold block 410 includes switches 411 to 418 and capacitive elements 419 and 420 .
  • the sample and hold block 430 includes switches 431 to 438 and capacitive elements 439 and 440 .
  • the sample and hold block 450 includes switches 451 to 458 and capacitive elements 459 and 460 .
  • the switch 411 opens and closes the path between the column amplifier 310 of the 0th column that supplies the pixel signal VSL0′ and the capacitive element 419 according to the control signal SIN0A from the timing control circuit 212 .
  • the switch 412 opens and closes the path between the column amplifier 310 of the fourth column that supplies the pixel signal VSL4′ and the capacitive element 419 according to the control signal SIN1A from the timing control circuit 212 .
  • the switch 413 opens and closes the path between the local reference voltage VR and the capacitive element 420 according to the control signal SINA from the timing control circuit 212 .
  • the switch 414 opens and closes the path between the connection node of the switch 411 and the capacitance element 419 and the connection node of the switch 413 and the capacitance element 420 according to the control signal SVMIA[n] from the timing control circuit 212 .
  • the subscript n in the control signal S VMIA[n] indicates the n (n is an integer from 0 to N) out of the N (eg, 4) capacitive multiplexers 400 that share the SAR ADC 320 . The same applies to the following control signals.
  • a capacitive element 419 is inserted between switches 411 and 417 .
  • a capacitive element 420 is inserted between switches 413 and 418 .
  • Switches 415 and 416 are connected in series between the connection node of capacitive element 419 and switch 417 and the connection node of capacitive element 420 and switch 418 . These switches 415 and 416 open and close according to the control signal SVMA from the timing control circuit 212 .
  • a connection node of switches 415 and 416 is connected to SAR ADC 320 and receives common voltage VCR.
  • the switch 417 opens and closes the path between the capacitive element 419 and the SAR ADC 320 according to the control signal SSUMA[n] from the timing control circuit 212 .
  • An analog positive signal SH+ is output to SAR ADC 320 when switch 417 is closed.
  • the switch 418 opens and closes the path between the capacitive element 420 and the SAR ADC 320 according to the control signal SSUMA[n] from the timing control circuit 212 .
  • An analog negative signal SH ⁇ is output to SAR ADC 320 when switch 418 is closed.
  • sample and hold blocks 430 and 450 are similar to sample and hold block 410 .
  • control signals S IN0B , S IN1B , S INB , S VMIB[n] , S VMB and S SUMB[n] are input to the sample hold block 430 .
  • control signals S IN0C , S IN1C , S INC , S VMIC[n] , S VMC and S SUMC[n] are input to the sample hold block 450 .
  • Sample and hold blocks 410, 430 and 450 are also referred to as blocks A, B and C hereinafter.
  • the capacitive multiplexer 400 converts the pixel signals VSLm' (in other words, single-ended signals) of the corresponding two columns into differential signals and holds them. Then, the capacitive multiplexer 400 sequentially outputs the held pixel signals for two columns (in other words, differential signals) to the SAR ADC 320 .
  • the capacitive multiplexer 400 performs differential conversion, it is also possible to hold and output a single-ended signal without performing differential conversion. In this case, the number of capacitive elements can be reduced by half.
  • FIG. 8 is a block diagram showing one configuration example of the SAR ADC 320 and the digital signal processing unit 240 according to the first embodiment of the present technology.
  • SAR ADC 320 comprises autozero switches 321 and 322 , preamplifier 323 , comparator 324 , CDACs 325 and 326 and SAR logic circuit 327 .
  • a positive side signal SH+ from the capacitance multiplexer 400 is input to the non-inverting input terminal (+) of the preamplifier 323 .
  • the negative side signal SH- from the capacitance multiplexer 400 is input to the inverting input terminal (-) of the preamplifier 323 .
  • the common voltage VCR from the capacitance multiplexer 400 is used as the positive side and negative side common voltages in the preamplifier 323 .
  • the preamplifier 323 amplifies a differential signal composed of the positive side signal SH+ and the negative side signal SH ⁇ and differentially outputs it to the comparator 324 . This differential signal corresponds to a differentially converted pixel signal, as described above.
  • the auto-zero switch 321 opens and closes the path between the non-inverting input terminal (+) and the non-inverting output terminal of the preamplifier 323 according to the control signal SAZ from the timing control circuit 212 .
  • the auto-zero switch 322 opens and closes the path between the inverting input terminal (-) and the inverting output terminal of the preamplifier 323 according to the control signal SAZ .
  • the auto-zero switches 321 and 322 are closed at the timing indicated by the control signal SAZ , and auto-zero is performed.
  • the comparator 324 compares the potential of the non-inverting output terminal and the potential of the inverting output terminal of the preamplifier 323 in synchronization with the clock signal CKI from the timing control circuit 212 . This comparator 324 supplies the comparison result to the SAR logic circuit 327 .
  • the CDAC 325 generates a positive side reference signal under the control of the SAR logic circuit 327 and supplies it to the non-inverting input terminal (+) of the preamplifier 323 .
  • the CDAC 326 generates a negative side reference signal under the control of the SAR logic circuit 327 and supplies it to the inverting input terminal (-) of the preamplifier 323 .
  • These reference signals increase or decrease the value of the pixel signal (that is, the differential signal).
  • the comparison result of comparator 324 is obtained from the differential signal and the reference signal. For example, the comparison result indicates whether or not the value obtained by increasing or decreasing the differential signal with the reference signal is higher than a predetermined level (such as "0").
  • the CDACs 325 and 326 are an example of the digital-analog converter described in the claims.
  • the SAR logic circuit 327 receives the control signal SAZ and the clock signal CK from the timing control circuit 212 , the reset code RC from the digital signal processing section 240 , and the comparison result from the comparator 324 .
  • Reset code RC is a code indicating the initial value of the reference signal from CDACs 325 and 326 .
  • the SAR logic circuit 327 initializes the reference signal with the reset code RC at the auto-zero timing indicated by the control signal SAZ . After initialization, the SAR logic circuit 327 updates the positive or negative side reference signal to increase or decrease the differential signal based on the comparison result. The incrementing or decrementing value is controlled to be smaller than the previous value for each comparison. This implements a binary search. The successive approximation is executed in synchronization with the clock signal CKI, and a digital signal in which comparison results for a predetermined number of times are arranged is output to the digital signal processing section 240 as Dout.
  • the SAR logic circuit 327 is an example of the successive approximation logic circuit described in the claims.
  • the digital signal processing section 240 includes a reset control section 241 , a pre-processing section 242 , a plurality of reset code processing sections 243 and a post-processing section 244 .
  • the reset code processing unit 243 is arranged for each SAR ADC 320 .
  • the reset control unit 241 controls the value of the reset code RC.
  • the reset control unit 241 updates the reset code RC to a value different from the previous value every time the vertical scanning circuit 211 drives the row.
  • the reset control unit 241 executes, for example, a predetermined calculation and updates to the calculation result.
  • Arithmetic at the time of updating includes addition of the reset code of the initial value and the dither signal.
  • the reset control unit 241 generates a dither signal each time an update is performed, and sets the result of adding the dither signal to the reset code of the initial value as a new reset code.
  • the computation at the time of updating may include processing for adding or subtracting a predetermined value (such as "1") from the previous value.
  • a predetermined value such as "1”
  • the reset control unit 241 increments or decrements the previous reset code at each update, and uses the result as a new reset code.
  • the reset control unit 241 supplies the updated reset code RC to the pre-processing unit 242 at the end of the AD conversion.
  • the pre-processing unit 242 decodes the digital signal Dout from the SAR ADC 320 and supplies it to the reset code processing unit 243 .
  • decoding includes processing to convert it into decimal numbers. Note that linearity correction can be performed simultaneously with decoding of the digital signal Dout.
  • the pre-processing unit 242 also decodes the updated reset code RC to obtain a correction amount, and supplies it to the reset code processing unit 243 .
  • the reset code processing unit 243 performs reset code processing on the decoded digital signal Dout based on the correction amount from the pre-processing unit 242 .
  • the correction amount in other words, reset code
  • the reset code processing unit 243 supplies the corrected digital signal to the post-processing unit 244 .
  • the post-processing unit 244 performs various post-processing on the digital signal from the reset code processing unit 243 as necessary.
  • the post-processing section 244 supplies the processed digital signal to the DSP circuit 120 .
  • the SAR ADC 320 AD converts differential signals, but can also AD convert single-ended signals. In this case, the previous-stage capacitive multiplexer 400 does not perform differential conversion. Also, one of the CDACs 325 and 326 is reduced and the comparator 324 compares the pixel signal with the reference signal.
  • the SAR ADC 320 and the digital signal processing unit 240 are arranged in the solid-state imaging device 200, the configuration is not limited to this.
  • the SAR ADC 320 and the digital signal processing unit 240 can be arranged in a circuit other than the solid-state imaging device 200 as long as it is a circuit that performs AD conversion.
  • the circuit in which the SAR ADC 320 and the digital signal processing unit 240 are arranged is an example of the analog-to-digital conversion circuit described in the claims.
  • FIG. 9 is a block diagram showing one configuration example of the analog-to-digital converter 300 and the digital signal processor 240 according to the first embodiment of the present technology.
  • the column amplifier 310 is omitted in FIG.
  • the SAR ADC 320 When the SAR ADC 320 is shared by 8 columns, the SAR ADC 320 is provided every 8 columns.
  • the reset control unit 241 supplies the same reset code RC to each of the SAR ADCs 320 . However, every time the vertical scanning circuit 211 drives a row, the reset control unit 241 controls the reset code RC to a value different from the previous value by a dither signal. Similarly, the same value is supplied to each of the reset code processing units 243 for the correction amount, and the correction amount is updated each time the row is driven.
  • FIG. 10 is a timing chart showing an example of control of the pixels 230, the column amplifiers 310 and the capacitance multiplexer 400 according to the first embodiment of the present technology.
  • the vertical scanning circuit 211 supplies the transfer signal TRG to the selected row to cause the pixels 230 in the row to generate signal levels.
  • the timing control circuit 212 supplies a high-level control signal SD for a certain period of time to cause the column amplifier 310 to perform analog CDS processing.
  • Timing control circuit 212 also provides high level control signals S IN , S IN0A , S IN1B , S VMA and S VMB for a certain period of time.
  • the control signal S IN shall include S INA , S INB and S INC . These control signals cause the capacitive multiplexer 400 to hold pixel signals for the corresponding two columns in the block A and block B.
  • the first of the four capacitive multiplexers 400 that share the SARADC 320 holds, for example, pixel signals for columns 0 and 4, and the second capacitive multiplexer 400 holds, for example, columns 1 and 5. holds the pixel signals of A third capacitive multiplexer 400 holds, for example, the pixel signals of the second and sixth columns, and a fourth capacitive multiplexer 400 holds, for example, the pixel signals of the third and seventh columns. The same applies to the eighth and subsequent columns. Thus, pixel signals for one row are held.
  • the vertical scanning circuit 211 supplies the reset signal RST to the selected row, causing the pixels 230 in the row to generate the reset level.
  • the timing control circuit 212 supplies high-level control signals SP and SVR for a certain period of time to cause the column amplifier 310 to hold the reset level.
  • the control contents of the pixels 230 and the column amplifiers 310 during the D-phase settling period from timings T2 to T3 are the same as those during the previous D-phase settling period.
  • the timing control circuit 212 supplies the high level control signals S IN , S IN1A , S IN0C , S VMA and S VMC to the capacitive multiplexer 400 for a certain period of time. These control signals cause the capacitive multiplexer 400 to hold pixel signals for two corresponding columns in blocks A and C.
  • the control contents of the P-phase settling period of the next timings T3 to T4 are the same as the previous P-phase settling period.
  • the control contents of the pixels 230 and the column amplifiers 310 during the D-phase settling period from timings T4 to T5 are the same as those during the previous D-phase settling period.
  • the timing control circuit 212 supplies the high level control signals S IN , S IN0B , S IN1C , S VMB and S VMC to the capacitive multiplexer 400 for a certain period of time. These control signals cause the capacitance multiplexer 400 to hold the pixel signals for the corresponding two columns in the blocks B and C. As shown in FIG.
  • timing T5 Similar control is repeatedly executed until all rows are selected.
  • FIG. 11 is a timing chart showing an example of control of the capacitance multiplexer 400 and the SAR ADC 320 according to the first embodiment of the present technology.
  • the four capacitive multiplexers 400 sharing the SAR ADC 320 hold pixel signals for eight columns.
  • the timing control circuit 212 sequentially supplies control signals S SUMA[0] , S SUMA[1] , S SUMA[2] and S SUMA[3] .
  • Control signals S-- VMIA[0] , S-- VMIA[1] , S-- VMIA[2] and S-- VMIA[3] are also provided in sequence.
  • the pixel signals held in the respective blocks A of the four capacitive multiplexers 400 sharing the SAR ADC 320 are sequentially output.
  • the SAR ADC 320 AD-converts each of the four pixel signals from the block A in sequence in synchronization with the clock signal CK.
  • a high-level control signal SAZ is supplied while the clock signal CK is at a low level, and the SAR ADC 320 performs auto-zeroing using the reset code RC during that period. While the clock signal CK is at high level, a clock signal CKI having a frequency higher than that of the clock signal CK is supplied, and the SAR ADC 320 performs successive approximation in synchronization with the clock signal CKI.
  • the timing control circuit 212 sequentially supplies the control signals S SUMB[0] , S SUMB[1] , S SUMB[2] and S SUMB[3] .
  • Control signals S-- VMIB[0] , S-- VMIB[1] , S-- VMIB[2] and S-- VMIB[3] are also provided in sequence.
  • the pixel signals held in the respective blocks B of the four capacitive multiplexers 400 sharing the SAR ADC 320 are sequentially output.
  • the SAR ADC 320 sequentially AD-converts each of the four pixel signals from the block B in synchronization with the clock signal CK. During the period from timings T1 to T3, pixel signals for eight columns held during the period from timings T0 to T1 are AD-converted. A plurality of SDRADCs 320 operate in parallel to AD-convert pixel signals for eight columns, thereby reading pixel signals for one row. Therefore, a period consisting of the P-phase settling period and the immediately following D-phase settling period corresponds to an AD conversion period for one row.
  • the SAR ADC 320 AD-converts each of the four pixel signals from block C in turn.
  • the SAR ADC 320 AD-converts each of the four pixel signals from block A in turn.
  • the SAR ADC 320 AD-converts each of the four pixel signals from block B in turn.
  • the SAR ADC 320 AD-converts each of the four pixel signals from block C in turn. After that, similar control is repeatedly executed.
  • the reset control unit 241 updates the reset code RC to a value different from the previous value every time the AD conversion period for one row passes (in other words, the row is driven). For example, during the AD conversion period of timings T1 to T3, the reset control unit 241 updates to RC_b different from the previous RC_a. The reset control unit 241 updates to RC_c different from the previous RC_b in the AD conversion period of the next timings T3 to T5. Below, the reset code is updated each time a row is driven. This sets a different reset code for each row.
  • FIG. 12 is a timing chart showing an example of control of the capacitance multiplexer 400 and SARADC 320 in the comparative example. As illustrated in the figure, in the comparative example, the reset code is not updated, and the same reset code is set for each row.
  • FIG. 13 is a diagram for explaining reset code processing in the first embodiment of the present technology.
  • the vertical axis in the figure indicates the value of the digital signal Dout, and the horizontal axis indicates the level of the analog pixel signal VSL.
  • a is a diagram showing linearity characteristics when no dither signal is applied.
  • b in the same figure is a diagram showing the linearity characteristic before the dither signal is applied and the reset code process is performed.
  • c is a diagram showing linearity characteristics after applying a dither signal and performing reset code processing.
  • the relationship between the input pixel signal and the output digital signal may not be linear.
  • VSLm a certain pixel signal
  • Dout a digital signal Dout indicating "64".
  • the reset control unit 241 applies a dither signal to the reset code of the initial value to generate a new reset code RC.
  • the initial value is set to "0" in decimal number. Due to the application of the dither signal, the reset code RC after application of the dither signal changes to a value different from the initial value (“0”), as illustrated by b in FIG. , which deviates greatly from "64". Note that the initial value may be a value other than "0".
  • the reset code processing unit 243 performs reset code processing on the digital signal Dout using the correction amount Cd corresponding to the reset code RC after application of the dither signal.
  • this correction makes the value corresponding to the pixel signal VSLm "66", and the deviation from "64" can be reduced.
  • AD conversion can be performed in portions with different linearities according to the dither signal, it is possible to reduce the influence of linearity breakdown.
  • FIG. 14 is a graph showing noise characteristics in the comparative example and the first embodiment of the present technology.
  • the vertical axis indicates fixed pattern noise (FPN) in the vertical direction
  • the horizontal axis indicates the digital signal Dout.
  • a indicates the noise characteristics of the comparative example
  • b indicates the noise characteristics of the first embodiment.
  • fixed pattern noise can also be reduced to some extent by arranging a single-slope ADC for each column and applying random noise to the reset level.
  • this method assumes the use of a single-slope ADC and cannot be applied to a configuration in which a SAR ADC is arranged.
  • analog CDS processing for obtaining the difference between the reset level and the signal level cannot be performed.
  • the random noise must be generated by analog circuitry, which is subject to imperfections such as manufacturing variations, which can result in constant, fixed-pattern noise.
  • FIG. 15 is a flow chart showing an example of the operation of the solid-state imaging device 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing image data is executed.
  • the vertical scanning circuit 211 selects a row to read (step S901). Also, the reset control unit 241 sets a different reset code for each row (step S902).
  • the SAR ADC 320 performs auto zero, and initializes the CDSC with a reset code (step S903). The SAR ADC 320 then performs successive approximation and generates a digital signal (step S904).
  • step S905 the digital signal processing unit 240 corrects the digital signal using the reset code (step S905).
  • SARADC 320 determines whether the last row has been read (step S906). If the last line has not been read (step S906: No), the solid-state imaging device 200 repeatedly executes step S901 and subsequent steps. If the last line has been read (step S906: Yes), the solid-state imaging device 200 ends the operation for imaging.
  • steps S901 to S906 are repeatedly executed in synchronization with the vertical synchronization signal.
  • the reset control unit 241 controls the reset code to a different value for each row, so fixed pattern noise can be suppressed. Thereby, the signal quality of the pixel signal can be improved.
  • the reset code is controlled to have a different value for each row, but with this configuration, there is a possibility that fixed pattern noise in the row direction cannot be sufficiently suppressed.
  • the solid-state imaging device 200 of the second embodiment differs from the first embodiment in that the reset code is controlled to have different values for each row and each column.
  • FIG. 16 is a block diagram showing one configuration example of the analog-to-digital converter 300 and the digital signal processor 240 according to the second embodiment of the present technology.
  • the reset control unit 241 of the second embodiment supplies reset codes of different values to each of the plurality of SAR ADCs 320 .
  • the reset control unit 241 supplies the reset code RC_A to the k-th (k is an integer) SAR ADC 320 . Also, the reset control unit 241 generates a reset code RC_B different from the reset code RC_A by applying a dither signal or the like, and supplies it to the k+1 th SAR ADC 320 .
  • FIG. 17 is a timing chart showing an example of reset code control of the k-th SAR ADC 320 according to the second embodiment of the present technology.
  • the reset control unit 241 controls the reset code to a value different from the previous value in synchronization with the control signal SAZ indicating the auto-zero timing. Since auto-zeroing is performed each time a pixel signal is input to the SAR ADC 320 (in other words, for each column), a different reset code is set for each column.
  • the reset control unit 241 supplies the reset code RC_A0 when the 0th column among the plurality of columns sharing the kth SAR ADC 320 is auto-zeroed. At the time of auto-zeroing of the next first column, the reset control unit 241 generates a reset code RC_A1 different from the reset code RC_A0 by applying a dither signal or the like, and supplies it to the SAR ADC 320 . Also, as in the first embodiment, a different reset code is set for each row.
  • FIG. 18 is a timing chart showing an example of reset code control of the k+1th SAR ADC 320 in the second embodiment of the technology.
  • the reset control unit 241 controls the reset code to different values for each row and each column.
  • the reset control unit 241 supplies the reset code RC_B0 during auto-zeroing of the 0th column among the plurality of columns sharing the k+1th SAR ADC 320 .
  • the reset control unit 241 At the next auto-zeroing of the first column, the reset control unit 241 generates a reset code RC_B1 different from the reset code RC_B0 by applying a dither signal or the like, and supplies it to the SAR ADC 320 .
  • the reset code RC_B0 in the 0th column of the k+1 SAR ADC 320 is different from the reset code RC_A0 in the 0th column of the k th SAR ADC 320 .
  • the first column reset code RC_B1 of the k+1 th SAR ADC 320 is different from the first column reset code RC_A1 of the k th SAR ADC 320 . The same applies to subsequent columns.
  • the reset control unit 241 controls the reset code so that it has different values for each row, each column, and each SAR ADC 320 .
  • FIG. 19 is a diagram showing an example of noise characteristics in the second embodiment of the present technology. Readout noise in the second embodiment is the same as in the first embodiment.
  • the pixel FPN in the second embodiment is approximately the same as in the first embodiment.
  • the FPN level in the row direction in the second embodiment is lowered (improved) compared to the first embodiment.
  • the FPN maximum value in the row direction in the second embodiment is also improved compared to the first embodiment.
  • the FPN level in the column direction and the FPN maximum value in the column direction are approximately the same as in the first embodiment.
  • the temporary noise level in the row direction in the second embodiment is reduced (improved) compared to the first embodiment.
  • the row-wise transient noise maximum in the second embodiment is also improved compared to the first embodiment.
  • the column-direction temporal noise level and the column-direction temporal noise maximum value are the same as in the first embodiment.
  • the reset control unit 241 can also set the same reset code for each column, and set a different reset code for each row and for each SAR ADC 320, as exemplified by a in FIG.
  • the reset control unit 241 can set the same reset code to a plurality of SAR ADCs 320, and set different reset codes for each row and each column.
  • the reset control unit 241 controls the reset code to a different value for each row and for each column, so fixed pattern noise can be further suppressed.
  • the technology (the present technology) according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
  • FIG. 21 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • a vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps.
  • the body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
  • the vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed.
  • the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 .
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
  • the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
  • the imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
  • the in-vehicle information detection unit 12040 detects in-vehicle information.
  • the in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
  • the microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit.
  • a control command can be output to 12010 .
  • the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
  • the audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 22 is a diagram showing an example of the installation position of the imaging unit 12031.
  • the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose of the vehicle 12100, the side mirrors, the rear bumper, the back door, and the upper part of the windshield in the vehicle interior, for example.
  • An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 .
  • Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 .
  • An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 .
  • the imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 22 shows an example of the imaging range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of an imaging unit 12104 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the course of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
  • automatic brake control including following stop control
  • automatic acceleration control including following start control
  • the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 .
  • recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian.
  • the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above.
  • the imaging apparatus 100 in FIG. 1 applies the technology according to the present disclosure to the imaging unit 12031 that can be applied to the imaging unit 12031, thereby suppressing fixed pattern noise and producing a more viewable captured image. can be obtained, it becomes possible to reduce the fatigue of the driver.
  • the present technology can also have the following configuration. (1) a comparator that generates a comparison result from an input analog signal and a predetermined reference signal; a digital-to-analog converter that provides the reference signal; a successive approximation logic circuit that initializes the reference signal with a predetermined reset code and then updates the reference signal based on the comparison result; and a reset control unit that controls the value of the reset code.
  • a plurality of SAR ADCs (Successive Approximation Register Analog to Digital Converters) are arranged, The comparator, the digital-to-analog converter, and the successive approximation logic circuit are arranged in each of the plurality of SAR ADCs;
  • a pixel that produces an analog signal; a comparator that generates a comparison result from the analog signal and a predetermined reference signal; a digital-to-analog converter that provides the reference signal; a successive approximation logic circuit that initializes the reference signal with a predetermined reset code and then updates the reference signal based on the comparison result; and a reset control unit that controls the value of the reset code.
  • (11) a comparison procedure for generating a comparison result from the input analog signal and a predetermined reference signal; a digital-to-analog conversion procedure providing said reference signal; a successive approximation procedure for initializing the reference signal with a predetermined reset code and then updating the reference signal based on the comparison result; and a reset control procedure for controlling the value of the reset code.
  • imaging device 110 optical unit 120 DSP circuit 130 display unit 140 operation unit 150 bus 160 frame memory 170 storage unit 180 power supply unit 200 solid-state imaging device 201 light receiving chip 202 circuit chip 211 vertical scanning circuit 212 timing control circuit 220 pixel array unit 230 pixels 231 photoelectric conversion element 232 transfer transistor 233 reset transistor 234 floating diffusion layer 235 amplification transistor 236 selection transistor 240 digital signal processing section 241 reset control section 242 pre-processing section 243 reset code processing section 244 post-processing section 300 analog-to-digital conversion section 310 column amplifier 311 amplifier 312, 313, 316, 411 to 418, 431 to 438, 451 to 458 switch 314, 315, 419, 420, 439, 440, 459, 460 capacitive element 320 SARADC 321, 322 auto-zero switch 323 preamplifier 324 comparator 325, 326 CDAC 327 SAR logic circuit 400 capacitance multiplexer 410, 430, 450 sample hold block 12031 imaging unit

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Abstract

The present invention suppresses the degradation of signal quality in a circuit that performs A/D conversion.　This analog/digital conversion circuit comprises a comparator, a digital/analog converter, a sequential conversion logic circuit, and a reset control unit. The comparator generates a comparison result from an analog signal and a predetermined reference signal both inputted thereto. The digital/analog converter supplies the reference signal. The sequential comparison logic circuit uses a predetermined reset code to initialize the reference signal and thereafter causes the reference signal to be updated on the basis of the comparison result. The reset control unit controls the value of the reset code.

Description

アナログデジタル変換回路、固体撮像素子、および、アナログデジタル変換回路の制御方法Analog-to-digital conversion circuit, solid-state imaging device, and control method for analog-to-digital conversion circuit
　本技術は、アナログデジタル変換回路に関する。詳しくは、ノイズを抑制するための処理を行うアナログデジタル変換回路、固体撮像素子、および、アナログデジタル変換回路の制御方法に関する。 This technology relates to analog-to-digital conversion circuits. Specifically, the present invention relates to an analog-to-digital conversion circuit that performs processing for suppressing noise, a solid-state imaging device, and a control method for the analog-to-digital conversion circuit.
　従来より、撮像装置などの装置には、画素から出力されるアナログ信号（画素信号）をデジタル信号に変換するＡＤＣ（Analog to Digital Converter）が搭載されている。例えば、カラムごとにＡＤＣを配置し、ＡＤ（Analog to Digital）変換前のリセットレベルに対してカラムごとに異なるランダムノイズを印加する撮像装置が提案されている（例えば、特許文献１参照）。 Conventionally, devices such as imaging devices are equipped with ADCs (Analog to Digital Converters) that convert analog signals (pixel signals) output from pixels into digital signals. For example, an imaging device has been proposed in which an ADC is arranged for each column and different random noise is applied for each column to a reset level before AD (Analog to Digital) conversion (see, for example, Patent Document 1).
国際公開第２０１４／１３２８２２号WO2014/132822
　上述の従来技術では、カラムごとのランダムノイズの印加により、量子化誤差やリニアリティ劣化などによる固定パターンノイズの抑制を図ってる。しかし、上述の従来技術では、ノイズを十分に抑制することができないおそれがある。アナログのリセットレベルに印加するランダムノイズは、アナログ回路により生成する必要があり、製造ばらつきにより行方向などに一定の固定パターンノイズが生じることがある。このノイズにより、画素信号の信号品質が低下するおそれがある。 In the conventional technology described above, random noise is applied to each column to suppress fixed pattern noise caused by quantization errors and linearity deterioration. However, the conventional technology described above may not be able to sufficiently suppress noise. The random noise applied to the analog reset level must be generated by an analog circuit, and a certain fixed pattern noise may occur in the row direction or the like due to manufacturing variations. This noise may degrade the signal quality of the pixel signal.
　本技術はこのような状況に鑑みて生み出されたものであり、ＡＤ変換を行う回路において、信号品質の低下を抑制することを目的とする。 This technology was created in view of this situation, and aims to suppress deterioration in signal quality in circuits that perform AD conversion.
　本技術は、上述の問題点を解消するためになされたものであり、その第１の側面は、入力されたアナログ信号と所定の参照信号とから比較結果を生成するコンパレータと、上記参照信号を供給するデジタルアナログ変換器と、所定のリセットコードにより上記参照信号を初期化させた後に上記比較結果に基づいて上記参照信号を更新させる逐次比較ロジック回路と、上記リセットコードの値を制御するリセット制御部とを具備するアナログデジタル変換回路、および、その制御方法である。これにより、固定パターンノイズが低減するという作用をもたらす。 The present technology has been made to solve the above-described problems, and a first aspect thereof includes a comparator that generates a comparison result from an input analog signal and a predetermined reference signal, and a comparator that generates the reference signal. a digital-to-analog converter to supply a digital-to-analog converter, a successive approximation logic circuit that initializes the reference signal with a predetermined reset code and then updates the reference signal based on the comparison result, and a reset control that controls the value of the reset code. and a control method thereof. This brings about the effect of reducing fixed pattern noise.
　また、この第１の側面において、それぞれが上記アナログ信号を生成する複数の画素が二次元格子状に配列された画素アレイ部と、上記画素アレイ部内の行を順に駆動して上記アナログ信号を出力させる垂直走査回路とをさらに具備し、上記リセット制御部は、上記垂直走査回路が行を駆動するたびに上記リセットコードを前回値と異なる値に更新してもよい。これにより、固定パターンノイズがさらに低減するという作用をもたらす。 Further, in the first aspect, a pixel array section in which a plurality of pixels each generating the analog signal are arranged in a two-dimensional lattice, and rows in the pixel array section are sequentially driven to output the analog signal. The reset control unit may update the reset code to a value different from the previous value each time the vertical scanning circuit drives the row. This has the effect of further reducing fixed pattern noise.
　また、この第１の側面において、上記リセット制御部は、上記アナログ信号が入力されるたびに上記リセットコードを前回値と異なる値に制御してもよい。これにより、固定パターンノイズがさらに低減するという作用をもたらす。 Further, in this first aspect, the reset control section may control the reset code to a value different from the previous value each time the analog signal is input. This has the effect of further reducing fixed pattern noise.
　また、この第１の側面において、複数のＳＡＲＡＤＣ（Successive Approximation Register Analog to Digital Converter）が配列され、上記複数のＳＡＲＡＤＣのそれぞれに上記コンパレータ、上記デジタルアナログ変換器および上記逐次比較ロジック回路が配置され、上記リセット制御部は、上記複数のＳＡＲＡＤＣのそれぞれのリセットコードを異なる値に制御してもよい。これにより、固定パターンノイズがさらに低減するという作用をもたらす。 Further, in this first aspect, a plurality of SARADCs (Successive Approximation Register Analog to Digital Converter) are arranged, and the comparator, the digital-to-analog converter and the successive approximation logic circuit are arranged in each of the plurality of SARADCs, The reset control unit may control reset codes of the plurality of SAR ADCs to different values. This has the effect of further reducing fixed pattern noise.
　また、この第１の側面において、複数のアナログ信号を容量素子に保持して上記保持した複数のアナログ信号のいずれかを順に選択して上記コンパレータに入力する容量マルチプレクサをさらに具備してもよい。これにより、複数列が容量マルチプレクサを共有するという作用をもたらす。 In addition, the first aspect may further include a capacitive multiplexer that holds a plurality of analog signals in capacitive elements, sequentially selects one of the held plurality of analog signals, and inputs the analog signals to the comparator. This has the effect of allowing multiple columns to share a capacitive multiplexer.
　また、この第１の側面において、所定のリセットレベルと露光量に応じた信号レベルとの差分を求めて上記アナログ信号として供給するカラムアンプをさらに具備してもよい。これにより、リセット時のノイズが低減するという作用をもたらす。 In addition, the first aspect may further include a column amplifier that obtains a difference between a predetermined reset level and a signal level corresponding to the amount of exposure and supplies it as the analog signal. This brings about the effect of reducing noise at the time of resetting.
　また、この第１の側面において、上記リセットコードに基づいて補正量を求める前段処理部と、上記補正量に基づいて上記逐次比較ロジック回路からのデジタル信号に対するリセットコード処理を行うリセットコード処理部をさらに具備し、上記リセット制御部は、所定の初期値のコードに対して所定の演算を行ったコードを上記リセットコードとして供給し、上記前段処理部は、上記リセットコードに応じた上記補正量を上記リセットコード処理部に供給し、上記逐次比較ロジック回路は、所定数の上記比較結果に基づいて上記デジタル信号を生成してもよい。これにより、デジタル信号のリセットコードが処理されるという作用をもたらす。 Further, in this first aspect, a pre-processing unit that obtains a correction amount based on the reset code, and a reset code processing unit that performs reset code processing on the digital signal from the successive approximation logic circuit based on the correction amount. Further, the reset control unit supplies a code obtained by performing a predetermined operation on a code of a predetermined initial value as the reset code, and the pre-processing unit calculates the correction amount according to the reset code. The digital signal may be supplied to the reset code processing unit, and the successive approximation logic circuit may generate the digital signal based on a predetermined number of the comparison results. This brings about the effect of processing the reset code of the digital signal.
　また、この第１の側面において、上記演算は、ディザ信号の加算を含むものであってもよい。これにより、ディザ信号が印加されるという作用をもたらす。 In addition, in this first aspect, the calculation may include addition of dither signals. This brings about the effect of applying a dither signal.
　また、この第１の側面において、上記演算は、前回値に所定値を加算または減算する処理を含むものであってもよい。これにより、演算が簡易化されるという作用をもたらす。 Also, in the first aspect, the above calculation may include a process of adding or subtracting a predetermined value to or from the previous value. This brings about the effect of simplifying the calculation.
　また、本技術の第２の側面は、アナログ信号を生成する画素と、上記アナログ信号と所定の参照信号とから比較結果を生成するコンパレータと、上記参照信号を供給するデジタルアナログ変換器と、所定のリセットコードにより上記参照信号を初期化させた後に上記比較結果に基づいて上記参照信号を更新させる逐次比較ロジック回路と、上記リセットコードの値を制御するリセット制御部とを具備する固体撮像素子である。これにより、画像データの固定パターンノイズが低減するという作用をもたらす。 A second aspect of the present technology includes a pixel that generates an analog signal, a comparator that generates a comparison result from the analog signal and a predetermined reference signal, a digital-to-analog converter that supplies the reference signal, a predetermined A solid-state imaging device comprising: a successive approximation logic circuit that initializes the reference signal by the reset code of and then updates the reference signal based on the comparison result; and a reset control unit that controls the value of the reset code be. This brings about the effect of reducing the fixed pattern noise of the image data.
本技術の第１の実施の形態における撮像装置の一構成例を示すブロック図である。It is a block diagram showing an example of 1 composition of an imaging device in a 1st embodiment of this art. 本技術の第１の実施の形態における固体撮像素子の積層構造の一例を示す図である。It is a figure showing an example of lamination structure of a solid-state image sensor in a 1st embodiment of this art. 本技術の第１の実施の形態における固体撮像素子の一構成例を示すブロック図である。It is a block diagram showing an example of 1 composition of a solid-state image sensing device in a 1st embodiment of this art. 本技術の第１の実施の形態における画素の一構成例を示す回路図である。It is a circuit diagram showing a configuration example of a pixel in the first embodiment of the present technology. 本技術の第１の実施の形態におけるアナログデジタル変換部の一構成例を示すブロック図である。It is a block diagram which shows one structural example of the analog-digital-conversion part in 1st Embodiment of this technique. 本技術の第１の実施の形態におけるカラムアンプの一構成例を示す回路図である。It is a circuit diagram showing an example of composition of a column amplifier in a 1st embodiment of this art. 本技術の第１の実施の形態における容量マルチプレクサの一構成例を示す回路図である。It is a circuit diagram showing a configuration example of a capacitive multiplexer in the first embodiment of the present technology. 本技術の第１の実施の形態におけるＳＡＲＡＤＣおよびデジタル信号処理部の一構成例を示すブロック図である。It is a block diagram showing an example of composition of SARADC and a digital signal processing part in a 1st embodiment of this art. 本技術の第１の実施の形態におけるアナログデジタル変換部およびデジタル信号処理部の一構成例を示すブロック図である。It is a block diagram showing an example of composition of an analog digital conversion part and a digital signal processing part in a 1st embodiment of this art. 本技術の第１の実施の形態における画素、カラムアンプおよび容量マルチプレクサの制御の一例を示すタイミングチャートである。4 is a timing chart showing an example of control of pixels, column amplifiers, and capacitive multiplexers according to the first embodiment of the present technology; 本技術の第１の実施の形態における容量マルチプレクサおよびＳＡＲＡＤＣの制御の一例を示すタイミングチャートである。It is a timing chart showing an example of control of a capacity multiplexer and SARADC in a 1st embodiment of this art. 比較例における容量マルチプレクサおよびＳＡＲＡＤＣの制御の一例を示すタイミングチャートである。5 is a timing chart showing an example of control of a capacitance multiplexer and SARADC in a comparative example; 本技術の第１の実施の形態におけるリセットコード処理を説明するための図である。It is a figure for explaining reset code processing in a 1st embodiment of this art. 比較例と本技術の第１の実施の形態とにおけるノイズ特性を示すグラフである。6 is a graph showing noise characteristics in a comparative example and the first embodiment of the present technology; 本技術の第１の実施の形態における固体撮像素子の動作の一例を示すフローチャートである。It is a flow chart which shows an example of operation of a solid-state image sensing device in a 1st embodiment of this art. 本技術の第２の実施の形態におけるアナログデジタル変換部およびデジタル信号処理部の一構成例を示すブロック図である。It is a block diagram showing an example of composition of an analog digital conversion part and a digital signal processing part in a 2nd embodiment of this art. 本技術の第２の実施の形態におけるＳＡＲＡＤＣのリセットコードの制御例を示すタイミングチャートである。9 is a timing chart showing a control example of a reset code of SAR ADC in the second embodiment of the present technology; 本技術の第２の実施の形態における、隣接するＳＡＲＡＤＣのリセットコードの制御例を示すタイミングチャートである。9 is a timing chart showing an example of control of reset codes of adjacent SAR ADCs in the second embodiment of the present technology; 本技術の第２の実施の形態におけるノイズ特性の一例を示す図である。It is a figure showing an example of the noise characteristic in a 2nd embodiment of this art. 本技術の第２の実施の形態におけるリセットコードの別の制御例を示すタイミングチャートである。9 is a timing chart showing another control example of the reset code according to the second embodiment of the present technology; 車両制御システムの概略的な構成例を示すブロック図である。1 is a block diagram showing a schematic configuration example of a vehicle control system; FIG. 撮像部の設置位置の一例を示す説明図である。FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit;
　以下、本技術を実施するための形態（以下、実施の形態と称する）について説明する。説明は以下の順序により行う。
　１．第１の実施の形態（行毎に異なる値にリセットコードを制御する例）
　２．第２の実施の形態（行毎、列毎に異なる値にリセットコードを制御する例）
　３．移動体への応用例 Hereinafter, a form for carrying out the present technology (hereinafter referred to as an embodiment) will be described. Explanation will be given in the following order.
1. First embodiment (example of controlling the reset code to a different value for each row)
2. Second Embodiment (Example of controlling the reset code to a different value for each row and each column)
3. Example of application to mobile objects
　＜１．第１の実施の形態＞
　［撮像装置の構成例］
　図１は、本技術の第１の実施の形態における撮像装置１００の一構成例を示すブロック図である。この撮像装置１００は、画像データを撮像するための装置であり、光学部１１０、固体撮像素子２００およびＤＳＰ（Digital Signal Processing）回路１２０を備える。さらに撮像装置１００は、表示部１３０、操作部１４０、バス１５０、フレームメモリ１６０、記憶部１７０および電源部１８０を備える。撮像装置１００としては、例えば、デジタルスチルカメラなどのデジタルカメラの他、撮像機能を持つスマートフォンやパーソナルコンピュータ、車載カメラ等が想定される。 <1. First Embodiment>
[Configuration example of imaging device]
FIG. 1 is a block diagram showing a configuration example of an imaging device 100 according to the first embodiment of the present technology. This imaging device 100 is a device for capturing image data, and includes an optical section 110 , a solid-state imaging device 200 and a DSP (Digital Signal Processing) circuit 120 . The imaging device 100 further includes a display section 130 , an operation section 140 , a bus 150 , a frame memory 160 , a storage section 170 and a power supply section 180 . As the imaging device 100, for example, in addition to a digital camera such as a digital still camera, a smart phone, a personal computer, an in-vehicle camera, and the like having an imaging function are assumed.
　光学部１１０は、被写体からの光を集光して固体撮像素子２００に導くものである。固体撮像素子２００は、垂直同期信号ＶＳＹＮＣに同期して、光電変換により画像データを生成するものである。ここで、垂直同期信号ＶＳＹＮＣは、撮像のタイミングを示す所定周波数の周期信号である。固体撮像素子２００は、生成した画像データをＤＳＰ回路１２０に信号線２０９を介して供給する。 The optical unit 110 collects light from a subject and guides it to the solid-state imaging device 200 . The solid-state imaging device 200 generates image data by photoelectric conversion in synchronization with the vertical synchronization signal VSYNC. Here, the vertical synchronizing signal VSYNC is a periodic signal with a predetermined frequency that indicates the timing of imaging. The solid-state imaging device 200 supplies the generated image data to the DSP circuit 120 via the signal line 209 .
　ＤＳＰ回路１２０は、固体撮像素子２００からの画像データに対して所定の信号処理を実行するものである。このＤＳＰ回路１２０は、処理後の画像データをバス１５０を介してフレームメモリ１６０などに出力する。 The DSP circuit 120 executes predetermined signal processing on the image data from the solid-state imaging device 200 . The DSP circuit 120 outputs the processed image data to the frame memory 160 or the like via the bus 150 .
　表示部１３０は、画像データを表示するものである。表示部１３０としては、例えば、液晶パネルや有機ＥＬ（Electro Luminescence）パネルが想定される。操作部１４０は、ユーザの操作に従って操作信号を生成するものである。 The display unit 130 displays image data. As the display unit 130, for example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed. The operation unit 140 generates an operation signal according to user's operation.
　バス１５０は、光学部１１０、固体撮像素子２００、ＤＳＰ回路１２０、表示部１３０、操作部１４０、フレームメモリ１６０、記憶部１７０および電源部１８０が互いにデータをやりとりするための共通の経路である。 The bus 150 is a common path through which the optical unit 110, the solid-state imaging device 200, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170, and the power supply unit 180 exchange data with each other.
　フレームメモリ１６０は、画像データを保持するものである。記憶部１７０は、画像データなどの様々なデータを記憶するものである。電源部１８０は、固体撮像素子２００、ＤＳＰ回路１２０や表示部１３０などに電源を供給するものである。 The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the solid-state imaging device 200, the DSP circuit 120, the display unit 130, and the like.
　［固体撮像素子の構成例］
　図２は、本技術の第１の実施の形態における固体撮像素子２００の積層構造の一例を示す図である。この固体撮像素子２００は、回路チップ２０２と、その回路チップ２０２に積層された受光チップ２０１とを備える。これらのチップは、ビアなどの接続部を介して電気的に接続される。なお、ビアの他、Ｃｕ－Ｃｕ接合やバンプにより接続することもできる。 [Configuration example of solid-state imaging device]
FIG. 2 is a diagram showing an example of the layered structure of the solid-state imaging device 200 according to the first embodiment of the present technology. This solid-state imaging device 200 comprises a circuit chip 202 and a light receiving chip 201 laminated on the circuit chip 202 . These chips are electrically connected through connections such as vias. In addition to vias, Cu--Cu bonding or bumps may be used for connection.
　図３は、本技術の第１の実施の形態における固体撮像素子２００の一構成例を示すブロック図である。この固体撮像素子２００は、垂直走査回路２１１、タイミング制御回路２１２、画素アレイ部２２０、アナログデジタル変換部３００およびデジタル信号処理部２４０を備える。画素アレイ部２２０には、複数の画素２３０が二次元格子状に配列される。以下、水平方向に配列された画素２３０の集合を「行」と称し、行に垂直な方向に配列された画素２３０の集合を「列」と称する。 FIG. 3 is a block diagram showing one configuration example of the solid-state imaging device 200 according to the first embodiment of the present technology. This solid-state imaging device 200 includes a vertical scanning circuit 211 , a timing control circuit 212 , a pixel array section 220 , an analog-to-digital conversion section 300 and a digital signal processing section 240 . A plurality of pixels 230 are arranged in a two-dimensional grid in the pixel array section 220 . Hereinafter, a set of pixels 230 arranged in the horizontal direction will be referred to as a "row", and a set of pixels 230 arranged in the direction perpendicular to the row will be referred to as a "column".
　画素アレイ部２２０は、例えば、受光チップ２０１に配置される。また、垂直走査回路２１１、タイミング制御回路２１２、アナログデジタル変換部３００およびデジタル信号処理部２４０は、例えば、回路チップ２０２に配置される。 The pixel array section 220 is arranged in the light receiving chip 201, for example. Also, the vertical scanning circuit 211, the timing control circuit 212, the analog-to-digital converter 300, and the digital signal processor 240 are arranged on the circuit chip 202, for example.
　垂直走査回路２１１は、行を順に選択して駆動し、画素信号を出力させるものである。画素２３０は、アナログの画素信号を生成してアナログデジタル変換部３００に出力するものである。アナログデジタル変換部３００は、各列の画素信号に対してＡＤ変換を行い、デジタル信号をデジタル信号処理部２４０に供給するものである。デジタル信号処理部２４０は、デジタル信号に対して所定の信号処理を行うものである。信号処理後のデジタル信号を配列したデータは、画像データとしてＤＳＰ回路１２０に供給される。 The vertical scanning circuit 211 sequentially selects and drives rows to output pixel signals. The pixels 230 generate analog pixel signals and output them to the analog-to-digital converter 300 . The analog-to-digital conversion section 300 performs AD conversion on the pixel signal of each column and supplies the digital signal to the digital signal processing section 240 . The digital signal processing section 240 performs predetermined signal processing on the digital signal. Data obtained by arranging the digital signals after signal processing is supplied to the DSP circuit 120 as image data.
　［画素回路の構成例］
　図４は、本技術の第１の実施の形態における画素２３０の一構成例を示す回路図である。この画素２３０は、光電変換素子２３１、転送トランジスタ２３２、リセットトランジスタ２３３、浮遊拡散層２３４、増幅トランジスタ２３５および選択トランジスタ２３６を備える。 [Configuration example of pixel circuit]
FIG. 4 is a circuit diagram showing one configuration example of the pixel 230 according to the first embodiment of the present technology. This pixel 230 includes a photoelectric conversion element 231 , a transfer transistor 232 , a reset transistor 233 , a floating diffusion layer 234 , an amplification transistor 235 and a selection transistor 236 .
　光電変換素子２３１は、入射光に対する光電変換により電荷を生成するものである。転送トランジスタ２３２は、垂直走査回路２１１からの転送信号ＴＲＧに従って、光電変換素子２３１から浮遊拡散層２３４に電荷を転送するものである。リセットトランジスタ２３３は、垂直走査回路２１１からのリセット信号ＲＳＴに従って、浮遊拡散層２３４を初期化するものである。浮遊拡散層２３４は、転送された電荷量に応じた電圧を生成するものである。 The photoelectric conversion element 231 generates charges by photoelectric conversion of incident light. The transfer transistor 232 transfers charges from the photoelectric conversion element 231 to the floating diffusion layer 234 according to the transfer signal TRG from the vertical scanning circuit 211 . The reset transistor 233 initializes the floating diffusion layer 234 according to the reset signal RST from the vertical scanning circuit 211 . The floating diffusion layer 234 generates a voltage corresponding to the transferred charge amount.
　増幅トランジスタ２３５は、浮遊拡散層２３４の電圧を増幅するものである。選択トランジスタ２３６は、垂直走査回路２１１からの選択信号ＳＥＬに従って、増幅された電圧のアナログ信号を画素信号ＶＳＬとして垂直信号線２２９を介してアナログデジタル変換部３００に出力するものである。第ｍ（ｍは、整数）列の画素信号ＶＳＬを以下、ＶＳＬｍとする。 The amplification transistor 235 amplifies the voltage of the floating diffusion layer 234 . The selection transistor 236 outputs the amplified voltage analog signal as the pixel signal VSL to the analog-to-digital converter 300 via the vertical signal line 229 in accordance with the selection signal SEL from the vertical scanning circuit 211 . The pixel signal VSL of the m-th (m is an integer) column is hereinafter referred to as VSLm.
　ここで、リセット信号ＲＳＴにより浮遊拡散層２３４が初期化された際の画素信号ＶＳＬｍのレベルを「リセットレベル」または「Ｐ相」と称する。また、転送信号ＴＲＧにより電荷が転送された際の画素信号ＶＳＬｍのレベルを「信号レベル」または「Ｄ相」と称する。 Here, the level of the pixel signal VSLm when the floating diffusion layer 234 is initialized by the reset signal RST is called "reset level" or "P phase". Also, the level of the pixel signal VSLm when the charge is transferred by the transfer signal TRG is referred to as "signal level" or "D phase".
　［アナログデジタル変換部の構成例］
　図５は、本技術の第１の実施の形態におけるアナログデジタル変換部３００の一構成例を示すブロック図である。このアナログデジタル変換部３００は、複数のカラムアンプ３１０と、複数の容量マルチプレクサ４００と、複数のＳＡＲＡＤＣ３２０とを備える。 [Configuration example of analog-to-digital converter]
FIG. 5 is a block diagram showing a configuration example of the analog-to-digital converter 300 according to the first embodiment of the present technology. This analog-to-digital converter 300 includes a plurality of column amplifiers 310 , a plurality of capacitive multiplexers 400 and a plurality of SAR ADCs 320 .
　カラムアンプ３１０は、列毎に配置される。列数がＭ（Ｍは、整数）である場合、Ｍ個のカラムアンプ３１０が配置される。また、複数の列は、１つの容量マルチプレクサ４００を共有する。容量マルチプレクサ４００を２列で共有する場合、Ｍ／２個の容量マルチプレクサ４００が配置される。また、複数の列は、１つのＳＡＲＡＤＣ３２０を共有する。ＳＡＲＡＤＣ３２０を８列で共有する場合、Ｍ／８個のＳＡＲＡＤＣ３２０が配列される。 A column amplifier 310 is arranged for each column. When the number of columns is M (M is an integer), M column amplifiers 310 are arranged. Multiple columns also share one capacitive multiplexer 400 . When the capacitance multiplexers 400 are shared by two columns, M/2 capacitance multiplexers 400 are arranged. Also, multiple columns share one SAR ADC 320 . When the SAR ADC 320 is shared by 8 columns, M/8 SAR ADCs 320 are arranged.
　容量マルチプレクサ４００、ＳＡＲＡＤＣ３２０のそれぞれを共有する列数は、２列や８列に限定されない。ただし、ＳＡＲＡＤＣ３２０を共有する列数は、容量マルチプレクサ４００を共有する列数以上である。なお、列ごとにＳＡＲＡＤＣ３２０を配置することもできる。この場合には容量マルチプレクサ４００を設けなくてもよい。 The number of columns that share the capacitive multiplexer 400 and the SAR ADC 320 is not limited to 2 columns or 8 columns. However, the number of columns sharing the SAR ADC 320 is greater than or equal to the number of columns sharing the capacitance multiplexer 400 . Note that the SARADC 320 can also be arranged for each column. In this case, the capacitive multiplexer 400 may not be provided.
　カラムアンプ３１０は、対応する列の画素信号ＶＳＬｍのリセットレベルと信号レベルとの差分を求めるアナログＣＤＳ処理を行うものである。アナログＣＤＳ処理により、正味の信号レベルが得られる。カラムアンプ３１０は、アナログＣＤＳ処理後の画素信号を容量マルチプレクサ４００に供給する。例えば、第０列および第４列の画素信号ＶＳＬ０およびＶＳＬ４が０個目の容量マルチプレクサ４００に入力される。第１列および第５列の画素信号ＶＳＬ１およびＶＳＬ５が１個目の容量マルチプレクサ４００に入力される。第２列および第６列の画素信号ＶＳＬ２およびＶＳＬ６が２個目の容量マルチプレクサ４００に入力される。第３列および第７列の画素信号ＶＳＬ３およびＶＳＬ７が３個目の容量マルチプレクサ４００に入力される。第８列以降も同様に２列分の画素信号が容量マルチプレクサ４００に入力される。これらの画素信号ＶＳＬｍはシングルエンド信号である。 The column amplifier 310 performs analog CDS processing to obtain the difference between the reset level and the signal level of the pixel signal VSLm of the corresponding column. Analog CDS processing provides a net signal level. The column amplifier 310 supplies the pixel signal after analog CDS processing to the capacitance multiplexer 400 . For example, the pixel signals VSL0 and VSL4 of the 0th and 4th columns are input to the 0th capacitance multiplexer 400 . Pixel signals VSL1 and VSL5 of the first and fifth columns are input to the first capacitive multiplexer 400 . Pixel signals VSL2 and VSL6 of the second and sixth columns are input to the second capacitive multiplexer 400 . Pixel signals VSL3 and VSL7 of the third and seventh columns are input to the third capacitive multiplexer 400 . Pixel signals for two columns are similarly input to the capacitance multiplexer 400 for the eighth column and beyond. These pixel signals VSLm are single-ended signals.
　なお、カラムアンプ３１０がアナログＣＤＳ処理を行っているが、アナログＣＤＳ処理の代わりに、ＳＡＲＡＤＣ３２０の後段の回路がデジタルＣＤＳ処理を行うこともできる。この場合にはカラムアンプ３１０は、アナログＣＤＳ処理を実行しなくてもよい。 Although the column amplifier 310 performs analog CDS processing, a circuit subsequent to the SAR ADC 320 can perform digital CDS processing instead of analog CDS processing. In this case, the column amplifier 310 does not need to perform analog CDS processing.
　容量マルチプレクサ４００は、複数列の画素信号を容量素子（不図示）に保持し、それらの画素信号を順に選択してＳＡＲＡＤＣ３２０に入力するものである。 The capacitive multiplexer 400 holds pixel signals of a plurality of columns in capacitive elements (not shown), selects those pixel signals in order, and inputs them to the SAR ADC 320 .
　ＳＡＲＡＤＣ３２０は、逐次比較方式によりアナログの画素信号をデジタル信号Ｄｏｕｔに変換し、デジタル信号処理部２４０に供給するものである。また、ＳＡＲＡＤＣ３２０は、ＣＤＡＣ（Capacitor DAC）を備え、デジタル信号処理部２４０からのリセットコードＲＣに従って、ＣＤＡＣを初期化してからＡＤ変換を行う。 The SAR ADC 320 converts an analog pixel signal into a digital signal Dout by a successive approximation method, and supplies the digital signal Dout to the digital signal processing section 240 . The SAR ADC 320 also includes a CDAC (Capacitor DAC), and performs AD conversion after initializing the CDAC according to a reset code RC from the digital signal processing unit 240 .
　［カラムアンプの構成例］
　図６は、本技術の第１の実施の形態におけるカラムアンプ３１０の一構成例を示す回路図である。このカラムアンプ３１０は、アンプ３１１と、スイッチ３１２、３１３および３１６と、容量素子３１４および３１５とを備える。 [Configuration example of column amplifier]
FIG. 6 is a circuit diagram showing a configuration example of the column amplifier 310 according to the first embodiment of the present technology. This column amplifier 310 includes an amplifier 311 , switches 312 , 313 and 316 , and capacitive elements 314 and 315 .
　アンプ３１１の非反転入力端子（＋）は、垂直信号線２２９に接続され、画素アレイ部２２０からの画素信号ＶＳＬｍが入力される。また、アンプ３１１の出力端子は、容量マルチプレクサ４００に接続される。 A non-inverting input terminal (+) of the amplifier 311 is connected to the vertical signal line 229 and receives the pixel signal VSLm from the pixel array section 220 . Also, the output terminal of the amplifier 311 is connected to the capacitance multiplexer 400 .
　スイッチ３１２は、タイミング制御回路２１２からの制御信号Ｓｐに従ってアンプ３１１の出力端子と、反転入力端子（－）との間の経路を開閉するものである。スイッチ３１３は、タイミング制御回路２１２からの制御信号ＳＤに従ってアンプ３１１の出力端子と容量素子３１４との間の経路を開閉するものである。容量素子３１４および３１５は、スイッチ３１３と基準電位（例えば、グランド）との間において直列に接続され、それらの接続ノードは、アンプ３１１の反転入力端子（－）に接続される。 The switch 312 opens and closes the path between the output terminal of the amplifier 311 and the inverting input terminal (−) according to the control signal Sp from the timing control circuit 212 . The switch 313 opens and closes the path between the output terminal of the amplifier 311 and the capacitive element 314 according to the control signal SD from the timing control circuit 212 . Capacitive elements 314 and 315 are connected in series between switch 313 and a reference potential (eg, ground), and their connection node is connected to the inverting input terminal (−) of amplifier 311 .
　また、スイッチ３１６は、タイミング制御回路２１２からの制御信号ＳＶＲに従って、スイッチ３１３および容量素子３１４の接続ノードと、基準電位のカラムアンプ３１０の出力のゼロ電圧を規定するローカル基準電圧ＶＲとの間の経路を開閉するものである。 In addition, according to the control signal SVR from the timing control circuit 212, the switch 316 operates between the connection node of the switch 313 and the capacitive element 314 and the local reference voltage VR that defines the zero voltage of the output of the column amplifier 310 at the reference potential. It opens and closes the path of
　スイッチを閉状態にする際に、対応する制御信号にハイレベルが設定されるものとする。以下の回路についても同様である。 　When the switch is closed, the corresponding control signal is set to a high level. The same applies to the following circuits.
　タイミング制御回路２１２は、リセットレベルが入力された際にスイッチ３１２およびスイッチ３１６のみを閉状態に制御して容量素子３１４および３１５にリセットレベルを保持させる。また、タイミング制御回路２１２は、信号レベルが入力された際にスイッチ３１３のみを閉状態に制御する。容量素子３１４および３１５の接続ノードの電圧は、信号レベルと同じ値となるようにフィードバックがかかる。これにより、アンプ３１１は、リセットレベルと信号レベルとの差分を増幅した信号を画素信号ＶＳＬｍ'として出力する。このように、カラムアンプ３１０により、リセットレベル（Ｐ相）と信号レベル（Ｄ相）との差分を求めるアナログＣＤＳ処理が行われる。 When the reset level is input, the timing control circuit 212 controls only the switches 312 and 316 to the closed state to cause the capacitive elements 314 and 315 to hold the reset level. The timing control circuit 212 also closes only the switch 313 when the signal level is input. Feedback is applied so that the voltage at the connection node of capacitive elements 314 and 315 has the same value as the signal level. As a result, the amplifier 311 outputs a signal obtained by amplifying the difference between the reset level and the signal level as the pixel signal VSLm'. In this manner, the column amplifier 310 performs analog CDS processing for obtaining the difference between the reset level (P phase) and the signal level (D phase).
　［容量マルチプレクサの構成例］
　図７は、本技術の第１の実施の形態における容量マルチプレクサ４００の一構成例を示す回路図である。この容量マルチプレクサ４００は、サンプルホールドブロック４１０、４３０および４５０を備える。サンプルホールドブロック４１０は、スイッチ４１１乃至４１８と、容量素子４１９および４２０を備える。サンプルホールドブロック４３０は、スイッチ４３１乃至４３８と、容量素子４３９および４４０を備える。サンプルホールドブロック４５０は、スイッチ４５１乃至４５８と、容量素子４５９および４６０を備える。 [Configuration example of capacitive multiplexer]
FIG. 7 is a circuit diagram showing a configuration example of the capacitive multiplexer 400 according to the first embodiment of the present technology. This capacitive multiplexer 400 comprises sample and hold blocks 410 , 430 and 450 . The sample and hold block 410 includes switches 411 to 418 and capacitive elements 419 and 420 . The sample and hold block 430 includes switches 431 to 438 and capacitive elements 439 and 440 . The sample and hold block 450 includes switches 451 to 458 and capacitive elements 459 and 460 .
　スイッチ４１１は、タイミング制御回路２１２からの制御信号ＳＩＮ０Ａに従って、画素信号ＶＳＬ０'を供給する第０列のカラムアンプ３１０と容量素子４１９との間の経路を開閉するものである。スイッチ４１２は、タイミング制御回路２１２からの制御信号ＳＩＮ１Ａに従って、画素信号ＶＳＬ４'を供給する第４列のカラムアンプ３１０と容量素子４１９との間の経路を開閉するものである。 The switch 411 opens and closes the path between the column amplifier 310 of the 0th column that supplies the pixel signal VSL0′ and the capacitive element 419 according to the control signal SIN0A from the timing control circuit 212 . The switch 412 opens and closes the path between the column amplifier 310 of the fourth column that supplies the pixel signal VSL4′ and the capacitive element 419 according to the control signal SIN1A from the timing control circuit 212 .
　スイッチ４１３は、タイミング制御回路２１２からの制御信号ＳＩＮＡに従って、ローカル基準電圧ＶＲと容量素子４２０との間の経路を開閉するものである。スイッチ４１４は、タイミング制御回路２１２からの制御信号ＳＶＭＩＡ［ｎ］に従って、スイッチ４１１および容量素子４１９の接続ノードと、スイッチ４１３および容量素子４２０の接続ノードとの間の経路を開閉するものである。制御信号ＳＶＭＩＡ［ｎ］における添え字内のｎは、ＳＡＲＡＤＣ３２０を共有するＮ（例えば、４）個の容量マルチプレクサ４００のうちｎ（ｎは、０乃至Ｎの整数）個目を示す。以下の制御信号についても同様である。 The switch 413 opens and closes the path between the local reference voltage VR and the capacitive element 420 according to the control signal SINA from the timing control circuit 212 . The switch 414 opens and closes the path between the connection node of the switch 411 and the capacitance element 419 and the connection node of the switch 413 and the capacitance element 420 according to the control signal SVMIA[n] from the timing control circuit 212 . . The subscript n in the control signal S VMIA[n] indicates the n (n is an integer from 0 to N) out of the N (eg, 4) capacitive multiplexers 400 that share the SAR ADC 320 . The same applies to the following control signals.
　容量素子４１９は、スイッチ４１１および４１７の間に挿入される。容量素子４２０は、スイッチ４１３および４１８の間に挿入される。 A capacitive element 419 is inserted between switches 411 and 417 . A capacitive element 420 is inserted between switches 413 and 418 .
　スイッチ４１５および４１６は、容量素子４１９およびスイッチ４１７の接続ノードと、容量素子４２０およびスイッチ４１８の接続ノードとの間において、直列に接続される。これらのスイッチ４１５および４１６は、タイミング制御回路２１２からの制御信号ＳＶＭＡに従って、開閉する。また、スイッチ４１５および４１６の接続ノードはＳＡＲＡＤＣ３２０に接続され、コモン電圧ＶＣＲが印加される。 Switches 415 and 416 are connected in series between the connection node of capacitive element 419 and switch 417 and the connection node of capacitive element 420 and switch 418 . These switches 415 and 416 open and close according to the control signal SVMA from the timing control circuit 212 . A connection node of switches 415 and 416 is connected to SAR ADC 320 and receives common voltage VCR.
　スイッチ４１７は、タイミング制御回路２１２からの制御信号ＳＳＵＭＡ［ｎ］に従って、容量素子４１９とＳＡＲＡＤＣ３２０との間の経路を開閉するものである。スイッチ４１７が閉状態の際に、アナログの正側信号ＳＨ＋がＳＡＲＡＤＣ３２０へ出力される。 The switch 417 opens and closes the path between the capacitive element 419 and the SAR ADC 320 according to the control signal SSUMA[n] from the timing control circuit 212 . An analog positive signal SH+ is output to SAR ADC 320 when switch 417 is closed.
　スイッチ４１８は、タイミング制御回路２１２からの制御信号ＳＳＵＭＡ［ｎ］に従って、容量素子４２０とＳＡＲＡＤＣ３２０との間の経路を開閉するものである。スイッチ４１８が閉状態の際に、アナログの負側信号ＳＨ－がＳＡＲＡＤＣ３２０へ出力される。 The switch 418 opens and closes the path between the capacitive element 420 and the SAR ADC 320 according to the control signal SSUMA[n] from the timing control circuit 212 . An analog negative signal SH− is output to SAR ADC 320 when switch 418 is closed.
　サンプルホールドブロック４３０および４５０の回路構成は、サンプルホールドブロック４１０と同様である。ただし、サンプルホールドブロック４３０には、制御信号ＳＩＮ０Ｂ、ＳＩＮ１Ｂ、ＳＩＮＢ、ＳＶＭＩＢ［ｎ］、ＳＶＭＢ、ＳＳＵＭＢ［ｎ］が入力される。また、サンプルホールドブロック４５０には、制御信号ＳＩＮ０Ｃ、ＳＩＮ１Ｃ、ＳＩＮＣ、ＳＶＭＩＣ［ｎ］、ＳＶＭＣ、ＳＳＵＭＣ［ｎ］が入力される。 The circuit configurations of sample and hold blocks 430 and 450 are similar to sample and hold block 410 . However, the control signals S IN0B , S IN1B , S INB , S VMIB[n] , S VMB and S SUMB[n] are input to the sample hold block 430 . Also, the control signals S IN0C , S IN1C , S INC , S VMIC[n] , S VMC and S SUMC[n] are input to the sample hold block 450 .
　上述の回路のスイッチの制御方法の詳細については後述する。また、以下、サンプルホールドブロック４１０、４３０および４５０をブロックＡ、ＢおよびＣと称する。 The details of the method of controlling the switches in the circuit described above will be described later. Sample and hold blocks 410, 430 and 450 are also referred to as blocks A, B and C hereinafter.
　同図に例示した回路構成により、容量マルチプレクサ４００は、対応する２列のそれぞれの画素信号ＶＳＬｍ'（言い換えれば、シングルエンド信号）を差動信号に変換して保持する。そして、容量マルチプレクサ４００は、保持した２列分の画素信号（言い換えれば、差動信号）を順にＳＡＲＡＤＣ３２０に出力する。 With the circuit configuration illustrated in the figure, the capacitive multiplexer 400 converts the pixel signals VSLm' (in other words, single-ended signals) of the corresponding two columns into differential signals and holds them. Then, the capacitive multiplexer 400 sequentially outputs the held pixel signals for two columns (in other words, differential signals) to the SAR ADC 320 .
　なお、容量マルチプレクサ４００は、差動変換を行っているが、差動変換を行わずにシングルエンド信号のままで保持し、出力することもできる。この場合には、容量素子を半分に削減することができる。 Although the capacitive multiplexer 400 performs differential conversion, it is also possible to hold and output a single-ended signal without performing differential conversion. In this case, the number of capacitive elements can be reduced by half.
　［ＳＡＲＡＤＣおよびデジタル信号処理部の構成例］
　図８は、本技術の第１の実施の形態におけるＳＡＲＡＤＣ３２０およびデジタル信号処理部２４０の一構成例を示すブロック図である。ＳＡＲＡＤＣ３２０は、オートゼロスイッチ３２１および３２２と、プリアンプ３２３と、コンパレータ３２４と、ＣＤＡＣ３２５および３２６と、ＳＡＲロジック回路３２７とを備える。 [Configuration example of SAR ADC and digital signal processing unit]
FIG. 8 is a block diagram showing one configuration example of the SAR ADC 320 and the digital signal processing unit 240 according to the first embodiment of the present technology. SAR ADC 320 comprises autozero switches 321 and 322 , preamplifier 323 , comparator 324 , CDACs 325 and 326 and SAR logic circuit 327 .
　プリアンプ３２３の非反転入力端子（＋）には、容量マルチプレクサ４００からの正側信号ＳＨ＋が入力される。プリアンプ３２３の反転入力端子（－）には、容量マルチプレクサ４００からの負側信号ＳＨ－が入力される。また、プリアンプ３２３内の正側、負側のコモン電圧として、容量マルチプレクサ４００からのコモン電圧ＶＣＲが用いられる。プリアンプ３２３は、正側信号ＳＨ＋および負側信号ＳＨ－からなる差動信号を増幅し、コンパレータ３２４に差動出力する。この差動信号は、前述したように、差動変換された画素信号に該当する。 A positive side signal SH+ from the capacitance multiplexer 400 is input to the non-inverting input terminal (+) of the preamplifier 323 . The negative side signal SH- from the capacitance multiplexer 400 is input to the inverting input terminal (-) of the preamplifier 323 . Further, the common voltage VCR from the capacitance multiplexer 400 is used as the positive side and negative side common voltages in the preamplifier 323 . The preamplifier 323 amplifies a differential signal composed of the positive side signal SH+ and the negative side signal SH− and differentially outputs it to the comparator 324 . This differential signal corresponds to a differentially converted pixel signal, as described above.
　オートゼロスイッチ３２１は、タイミング制御回路２１２からの制御信号ＳＡＺに従って、プリアンプ３２３の非反転入力端子（＋）と非反転出力端子との間の経路を開閉するものである。オートゼロスイッチ３２２は、制御信号ＳＡＺに従って、プリアンプ３２３の反転入力端子（－）と反転出力端子との間の経路を開閉するものである。制御信号ＳＡＺの示すタイミングでオートゼロスイッチ３２１および３２２が閉状態に移行し、オートゼロが実行される。 The auto-zero switch 321 opens and closes the path between the non-inverting input terminal (+) and the non-inverting output terminal of the preamplifier 323 according to the control signal SAZ from the timing control circuit 212 . The auto-zero switch 322 opens and closes the path between the inverting input terminal (-) and the inverting output terminal of the preamplifier 323 according to the control signal SAZ . The auto-zero switches 321 and 322 are closed at the timing indicated by the control signal SAZ , and auto-zero is performed.
　コンパレータ３２４は、タイミング制御回路２１２からのクロック信号ＣＫＩに同期して、プリアンプ３２３の非反転出力端子の電位と反転出力端子の電位とを比較するものである。このコンパレータ３２４は、比較結果をＳＡＲロジック回路３２７に供給する。 The comparator 324 compares the potential of the non-inverting output terminal and the potential of the inverting output terminal of the preamplifier 323 in synchronization with the clock signal CKI from the timing control circuit 212 . This comparator 324 supplies the comparison result to the SAR logic circuit 327 .
　ＣＤＡＣ３２５は、ＳＡＲロジック回路３２７の制御に従って正側の参照信号を生成し、プリアンプ３２３の非反転入力端子（＋）に供給するものである。ＣＤＡＣ３２６は、ＳＡＲロジック回路３２７の制御に従って負側の参照信号を生成し、プリアンプ３２３の反転入力端子（－）に供給するものである。これらの参照信号により、画素信号（すなわち、差動信号）の値が増減する。このように、コンパレータ３２４の比較結果は、差動信号と参照信号とから得られたものである。例えば、比較結果は、差動信号を参照信号により増減した値が所定レベル（「０」など）より高いか否かを示す。なお、ＣＤＡＣ３２５および３２６は、特許請求の範囲に記載のデジタルアナログ変換部の一例である。 The CDAC 325 generates a positive side reference signal under the control of the SAR logic circuit 327 and supplies it to the non-inverting input terminal (+) of the preamplifier 323 . The CDAC 326 generates a negative side reference signal under the control of the SAR logic circuit 327 and supplies it to the inverting input terminal (-) of the preamplifier 323 . These reference signals increase or decrease the value of the pixel signal (that is, the differential signal). Thus, the comparison result of comparator 324 is obtained from the differential signal and the reference signal. For example, the comparison result indicates whether or not the value obtained by increasing or decreasing the differential signal with the reference signal is higher than a predetermined level (such as "0"). Note that the CDACs 325 and 326 are an example of the digital-analog converter described in the claims.
　ＳＡＲロジック回路３２７には、タイミング制御回路２１２からの制御信号ＳＡＺおよびクロック信号ＣＫと、デジタル信号処理部２４０からのリセットコードＲＣと、コンパレータ３２４からの比較結果とが入力される。リセットコードＲＣは、ＣＤＡＣ３２５および３２６からの参照信号の初期値を示すコードである。 The SAR logic circuit 327 receives the control signal SAZ and the clock signal CK from the timing control circuit 212 , the reset code RC from the digital signal processing section 240 , and the comparison result from the comparator 324 . Reset code RC is a code indicating the initial value of the reference signal from CDACs 325 and 326 .
　ＳＡＲロジック回路３２７は、制御信号ＳＡＺの示すオートゼロのタイミングでリセットコードＲＣにより参照信号を初期化する。初期化の後にＳＡＲロジック回路３２７は、比較結果に基づいて、正側または負側の参照信号を更新して差動信号を増減させる。増減する値は、比較のたびに前回値よりも小さくなるように制御される。これにより、二分探索が実現される。逐次比較は、クロック信号ＣＫＩに同期して実行され、所定回数分の比較結果を配列したデジタル信号がＤｏｕｔとしてデジタル信号処理部２４０に出力される。なお、ＳＡＲロジック回路３２７は、特許請求の範囲に記載の逐次比較ロジック回路の一例である。 The SAR logic circuit 327 initializes the reference signal with the reset code RC at the auto-zero timing indicated by the control signal SAZ . After initialization, the SAR logic circuit 327 updates the positive or negative side reference signal to increase or decrease the differential signal based on the comparison result. The incrementing or decrementing value is controlled to be smaller than the previous value for each comparison. This implements a binary search. The successive approximation is executed in synchronization with the clock signal CKI, and a digital signal in which comparison results for a predetermined number of times are arranged is output to the digital signal processing section 240 as Dout. The SAR logic circuit 327 is an example of the successive approximation logic circuit described in the claims.
　デジタル信号処理部２４０は、リセット制御部２４１と、前段処理部２４２と、複数のリセットコード処理部２４３と、後段処理部２４４とを備える。リセットコード処理部２４３は、ＳＡＲＡＤＣ３２０ごとに配置される。 The digital signal processing section 240 includes a reset control section 241 , a pre-processing section 242 , a plurality of reset code processing sections 243 and a post-processing section 244 . The reset code processing unit 243 is arranged for each SAR ADC 320 .
　リセット制御部２４１は、リセットコードＲＣの値を制御するものである。このリセット制御部２４１は、垂直走査回路２１１により行が駆動されるたびにリセットコードＲＣを前回値と異なる値に更新する。リセットコードＲＣを更新する場合、リセット制御部２４１は、例えば、所定の演算を実行し、その演算結果に更新する。 The reset control unit 241 controls the value of the reset code RC. The reset control unit 241 updates the reset code RC to a value different from the previous value every time the vertical scanning circuit 211 drives the row. When updating the reset code RC, the reset control unit 241 executes, for example, a predetermined calculation and updates to the calculation result.
　更新時の演算は、初期値のリセットコードとディザ信号との加算を含む。例えば、リセット制御部２４１は、更新のたびにディザ信号を生成し、初期値のリセットコードにディザ信号を加算した結果を新たなリセットコードとする。 　Arithmetic at the time of updating includes addition of the reset code of the initial value and the dither signal. For example, the reset control unit 241 generates a dither signal each time an update is performed, and sets the result of adding the dither signal to the reset code of the initial value as a new reset code.
　なお、更新時の演算は、前回値に所定値（「１」など）を加算または減算する処理を含むものであってもよい。この場合、例えば、リセット制御部２４１は、更新のたびに前回のリセットコードに対するインクリメントやデクリメントを行い、その結果を新たなリセットコードとする。 Note that the computation at the time of updating may include processing for adding or subtracting a predetermined value (such as "1") from the previous value. In this case, for example, the reset control unit 241 increments or decrements the previous reset code at each update, and uses the result as a new reset code.
　また、リセット制御部２４１は、ＡＤ変換の終了時に、更新後のリセットコードＲＣを前段処理部２４２に供給する。前段処理部２４２は、ＳＡＲＡＤＣ３２０からのデジタル信号Ｄｏｕｔをデコードしてリセットコード処理部２４３に供給する。デコードは、例えば、デジタル信号Ｄｏｕｔがバイナリデータの場合、１０進数に変換する処理を含む。なお、デジタル信号Ｄｏｕｔのデコードの際にリニアリティ補正を同時に行うこともできる。また、前段処理部２４２は、更新後のリセットコードＲＣをデコードして補正量を求め、リセットコード処理部２４３に供給する。 Also, the reset control unit 241 supplies the updated reset code RC to the pre-processing unit 242 at the end of the AD conversion. The pre-processing unit 242 decodes the digital signal Dout from the SAR ADC 320 and supplies it to the reset code processing unit 243 . For example, when the digital signal Dout is binary data, decoding includes processing to convert it into decimal numbers. Note that linearity correction can be performed simultaneously with decoding of the digital signal Dout. The pre-processing unit 242 also decodes the updated reset code RC to obtain a correction amount, and supplies it to the reset code processing unit 243 .
　リセットコード処理部２４３は、前段処理部２４２からの補正量に基づいて、デコード後のデジタル信号Ｄｏｕｔに対するリセットコード処理を行うものである。例えば、デジタル信号Ｄｏｕｔから補正量（言い換えれば、リセットコード）が減算される。リセットコード処理部２４３は、補正後のデジタル信号を後段処理部２４４に供給する。 The reset code processing unit 243 performs reset code processing on the decoded digital signal Dout based on the correction amount from the pre-processing unit 242 . For example, the correction amount (in other words, reset code) is subtracted from the digital signal Dout. The reset code processing unit 243 supplies the corrected digital signal to the post-processing unit 244 .
　後段処理部２４４は、リセットコード処理部２４３からのデジタル信号に対して、各種の後段処理を必要に応じて実行するものである。この後段処理部２４４は、処理後のデジタル信号をＤＳＰ回路１２０に供給する。 The post-processing unit 244 performs various post-processing on the digital signal from the reset code processing unit 243 as necessary. The post-processing section 244 supplies the processed digital signal to the DSP circuit 120 .
　なお、ＳＡＲＡＤＣ３２０は、差動信号をＡＤ変換しているが、シングルエンド信号をＡＤ変換することもできる。この場合、前段の容量マルチプレクサ４００が差動変換を行わない。また、ＣＤＡＣ３２５および３２６の一方が削減され、コンパレータ３２４は、画素信号と参照信号とを比較する。 The SAR ADC 320 AD converts differential signals, but can also AD convert single-ended signals. In this case, the previous-stage capacitive multiplexer 400 does not perform differential conversion. Also, one of the CDACs 325 and 326 is reduced and the comparator 324 compares the pixel signal with the reference signal.
　また、ＳＡＲＡＤＣ３２０およびデジタル信号処理部２４０を固体撮像素子２００内に配置しているが、この構成に限定されない。ＡＤ変換を行う回路であれば、固体撮像素子２００以外の回路にＳＡＲＡＤＣ３２０およびデジタル信号処理部２４０を配置することもできる。なお、ＳＡＲＡＤＣ３２０およびデジタル信号処理部２４０を配置した回路は、特許請求の範囲に記載のアナログデジタル変換回路の一例である。 Also, although the SAR ADC 320 and the digital signal processing unit 240 are arranged in the solid-state imaging device 200, the configuration is not limited to this. The SAR ADC 320 and the digital signal processing unit 240 can be arranged in a circuit other than the solid-state imaging device 200 as long as it is a circuit that performs AD conversion. The circuit in which the SAR ADC 320 and the digital signal processing unit 240 are arranged is an example of the analog-to-digital conversion circuit described in the claims.
　図９は、本技術の第１の実施の形態におけるアナログデジタル変換部３００およびデジタル信号処理部２４０の一構成例を示すブロック図である。同図においてカラムアンプ３１０は省略されている。 FIG. 9 is a block diagram showing one configuration example of the analog-to-digital converter 300 and the digital signal processor 240 according to the first embodiment of the present technology. The column amplifier 310 is omitted in FIG.
　８列でＳＡＲＡＤＣ３２０を共有する場合、８列毎にＳＡＲＡＤＣ３２０が設けられる。リセット制御部２４１は、ＳＡＲＡＤＣ３２０のそれぞれに同一のリセットコードＲＣを供給する。ただし、リセット制御部２４１は、垂直走査回路２１１により行が駆動されるたびに、ディザ信号により、リセットコードＲＣを前回値と異なる値に制御する。補正量についても同様に、リセットコード処理部２４３のそれぞれに同一の値が供給され、行が駆動されるたびに補正量が更新される。 When the SAR ADC 320 is shared by 8 columns, the SAR ADC 320 is provided every 8 columns. The reset control unit 241 supplies the same reset code RC to each of the SAR ADCs 320 . However, every time the vertical scanning circuit 211 drives a row, the reset control unit 241 controls the reset code RC to a value different from the previous value by a dither signal. Similarly, the same value is supplied to each of the reset code processing units 243 for the correction amount, and the correction amount is updated each time the row is driven.
　行ごとにリセットコードＲＣを異なる値にすることにより、列方向に生じる固定パターンノイズを抑制することができる。 By setting the reset code RC to a different value for each row, fixed pattern noise occurring in the column direction can be suppressed.
　［固体撮像素子の動作例］
　図１０は、本技術の第１の実施の形態における画素２３０、カラムアンプ３１０および容量マルチプレクサ４００の制御の一例を示すタイミングチャートである。 [Operation example of solid-state imaging device]
FIG. 10 is a timing chart showing an example of control of the pixels 230, the column amplifiers 310 and the capacitance multiplexer 400 according to the first embodiment of the present technology.
　タイミングＴ０乃至Ｔ１のＤ相セトリング期間において、垂直走査回路２１１は、選択した行に転送信号ＴＲＧを供給し、行内の画素２３０に信号レベルを生成させる。 During the D-phase settling period from timing T0 to T1, the vertical scanning circuit 211 supplies the transfer signal TRG to the selected row to cause the pixels 230 in the row to generate signal levels.
　また、そのＤ相セトリング期間において、タイミング制御回路２１２は、一定期間に亘ってハイレベルの制御信号ＳＤを供給し、カラムアンプ３１０にアナログＣＤＳ処理を実行させる。また、タイミング制御回路２１２は、一定期間に亘ってハイレベルの制御信号ＳＩＮ、ＳＩＮ０Ａ、ＳＩＮ１Ｂ、ＳＶＭＡおよびＳＶＭＢを供給する。制御信号ＳＩＮは、ＳＩＮＡ、ＳＩＮＢおよびＳＩＮＣを含むものとする。これらの制御信号により、容量マルチプレクサ４００は、ブロックＡおよびブロックＢに、対応する２列分の画素信号を保持する。 Also, during the D-phase settling period, the timing control circuit 212 supplies a high-level control signal SD for a certain period of time to cause the column amplifier 310 to perform analog CDS processing. Timing control circuit 212 also provides high level control signals S IN , S IN0A , S IN1B , S VMA and S VMB for a certain period of time. The control signal S IN shall include S INA , S INB and S INC . These control signals cause the capacitive multiplexer 400 to hold pixel signals for the corresponding two columns in the block A and block B. FIG.
　ＳＡＲＡＤＣ３２０を共有する４つのうち１つ目の容量マルチプレクサ４００は、例えば、第０列および第４列の画素信号を保持し、２つ目の容量マルチプレクサ４００は、例えば、第１列および第５列の画素信号を保持する。３つ目の容量マルチプレクサ４００は、例えば、第２列および第６列の画素信号を保持し、４つ目の容量マルチプレクサ４００は、例えば、第３列および第７列の画素信号を保持する。８列目以降も同様である。これにより、１行分の画素信号が保持される。 The first of the four capacitive multiplexers 400 that share the SARADC 320 holds, for example, pixel signals for columns 0 and 4, and the second capacitive multiplexer 400 holds, for example, columns 1 and 5. holds the pixel signals of A third capacitive multiplexer 400 holds, for example, the pixel signals of the second and sixth columns, and a fourth capacitive multiplexer 400 holds, for example, the pixel signals of the third and seventh columns. The same applies to the eighth and subsequent columns. Thus, pixel signals for one row are held.
　タイミングＴ１乃至Ｔ２のＰ相セトリング期間において、垂直走査回路２１１は、選択した行にリセット信号ＲＳＴを供給し、行内の画素２３０にリセットレベルを生成させる。 During the P-phase settling period from timings T1 to T2, the vertical scanning circuit 211 supplies the reset signal RST to the selected row, causing the pixels 230 in the row to generate the reset level.
　また、そのＰ相セトリング期間において、タイミング制御回路２１２は、一定期間に亘ってハイレベルの制御信号ＳＰおよびＳＶＲを供給し、カラムアンプ３１０にリセットレベルを保持させる。 During the P -phase settling period, the timing control circuit 212 supplies high-level control signals SP and SVR for a certain period of time to cause the column amplifier 310 to hold the reset level.
　次のタイミングＴ２乃至Ｔ３のＤ相セトリング期間の画素２３０およびカラムアンプ３１０の制御内容は、前回のＤ相セトリング期間と同様である。一方、容量マルチプレクサ４００に対してタイミング制御回路２１２は、一定期間に亘ってハイレベルの制御信号ＳＩＮ、ＳＩＮ１Ａ、ＳＩＮ０Ｃ、ＳＶＭＡおよびＳＶＭＣを供給する。これらの制御信号により、容量マルチプレクサ４００は、ブロックＡおよびブロックＣに、対応する２列分の画素信号を保持する。 The control contents of the pixels 230 and the column amplifiers 310 during the D-phase settling period from timings T2 to T3 are the same as those during the previous D-phase settling period. On the other hand, the timing control circuit 212 supplies the high level control signals S IN , S IN1A , S IN0C , S VMA and S VMC to the capacitive multiplexer 400 for a certain period of time. These control signals cause the capacitive multiplexer 400 to hold pixel signals for two corresponding columns in blocks A and C. FIG.
　次のタイミングＴ３乃至Ｔ４のＰ相セトリング期間の制御内容は、前回のＰ相セトリング期間と同様である。 The control contents of the P-phase settling period of the next timings T3 to T4 are the same as the previous P-phase settling period.
　次のタイミングＴ４乃至Ｔ５のＤ相セトリング期間の画素２３０およびカラムアンプ３１０の制御内容は、前回のＤ相セトリング期間と同様である。一方、容量マルチプレクサ４００に対してタイミング制御回路２１２は、一定期間に亘ってハイレベルの制御信号ＳＩＮ、ＳＩＮ０Ｂ、ＳＩＮ１Ｃ、ＳＶＭＢおよびＳＶＭＣを供給する。これらの制御信号により、容量マルチプレクサ４００は、ブロックＢおよびブロックＣに、対応する２列分の画素信号を保持する。 The control contents of the pixels 230 and the column amplifiers 310 during the D-phase settling period from timings T4 to T5 are the same as those during the previous D-phase settling period. On the other hand, the timing control circuit 212 supplies the high level control signals S IN , S IN0B , S IN1C , S VMB and S VMC to the capacitive multiplexer 400 for a certain period of time. These control signals cause the capacitance multiplexer 400 to hold the pixel signals for the corresponding two columns in the blocks B and C. As shown in FIG.
　タイミングＴ５以降は、全行が選択されるまで同様の制御が繰り返し実行される。 After timing T5, similar control is repeatedly executed until all rows are selected.
　図１１は、本技術の第１の実施の形態における容量マルチプレクサ４００およびＳＡＲＡＤＣ３２０の制御の一例を示すタイミングチャートである。 FIG. 11 is a timing chart showing an example of control of the capacitance multiplexer 400 and the SAR ADC 320 according to the first embodiment of the present technology.
　前述したように、タイミングＴ０乃至Ｔ１のＤ相セトリング期間において、ＳＡＲＡＤＣ３２０を共有する４つの容量マルチプレクサ４００は、８列分の画素信号を保持する。 As described above, during the D-phase settling period from timing T0 to T1, the four capacitive multiplexers 400 sharing the SAR ADC 320 hold pixel signals for eight columns.
　タイミングＴ１乃至Ｔ２のＰ相セトリング期間において、タイミング制御回路２１２は、制御信号ＳＳＵＭＡ［０］、ＳＳＵＭＡ［１］、ＳＳＵＭＡ［２］およびＳＳＵＭＡ［３］を順に供給する。また、制御信号ＳＶＭＩＡ［０］、ＳＶＭＩＡ［１］、ＳＶＭＩＡ［２］およびＳＶＭＩＡ［３］も順に供給される。これにより、ＳＡＲＡＤＣ３２０を共有する４つの容量マルチプレクサ４００のそれぞれのブロックＡに保持された画素信号が順に出力される。 During the P-phase settling period of timings T1 to T2, the timing control circuit 212 sequentially supplies control signals S SUMA[0] , S SUMA[1] , S SUMA[2] and S SUMA[3] . Control signals S-- VMIA[0] , S-- VMIA[1] , S-- VMIA[2] and S-- VMIA[3] are also provided in sequence. As a result, the pixel signals held in the respective blocks A of the four capacitive multiplexers 400 sharing the SAR ADC 320 are sequentially output.
　また、ＳＡＲＡＤＣ３２０は、クロック信号ＣＫに同期して、ブロックＡからの４つの画素信号のそれぞれを順にＡＤ変換する。 In addition, the SAR ADC 320 AD-converts each of the four pixel signals from the block A in sequence in synchronization with the clock signal CK.
　クロック信号ＣＫがローレベルの期間内にハイレベルの制御信号ＳＡＺが供給され、その期間内にＳＡＲＡＤＣ３２０は、リセットコードＲＣを用いてオートゼロを行う。クロック信号ＣＫがハイレベルの期間内に、そのクロック信号ＣＫより周波数の高いクロック信号ＣＫＩが供給され、ＳＡＲＡＤＣ３２０は、そのクロック信号ＣＫＩに同期して逐次比較を行う。 A high-level control signal SAZ is supplied while the clock signal CK is at a low level, and the SAR ADC 320 performs auto-zeroing using the reset code RC during that period. While the clock signal CK is at high level, a clock signal CKI having a frequency higher than that of the clock signal CK is supplied, and the SAR ADC 320 performs successive approximation in synchronization with the clock signal CKI.
　次のタイミングＴ２乃至Ｔ３のＤ相セトリング期間において、タイミング制御回路２１２は、制御信号ＳＳＵＭＢ［０］、ＳＳＵＭＢ［１］、ＳＳＵＭＢ［２］およびＳＳＵＭＢ［３］を順に供給する。また、制御信号ＳＶＭＩＢ［０］、ＳＶＭＩＢ［１］、ＳＶＭＩＢ［２］およびＳＶＭＩＢ［３］も順に供給される。これにより、ＳＡＲＡＤＣ３２０を共有する４つの容量マルチプレクサ４００のそれぞれのブロックＢに保持された画素信号が順に出力される。 During the D-phase settling period of the next timings T2 to T3, the timing control circuit 212 sequentially supplies the control signals S SUMB[0] , S SUMB[1] , S SUMB[2] and S SUMB[3] . Control signals S-- VMIB[0] , S-- VMIB[1] , S-- VMIB[2] and S-- VMIB[3] are also provided in sequence. As a result, the pixel signals held in the respective blocks B of the four capacitive multiplexers 400 sharing the SAR ADC 320 are sequentially output.
　また、ＳＡＲＡＤＣ３２０は、クロック信号ＣＫに同期して、ブロックＢからの４つの画素信号のそれぞれを順にＡＤ変換する。タイミングＴ１乃至Ｔ３までの期間内に、タイミングＴ０乃至Ｔ１の期間内に保持された８列分の画素信号がＡＤ変換される。複数のＳＤＲＡＤＣ３２０が並列に動作して、それぞれ８列分の画素信号をＡＤ変換することにより、１行分の画素信号が読み出される。このため、Ｐ相セトリング期間と、その直後のＤ相セトリング期間とからなる期間は、１行分のＡＤ変換期間に該当する。 In addition, the SAR ADC 320 sequentially AD-converts each of the four pixel signals from the block B in synchronization with the clock signal CK. During the period from timings T1 to T3, pixel signals for eight columns held during the period from timings T0 to T1 are AD-converted. A plurality of SDRADCs 320 operate in parallel to AD-convert pixel signals for eight columns, thereby reading pixel signals for one row. Therefore, a period consisting of the P-phase settling period and the immediately following D-phase settling period corresponds to an AD conversion period for one row.
　次のタイミングＴ３乃至Ｔ４のＰ相セトリング期間において、ＳＡＲＡＤＣ３２０は、ブロックＣからの４つの画素信号のそれぞれを順にＡＤ変換する。次のタイミングＴ４乃至Ｔ５のＤ相セトリング期間において、ＳＡＲＡＤＣ３２０は、ブロックＡからの４つの画素信号のそれぞれを順にＡＤ変換する。 In the next P-phase settling period from timing T3 to T4, the SAR ADC 320 AD-converts each of the four pixel signals from block C in turn. During the next D-phase settling period from timing T4 to T5, the SAR ADC 320 AD-converts each of the four pixel signals from block A in turn.
　次のタイミングＴ５乃至Ｔ６のＰ相セトリング期間において、ＳＡＲＡＤＣ３２０は、ブロックＢからの４つの画素信号のそれぞれを順にＡＤ変換する。次のタイミングＴ６からのＤ相セトリング期間において、ＳＡＲＡＤＣ３２０は、ブロックＣからの４つの画素信号のそれぞれを順にＡＤ変換する。以降は、同様の制御が繰り返し実行される。 In the next P-phase settling period from timings T5 to T6, the SAR ADC 320 AD-converts each of the four pixel signals from block B in turn. In the D-phase settling period from the next timing T6, the SAR ADC 320 AD-converts each of the four pixel signals from block C in turn. After that, similar control is repeatedly executed.
　また、リセット制御部２４１は、１行分のＡＤ変換期間が経過する（言い換えれば、行が駆動される）たびに、リセットコードＲＣを前回値と異なる値に更新する。例えば、タイミングＴ１乃至Ｔ３のＡＤ変換期間にリセット制御部２４１は、前回のＲＣ＿ａと異なるＲＣ＿ｂに更新する。次のタイミングＴ３乃至Ｔ５のＡＤ変換期間にリセット制御部２４１は、前回のＲＣ＿ｂと異なるＲＣ＿ｃに更新する。以下、行が駆動されるたびにリセットコードが更新される。これにより各行について異なるリセットコードが設定される。 Also, the reset control unit 241 updates the reset code RC to a value different from the previous value every time the AD conversion period for one row passes (in other words, the row is driven). For example, during the AD conversion period of timings T1 to T3, the reset control unit 241 updates to RC_b different from the previous RC_a. The reset control unit 241 updates to RC_c different from the previous RC_b in the AD conversion period of the next timings T3 to T5. Below, the reset code is updated each time a row is driven. This sets a different reset code for each row.
　ここで、各行のリセットコードＲＣを一定とする構成を比較例として想定する。 Here, as a comparative example, assume a configuration in which the reset code RC of each row is constant.
　図１２は、比較例における容量マルチプレクサ４００およびＳＡＲＡＤＣ３２０の制御の一例を示すタイミングチャートである。同図に例示するように比較例では、リセットコードが更新されず、各行について同一のリセットコードが設定される。 FIG. 12 is a timing chart showing an example of control of the capacitance multiplexer 400 and SARADC 320 in the comparative example. As illustrated in the figure, in the comparative example, the reset code is not updated, and the same reset code is set for each row.
　図１３は、本技術の第１の実施の形態におけるリセットコード処理を説明するための図である。同図における縦軸は、デジタル信号Ｄｏｕｔの値を示し、横軸は、アナログの画素信号ＶＳＬのレベルを示す。同図におけるａは、ディザ信号を印加しない場合のリニアリティ特性を示す図である。同図におけるｂは、ディザ信号を印加し、リセットコード処理を行う前のリニアリティ特性を示す図である。同図におけるｃは、ディザ信号を印加し、リセットコード処理を行った後のリニアリティ特性を示す図である。 FIG. 13 is a diagram for explaining reset code processing in the first embodiment of the present technology. The vertical axis in the figure indicates the value of the digital signal Dout, and the horizontal axis indicates the level of the analog pixel signal VSL. In the figure, a is a diagram showing linearity characteristics when no dither signal is applied. b in the same figure is a diagram showing the linearity characteristic before the dither signal is applied and the reset code process is performed. In the same figure, c is a diagram showing linearity characteristics after applying a dither signal and performing reset code processing.
　同図におけるａに例示するように、ＣＤＡＣを用いるＳＡＲＡＤＣ３２０では、入力の画素信号と、出力のデジタル信号との関係が直線的にならないことがある。この場合に、ある画素信号ＶＳＬｍが、「６４」を示すデジタル信号Ｄｏｕｔに変換されるものとする。 As exemplified by a in the figure, in the SAR ADC 320 using the CDAC, the relationship between the input pixel signal and the output digital signal may not be linear. In this case, it is assumed that a certain pixel signal VSLm is converted into a digital signal Dout indicating "64".
　前述したように固定パターンノイズを抑制するためにリセット制御部２４１は、ディザ信号を初期値のリセットコードに印加して新たなリセットコードＲＣとする。同図において、初期値は、１０進数で「０」の値に設定されたものとする。ディザ信号の印加により、同図におけるｂに例示するように、ディザ信号印加後のリセットコードＲＣが初期値（「０」）と異なる値になるため、画素信号ＶＳＬｍに対応する値は、「９６」となり、「６４」から、大きくずれてしまう。なお、初期値は、「０」以外の値であってもよい。 As described above, in order to suppress fixed pattern noise, the reset control unit 241 applies a dither signal to the reset code of the initial value to generate a new reset code RC. In the figure, it is assumed that the initial value is set to "0" in decimal number. Due to the application of the dither signal, the reset code RC after application of the dither signal changes to a value different from the initial value (“0”), as illustrated by b in FIG. , which deviates greatly from "64". Note that the initial value may be a value other than "0".
　そこで、リセットコード処理部２４３は、ディザ信号印加後のリセットコードＲＣに対応する補正量Ｃｄによりデジタル信号Ｄｏｕｔに対するリセットコード処理を行う。同図におけるｃに例示するように、この補正により、画素信号ＶＳＬｍに対応する値は、「６６」となり、「６４」からのずれを小さくすることができる。同図に例示したように、ディザ信号に応じて、リニアリティの異なる部分でＡＤ変換を行うことができるため、リニアリティのくずれの影響を低減することができる。 Therefore, the reset code processing unit 243 performs reset code processing on the digital signal Dout using the correction amount Cd corresponding to the reset code RC after application of the dither signal. As exemplified by c in the figure, this correction makes the value corresponding to the pixel signal VSLm "66", and the deviation from "64" can be reduced. As illustrated in the figure, since AD conversion can be performed in portions with different linearities according to the dither signal, it is possible to reduce the influence of linearity breakdown.
　図１４は、比較例と本技術の第１の実施の形態とにおけるノイズ特性を示すグラフである。同図における縦軸は、縦方向の固定パターンノイズ（ＦＰＮ：Fixed Pattern Noise）を示し、横軸は、デジタル信号Ｄｏｕｔを示す。同図におけるａは、比較例のノイズ特性を示し、同図におけるｂは、第１の実施の形態のノイズ特性を示す。 FIG. 14 is a graph showing noise characteristics in the comparative example and the first embodiment of the present technology. In the figure, the vertical axis indicates fixed pattern noise (FPN) in the vertical direction, and the horizontal axis indicates the digital signal Dout. In the figure, a indicates the noise characteristics of the comparative example, and b indicates the noise characteristics of the first embodiment.
　同図に例示するように、ディザ信号を印加しない比較例と比較して、第１の実施の形態では、ディザ信号を印加したため、縦方向のＦＰＮを抑制することができる。 As illustrated in the figure, compared to the comparative example in which no dither signal is applied, in the first embodiment, since the dither signal is applied, FPN in the vertical direction can be suppressed.
　なお、特許文献１に記載のように、シングルスロープ型のＡＤＣをカラムごとに配置し、リセットレベルにランダムノイズを印加する方法でも、ある程度は固定パターンノイズを低減することができる。しかし、この方法は、シングルスロープ型のＡＤＣを用いることを前提としており、ＳＡＲＡＤＣを配置する構成に適用することができない。また、リセットレベルにランダムノイズを印加する必要があるため、リセットレベルと信号レベルとの差分を求めるアナログＣＤＳ処理を行うことができない。さらに、ランダムノイズをアナログ回路により生成する必要があり、その回路は不完全な製造ばらつきなどの影響を受けるため、一定の固定パターンノイズが生じるおそれがある。 As described in Patent Document 1, fixed pattern noise can also be reduced to some extent by arranging a single-slope ADC for each column and applying random noise to the reset level. However, this method assumes the use of a single-slope ADC and cannot be applied to a configuration in which a SAR ADC is arranged. Moreover, since it is necessary to apply random noise to the reset level, analog CDS processing for obtaining the difference between the reset level and the signal level cannot be performed. In addition, the random noise must be generated by analog circuitry, which is subject to imperfections such as manufacturing variations, which can result in constant, fixed-pattern noise.
　これに対して、第１の実施の形態では、ＳＡＲＡＤＣを用いることを前提としている。また、リセットレベルにランダムノイズを印加する必要が無いため、アナログＣＤＳ処理を行うことができる。さらに、ディザ信号などを印加したリセットコードを用いるため、デジタル設定を元に確定的にノイズを印加することができ、製造ばらつきの影響を受けない。 On the other hand, in the first embodiment, it is assumed that SARADC is used. Also, since there is no need to apply random noise to the reset level, analog CDS processing can be performed. Furthermore, since a reset code to which a dither signal or the like is applied is used, noise can be applied deterministically based on digital settings, and is not affected by manufacturing variations.
　図１５は、本技術の第１の実施の形態における固体撮像素子２００の動作の一例を示すフローチャートである。この動作は、例えば、画像データを撮像するための所定のアプリケーションが実行されたときに開始される。 FIG. 15 is a flow chart showing an example of the operation of the solid-state imaging device 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing image data is executed.
　垂直走査回路２１１は、読み出す行を選択する（ステップＳ９０１）。また、リセット制御部２４１は、行ごとに異なるリセットコードを設定する（ステップＳ９０２）。ＳＡＲＡＤＣ３２０は、オートゼロを行い、この際にリセットコードによりＣＤＳＣを初期化する（ステップＳ９０３）。そして、ＳＡＲＡＤＣ３２０は、逐次比較を行い、デジタル信号を生成する（ステップＳ９０４）。 The vertical scanning circuit 211 selects a row to read (step S901). Also, the reset control unit 241 sets a different reset code for each row (step S902). The SAR ADC 320 performs auto zero, and initializes the CDSC with a reset code (step S903). The SAR ADC 320 then performs successive approximation and generates a digital signal (step S904).
　また、デジタル信号処理部２４０は、リセットコードによりデジタル信号を補正する（ステップＳ９０５）。ＳＡＲＡＤＣ３２０は、最終行が読み出されたか否かを判断する（ステップＳ９０６）。最終行が読み出されていない場合（ステップＳ９０６：Ｎｏ）、固体撮像素子２００は、ステップＳ９０１以降を繰り返し実行する。最終行が読み出された場合（ステップＳ９０６：Ｙｅｓ）、固体撮像素子２００は、撮像のための動作を終了する。 Also, the digital signal processing unit 240 corrects the digital signal using the reset code (step S905). SARADC 320 determines whether the last row has been read (step S906). If the last line has not been read (step S906: No), the solid-state imaging device 200 repeatedly executes step S901 and subsequent steps. If the last line has been read (step S906: Yes), the solid-state imaging device 200 ends the operation for imaging.
　垂直同期信号に同期して複数枚の画像データを連続して撮像する場合、ステップＳ９０１乃至Ｓ９０６が垂直同期信号に同期して繰り返し実行される。 When continuously capturing a plurality of image data in synchronization with the vertical synchronization signal, steps S901 to S906 are repeatedly executed in synchronization with the vertical synchronization signal.
　このように、本技術の第１の実施の形態によれば、リセット制御部２４１が、行ごとに異なる値にリセットコードを制御するため、固定パターンノイズを抑制することができる。これにより、画素信号の信号品質を向上させることができる。 Thus, according to the first embodiment of the present technology, the reset control unit 241 controls the reset code to a different value for each row, so fixed pattern noise can be suppressed. Thereby, the signal quality of the pixel signal can be improved.
　＜２．第２の実施の形態＞
　上述の第１の実施の形態では、リセットコードを行ごとに異なる値に制御していたが、この構成では、行方向の固定パターンノイズを十分に抑制することができないおそれがある。この第２の実施の形態の固体撮像素子２００は、リセットコードを、行毎および列毎に異なる値に制御する点において第１の実施の形態と異なる。 <2. Second Embodiment>
In the first embodiment described above, the reset code is controlled to have a different value for each row, but with this configuration, there is a possibility that fixed pattern noise in the row direction cannot be sufficiently suppressed. The solid-state imaging device 200 of the second embodiment differs from the first embodiment in that the reset code is controlled to have different values for each row and each column.
　図１６は、本技術の第２の実施の形態におけるアナログデジタル変換部３００およびデジタル信号処理部２４０の一構成例を示すブロック図である。この第２の実施の形態のリセット制御部２４１は複数のＳＡＲＡＤＣ３２０のそれぞれに異なる値のリセットコードを供給する。 FIG. 16 is a block diagram showing one configuration example of the analog-to-digital converter 300 and the digital signal processor 240 according to the second embodiment of the present technology. The reset control unit 241 of the second embodiment supplies reset codes of different values to each of the plurality of SAR ADCs 320 .
　例えば、リセット制御部２４１は、ｋ（ｋは、整数）個目のＳＡＲＡＤＣ３２０にリセットコードＲＣ＿Ａを供給する。また、リセット制御部２４１は、リセットコードＲＣ＿Ａと異なるリセットコードＲＣ＿Ｂをディザ信号の印加などにより生成し、ｋ＋１個目のＳＡＲＡＤＣ３２０に供給する。 For example, the reset control unit 241 supplies the reset code RC_A to the k-th (k is an integer) SAR ADC 320 . Also, the reset control unit 241 generates a reset code RC_B different from the reset code RC_A by applying a dither signal or the like, and supplies it to the k+1 th SAR ADC 320 .
　図１７は、本技術の第２の実施の形態におけるｋ個目のＳＡＲＡＤＣ３２０のリセットコードの制御例を示すタイミングチャートである。リセット制御部２４１は、オートゼロのタイミングを示す制御信号ＳＡＺに同期して前回値と異なる値にリセットコードを制御する。オートゼロは、画素信号がＳＡＲＡＤＣ３２０に入力されるたび（言い換えれば、列毎）に実行されるため、列毎に異なるリセットコードが設定される。 FIG. 17 is a timing chart showing an example of reset code control of the k-th SAR ADC 320 according to the second embodiment of the present technology. The reset control unit 241 controls the reset code to a value different from the previous value in synchronization with the control signal SAZ indicating the auto-zero timing. Since auto-zeroing is performed each time a pixel signal is input to the SAR ADC 320 (in other words, for each column), a different reset code is set for each column.
　例えば、ｋ個目のＳＡＲＡＤＣ３２０を共有する複数列のうち第０列のオートゼロの際にリセット制御部２４１は、リセットコードＲＣ＿Ａ０を供給する。次の第１列のオートゼロの際にリセット制御部２４１は、リセットコードＲＣ＿Ａ０と異なるリセットコードＲＣ＿Ａ１をディザ信号の印加などにより生成し、ＳＡＲＡＤＣ３２０に供給する。また、第１の実施の形態と同様に、行毎に異なるリセットコードが設定される。 For example, the reset control unit 241 supplies the reset code RC_A0 when the 0th column among the plurality of columns sharing the kth SAR ADC 320 is auto-zeroed. At the time of auto-zeroing of the next first column, the reset control unit 241 generates a reset code RC_A1 different from the reset code RC_A0 by applying a dither signal or the like, and supplies it to the SAR ADC 320 . Also, as in the first embodiment, a different reset code is set for each row.
　図１８は、技術の第２の実施の形態におけるｋ＋１個目のＳＡＲＡＤＣ３２０のリセットコードの制御例を示すタイミングチャートである。リセット制御部２４１は、行毎および列毎に異なる値にリセットコードを制御する。 FIG. 18 is a timing chart showing an example of reset code control of the k+1th SAR ADC 320 in the second embodiment of the technology. The reset control unit 241 controls the reset code to different values for each row and each column.
　例えば、ｋ＋１個目のＳＡＲＡＤＣ３２０を共有する複数列のうち第０列のオートゼロの際にリセット制御部２４１は、リセットコードＲＣ＿Ｂ０を供給する。次の第１列のオートゼロの際にリセット制御部２４１は、リセットコードＲＣ＿Ｂ０と異なるリセットコードＲＣ＿Ｂ１をディザ信号の印加などにより生成し、ＳＡＲＡＤＣ３２０に供給する。 For example, the reset control unit 241 supplies the reset code RC_B0 during auto-zeroing of the 0th column among the plurality of columns sharing the k+1th SAR ADC 320 . At the next auto-zeroing of the first column, the reset control unit 241 generates a reset code RC_B1 different from the reset code RC_B0 by applying a dither signal or the like, and supplies it to the SAR ADC 320 .
　また、ｋ＋１個目のＳＡＲＡＤＣ３２０の第０列のリセットコードＲＣ＿Ｂ０は、ｋ個目のＳＡＲＡＤＣ３２０の第０列のリセットコードＲＣ＿Ａ０と異なる。ｋ＋１個目のＳＡＲＡＤＣ３２０の第１列のリセットコードＲＣ＿Ｂ１は、ｋ個目のＳＡＲＡＤＣ３２０の第１列のリセットコードＲＣ＿Ａ１と異なる。以降の列についても同様である。 Also, the reset code RC_B0 in the 0th column of the k+1 SAR ADC 320 is different from the reset code RC_A0 in the 0th column of the k th SAR ADC 320 . The first column reset code RC_B1 of the k+1 th SAR ADC 320 is different from the first column reset code RC_A1 of the k th SAR ADC 320 . The same applies to subsequent columns.
　図１６乃至図１８に例示したように、リセット制御部２４１は、行毎、列毎、さらに、ＳＡＲＡＤＣ３２０毎に、異なる値となるようにリセットコードを制御する。 As illustrated in FIGS. 16 to 18, the reset control unit 241 controls the reset code so that it has different values for each row, each column, and each SAR ADC 320 .
　図１９は、本技術の第２の実施の形態におけるノイズ特性の一例を示す図である。第２の実施の形態におけるリードアウトノイズは、第１の実施の形態と同一である。第２の実施の形態における画素のＦＰＮは、第１の実施の形態と同程度である。 FIG. 19 is a diagram showing an example of noise characteristics in the second embodiment of the present technology. Readout noise in the second embodiment is the same as in the first embodiment. The pixel FPN in the second embodiment is approximately the same as in the first embodiment.
　第２の実施の形態における行方向のＦＰＮレベルは、第１の実施の形態と比較して低下（改善）する。第２の実施の形態における行方向のＦＰＮ最大値も、第１の実施の形態と比較して改善する。また、第２の実施の形態において、列方向のＦＰＮレベル、列方向のＦＰＮ最大値は、第１の実施の形態と同程度である。 The FPN level in the row direction in the second embodiment is lowered (improved) compared to the first embodiment. The FPN maximum value in the row direction in the second embodiment is also improved compared to the first embodiment. In the second embodiment, the FPN level in the column direction and the FPN maximum value in the column direction are approximately the same as in the first embodiment.
　第２の実施の形態における行方向の一時ノイズレベルは、第１の実施の形態と比較して低下（改善）する。第２の実施の形態における行方向の一時ノイズ最大値も、第１の実施の形態と比較して改善する。また、第２の実施の形態において、列方向の一時ノイズレベル、列方向の一時ノイズ最大値は、第１の実施の形態と同一である。 The temporary noise level in the row direction in the second embodiment is reduced (improved) compared to the first embodiment. The row-wise transient noise maximum in the second embodiment is also improved compared to the first embodiment. In the second embodiment, the column-direction temporal noise level and the column-direction temporal noise maximum value are the same as in the first embodiment.
　同図に例示したように、第２の実施の形態では、行毎、列毎、ＳＡＲＡＤＣ３２０毎に異なるリセットコードを設定するため、行方向のノイズがさらに低減する。 As illustrated in the figure, in the second embodiment, different reset codes are set for each row, each column, and for each SAR ADC 320, so noise in the row direction is further reduced.
　なお、図２０におけるａに例示するように、リセット制御部２４１は、各列に同一のリセットコードを設定し、行毎、ＳＡＲＡＤＣ３２０毎に異なるリセットコードを設定することもできる。 Note that the reset control unit 241 can also set the same reset code for each column, and set a different reset code for each row and for each SAR ADC 320, as exemplified by a in FIG.
　また、同図におけるｂに例示するように、リセット制御部２４１は、複数のＳＡＲＡＤＣ３２０に同一のリセットコードを設定し、行毎、列毎に異なるリセットコードを設定することもできる。 Also, as exemplified by b in the figure, the reset control unit 241 can set the same reset code to a plurality of SAR ADCs 320, and set different reset codes for each row and each column.
　このように本技術の第２の実施の形態によれば、リセット制御部２４１が、行毎、列毎に異なる値にリセットコードを制御するため、固定パターンノイズをさらに抑制することができる。 As described above, according to the second embodiment of the present technology, the reset control unit 241 controls the reset code to a different value for each row and for each column, so fixed pattern noise can be further suppressed.
　＜３．移動体への応用例＞
　本開示に係る技術（本技術）は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。 <3. Example of application to moving objects>
The technology (the present technology) according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
　図２１は、本開示に係る技術が適用され得る移動体制御システムの一例である車両制御システムの概略的な構成例を示すブロック図である。 FIG. 21 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
　車両制御システム１２０００は、通信ネットワーク１２００１を介して接続された複数の電子制御ユニットを備える。図２１に示した例では、車両制御システム１２０００は、駆動系制御ユニット１２０１０、ボディ系制御ユニット１２０２０、車外情報検出ユニット１２０３０、車内情報検出ユニット１２０４０、及び統合制御ユニット１２０５０を備える。また、統合制御ユニット１２０５０の機能構成として、マイクロコンピュータ１２０５１、音声画像出力部１２０５２、及び車載ネットワークＩ／Ｆ(interface)１２０５３が図示されている。 A vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 21, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. Also, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (interface) 12053 are illustrated.
　駆動系制御ユニット１２０１０は、各種プログラムにしたがって車両の駆動系に関連する装置の動作を制御する。例えば、駆動系制御ユニット１２０１０は、内燃機関又は駆動用モータ等の車両の駆動力を発生させるための駆動力発生装置、駆動力を車輪に伝達するための駆動力伝達機構、車両の舵角を調節するステアリング機構、及び、車両の制動力を発生させる制動装置等の制御装置として機能する。 The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
　ボディ系制御ユニット１２０２０は、各種プログラムにしたがって車体に装備された各種装置の動作を制御する。例えば、ボディ系制御ユニット１２０２０は、キーレスエントリシステム、スマートキーシステム、パワーウィンドウ装置、あるいは、ヘッドランプ、バックランプ、ブレーキランプ、ウィンカー又はフォグランプ等の各種ランプの制御装置として機能する。この場合、ボディ系制御ユニット１２０２０には、鍵を代替する携帯機から発信される電波又は各種スイッチの信号が入力され得る。ボディ系制御ユニット１２０２０は、これらの電波又は信号の入力を受け付け、車両のドアロック装置、パワーウィンドウ装置、ランプ等を制御する。 The body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps. In this case, the body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
　車外情報検出ユニット１２０３０は、車両制御システム１２０００を搭載した車両の外部の情報を検出する。例えば、車外情報検出ユニット１２０３０には、撮像部１２０３１が接続される。車外情報検出ユニット１２０３０は、撮像部１２０３１に車外の画像を撮像させるとともに、撮像された画像を受信する。車外情報検出ユニット１２０３０は、受信した画像に基づいて、人、車、障害物、標識又は路面上の文字等の物体検出処理又は距離検出処理を行ってもよい。 The vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed. For example, the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 . The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
　撮像部１２０３１は、光を受光し、その光の受光量に応じた電気信号を出力する光センサである。撮像部１２０３１は、電気信号を画像として出力することもできるし、測距の情報として出力することもできる。また、撮像部１２０３１が受光する光は、可視光であっても良いし、赤外線等の非可視光であっても良い。 The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information. Also, the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
　車内情報検出ユニット１２０４０は、車内の情報を検出する。車内情報検出ユニット１２０４０には、例えば、運転者の状態を検出する運転者状態検出部１２０４１が接続される。運転者状態検出部１２０４１は、例えば運転者を撮像するカメラを含み、車内情報検出ユニット１２０４０は、運転者状態検出部１２０４１から入力される検出情報に基づいて、運転者の疲労度合い又は集中度合いを算出してもよいし、運転者が居眠りをしていないかを判別してもよい。 The in-vehicle information detection unit 12040 detects in-vehicle information. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
　マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０又は車内情報検出ユニット１２０４０で取得される車内外の情報に基づいて、駆動力発生装置、ステアリング機構又は制動装置の制御目標値を演算し、駆動系制御ユニット１２０１０に対して制御指令を出力することができる。例えば、マイクロコンピュータ１２０５１は、車両の衝突回避あるいは衝撃緩和、車間距離に基づく追従走行、車速維持走行、車両の衝突警告、又は車両のレーン逸脱警告等を含むＡＤＡＳ(Advanced Driver Assistance System)の機能実現を目的とした協調制御を行うことができる。 The microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit. A control command can be output to 12010 . For example, the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of
　また、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０又は車内情報検出ユニット１２０４０で取得される車両の周囲の情報に基づいて駆動力発生装置、ステアリング機構又は制動装置等を制御することにより、運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 In addition, the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
　また、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０で取得される車外の情報に基づいて、ボディ系制御ユニット１２０２０に対して制御指令を出力することができる。例えば、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０で検知した先行車又は対向車の位置に応じてヘッドランプを制御し、ハイビームをロービームに切り替える等の防眩を図ることを目的とした協調制御を行うことができる。 Also, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
　音声画像出力部１２０５２は、車両の搭乗者又は車外に対して、視覚的又は聴覚的に情報を通知することが可能な出力装置へ音声及び画像のうちの少なくとも一方の出力信号を送信する。図２１の例では、出力装置として、オーディオスピーカ１２０６１、表示部１２０６２及びインストルメントパネル１２０６３が例示されている。表示部１２０６２は、例えば、オンボードディスプレイ及びヘッドアップディスプレイの少なくとも一つを含んでいてもよい。 The audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle. In the example of FIG. 21, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.
　図２２は、撮像部１２０３１の設置位置の例を示す図である。 FIG. 22 is a diagram showing an example of the installation position of the imaging unit 12031. FIG.
　図２２では、撮像部１２０３１として、撮像部１２１０１，１２１０２，１２１０３，１２１０４，１２１０５を有する。 In FIG. 22, the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105.
　撮像部１２１０１，１２１０２，１２１０３，１２１０４，１２１０５は、例えば、車両１２１００のフロントノーズ、サイドミラー、リアバンパ、バックドア及び車室内のフロントガラスの上部等の位置に設けられる。フロントノーズに備えられる撮像部１２１０１及び車室内のフロントガラスの上部に備えられる撮像部１２１０５は、主として車両１２１００の前方の画像を取得する。サイドミラーに備えられる撮像部１２１０２，１２１０３は、主として車両１２１００の側方の画像を取得する。リアバンパ又はバックドアに備えられる撮像部１２１０４は、主として車両１２１００の後方の画像を取得する。車室内のフロントガラスの上部に備えられる撮像部１２１０５は、主として先行車両又は、歩行者、障害物、信号機、交通標識又は車線等の検出に用いられる。 The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose of the vehicle 12100, the side mirrors, the rear bumper, the back door, and the upper part of the windshield in the vehicle interior, for example. An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 . Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 . An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 . The imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
　なお、図２２には、撮像部１２１０１ないし１２１０４の撮影範囲の一例が示されている。撮像範囲１２１１１は、フロントノーズに設けられた撮像部１２１０１の撮像範囲を示し、撮像範囲１２１１２，１２１１３は、それぞれサイドミラーに設けられた撮像部１２１０２，１２１０３の撮像範囲を示し、撮像範囲１２１１４は、リアバンパ又はバックドアに設けられた撮像部１２１０４の撮像範囲を示す。例えば、撮像部１２１０１ないし１２１０４で撮像された画像データが重ね合わせられることにより、車両１２１００を上方から見た俯瞰画像が得られる。 Note that FIG. 22 shows an example of the imaging range of the imaging units 12101 to 12104. FIG. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively, and the imaging range 12114 The imaging range of an imaging unit 12104 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
　撮像部１２１０１ないし１２１０４の少なくとも１つは、距離情報を取得する機能を有していてもよい。例えば、撮像部１２１０１ないし１２１０４の少なくとも１つは、複数の撮像素子からなるステレオカメラであってもよいし、位相差検出用の画素を有する撮像素子であってもよい。 At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
　例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４から得られた距離情報を基に、撮像範囲１２１１１ないし１２１１４内における各立体物までの距離と、この距離の時間的変化（車両１２１００に対する相対速度）を求めることにより、特に車両１２１００の進行路上にある最も近い立体物で、車両１２１００と略同じ方向に所定の速度（例えば、０ｋｍ／ｈ以上）で走行する立体物を先行車として抽出することができる。さらに、マイクロコンピュータ１２０５１は、先行車の手前に予め確保すべき車間距離を設定し、自動ブレーキ制御（追従停止制御も含む）や自動加速制御（追従発進制御も含む）等を行うことができる。このように運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the course of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
　例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４から得られた距離情報を元に、立体物に関する立体物データを、２輪車、普通車両、大型車両、歩行者、電柱等その他の立体物に分類して抽出し、障害物の自動回避に用いることができる。例えば、マイクロコンピュータ１２０５１は、車両１２１００の周辺の障害物を、車両１２１００のドライバが視認可能な障害物と視認困難な障害物とに識別する。そして、マイクロコンピュータ１２０５１は、各障害物との衝突の危険度を示す衝突リスクを判断し、衝突リスクが設定値以上で衝突可能性がある状況であるときには、オーディオスピーカ１２０６１や表示部１２０６２を介してドライバに警報を出力することや、駆動系制御ユニット１２０１０を介して強制減速や回避操舵を行うことで、衝突回避のための運転支援を行うことができる。 For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
　撮像部１２１０１ないし１２１０４の少なくとも１つは、赤外線を検出する赤外線カメラであってもよい。例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４の撮像画像中に歩行者が存在するか否かを判定することで歩行者を認識することができる。かかる歩行者の認識は、例えば赤外線カメラとしての撮像部１２１０１ないし１２１０４の撮像画像における特徴点を抽出する手順と、物体の輪郭を示す一連の特徴点にパターンマッチング処理を行って歩行者か否かを判別する手順によって行われる。マイクロコンピュータ１２０５１が、撮像部１２１０１ないし１２１０４の撮像画像中に歩行者が存在すると判定し、歩行者を認識すると、音声画像出力部１２０５２は、当該認識された歩行者に強調のための方形輪郭線を重畳表示するように、表示部１２０６２を制御する。また、音声画像出力部１２０５２は、歩行者を示すアイコン等を所望の位置に表示するように表示部１２０６２を制御してもよい。 At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 . Such recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. This is done by a procedure that determines When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
　以上、本開示に係る技術が適用され得る車両制御システムの一例について説明した。本開示に係る技術は、以上説明した構成のうち、撮像部１２０３１に適用され得る。具体的には、図１の撮像装置１００は、撮像部１２０３１に適用することができる撮像部１２０３１に本開示に係る技術を適用することにより、固定パターンノイズを抑制して、より見やすい撮影画像を得ることができるため、ドライバの疲労を軽減することが可能になる。 An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. Specifically, the imaging apparatus 100 in FIG. 1 applies the technology according to the present disclosure to the imaging unit 12031 that can be applied to the imaging unit 12031, thereby suppressing fixed pattern noise and producing a more viewable captured image. can be obtained, it becomes possible to reduce the fatigue of the driver.
　なお、上述の実施の形態は本技術を具現化するための一例を示したものであり、実施の形態における事項と、特許請求の範囲における発明特定事項とはそれぞれ対応関係を有する。同様に、特許請求の範囲における発明特定事項と、これと同一名称を付した本技術の実施の形態における事項とはそれぞれ対応関係を有する。ただし、本技術は実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において実施の形態に種々の変形を施すことにより具現化することができる。 It should be noted that the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the scope of claims have corresponding relationships. Similarly, the matters specifying the invention in the scope of claims and the matters in the embodiments of the present technology with the same names have corresponding relationships. However, the present technology is not limited to the embodiments, and can be embodied by various modifications to the embodiments without departing from the scope of the present technology.
　なお、本明細書に記載された効果はあくまで例示であって、限定されるものではなく、また、他の効果があってもよい。 It should be noted that the effects described in this specification are only examples and are not limited, and other effects may also occur.
　なお、本技術は以下のような構成もとることができる。
（１）入力されたアナログ信号と所定の参照信号とから比較結果を生成するコンパレータと、
　前記参照信号を供給するデジタルアナログ変換器と、
　所定のリセットコードにより前記参照信号を初期化させた後に前記比較結果に基づいて前記参照信号を更新させる逐次比較ロジック回路と、
　前記リセットコードの値を制御するリセット制御部と
を具備するアナログデジタル変換回路。
（２）それぞれが前記アナログ信号を生成する複数の画素が二次元格子状に配列された画素アレイ部と、
　前記画素アレイ部内の行を順に駆動して前記アナログ信号を出力させる垂直走査回路と
をさらに具備し、
　前記リセット制御部は、前記垂直走査回路が行を駆動するたびに前記リセットコードを前回値と異なる値に更新する
前記（１）記載のアナログデジタル変換回路。
（３）前記リセット制御部は、前記アナログ信号が入力されるたびに前記リセットコードを前回値と異なる値に制御する
前記（２）記載のアナログデジタル変換回路。
（４）複数のＳＡＲＡＤＣ（Successive Approximation Register Analog to Digital Converter）が配列され、
　前記複数のＳＡＲＡＤＣのそれぞれに前記コンパレータ、前記デジタルアナログ変換器および前記逐次比較ロジック回路が配置され、
　前記リセット制御部は、前記複数のＳＡＲＡＤＣのそれぞれのリセットコードを異なる値に制御する
前記（２）または（３）に記載のアナログデジタル変換回路。
（５）複数のアナログ信号を容量素子に保持して前記保持した複数のアナログ信号のいずれかを順に選択して前記コンパレータに入力する容量マルチプレクサをさらに具備する
前記（１）から（４）のいずれかに記載のアナログデジタル変換回路。
（６）所定のリセットレベルと露光量に応じた信号レベルとの差分を求めて前記アナログ信号として供給するカラムアンプをさらに具備する
前記（１）から（５）のいずれかに記載のアナログデジタル変換回路。
（７）前記リセットコードに基づいて補正量を求める前段処理部と、
　前記補正量に基づいて前記逐次比較ロジック回路からのデジタル信号に対するリセットコード処理を行うリセットコード処理部をさらに具備し、
　前記リセット制御部は、所定の初期値のコードに対して所定の演算を行った演算結果を前記リセットコードとして供給し、
　前記前段処理部は、前記リセットコードに応じた前記補正量を前記リセットコード処理部に供給し、
　前記逐次比較ロジック回路は、所定数の前記比較結果に基づいて前記デジタル信号を生成する
前記（１）から（６）のいずれかに記載のアナログデジタル変換回路。
（８）前記演算は、ディザ信号の加算を含む
前記（７）記載のアナログデジタル変換回路。
（９）前記演算は、前回値に所定値を加算または減算する処理を含む
前記（７）記載のアナログデジタル変換回路。
（１０）アナログ信号を生成する画素と、
　前記アナログ信号と所定の参照信号とから比較結果を生成するコンパレータと、
　前記参照信号を供給するデジタルアナログ変換器と、
　所定のリセットコードにより前記参照信号を初期化させた後に前記比較結果に基づいて前記参照信号を更新させる逐次比較ロジック回路と、
　前記リセットコードの値を制御するリセット制御部と
を具備する固体撮像素子。
（１１）入力されたアナログ信号と所定の参照信号とから比較結果を生成する比較手順と、
　前記参照信号を供給するデジタルアナログ変換手順と、
　所定のリセットコードにより前記参照信号を初期化させた後に前記比較結果に基づいて前記参照信号を更新させる逐次比較手順と、
　前記リセットコードの値を制御するリセット制御手順と
を具備するアナログデジタル変換回路の制御方法。 Note that the present technology can also have the following configuration.
(1) a comparator that generates a comparison result from an input analog signal and a predetermined reference signal;
a digital-to-analog converter that provides the reference signal;
a successive approximation logic circuit that initializes the reference signal with a predetermined reset code and then updates the reference signal based on the comparison result;
and a reset control unit that controls the value of the reset code.
(2) a pixel array section in which a plurality of pixels each generating the analog signal are arranged in a two-dimensional grid;
a vertical scanning circuit for sequentially driving rows in the pixel array unit to output the analog signal;
The analog-to-digital conversion circuit according to (1), wherein the reset control unit updates the reset code to a value different from the previous value each time the vertical scanning circuit drives a row.
(3) The analog-to-digital conversion circuit according to (2), wherein the reset control section controls the reset code to a value different from the previous value each time the analog signal is input.
(4) a plurality of SAR ADCs (Successive Approximation Register Analog to Digital Converters) are arranged,
The comparator, the digital-to-analog converter, and the successive approximation logic circuit are arranged in each of the plurality of SAR ADCs;
The analog-to-digital conversion circuit according to (2) or (3), wherein the reset control unit controls reset codes of the plurality of SAR ADCs to different values.
(5) Any one of (1) to (4) above, further comprising a capacitive multiplexer that holds a plurality of analog signals in a capacitive element, sequentially selects one of the held plurality of analog signals, and inputs it to the comparator. The analog-to-digital conversion circuit according to claim 1.
(6) The analog-to-digital conversion according to any one of (1) to (5), further comprising a column amplifier that obtains a difference between a predetermined reset level and a signal level corresponding to the amount of exposure and supplies the difference as the analog signal. circuit.
(7) a pre-processing unit that obtains a correction amount based on the reset code;
further comprising a reset code processing unit that performs reset code processing on the digital signal from the successive approximation logic circuit based on the correction amount;
The reset control unit supplies, as the reset code, a calculation result obtained by performing a predetermined calculation on a code of a predetermined initial value,
The pre-processing unit supplies the correction amount according to the reset code to the reset code processing unit,
The analog-to-digital conversion circuit according to any one of (1) to (6), wherein the successive approximation logic circuit generates the digital signal based on a predetermined number of comparison results.
(8) The analog-to-digital conversion circuit according to (7), wherein the calculation includes addition of dither signals.
(9) The analog-to-digital conversion circuit according to (7), wherein the calculation includes a process of adding or subtracting a predetermined value to or from the previous value.
(10) a pixel that produces an analog signal;
a comparator that generates a comparison result from the analog signal and a predetermined reference signal;
a digital-to-analog converter that provides the reference signal;
a successive approximation logic circuit that initializes the reference signal with a predetermined reset code and then updates the reference signal based on the comparison result;
and a reset control unit that controls the value of the reset code.
(11) a comparison procedure for generating a comparison result from the input analog signal and a predetermined reference signal;
a digital-to-analog conversion procedure providing said reference signal;
a successive approximation procedure for initializing the reference signal with a predetermined reset code and then updating the reference signal based on the comparison result;
and a reset control procedure for controlling the value of the reset code.
　１００　撮像装置
　１１０　光学部
　１２０　ＤＳＰ回路
　１３０　表示部
　１４０　操作部
　１５０　バス
　１６０　フレームメモリ
　１７０　記憶部
　１８０　電源部
　２００　固体撮像素子
　２０１　受光チップ
　２０２　回路チップ
　２１１　垂直走査回路
　２１２　タイミング制御回路
　２２０　画素アレイ部
　２３０　画素
　２３１　光電変換素子
　２３２　転送トランジスタ
　２３３　リセットトランジスタ
　２３４　浮遊拡散層
　２３５　増幅トランジスタ
　２３６　選択トランジスタ
　２４０　デジタル信号処理部
　２４１　リセット制御部
　２４２　前段処理部
　２４３　リセットコード処理部
　２４４　後段処理部
　３００　アナログデジタル変換部
　３１０　カラムアンプ
　３１１　アンプ
　３１２、３１３、３１６、４１１～４１８、４３１～４３８、４５１～４５８　スイッチ
　３１４、３１５、４１９、４２０、４３９、４４０、４５９、４６０　容量素子
　３２０　ＳＡＲＡＤＣ
　３２１、３２２　オートゼロスイッチ
　３２３　プリアンプ
　３２４　コンパレータ
　３２５、３２６　ＣＤＡＣ
　３２７　ＳＡＲロジック回路
　４００　容量マルチプレクサ
　４１０、４３０、４５０　サンプルホールドブロック
　１２０３１　撮像部 100 imaging device 110 optical unit 120 DSP circuit 130 display unit 140 operation unit 150 bus 160 frame memory 170 storage unit 180 power supply unit 200 solid-state imaging device 201 light receiving chip 202 circuit chip 211 vertical scanning circuit 212 timing control circuit 220 pixel array unit 230 pixels 231 photoelectric conversion element 232 transfer transistor 233 reset transistor 234 floating diffusion layer 235 amplification transistor 236 selection transistor 240 digital signal processing section 241 reset control section 242 pre-processing section 243 reset code processing section 244 post-processing section 300 analog-to-digital conversion section 310 column amplifier 311 amplifier 312, 313, 316, 411 to 418, 431 to 438, 451 to 458 switch 314, 315, 419, 420, 439, 440, 459, 460 capacitive element 320 SARADC
321, 322 auto-zero switch 323 preamplifier 324 comparator 325, 326 CDAC
327 SAR logic circuit 400 capacitance multiplexer 410, 430, 450 sample hold block 12031 imaging unit

Claims (11)

  1. 　入力されたアナログ信号と所定の参照信号とから比較結果を生成するコンパレータと、
    　前記参照信号を供給するデジタルアナログ変換器と、
    　所定のリセットコードにより前記参照信号を初期化させた後に前記比較結果に基づいて前記参照信号を更新させる逐次比較ロジック回路と、
    　前記リセットコードの値を制御するリセット制御部と
    を具備するアナログデジタル変換回路。     a comparator that generates a comparison result from an input analog signal and a predetermined reference signal;
    a digital-to-analog converter that provides the reference signal;
    a successive approximation logic circuit that initializes the reference signal with a predetermined reset code and then updates the reference signal based on the comparison result;
    and a reset control unit that controls the value of the reset code.
  2. 　それぞれが前記アナログ信号を生成する複数の画素が二次元格子状に配列された画素アレイ部と、
    　前記画素アレイ部内の行を順に駆動して前記アナログ信号を出力させる垂直走査回路と
    をさらに具備し、
    　前記リセット制御部は、前記垂直走査回路が行を駆動するたびに前記リセットコードを前回値と異なる値に更新する
    請求項１記載のアナログデジタル変換回路。     a pixel array section in which a plurality of pixels each generating the analog signal are arranged in a two-dimensional grid;
    a vertical scanning circuit for sequentially driving rows in the pixel array unit to output the analog signal;
    2. The analog-to-digital conversion circuit according to claim 1, wherein said reset control unit updates said reset code to a value different from the previous value each time said vertical scanning circuit drives a row.
  3. 　前記リセット制御部は、前記アナログ信号が入力されるたびに前記リセットコードを前回値と異なる値に制御する
    請求項２記載のアナログデジタル変換回路。     3. The analog-to-digital conversion circuit according to claim 2, wherein said reset control section controls said reset code to a value different from a previous value each time said analog signal is input.
  4. 　複数のＳＡＲＡＤＣ（Successive Approximation Register Analog to Digital Converter）が配列され、
    　前記複数のＳＡＲＡＤＣのそれぞれに前記コンパレータ、前記デジタルアナログ変換器および前記逐次比較ロジック回路が配置され、
    　前記リセット制御部は、前記複数のＳＡＲＡＤＣのそれぞれのリセットコードを異なる値に制御する
    請求項２記載のアナログデジタル変換回路。     A plurality of SAR ADCs (Successive Approximation Register Analog to Digital Converter) are arranged,
    The comparator, the digital-to-analog converter, and the successive approximation logic circuit are arranged in each of the plurality of SAR ADCs;
    3. The analog-to-digital conversion circuit according to claim 2, wherein said reset control section controls reset codes of said plurality of SAR ADCs to different values.
  5. 　複数のアナログ信号を容量素子に保持して前記保持した複数のアナログ信号のいずれかを順に選択して前記コンパレータに入力する容量マルチプレクサをさらに具備する
    請求項１記載のアナログデジタル変換回路。     2. The analog-to-digital conversion circuit according to claim 1, further comprising a capacitive multiplexer that holds a plurality of analog signals in capacitive elements, sequentially selects one of the plurality of held analog signals, and inputs it to the comparator.
  6. 　所定のリセットレベルと露光量に応じた信号レベルとの差分を求めて前記アナログ信号として供給するカラムアンプをさらに具備する
    請求項１記載のアナログデジタル変換回路。     2. The analog-to-digital conversion circuit according to claim 1, further comprising a column amplifier that obtains a difference between a predetermined reset level and a signal level corresponding to the amount of exposure and supplies it as the analog signal.
  7. 　前記リセットコードに基づいて補正量を求める前段処理部と、
    　前記補正量に基づいて前記逐次比較ロジック回路からのデジタル信号に対するリセットコード処理を行うリセットコード処理部をさらに具備し、
    　前記リセット制御部は、所定の初期値のコードに対して所定の演算を行った演算結果を前記リセットコードとして供給し、
    　前記前段処理部は、前記リセットコードに応じた前記補正量を前記リセットコード処理部に供給し、
    　前記逐次比較ロジック回路は、所定数の前記比較結果に基づいて前記デジタル信号を生成する
    請求項１記載のアナログデジタル変換回路。     a pre-processing unit that obtains a correction amount based on the reset code;
    further comprising a reset code processing unit that performs reset code processing on the digital signal from the successive approximation logic circuit based on the correction amount;
    The reset control unit supplies, as the reset code, a calculation result obtained by performing a predetermined calculation on a code of a predetermined initial value,
    The pre-processing unit supplies the correction amount corresponding to the reset code to the reset code processing unit,
    2. The analog-to-digital conversion circuit according to claim 1, wherein said successive approximation logic circuit generates said digital signal based on a predetermined number of said comparison results.
  8. 　前記演算は、ディザ信号の加算を含む
    請求項７記載のアナログデジタル変換回路。     8. The analog-to-digital conversion circuit according to claim 7, wherein said calculation includes addition of dither signals.
  9. 　前記演算は、前回値に所定値を加算または減算する処理を含む
    請求項７記載のアナログデジタル変換回路。     8. The analog-to-digital conversion circuit according to claim 7, wherein said calculation includes a process of adding or subtracting a predetermined value to or from the previous value.
  10. 　アナログ信号を生成する画素と、
    　前記アナログ信号と所定の参照信号とから比較結果を生成するコンパレータと、
    　前記参照信号を供給するデジタルアナログ変換器と、
    　所定のリセットコードにより前記参照信号を初期化させた後に前記比較結果に基づいて前記参照信号を更新させる逐次比較ロジック回路と、
    　前記リセットコードの値を制御するリセット制御部と
    を具備する固体撮像素子。     a pixel that generates an analog signal;
    a comparator that generates a comparison result from the analog signal and a predetermined reference signal;
    a digital-to-analog converter that provides the reference signal;
    a successive approximation logic circuit that initializes the reference signal with a predetermined reset code and then updates the reference signal based on the comparison result;
    and a reset control unit that controls the value of the reset code.
  11. 　入力されたアナログ信号と所定の参照信号とから比較結果を生成する比較手順と、
    　前記参照信号を供給するデジタルアナログ変換手順と、
    　所定のリセットコードにより前記参照信号を初期化させた後に前記比較結果に基づいて前記参照信号を更新させる逐次比較手順と、
    　前記リセットコードの値を制御するリセット制御手順と
    を具備するアナログデジタル変換回路の制御方法。     a comparison procedure for generating a comparison result from an input analog signal and a predetermined reference signal;
    a digital-to-analog conversion procedure providing said reference signal;
    a successive approximation procedure for initializing the reference signal with a predetermined reset code and then updating the reference signal based on the comparison result;
    and a reset control procedure for controlling the value of the reset code.
PCT/JP2021/048865 2021-05-20 2021-12-28 Analog/digital conversion circuit, solid-state image sensing device, and method for controlling analog/digital conversion circuit WO2022244293A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014022990A (en) * 2012-07-19 2014-02-03 Denso Corp Ad conversion circuit
WO2020045373A1 (en) * 2018-08-30 2020-03-05 ソニーセミコンダクタソリューションズ株式会社 Solid state imaging device
JP2021048571A (en) * 2019-09-20 2021-03-25 日本放送協会 Lamination type solid-state image pickup element and lamination type solid-state image pickup device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014022990A (en) * 2012-07-19 2014-02-03 Denso Corp Ad conversion circuit
WO2020045373A1 (en) * 2018-08-30 2020-03-05 ソニーセミコンダクタソリューションズ株式会社 Solid state imaging device
JP2021048571A (en) * 2019-09-20 2021-03-25 日本放送協会 Lamination type solid-state image pickup element and lamination type solid-state image pickup device

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