WO2021145033A1 - Solid-state imaging element, imaging device, and control method for solid-state imaging element - Google Patents
Solid-state imaging element, imaging device, and control method for solid-state imaging element Download PDFInfo
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Definitions
- This technology relates to a solid-state image sensor. More specifically, the present invention relates to a solid-state image sensor that converts an analog signal into a digital signal for each column, an image pickup device, and a control method for the solid-state image sensor.
- This technology was created in view of this situation, and aims to reduce the memory capacity of a solid-state image sensor that holds a correction coefficient for each column.
- the present technology has been made to solve the above-mentioned problems, and the first aspect thereof is to increase or decrease the analog signal by the analog gain selected from the plurality of analog gains to increase or decrease the analog signal.
- An analog-to-digital converter that converts to a digital signal, multiple memories of different sizes, and a gain correction coefficient that calculates the correction coefficient for correcting the error of the selected analog gain as a gain correction coefficient based on the digital signal. It is provided with a calculation unit and a reduction processing unit that reduces the number of digits of the gain correction coefficient to a value corresponding to the analog gain and holds it in a memory having a size corresponding to the number of digits after reduction among the plurality of memories.
- a solid-state imaging device and a control method thereof This has the effect of reducing the amount of memory required.
- the plurality of memories are arranged in a predetermined direction, the sizes of the plurality of memories in the predetermined direction are different from each other, and the sizes of the plurality of memories are perpendicular to each of the predetermined directions.
- the size of the directions may be substantially the same. This has the effect of reducing the size of the memory in the direction perpendicular to the predetermined direction.
- the plurality of memories are grouped into two groups, and a predetermined number of memories belonging to each of the two groups are different in size in a predetermined direction from each other and are arranged in the predetermined direction.
- the size of one of the two groups in the direction perpendicular to the predetermined direction may be different from that of the other. This has the effect of reducing the size of the memory in the predetermined direction.
- the sizes of the plurality of memories in the predetermined directions are substantially the same, and the sizes of the plurality of memories in the directions perpendicular to the predetermined directions are different from each other, and each of them is a pair. Even if a plurality of sets of memories are arranged in the predetermined direction, the pair of memories are arranged in the vertical direction, and the total size of each of the plurality of sets in the vertical direction is substantially the same. good. This has the effect of reducing the size of the memory in the predetermined direction.
- the reduction processing unit may reduce the number of digits as the analog gain becomes smaller. This has the effect of reducing the memory capacity according to the analog gain.
- the digital signal is provided by an input switching unit that inputs one of a predetermined level test signal and a pixel signal as the analog signal to the analog digital converter and the retained gain correction coefficient.
- the gain correction coefficient calculation unit may further include a correction unit for correcting the above, and the gain correction coefficient calculation unit may calculate the gain correction coefficient from the test signal and the digital signal. This has the effect of holding the gain correction coefficient calculated from the test signal and the digital signal in the memory.
- the correction unit may extend the number of digits of the retained gain correction coefficient to a predetermined value to perform correction. This has the effect that the correction is performed by the gain correction coefficient with the expanded number of digits.
- the analog-to-digital converter has a comparator that compares the analog signal with a predetermined lamp signal and outputs a comparison result, and a digital that generates the digital signal based on the comparison result.
- the comparator includes a signal generation unit, and the comparator amplifies the difference between the predetermined reference voltage and the voltage of the predetermined node and outputs the difference as the comparison result, and between the predetermined node and the input switching unit.
- a switch for changing the capacitance ratio according to a predetermined control signal is provided, and the plurality of analog gains are grouped into a plurality of gain domains having different capacitance ratios, and each of the plurality of memories has different analog gains.
- the above gain correction coefficient corresponding to may be retained. This has the effect of maintaining the gain correction coefficient for each gain domain.
- the second aspect of the present technology is an analog digital converter that increases or decreases the analog signal according to the analog gain selected from the plurality of analog gains and converts the increased or decreased analog signal into a digital signal, and a plurality of analog signals having different sizes.
- Memory a gain correction coefficient calculation unit that calculates a correction coefficient for correcting the error of the selected analog gain as a gain correction coefficient based on the digital signal, and an analog gain that calculates the number of digits of the gain correction coefficient.
- An image in which a reduction processing unit that reduces the value according to the above and holds it in a memory of a size corresponding to the number of digits after reduction among the plurality of memories and a digital signal corrected by the held gain correction coefficient are arranged. It is an image pickup apparatus including an image signal processing unit that processes a signal. This brings about the effect that the digital signal is corrected by the gain correction coefficient held in the memory with the reduced capacity.
- VSL Very Signal Line
- FIG. 1 is a block diagram showing a configuration example of the image pickup apparatus 100 according to the first embodiment of the present technology.
- the image pickup device 100 is a device for taking an image of image data (frame), and includes an optical unit 110, a solid-state image sensor 200, and a DSP (Digital Signal Processing) circuit 120. Further, the image pickup apparatus 100 includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180.
- a digital camera such as a digital still camera, a smartphone having an image pickup function, a personal computer, an in-vehicle camera, or the like is assumed.
- the optical unit 110 collects the light from the subject and guides it to the solid-state image sensor 200.
- the solid-state image sensor 200 generates a frame by photoelectric conversion in synchronization with a vertical synchronization signal.
- the vertical synchronization signal is a periodic signal having a predetermined frequency indicating the timing of imaging.
- the solid-state image sensor 200 supplies the generated image data to the DSP circuit 120 via the signal line 209.
- the DSP circuit 120 executes predetermined signal processing on the frame from the solid-state image sensor 200.
- the DSP circuit 120 outputs the processed frame to the frame memory 160 or the like via the bus 150.
- the display unit 130 displays a frame.
- a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed.
- the operation unit 140 generates an operation signal according to the operation of the user.
- the bus 150 is a common route for the optical unit 110, the solid-state image sensor 200, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170, and the power supply unit 180 to exchange data with each other.
- the frame memory 160 holds image data.
- the storage unit 170 stores various data such as frames.
- the power supply unit 180 supplies power to the solid-state image sensor 200, the DSP circuit 120, the display unit 130, and the like.
- FIG. 2 is a diagram showing an example of a laminated structure of the solid-state image sensor 200 according to the first embodiment of the present technology.
- the solid-state image sensor 200 includes a circuit chip 202 and a pixel chip 201 laminated on the circuit chip 202. These chips are electrically connected via a connection such as a via. In addition to vias, it can also be connected by Cu-Cu bonding or bumps.
- FIG. 3 is a block diagram showing a configuration example of the solid-state image sensor 200 according to the first embodiment of the present technology.
- the solid-state image sensor 200 includes a vertical scanning circuit 210, a test signal source 220, a DAC 230, a timing control circuit 240, a pixel array unit 250, an input switching unit 270, a column signal processing unit 280, and an image processing unit 300.
- a plurality of pixels 260 are arranged in a two-dimensional grid pattern.
- a set of pixels 260 arranged in a predetermined horizontal direction is referred to as a "row”
- a set of pixels 260 arranged in a direction perpendicular to the horizontal direction is referred to as a "column” or a “column”.
- the timing control circuit 240 controls the operation timing of the vertical scanning circuit 210, the DAC 230, and the column signal processing unit 280 in synchronization with the vertical synchronization signal Vsync. Further, an imaging start signal instructing the start of imaging of a moving image including a plurality of consecutive frames is input to the timing control circuit 240.
- the imaging start signal is generated by, for example, an external host computer (not shown).
- the vertical scanning circuit 210 selects and drives rows in order, and outputs an analog pixel signal to the input switching unit 270.
- Pixel 260 generates a pixel signal by photoelectric conversion under the control of the vertical scanning circuit 210. Each of the pixels 260 outputs a pixel signal to the input switching unit 270 via the vertical signal line 269.
- the test signal source 220 generates a signal of a predetermined level as a test signal according to the control signal Tin from the image processing unit 300, and supplies the signal to the input switching unit 270 via the signal line 229.
- a DAC for correction provided separately from the DAC 230 is used.
- the input switching unit 270 selects either the pixel signal or the test signal of the column for each column according to the control of the image processing unit 300.
- the input switching unit 270 supplies the selected signal as an input signal to the column signal processing unit 280 via the signal line 279.
- the DAC 230 generates a reference signal by DA (Digital to Analog) conversion and supplies it to the column signal processing unit 280 via a signal line 239.
- DA Digital to Analog
- the reference signal for example, a saw blade-shaped lamp signal is used.
- the column signal processing unit 280 converts an analog input signal into a digital signal for each column using a reference signal.
- the column signal processing unit 280 supplies a digital signal to the image processing unit 300 via the signal line 289.
- the image processing unit 300 performs predetermined image processing on a frame in which digital signals are arranged. This image processing includes correction processing for reducing fixed pattern noise.
- the image processing unit 300 supplies the processed frame to the DSP circuit 120.
- setting information from the outside is input to the timing control circuit 240 and the image processing unit 300.
- This setting information is information indicating a setting value such as an analog gain during imaging, and is generated by a host computer or the like.
- the above-mentioned circuit in the solid-state image sensor 200 is distributed and arranged in the pixel chip 201 and the circuit chip 202.
- the pixel array unit 250 is provided on the pixel chip 201, and circuits other than the pixel array unit 250 (such as the column signal processing unit 280) are arranged on the circuit chip 202.
- the circuits arranged in the pixel chip 201 and the circuit chip 202 are not limited to this combination.
- the pixel array unit 250, the input switching unit 270, and the comparator in the column signal processing unit 280 may be arranged on the pixel chip 201, and other circuits may be arranged on the circuit chip 202.
- FIG. 4 is a circuit diagram showing a configuration example of the pixel 260 according to the first embodiment of the present technology.
- the pixel 260 includes a photoelectric conversion element 261, a transfer transistor 262, a reset transistor 263, a floating diffusion layer 264, an amplification transistor 265, and a selection transistor 266.
- the photoelectric conversion element 261 photoelectrically converts the incident light to generate an electric charge.
- the transfer transistor 262 transfers an electric charge from the photoelectric conversion element 261 to the floating diffusion layer 264 according to the transfer signal TX from the vertical scanning circuit 210.
- the reset transistor 263 initializes the charge amount of the floating diffusion layer 264 according to the reset signal RST from the vertical scanning circuit 210.
- the floating diffusion layer 264 accumulates electric charges and generates a voltage according to the amount of electric charges.
- the amplification transistor 265 amplifies the voltage of the floating diffusion layer 264.
- the selection transistor 266 outputs a signal of the amplified voltage as a pixel signal SIG according to the selection signal SEL from the vertical scanning circuit 210. Assuming that the number of columns is N (N is an integer), the pixel signal of the nth (n is an integer of 1 to N) column is transmitted to the input switching unit 270 via the vertical signal line 269-n.
- the circuit of the pixel 260 is not limited to the one illustrated in the figure as long as it can generate a pixel signal by photoelectric conversion.
- FIG. 5 is a circuit diagram showing a configuration example of the input switching unit 270 according to the first embodiment of the present technology.
- the input switching unit 270 includes a plurality of selectors 271.
- the selector 271 is provided for each column. When the number of columns is N, N selectors 271 are arranged.
- the selector 271 selects either the pixel signal SIG of the corresponding column or the test signal Tout from the test signal source 220 according to the input switching signal SWin from the image processing unit 300.
- One of the two input terminals of the selector 271 in the nth column is connected to the pixel array unit 250 via the vertical signal line 269-n, and the other is connected to the test signal source 220 via the signal line 229.
- the output terminal of the selector 271 in the nth column is connected to the column signal processing unit 280 via the signal line 279-n.
- the selector 271 outputs the selected signal as an input signal Ain.
- FIG. 6 is a block diagram showing a configuration example of the column signal processing unit 280 according to the first embodiment of the present technology.
- the column signal processing unit 280 includes a plurality of ADC 281s. ADC 281 is provided for each row. When the number of columns is N, N ADC281s are arranged.
- the ADC 281 converts the analog input signal Ain of the corresponding column into the digital signal Dout.
- the ADC 281 includes a comparator 400 and a counter 282.
- the comparator 400 compares the reference signal RMP with the input signal Ain in the corresponding column.
- the comparator 400 supplies the comparison result CMP to the counter 282.
- the auto zero signal AZ from the timing control circuit 240 and the capacitance ratio control signal Gctrl from the image processing unit 300 are input to the comparator 400.
- the capacitance ratio control signal Gctrl is a signal for controlling the analog gain of the ADC 281 by switching the capacitance ratio.
- the counter 282 counts the count value over a period until the comparison result CMP is inverted according to the control of the timing control circuit 240.
- the counter 282 supplies a signal indicating the count value to the image processing unit 300 as a digital signal Dout.
- the counter 282 is an example of the digital signal generation unit described in the claims.
- the ADC 281 that performs AD conversion by the comparator 400 and the counter 282 is called a single slope type ADC.
- an ADC other than the single slope type such as a sequential comparison type can be arranged as the ADC 281.
- a sequential comparison type ADC is arranged, a SAR (Successive Approximation Register) logic circuit and a register are arranged instead of the counter 282.
- This SAR logic circuit obtains a value of a reference signal that approximates the input signal based on the comparison result CMP, and generates a DAC control signal for updating the reference signal to that value.
- the register holds a digital signal in which the comparison results are arranged and a DAC control signal, and outputs the digital signal to the image processing unit 300 while outputting the DAC control signal to the DAC 230.
- FIG. 7 is a circuit diagram showing a configuration example of the comparator 400 according to the first embodiment of the present technology.
- a capacitance ratio switching circuit 410 and a differential amplifier circuit 430 are arranged in the comparator 400.
- the capacity ratio switching circuit 410 includes a predetermined number of switches such as switches 411 to 415 and a plurality of capacities such as capacities 416 to 421.
- One end of the capacities 416 to 421 is commonly connected to the node 422.
- the other end of the capacitance 416 is connected to the input switching unit 270 via the signal line 279-n, and the other end of the capacitance 421 is connected to the DAC 230 via the signal line 239.
- the switch 411 opens and closes the path between the other end of the capacitance 416 and the other end of the capacitance 417 according to the capacitance ratio control signal Gctrl.
- the switch 412 opens and closes the path between the other end of the capacitance 417 and the other end of the capacitance 418 according to the capacitance ratio control signal Gctrl.
- the switch 413 opens and closes the path between the other end of the capacitance 418 and the other end of the capacitance 419 according to the capacitance ratio control signal Gctrl.
- the switch 414 opens and closes a path between the other end of the capacitance 419 and the other end of the capacitance 420 according to the capacitance ratio control signal Gctrl.
- the switch 415 opens and closes a path between the other end of the capacitance 420 and the other end of the capacitance 421 according to the capacitance ratio control signal Gctrl.
- the image processing unit 300 controls only one of the switches 411 to 415 to be in the open state and the rest to the closed state by the capacitance ratio control signal Gctrl. By this control, the combined capacitance of the capacitance inserted between the signal line 279-n on the vertical signal line side and the node 422 and the combined capacitance inserted between the signal line 239 on the lamp signal side and the node 422 are combined. The capacity ratio with the capacity is changed.
- the combined capacitance on the vertical signal line side is referred to as "VSL side capacitance”
- the combined capacitance on the lamp signal side is referred to as "lamp side capacitance”.
- the image processing unit 300 can switch the capacitance ratio in five stages by controlling five switches.
- the image processing unit 300 can switch the capacity ratio to a plurality of stages other than the 5 stages. Assuming that the number of stages is M (M is an integer), M switches and M + 1 capacitances are arranged in the capacitance ratio switching circuit 410.
- the capacity value of the capacity 416 is the largest, and the capacity values of the capacities 417 to 421 are set to be the same.
- the respective capacity values of the capacities 416 to 421 can be set to arbitrary values.
- the capacity 440 holds a predetermined reference voltage VSH.
- the differential amplifier circuit 430 amplifies the difference between the voltage of the node 422 and the reference voltage VSH.
- the differential amplifier circuit 430 includes pMOS transistors 431 and 432, auto-zero switches 436 and 437, and nMOS transistors 433 to 435.
- the pMOS transistors 431 and 432 are connected in parallel to the power supply.
- the gate of the pMOS transistor 431 is connected to its own drain and the gate of the pMOS transistor 432.
- the drain of the nMOS transistor 433 is connected to the pMOS transistor 431, and the source is connected to the common node. Further, the gate of the nMOS transistor 433 is connected to the node 422. The drain of the nMOS transistor 434 is connected to the pMOS transistor 432 and the source is connected to the common node. Further, the gate of the nMOS transistor 434 is connected to the capacitance 440.
- the nMOS transistor 435 is inserted between the common node and the ground terminal, and a predetermined bias voltage Vbias is input to the gate.
- the auto zero switch 436 short-circuits between the drain and the gate of the nMOS transistor 433 according to the auto zero signal AZ from the timing control circuit 240.
- the auto zero switch 437 short-circuits between the drain and the gate of the nMOS transistor 434 according to the auto zero signal AZ.
- comparison result CMP is output to the counter 282 from the connection point of the pMOS transistor 432 and the nMOS transistor 434.
- a lamp signal whose level increases with the passage of time is input as a reference signal RMP to the comparator 400 having the configuration illustrated in the figure.
- FIG. 8 is a diagram showing an example of VSL side capacity and lamp side capacity for each gain domain in the first embodiment of the present technology.
- the analog gain of the ADC 281 can be controlled by the slope inclination of the reference signal RMP (lamp signal) and the capacitance ratio of the VSL side capacitance and the lamp side capacitance. The gentler the slope, the higher the analog gain. In addition, the analog gain increases or decreases according to the capacitance ratio.
- K K is an integer
- M step an analog gain in K ⁇ M step can be realized.
- the analog gain can be grouped into 5 gain domains d0 to d4. Within each gain domain, the capacitance ratio is set to be the same, and the analog gain is controlled in multiple stages by the slope inclination.
- the host computer measures the amount of ambient light, and the higher the amount of metering, the lower the analog gain.
- the vertical axis of the figure shows the VSL side capacity or the lamp side capacity
- the horizontal axis shows the analog gain.
- the VSL side capacitance is the same as the lamp side capacitance.
- the VSL side capacitance is larger than the lamp side capacitance. The larger the VSL side capacitance, the larger the analog gain.
- FIG. 9 is a block diagram showing a configuration example of the image processing unit 300 according to the first embodiment of the present technology.
- the image processing unit 300 includes a gain error measuring unit 310, a correction value calculation unit 320, a storage unit 330, a selector 340, a correction unit 350, and a controller 360.
- the selector 340 outputs the digital signal Dout from the column signal processing unit 280 to either the gain error measuring unit 310 or the correction unit 350 according to the output switching signal SWout from the controller 360.
- the gain error measuring unit 310 measures a parameter representing an analog gain error from a digital signal from the selector 340.
- an error may occur in each analog gain of the ADC 281, and the error is often different for each column. Fixed pattern noise can occur due to the relative gain error between the columns.
- the analog gain error is caused by, for example, product variation of the analog circuit in the comparator 400 and deterioration over time. Therefore, the gain error measuring unit 310 measures the brightness level error a plurality of times for each column and each gain domain in order to make the analog gain uniform, and obtains the relative gain error between the columns based on them. ..
- the number of AD conversions for obtaining the analog gain is set as the number of samples according to the setting information from the host computer. Then, the gain error measuring unit 310 supplies the obtained error as measurement data to the correction value calculation unit 320.
- the gain error measurement unit 310 generates an update pulse based on the number of samples from the controller 360, and supplies the update pulse together with the measurement data to the correction value calculation unit 320.
- This update pulse is a signal that indicates the update timing of the correction value.
- the correction value calculation unit 320 obtains a correction value for correcting an analog gain error for each column and each gain domain based on the measurement data.
- the correction value includes a value of the gain correction coefficient a for correcting the analog gain error and a value of the offset correction coefficient b for correcting the offset error.
- the correction value calculation unit 320 stores the obtained correction value (gain correction coefficient and offset correction coefficient) in the storage unit 330. Further, the correction value calculation unit 320 is input with the measurement target domain information indicating the gain domain to be measured by the gain error measurement unit 310. The correction value calculation unit 320 updates the correction value of the gain domain indicated by the measurement target domain information in synchronization with the update pulse.
- the storage unit 330 stores the correction value for each column and each gain domain.
- the correction unit 350 corrects the digital signal from the selector 340 according to the correction value.
- the correction target domain information indicating the gain domain to be corrected is input to the correction unit 350 by the controller 360.
- the correction unit 350 starts from the storage unit 330 in the mth column in the nth column.
- the gain correction coefficient a and the offset correction coefficient b of the gain domain of the above are read out.
- the digital signal Dout is corrected by the following equation.
- Dout' Dout ⁇ a + b ⁇ ⁇ ⁇ Equation 1 In the above equation, Dout'indicates the corrected digital signal.
- the correction unit 350 supplies the image data (frame) in which the digital signal Dout'obtained by the equation 1 is arranged to the DSP circuit 120.
- the controller 360 controls the calibration. First, the controller 360 performs start-up processing for calculating the correction value before the start of the video period, which is the period for generating the frame. In this start-up process, the controller 360 controls the input switching unit 270 by the input switching signal SWin to input the test signal. Further, the controller 360 controls the selector 340 by the output switching signal SWout to output a digital signal to the gain error measuring unit 310. Further, the controller 360 controls the comparator 400 by the capacitance ratio control signal Gctrl to sequentially switch to each of the M gain domains. Further, the controller 360 causes the correction value calculation unit 320 to calculate the correction values of the M gain domains in order based on the measurement target domain information.
- the controller 360 inputs a pixel signal by the input switching signal SWin, controls the selector 340 by the output switching signal SWout, and outputs a digital signal to the correction unit 350. Further, the controller 360 is switched to the gain domain corresponding to the analog gain indicated by the setting information by the capacitance ratio control signal Gctrl. Further, the controller 360 corrects the digital signal by the correction value of the gain domain corresponding to the analog gain indicated by the setting information by the correction target domain information.
- the controller 360 executes the division processing performed by dividing the processing performed in the startup processing.
- the controller 360 causes the input switching signal SWin to input a test signal, and the output switching signal SWout to output a digital signal to the gain error measuring unit 310.
- the controller 360 controls the comparator 400 by the capacitance ratio control signal Gctrl to switch to any of the M gain domains.
- the controller 360 causes the correction value calculation unit 320 to calculate the correction value of any of the M gain domains based on the measurement target domain information. The controller 360 does not have to execute this division process when there is little deterioration over time.
- the controller 360 supplies the number of samples indicated by the setting information to the gain error measuring unit 310, controls the test signal source 220 by the control signal Tin, and generates test signals for the number of samples. Let me.
- the setting information includes the analog gain set in the video period, the number of samples in the start-up processing and the division processing, and the drive mode.
- This drive mode indicates, for example, one of a plurality of modes in which the resolution of the frame to be read and the reading range are different.
- FIG. 10 is a block diagram showing a configuration example of the gain error measuring unit 310 according to the first embodiment of the present technology.
- the gain error measurement unit 310 includes a sample number counter 311, an update pulse generation unit 312, a gain calculation unit 313, and an offset calculation unit 314.
- the sample number counter 311 counts the number of digital signals input from the selector 340 as the number of samples.
- the sample number counter 311 supplies the number of samples to the update pulse generation unit 312.
- the update pulse generation unit 312 generates an update pulse based on the number of samples counted by the sample number counter 311.
- the total number of samples and the number of divided samples from the controller 360 are input to the update pulse generation unit 312.
- the update pulse generation unit 312 generates an update pulse when the total number of samples reaches the total number of samples in the start-up process, and supplies the update pulse to the correction value calculation unit 320. Further, in the division process, the update pulse generation unit 312 generates an update pulse every time the number of samples reaches the number of divided samples and supplies the update pulse to the correction value calculation unit 320.
- the number of divided samples means the total number of samples for each gain domain acquired over a predetermined frame in the divided process.
- the gain calculation unit 313 calculates the brightness level error for each column and each gain domain.
- Ain H is a high level input signal
- Ain L is a low level input signal.
- Dout H is a digital signal corresponding to Ain H
- Dout L is a digital signal corresponding to Ain H.
- the gain calculation unit 313 calculates a statistic (average, total, etc.) of the slope g for each gain domain and each column as STg.
- STg cn_dm be the statistic of the mth gain domain in the nth column.
- the statistic STg cn_dm is calculated for all gain domains.
- the statistic STg cn_dm is calculated for each frame for the gain domain to be measured.
- the offset calculation unit 314 calculates the offset for each column and each gain domain.
- the offset calculation unit 314 calculates the offset for each column in the gain domain.
- the offset calculation unit 314 calculates the offset statistic (average, total, etc.) as ST Azure for each gain domain and each column. Let ST réelle cn_dm be the statistic ST réelle of the mth gain domain in the nth column.
- the gain calculation unit 313 and the offset calculation unit 314 supply the data including the calculation result to the correction value calculation unit 320 as measurement data.
- the gain error measuring unit 310 performs an offset calculation in addition to the gain calculation, but if the error is small, the gain calculation may be performed without performing this calculation.
- FIG. 11 is a block diagram showing a configuration example of the correction value calculation unit 320 according to the first embodiment of the present technology.
- the correction value calculation unit 320 includes a gain correction coefficient calculation unit 321 and a reduction processing unit 322.
- the reduction processing unit 322 includes a subtractor 323 and a demultiplexer 324, a plurality of clip processing units 325, and a plurality of decimal digit reduction units 326.
- the clip processing unit 325 is provided for each gain domain.
- the decimal digit reduction unit 326 is provided for each gain domain for the gain domains d0 to dM-2.
- the gain correction coefficient calculation unit 321 calculates the gain correction coefficient a for each column and each gain domain.
- the gain correction coefficient calculation unit 321 calculates the average value of the statistics STg cn_dm of all the columns as the target value AVGg d0 in the gain domain d0. do. Then, the gain correction coefficient calculation unit 321 calculates AVGg d0 / STg cn_dm as the gain correction coefficient a for each column.
- the gain correction coefficient calculation unit 321 performs a calculation for each gain domain of the measurement target.
- the gain correction coefficient calculation unit 321 sets the average value of the statistic STg cn_dm of all the columns of the gain domain dm as the target value AVGg d0 of the gain domain d0 so that the linearity of the analog gain can be obtained in the gain domain d1 and later. Correct based on the standard. Then, the gain correction coefficient calculation unit 321 calculates the corrected average value as the target value AVGg dm of the gain domain dm, and AVGg dm / STg cn_dm as the gain correction coefficient a for each column. Let a cn_dm be the gain correction coefficient of the m-th gain domain in the nth column.
- the gain correction coefficient calculation unit 321 outputs the calculated gain correction coefficient a cn_dm to the subtractor 323 in synchronization with the update pulse.
- the subtractor 323 reduces the integer part of the gain correction coefficient by subtracting a predetermined value from the gain correction coefficient a cn_dm. For example, when the gain correction coefficient is a value around "1", "1" is subtracted. The subtractor 323 supplies a decimal part of the gain correction coefficient obtained by the subtraction to the demultiplexer 324.
- the demultiplexer 324 supplies a decimal part from the subtractor 323 to the clip processing unit 325 corresponding to the gain domain indicated by the measurement target domain information.
- the clip processing unit 325 performs clip processing that limits the value of the decimal part within a predetermined range.
- the clip processing unit 325 related to the gain domains d0 to dM-2 supplies the decimal part after the clip processing to the corresponding decimal digit reduction unit 326.
- the clip processing unit 325 related to the gain domain dM-1 outputs the decimal part after the clip processing to the storage unit 330 as it is.
- the decimal digit reduction unit 326 reduces the number of decimal places after the clip process to a value corresponding to the analog gain.
- the decimal digit reduction unit 326 causes the storage unit 330 to hold the decimal part after the decimal digit reduction as fcn_dm.
- the reduction processing unit 322 reduces the integer part of the gain correction coefficient and reduces the decimal digits except for the gain domain dM-1, but the reduction method is not limited to this.
- the reduction processing unit 322 can also reduce a part of the integer digits of the gain correction coefficient in all gain domains.
- the reduction processing unit 322 can reduce the integer part and a part of the decimal digits of the gain correction coefficient in all the gain domains.
- correction value calculation unit 320 further calculates the offset correction coefficient as necessary, and causes the storage unit 330 to hold the offset correction coefficient.
- the circuit for calculating the offset correction coefficient is omitted.
- FIG. 12 is a graph showing an example of the relationship between the input value and the output value of the clip processing unit 325 according to the first embodiment of the present technology.
- the horizontal axis represents the input value of the clip processing unit 325
- the vertical axis represents the output value of the clip processing unit 325.
- the clip processing unit 325 when the input value exceeds a predetermined upper limit value MAX, the clip processing unit 325 outputs the upper limit value MAX as an output value instead of the input value. Further, when the input value is less than the predetermined lower limit value MIN, the clip processing unit 325 outputs the lower limit value MIN as an output value instead of the input value. When the input value is equal to or greater than the lower limit value MIN and equal to or less than the upper limit value MAX, the input value is output as it is as an output value. By this clipping process, the value of the decimal part is limited to the range from the lower limit value MIN to the upper limit value MAX.
- FIG. 13 is a block diagram showing a configuration example of the storage unit 330 according to the first embodiment of the present technology.
- a plurality of memories 331 are arranged in the storage unit 330 in a predetermined X direction.
- the memory 331 is provided for each gain domain.
- the memory 331 corresponding to the mth gain domain is hereinafter referred to as “memory # m”.
- the memory #m holds a decimal part f cn_dm of the gain correction coefficient of the mth gain domain. As described above, since the gain correction coefficient is calculated for each column in each gain domain, N fractional parts f cn_dm are held in each of the memory # m, where N is the number of columns. These decimal parts f cn_dm are arranged in the Y direction perpendicular to the X direction.
- each of the M memories 331 in the X direction is set to a value corresponding to the number of digits of the decimal part f cn_dm to be held.
- the size of the mth memory 331 in the X direction is hereinafter referred to as X m . Assuming that the number of digits in the binary notation of the fractional part f cn_dm is W m , the size X m is a value proportional to W m.
- the physical size Y of each of the M memories 331 in the Y direction is substantially the same, and is a value proportional to N, which is the number of columns.
- substantially the same means a case where the sizes are exactly the same, or a case where the difference between the sizes is within a predetermined value.
- the reduction processing unit 322 reduces a part of the integer digits of the gain correction coefficient, the remaining integer digits and the decimal part are held in the memory 331 at the maximum.
- the reduction processing unit 322 reduces the integer part and a part of the decimal digits of the gain correction coefficient, the remaining decimal digits are held in the memory 331 at the maximum.
- the memory # 0 to the memory # M-1 are arranged in ascending order in the X direction, starting from the memory # 0 having the smallest size. Conversely, if memory # M-1 is considered as the starting point, they are arranged in descending order.
- the storage unit 330 further holds an offset correction coefficient as needed.
- the memory that holds the offset correction coefficient is omitted in the figure.
- the memory arrangement method is not limited to ascending order.
- a plurality of pairs of memories # m having substantially the same total size in each X direction can be arranged in a predetermined order.
- FIG. 15 is a diagram showing an example of processing of the correction value calculation unit 320 in the first embodiment of the present technology.
- a is a diagram showing an example of processing for the gain correction coefficient of the gain domain d0.
- Reference numeral b in the figure is an example of the gain correction coefficient after the reduction of the gain domains d0 to d6.
- the value of "1.0000000101101” in binary notation is calculated as the gain correction coefficient a cn_d0 in the gain domain d0.
- the correction value calculation unit 320 subtracts “1” from the gain correction coefficient a cn_d0 to obtain “0.0000000101101”. Further, a sign bit S indicating a sign after subtraction is generated.
- the correction value calculation unit 320 performs a clip process to reduce the first to sixth decimal places to "101101".
- the correction value calculation unit 320 can reduce the large number of digits and reduce the dynamic range of the decimal part as the analog gain becomes smaller.
- the number of digits of the gain correction coefficient in other words, reducing the dynamic range
- the required size of the memory 331 can be reduced.
- the number of gain domains is 7, the decimal digit before reduction is 12 digits, and the digit to be reduced in the mth gain domain is up to (6-m) digits.
- the 0th memory # 0 which has the smallest size, holds 7 bits of data for each column, including the code bit S.
- Memory # 1 holds 8 bits of data for each column, including the code bit S.
- the data size is increased by one bit, and the memory # 6, which has the largest size, holds 13 bits of data for each column, including the code bit S.
- the memory capacity can be reduced as compared with the comparative example. Since the physical size of the memory is proportional to the capacity, the size can be reduced by reducing the capacity.
- FIG. 16 is a block diagram showing a configuration example of the correction unit 350 according to the first embodiment of the present technology.
- the correction unit 350 includes a plurality of digit number expansion units 351, a multiplexer 352, an adder 353, and a multiplier 354.
- the digit number expansion unit 351 is provided for all gain domains other than the gain domain dM-1 in which decimal digits are not reduced.
- the digit number expansion unit 351 expands the number of digits of the fractional part fcn_dm of the gain correction coefficient of the corresponding gain domain to a predetermined value by zero padding or the like.
- the digit number expansion unit 351 supplies the expanded decimal part to the multiplexer 352.
- the digit number expansion unit 351 expands the part of the integer digits and the decimal digits.
- the digit number expansion unit 351 expands the part of the decimal digits. ..
- the decimal part of the gain domain dM-1 and the fractional part from each of the digit expansion units 351 are input to the multiplexer 352.
- a fractional part corresponding to the gain domain indicated by the correction target domain information from the controller 360 is selected and supplied to the adder 353.
- the adder 353 adds a reduced integer part (such as "1") to the decimal part from the multiplexer 352.
- the adder 353 supplies the addition result to the multiplier 354.
- the multiplier 354 multiplies the addition result of the adder 353 with the digital signal in the frame from the selector 340. By this multiplication, the result of correcting the digital signal by the gain correction coefficient before the reduction of the integer part is obtained.
- the multiplier 354 outputs the calculation result to the DSP circuit 120 as a corrected digital signal.
- the correction unit 350 makes corrections using an offset coefficient as necessary.
- the circuit that corrects by the offset coefficient is omitted. Further, the correction unit 350 can further perform dither processing.
- FIG. 17 is a diagram for explaining a method of correcting an analog gain error in the first embodiment of the present technology.
- Pixel 260 produces a pixel signal SIG
- test signal source 220 produces a predetermined level (high level or low level) test signal Tout.
- the selector 271 in the input switching unit 270 selects either the test signal Tout or the pixel signal SIG of the corresponding column according to the input switching signal SWin, and supplies the input signal Ain to the ADC 281 of the corresponding column.
- the ADC 281 increases or decreases the analog input signal Ain according to the analog gain selected by the capacitance ratio control signal Gctrl among the plurality of analog gains, and converts the increased or decreased input signal Ain into a digital signal Dout.
- the selector 340 selects either the gain error measuring unit 310 or the correction unit 350 as the output destination according to the output switching signal SWout, and outputs the digital signal Dout.
- the gain error measuring unit 310 measures the analog gain and offset for each column and each gain domain in order to correct the error of the analog gain and the offset, and supplies the measurement data to the correction value calculation unit 320.
- the gain correction coefficient calculation unit 321 in the correction value calculation unit 320 is for correcting the analog gain error for each column and each gain domain based on the test signal Tout (input) and the digital signal Dout (output). Calculate the gain correction coefficient.
- the reduction processing unit 322 reduces the number of digits of the gain correction coefficient to a value corresponding to the corresponding analog gain, and holds the memory in a memory having a size corresponding to the number of digits after the reduction among the plurality of memories 331.
- the correction unit 350 corrects the digital signal Dout with the output correction value (gain correction coefficient, etc.). By this correction, it is possible to remove the vertical streak-shaped fixed pattern noise caused by the variation of the analog gain for each column.
- FIG. 18 is a flowchart showing an example of the operation of the solid-state image sensor 200 according to the first embodiment of the present technology.
- the operation of the solid-state image sensor 200 is started, for example, when a predetermined application for capturing image data is executed.
- the column signal processing unit 280 in the solid-state image sensor 200 AD-converts the test signal for all of the gain domains (step S901).
- the gain error measuring unit 310 measures the gain error for each column and each gain domain (step S902).
- the correction value calculation unit 320 calculates the correction value for each column and each gain domain, and causes the storage unit 330 to hold the correction value (step S903).
- the column signal processing unit 280 AD-converts the pixel signals of all the pixels to generate a frame (step S904).
- the correction unit 350 corrects the digital signal in the frame according to the correction value (step S905).
- the column signal processing unit 280 AD-converts the test signal for the gain domain to be measured (step S906).
- the gain error measuring unit 310 measures the gain error for each column for the gain domain (step S907).
- the correction value calculation unit 320 determines whether or not an update pulse has been generated (step S908). When the update pulse is not generated (step S908: No), the solid-state image sensor 200 repeats steps S904 and subsequent steps.
- step S908 when an update pulse is generated (step S908: Yes), the correction value calculation unit 320 calculates a correction value for each column for the gain domain to be corrected, and updates based on the calculation result (step S909). After step S909, the solid-state image sensor 200 repeatedly executes step S904 and subsequent steps.
- the solid-state image sensor 200 does not have to perform the division process when there is little deterioration over time.
- steps S906 to S909 are not executed, and after step S905, steps S904 and subsequent steps are repeatedly executed.
- the reduction processing unit 322 reduces the number of digits of the gain correction coefficient according to the analog gain, so that the number of digits is not changed as compared with the case where the number of digits is not changed.
- the required memory capacity can be reduced.
- Second Embodiment> In the first embodiment described above, a plurality of memories 331 are arranged in the X direction in the storage unit 330, but in this arrangement, the storage unit 330 is arranged in the X direction as the number of the memories 331 increases. May increase size.
- the storage unit 330 of the second embodiment is different from the first embodiment in that the arrangement of the memory 331 is changed to reduce the size in the X direction.
- FIG. 20 is a block diagram showing a configuration example of the storage unit 330 according to the second embodiment of the present technology.
- the M memories 331 are grouped into two groups. Let the number of one of the two groups be K (K is an integer less than M-1). In one of the groups, memories # 0 to # K-1 are arranged in the X direction. In the other group, the remaining memories # K to # M-1 are arranged in the X direction.
- Each Y-direction size of the memory # 0 to # K-1 is substantially identical to the size and Y 1. Further, the sizes of the memories # 0 to # K-1 in the X direction are different, and the values correspond to the analog gain.
- the sizes of the memories # K to # M-1 in the Y direction are substantially the same, and the size is defined as Y 2 .
- This Y 2 is set to a value larger than Y 1.
- the size X K in the X direction is smaller than the X K-1 of the memory # K-1 by the amount that the size in the Y direction is increased. For example, if the number of digits of the binary representation of the decimal part of the memory #K and W K, the size X K in the X direction is set to a value proportional to W K ⁇ (Y 1 / Y 2). Further, the sizes of the memories # K to # M-1 in the X direction are different, and the values correspond to the analog gain.
- the M memories 331 are divided into two groups having different sizes in the Y direction and the memories 331 are arranged in the X direction in each group, the size of the storage unit 330 in the X direction can be reduced. Can be done.
- the M memories 331 are divided into two groups having different sizes in the Y direction, and the memories 331 are arranged in the X direction in each group.
- the size in the X direction can be reduced.
- the M memories 331 are divided into two groups having different sizes in the Y direction, and the memories 331 are arranged in the X direction in each group. However, in this array, the size of the memory 331 in the X direction is different.
- the storage unit 330 of the modified example of this second embodiment is different from the first embodiment in which the arrangement of the memory 331 is changed and the sizes in the X direction are aligned.
- FIG. 21 is a block diagram showing a configuration example of the storage unit 330 according to the second embodiment of the present technology.
- the sizes of the memories 331 in the X direction are substantially the same, and the size in the Y direction is a value corresponding to the analog gain.
- a plurality of pairs of memories 331 are arranged in the X direction in a predetermined order. In each set, the pair of memories are arranged in the Y direction, and the total size of each set in the Y direction is substantially the same.
- the sizes of the respective memories 331 in the X direction can be made substantially the same.
- the technology according to the present disclosure can be applied to various products.
- the technology according to the present disclosure is realized as a device mounted on a moving body of any kind such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. You may.
- FIG. 22 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technique according to the present disclosure can be applied.
- the vehicle control system 12000 includes a plurality of electronic control units connected via the communication network 12001.
- the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050.
- a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown as a functional configuration of the integrated control unit 12050.
- the drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs.
- the drive system control unit 12010 provides a driving force generator for generating the driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism for adjusting and a braking device for generating a braking force of a vehicle.
- the body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs.
- the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, blinkers or fog lamps.
- the body system control unit 12020 may be input with radio waves transmitted from a portable device that substitutes for the key or signals of various switches.
- the body system control unit 12020 receives inputs of these radio waves or signals and controls a vehicle door lock device, a power window device, a lamp, and the like.
- the vehicle outside information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000.
- the image pickup unit 12031 is connected to the vehicle exterior information detection unit 12030.
- the vehicle outside information detection unit 12030 causes the image pickup unit 12031 to capture an image of the outside of the vehicle and receives the captured image.
- the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as a person, a vehicle, an obstacle, a sign, or a character on the road surface based on the received image.
- the imaging unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of the light received.
- the image pickup unit 12031 can output an electric signal as an image or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.
- the in-vehicle information detection unit 12040 detects the in-vehicle information.
- a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040.
- the driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether or not the driver has fallen asleep.
- the microcomputer 12051 calculates the control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit.
- a control command can be output to 12010.
- the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, and the like. It is possible to perform cooperative control for the purpose of.
- ADAS Advanced Driver Assistance System
- the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform coordinated control for the purpose of automatic driving, etc., which runs autonomously without depending on the operation.
- the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030.
- the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the external information detection unit 12030, and performs coordinated control for the purpose of anti-glare such as switching the high beam to the low beam. It can be carried out.
- the audio image output unit 12052 transmits an output signal of at least one of audio and an image to an output device capable of visually or audibly notifying information to the passenger or the outside of the vehicle.
- an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices.
- the display unit 12062 may include, for example, at least one of an onboard display and a heads-up display.
- FIG. 23 is a diagram showing an example of the installation position of the imaging unit 12031.
- the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
- the imaging units 12101, 12102, 12103, 12104, 12105 are provided at positions such as the front nose, side mirrors, rear bumpers, back doors, and the upper part of the windshield in the vehicle interior of the vehicle 12100, for example.
- the imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100.
- the imaging units 12102 and 12103 provided in the side mirrors mainly acquire images of the side of the vehicle 12100.
- the imaging unit 12104 provided on the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100.
- the imaging unit 12105 provided on the upper part of the windshield in the vehicle interior is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.
- FIG. 23 shows an example of the photographing range of the imaging units 12101 to 12104.
- the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
- the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively
- the imaging range 12114 indicates the imaging range of the imaging units 12102 and 12103.
- the imaging range of the imaging unit 12104 provided on the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 as viewed from above can be obtained.
- At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
- at least one of the image pickup units 12101 to 12104 may be a stereo camera composed of a plurality of image pickup elements, or may be an image pickup element having pixels for phase difference detection.
- the microcomputer 12051 uses the distance information obtained from the imaging units 12101 to 12104 to obtain the distance to each three-dimensional object within the imaging range 12111 to 12114 and the temporal change of this distance (relative velocity with respect to the vehicle 12100). By obtaining, it is possible to extract as the preceding vehicle a three-dimensional object that is the closest three-dimensional object on the traveling path of the vehicle 12100 and that travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or more). can.
- a predetermined speed for example, 0 km / h or more.
- the microcomputer 12051 can set an inter-vehicle distance to be secured in front of the preceding vehicle in advance, and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform coordinated control for the purpose of automatic driving or the like in which the vehicle travels autonomously without depending on the operation of the driver.
- the microcomputer 12051 converts three-dimensional object data related to a three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that can be seen by the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 is used via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.
- At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
- the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104.
- pedestrian recognition includes, for example, a procedure for extracting feature points in an image captured by an imaging unit 12101 to 12104 as an infrared camera, and pattern matching processing for a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. It is done by the procedure to determine.
- the audio image output unit 12052 When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 outputs a square contour line for emphasizing the recognized pedestrian.
- the display unit 12062 is controlled so as to superimpose and display. Further, the audio image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.
- the above is an example of a vehicle control system to which the technology according to the present disclosure can be applied.
- the technique according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above.
- the image pickup apparatus 100 of FIG. 1 can be applied to the image pickup unit 12031.
- the present technology can have the following configurations.
- An analog-to-digital converter that increases or decreases the analog signal according to the selected analog gain from a plurality of analog gains and converts the increased or decreased analog signal into a digital signal.
- a gain correction coefficient calculation unit that calculates a correction coefficient for correcting the error of the selected analog gain as a gain correction coefficient based on the digital signal, and a gain correction coefficient calculation unit.
- a solid-state image sensor including a reduction processing unit that reduces the number of digits of the gain correction coefficient to a value corresponding to the analog gain and holds the memory in a size corresponding to the number of digits after reduction among the plurality of memories.
- the plurality of memories are arranged in a predetermined direction.
- the sizes of the plurality of memories in the predetermined direction are different from each other.
- the solid-state image sensor according to (1) above wherein the sizes of the plurality of memories in the direction perpendicular to the predetermined direction are substantially the same.
- the plurality of memories are grouped into two groups. A predetermined number of memories belonging to each of the two groups have different sizes in a predetermined direction from each other and are arranged in the predetermined direction.
- the solid-state image sensor according to (1) wherein the size of one of the two groups in the direction perpendicular to the predetermined direction is different from that of the other.
- the sizes of the plurality of memories in the predetermined directions are substantially the same. The sizes of the plurality of memories in the direction perpendicular to the predetermined direction are different from each other.
- a plurality of sets, each consisting of a pair of memories, are arranged in the predetermined direction.
- the pair of memories are arranged in the vertical direction and are arranged in the vertical direction.
- An input switching unit that inputs either a predetermined level test signal or a pixel signal as the analog signal to the analog-to-digital converter.
- a correction unit that corrects the digital signal by the retained gain correction coefficient is further provided.
- the solid-state image sensor according to any one of (1) to (5), wherein the gain correction coefficient calculation unit calculates the gain correction coefficient from the test signal and the digital signal. (7) The solid-state image sensor according to (6), wherein the correction unit expands the number of digits of the held gain correction coefficient to a predetermined value and performs correction.
- the analog-to-digital converter is A comparator that compares the analog signal with a predetermined lamp signal and outputs a comparison result, A digital signal generation unit that generates the digital signal based on the comparison result is provided.
- the comparator A differential amplifier circuit that amplifies the difference between the predetermined reference voltage and the voltage of the predetermined node and outputs it as the comparison result.
- the plurality of analog gains are grouped into a plurality of gain domains having different capacitance ratios.
- An analog-to-digital converter that increases or decreases the analog signal according to the analog gain selected from the plurality of analog gains and converts the increased or decreased analog signal into a digital signal.
- a gain correction coefficient calculation unit that calculates a correction coefficient for correcting the error of the selected analog gain as a gain correction coefficient based on the digital signal, and a gain correction coefficient calculation unit.
- a reduction processing unit that reduces the number of digits of the gain correction coefficient to a value corresponding to the analog gain and holds the memory in a size corresponding to the number of digits after reduction among the plurality of memories.
- An image pickup apparatus including an image signal processing unit that processes an image signal in which digital signals corrected by the held gain correction coefficient are arranged.
- Image sensor 110 Optical unit 120
- DSP circuit 130 Display unit 140 Operation unit 150
- Bus 160 Frame memory 170
- Power supply unit 200 Solid-state image sensor 201 Pixel chip 202 Circuit chip 210 Vertical scanning circuit 220 Test signal source 230 DAC 240 Timing control circuit 250 pixel array unit 260 pixels 261 photoelectric conversion element 262 Transfer transistor 263 Reset transistor 264 Floating diffusion layer 265 Amplification transistor 266 Selection transistor 270 Input switching unit 271, 340 Selector 280 Column signal processing unit 281 ADC 282 Counter 300 Image processing unit 310 Gain error measurement unit 311 Sample number counter 312 Update pulse generation unit 313 Gain calculation unit 314 Offset calculation unit 320 Correction value calculation unit 321 Gain correction coefficient calculation unit 322 Reduction processing unit 323 Subtractor 324 Demultiplexer 325 Clip processing unit 326 Fractional digit reduction unit 330 Storage unit 331 Memory 350 Correction unit 351 Digit number expansion unit 352 Multiplexer 353 Adder 354 Multiplier 360 controller 400 Comparator 410 Capacity ratio switching circuit 411
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Abstract
The present invention reduces the capacity of memories in a solid-state imaging element which holds correction coefficients for each column. An analog-to-digital converter increases and decreases an analog signal via an analog gain selected from among a plurality of analog gains, and converts the increased and decreased analog signal into a digital signal. A plurality of memories respectively have different sizes. A gain correction coefficient calculation unit calculates, as a gain correction coefficient, the correction coefficient for correcting an error of the selected analog gain on the basis of the digital signal. A reduction processing unit reduces the number of digits of the gain correction coefficient to a value corresponding to the analog gain, and stores the gain correction coefficient in a memory having a size according to the number of digits after the reduction among the plurality of memories.
Description
本技術は、固体撮像素子に関する。詳しくは、カラム毎にアナログ信号をデジタル信号に変換する固体撮像素子、撮像装置、および、固体撮像素子の制御方法に関する。
This technology relates to a solid-state image sensor. More specifically, the present invention relates to a solid-state image sensor that converts an analog signal into a digital signal for each column, an image pickup device, and a control method for the solid-state image sensor.
従来より、固体撮像素子などにおいては、アナログ信号をデジタル信号に変換するために、シングルスロープ型などの各種のADCが用いられている。このADCをカラム毎に配置した場合、ADCのそれぞれのアナログゲインのばらつきに起因して筋状の固定パターンノイズが生じるおそれがある。そこで、アナログゲインのばらつきを補正するための補正係数をカラム毎に算出し、メモリに保持しておく固体撮像素子が提案されている(例えば、特許文献1参照。)。
Conventionally, in solid-state image sensors and the like, various ADCs such as a single slope type have been used in order to convert an analog signal into a digital signal. When this ADC is arranged for each column, streaky fixed pattern noise may occur due to variations in the analog gains of the ADCs. Therefore, a solid-state image sensor has been proposed in which a correction coefficient for correcting variations in analog gain is calculated for each column and stored in a memory (see, for example, Patent Document 1).
上述の従来技術では、メモリからカラム毎の補正係数を読み出して補正に用いることにより、固定パターンノイズの低減を図っている。しかしながら、カラム数が増大するほど補正係数の個数が多くなり、それらを保持するのに必要なメモリの容量が大きくなってしまう。メモリの容量が大きくなるほど、メモリの物理的なサイズや製造コストが増大するため、メモリの容量を削減することが望ましい。
In the above-mentioned conventional technique, fixed pattern noise is reduced by reading the correction coefficient for each column from the memory and using it for correction. However, as the number of columns increases, the number of correction coefficients increases, and the amount of memory required to hold them increases. As the memory capacity increases, the physical size of the memory and the manufacturing cost increase, so it is desirable to reduce the memory capacity.
本技術はこのような状況に鑑みて生み出されたものであり、カラム毎に補正係数を保持する固体撮像素子において、メモリの容量を削減することを目的とする。
This technology was created in view of this situation, and aims to reduce the memory capacity of a solid-state image sensor that holds a correction coefficient for each column.
本技術は、上述の問題点を解消するためになされたものであり、その第1の側面は、複数のアナログゲインのうち選択されたアナログゲインによりアナログ信号を増減して当該増減したアナログ信号をデジタル信号に変換するアナログデジタル変換器と、サイズの異なる複数のメモリと、上記選択されたアナログゲインの誤差を補正するための補正係数を上記デジタル信号に基づいてゲイン補正係数として演算するゲイン補正係数演算部と、上記ゲイン補正係数の桁数を上記アナログゲインに応じた値に削減して上記複数のメモリのうち削減後の桁数に応じたサイズのメモリに保持させる削減処理部とを具備する固体撮像素子、および、その制御方法である。これにより、必要なメモリの容量が削減されるという作用をもたらす。
The present technology has been made to solve the above-mentioned problems, and the first aspect thereof is to increase or decrease the analog signal by the analog gain selected from the plurality of analog gains to increase or decrease the analog signal. An analog-to-digital converter that converts to a digital signal, multiple memories of different sizes, and a gain correction coefficient that calculates the correction coefficient for correcting the error of the selected analog gain as a gain correction coefficient based on the digital signal. It is provided with a calculation unit and a reduction processing unit that reduces the number of digits of the gain correction coefficient to a value corresponding to the analog gain and holds it in a memory having a size corresponding to the number of digits after reduction among the plurality of memories. A solid-state imaging device and a control method thereof. This has the effect of reducing the amount of memory required.
また、この第1の側面において、上記複数のメモリは、所定方向に配列され、上記複数のメモリのそれぞれの上記所定方向のサイズは互いに異なり、上記複数のメモリのそれぞれの上記所定方向に垂直な方向のサイズは略同一であってもよい。これにより、所定方向に垂直な方向のメモリのサイズが削減されるという作用をもたらす。
Further, in the first aspect, the plurality of memories are arranged in a predetermined direction, the sizes of the plurality of memories in the predetermined direction are different from each other, and the sizes of the plurality of memories are perpendicular to each of the predetermined directions. The size of the directions may be substantially the same. This has the effect of reducing the size of the memory in the direction perpendicular to the predetermined direction.
また、この第1の側面において、上記複数のメモリは、2つのグループにグループ化され、上記2つのグループのそれぞれに属する所定数のメモリは、互いに所定方向のサイズが異なり、上記所定方向に配列され、上記2つのグループの一方の上記所定方向に垂直な方向のサイズは、他方と異なってもよい。これにより、所定方向のメモリのサイズが削減されるという作用をもたらす。
Further, in the first aspect, the plurality of memories are grouped into two groups, and a predetermined number of memories belonging to each of the two groups are different in size in a predetermined direction from each other and are arranged in the predetermined direction. The size of one of the two groups in the direction perpendicular to the predetermined direction may be different from that of the other. This has the effect of reducing the size of the memory in the predetermined direction.
また、この第1の側面において、上記複数のメモリのそれぞれの所定方向のサイズは略同一であり、上記複数のメモリのそれぞれの上記所定方向に垂直な方向のサイズは互いに異なり、各々が一対のメモリからなる複数の組が上記所定方向に配列され、上記一対のメモリは、前記垂直な方向に配列され、上記複数の組のそれぞれの上記垂直な方向のサイズの合計は略同一であってもよい。これにより、所定方向のメモリのサイズが削減されるという作用をもたらす。
Further, in the first aspect, the sizes of the plurality of memories in the predetermined directions are substantially the same, and the sizes of the plurality of memories in the directions perpendicular to the predetermined directions are different from each other, and each of them is a pair. Even if a plurality of sets of memories are arranged in the predetermined direction, the pair of memories are arranged in the vertical direction, and the total size of each of the plurality of sets in the vertical direction is substantially the same. good. This has the effect of reducing the size of the memory in the predetermined direction.
また、この第1の側面において、上記削減処理部は、上記アナログゲインが小さいほど多くの桁数を削減してもよい。これにより、アナログゲインに応じてメモリの容量が削減されるという作用をもたらす。
Further, in this first aspect, the reduction processing unit may reduce the number of digits as the analog gain becomes smaller. This has the effect of reducing the memory capacity according to the analog gain.
また、この第1の側面において、所定レベルのテスト信号と画素信号とのいずれかを上記アナログ信号として上記アナログデジタル変換器に入力する入力切替部と、上記保持されたゲイン補正係数により上記デジタル信号の補正を行う補正部とをさらに具備し、上記ゲイン補正係数演算部は、上記テスト信号および上記デジタル信号から上記ゲイン補正係数を演算してもよい。これにより、テスト信号およびデジタル信号から演算されたゲイン補正係数がメモリに保持されるという作用をもたらす。
Further, in the first aspect, the digital signal is provided by an input switching unit that inputs one of a predetermined level test signal and a pixel signal as the analog signal to the analog digital converter and the retained gain correction coefficient. The gain correction coefficient calculation unit may further include a correction unit for correcting the above, and the gain correction coefficient calculation unit may calculate the gain correction coefficient from the test signal and the digital signal. This has the effect of holding the gain correction coefficient calculated from the test signal and the digital signal in the memory.
また、この第1の側面において、上記補正部は、上記保持されたゲイン補正係数の桁数を所定値に拡張して補正を行ってもよい。これにより、桁数が拡張されたゲイン補正係数により補正が行われるという作用をもたらす。
Further, in the first aspect, the correction unit may extend the number of digits of the retained gain correction coefficient to a predetermined value to perform correction. This has the effect that the correction is performed by the gain correction coefficient with the expanded number of digits.
また、この第1の側面において、上記アナログデジタル変換器は、上記アナログ信号と所定のランプ信号とを比較して比較結果を出力するコンパレータと、上記比較結果に基づいて上記デジタル信号を生成するデジタル信号生成部とを備え、上記コンパレータは、所定の基準電圧と所定ノードの電圧との差分を増幅して上記比較結果として出力する差動増幅回路と、上記所定ノードと上記入力切替部との間に挿入された垂直信号線側容量と、上記所定ノードと上記ランプ信号を生成するデジタルアナログ変換器との間に挿入されたランプ側容量と、上記垂直信号線側容量と上記ランプ側容量との容量比を所定の制御信号に従って変更するスイッチとを備え、上記複数のアナログゲインは、上記容量比が互いに異なる複数のゲインドメインにグループ化され、上記複数のメモリのそれぞれには、互いに異なるアナログゲインに対応する上記ゲイン補正係数が保持されてもよい。これにより、ゲインドメインごとのゲイン補正係数が保持されるという作用をもたらす。
Further, in the first aspect, the analog-to-digital converter has a comparator that compares the analog signal with a predetermined lamp signal and outputs a comparison result, and a digital that generates the digital signal based on the comparison result. The comparator includes a signal generation unit, and the comparator amplifies the difference between the predetermined reference voltage and the voltage of the predetermined node and outputs the difference as the comparison result, and between the predetermined node and the input switching unit. The vertical signal line side capacitance inserted in, the lamp side capacitance inserted between the predetermined node and the digital analog converter that generates the lamp signal, and the vertical signal line side capacitance and the lamp side capacitance. A switch for changing the capacitance ratio according to a predetermined control signal is provided, and the plurality of analog gains are grouped into a plurality of gain domains having different capacitance ratios, and each of the plurality of memories has different analog gains. The above gain correction coefficient corresponding to may be retained. This has the effect of maintaining the gain correction coefficient for each gain domain.
また、本技術の第2の側面は、複数のアナログゲインのうち選択されたアナログゲインによりアナログ信号を増減して当該増減したアナログ信号をデジタル信号に変換するアナログデジタル変換器と、サイズの異なる複数のメモリと、上記選択されたアナログゲインの誤差を補正するための補正係数を上記デジタル信号に基づいてゲイン補正係数として演算するゲイン補正係数演算部と、上記ゲイン補正係数の桁数を上記アナログゲインに応じた値に削減して上記複数のメモリのうち削減後の桁数に応じたサイズのメモリに保持させる削減処理部と、上記保持されたゲイン補正係数により補正されたデジタル信号を配列した画像信号を処理する画像信号処理部とを具備する撮像装置である。これにより、容量の削減されたメモリに保持されたゲイン補正係数によりデジタル信号が補正されるという作用をもたらす。
The second aspect of the present technology is an analog digital converter that increases or decreases the analog signal according to the analog gain selected from the plurality of analog gains and converts the increased or decreased analog signal into a digital signal, and a plurality of analog signals having different sizes. Memory, a gain correction coefficient calculation unit that calculates a correction coefficient for correcting the error of the selected analog gain as a gain correction coefficient based on the digital signal, and an analog gain that calculates the number of digits of the gain correction coefficient. An image in which a reduction processing unit that reduces the value according to the above and holds it in a memory of a size corresponding to the number of digits after reduction among the plurality of memories and a digital signal corrected by the held gain correction coefficient are arranged. It is an image pickup apparatus including an image signal processing unit that processes a signal. This brings about the effect that the digital signal is corrected by the gain correction coefficient held in the memory with the reduced capacity.
以下、本技術を実施するための形態(以下、実施の形態と称する)について説明する。説明は以下の順序により行う。
1.第1の実施の形態(アナログゲインに応じたサイズのメモリに補正値を保持する例)
2.第2の実施の形態(アナログゲインに応じたサイズのメモリの配列を変更し、補正値を保持する例)
3.移動体への応用例 Hereinafter, embodiments for carrying out the present technology (hereinafter referred to as embodiments) will be described. The explanation will be given in the following order.
1. 1. First Embodiment (Example of holding a correction value in a memory of a size corresponding to an analog gain)
2. Second embodiment (example of changing the memory array of the size according to the analog gain and holding the correction value)
3. 3. Application example to mobile
1.第1の実施の形態(アナログゲインに応じたサイズのメモリに補正値を保持する例)
2.第2の実施の形態(アナログゲインに応じたサイズのメモリの配列を変更し、補正値を保持する例)
3.移動体への応用例 Hereinafter, embodiments for carrying out the present technology (hereinafter referred to as embodiments) will be described. The explanation will be given in the following order.
1. 1. First Embodiment (Example of holding a correction value in a memory of a size corresponding to an analog gain)
2. Second embodiment (example of changing the memory array of the size according to the analog gain and holding the correction value)
3. 3. Application example to mobile
<1.第1の実施の形態>
[撮像装置の構成例]
図1は、本技術の第1の実施の形態における撮像装置100の一構成例を示すブロック図である。この撮像装置100は、画像データ(フレーム)を撮像するための装置であり、光学部110、固体撮像素子200およびDSP(Digital Signal Processing)回路120を備える。さらに撮像装置100は、表示部130、操作部140、バス150、フレームメモリ160、記憶部170および電源部180を備える。撮像装置100としては、例えば、デジタルスチルカメラなどのデジタルカメラの他、撮像機能を持つスマートフォンやパーソナルコンピュータ、車載カメラ等が想定される。 <1. First Embodiment>
[Configuration example of imaging device]
FIG. 1 is a block diagram showing a configuration example of theimage pickup apparatus 100 according to the first embodiment of the present technology. The image pickup device 100 is a device for taking an image of image data (frame), and includes an optical unit 110, a solid-state image sensor 200, and a DSP (Digital Signal Processing) circuit 120. Further, the image pickup apparatus 100 includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. As the image pickup device 100, for example, in addition to a digital camera such as a digital still camera, a smartphone having an image pickup function, a personal computer, an in-vehicle camera, or the like is assumed.
[撮像装置の構成例]
図1は、本技術の第1の実施の形態における撮像装置100の一構成例を示すブロック図である。この撮像装置100は、画像データ(フレーム)を撮像するための装置であり、光学部110、固体撮像素子200およびDSP(Digital Signal Processing)回路120を備える。さらに撮像装置100は、表示部130、操作部140、バス150、フレームメモリ160、記憶部170および電源部180を備える。撮像装置100としては、例えば、デジタルスチルカメラなどのデジタルカメラの他、撮像機能を持つスマートフォンやパーソナルコンピュータ、車載カメラ等が想定される。 <1. First Embodiment>
[Configuration example of imaging device]
FIG. 1 is a block diagram showing a configuration example of the
光学部110は、被写体からの光を集光して固体撮像素子200に導くものである。固体撮像素子200は、垂直同期信号に同期して、光電変換によりフレームを生成するものである。ここで、垂直同期信号は、撮像のタイミングを示す所定周波数の周期信号である。固体撮像素子200は、生成した画像データをDSP回路120に信号線209を介して供給する。
The optical unit 110 collects the light from the subject and guides it to the solid-state image sensor 200. The solid-state image sensor 200 generates a frame by photoelectric conversion in synchronization with a vertical synchronization signal. Here, the vertical synchronization signal is a periodic signal having a predetermined frequency indicating the timing of imaging. The solid-state image sensor 200 supplies the generated image data to the DSP circuit 120 via the signal line 209.
DSP回路120は、固体撮像素子200からのフレームに対して所定の信号処理を実行するものである。このDSP回路120は、処理後のフレームをバス150を介してフレームメモリ160などに出力する。
The DSP circuit 120 executes predetermined signal processing on the frame from the solid-state image sensor 200. The DSP circuit 120 outputs the processed frame to the frame memory 160 or the like via the bus 150.
表示部130は、フレームを表示するものである。表示部130としては、例えば、液晶パネルや有機EL(Electro Luminescence)パネルが想定される。操作部140は、ユーザの操作に従って操作信号を生成するものである。
The display unit 130 displays a frame. As the display unit 130, for example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed. The operation unit 140 generates an operation signal according to the operation of the user.
バス150は、光学部110、固体撮像素子200、DSP回路120、表示部130、操作部140、フレームメモリ160、記憶部170および電源部180が互いにデータをやりとりするための共通の経路である。
The bus 150 is a common route for the optical unit 110, the solid-state image sensor 200, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170, and the power supply unit 180 to exchange data with each other.
フレームメモリ160は、画像データを保持するものである。記憶部170は、フレームなどの様々なデータを記憶するものである。電源部180は、固体撮像素子200、DSP回路120や表示部130などに電源を供給するものである。
The frame memory 160 holds image data. The storage unit 170 stores various data such as frames. The power supply unit 180 supplies power to the solid-state image sensor 200, the DSP circuit 120, the display unit 130, and the like.
[固体撮像素子の構成例]
図2は、本技術の第1の実施の形態における固体撮像素子200の積層構造の一例を示す図である。この固体撮像素子200は、回路チップ202と、その回路チップ202に積層された画素チップ201とを備える。これらのチップは、ビアなどの接続部を介して電気的に接続される。なお、ビアの他、Cu-Cu接合やバンプにより接続することもできる。 [Structure example of solid-state image sensor]
FIG. 2 is a diagram showing an example of a laminated structure of the solid-state image sensor 200 according to the first embodiment of the present technology. The solid-state image sensor 200 includes a circuit chip 202 and a pixel chip 201 laminated on the circuit chip 202. These chips are electrically connected via a connection such as a via. In addition to vias, it can also be connected by Cu-Cu bonding or bumps.
図2は、本技術の第1の実施の形態における固体撮像素子200の積層構造の一例を示す図である。この固体撮像素子200は、回路チップ202と、その回路チップ202に積層された画素チップ201とを備える。これらのチップは、ビアなどの接続部を介して電気的に接続される。なお、ビアの他、Cu-Cu接合やバンプにより接続することもできる。 [Structure example of solid-state image sensor]
FIG. 2 is a diagram showing an example of a laminated structure of the solid-
図3は、本技術の第1の実施の形態における固体撮像素子200の一構成例を示すブロック図である。この固体撮像素子200は、垂直走査回路210、テスト信号源220、DAC230、タイミング制御回路240、画素アレイ部250、入力切替部270、カラム信号処理部280、および、画像処理部300を備える。
FIG. 3 is a block diagram showing a configuration example of the solid-state image sensor 200 according to the first embodiment of the present technology. The solid-state image sensor 200 includes a vertical scanning circuit 210, a test signal source 220, a DAC 230, a timing control circuit 240, a pixel array unit 250, an input switching unit 270, a column signal processing unit 280, and an image processing unit 300.
また、画素アレイ部250には、複数の画素260が二次元格子状に配列される。以下、所定の水平方向に配列された画素260の集合を「行」と称し、水平方向に垂直な方向に配列された画素260の集合を「列」または「カラム」と称する。
Further, in the pixel array unit 250, a plurality of pixels 260 are arranged in a two-dimensional grid pattern. Hereinafter, a set of pixels 260 arranged in a predetermined horizontal direction is referred to as a "row", and a set of pixels 260 arranged in a direction perpendicular to the horizontal direction is referred to as a "column" or a "column".
タイミング制御回路240は、垂直同期信号Vsyncに同期して垂直走査回路210、DAC230やカラム信号処理部280の動作タイミングを制御するものである。また、タイミング制御回路240には、連続する複数のフレームを含む動画の撮像開始を指示する撮像開始信号が入力される。撮像開始信号は、例えば、外部のホストコンピュータ(不図示)により生成される。
The timing control circuit 240 controls the operation timing of the vertical scanning circuit 210, the DAC 230, and the column signal processing unit 280 in synchronization with the vertical synchronization signal Vsync. Further, an imaging start signal instructing the start of imaging of a moving image including a plurality of consecutive frames is input to the timing control circuit 240. The imaging start signal is generated by, for example, an external host computer (not shown).
垂直走査回路210は、行を順に選択して駆動し、アナログの画素信号を入力切替部270に出力させるものである。
The vertical scanning circuit 210 selects and drives rows in order, and outputs an analog pixel signal to the input switching unit 270.
画素260は、垂直走査回路210の制御に従って、光電変換により画素信号を生成するものである。画素260のそれぞれは、画素信号を垂直信号線269を介して入力切替部270へ出力する。
Pixel 260 generates a pixel signal by photoelectric conversion under the control of the vertical scanning circuit 210. Each of the pixels 260 outputs a pixel signal to the input switching unit 270 via the vertical signal line 269.
テスト信号源220は、画像処理部300からの制御信号Tinに従って、所定レベルの信号をテスト信号として生成し、入力切替部270に信号線229を介して供給するものである。テスト信号源220として、例えば、DAC230と別途に設けられた補正用のDACが用いられる。
The test signal source 220 generates a signal of a predetermined level as a test signal according to the control signal Tin from the image processing unit 300, and supplies the signal to the input switching unit 270 via the signal line 229. As the test signal source 220, for example, a DAC for correction provided separately from the DAC 230 is used.
入力切替部270は、画像処理部300の制御に従って、列ごとに、その列の画素信号とテスト信号とのいずれかを選択するものである。この入力切替部270は、選択した信号を入力信号としてカラム信号処理部280に信号線279を介して供給する。
The input switching unit 270 selects either the pixel signal or the test signal of the column for each column according to the control of the image processing unit 300. The input switching unit 270 supplies the selected signal as an input signal to the column signal processing unit 280 via the signal line 279.
DAC230は、DA(Digital to Analog)変換により参照信号を生成して、カラム信号処理部280に信号線239を介して供給するものである。参照信号として、例えば、のこぎり刃状のランプ信号が用いられる。
The DAC 230 generates a reference signal by DA (Digital to Analog) conversion and supplies it to the column signal processing unit 280 via a signal line 239. As the reference signal, for example, a saw blade-shaped lamp signal is used.
カラム信号処理部280は、参照信号を用いて、列ごとにアナログの入力信号をデジタル信号に変換するものである。このカラム信号処理部280は、デジタル信号を画像処理部300に信号線289を介して供給する。
The column signal processing unit 280 converts an analog input signal into a digital signal for each column using a reference signal. The column signal processing unit 280 supplies a digital signal to the image processing unit 300 via the signal line 289.
画像処理部300は、デジタル信号を配列したフレームに対して所定の画像処理を行うものである。この画像処理は、固定パターンノイズを低減するための補正処理を含む。画像処理部300は、処理後のフレームをDSP回路120へ供給する。
The image processing unit 300 performs predetermined image processing on a frame in which digital signals are arranged. This image processing includes correction processing for reducing fixed pattern noise. The image processing unit 300 supplies the processed frame to the DSP circuit 120.
また、タイミング制御回路240と画像処理部300とには、外部からの設定情報が入力される。この設定情報は、例えば、撮像中のアナログゲインなどの設定値を示す情報であり、ホストコンピュータなどにより生成される。
Further, setting information from the outside is input to the timing control circuit 240 and the image processing unit 300. This setting information is information indicating a setting value such as an analog gain during imaging, and is generated by a host computer or the like.
また、固体撮像素子200内の上述の回路は、画素チップ201と回路チップ202とに分散して配置される。例えば、画素アレイ部250が画素チップ201に設けられ、画素アレイ部250以外の回路(カラム信号処理部280など)は、回路チップ202に配置される。なお、画素チップ201と回路チップ202とそれぞれに配置する回路は、この組み合わせに限定されない。例えば、画素アレイ部250と、入力切替部270と、カラム信号処理部280内のコンパレータとを画素チップ201に配置し、それ以外の回路を回路チップ202に配置することもできる。
Further, the above-mentioned circuit in the solid-state image sensor 200 is distributed and arranged in the pixel chip 201 and the circuit chip 202. For example, the pixel array unit 250 is provided on the pixel chip 201, and circuits other than the pixel array unit 250 (such as the column signal processing unit 280) are arranged on the circuit chip 202. The circuits arranged in the pixel chip 201 and the circuit chip 202 are not limited to this combination. For example, the pixel array unit 250, the input switching unit 270, and the comparator in the column signal processing unit 280 may be arranged on the pixel chip 201, and other circuits may be arranged on the circuit chip 202.
[画素の構成例]
図4は、本技術の第1の実施の形態における画素260の一構成例を示す回路図である。この画素260は、光電変換素子261、転送トランジスタ262、リセットトランジスタ263、浮遊拡散層264、増幅トランジスタ265および選択トランジスタ266を備える。 [Pixel configuration example]
FIG. 4 is a circuit diagram showing a configuration example of thepixel 260 according to the first embodiment of the present technology. The pixel 260 includes a photoelectric conversion element 261, a transfer transistor 262, a reset transistor 263, a floating diffusion layer 264, an amplification transistor 265, and a selection transistor 266.
図4は、本技術の第1の実施の形態における画素260の一構成例を示す回路図である。この画素260は、光電変換素子261、転送トランジスタ262、リセットトランジスタ263、浮遊拡散層264、増幅トランジスタ265および選択トランジスタ266を備える。 [Pixel configuration example]
FIG. 4 is a circuit diagram showing a configuration example of the
光電変換素子261は、入射光を光電変換して電荷を生成するものである。転送トランジスタ262は、垂直走査回路210からの転送信号TXに従って、光電変換素子261から浮遊拡散層264へ電荷を転送するものである。リセットトランジスタ263は、垂直走査回路210からのリセット信号RSTに従って、浮遊拡散層264の電荷量を初期化するものである。
The photoelectric conversion element 261 photoelectrically converts the incident light to generate an electric charge. The transfer transistor 262 transfers an electric charge from the photoelectric conversion element 261 to the floating diffusion layer 264 according to the transfer signal TX from the vertical scanning circuit 210. The reset transistor 263 initializes the charge amount of the floating diffusion layer 264 according to the reset signal RST from the vertical scanning circuit 210.
浮遊拡散層264は、電荷を蓄積し、電荷量に応じた電圧を生成するものである。増幅トランジスタ265は、浮遊拡散層264の電圧を増幅するものである。選択トランジスタ266は、垂直走査回路210からの選択信号SELに従って、増幅された電圧の信号を画素信号SIGとして出力するものである。列数をN(Nは、整数)として、第n(nは、1乃至Nの整数)列の画素信号は、垂直信号線269-nを介して入力切替部270に伝送される。
The floating diffusion layer 264 accumulates electric charges and generates a voltage according to the amount of electric charges. The amplification transistor 265 amplifies the voltage of the floating diffusion layer 264. The selection transistor 266 outputs a signal of the amplified voltage as a pixel signal SIG according to the selection signal SEL from the vertical scanning circuit 210. Assuming that the number of columns is N (N is an integer), the pixel signal of the nth (n is an integer of 1 to N) column is transmitted to the input switching unit 270 via the vertical signal line 269-n.
なお、画素260の回路は、光電変換により画素信号を生成することができるものであれば、同図に例示したものに限定されない。
The circuit of the pixel 260 is not limited to the one illustrated in the figure as long as it can generate a pixel signal by photoelectric conversion.
[入力切替部の構成例]
図5は、本技術の第1の実施の形態における入力切替部270の一構成例を示す回路図である。この入力切替部270は、複数のセレクタ271を備える。セレクタ271は、列ごとに設けられる。列数がNである場合、N個のセレクタ271が配列される。 [Configuration example of input switching unit]
FIG. 5 is a circuit diagram showing a configuration example of theinput switching unit 270 according to the first embodiment of the present technology. The input switching unit 270 includes a plurality of selectors 271. The selector 271 is provided for each column. When the number of columns is N, N selectors 271 are arranged.
図5は、本技術の第1の実施の形態における入力切替部270の一構成例を示す回路図である。この入力切替部270は、複数のセレクタ271を備える。セレクタ271は、列ごとに設けられる。列数がNである場合、N個のセレクタ271が配列される。 [Configuration example of input switching unit]
FIG. 5 is a circuit diagram showing a configuration example of the
セレクタ271は、画像処理部300からの入力切替信号SWinに従って、対応する列の画素信号SIGと、テスト信号源220からのテスト信号Toutとのいずれかを選択するものである。第n列のセレクタ271の2つの入力端子の一方は、垂直信号線269-nを介して画素アレイ部250に接続され、他方は、信号線229を介してテスト信号源220に接続される。また、第n列のセレクタ271の出力端子は、信号線279-nを介してカラム信号処理部280に接続される。セレクタ271は、選択した信号を入力信号Ainとして出力する。
The selector 271 selects either the pixel signal SIG of the corresponding column or the test signal Tout from the test signal source 220 according to the input switching signal SWin from the image processing unit 300. One of the two input terminals of the selector 271 in the nth column is connected to the pixel array unit 250 via the vertical signal line 269-n, and the other is connected to the test signal source 220 via the signal line 229. Further, the output terminal of the selector 271 in the nth column is connected to the column signal processing unit 280 via the signal line 279-n. The selector 271 outputs the selected signal as an input signal Ain.
[カラム信号処理部の構成例]
図6は、本技術の第1の実施の形態におけるカラム信号処理部280の一構成例を示すブロック図である。このカラム信号処理部280は、複数のADC281を備える。ADC281は、列ごとに設けられる。列数がNである場合、N個のADC281が配列される。 [Configuration example of column signal processing unit]
FIG. 6 is a block diagram showing a configuration example of the columnsignal processing unit 280 according to the first embodiment of the present technology. The column signal processing unit 280 includes a plurality of ADC 281s. ADC 281 is provided for each row. When the number of columns is N, N ADC281s are arranged.
図6は、本技術の第1の実施の形態におけるカラム信号処理部280の一構成例を示すブロック図である。このカラム信号処理部280は、複数のADC281を備える。ADC281は、列ごとに設けられる。列数がNである場合、N個のADC281が配列される。 [Configuration example of column signal processing unit]
FIG. 6 is a block diagram showing a configuration example of the column
ADC281は、対応する列のアナログの入力信号Ainをデジタル信号Doutに変換するものである。このADC281は、コンパレータ400およびカウンタ282を備える。
The ADC 281 converts the analog input signal Ain of the corresponding column into the digital signal Dout. The ADC 281 includes a comparator 400 and a counter 282.
コンパレータ400は、参照信号RMPと、対応する列の入力信号Ainとを比較するものである。このコンパレータ400は、比較結果CMPをカウンタ282に供給する。また、コンパレータ400には、タイミング制御回路240からのオートゼロ信号AZと、画像処理部300からの容量比制御信号Gctrlとが入力される。ここで、容量比制御信号Gctrlは、容量比の切り替えによりADC281のアナログゲインを制御するための信号である。
The comparator 400 compares the reference signal RMP with the input signal Ain in the corresponding column. The comparator 400 supplies the comparison result CMP to the counter 282. Further, the auto zero signal AZ from the timing control circuit 240 and the capacitance ratio control signal Gctrl from the image processing unit 300 are input to the comparator 400. Here, the capacitance ratio control signal Gctrl is a signal for controlling the analog gain of the ADC 281 by switching the capacitance ratio.
カウンタ282は、タイミング制御回路240の制御に従って、比較結果CMPが反転するまでの期間に亘って、計数値を計数するものである。このカウンタ282は、計数値を示す信号をデジタル信号Doutとして画像処理部300に供給する。なお、カウンタ282は、特許請求の範囲に記載のデジタル信号生成部の一例である。
The counter 282 counts the count value over a period until the comparison result CMP is inverted according to the control of the timing control circuit 240. The counter 282 supplies a signal indicating the count value to the image processing unit 300 as a digital signal Dout. The counter 282 is an example of the digital signal generation unit described in the claims.
同図に例示したように、コンパレータ400およびカウンタ282によりAD変換を行うADC281は、シングルスロープ型のADCと呼ばれる。
As illustrated in the figure, the ADC 281 that performs AD conversion by the comparator 400 and the counter 282 is called a single slope type ADC.
なお、コンパレータ400を用いてAD変換を行うものであれば、逐次比較型など、シングルスロープ型以外のADCをADC281として配置することもできる。逐次比較型のADCを配置する場合、カウンタ282の代わりに、SAR(Successive Approximation Register)ロジック回路と、レジスタとが配置される。このSARロジック回路は、比較結果CMPに基づいて入力信号に近似するような参照信号の値を求め、その値に参照信号を更新させるためのDAC制御信号を生成する。レジスタは、比較結果を配列したデジタル信号とDAC制御信号とを保持し、DAC230にDAC制御信号を出力しつつ、デジタル信号を画像処理部300に出力する。
If AD conversion is performed using the comparator 400, an ADC other than the single slope type such as a sequential comparison type can be arranged as the ADC 281. When a sequential comparison type ADC is arranged, a SAR (Successive Approximation Register) logic circuit and a register are arranged instead of the counter 282. This SAR logic circuit obtains a value of a reference signal that approximates the input signal based on the comparison result CMP, and generates a DAC control signal for updating the reference signal to that value. The register holds a digital signal in which the comparison results are arranged and a DAC control signal, and outputs the digital signal to the image processing unit 300 while outputting the DAC control signal to the DAC 230.
[コンパレータの構成例]
図7は、本技術の第1の実施の形態におけるコンパレータ400の一構成例を示す回路図である。このコンパレータ400には、容量比切替回路410と差動増幅回路430とが配置される。容量比切替回路410は、スイッチ411乃至415などの所定数のスイッチと、容量416乃至421などの複数の容量とを備える。 [Comparator configuration example]
FIG. 7 is a circuit diagram showing a configuration example of thecomparator 400 according to the first embodiment of the present technology. A capacitance ratio switching circuit 410 and a differential amplifier circuit 430 are arranged in the comparator 400. The capacity ratio switching circuit 410 includes a predetermined number of switches such as switches 411 to 415 and a plurality of capacities such as capacities 416 to 421.
図7は、本技術の第1の実施の形態におけるコンパレータ400の一構成例を示す回路図である。このコンパレータ400には、容量比切替回路410と差動増幅回路430とが配置される。容量比切替回路410は、スイッチ411乃至415などの所定数のスイッチと、容量416乃至421などの複数の容量とを備える。 [Comparator configuration example]
FIG. 7 is a circuit diagram showing a configuration example of the
容量416乃至421の一端は、ノード422に共通に接続される。容量416の他端は、信号線279-nを介して入力切替部270に接続され、容量421の他端は、信号線239を介してDAC230と接続される。
One end of the capacities 416 to 421 is commonly connected to the node 422. The other end of the capacitance 416 is connected to the input switching unit 270 via the signal line 279-n, and the other end of the capacitance 421 is connected to the DAC 230 via the signal line 239.
スイッチ411は、容量比制御信号Gctrlに従って容量416の他端と、容量417の他端との間の経路を開閉するものである。スイッチ412は、容量比制御信号Gctrlに従って容量417の他端と、容量418の他端との間の経路を開閉するものである。スイッチ413は、容量比制御信号Gctrlに従って容量418の他端と、容量419の他端との間の経路を開閉するものである。スイッチ414は、容量比制御信号Gctrlに従って容量419の他端と、容量420の他端との間の経路を開閉するものである。スイッチ415は、容量比制御信号Gctrlに従って容量420の他端と、容量421の他端との間の経路を開閉するものである。
The switch 411 opens and closes the path between the other end of the capacitance 416 and the other end of the capacitance 417 according to the capacitance ratio control signal Gctrl. The switch 412 opens and closes the path between the other end of the capacitance 417 and the other end of the capacitance 418 according to the capacitance ratio control signal Gctrl. The switch 413 opens and closes the path between the other end of the capacitance 418 and the other end of the capacitance 419 according to the capacitance ratio control signal Gctrl. The switch 414 opens and closes a path between the other end of the capacitance 419 and the other end of the capacitance 420 according to the capacitance ratio control signal Gctrl. The switch 415 opens and closes a path between the other end of the capacitance 420 and the other end of the capacitance 421 according to the capacitance ratio control signal Gctrl.
画像処理部300は、容量比制御信号Gctrlにより、スイッチ411乃至415のいずれかのみを開状態にし、残りを閉状態に制御する。この制御により、垂直信号線側の信号線279-nとノード422との間に挿入された容量の合成容量と、ランプ信号側の信号線239とノード422との間に挿入された容量の合成容量との容量比が変更される。以下、垂直信号線側の合成容量を「VSL側容量」と称し、ランプ信号側の合成容量を「ランプ側容量」と称する。同図において、画像処理部300は、5つのスイッチの制御により容量比を5段階に切り替えることができる。
The image processing unit 300 controls only one of the switches 411 to 415 to be in the open state and the rest to the closed state by the capacitance ratio control signal Gctrl. By this control, the combined capacitance of the capacitance inserted between the signal line 279-n on the vertical signal line side and the node 422 and the combined capacitance inserted between the signal line 239 on the lamp signal side and the node 422 are combined. The capacity ratio with the capacity is changed. Hereinafter, the combined capacitance on the vertical signal line side is referred to as "VSL side capacitance", and the combined capacitance on the lamp signal side is referred to as "lamp side capacitance". In the figure, the image processing unit 300 can switch the capacitance ratio in five stages by controlling five switches.
なお、容量比を5段階としているが、画像処理部300は、5段階以外の複数の段階に容量比を切り替えることもできる。段階数をM(Mは、整数)とすると、M個のスイッチとM+1個の容量とが容量比切替回路410に配置される。
Although the capacity ratio is set to 5 stages, the image processing unit 300 can switch the capacity ratio to a plurality of stages other than the 5 stages. Assuming that the number of stages is M (M is an integer), M switches and M + 1 capacitances are arranged in the capacitance ratio switching circuit 410.
また、容量416の容量値は最も大きく、容量417乃至421のそれぞれの容量値は同一に設定される。なお、容量416乃至421のそれぞれの容量値は、任意の値に設定することができる。
Further, the capacity value of the capacity 416 is the largest, and the capacity values of the capacities 417 to 421 are set to be the same. The respective capacity values of the capacities 416 to 421 can be set to arbitrary values.
容量440は、所定の基準電圧VSHを保持するものである。
The capacity 440 holds a predetermined reference voltage VSH.
差動増幅回路430は、ノード422の電圧と、基準電圧VSHとの差分を増幅するものである。この差動増幅回路430は、pMOSトランジスタ431および432と、オートゼロスイッチ436および437と、nMOSトランジスタ433乃至435とを備える。
The differential amplifier circuit 430 amplifies the difference between the voltage of the node 422 and the reference voltage VSH. The differential amplifier circuit 430 includes pMOS transistors 431 and 432, auto-zero switches 436 and 437, and nMOS transistors 433 to 435.
pMOSトランジスタ431および432は、電源に並列に接続される。pMOSトランジスタ431のゲートは、自身のドレインとpMOSトランジスタ432のゲートとに接続される。
The pMOS transistors 431 and 432 are connected in parallel to the power supply. The gate of the pMOS transistor 431 is connected to its own drain and the gate of the pMOS transistor 432.
nMOSトランジスタ433のドレインは、pMOSトランジスタ431に接続され、ソースは、コモンノードに接続される。また、nMOSトランジスタ433のゲートは、ノード422に接続される。nMOSトランジスタ434のドレインは、pMOSトランジスタ432に接続され、ソースは、コモンノードに接続される。また、nMOSトランジスタ434のゲートは、容量440に接続される。
The drain of the nMOS transistor 433 is connected to the pMOS transistor 431, and the source is connected to the common node. Further, the gate of the nMOS transistor 433 is connected to the node 422. The drain of the nMOS transistor 434 is connected to the pMOS transistor 432 and the source is connected to the common node. Further, the gate of the nMOS transistor 434 is connected to the capacitance 440.
nMOSトランジスタ435は、コモンノードと接地端子との間に挿入され、ゲートには、所定のバイアス電圧Vbiasが入力される。
The nMOS transistor 435 is inserted between the common node and the ground terminal, and a predetermined bias voltage Vbias is input to the gate.
オートゼロスイッチ436は、タイミング制御回路240からのオートゼロ信号AZに従ってnMOSトランジスタ433のドレインおよびゲートの間を短絡するものである。オートゼロスイッチ437は、オートゼロ信号AZに従ってnMOSトランジスタ434のドレインおよびゲートの間を短絡するものである。
The auto zero switch 436 short-circuits between the drain and the gate of the nMOS transistor 433 according to the auto zero signal AZ from the timing control circuit 240. The auto zero switch 437 short-circuits between the drain and the gate of the nMOS transistor 434 according to the auto zero signal AZ.
また、pMOSトランジスタ432およびnMOSトランジスタ434の接続点からは、比較結果CMPがカウンタ282へ出力される。
Further, the comparison result CMP is output to the counter 282 from the connection point of the pMOS transistor 432 and the nMOS transistor 434.
同図に例示した構成のコンパレータ400には、AD変換期間内に、時間の経過とともにレベルが増大するランプ信号が参照信号RMPとして入力される。
A lamp signal whose level increases with the passage of time is input as a reference signal RMP to the comparator 400 having the configuration illustrated in the figure.
図8は、本技術の第1の実施の形態におけるゲインドメインごとのVSL側容量およびランプ側容量の一例を示す図である。
FIG. 8 is a diagram showing an example of VSL side capacity and lamp side capacity for each gain domain in the first embodiment of the present technology.
ここで、ADC281のアナログゲインは、参照信号RMP(ランプ信号)のスロープの傾きと、VSL側容量およびランプ側容量の容量比とにより制御することができる。スロープの傾きを緩やかにするほど、アナログゲインが高くなる。また、容量比に応じてアナログゲインが増減する。スロープの傾きをK(Kは、整数)段階に制御し、容量比をM段階に制御した場合、K×M段階のアナログゲインを実現することができる。これらのK×M個のアナログゲインを、容量比が互いに異なるM個のグループに分類し、それらのグループを以下、「ゲインドメイン」と称する。例えば、容量比を5段階に切り替えることができる場合、ゲインドメインd0乃至d4の5つにアナログゲインをグループ化することができる。個々のゲインドメイン内においては、容量比が同一に設定され、スロープの傾きにより、複数段にアナログゲインが制御される。ホストコンピュータは、例えば、環境光の光量を測定し、測光量が高いほど、アナログゲインを低くする。
Here, the analog gain of the ADC 281 can be controlled by the slope inclination of the reference signal RMP (lamp signal) and the capacitance ratio of the VSL side capacitance and the lamp side capacitance. The gentler the slope, the higher the analog gain. In addition, the analog gain increases or decreases according to the capacitance ratio. When the slope inclination is controlled in K (K is an integer) step and the capacitance ratio is controlled in M step, an analog gain in K × M step can be realized. These K × M analog gains are classified into M groups having different capacitance ratios, and these groups are hereinafter referred to as “gain domains”. For example, when the capacitance ratio can be switched in 5 steps, the analog gain can be grouped into 5 gain domains d0 to d4. Within each gain domain, the capacitance ratio is set to be the same, and the analog gain is controlled in multiple stages by the slope inclination. The host computer, for example, measures the amount of ambient light, and the higher the amount of metering, the lower the analog gain.
同図の縦軸は、VSL側容量またはランプ側容量を示し、横軸はアナログゲインを示す。ゲインドメインd0において、VSL側容量は、ランプ側容量と同一である。ゲインドメインd1乃至d4では、VSL側容量がランプ側容量より大きくなる。VSL側容量が大きくなるほど、アナログゲインが大きくなる。
The vertical axis of the figure shows the VSL side capacity or the lamp side capacity, and the horizontal axis shows the analog gain. In the gain domain d0, the VSL side capacitance is the same as the lamp side capacitance. In the gain domains d1 to d4, the VSL side capacitance is larger than the lamp side capacitance. The larger the VSL side capacitance, the larger the analog gain.
[画像処理部の構成例]
図9は、本技術の第1の実施の形態における画像処理部300の一構成例を示すブロック図である。この画像処理部300は、ゲイン誤差測定部310、補正値計算部320、記憶部330、セレクタ340、補正部350およびコントローラ360を備える。 [Configuration example of image processing unit]
FIG. 9 is a block diagram showing a configuration example of theimage processing unit 300 according to the first embodiment of the present technology. The image processing unit 300 includes a gain error measuring unit 310, a correction value calculation unit 320, a storage unit 330, a selector 340, a correction unit 350, and a controller 360.
図9は、本技術の第1の実施の形態における画像処理部300の一構成例を示すブロック図である。この画像処理部300は、ゲイン誤差測定部310、補正値計算部320、記憶部330、セレクタ340、補正部350およびコントローラ360を備える。 [Configuration example of image processing unit]
FIG. 9 is a block diagram showing a configuration example of the
セレクタ340は、コントローラ360からの出力切替信号SWoutに従って、カラム信号処理部280からのデジタル信号Doutをゲイン誤差測定部310および補正部350のいずれかに出力するものである。
The selector 340 outputs the digital signal Dout from the column signal processing unit 280 to either the gain error measuring unit 310 or the correction unit 350 according to the output switching signal SWout from the controller 360.
ゲイン誤差測定部310は、セレクタ340からのデジタル信号から、アナログゲインの誤差を表すパラメータを測定するものである。ここで、カラムごとにADC281を設けた場合、ADC281のそれぞれのアナログゲインには誤差が生じることがあり、その誤差もカラム毎に異なることが多い。このカラム間の相対的なゲイン誤差に起因して、固定のパターンノイズが生じるおそれがある。アナログゲインの誤差は、例えば、コンパレータ400内のアナログ回路の製品ばらつきや、経時劣化により生じる。そこで、ゲイン誤差測定部310は、アナログゲインを揃えるために、カラム毎およびゲインドメイン毎に複数回に亘って輝度レベルの誤差を測定し、それらを元にカラム間の相対的なゲイン誤差を求める。アナログゲインを得るためのAD変換の回数は、ホストコンピュータからの設定情報により、サンプル数として設定される。そして、ゲイン誤差測定部310は、求めた誤差を測定データとして補正値計算部320に供給する。
The gain error measuring unit 310 measures a parameter representing an analog gain error from a digital signal from the selector 340. Here, when the ADC 281 is provided for each column, an error may occur in each analog gain of the ADC 281, and the error is often different for each column. Fixed pattern noise can occur due to the relative gain error between the columns. The analog gain error is caused by, for example, product variation of the analog circuit in the comparator 400 and deterioration over time. Therefore, the gain error measuring unit 310 measures the brightness level error a plurality of times for each column and each gain domain in order to make the analog gain uniform, and obtains the relative gain error between the columns based on them. .. The number of AD conversions for obtaining the analog gain is set as the number of samples according to the setting information from the host computer. Then, the gain error measuring unit 310 supplies the obtained error as measurement data to the correction value calculation unit 320.
また、ゲイン誤差測定部310は、コントローラ360からのサンプル数に基づいて更新パルスを生成し、測定データとともに補正値計算部320に供給する。この更新パルスは、補正値の更新タイミングを指示する信号である。
Further, the gain error measurement unit 310 generates an update pulse based on the number of samples from the controller 360, and supplies the update pulse together with the measurement data to the correction value calculation unit 320. This update pulse is a signal that indicates the update timing of the correction value.
補正値計算部320は、測定データに基づいて、カラム毎およびゲインドメイン毎にアナログゲインの誤差を補正するための補正値を求めるものである。ここで、補正値は、アナログゲインの誤差を補正するためのゲイン補正係数aの値と、オフセットの誤差を補正するためのオフセット補正係数bの値とを含む。カラム数がNであり、ゲインドメイン数がMである場合、N×M×2個の補正値が求められる。なお、オフセット補正係数は、必要に応じて演算される。
The correction value calculation unit 320 obtains a correction value for correcting an analog gain error for each column and each gain domain based on the measurement data. Here, the correction value includes a value of the gain correction coefficient a for correcting the analog gain error and a value of the offset correction coefficient b for correcting the offset error. When the number of columns is N and the number of gain domains is M, correction values of N × M × 2 are obtained. The offset correction coefficient is calculated as necessary.
補正値計算部320は、求めた補正値(ゲイン補正係数およびオフセット補正係数)を記憶部330に格納する。また、補正値計算部320には、ゲイン誤差測定部310の測定対象のゲインドメインを示す測定対象ドメイン情報が入力される。補正値計算部320は、更新パルスに同期して、測定対象ドメイン情報の示すゲインドメインの補正値を更新する。
The correction value calculation unit 320 stores the obtained correction value (gain correction coefficient and offset correction coefficient) in the storage unit 330. Further, the correction value calculation unit 320 is input with the measurement target domain information indicating the gain domain to be measured by the gain error measurement unit 310. The correction value calculation unit 320 updates the correction value of the gain domain indicated by the measurement target domain information in synchronization with the update pulse.
記憶部330は、カラム毎およびゲインドメイン毎に補正値を記憶するものである。
The storage unit 330 stores the correction value for each column and each gain domain.
補正部350は、補正値によりセレクタ340からのデジタル信号を補正するものである。この補正部350には、補正対象のゲインドメインを示す補正対象ドメイン情報がコントローラ360により入力される。n列目のデジタル信号Doutが入力され、補正対象ドメイン情報がm(mは、0乃至M-1の整数)を示す場合、補正部350は、記憶部330から、n列目のm個目のゲインドメインのゲイン補正係数aおよびオフセット補正係数bを読み出す。そして、次の式により、デジタル信号Doutを補正する。
Dout'=Dout×a+b ・・・式1
上式において、Dout'は、補正後のデジタル信号を示す。 Thecorrection unit 350 corrects the digital signal from the selector 340 according to the correction value. The correction target domain information indicating the gain domain to be corrected is input to the correction unit 350 by the controller 360. When the digital signal Dout in the nth column is input and the correction target domain information indicates m (m is an integer of 0 to M-1), the correction unit 350 starts from the storage unit 330 in the mth column in the nth column. The gain correction coefficient a and the offset correction coefficient b of the gain domain of the above are read out. Then, the digital signal Dout is corrected by the following equation.
Dout'= Dout × a + b ・ ・ ・Equation 1
In the above equation, Dout'indicates the corrected digital signal.
Dout'=Dout×a+b ・・・式1
上式において、Dout'は、補正後のデジタル信号を示す。 The
Dout'= Dout × a + b ・ ・ ・
In the above equation, Dout'indicates the corrected digital signal.
補正部350は、式1により求めたデジタル信号Dout'を配列した画像データ(フレーム)をDSP回路120に供給する。
The correction unit 350 supplies the image data (frame) in which the digital signal Dout'obtained by the equation 1 is arranged to the DSP circuit 120.
コントローラ360は、キャリブレーションに関する制御を行うものである。このコントローラ360は、まず、フレームを生成する期間である映像期間の開始前において、補正値を演算させるための起動時処理を行う。この起動時処理において、コントローラ360は、入力切替信号SWinにより入力切替部270を制御してテスト信号を入力させる。また、コントローラ360は、出力切替信号SWoutによりセレクタ340を制御してゲイン誤差測定部310へデジタル信号を出力させる。また、コントローラ360は、容量比制御信号Gctrlによりコンパレータ400を制御して、M個のゲインドメインのそれぞれに順に切り替えさせる。また、コントローラ360は、測定対象ドメイン情報により、補正値計算部320に、M個のゲインドメインのそれぞれの補正値を順に演算させる。
The controller 360 controls the calibration. First, the controller 360 performs start-up processing for calculating the correction value before the start of the video period, which is the period for generating the frame. In this start-up process, the controller 360 controls the input switching unit 270 by the input switching signal SWin to input the test signal. Further, the controller 360 controls the selector 340 by the output switching signal SWout to output a digital signal to the gain error measuring unit 310. Further, the controller 360 controls the comparator 400 by the capacitance ratio control signal Gctrl to sequentially switch to each of the M gain domains. Further, the controller 360 causes the correction value calculation unit 320 to calculate the correction values of the M gain domains in order based on the measurement target domain information.
そして、映像期間内において、コントローラ360は、入力切替信号SWinにより画素信号を入力させ、出力切替信号SWoutによりセレクタ340を制御して補正部350へデジタル信号を出力させる。また、コントローラ360は、容量比制御信号Gctrlにより、設定情報の示すアナログゲインに対応するゲインドメインに切り替えさせる。また、コントローラ360は、補正対象ドメイン情報により、設定情報の示すアナログゲインに対応するゲインドメインの補正値によってデジタル信号を補正させる。
Then, within the video period, the controller 360 inputs a pixel signal by the input switching signal SWin, controls the selector 340 by the output switching signal SWout, and outputs a digital signal to the correction unit 350. Further, the controller 360 is switched to the gain domain corresponding to the analog gain indicated by the setting information by the capacitance ratio control signal Gctrl. Further, the controller 360 corrects the digital signal by the correction value of the gain domain corresponding to the analog gain indicated by the setting information by the correction target domain information.
続いて、垂直ブランキング期間において、コントローラ360は、起動時処理で行った処理を分割して行う分割処理を実行する。分割処理において、コントローラ360は、入力切替信号SWinによりテスト信号を入力させ、出力切替信号SWoutによりゲイン誤差測定部310へデジタル信号を出力させる。また、コントローラ360は、容量比制御信号Gctrlによりコンパレータ400を制御して、M個のゲインドメインのいずれかに切り替えさせる。また、コントローラ360は、測定対象ドメイン情報により、補正値計算部320に、M個のゲインドメインのいずれかの補正値を演算させる。なお、コントローラ360は、経時劣化の少ない場合などは、この分割処理を実行しなくてもよい。
Subsequently, in the vertical blanking period, the controller 360 executes the division processing performed by dividing the processing performed in the startup processing. In the division process, the controller 360 causes the input switching signal SWin to input a test signal, and the output switching signal SWout to output a digital signal to the gain error measuring unit 310. Further, the controller 360 controls the comparator 400 by the capacitance ratio control signal Gctrl to switch to any of the M gain domains. Further, the controller 360 causes the correction value calculation unit 320 to calculate the correction value of any of the M gain domains based on the measurement target domain information. The controller 360 does not have to execute this division process when there is little deterioration over time.
起動時処理と分割処理とにおいて、コントローラ360は、設定情報の示すサンプル数をゲイン誤差測定部310に供給し、制御信号Tinによりテスト信号源220を制御して、サンプル数分のテスト信号を生成させる。
In the start-up processing and the division processing, the controller 360 supplies the number of samples indicated by the setting information to the gain error measuring unit 310, controls the test signal source 220 by the control signal Tin, and generates test signals for the number of samples. Let me.
上述したように、設定情報は、映像期間に設定するアナログゲインと、起動時処理および分割処理におけるサンプル数と、駆動モードとを含む。この駆動モードは、例えば、読み出すフレームの解像度や、読み出す範囲が異なる複数のモードのいずれかを示す。
As described above, the setting information includes the analog gain set in the video period, the number of samples in the start-up processing and the division processing, and the drive mode. This drive mode indicates, for example, one of a plurality of modes in which the resolution of the frame to be read and the reading range are different.
図10は、本技術の第1の実施の形態におけるゲイン誤差測定部310の一構成例を示すブロック図である。このゲイン誤差測定部310は、サンプル数カウンタ311、更新パルス生成部312、ゲイン演算部313およびオフセット演算部314を備える。
FIG. 10 is a block diagram showing a configuration example of the gain error measuring unit 310 according to the first embodiment of the present technology. The gain error measurement unit 310 includes a sample number counter 311, an update pulse generation unit 312, a gain calculation unit 313, and an offset calculation unit 314.
サンプル数カウンタ311は、セレクタ340から入力されるデジタル信号の個数をサンプル数として計数するものである。このサンプル数カウンタ311は、サンプル数を更新パルス生成部312に供給する。
The sample number counter 311 counts the number of digital signals input from the selector 340 as the number of samples. The sample number counter 311 supplies the number of samples to the update pulse generation unit 312.
更新パルス生成部312は、サンプル数カウンタ311により計数されたサンプル数に基づいて更新パルスを生成するものである。この更新パルス生成部312には、コントローラ360からの合計サンプル数および分割サンプル数が入力される。更新パルス生成部312には、起動時処理において、サンプル数が合計サンプル数になったときに更新パルスを生成して補正値計算部320に供給する。また、更新パルス生成部312には、分割処理において、サンプル数が分割サンプル数になるたびに更新パルスを生成して補正値計算部320に供給する。ここで、分割サンプル数は、分割処理において所定フレームに亘って取得される、ゲインドメイン毎のサンプル数の合計を意味する。
The update pulse generation unit 312 generates an update pulse based on the number of samples counted by the sample number counter 311. The total number of samples and the number of divided samples from the controller 360 are input to the update pulse generation unit 312. The update pulse generation unit 312 generates an update pulse when the total number of samples reaches the total number of samples in the start-up process, and supplies the update pulse to the correction value calculation unit 320. Further, in the division process, the update pulse generation unit 312 generates an update pulse every time the number of samples reaches the number of divided samples and supplies the update pulse to the correction value calculation unit 320. Here, the number of divided samples means the total number of samples for each gain domain acquired over a predetermined frame in the divided process.
ゲイン演算部313は、カラム毎およびゲインドメイン毎に、輝度レベルの誤差を演算するものである。このゲイン演算部313は、カラム毎およびゲインドメイン毎に、傾きgを次の式により演算する。
g=(DoutH-DoutL)/(AinH-AinL)・・・式2
上式において、AinHは、ハイレベルの入力信号であり、AinLは、ローレベルの入力信号である。DoutHは、AinHに対応するデジタル信号であり、DoutLは、AinHに対応するデジタル信号である。 Thegain calculation unit 313 calculates the brightness level error for each column and each gain domain. The gain calculation unit 313 calculates the slope g for each column and each gain domain by the following equation.
g = (Dout H -Dout L ) / (Ain H- Ain L ) ...Equation 2
In the above equation, Ain H is a high level input signal and Ain L is a low level input signal. Dout H is a digital signal corresponding to Ain H , and Dout L is a digital signal corresponding to Ain H.
g=(DoutH-DoutL)/(AinH-AinL)・・・式2
上式において、AinHは、ハイレベルの入力信号であり、AinLは、ローレベルの入力信号である。DoutHは、AinHに対応するデジタル信号であり、DoutLは、AinHに対応するデジタル信号である。 The
g = (Dout H -Dout L ) / (Ain H- Ain L ) ...
In the above equation, Ain H is a high level input signal and Ain L is a low level input signal. Dout H is a digital signal corresponding to Ain H , and Dout L is a digital signal corresponding to Ain H.
ゲイン演算部313は、ゲインドメイン毎およびカラム毎に傾きgの統計量(平均や合計など)をSTgとして演算する。第n列のm個目のゲインドメインの統計量をSTgcn_dmとする。起動時処理においては、全てのゲインドメインについて、統計量STgcn_dmが演算される。一方、分割処理においては、フレームごとに、測定対象のゲインドメインについて、統計量STgcn_dmが演算される。
The gain calculation unit 313 calculates a statistic (average, total, etc.) of the slope g for each gain domain and each column as STg. Let STg cn_dm be the statistic of the mth gain domain in the nth column. In the startup process, the statistic STg cn_dm is calculated for all gain domains. On the other hand, in the division process, the statistic STg cn_dm is calculated for each frame for the gain domain to be measured.
オフセット演算部314は、カラム毎およびゲインドメイン毎に、オフセットを演算するものである。このオフセット演算部314は、ゲインドメイン内において、カラムごとにオフセットを演算する。
The offset calculation unit 314 calculates the offset for each column and each gain domain. The offset calculation unit 314 calculates the offset for each column in the gain domain.
オフセット演算部314は、ゲインドメイン毎およびカラム毎に、オフセットの統計量(平均や合計など)をSTоとして演算する。第n列のm個目のゲインドメインの統計量STоをSTоcn_dmとする。
The offset calculation unit 314 calculates the offset statistic (average, total, etc.) as STо for each gain domain and each column. Let STо cn_dm be the statistic STо of the mth gain domain in the nth column.
ゲイン演算部313およびオフセット演算部314は、演算結果を含むデータを測定データとして補正値計算部320に供給する。なお、ゲイン誤差測定部310は、ゲインの演算に加えて、オフセットの演算を行っているが、誤差の少ない場合などは、これを行わずにゲインの演算のみを行ってもよい。
The gain calculation unit 313 and the offset calculation unit 314 supply the data including the calculation result to the correction value calculation unit 320 as measurement data. The gain error measuring unit 310 performs an offset calculation in addition to the gain calculation, but if the error is small, the gain calculation may be performed without performing this calculation.
[補正値計算部]
図11は、本技術の第1の実施の形態における補正値計算部320の一構成例を示すブロック図である。この補正値計算部320は、ゲイン補正係数演算部321および削減処理部322を備える。削減処理部322は、減算器323およびデマルチプレクサ324と、複数のクリップ処理部325と、複数の小数桁削減部326とを備える。クリップ処理部325は、ゲインドメイン毎に設けられる。また、小数桁削減部326は、ゲインドメインd0乃至dM-2について、ゲインドメイン毎に設けられる。 [Correction value calculation unit]
FIG. 11 is a block diagram showing a configuration example of the correctionvalue calculation unit 320 according to the first embodiment of the present technology. The correction value calculation unit 320 includes a gain correction coefficient calculation unit 321 and a reduction processing unit 322. The reduction processing unit 322 includes a subtractor 323 and a demultiplexer 324, a plurality of clip processing units 325, and a plurality of decimal digit reduction units 326. The clip processing unit 325 is provided for each gain domain. Further, the decimal digit reduction unit 326 is provided for each gain domain for the gain domains d0 to dM-2.
図11は、本技術の第1の実施の形態における補正値計算部320の一構成例を示すブロック図である。この補正値計算部320は、ゲイン補正係数演算部321および削減処理部322を備える。削減処理部322は、減算器323およびデマルチプレクサ324と、複数のクリップ処理部325と、複数の小数桁削減部326とを備える。クリップ処理部325は、ゲインドメイン毎に設けられる。また、小数桁削減部326は、ゲインドメインd0乃至dM-2について、ゲインドメイン毎に設けられる。 [Correction value calculation unit]
FIG. 11 is a block diagram showing a configuration example of the correction
ゲイン補正係数演算部321は、カラム毎およびゲインドメイン毎にゲイン補正係数aを演算するものである。このゲイン補正係数演算部321は、コントローラ360からの測定対象ドメイン情報がゲインドメインd0を示す際に、そのゲインドメインd0において、全てのカラムの統計量STgcn_dmの平均値を目標値AVGgd0として演算する。そして、ゲイン補正係数演算部321は、カラム毎に、AVGgd0/STgcn_dmをゲイン補正係数aとして演算する。
The gain correction coefficient calculation unit 321 calculates the gain correction coefficient a for each column and each gain domain. When the measurement target domain information from the controller 360 indicates the gain domain d0, the gain correction coefficient calculation unit 321 calculates the average value of the statistics STg cn_dm of all the columns as the target value AVGg d0 in the gain domain d0. do. Then, the gain correction coefficient calculation unit 321 calculates AVGg d0 / STg cn_dm as the gain correction coefficient a for each column.
また、測定対象ドメイン情報がゲインドメインd1以降を示す際に、ゲイン補正係数演算部321は、測定対象のそれぞれのゲインドメインについて演算を行う。ゲイン補正係数演算部321は、ゲインドメインd1以降において、アナログゲインのリニアリティが得られるように、ゲインドメインdmの全てのカラムの統計量STgcn_dmの平均値を、ゲインドメインd0の目標値AVGgd0を基準にして修正する。そして、ゲイン補正係数演算部321は、修正後の平均値をゲインドメインdmの目標値AVGgdmとして、カラム毎に、AVGgdm/STgcn_dmをゲイン補正係数aとして演算する。第n列のm個目のゲインドメインのゲイン補正係数をacn_dmとする。
Further, when the measurement target domain information indicates the gain domain d1 or later, the gain correction coefficient calculation unit 321 performs a calculation for each gain domain of the measurement target. The gain correction coefficient calculation unit 321 sets the average value of the statistic STg cn_dm of all the columns of the gain domain dm as the target value AVGg d0 of the gain domain d0 so that the linearity of the analog gain can be obtained in the gain domain d1 and later. Correct based on the standard. Then, the gain correction coefficient calculation unit 321 calculates the corrected average value as the target value AVGg dm of the gain domain dm, and AVGg dm / STg cn_dm as the gain correction coefficient a for each column. Let a cn_dm be the gain correction coefficient of the m-th gain domain in the nth column.
ゲイン補正係数演算部321は、演算したゲイン補正係数acn_dmを更新パルスに同期して減算器323に出力する。
The gain correction coefficient calculation unit 321 outputs the calculated gain correction coefficient a cn_dm to the subtractor 323 in synchronization with the update pulse.
減算器323は、ゲイン補正係数acn_dmから所定値を減算することにより、ゲイン補正係数の整数部を削減するものである。例えば、ゲイン補正係数が「1」前後の値である場合、「1」が減算される。この減算器323は、減算により得られたゲイン補正係数の小数部をデマルチプレクサ324へ供給する。
The subtractor 323 reduces the integer part of the gain correction coefficient by subtracting a predetermined value from the gain correction coefficient a cn_dm. For example, when the gain correction coefficient is a value around "1", "1" is subtracted. The subtractor 323 supplies a decimal part of the gain correction coefficient obtained by the subtraction to the demultiplexer 324.
デマルチプレクサ324は、測定対象ドメイン情報の示すゲインドメインに対応するクリップ処理部325へ、減算器323からの小数部を供給するものである。
The demultiplexer 324 supplies a decimal part from the subtractor 323 to the clip processing unit 325 corresponding to the gain domain indicated by the measurement target domain information.
クリップ処理部325は、小数部の値を所定の範囲内に制限するクリップ処理を行うものである。ゲインドメインd0乃至dM-2に係るクリップ処理部325は、クリップ処理後の小数部を、対応する小数桁削減部326に供給する。ゲインドメインdM-1に係るクリップ処理部325は、クリップ処理後の小数部を、そのまま記憶部330に出力する。
The clip processing unit 325 performs clip processing that limits the value of the decimal part within a predetermined range. The clip processing unit 325 related to the gain domains d0 to dM-2 supplies the decimal part after the clip processing to the corresponding decimal digit reduction unit 326. The clip processing unit 325 related to the gain domain dM-1 outputs the decimal part after the clip processing to the storage unit 330 as it is.
小数桁削減部326は、クリップ処理後の小数部の桁数を、アナログゲインに応じた値に削減するものである。ゲインドメイン内のアナログゲインの統計量(平均値や合計値など)が大きいほど、少ない桁数に削減される。例えば、ゲインドメインd0の統計量が最も小さく、ゲインドメインd1以降は、徐々に大きくなる場合を考える。この場合、ゲインドメインd0の削減量が最も大きく、ゲインドメインd1以降は、削減量が徐々に少なくなる。小数桁削減部326は、桁数削減後の小数部をfcn_dmとして記憶部330に保持させる。なお、全てのゲインドメインにおいて、削減処理部322は、ゲイン補正係数の整数部を削減し、ゲインドメインdM-1を除き、小数桁を削減しているが、この削減方法に限定されない。ゲイン補正係数が大きな値である場合は、全てのゲインドメインにおいて、削減処理部322がゲイン補正係数の整数桁の一部を削減することもできる。一方、ゲイン補正係数が小さい場合には、全てのゲインドメインにおいて、削減処理部322が、ゲイン補正係数の整数部と小数桁の一部とを削減することもできる。
The decimal digit reduction unit 326 reduces the number of decimal places after the clip process to a value corresponding to the analog gain. The larger the analog gain statistic (mean, total, etc.) in the gain domain, the smaller the number of digits. For example, consider the case where the statistic of the gain domain d0 is the smallest, and after the gain domain d1, it gradually increases. In this case, the reduction amount of the gain domain d0 is the largest, and the reduction amount gradually decreases after the gain domain d1. The decimal digit reduction unit 326 causes the storage unit 330 to hold the decimal part after the decimal digit reduction as fcn_dm. In all gain domains, the reduction processing unit 322 reduces the integer part of the gain correction coefficient and reduces the decimal digits except for the gain domain dM-1, but the reduction method is not limited to this. When the gain correction coefficient is a large value, the reduction processing unit 322 can also reduce a part of the integer digits of the gain correction coefficient in all gain domains. On the other hand, when the gain correction coefficient is small, the reduction processing unit 322 can reduce the integer part and a part of the decimal digits of the gain correction coefficient in all the gain domains.
また、補正値計算部320は、必要に応じてオフセット補正係数をさらに演算し、記憶部330に保持させる。なお、同図において、オフセット補正係数を演算する回路は省略されている。
Further, the correction value calculation unit 320 further calculates the offset correction coefficient as necessary, and causes the storage unit 330 to hold the offset correction coefficient. In the figure, the circuit for calculating the offset correction coefficient is omitted.
図12は、本技術の第1の実施の形態におけるクリップ処理部325の入力値および出力値の関係の一例を示すグラフである。同図における横軸は、クリップ処理部325の入力値を示し、縦軸は、クリップ処理部325の出力値を示す。
FIG. 12 is a graph showing an example of the relationship between the input value and the output value of the clip processing unit 325 according to the first embodiment of the present technology. In the figure, the horizontal axis represents the input value of the clip processing unit 325, and the vertical axis represents the output value of the clip processing unit 325.
同図に例示するように、クリップ処理部325は、入力値が所定の上限値MAXを超える場合に、その入力値の代わりに上限値MAXを出力値として出力する。また、クリップ処理部325は、入力値が所定の下限値MINを下回る場合に、その入力値の代わりに下限値MINを出力値として出力する。入力値が下限値MIN以上、上限値MAX以下の場合、入力値がそのまま出力値として出力される。このクリップ処理により、小数部の値は、下限値MINから上限値MAXまでの範囲内に制限される。
As illustrated in the figure, when the input value exceeds a predetermined upper limit value MAX, the clip processing unit 325 outputs the upper limit value MAX as an output value instead of the input value. Further, when the input value is less than the predetermined lower limit value MIN, the clip processing unit 325 outputs the lower limit value MIN as an output value instead of the input value. When the input value is equal to or greater than the lower limit value MIN and equal to or less than the upper limit value MAX, the input value is output as it is as an output value. By this clipping process, the value of the decimal part is limited to the range from the lower limit value MIN to the upper limit value MAX.
[記憶部の構成例]
図13は、本技術の第1の実施の形態における記憶部330の一構成例を示すブロック図である。この記憶部330には、複数のメモリ331が所定のX方向に配列される。メモリ331は、ゲインドメインごとに設けられる。m個目のゲインドメインに対応するメモリ331を以下、「メモリ#m」とする。メモリ331として、例えば、SRAM(Static Random Access Memory)が用いられる。 [Example of storage unit configuration]
FIG. 13 is a block diagram showing a configuration example of thestorage unit 330 according to the first embodiment of the present technology. A plurality of memories 331 are arranged in the storage unit 330 in a predetermined X direction. The memory 331 is provided for each gain domain. The memory 331 corresponding to the mth gain domain is hereinafter referred to as “memory # m”. As the memory 331, for example, SRAM (Static Random Access Memory) is used.
図13は、本技術の第1の実施の形態における記憶部330の一構成例を示すブロック図である。この記憶部330には、複数のメモリ331が所定のX方向に配列される。メモリ331は、ゲインドメインごとに設けられる。m個目のゲインドメインに対応するメモリ331を以下、「メモリ#m」とする。メモリ331として、例えば、SRAM(Static Random Access Memory)が用いられる。 [Example of storage unit configuration]
FIG. 13 is a block diagram showing a configuration example of the
メモリ#mには、m個目のゲインドメインのゲイン補正係数の小数部fcn_dmが保持される。前述したように、それぞれのゲインドメインにおいて、カラム毎にゲイン補正係数が演算されるため、メモリ#mのそれぞれには、カラム数をNとすると、N個の小数部fcn_dmが保持される。これらの小数部fcn_dmは、X方向に垂直なY方向に配列される。
The memory #m holds a decimal part f cn_dm of the gain correction coefficient of the mth gain domain. As described above, since the gain correction coefficient is calculated for each column in each gain domain, N fractional parts f cn_dm are held in each of the memory # m, where N is the number of columns. These decimal parts f cn_dm are arranged in the Y direction perpendicular to the X direction.
また、M個のメモリ331のそれぞれのX方向の物理的なサイズは、保持する小数部fcn_dmの桁数に応じた値に設定される。前述したように小数部fcn_dmの桁数は、ゲインドメインに応じて削減されているため、M個のメモリ331のそれぞれのX方向のサイズは、異なるものとなる。m個目のメモリ331のX方向のサイズを以下、Xmとする。小数部fcn_dmの2進数表記の桁数をWmとすると、サイズXmは、Wmに比例する値となる。一方、M個のメモリ331のそれぞれのY方向の物理的なサイズYは略同一であり、列数であるNに比例する値である。ここで、略同一は、サイズが完全一致する場合、または、サイズ間の差が所定値以内である場合を意味する。なお、全てのゲインドメインにおいて、削減処理部322がゲイン補正係数の整数桁の一部を削減する場合、最大で、残りの整数桁と小数部とがメモリ331に保持される。一方、全てのゲインドメインにおいて、削減処理部322が、ゲイン補正係数の整数部と小数桁の一部とを削減する場合、最大で、残りの小数桁がメモリ331に保持される。
Further, the physical size of each of the M memories 331 in the X direction is set to a value corresponding to the number of digits of the decimal part f cn_dm to be held. As described above, since the number of digits in the fractional part f cn_dm is reduced according to the gain domain, the sizes of the M memories 331 in the X direction are different. The size of the mth memory 331 in the X direction is hereinafter referred to as X m . Assuming that the number of digits in the binary notation of the fractional part f cn_dm is W m , the size X m is a value proportional to W m. On the other hand, the physical size Y of each of the M memories 331 in the Y direction is substantially the same, and is a value proportional to N, which is the number of columns. Here, substantially the same means a case where the sizes are exactly the same, or a case where the difference between the sizes is within a predetermined value. In all gain domains, when the reduction processing unit 322 reduces a part of the integer digits of the gain correction coefficient, the remaining integer digits and the decimal part are held in the memory 331 at the maximum. On the other hand, in all gain domains, when the reduction processing unit 322 reduces the integer part and a part of the decimal digits of the gain correction coefficient, the remaining decimal digits are held in the memory 331 at the maximum.
また、メモリ#0乃至メモリ#M-1は、最もサイズの小さいメモリ#0を起点とすると、X方向において昇順に配列される。逆にメモリ#M-1を起点と考えると、降順に配列される。
Further, the memory # 0 to the memory # M-1 are arranged in ascending order in the X direction, starting from the memory # 0 having the smallest size. Conversely, if memory # M-1 is considered as the starting point, they are arranged in descending order.
なお、記憶部330には、必要に応じてオフセット補正係数がさらに保持される。オフセット補正係数を保持するメモリは同図において省略されている。
The storage unit 330 further holds an offset correction coefficient as needed. The memory that holds the offset correction coefficient is omitted in the figure.
また、メモリの配列方法は、昇順に限定されない。例えば、図14に例示するように、それぞれのX方向の合計サイズが略同一となる複数対のメモリ#mを所定の順序で配列することもできる。
Also, the memory arrangement method is not limited to ascending order. For example, as illustrated in FIG. 14, a plurality of pairs of memories # m having substantially the same total size in each X direction can be arranged in a predetermined order.
図15は、本技術の第1の実施の形態における補正値計算部320の処理の一例を示す図である。同図におけるaは、ゲインドメインd0のゲイン補正係数に対する処理の一例を示す図である。同図におけるbは、ゲインドメインd0乃至d6の削減後のゲイン補正係数の一例である。
FIG. 15 is a diagram showing an example of processing of the correction value calculation unit 320 in the first embodiment of the present technology. In the figure, a is a diagram showing an example of processing for the gain correction coefficient of the gain domain d0. Reference numeral b in the figure is an example of the gain correction coefficient after the reduction of the gain domains d0 to d6.
同図におけるaに例示するように、ゲインドメインd0において、2進数表記で「1.000000101101」の値がゲイン補正係数acn_d0として演算されたものとする。補正値計算部320は、そのゲイン補正係数acn_d0から「1」を減算して「0.000000101101」とする。また、減算後の符号を示す符号ビットSが生成される。
As illustrated in a in the figure, it is assumed that the value of "1.0000000101101" in binary notation is calculated as the gain correction coefficient a cn_d0 in the gain domain d0. The correction value calculation unit 320 subtracts “1” from the gain correction coefficient a cn_d0 to obtain “0.0000000101101”. Further, a sign bit S indicating a sign after subtraction is generated.
そして、補正値計算部320は、クリップ処理を行い、小数桁の第1桁から第6桁を削減し、「101101」とする。
Then, the correction value calculation unit 320 performs a clip process to reduce the first to sixth decimal places to "101101".
アナログゲインが小さいほど、AD変換後のデジタル信号の誤差は比較的小さくなり、その誤差を補正するためのゲイン補正係数の絶対値も小さな値となる。したがって、補正値計算部320は、アナログゲインが小さいほど、大きな桁数を削減し、小数部のダイナミックレンジを小さくすることができる。アナログゲインに応じてゲイン補正係数の桁数を削減(言い換えれば、ダイナミックレンジを小さく)してメモリ331に保持させることにより、必要なメモリ331のサイズを削減することができる。
The smaller the analog gain, the smaller the error of the digital signal after AD conversion, and the smaller the absolute value of the gain correction coefficient for correcting the error. Therefore, the correction value calculation unit 320 can reduce the large number of digits and reduce the dynamic range of the decimal part as the analog gain becomes smaller. By reducing the number of digits of the gain correction coefficient (in other words, reducing the dynamic range) according to the analog gain and holding the memory 331, the required size of the memory 331 can be reduced.
同図におけるbに例示するように、例えば、ゲインドメインの個数を7個とし、削減前の小数桁を12桁とし、m個目のゲインドメインにおいて削減する桁を、(6-m)桁までとする。この場合、サイズが最小の0個目のメモリ#0には、符号ビットSも含めて、カラム毎に7ビットのデータが保持される。メモリ#1には、符号ビットSも含めて、カラム毎に8ビットのデータが保持される。以下、1ビットずつデータサイズが大きくなり、サイズが最大のメモリ#6には、符号ビットSも含めて、カラム毎に13ビットのデータが保持される。これらのメモリ#0乃至#6に保持されるビット数の合計は、等差数列の和の公式を用いて下記の式により求められる。
(7/2)×(7+13)×N=70×N ・・・式3 As illustrated in b in the figure, for example, the number of gain domains is 7, the decimal digit before reduction is 12 digits, and the digit to be reduced in the mth gain domain is up to (6-m) digits. And. In this case, the0th memory # 0, which has the smallest size, holds 7 bits of data for each column, including the code bit S. Memory # 1 holds 8 bits of data for each column, including the code bit S. Hereinafter, the data size is increased by one bit, and the memory # 6, which has the largest size, holds 13 bits of data for each column, including the code bit S. The total number of bits held in these memories # 0 to # 6 is calculated by the following formula using the formula of the sum of arithmetic progressions.
(7/2) × (7 + 13) × N = 70 × N ・ ・ ・Equation 3
(7/2)×(7+13)×N=70×N ・・・式3 As illustrated in b in the figure, for example, the number of gain domains is 7, the decimal digit before reduction is 12 digits, and the digit to be reduced in the mth gain domain is up to (6-m) digits. And. In this case, the
(7/2) × (7 + 13) × N = 70 × N ・ ・ ・
一方、桁数を削減せずに保持する比較例を想定する。この比較例では、全てのメモリ#mのそれぞれには、符号ビットSも含めて、カラム毎に13ビットのデータが保持される。この場合、メモリ#0乃至#6に保持されるビット数の合計は、下記の式により求められる。
13×7×N=91×N ・・・式4 On the other hand, assume a comparative example in which the number of digits is retained without being reduced. In this comparative example, 13 bits of data are held for each column, including the code bit S, in each of all the memories #m. In this case, the total number of bits held in thememories # 0 to # 6 is calculated by the following formula.
13 × 7 × N = 91 × N ・ ・ ・Equation 4
13×7×N=91×N ・・・式4 On the other hand, assume a comparative example in which the number of digits is retained without being reduced. In this comparative example, 13 bits of data are held for each column, including the code bit S, in each of all the memories #m. In this case, the total number of bits held in the
13 × 7 × N = 91 × N ・ ・ ・
式3および式4に例示するように、アナログゲインに応じたサイズのメモリ331を用いることにより、比較例よりもメモリの容量を削減することができる。メモリの物理的なサイズは容量に比例するため、容量の削減により、サイズを削減することができる。
As illustrated in Equations 3 and 4, by using the memory 331 of the size corresponding to the analog gain, the memory capacity can be reduced as compared with the comparative example. Since the physical size of the memory is proportional to the capacity, the size can be reduced by reducing the capacity.
[補正部の構成例]
図16は、本技術の第1の実施の形態における補正部350の一構成例を示すブロック図である。この補正部350は、複数の桁数拡張部351と、マルチプレクサ352と、加算器353と、乗算器354とを備える。桁数拡張部351は、小数桁が削減されないゲインドメインdM-1以外の全てのゲインドメインについて設けられる。 [Structure example of correction unit]
FIG. 16 is a block diagram showing a configuration example of thecorrection unit 350 according to the first embodiment of the present technology. The correction unit 350 includes a plurality of digit number expansion units 351, a multiplexer 352, an adder 353, and a multiplier 354. The digit number expansion unit 351 is provided for all gain domains other than the gain domain dM-1 in which decimal digits are not reduced.
図16は、本技術の第1の実施の形態における補正部350の一構成例を示すブロック図である。この補正部350は、複数の桁数拡張部351と、マルチプレクサ352と、加算器353と、乗算器354とを備える。桁数拡張部351は、小数桁が削減されないゲインドメインdM-1以外の全てのゲインドメインについて設けられる。 [Structure example of correction unit]
FIG. 16 is a block diagram showing a configuration example of the
桁数拡張部351は、対応するゲインドメインのゲイン補正係数の小数部fcn_dmの桁数をゼロパディングなどにより所定値に拡張するものである。この桁数拡張部351は、拡張後の小数部をマルチプレクサ352に供給する。なお、全てのゲインドメインにおいて、削減処理部322がゲイン補正係数の整数桁の一部を削減する場合、桁数拡張部351は、その一部の整数桁と小数桁とを拡張対象とする。一方、全てのゲインドメインにおいて、削減処理部322が、ゲイン補正係数の整数部と小数桁の一部とを削減する場合、桁数拡張部351は、その一部の小数桁を拡張対象とする。
The digit number expansion unit 351 expands the number of digits of the fractional part fcn_dm of the gain correction coefficient of the corresponding gain domain to a predetermined value by zero padding or the like. The digit number expansion unit 351 supplies the expanded decimal part to the multiplexer 352. In all gain domains, when the reduction processing unit 322 reduces a part of the integer digits of the gain correction coefficient, the digit number expansion unit 351 expands the part of the integer digits and the decimal digits. On the other hand, in all gain domains, when the reduction processing unit 322 reduces the integer part and a part of the decimal digits of the gain correction coefficient, the digit number expansion unit 351 expands the part of the decimal digits. ..
マルチプレクサ352には、ゲインドメインdM-1の小数部と、桁数拡張部351のそれぞれからの小数部とが入力される。マルチプレクサ352には、コントローラ360からの補正対象ドメイン情報の示すゲインドメインに対応する小数部を選択し、加算器353に供給する。
The decimal part of the gain domain dM-1 and the fractional part from each of the digit expansion units 351 are input to the multiplexer 352. For the multiplexer 352, a fractional part corresponding to the gain domain indicated by the correction target domain information from the controller 360 is selected and supplied to the adder 353.
加算器353は、マルチプレクサ352からの小数部に、削減した整数部(「1」など)を加算するものである。加算器353は、加算結果を乗算器354に供給する。
The adder 353 adds a reduced integer part (such as "1") to the decimal part from the multiplexer 352. The adder 353 supplies the addition result to the multiplier 354.
乗算器354は、加算器353の加算結果と、セレクタ340からのフレーム内のデジタル信号とを乗算するものである。この乗算により、整数部の削減前のゲイン補正係数によりデジタル信号を補正した結果が得られる。乗算器354は、演算結果を補正後のデジタル信号としてDSP回路120に出力する。
The multiplier 354 multiplies the addition result of the adder 353 with the digital signal in the frame from the selector 340. By this multiplication, the result of correcting the digital signal by the gain correction coefficient before the reduction of the integer part is obtained. The multiplier 354 outputs the calculation result to the DSP circuit 120 as a corrected digital signal.
なお、補正部350は、必要に応じてオフセット係数を用いた補正を行う。同図において、オフセット係数による補正を行う回路は省略されている。また、補正部350は、さらにディザ処理を行うこともできる。
The correction unit 350 makes corrections using an offset coefficient as necessary. In the figure, the circuit that corrects by the offset coefficient is omitted. Further, the correction unit 350 can further perform dither processing.
図17は、本技術の第1の実施の形態におけるアナログゲインの誤差の補正方法を説明するための図である。画素260は、画素信号SIGを生成し、テスト信号源220は、所定レベル(ハイレベルまたはローレベル)のテスト信号Toutを生成する。
FIG. 17 is a diagram for explaining a method of correcting an analog gain error in the first embodiment of the present technology. Pixel 260 produces a pixel signal SIG, and test signal source 220 produces a predetermined level (high level or low level) test signal Tout.
入力切替部270内のセレクタ271は、入力切替信号SWinに従って、テスト信号Toutと対応する列の画素信号SIGとのいずれかを選択し、入力信号Ainとして、対応する列のADC281に供給する。
The selector 271 in the input switching unit 270 selects either the test signal Tout or the pixel signal SIG of the corresponding column according to the input switching signal SWin, and supplies the input signal Ain to the ADC 281 of the corresponding column.
ADC281は、複数のアナログゲインのうち、容量比制御信号Gctrlにより選択されたアナログゲインによって、アナログの入力信号Ainを増減し、増減した入力信号Ainをデジタル信号Doutに変換する。
The ADC 281 increases or decreases the analog input signal Ain according to the analog gain selected by the capacitance ratio control signal Gctrl among the plurality of analog gains, and converts the increased or decreased input signal Ain into a digital signal Dout.
セレクタ340は、出力切替信号SWoutに従ってゲイン誤差測定部310および補正部350のいずれかを出力先として選択し、デジタル信号Doutを出力する。
The selector 340 selects either the gain error measuring unit 310 or the correction unit 350 as the output destination according to the output switching signal SWout, and outputs the digital signal Dout.
ゲイン誤差測定部310は、アナログゲインやオフセットの誤差を補正するために、カラム毎およびゲインドメイン毎にアナログゲインおよびオフセットを測定し、測定データとして補正値計算部320に供給する。
The gain error measuring unit 310 measures the analog gain and offset for each column and each gain domain in order to correct the error of the analog gain and the offset, and supplies the measurement data to the correction value calculation unit 320.
補正値計算部320内のゲイン補正係数演算部321は、テスト信号Tout(入力)とデジタル信号Dout(出力)とに基づいて、カラム毎およびゲインドメイン毎に、アナログゲインの誤差を補正するためのゲイン補正係数を演算する。
The gain correction coefficient calculation unit 321 in the correction value calculation unit 320 is for correcting the analog gain error for each column and each gain domain based on the test signal Tout (input) and the digital signal Dout (output). Calculate the gain correction coefficient.
そして、削減処理部322は、ゲイン補正係数の桁数を、対応するアナログゲインに応じた値に削減し、複数のメモリ331のうち削減後の桁数に応じたサイズのメモリに保持させる。
Then, the reduction processing unit 322 reduces the number of digits of the gain correction coefficient to a value corresponding to the corresponding analog gain, and holds the memory in a memory having a size corresponding to the number of digits after the reduction among the plurality of memories 331.
そして、補正部350は、出力された補正値(ゲイン補正係数など)によりデジタル信号Doutを補正する。この補正により、カラムごとのアナログゲインのばらつきに起因する縦筋状の固定パターンノイズを除去することができる。
Then, the correction unit 350 corrects the digital signal Dout with the output correction value (gain correction coefficient, etc.). By this correction, it is possible to remove the vertical streak-shaped fixed pattern noise caused by the variation of the analog gain for each column.
[固体撮像素子の動作例]
図18は、本技術の第1の実施の形態における固体撮像素子200の動作の一例を示すフローチャートである。この固体撮像素子200の動作は、例えば、画像データを撮像するための所定のアプリケーションが実行されたときに開始される。 [Operation example of solid-state image sensor]
FIG. 18 is a flowchart showing an example of the operation of the solid-state image sensor 200 according to the first embodiment of the present technology. The operation of the solid-state image sensor 200 is started, for example, when a predetermined application for capturing image data is executed.
図18は、本技術の第1の実施の形態における固体撮像素子200の動作の一例を示すフローチャートである。この固体撮像素子200の動作は、例えば、画像データを撮像するための所定のアプリケーションが実行されたときに開始される。 [Operation example of solid-state image sensor]
FIG. 18 is a flowchart showing an example of the operation of the solid-
固体撮像素子200内のカラム信号処理部280は、ゲインドメインの全てについて、テスト信号をAD変換する(ステップS901)。ゲイン誤差測定部310は、カラム毎およびゲインドメイン毎にゲイン誤差を測定する(ステップS902)。そして、補正値計算部320は、カラム毎およびゲインドメイン毎に補正値を演算し、記憶部330に保持させる(ステップS903)。
The column signal processing unit 280 in the solid-state image sensor 200 AD-converts the test signal for all of the gain domains (step S901). The gain error measuring unit 310 measures the gain error for each column and each gain domain (step S902). Then, the correction value calculation unit 320 calculates the correction value for each column and each gain domain, and causes the storage unit 330 to hold the correction value (step S903).
そして、映像期間内にカラム信号処理部280は、全画素の画素信号をAD変換してフレームを生成する(ステップS904)。補正部350は、そのフレーム内のデジタル信号を補正値により補正する(ステップS905)。
Then, within the video period, the column signal processing unit 280 AD-converts the pixel signals of all the pixels to generate a frame (step S904). The correction unit 350 corrects the digital signal in the frame according to the correction value (step S905).
続いて、垂直ブランキング期間内にカラム信号処理部280は、測定対象のゲインドメインについて、テスト信号をAD変換する(ステップS906)。ゲイン誤差測定部310は、そのゲインドメインについてカラム毎にゲイン誤差を測定する(ステップS907)。
Subsequently, within the vertical blanking period, the column signal processing unit 280 AD-converts the test signal for the gain domain to be measured (step S906). The gain error measuring unit 310 measures the gain error for each column for the gain domain (step S907).
補正値計算部320は、更新パルスが生成されたか否かを判断する(ステップS908)。更新パルスが生成されていない場合に(ステップS908:No)、固体撮像素子200は、ステップS904以降を繰り返す。
The correction value calculation unit 320 determines whether or not an update pulse has been generated (step S908). When the update pulse is not generated (step S908: No), the solid-state image sensor 200 repeats steps S904 and subsequent steps.
一方、更新パルスが生成された場合に(ステップS908:Yes)、補正値計算部320は、補正対象のゲインドメインについてカラム毎に補正値を演算し、演算結果により更新を行う(ステップS909)。ステップS909の後に固体撮像素子200は、ステップS904以降を繰り返し実行する。
On the other hand, when an update pulse is generated (step S908: Yes), the correction value calculation unit 320 calculates a correction value for each column for the gain domain to be corrected, and updates based on the calculation result (step S909). After step S909, the solid-state image sensor 200 repeatedly executes step S904 and subsequent steps.
なお、固体撮像素子200は、経時劣化の少ない場合などにおいて、分割処理を実行しなくてもよい。分割処理を実行しない場合、図19に例示するように、ステップS906乃至S909が実行されず、ステップS905の後に、ステップS904以降が繰り返し実行される。
Note that the solid-state image sensor 200 does not have to perform the division process when there is little deterioration over time. When the division process is not executed, as illustrated in FIG. 19, steps S906 to S909 are not executed, and after step S905, steps S904 and subsequent steps are repeatedly executed.
このように、本技術の第1の実施の形態によれば、削減処理部322が、ゲイン補正係数の桁数をアナログゲインに応じて削減するため、桁数を変えない場合と比較して、必要なメモリの容量を削減することができる。
As described above, according to the first embodiment of the present technology, the reduction processing unit 322 reduces the number of digits of the gain correction coefficient according to the analog gain, so that the number of digits is not changed as compared with the case where the number of digits is not changed. The required memory capacity can be reduced.
<2.第2の実施の形態>
上述の第1の実施の形態では、記憶部330内においてX方向に複数のメモリ331を配列していたが、この配列では、メモリ331の個数の増大に応じて、記憶部330のX方向のサイズが長くなるおそれがある。この第2の実施の形態の記憶部330は、メモリ331の配列を変えて、X方向のサイズを削減した点において第1の実施の形態と異なる。 <2. Second Embodiment>
In the first embodiment described above, a plurality ofmemories 331 are arranged in the X direction in the storage unit 330, but in this arrangement, the storage unit 330 is arranged in the X direction as the number of the memories 331 increases. May increase size. The storage unit 330 of the second embodiment is different from the first embodiment in that the arrangement of the memory 331 is changed to reduce the size in the X direction.
上述の第1の実施の形態では、記憶部330内においてX方向に複数のメモリ331を配列していたが、この配列では、メモリ331の個数の増大に応じて、記憶部330のX方向のサイズが長くなるおそれがある。この第2の実施の形態の記憶部330は、メモリ331の配列を変えて、X方向のサイズを削減した点において第1の実施の形態と異なる。 <2. Second Embodiment>
In the first embodiment described above, a plurality of
図20は、本技術の第2の実施の形態における記憶部330の一構成例を示すブロック図である。この第2の実施の形態の記憶部330において、M個のメモリ331は、2つのグループにグループ化される。2つのグループの一方の個数をK(Kは、M-1未満の整数)個とする。その一方のグループには、メモリ#0乃至#K-1がX方向に配列される。また、他方のグループには、残りのメモリ#K乃至#M-1がX方向に配列される。
FIG. 20 is a block diagram showing a configuration example of the storage unit 330 according to the second embodiment of the present technology. In the storage unit 330 of the second embodiment, the M memories 331 are grouped into two groups. Let the number of one of the two groups be K (K is an integer less than M-1). In one of the groups, memories # 0 to # K-1 are arranged in the X direction. In the other group, the remaining memories # K to # M-1 are arranged in the X direction.
メモリ#0乃至#K-1のそれぞれのY方向のサイズは、略同一であり、そのサイズをY1とする。また、メモリ#0乃至#K-1のそれぞれのX方向のサイズは異なり、アナログゲインに応じた値となる。
Each Y-direction size of the memory # 0 to # K-1 is substantially identical to the size and Y 1. Further, the sizes of the memories # 0 to # K-1 in the X direction are different, and the values correspond to the analog gain.
メモリ#K乃至#M-1のそれぞれのY方向のサイズは、略同一であり、そのサイズをY2とする。このY2は、Y1より大きな値に設定される。メモリ#Kでは、Y方向のサイズを大きくした分、そのX方向のサイズXKは、メモリ#K-1のXK-1よりも小さな値となる。例えば、メモリ#Kの小数部の2進数表記の桁数をWKとすると、そのX方向のサイズXKは、WK×(Y1/Y2)に比例した値に設定される。また、メモリ#K乃至#M-1のそれぞれのX方向のサイズは異なり、アナログゲインに応じた値となる。
The sizes of the memories # K to # M-1 in the Y direction are substantially the same, and the size is defined as Y 2 . This Y 2 is set to a value larger than Y 1. In the memory # K, the size X K in the X direction is smaller than the X K-1 of the memory # K-1 by the amount that the size in the Y direction is increased. For example, if the number of digits of the binary representation of the decimal part of the memory #K and W K, the size X K in the X direction is set to a value proportional to W K × (Y 1 / Y 2). Further, the sizes of the memories # K to # M-1 in the X direction are different, and the values correspond to the analog gain.
同図に例示するように、M個のメモリ331をY方向のサイズの異なる2つのグループに分け、各グループにおいてX方向にメモリ331を配列したため、記憶部330のX方向のサイズを削減することができる。
As illustrated in the figure, since the M memories 331 are divided into two groups having different sizes in the Y direction and the memories 331 are arranged in the X direction in each group, the size of the storage unit 330 in the X direction can be reduced. Can be done.
このように、本技術の第2の実施の形態では、M個のメモリ331をY方向のサイズの異なる2つのグループに分け、それぞれのグループにおいてメモリ331をX方向に配列したため、記憶部330のX方向のサイズを削減することができる。
As described above, in the second embodiment of the present technology, the M memories 331 are divided into two groups having different sizes in the Y direction, and the memories 331 are arranged in the X direction in each group. The size in the X direction can be reduced.
[変形例]
上述の第2の実施の形態では、M個のメモリ331をY方向のサイズの異なる2つのグループに分け、それぞれのグループにおいてメモリ331をX方向に配列していた。しかし、この配列では、メモリ331のX方向のサイズが異なるものとなる。この第2の実施の形態の変形例の記憶部330は、メモリ331の配列を変えて、X方向のサイズを揃えた第1の実施の形態と異なる。 [Modification example]
In the second embodiment described above, theM memories 331 are divided into two groups having different sizes in the Y direction, and the memories 331 are arranged in the X direction in each group. However, in this array, the size of the memory 331 in the X direction is different. The storage unit 330 of the modified example of this second embodiment is different from the first embodiment in which the arrangement of the memory 331 is changed and the sizes in the X direction are aligned.
上述の第2の実施の形態では、M個のメモリ331をY方向のサイズの異なる2つのグループに分け、それぞれのグループにおいてメモリ331をX方向に配列していた。しかし、この配列では、メモリ331のX方向のサイズが異なるものとなる。この第2の実施の形態の変形例の記憶部330は、メモリ331の配列を変えて、X方向のサイズを揃えた第1の実施の形態と異なる。 [Modification example]
In the second embodiment described above, the
図21は、本技術の第2の実施の形態における記憶部330の一構成例を示すブロック図である。この第2の実施の形態の変形例の記憶部330において、メモリ331のそれぞれのX方向のサイズは略同一であり、Y方向のサイズがアナログゲインに応じた値である。そして、複数対のメモリ331が所定の順序でX方向に配列される。それぞれの組において一対のメモリは、Y方向に配列され、それぞれの組のY方向の合計サイズは、略同一である。
FIG. 21 is a block diagram showing a configuration example of the storage unit 330 according to the second embodiment of the present technology. In the storage unit 330 of the modified example of the second embodiment, the sizes of the memories 331 in the X direction are substantially the same, and the size in the Y direction is a value corresponding to the analog gain. Then, a plurality of pairs of memories 331 are arranged in the X direction in a predetermined order. In each set, the pair of memories are arranged in the Y direction, and the total size of each set in the Y direction is substantially the same.
同図に例示したように、Y方向の合計サイズが略同一となる複数対のメモリ331をX方向に配列することにより、それぞれのメモリ331のX方向のサイズを略同一に揃えることができる。
As illustrated in the figure, by arranging a plurality of pairs of memories 331 having substantially the same total size in the Y direction in the X direction, the sizes of the respective memories 331 in the X direction can be made substantially the same.
このように、本技術の第2の実施の形態の変形例では、Y方向の合計サイズが略同一となる複数対のメモリ331をX方向に配列したため、それぞれのメモリ331のX方向のサイズを略同一に揃えることができる。
As described above, in the modified example of the second embodiment of the present technology, since a plurality of pairs of memories 331 having substantially the same total size in the Y direction are arranged in the X direction, the size of each memory 331 in the X direction is set. It can be arranged almost the same.
<3.移動体への応用例>
本開示に係る技術(本技術)は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。 <3. Application example to mobile>
The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure is realized as a device mounted on a moving body of any kind such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. You may.
本開示に係る技術(本技術)は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。 <3. Application example to mobile>
The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure is realized as a device mounted on a moving body of any kind such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. You may.
図22は、本開示に係る技術が適用され得る移動体制御システムの一例である車両制御システムの概略的な構成例を示すブロック図である。
FIG. 22 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technique according to the present disclosure can be applied.
車両制御システム12000は、通信ネットワーク12001を介して接続された複数の電子制御ユニットを備える。図22に示した例では、車両制御システム12000は、駆動系制御ユニット12010、ボディ系制御ユニット12020、車外情報検出ユニット12030、車内情報検出ユニット12040、及び統合制御ユニット12050を備える。また、統合制御ユニット12050の機能構成として、マイクロコンピュータ12051、音声画像出力部12052、及び車載ネットワークI/F(interface)12053が図示されている。
The vehicle control system 12000 includes a plurality of electronic control units connected via the communication network 12001. In the example shown in FIG. 22, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.
駆動系制御ユニット12010は、各種プログラムにしたがって車両の駆動系に関連する装置の動作を制御する。例えば、駆動系制御ユニット12010は、内燃機関又は駆動用モータ等の車両の駆動力を発生させるための駆動力発生装置、駆動力を車輪に伝達するための駆動力伝達機構、車両の舵角を調節するステアリング機構、及び、車両の制動力を発生させる制動装置等の制御装置として機能する。
The drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 provides a driving force generator for generating the driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism for adjusting and a braking device for generating a braking force of a vehicle.
ボディ系制御ユニット12020は、各種プログラムにしたがって車体に装備された各種装置の動作を制御する。例えば、ボディ系制御ユニット12020は、キーレスエントリシステム、スマートキーシステム、パワーウィンドウ装置、あるいは、ヘッドランプ、バックランプ、ブレーキランプ、ウィンカー又はフォグランプ等の各種ランプの制御装置として機能する。この場合、ボディ系制御ユニット12020には、鍵を代替する携帯機から発信される電波又は各種スイッチの信号が入力され得る。ボディ系制御ユニット12020は、これらの電波又は信号の入力を受け付け、車両のドアロック装置、パワーウィンドウ装置、ランプ等を制御する。
The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, blinkers or fog lamps. In this case, the body system control unit 12020 may be input with radio waves transmitted from a portable device that substitutes for the key or signals of various switches. The body system control unit 12020 receives inputs of these radio waves or signals and controls a vehicle door lock device, a power window device, a lamp, and the like.
車外情報検出ユニット12030は、車両制御システム12000を搭載した車両の外部の情報を検出する。例えば、車外情報検出ユニット12030には、撮像部12031が接続される。車外情報検出ユニット12030は、撮像部12031に車外の画像を撮像させるとともに、撮像された画像を受信する。車外情報検出ユニット12030は、受信した画像に基づいて、人、車、障害物、標識又は路面上の文字等の物体検出処理又は距離検出処理を行ってもよい。
The vehicle outside information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image pickup unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle outside information detection unit 12030 causes the image pickup unit 12031 to capture an image of the outside of the vehicle and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as a person, a vehicle, an obstacle, a sign, or a character on the road surface based on the received image.
撮像部12031は、光を受光し、その光の受光量に応じた電気信号を出力する光センサである。撮像部12031は、電気信号を画像として出力することもできるし、測距の情報として出力することもできる。また、撮像部12031が受光する光は、可視光であっても良いし、赤外線等の非可視光であっても良い。
The imaging unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of the light received. The image pickup unit 12031 can output an electric signal as an image or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.
車内情報検出ユニット12040は、車内の情報を検出する。車内情報検出ユニット12040には、例えば、運転者の状態を検出する運転者状態検出部12041が接続される。運転者状態検出部12041は、例えば運転者を撮像するカメラを含み、車内情報検出ユニット12040は、運転者状態検出部12041から入力される検出情報に基づいて、運転者の疲労度合い又は集中度合いを算出してもよいし、運転者が居眠りをしていないかを判別してもよい。
The in-vehicle information detection unit 12040 detects the in-vehicle information. For example, a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether or not the driver has fallen asleep.
マイクロコンピュータ12051は、車外情報検出ユニット12030又は車内情報検出ユニット12040で取得される車内外の情報に基づいて、駆動力発生装置、ステアリング機構又は制動装置の制御目標値を演算し、駆動系制御ユニット12010に対して制御指令を出力することができる。例えば、マイクロコンピュータ12051は、車両の衝突回避あるいは衝撃緩和、車間距離に基づく追従走行、車速維持走行、車両の衝突警告、又は車両のレーン逸脱警告等を含むADAS(Advanced Driver Assistance System)の機能実現を目的とした協調制御を行うことができる。
The microcomputer 12051 calculates the control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit. A control command can be output to 12010. For example, the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, and the like. It is possible to perform cooperative control for the purpose of.
また、マイクロコンピュータ12051は、車外情報検出ユニット12030又は車内情報検出ユニット12040で取得される車両の周囲の情報に基づいて駆動力発生装置、ステアリング機構又は制動装置等を制御することにより、運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。
Further, the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform coordinated control for the purpose of automatic driving, etc., which runs autonomously without depending on the operation.
また、マイクロコンピュータ12051は、車外情報検出ユニット12030で取得される車外の情報に基づいて、ボディ系制御ユニット12020に対して制御指令を出力することができる。例えば、マイクロコンピュータ12051は、車外情報検出ユニット12030で検知した先行車又は対向車の位置に応じてヘッドランプを制御し、ハイビームをロービームに切り替える等の防眩を図ることを目的とした協調制御を行うことができる。
Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the external information detection unit 12030, and performs coordinated control for the purpose of anti-glare such as switching the high beam to the low beam. It can be carried out.
音声画像出力部12052は、車両の搭乗者又は車外に対して、視覚的又は聴覚的に情報を通知することが可能な出力装置へ音声及び画像のうちの少なくとも一方の出力信号を送信する。図22の例では、出力装置として、オーディオスピーカ12061、表示部12062及びインストルメントパネル12063が例示されている。表示部12062は、例えば、オンボードディスプレイ及びヘッドアップディスプレイの少なくとも一つを含んでいてもよい。
The audio image output unit 12052 transmits an output signal of at least one of audio and an image to an output device capable of visually or audibly notifying information to the passenger or the outside of the vehicle. In the example of FIG. 22, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an onboard display and a heads-up display.
図23は、撮像部12031の設置位置の例を示す図である。
FIG. 23 is a diagram showing an example of the installation position of the imaging unit 12031.
図23では、撮像部12031として、撮像部12101,12102,12103,12104,12105を有する。
In FIG. 23, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
撮像部12101,12102,12103,12104,12105は、例えば、車両12100のフロントノーズ、サイドミラー、リアバンパ、バックドア及び車室内のフロントガラスの上部等の位置に設けられる。フロントノーズに備えられる撮像部12101及び車室内のフロントガラスの上部に備えられる撮像部12105は、主として車両12100の前方の画像を取得する。サイドミラーに備えられる撮像部12102,12103は、主として車両12100の側方の画像を取得する。リアバンパ又はバックドアに備えられる撮像部12104は、主として車両12100の後方の画像を取得する。車室内のフロントガラスの上部に備えられる撮像部12105は、主として先行車両又は、歩行者、障害物、信号機、交通標識又は車線等の検出に用いられる。
The imaging units 12101, 12102, 12103, 12104, 12105 are provided at positions such as the front nose, side mirrors, rear bumpers, back doors, and the upper part of the windshield in the vehicle interior of the vehicle 12100, for example. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100. The imaging units 12102 and 12103 provided in the side mirrors mainly acquire images of the side of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100. The imaging unit 12105 provided on the upper part of the windshield in the vehicle interior is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.
なお、図23には、撮像部12101ないし12104の撮影範囲の一例が示されている。撮像範囲12111は、フロントノーズに設けられた撮像部12101の撮像範囲を示し、撮像範囲12112,12113は、それぞれサイドミラーに設けられた撮像部12102,12103の撮像範囲を示し、撮像範囲12114は、リアバンパ又はバックドアに設けられた撮像部12104の撮像範囲を示す。例えば、撮像部12101ないし12104で撮像された画像データが重ね合わせられることにより、車両12100を上方から見た俯瞰画像が得られる。
Note that FIG. 23 shows an example of the photographing range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and the imaging range 12114 indicates the imaging range of the imaging units 12102 and 12103. The imaging range of the imaging unit 12104 provided on the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 as viewed from above can be obtained.
撮像部12101ないし12104の少なくとも1つは、距離情報を取得する機能を有していてもよい。例えば、撮像部12101ないし12104の少なくとも1つは、複数の撮像素子からなるステレオカメラであってもよいし、位相差検出用の画素を有する撮像素子であってもよい。
At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image pickup units 12101 to 12104 may be a stereo camera composed of a plurality of image pickup elements, or may be an image pickup element having pixels for phase difference detection.
例えば、マイクロコンピュータ12051は、撮像部12101ないし12104から得られた距離情報を基に、撮像範囲12111ないし12114内における各立体物までの距離と、この距離の時間的変化(車両12100に対する相対速度)を求めることにより、特に車両12100の進行路上にある最も近い立体物で、車両12100と略同じ方向に所定の速度(例えば、0km/h以上)で走行する立体物を先行車として抽出することができる。さらに、マイクロコンピュータ12051は、先行車の手前に予め確保すべき車間距離を設定し、自動ブレーキ制御(追従停止制御も含む)や自動加速制御(追従発進制御も含む)等を行うことができる。このように運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。
For example, the microcomputer 12051 uses the distance information obtained from the imaging units 12101 to 12104 to obtain the distance to each three-dimensional object within the imaging range 12111 to 12114 and the temporal change of this distance (relative velocity with respect to the vehicle 12100). By obtaining, it is possible to extract as the preceding vehicle a three-dimensional object that is the closest three-dimensional object on the traveling path of the vehicle 12100 and that travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or more). can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in front of the preceding vehicle in advance, and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform coordinated control for the purpose of automatic driving or the like in which the vehicle travels autonomously without depending on the operation of the driver.
例えば、マイクロコンピュータ12051は、撮像部12101ないし12104から得られた距離情報を元に、立体物に関する立体物データを、2輪車、普通車両、大型車両、歩行者、電柱等その他の立体物に分類して抽出し、障害物の自動回避に用いることができる。例えば、マイクロコンピュータ12051は、車両12100の周辺の障害物を、車両12100のドライバが視認可能な障害物と視認困難な障害物とに識別する。そして、マイクロコンピュータ12051は、各障害物との衝突の危険度を示す衝突リスクを判断し、衝突リスクが設定値以上で衝突可能性がある状況であるときには、オーディオスピーカ12061や表示部12062を介してドライバに警報を出力することや、駆動系制御ユニット12010を介して強制減速や回避操舵を行うことで、衝突回避のための運転支援を行うことができる。
For example, the microcomputer 12051 converts three-dimensional object data related to a three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that can be seen by the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 is used via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.
撮像部12101ないし12104の少なくとも1つは、赤外線を検出する赤外線カメラであってもよい。例えば、マイクロコンピュータ12051は、撮像部12101ないし12104の撮像画像中に歩行者が存在するか否かを判定することで歩行者を認識することができる。かかる歩行者の認識は、例えば赤外線カメラとしての撮像部12101ないし12104の撮像画像における特徴点を抽出する手順と、物体の輪郭を示す一連の特徴点にパターンマッチング処理を行って歩行者か否かを判別する手順によって行われる。マイクロコンピュータ12051が、撮像部12101ないし12104の撮像画像中に歩行者が存在すると判定し、歩行者を認識すると、音声画像出力部12052は、当該認識された歩行者に強調のための方形輪郭線を重畳表示するように、表示部12062を制御する。また、音声画像出力部12052は、歩行者を示すアイコン等を所望の位置に表示するように表示部12062を制御してもよい。
At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. Such pedestrian recognition includes, for example, a procedure for extracting feature points in an image captured by an imaging unit 12101 to 12104 as an infrared camera, and pattern matching processing for a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. It is done by the procedure to determine. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 outputs a square contour line for emphasizing the recognized pedestrian. The display unit 12062 is controlled so as to superimpose and display. Further, the audio image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.
以上、本開示に係る技術が適用され得る車両制御システムの一例について説明した。本開示に係る技術は、以上説明した構成のうち、例えば、撮像部12031に適用され得る。具体的には、例えば、図1の撮像装置100は、撮像部12031に適用することができる。撮像部12031に本開示に係る技術を適用することにより、メモリのサイズを削減することがきるため、システム全体のコストを低減することが可能になる。
The above is an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technique according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above. Specifically, for example, the image pickup apparatus 100 of FIG. 1 can be applied to the image pickup unit 12031. By applying the technique according to the present disclosure to the imaging unit 12031, the size of the memory can be reduced, so that the cost of the entire system can be reduced.
なお、上述の実施の形態は本技術を具現化するための一例を示したものであり、実施の形態における事項と、特許請求の範囲における発明特定事項とはそれぞれ対応関係を有する。同様に、特許請求の範囲における発明特定事項と、これと同一名称を付した本技術の実施の形態における事項とはそれぞれ対応関係を有する。ただし、本技術は実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において実施の形態に種々の変形を施すことにより具現化することができる。
Note that the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the claims have a corresponding relationship with each other. Similarly, the matters specifying the invention within the scope of claims and the matters in the embodiment of the present technology having the same name have a corresponding relationship with each other. However, the present technology is not limited to the embodiment, and can be embodied by applying various modifications to the embodiment without departing from the gist thereof.
なお、本明細書に記載された効果はあくまで例示であって、限定されるものではなく、また、他の効果があってもよい。
It should be noted that the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.
なお、本技術は以下のような構成もとることができる。
(1)複数のアナログゲインのうち選択されたアナログゲインによりアナログ信号を増減して当該増減したアナログ信号をデジタル信号に変換するアナログデジタル変換器と、
サイズの異なる複数のメモリと、
前記選択されたアナログゲインの誤差を補正するための補正係数を前記デジタル信号に基づいてゲイン補正係数として演算するゲイン補正係数演算部と、
前記ゲイン補正係数の桁数を前記アナログゲインに応じた値に削減して前記複数のメモリのうち削減後の桁数に応じたサイズのメモリに保持させる削減処理部と
を具備する固体撮像素子。
(2)前記複数のメモリは、所定方向に配列され、
前記複数のメモリのそれぞれの前記所定方向のサイズは互いに異なり、
前記複数のメモリのそれぞれの前記所定方向に垂直な方向のサイズは略同一である
前記(1)記載の固体撮像素子。
(3)前記複数のメモリは、2つのグループにグループ化され、
前記2つのグループのそれぞれに属する所定数のメモリは、互いに所定方向のサイズが異なり、前記所定方向に配列され、
前記2つのグループの一方の前記所定方向に垂直な方向のサイズは、他方と異なる
前記(1)記載の固体撮像素子。
(4)前記複数のメモリのそれぞれの所定方向のサイズは略同一であり、
前記複数のメモリのそれぞれの前記所定方向に垂直な方向のサイズは互いに異なり、
各々が一対のメモリからなる複数の組が前記所定方向に配列され、
前記一対のメモリは、前記垂直な方向に配列され、
前記複数の組のそれぞれの前記垂直な方向のサイズの合計は略同一である
前記(1)記載の固体撮像素子。
(5)前記削減処理部は、前記アナログゲインが小さいほど多くの桁数を削減する
前記(1)から(4)のいずかに記載の固体撮像素子。
(6)所定レベルのテスト信号と画素信号とのいずれかを前記アナログ信号として前記アナログデジタル変換器に入力する入力切替部と、
前記保持されたゲイン補正係数により前記デジタル信号の補正を行う補正部と
をさらに具備し、
前記ゲイン補正係数演算部は、前記テスト信号および前記デジタル信号から前記ゲイン補正係数を演算する
前記(1)から(5)のいずれかに記載の固体撮像素子。
(7)前記補正部は、前記保持されたゲイン補正係数の桁数を所定値に拡張して補正を行う前記(6)の固体撮像素子。
(8)前記アナログデジタル変換器は、
前記アナログ信号と所定のランプ信号とを比較して比較結果を出力するコンパレータと、
前記比較結果に基づいて前記デジタル信号を生成するデジタル信号生成部と
を備え、
前記コンパレータは、
所定の基準電圧と所定ノードの電圧との差分を増幅して前記比較結果として出力する差動増幅回路と、
前記所定ノードと前記入力切替部との間に挿入された垂直信号線側容量と、
前記所定ノードと前記ランプ信号を生成するデジタルアナログ変換器との間に挿入されたランプ側容量と、
前記垂直信号線側容量と前記ランプ側容量との容量比を所定の制御信号に従って変更するスイッチと
を備え、
前記複数のアナログゲインは、前記容量比が互いに異なる複数のゲインドメインにグループ化され、
前記複数のメモリのそれぞれには、互いに異なるアナログゲインに対応する前記ゲイン補正係数が保持される
前記(6)または(7)に記載の固体撮像素子。
(9)複数のアナログゲインのうち選択されたアナログゲインによりアナログ信号を増減して当該増減したアナログ信号をデジタル信号に変換するアナログデジタル変換器と、
サイズの異なる複数のメモリと、
前記選択されたアナログゲインの誤差を補正するための補正係数を前記デジタル信号に基づいてゲイン補正係数として演算するゲイン補正係数演算部と、
前記ゲイン補正係数の桁数を前記アナログゲインに応じた値に削減して前記複数のメモリのうち削減後の桁数に応じたサイズのメモリに保持させる削減処理部と、
前記保持されたゲイン補正係数により補正されたデジタル信号を配列した画像信号を処理する画像信号処理部と
を具備する撮像装置。
(10)複数のアナログゲインのうち選択されたアナログゲインによりアナログ信号を増減して当該増減したアナログ信号をデジタル信号に変換するアナログデジタル変換手順と、
前記選択されたアナログゲインの誤差を補正するための補正係数を前記デジタル信号に基づいてゲイン補正係数として演算するゲイン補正係数演算手順と、
前記ゲイン補正係数の桁数を前記アナログゲインに応じた値に削減してサイズの異なる複数のメモリのうち削減後の桁数に応じたサイズのメモリに保持させる削減処理手順と
を具備する固体撮像素子の制御方法。 The present technology can have the following configurations.
(1) An analog-to-digital converter that increases or decreases the analog signal according to the selected analog gain from a plurality of analog gains and converts the increased or decreased analog signal into a digital signal.
With multiple memories of different sizes
A gain correction coefficient calculation unit that calculates a correction coefficient for correcting the error of the selected analog gain as a gain correction coefficient based on the digital signal, and a gain correction coefficient calculation unit.
A solid-state image sensor including a reduction processing unit that reduces the number of digits of the gain correction coefficient to a value corresponding to the analog gain and holds the memory in a size corresponding to the number of digits after reduction among the plurality of memories.
(2) The plurality of memories are arranged in a predetermined direction.
The sizes of the plurality of memories in the predetermined direction are different from each other.
The solid-state image sensor according to (1) above, wherein the sizes of the plurality of memories in the direction perpendicular to the predetermined direction are substantially the same.
(3) The plurality of memories are grouped into two groups.
A predetermined number of memories belonging to each of the two groups have different sizes in a predetermined direction from each other and are arranged in the predetermined direction.
The solid-state image sensor according to (1), wherein the size of one of the two groups in the direction perpendicular to the predetermined direction is different from that of the other.
(4) The sizes of the plurality of memories in the predetermined directions are substantially the same.
The sizes of the plurality of memories in the direction perpendicular to the predetermined direction are different from each other.
A plurality of sets, each consisting of a pair of memories, are arranged in the predetermined direction.
The pair of memories are arranged in the vertical direction and are arranged in the vertical direction.
The solid-state image sensor according to (1) above, wherein the total size of each of the plurality of sets in the vertical direction is substantially the same.
(5) The solid-state image sensor according to any one of (1) to (4) above, wherein the reduction processing unit reduces the number of digits as the analog gain becomes smaller.
(6) An input switching unit that inputs either a predetermined level test signal or a pixel signal as the analog signal to the analog-to-digital converter.
A correction unit that corrects the digital signal by the retained gain correction coefficient is further provided.
The solid-state image sensor according to any one of (1) to (5), wherein the gain correction coefficient calculation unit calculates the gain correction coefficient from the test signal and the digital signal.
(7) The solid-state image sensor according to (6), wherein the correction unit expands the number of digits of the held gain correction coefficient to a predetermined value and performs correction.
(8) The analog-to-digital converter is
A comparator that compares the analog signal with a predetermined lamp signal and outputs a comparison result,
A digital signal generation unit that generates the digital signal based on the comparison result is provided.
The comparator
A differential amplifier circuit that amplifies the difference between the predetermined reference voltage and the voltage of the predetermined node and outputs it as the comparison result.
The vertical signal line side capacitance inserted between the predetermined node and the input switching unit,
The lamp-side capacitance inserted between the predetermined node and the digital-to-analog converter that generates the lamp signal,
A switch for changing the capacitance ratio between the vertical signal line side capacitance and the lamp side capacitance according to a predetermined control signal is provided.
The plurality of analog gains are grouped into a plurality of gain domains having different capacitance ratios.
The solid-state imaging device according to (6) or (7), wherein the gain correction coefficients corresponding to different analog gains are held in each of the plurality of memories.
(9) An analog-to-digital converter that increases or decreases the analog signal according to the analog gain selected from the plurality of analog gains and converts the increased or decreased analog signal into a digital signal.
With multiple memories of different sizes
A gain correction coefficient calculation unit that calculates a correction coefficient for correcting the error of the selected analog gain as a gain correction coefficient based on the digital signal, and a gain correction coefficient calculation unit.
A reduction processing unit that reduces the number of digits of the gain correction coefficient to a value corresponding to the analog gain and holds the memory in a size corresponding to the number of digits after reduction among the plurality of memories.
An image pickup apparatus including an image signal processing unit that processes an image signal in which digital signals corrected by the held gain correction coefficient are arranged.
(10) An analog-to-digital conversion procedure in which an analog signal is increased or decreased according to an analog gain selected from a plurality of analog gains and the increased or decreased analog signal is converted into a digital signal.
A gain correction coefficient calculation procedure for calculating a correction coefficient for correcting an error of the selected analog gain as a gain correction coefficient based on the digital signal, and a procedure for calculating the gain correction coefficient.
Solid-state imaging including a reduction processing procedure for reducing the number of digits of the gain correction coefficient to a value corresponding to the analog gain and holding the memory having a size corresponding to the number of digits after reduction among a plurality of memories having different sizes. Element control method.
(1)複数のアナログゲインのうち選択されたアナログゲインによりアナログ信号を増減して当該増減したアナログ信号をデジタル信号に変換するアナログデジタル変換器と、
サイズの異なる複数のメモリと、
前記選択されたアナログゲインの誤差を補正するための補正係数を前記デジタル信号に基づいてゲイン補正係数として演算するゲイン補正係数演算部と、
前記ゲイン補正係数の桁数を前記アナログゲインに応じた値に削減して前記複数のメモリのうち削減後の桁数に応じたサイズのメモリに保持させる削減処理部と
を具備する固体撮像素子。
(2)前記複数のメモリは、所定方向に配列され、
前記複数のメモリのそれぞれの前記所定方向のサイズは互いに異なり、
前記複数のメモリのそれぞれの前記所定方向に垂直な方向のサイズは略同一である
前記(1)記載の固体撮像素子。
(3)前記複数のメモリは、2つのグループにグループ化され、
前記2つのグループのそれぞれに属する所定数のメモリは、互いに所定方向のサイズが異なり、前記所定方向に配列され、
前記2つのグループの一方の前記所定方向に垂直な方向のサイズは、他方と異なる
前記(1)記載の固体撮像素子。
(4)前記複数のメモリのそれぞれの所定方向のサイズは略同一であり、
前記複数のメモリのそれぞれの前記所定方向に垂直な方向のサイズは互いに異なり、
各々が一対のメモリからなる複数の組が前記所定方向に配列され、
前記一対のメモリは、前記垂直な方向に配列され、
前記複数の組のそれぞれの前記垂直な方向のサイズの合計は略同一である
前記(1)記載の固体撮像素子。
(5)前記削減処理部は、前記アナログゲインが小さいほど多くの桁数を削減する
前記(1)から(4)のいずかに記載の固体撮像素子。
(6)所定レベルのテスト信号と画素信号とのいずれかを前記アナログ信号として前記アナログデジタル変換器に入力する入力切替部と、
前記保持されたゲイン補正係数により前記デジタル信号の補正を行う補正部と
をさらに具備し、
前記ゲイン補正係数演算部は、前記テスト信号および前記デジタル信号から前記ゲイン補正係数を演算する
前記(1)から(5)のいずれかに記載の固体撮像素子。
(7)前記補正部は、前記保持されたゲイン補正係数の桁数を所定値に拡張して補正を行う前記(6)の固体撮像素子。
(8)前記アナログデジタル変換器は、
前記アナログ信号と所定のランプ信号とを比較して比較結果を出力するコンパレータと、
前記比較結果に基づいて前記デジタル信号を生成するデジタル信号生成部と
を備え、
前記コンパレータは、
所定の基準電圧と所定ノードの電圧との差分を増幅して前記比較結果として出力する差動増幅回路と、
前記所定ノードと前記入力切替部との間に挿入された垂直信号線側容量と、
前記所定ノードと前記ランプ信号を生成するデジタルアナログ変換器との間に挿入されたランプ側容量と、
前記垂直信号線側容量と前記ランプ側容量との容量比を所定の制御信号に従って変更するスイッチと
を備え、
前記複数のアナログゲインは、前記容量比が互いに異なる複数のゲインドメインにグループ化され、
前記複数のメモリのそれぞれには、互いに異なるアナログゲインに対応する前記ゲイン補正係数が保持される
前記(6)または(7)に記載の固体撮像素子。
(9)複数のアナログゲインのうち選択されたアナログゲインによりアナログ信号を増減して当該増減したアナログ信号をデジタル信号に変換するアナログデジタル変換器と、
サイズの異なる複数のメモリと、
前記選択されたアナログゲインの誤差を補正するための補正係数を前記デジタル信号に基づいてゲイン補正係数として演算するゲイン補正係数演算部と、
前記ゲイン補正係数の桁数を前記アナログゲインに応じた値に削減して前記複数のメモリのうち削減後の桁数に応じたサイズのメモリに保持させる削減処理部と、
前記保持されたゲイン補正係数により補正されたデジタル信号を配列した画像信号を処理する画像信号処理部と
を具備する撮像装置。
(10)複数のアナログゲインのうち選択されたアナログゲインによりアナログ信号を増減して当該増減したアナログ信号をデジタル信号に変換するアナログデジタル変換手順と、
前記選択されたアナログゲインの誤差を補正するための補正係数を前記デジタル信号に基づいてゲイン補正係数として演算するゲイン補正係数演算手順と、
前記ゲイン補正係数の桁数を前記アナログゲインに応じた値に削減してサイズの異なる複数のメモリのうち削減後の桁数に応じたサイズのメモリに保持させる削減処理手順と
を具備する固体撮像素子の制御方法。 The present technology can have the following configurations.
(1) An analog-to-digital converter that increases or decreases the analog signal according to the selected analog gain from a plurality of analog gains and converts the increased or decreased analog signal into a digital signal.
With multiple memories of different sizes
A gain correction coefficient calculation unit that calculates a correction coefficient for correcting the error of the selected analog gain as a gain correction coefficient based on the digital signal, and a gain correction coefficient calculation unit.
A solid-state image sensor including a reduction processing unit that reduces the number of digits of the gain correction coefficient to a value corresponding to the analog gain and holds the memory in a size corresponding to the number of digits after reduction among the plurality of memories.
(2) The plurality of memories are arranged in a predetermined direction.
The sizes of the plurality of memories in the predetermined direction are different from each other.
The solid-state image sensor according to (1) above, wherein the sizes of the plurality of memories in the direction perpendicular to the predetermined direction are substantially the same.
(3) The plurality of memories are grouped into two groups.
A predetermined number of memories belonging to each of the two groups have different sizes in a predetermined direction from each other and are arranged in the predetermined direction.
The solid-state image sensor according to (1), wherein the size of one of the two groups in the direction perpendicular to the predetermined direction is different from that of the other.
(4) The sizes of the plurality of memories in the predetermined directions are substantially the same.
The sizes of the plurality of memories in the direction perpendicular to the predetermined direction are different from each other.
A plurality of sets, each consisting of a pair of memories, are arranged in the predetermined direction.
The pair of memories are arranged in the vertical direction and are arranged in the vertical direction.
The solid-state image sensor according to (1) above, wherein the total size of each of the plurality of sets in the vertical direction is substantially the same.
(5) The solid-state image sensor according to any one of (1) to (4) above, wherein the reduction processing unit reduces the number of digits as the analog gain becomes smaller.
(6) An input switching unit that inputs either a predetermined level test signal or a pixel signal as the analog signal to the analog-to-digital converter.
A correction unit that corrects the digital signal by the retained gain correction coefficient is further provided.
The solid-state image sensor according to any one of (1) to (5), wherein the gain correction coefficient calculation unit calculates the gain correction coefficient from the test signal and the digital signal.
(7) The solid-state image sensor according to (6), wherein the correction unit expands the number of digits of the held gain correction coefficient to a predetermined value and performs correction.
(8) The analog-to-digital converter is
A comparator that compares the analog signal with a predetermined lamp signal and outputs a comparison result,
A digital signal generation unit that generates the digital signal based on the comparison result is provided.
The comparator
A differential amplifier circuit that amplifies the difference between the predetermined reference voltage and the voltage of the predetermined node and outputs it as the comparison result.
The vertical signal line side capacitance inserted between the predetermined node and the input switching unit,
The lamp-side capacitance inserted between the predetermined node and the digital-to-analog converter that generates the lamp signal,
A switch for changing the capacitance ratio between the vertical signal line side capacitance and the lamp side capacitance according to a predetermined control signal is provided.
The plurality of analog gains are grouped into a plurality of gain domains having different capacitance ratios.
The solid-state imaging device according to (6) or (7), wherein the gain correction coefficients corresponding to different analog gains are held in each of the plurality of memories.
(9) An analog-to-digital converter that increases or decreases the analog signal according to the analog gain selected from the plurality of analog gains and converts the increased or decreased analog signal into a digital signal.
With multiple memories of different sizes
A gain correction coefficient calculation unit that calculates a correction coefficient for correcting the error of the selected analog gain as a gain correction coefficient based on the digital signal, and a gain correction coefficient calculation unit.
A reduction processing unit that reduces the number of digits of the gain correction coefficient to a value corresponding to the analog gain and holds the memory in a size corresponding to the number of digits after reduction among the plurality of memories.
An image pickup apparatus including an image signal processing unit that processes an image signal in which digital signals corrected by the held gain correction coefficient are arranged.
(10) An analog-to-digital conversion procedure in which an analog signal is increased or decreased according to an analog gain selected from a plurality of analog gains and the increased or decreased analog signal is converted into a digital signal.
A gain correction coefficient calculation procedure for calculating a correction coefficient for correcting an error of the selected analog gain as a gain correction coefficient based on the digital signal, and a procedure for calculating the gain correction coefficient.
Solid-state imaging including a reduction processing procedure for reducing the number of digits of the gain correction coefficient to a value corresponding to the analog gain and holding the memory having a size corresponding to the number of digits after reduction among a plurality of memories having different sizes. Element control method.
100 撮像装置
110 光学部
120 DSP回路
130 表示部
140 操作部
150 バス
160 フレームメモリ
170 記憶部
180 電源部
200 固体撮像素子
201 画素チップ
202 回路チップ
210 垂直走査回路
220 テスト信号源
230 DAC
240 タイミング制御回路
250 画素アレイ部
260 画素
261 光電変換素子
262 転送トランジスタ
263 リセットトランジスタ
264 浮遊拡散層
265 増幅トランジスタ
266 選択トランジスタ
270 入力切替部
271、340 セレクタ
280 カラム信号処理部
281 ADC
282 カウンタ
300 画像処理部
310 ゲイン誤差測定部
311 サンプル数カウンタ
312 更新パルス生成部
313 ゲイン演算部
314 オフセット演算部
320 補正値計算部
321 ゲイン補正係数演算部
322 削減処理部
323 減算器
324 デマルチプレクサ
325 クリップ処理部
326 小数桁削減部
330 記憶部
331 メモリ
350 補正部
351 桁数拡張部
352 マルチプレクサ
353 加算器
354 乗算器
360 コントローラ
400 コンパレータ
410 容量比切替回路
411~415 スイッチ
416~421、440 容量
430 差動増幅回路
431、432 pMOSトランジスタ
433~435 nMOSトランジスタ
436、437 オートゼロスイッチ
12031 撮像部 100Image sensor 110 Optical unit 120 DSP circuit 130 Display unit 140 Operation unit 150 Bus 160 Frame memory 170 Storage unit 180 Power supply unit 200 Solid-state image sensor 201 Pixel chip 202 Circuit chip 210 Vertical scanning circuit 220 Test signal source 230 DAC
240Timing control circuit 250 pixel array unit 260 pixels 261 photoelectric conversion element 262 Transfer transistor 263 Reset transistor 264 Floating diffusion layer 265 Amplification transistor 266 Selection transistor 270 Input switching unit 271, 340 Selector 280 Column signal processing unit 281 ADC
282Counter 300 Image processing unit 310 Gain error measurement unit 311 Sample number counter 312 Update pulse generation unit 313 Gain calculation unit 314 Offset calculation unit 320 Correction value calculation unit 321 Gain correction coefficient calculation unit 322 Reduction processing unit 323 Subtractor 324 Demultiplexer 325 Clip processing unit 326 Fractional digit reduction unit 330 Storage unit 331 Memory 350 Correction unit 351 Digit number expansion unit 352 Multiplexer 353 Adder 354 Multiplier 360 controller 400 Comparator 410 Capacity ratio switching circuit 411 to 415 Switch 416 to 421, 440 Capacity 430 Difference Dynamic amplification circuit 431, 432 pMOS transistor 433 to 435 nMOS transistor 436, 437 auto-zero switch 12031 Imaging unit
110 光学部
120 DSP回路
130 表示部
140 操作部
150 バス
160 フレームメモリ
170 記憶部
180 電源部
200 固体撮像素子
201 画素チップ
202 回路チップ
210 垂直走査回路
220 テスト信号源
230 DAC
240 タイミング制御回路
250 画素アレイ部
260 画素
261 光電変換素子
262 転送トランジスタ
263 リセットトランジスタ
264 浮遊拡散層
265 増幅トランジスタ
266 選択トランジスタ
270 入力切替部
271、340 セレクタ
280 カラム信号処理部
281 ADC
282 カウンタ
300 画像処理部
310 ゲイン誤差測定部
311 サンプル数カウンタ
312 更新パルス生成部
313 ゲイン演算部
314 オフセット演算部
320 補正値計算部
321 ゲイン補正係数演算部
322 削減処理部
323 減算器
324 デマルチプレクサ
325 クリップ処理部
326 小数桁削減部
330 記憶部
331 メモリ
350 補正部
351 桁数拡張部
352 マルチプレクサ
353 加算器
354 乗算器
360 コントローラ
400 コンパレータ
410 容量比切替回路
411~415 スイッチ
416~421、440 容量
430 差動増幅回路
431、432 pMOSトランジスタ
433~435 nMOSトランジスタ
436、437 オートゼロスイッチ
12031 撮像部 100
240
282
Claims (10)
- 複数のアナログゲインのうち選択されたアナログゲインによりアナログ信号を増減して当該増減したアナログ信号をデジタル信号に変換するアナログデジタル変換器と、
サイズの異なる複数のメモリと、
前記選択されたアナログゲインの誤差を補正するための補正係数を前記デジタル信号に基づいてゲイン補正係数として演算するゲイン補正係数演算部と、
前記ゲイン補正係数の桁数を前記アナログゲインに応じた値に削減して前記複数のメモリのうち削減後の桁数に応じたサイズのメモリに保持させる削減処理部と
を具備する固体撮像素子。 An analog-to-digital converter that increases or decreases the analog signal according to the selected analog gain from multiple analog gains and converts the increased or decreased analog signal into a digital signal.
With multiple memories of different sizes
A gain correction coefficient calculation unit that calculates a correction coefficient for correcting the error of the selected analog gain as a gain correction coefficient based on the digital signal, and a gain correction coefficient calculation unit.
A solid-state image sensor including a reduction processing unit that reduces the number of digits of the gain correction coefficient to a value corresponding to the analog gain and holds the memory in a size corresponding to the number of digits after reduction among the plurality of memories. - 前記複数のメモリは、所定方向に配列され、
前記複数のメモリのそれぞれの前記所定方向のサイズは互いに異なり、
前記複数のメモリのそれぞれの前記所定方向に垂直な方向のサイズは略同一である
請求項1記載の固体撮像素子。 The plurality of memories are arranged in a predetermined direction, and the plurality of memories are arranged in a predetermined direction.
The sizes of the plurality of memories in the predetermined direction are different from each other.
The solid-state image sensor according to claim 1, wherein the sizes of the plurality of memories in the direction perpendicular to the predetermined direction are substantially the same. - 前記複数のメモリは、2つのグループにグループ化され、
前記2つのグループのそれぞれに属する所定数のメモリは、互いに所定方向のサイズが異なり、前記所定方向に配列され、
前記2つのグループの一方の前記所定方向に垂直な方向のサイズは、他方と異なる
請求項1記載の固体撮像素子。 The plurality of memories are grouped into two groups, and the plurality of memories are grouped into two groups.
A predetermined number of memories belonging to each of the two groups have different sizes in a predetermined direction from each other and are arranged in the predetermined direction.
The solid-state image sensor according to claim 1, wherein the size of one of the two groups in the direction perpendicular to the predetermined direction is different from that of the other. - 前記複数のメモリのそれぞれの所定方向のサイズは略同一であり、
前記複数のメモリのそれぞれの前記所定方向に垂直な方向のサイズは互いに異なり、
各々が一対のメモリからなる複数の組が前記所定方向に配列され、
前記一対のメモリは、前記垂直な方向に配列され、
前記複数の組のそれぞれの前記垂直な方向のサイズの合計は略同一である
請求項1記載の固体撮像素子。 The size of each of the plurality of memories in a predetermined direction is substantially the same.
The sizes of the plurality of memories in the direction perpendicular to the predetermined direction are different from each other.
A plurality of sets, each consisting of a pair of memories, are arranged in the predetermined direction.
The pair of memories are arranged in the vertical direction and are arranged in the vertical direction.
The solid-state image sensor according to claim 1, wherein the total size of each of the plurality of sets in the vertical direction is substantially the same. - 前記削減処理部は、前記アナログゲインが小さいほど多くの桁数を削減する
請求項1記載の固体撮像素子。 The solid-state image sensor according to claim 1, wherein the reduction processing unit reduces the number of digits as the analog gain becomes smaller. - 所定レベルのテスト信号と画素信号とのいずれかを前記アナログ信号として前記アナログデジタル変換器に入力する入力切替部と、
前記保持されたゲイン補正係数により前記デジタル信号の補正を行う補正部と
をさらに具備し、
前記ゲイン補正係数演算部は、前記テスト信号および前記デジタル信号から前記ゲイン補正係数を演算する
請求項1記載の固体撮像素子。 An input switching unit that inputs either a predetermined level test signal or a pixel signal as the analog signal to the analog-to-digital converter.
A correction unit that corrects the digital signal by the retained gain correction coefficient is further provided.
The solid-state image sensor according to claim 1, wherein the gain correction coefficient calculation unit calculates the gain correction coefficient from the test signal and the digital signal. - 前記補正部は、前記保持されたゲイン補正係数の桁数を所定値に拡張して補正を行う請求項6の固体撮像素子。 The solid-state image sensor according to claim 6, wherein the correction unit expands the number of digits of the held gain correction coefficient to a predetermined value to perform correction.
- 前記アナログデジタル変換器は、
前記アナログ信号と所定のランプ信号とを比較して比較結果を出力するコンパレータと、
前記比較結果に基づいて前記デジタル信号を生成するデジタル信号生成部と
を備え、
前記コンパレータは、
所定の基準電圧と所定ノードの電圧との差分を増幅して前記比較結果として出力する差動増幅回路と、
前記所定ノードと前記入力切替部との間に挿入された垂直信号線側容量と、
前記所定ノードと前記ランプ信号を生成するデジタルアナログ変換器との間に挿入されたランプ側容量と、
前記垂直信号線側容量と前記ランプ側容量との容量比を所定の制御信号に従って変更するスイッチと
を備え、
前記複数のアナログゲインは、前記容量比が互いに異なる複数のゲインドメインにグループ化され、
前記複数のメモリのそれぞれには、互いに異なるアナログゲインに対応する前記ゲイン補正係数が保持される
請求項6記載の固体撮像素子。 The analog-to-digital converter is
A comparator that compares the analog signal with a predetermined lamp signal and outputs a comparison result,
A digital signal generation unit that generates the digital signal based on the comparison result is provided.
The comparator
A differential amplifier circuit that amplifies the difference between the predetermined reference voltage and the voltage of the predetermined node and outputs it as the comparison result.
The vertical signal line side capacitance inserted between the predetermined node and the input switching unit,
The lamp-side capacitance inserted between the predetermined node and the digital-to-analog converter that generates the lamp signal,
A switch for changing the capacitance ratio between the vertical signal line side capacitance and the lamp side capacitance according to a predetermined control signal is provided.
The plurality of analog gains are grouped into a plurality of gain domains having different capacitance ratios.
The solid-state imaging device according to claim 6, wherein the gain correction coefficients corresponding to different analog gains are held in each of the plurality of memories. - 複数のアナログゲインのうち選択されたアナログゲインによりアナログ信号を増減して当該増減したアナログ信号をデジタル信号に変換するアナログデジタル変換器と、
サイズの異なる複数のメモリと、
前記選択されたアナログゲインの誤差を補正するための補正係数を前記デジタル信号に基づいてゲイン補正係数として演算するゲイン補正係数演算部と、
前記ゲイン補正係数の桁数を前記アナログゲインに応じた値に削減して前記複数のメモリのうち削減後の桁数に応じたサイズのメモリに保持させる削減処理部と、
前記保持されたゲイン補正係数により補正されたデジタル信号を配列した画像信号を処理する画像信号処理部と
を具備する撮像装置。 An analog-to-digital converter that increases or decreases the analog signal according to the selected analog gain from multiple analog gains and converts the increased or decreased analog signal into a digital signal.
With multiple memories of different sizes
A gain correction coefficient calculation unit that calculates a correction coefficient for correcting the error of the selected analog gain as a gain correction coefficient based on the digital signal, and a gain correction coefficient calculation unit.
A reduction processing unit that reduces the number of digits of the gain correction coefficient to a value corresponding to the analog gain and holds the memory in a size corresponding to the number of digits after reduction among the plurality of memories.
An image pickup apparatus including an image signal processing unit that processes an image signal in which digital signals corrected by the held gain correction coefficient are arranged. - 複数のアナログゲインのうち選択されたアナログゲインによりアナログ信号を増減して当該増減したアナログ信号をデジタル信号に変換するアナログデジタル変換手順と、
前記選択されたアナログゲインの誤差を補正するための補正係数を前記デジタル信号に基づいてゲイン補正係数として演算するゲイン補正係数演算手順と、
前記ゲイン補正係数の桁数を前記アナログゲインに応じた値に削減してサイズの異なる複数のメモリのうち削減後の桁数に応じたサイズのメモリに保持させる削減処理手順と
を具備する固体撮像素子の制御方法。 An analog-to-digital conversion procedure that increases or decreases the analog signal according to the selected analog gain from multiple analog gains and converts the increased or decreased analog signal into a digital signal.
A gain correction coefficient calculation procedure for calculating a correction coefficient for correcting an error of the selected analog gain as a gain correction coefficient based on the digital signal, and a procedure for calculating the gain correction coefficient.
Solid-state imaging including a reduction processing procedure for reducing the number of digits of the gain correction coefficient to a value corresponding to the analog gain and holding the memory having a size corresponding to the number of digits after reduction among a plurality of memories having different sizes. Element control method.
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Citations (4)
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JPS62279787A (en) * | 1986-05-28 | 1987-12-04 | Nec Corp | Noise eliminating device for flat image pickup element fix pattern |
JP2007028521A (en) * | 2005-07-21 | 2007-02-01 | Micron Technol Inc | Method and apparatus for performing imager noise reduction using parallel input arithmetic average module |
JP2008244947A (en) * | 2007-03-28 | 2008-10-09 | Sony Corp | Fixed pattern noise elimination circuit, fixed pattern noise elimination method, program, and imaging apparatus |
JP2016143958A (en) * | 2015-01-30 | 2016-08-08 | 株式会社東芝 | Solid-state image pickup device |
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JPS62279787A (en) * | 1986-05-28 | 1987-12-04 | Nec Corp | Noise eliminating device for flat image pickup element fix pattern |
JP2007028521A (en) * | 2005-07-21 | 2007-02-01 | Micron Technol Inc | Method and apparatus for performing imager noise reduction using parallel input arithmetic average module |
JP2008244947A (en) * | 2007-03-28 | 2008-10-09 | Sony Corp | Fixed pattern noise elimination circuit, fixed pattern noise elimination method, program, and imaging apparatus |
JP2016143958A (en) * | 2015-01-30 | 2016-08-08 | 株式会社東芝 | Solid-state image pickup device |
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