WO2022241834A1 - 一种显示面板 - Google Patents

一种显示面板 Download PDF

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Publication number
WO2022241834A1
WO2022241834A1 PCT/CN2021/097505 CN2021097505W WO2022241834A1 WO 2022241834 A1 WO2022241834 A1 WO 2022241834A1 CN 2021097505 W CN2021097505 W CN 2021097505W WO 2022241834 A1 WO2022241834 A1 WO 2022241834A1
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WO
WIPO (PCT)
Prior art keywords
transistor
node
metal layer
capacitor
layer
Prior art date
Application number
PCT/CN2021/097505
Other languages
English (en)
French (fr)
Inventor
李波
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/419,277 priority Critical patent/US20240013715A1/en
Publication of WO2022241834A1 publication Critical patent/WO2022241834A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present application relates to the display field, in particular to a display panel.
  • OLED Organic Light Emitting Diode
  • LCD Liquid Crystal Displays
  • the thin film transistors in the pixel circuit are usually formed by the Low Temperature Poly-silicon (LTPS) process, and the leakage current of the thin film transistors formed by the LTPS process is large, when using low-frequency display It is prone to problems such as flickering and high power consumption, which will affect the display quality.
  • LTPS Low Temperature Poly-silicon
  • An embodiment of the present application provides a display panel for reducing power consumption of a pixel driving circuit.
  • the application provides a display panel, including:
  • a pixel driving circuit layer including a plurality of pixel driving circuits, each of which includes a first capacitor and a second capacitor;
  • the pixel driving circuit layer includes: first semiconductor semiconductors sequentially stacked on the substrate
  • the body layer a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, and a fourth metal layer, wherein the fourth metal layer includes a first source, a first drain, a second source pole and a second drain, the first source and the first drain are electrically connected to the first semiconductor layer, the second source and the second drain are connected to the second semiconductor layer electrically connected, the second semiconductor layer is an oxide semiconductor layer;
  • both the first capacitor and the second capacitor have a capacitor electrode disposed on the second metal layer.
  • the first metal layer includes a first capacitor electrode
  • the second metal layer includes a second capacitor electrode
  • the second metal layer includes a first capacitor electrode
  • the first metal layer includes a first capacitor electrode.
  • the three metal layers include a second capacitor electrode; the first capacitor electrode and the second capacitor electrode form the first capacitor, and the second capacitor electrode is electrically connected to the fourth metal layer.
  • the display panel further includes a first interlayer dielectric layer located between the second metal layer and the second semiconductor layer, a first interlayer dielectric layer located between the second semiconductor layer and the A third insulating layer between the third metal layers and a second interlayer dielectric layer between the third metal layer and the fourth metal layer.
  • the display panel is provided with a first via hole passing through the second interlayer dielectric layer, the third insulating layer, and the first interlayer dielectric layer;
  • the fourth metal layer is electrically connected to the second capacitor electrode through the first via hole.
  • the display panel is provided with a first via hole passing through the second interlayer dielectric layer
  • the fourth metal layer is electrically connected to the second capacitor electrode through the first via hole.
  • the display panel further includes a first insulating layer located between the first semiconductor layer and the first metal layer, and a first insulation layer located between the first metal layer and the first metal layer. a second insulating layer between the two metal layers;
  • the first metal layer further includes a first grid and a third capacitor electrode
  • the second metal layer further includes a fourth capacitor electrode
  • the third metal layer further includes a third grid, wherein the The third capacitor electrode and the fourth capacitor electrode form the second capacitor.
  • the display panel further includes a third semiconductor layer arranged in the same layer as the second semiconductor layer and spaced apart, and the third semiconductor layer is electrically connected to the fourth metal layer;
  • the projection of the third semiconductor layer on the substrate at least partially overlaps with the projection of the overlapping region of the first capacitive electrode and the second capacitive electrode on the substrate.
  • the first semiconductor layer is a polysilicon semiconductor layer
  • the third semiconductor layer is an oxide semiconductor layer
  • the display panel further includes a plurality of light-emitting devices arranged in an array and a pixel driving circuit for driving the light-emitting devices to emit light
  • the pixel driving circuit includes a first initialization transistor, a switching transistor, a driving Transistors, compensation transistors, second initialization transistors, first light emission control transistors, second light emission control transistors, the first capacitor and the second capacitor;
  • the gate of the driving transistor is connected to the first node, the first terminal of the driving transistor is connected to the third node, and the second terminal of the driving transistor is connected to the second node;
  • the gate of the switch transistor is connected to the second scan signal, the first end of the switch transistor is connected to the data signal, and the second end of the switch transistor is connected to the second node;
  • the gate of the compensation transistor is connected to the second scanning signal, and the first terminal of the compensation transistor is connected to
  • the second terminal of the compensation transistor is connected to the first node
  • the gate of the first initialization transistor is connected to the first scan signal, the first end of the first initialization transistor is connected to the second initialization signal, and the second end of the first initialization transistor is connected to the first node;
  • the gate of the first light emission control transistor is connected to the light emission control signal, the first end of the first light emission control transistor is connected to the fifth node, and the second end of the first light emission control transistor is connected to the second node, so The first light emitting control transistor is connected to the high potential signal line of the power supply through the fifth node;
  • the gate of the second light emission control transistor is connected to a light emission control signal, the first end of the second light emission control transistor is connected to the third node, and the second end of the second light emission control transistor is connected to the fourth node;
  • the gate of the second initialization transistor is connected to the second scan signal, the first terminal of the second initialization transistor is connected to the fourth node, and the second terminal of the second initialization transistor is connected to the first initialization signal;
  • the first capacitor electrode of the first capacitor is connected to the gate of the switching transistor, and the second capacitor electrode of the first capacitor is connected to the first node;
  • the third capacitor electrode of the second capacitor is connected to the fifth node
  • the fourth capacitor electrode of the second capacitor is connected to the first node
  • the second capacitor is connected to the high potential signal line of the power supply through the fifth node.
  • the compensation transistor, the first initialization transistor, and the second initialization transistor are oxide transistors, and the switching transistor, the driving transistor, and the first light emission control transistor And the second light emission control transistor is a low temperature polysilicon transistor.
  • the present application provides a display panel.
  • the display panel includes a plurality of light emitting devices arranged in an array and a pixel driving circuit for driving the light emitting devices to emit light.
  • the pixel driving circuit includes:
  • a first initialization transistor configured to input a second initialization signal to the first node under the control of the first scan signal
  • a switch transistor configured to input a data signal to the second node under the control of the second scan signal
  • a driving transistor configured to drive the light emitting device to emit light under the control of the potentials of the first node and the second node;
  • a compensation transistor connected to the driving transistor through the first node and the third node, and used to compensate the threshold voltage of the driving transistor under the control of the third scanning signal;
  • the second initialization transistor is used to input the first initialization signal to the anode of the light emitting device under the control of the second scanning signal;
  • the first light emission control transistor is connected to the drive transistor through the second node, and is used to turn on the current flowing from the high potential signal line of the power supply to the drive transistor under the control of the light emission control signal;
  • the second light emission control transistor is connected to the drive transistor through a third node, and is used to turn on the current flowing from the drive transistor to the anode of the light emitting device under the control of the light emission control signal;
  • a first capacitor coupled between the first node and the gate of the switch transistor, for reducing the potential of the first node
  • the second capacitor is connected to the driving transistor through the first node, and connected to the high potential signal line of the power supply through the fourth node, and is used for storing data signals;
  • the first capacitor includes a first capacitor electrode and a second capacitor electrode oppositely arranged, the first capacitor electrode is electrically connected to the gate of the switching transistor, and the second capacitor electrode is connected to the first node through the first node.
  • the first initialization transistor is electrically connected, wherein the switch transistor is a low temperature polysilicon transistor, and the first initialization transistor is an oxide transistor.
  • the gate of the driving transistor is connected to the first node, the first terminal of the driving transistor is connected to the third node, and the second terminal of the driving transistor is connected to the second node ;
  • the gate of the switch transistor is connected to the second scan signal, the first end of the switch transistor is connected to the data signal, and the second end of the switch transistor is connected to the second node;
  • the gate of the compensation transistor is connected to the second scanning signal, and the first terminal of the compensation transistor is connected to
  • the second terminal of the compensation transistor is connected to the first node
  • the gate of the first initialization transistor is connected to the first scan signal, the first end of the first initialization transistor is connected to the second initialization signal, and the second end of the first initialization transistor is connected to the first node;
  • the gate of the first light emission control transistor is connected to the light emission control signal, the first end of the first light emission control transistor is connected to the fifth node, and the second end of the first light emission control transistor is connected to the second node, so The first light emitting control transistor is connected to the high potential signal line of the power supply through the fifth node;
  • the gate of the second light emission control transistor is connected to a light emission control signal, the first end of the second light emission control transistor is connected to the third node, and the second end of the second light emission control transistor is connected to the fourth node;
  • the gate of the second initialization transistor is connected to the second scan signal, the first terminal of the second initialization transistor is connected to the fourth node, and the second terminal of the second initialization transistor is connected to the first initialization signal;
  • the first capacitor electrode of the first capacitor is connected to the gate of the switching transistor, and the second capacitor electrode of the first capacitor is connected to the first node;
  • the third capacitor electrode of the second capacitor is connected to the fifth node
  • the fourth capacitor electrode of the second capacitor is connected to the first node
  • the second capacitor is connected to the high potential signal line of the power supply through the fifth node.
  • the compensation transistor and the second initialization transistor are oxide transistors
  • the drive transistor, the first light emission control transistor and the second light emission control transistor are low temperature polysilicon transistors .
  • the display panel also includes:
  • a pixel driving circuit layer including a plurality of pixel driving circuits, each of which includes a first capacitor and a second capacitor;
  • the pixel driving circuit layer includes: first semiconductor semiconductors sequentially stacked on the substrate
  • the body layer a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, and a fourth metal layer, wherein the fourth metal layer includes a first source, a first drain, a second source pole and a second drain, the first source and the first drain are electrically connected to the first semiconductor layer, the second source and the second drain are connected to the second semiconductor layer electrically connected, the second semiconductor layer is an oxide semiconductor layer;
  • both the first capacitor and the second capacitor have a capacitor electrode disposed on the second metal layer.
  • the first metal layer includes a first capacitor electrode
  • the second metal layer includes a second capacitor electrode
  • the second metal layer includes a first capacitor electrode
  • the first metal layer includes a first capacitor electrode.
  • the three metal layers include a second capacitor electrode; the first capacitor electrode and the second capacitor electrode form the first capacitor, and the second capacitor electrode is electrically connected to the fourth metal layer.
  • the display panel further includes a first interlayer dielectric layer located between the second metal layer and the second semiconductor layer, a first interlayer dielectric layer located between the second semiconductor layer and the A third insulating layer between the third metal layers and a second interlayer dielectric layer between the third metal layer and the fourth metal layer.
  • the display panel is provided with a first via hole passing through the second interlayer dielectric layer, the third insulating layer, and the first interlayer dielectric layer;
  • the fourth metal layer is electrically connected to the second capacitor electrode through the first via hole.
  • the display panel is provided with a first via hole passing through the second interlayer dielectric layer
  • the fourth metal layer is electrically connected to the second capacitor electrode through the first via hole.
  • the display panel further includes a second insulating layer located between the first semiconductor layer and the first metal layer, and a second insulating layer located between the first metal layer and the first metal layer. a third insulating layer between the two metal layers;
  • the first metal layer further includes a first grid and a third capacitor electrode
  • the second metal layer further includes a fourth capacitor electrode
  • the third metal layer further includes a third grid, wherein the The third capacitor electrode and the fourth capacitor electrode form the second capacitor.
  • the display panel further includes a third semiconductor layer arranged in the same layer as the second semiconductor layer and spaced apart, and the third semiconductor layer is electrically connected to the fourth metal layer;
  • the projection of the third semiconductor layer on the substrate at least partially overlaps with the projection of the overlapping region of the first capacitive electrode and the second capacitive electrode on the substrate.
  • the present application proposes a 7T2C circuit structure, by sequentially stacking the first semiconductor layer, the first metal layer, the second metal layer, the second semiconductor layer, the third metal layer and the fourth metal layer, wherein the fourth metal layer includes a first source, a first drain, a second source, and a second drain, and the first source and the first drain are connected to the first The semiconductor layer is electrically connected, the second source and the second drain are electrically connected to the second semiconductor layer, and the second semiconductor layer is an oxide semiconductor layer; wherein, the first metal layer includes a first A capacitor electrode, the second metal layer includes a second capacitor electrode, or the second metal layer includes a first capacitor electrode, and the third metal layer includes a second capacitor electrode; the first capacitor electrode and the The second capacitor electrode forms a first capacitor, and the second capacitor electrode is electrically connected to the fourth metal layer, so that the display panel can realize low-frequency display and have a stable display effect; at the same time, the power of the pixel driving circuit can be reduced. consumption, to avoid
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit of a display panel in the prior art
  • FIG. 2 is a schematic structural diagram of a display panel in the prior art
  • FIG. 3 is a schematic diagram of a planar superposition structure of each film layer of a display panel in the prior art
  • FIG. 4 is a first structural schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a pixel driving circuit of a display panel provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of the planar superposition structure of the first film layers of the display panel provided by the embodiment of the present application.
  • FIG. 7 is a schematic diagram of a first planar structure of a first metal layer of a display panel provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of the first planar structure of the second metal layer of the display panel provided by the embodiment of the present application.
  • FIG. 9 is a schematic diagram of a first planar structure of the second semiconductor layer and the third semiconductor layer of the display panel provided by the embodiment of the present application.
  • FIG. 10 is a schematic diagram of a first planar structure of a third metal layer of a display panel provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of the first planar structure of the fourth metal layer of the display panel provided by the embodiment of the present application.
  • FIG. 12 is a schematic diagram of the first planar structure of the fifth metal layer of the display panel provided by the embodiment of the present application.
  • FIG. 13 is a second structural schematic diagram of the display panel provided by the embodiment of the present application.
  • Fig. 14 is a schematic diagram of the plane superposition structure of the second type of various film layers of the display panel provided by the embodiment of the present application;
  • FIG. 15 is a schematic diagram of a second planar structure of the first metal layer of the display panel provided by the embodiment of the present application.
  • FIG. 16 is a schematic diagram of a second planar structure of a second metal layer of a display panel provided by an embodiment of the present application.
  • 17 is a schematic diagram of a second planar structure of the second semiconductor layer and the third semiconductor layer of the display panel provided by the embodiment of the present application;
  • FIG. 18 is a schematic diagram of a second planar structure of the third metal layer of the display panel provided by the embodiment of the present application.
  • the display panel includes a substrate 10, a first semiconductor layer 20, a first metal layer 30, and a second metal layer 40 stacked from bottom to top , the second semiconductor layer 51 , the third metal layer 60 , the fourth metal layer 70 and the fifth metal layer 80 .
  • the first metal layer is patterned to form the first gate 31 and the third capacitor electrode (not shown in the figure), the second metal layer is patterned to form the fourth capacitor electrode 41, the The third metal layer is patterned to form the third gate 61, the fourth metal layer 70 is patterned to form the first source 71 and the first drain 72 electrically connected to the first semiconductor layer 20, and A second source 73 and a second drain 74 electrically connected to the second semiconductor layer 51 , respectively.
  • the third capacitor electrode and the fourth capacitor electrode 41 form a storage capacitor Cst.
  • the thin film transistors in the pixel circuit are usually formed by Low Temperature Poly-Silicon (LTPS) process, and the leakage current of the thin film transistors formed by the LTPS process is relatively large, so it is easy to appear flickering and power failure when low-frequency display is used. High power consumption and other issues affect the display quality.
  • LTPS Low Temperature Poly-Silicon
  • an embodiment of the present application provides a display panel, which is used to reduce the power consumption of the pixel driving circuit, so as to stabilize the display effect of the display panel.
  • Figure 4 is a schematic diagram of the first structure of the display panel provided by the embodiment of the present application
  • Figure 6 is the first structure of the display panel provided by the embodiment of the present application
  • Figure 8 is a schematic view of the first planar structure of the second metal layer of the display panel provided by the embodiment of the present application
  • Figure 10 is a schematic view of the third layer of the display panel provided by the embodiment of the present application Schematic diagram of the first planar structure of the metal layer.
  • This embodiment provides a display panel, the display panel includes a substrate 10; and a pixel driving circuit layer (not marked in the figure), including a plurality of pixel driving circuits (not marked in the figure), each of the pixel driving circuits It includes a first capacitor Cboost and a second capacitor Cst.
  • the pixel driving circuit layer includes: a first semiconductor layer 20 , a first metal layer 30 , a second metal layer 40 , a second semiconductor layer 51 , and a third metal layer 60 stacked on the substrate 10 in sequence. and the fourth metal layer 70, wherein the fourth metal layer 70 includes a first source 71, a first drain 72, a second source 73, and a second drain 74, the first source 71 and the The first drain 72 is electrically connected to the first semiconductor layer 20, the second source 73 and the second drain 74 are electrically connected to the second semiconductor layer 51, and the second semiconductor layer 51 is an oxide semiconductor layer.
  • the first metal layer 30 includes the first capacitor electrode 32
  • the second metal layer 40 includes the second capacitor electrode 42
  • the second metal layer 40 includes the first capacitor electrode 32
  • the third metal layer Layer 60 includes a second capacitor electrode 42 ; the first capacitor electrode 32 and the second capacitor electrode 42 form a first capacitor Cboost, and the second capacitor electrode 42 is electrically connected to the fourth metal layer 70 .
  • the first metal layer 30 includes a first capacitor electrode 32
  • the second metal layer 40 includes a second capacitor electrode 42
  • the first capacitor electrode 32 and the second capacitor The electrode 42 forms the first capacitor Cboost
  • the second electrode layer 43 is electrically connected to the second drain 74 .
  • the first metal layer 30 also includes a first grid 31 and a third capacitor electrode (not shown in the figure), the first The second metal layer 40 also includes a fourth capacitor electrode 41, and the third metal layer 60 also includes a third grid 61, wherein the third capacitor electrode and the fourth capacitor electrode 41 form the second capacitor Cst .
  • the first gate 31 and the third capacitor electrode may be formed by the same metal block, and they are located in different regions of the same metal block.
  • the display panel further includes a first interlayer dielectric layer 110 located between the second metal layer 40 and the second semiconductor layer 51, a first interlayer dielectric layer 110 located between the second semiconductor layer 51 and the third metal layer 60 The third insulating layer 120 between them and the second interlayer dielectric layer 130 between the third metal layer 60 and the fourth metal layer 70 .
  • the display panel includes the substrate 10, the first semiconductor layer 20, the first insulating layer 90, the first gate 31, the second insulating layer 100, and the fourth capacitor stacked from bottom to top. electrode 41, the first interlayer dielectric layer 110, the second semiconductor layer 51, the third insulating layer 120, the third gate 61, the second interlayer dielectric layer 130, the fourth metal layer 70, passivation layer 140, the first planarization layer 150 and the fifth metal layer 80.
  • the substrate 10 may include a rigid substrate or a flexible substrate.
  • the material may be metal or glass.
  • materials can include acrylic, methacrylic, polyisoprene, vinyl, epoxy, polyurethane, cellulose, silicone, polyimide, poly at least one of amide-based resins. The present application does not limit the material of the substrate 10 .
  • the substrate 10 is a flexible substrate, including a stacked first flexible substrate, a barrier layer, a second flexible substrate and a buffer layer, wherein the materials of the first flexible substrate and the second flexible substrate can be Including at least one of polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyarylate and polyethersulfone, the material of the barrier layer is usually silicon oxide (SiOx), the buffer layer can include inorganic materials, such as at least one of silicon nitride or silicon oxide, used to prevent external impurities below the substrate 10 from penetrating into the transistors on the upper layer, and improve the relationship between the substrate 10 and the upper film layer. the bonding strength between them.
  • the materials of the first flexible substrate and the second flexible substrate can be Including at least one of polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyarylate and polyethersulfone
  • the material of the barrier layer is usually silicon oxide (SiOx)
  • the material of the first semiconductor layer 20 includes but not limited to polysilicon
  • the material of the second semiconductor layer 51 includes but not limited to oxide
  • the first semiconductor layer 20 forms the low temperature polysilicon transistor.
  • the polysilicon active layer, the second semiconductor layer 51 forms the oxide active layer of each oxide transistor, and the first semiconductor layer 20 and the second semiconductor layer 51 are electrically connected through the second source 73 .
  • the materials of the first metal layer 30, the second metal layer 40 and the third metal layer 60 may include molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta) and tungsten (W) at least one metal.
  • the first grid 31 and the first capacitor electrode 32 are located in the same film layer and can be produced in the same process.
  • the fourth capacitor electrode 41 and the second capacitor electrode 42 are located in the same film layer and can also be made in the same process. Manufactured in the same process, both can minimize the impact on the thickness of the display panel.
  • the materials of the first insulating layer 90, the second insulating layer 100 and the third insulating layer 120 include but not limited to silicon oxide; the first interlayer dielectric layer 110 and the The material of the second interlayer dielectric layer 130 includes at least one of silicon nitride and silicon oxide.
  • the display panel may further include a first planar layer 150 , a second planar layer 160 , an anode 180 , a pixel definition layer 170 , a light-emitting functional layer 190 and supporting spacer columns 200 located above the fifth metal layer 80 .
  • the display panel is provided with a The first via hole 1 of the interlayer dielectric layer 110 ; wherein, the fourth metal layer 70 is electrically connected to the second capacitor electrode 42 through the first via hole 1 .
  • the second source 73 or the second drain 74 is electrically connected to the second electrode layer 43 through the first via hole 1. It can be understood that, This embodiment does not make further limitations on this.
  • the display panel further includes a third semiconductor layer 52 on the same layer as the second semiconductor layer 51 and arranged at intervals, the third semiconductor layer 52 and the fourth metal Layer 70 is electrically connected; wherein, the projection of the third semiconductor layer 52 on the substrate 10 is at least partially in the overlapping area of the first capacitance electrode 32 and the second capacitance electrode 42 on the substrate 10 The projections on the overlap.
  • the third semiconductor layer 52 is electrically connected to the second semiconductor layer 51 through the second source 73 or the second drain 74, it can be understood that this embodiment does not further limit.
  • the material of the third semiconductor layer 52 includes oxide, and the third semiconductor layer 52 and the second semiconductor layer 51 are formed of the same oxide.
  • the display panel is provided with a first Two via holes 2 ; wherein, the fourth metal layer 70 is electrically connected to the third semiconductor layer 52 through the second via hole 2 .
  • the second source 73 or the second drain 74 is electrically connected to the third semiconductor layer 52 through the second via hole 2. It can be understood that, This embodiment does not make further limitations on this.
  • the third semiconductor layer 52 is prepared on the second electrode layer 43, so that the second electrode layer 43 constituting the first capacitor Cboost has a three-dimensional structure, so that the capacitor structure can be implemented on the same chip
  • the surface area of the capacitor is increased, thereby increasing the capacitance value of the first capacitor Cboos, that is, a capacitor structure with a small size and a large capacity is provided.
  • the display panel further includes a plurality of light emitting devices D1 arranged in an array and a pixel driving circuit for driving the light emitting device D1 to emit light.
  • the pixel driving circuit includes:
  • the gate of the driving transistor T1 is connected to the first node Q(N)(M), the first terminal of the driving transistor T1 is connected to the third node B, and the second terminal of the driving transistor T1 is connected to The second node A.
  • the gate of the switch transistor T2 is connected to the second scanning signal Scan2, the first end of the switch transistor T2 is connected to the data signal Data, and the second end of the switch transistor T2 is connected to the second node A.
  • the gate of the compensation transistor T3 is connected to the second scanning signal Scan2, the first terminal of the compensation transistor T3 is connected to the third node B, and the second terminal of the compensation transistor T3 is connected to the first node Q(N) ( M).
  • the gate of the first initialization transistor T4 is connected to the first scan signal Scan1, the first terminal of the first initialization transistor T4 is connected to the second initialization signal VI2, and the second terminal of the first initialization transistor T4 is connected to the first node Q(N)(M).
  • the gate of the first light emission control transistor T5 is connected to the light emission control signal EM, the first end of the first light emission control transistor T5 is connected to the fifth node D, and the second end of the first light emission control transistor T5 is connected to The second node A, the first light emission control transistor T5 is connected to the high potential signal line Vdd of the power supply through the fifth node D.
  • the gate of the second light emission control transistor T6 is connected to the light emission control signal EM, the first end of the second light emission control transistor T6 is connected to the third node B, and the second end of the second light emission control transistor T6 is connected to The fourth node C.
  • the gate of the second initialization transistor T7 is connected to the second scanning signal Scan2, the first end of the second initialization transistor T7 is connected to the fourth node C, and the second end of the second initialization transistor T7 is connected to the first initialization Signal VI.
  • the first capacitor electrode 32 of the first capacitor Cboost is connected to the gate of the switching transistor T2, and the second capacitor electrode 42 of the first capacitor Cboost is connected to the first node Q(N)(M).
  • the third capacitor electrode of the second capacitor Cst is connected to the fifth node D
  • the fourth capacitor electrode 41 of the second capacitor Cst is connected to the first node Q(N)(M)
  • the second capacitor Cst passes through
  • the fifth node D is connected to the power high potential signal line Vdd.
  • the compensation transistor T3, the first initialization transistor T4, and the second initialization transistor T7 are oxide transistors
  • the switching transistor T2, the driving transistor T1, and the second initialization transistor T2 are oxide transistors.
  • the first light emission control transistor T5 and the second light emission control transistor T6 are low temperature polysilicon transistors.
  • the compensation transistor T3 includes the fourth capacitor stacked on the substrate 10 electrode 41, the first interlayer dielectric layer 110, the second semiconductor layer 51, the third insulating layer 120, the third gate 61, the second interlayer dielectric layer 130 and the first Four metal layers 70; the display panel is also provided with a third via hole 3 passing through the second interlayer dielectric layer 130 and the third insulating layer 120, and the fourth metal layer 70 passes through the
  • the third via hole 3 is electrically connected to the second semiconductor layer 51; wherein, the distance from the first via hole 1 to the second semiconductor layer 51 of the compensation transistor T3 is the same as the distance from the third via hole 3 to the second semiconductor layer 51.
  • the distance between the second semiconductor layer 51 of the compensation transistor T3 is equal, so that the electrical performance of the compensation transistor T3 can be significantly improved, and when the compensation transistor T3 is turned on, it can work more stably.
  • the second semiconductor layer 51 is electrically connected, and the second semiconductor layer 51 is an oxide semiconductor layer; wherein, the first metal layer 30 includes a first capacitor electrode 32, and the second metal layer 40 includes a second capacitor electrode An electrode 42; the first capacitance electrode 32 and the second capacitance electrode 42 form a first capacitance Cboost, and the second capacitance electrode 42 is electrically connected to the fourth metal layer 70, so that the display panel realizes low-frequency display, And it has a stable display effect; at the same time, the power consumption of the pixel driving circuit is reduced, and the problem of poor dark state effect of the display panel under high-frequency display is avoided.
  • FIG. 13 is a schematic diagram of the second structure of the display panel provided by the embodiment of the present application.
  • the second structural schematic diagram of the display panel is similar/identical to the first structural schematic diagram of the display panel provided in the above-mentioned first embodiment, please refer to the above-mentioned first embodiment about the display
  • the description of the first structural diagram of the panel will not be repeated here. The only difference between the two is:
  • the second metal layer 40 includes a first capacitor electrode 32
  • the third metal layer 60 includes a second capacitor electrode 42; the first capacitor electrode 32 and the second capacitor electrode 42 form The first capacitor Cboost, the second capacitor electrode 42 is electrically connected to the fourth metal layer 70 .
  • the second electrode layer 43 is electrically connected to the second drain 74 .
  • the first metal layer 30 further includes a first gate 31
  • the second metal layer 40 further includes a fourth capacitor electrode 41
  • the third metal layer 60 further includes a third gate 61 .
  • first capacitive electrodes 32 and second electrode layers 43 are provided, the first capacitive electrodes 32 and the fourth capacitive electrodes 41 are arranged on the same layer, and the second The electrode layer 43 is set on the same layer as the third grid 61, and the first capacitance electrode 32 and the second electrode layer 43 form the first capacitance Cboost, so that the display panel can realize low-frequency display and has a stable display effect.
  • the display panel is provided with a first via hole 1 passing through the second interlayer dielectric layer 130; wherein, the fourth metal layer 70 It is electrically connected to the second capacitor electrode 42 through the first via hole 1 .
  • the second source 73 or the second drain 74 is electrically connected to the second electrode layer 43 through the first via hole 1. It can be understood that, This embodiment does not make further limitations on this.
  • the The first capacitor electrode 32 has a three-dimensional structure, so that the capacitor structure can increase the capacitor surface area under the same chip area, thereby increasing the capacitance value of the first capacitor Cboost, that is, providing a capacitor structure with small size and large capacity.
  • the display panel is provided with a second via hole 2 passing through the second interlayer dielectric layer 130; wherein, the fourth The metal layer 70 is electrically connected to the third semiconductor layer 52 through the second via hole 2 .
  • the second source 73 or the second drain 74 is electrically connected to the third semiconductor layer 52 through the second via hole 2. It can be understood that, This embodiment does not make further limitations on this.
  • the first metal layer 30 further includes a first grid 31 and a third capacitor electrode (not shown in the figure), and the first The second metal layer 40 also includes a fourth capacitor electrode 41, and the third metal layer 60 also includes a third grid 61, wherein the third capacitor electrode and the fourth capacitor electrode 41 form the second capacitor Cst .
  • the first gate 31 and the third capacitor electrode may be formed by the same metal block, and they are located in different regions of the same metal block.
  • an embodiment of the present application provides a display panel, the display panel includes a plurality of light emitting devices arranged in an array and a pixel driving circuit that drives the light emitting device D1 to emit light, and the pixel driving circuit includes:
  • the first initialization transistor T4 is configured to input the second initialization signal VI2 to the first node Q(N)(M) under the control of the first scan signal Scan1 .
  • the switch transistor T2 is used to input the data signal Data to the second node A under the control of the second scanning signal Scan2.
  • the driving transistor T1 is used to drive the light emitting device D1 to emit light under the control of the potentials of the first node Q(N)(M) and the second node A.
  • the compensation transistor T3 is connected to the driving transistor T1 through the first node Q(N)(M) and the third node B, and is used to compensate the threshold voltage of the driving transistor T1 under the control of the third scanning signal Scan2;
  • the second initialization transistor T7 is configured to input the first initialization signal VI1 to the anode of the light emitting device D1 under the control of the second scanning signal Scan2.
  • the first light emitting control transistor T5 is connected to the driving transistor T1 through the second node A, and is used for turning on the current flowing from the high potential signal line of the power supply to the driving transistor T1 under the control of the light emitting control signal EM.
  • the second light emitting control transistor T6 is connected to the driving transistor T1 through the third node B, and is used to turn on the current flowing from the driving transistor T1 to the anode of the light emitting device D1 under the control of the light emitting control signal EM;
  • the first capacitor Cboost is coupled between the first node Q(N)(M) and the gate of the switching transistor T2, and is used for lowering the potential of the first node Q(N)(M).
  • the second capacitor Cst is connected to the driving transistor T1 through the first node Q(N)(M), and connected to the power high potential signal line Vdd through the fourth node C, for storing data signals.
  • the first capacitor Cboost includes a first capacitor electrode 32 and a second capacitor electrode 42 oppositely arranged, the first capacitor electrode 32 is electrically connected to the gate of the switching transistor T2, and the second capacitor electrode 42 is electrically connected to the first initialization transistor T4 through the first node Q(N)(M), wherein the switch transistor T2 is a low temperature polysilicon transistor, and the first initialization transistor T4 is an oxide transistor.
  • the gate of the driving transistor T1 is connected to the first node Q(N)(M), the first end of the driving transistor T1 is connected to the third node B, and the first terminal of the driving transistor T1 The two terminals are connected to the second node A.
  • the gate of the switch transistor T2 is connected to the second scanning signal Scan2, the first end of the switch transistor T2 is connected to the data signal Data, and the second end of the switch transistor T2 is connected to the second node A.
  • the gate of the compensation transistor T3 is connected to the second scanning signal Scan2, the first terminal of the compensation transistor T3 is connected to the third node B, and the second terminal of the compensation transistor T3 is connected to the first node Q(N) ( M).
  • the gate of the first initialization transistor T4 is connected to the first scan signal Scan1, the first terminal of the first initialization transistor T4 is connected to the second initialization signal VI2, and the second terminal of the first initialization transistor T4 is connected to the first node Q(N)(M).
  • the gate of the first light emission control transistor T5 is connected to the light emission control signal EM, the first end of the first light emission control transistor T5 is connected to the fifth node D, and the second end of the first light emission control transistor T5 is connected to The second node A, the first light emission control transistor T5 is connected to the high potential signal line Vdd of the power supply through the fifth node D.
  • the gate of the second light emission control transistor T6 is connected to the light emission control signal EM, the first end of the second light emission control transistor T6 is connected to the third node B, and the second end of the second light emission control transistor T6 is connected to The fourth node C.
  • the gate of the second initialization transistor T7 is connected to the second scanning signal Scan2, the first end of the second initialization transistor T7 is connected to the fourth node C, and the second end of the second initialization transistor T7 is connected to the first initialization Signal VI.
  • the first capacitor electrode 32 of the first capacitor Cboost is connected to the gate of the switching transistor T2, and the second capacitor electrode 42 of the first capacitor Cboost is connected to the first node Q(N)(M).
  • the third capacitor electrode of the second capacitor Cst is connected to the fifth node D
  • the fourth capacitor electrode 41 of the second capacitor Cst is connected to the first node Q(N)(M)
  • the second capacitor Cst passes through
  • the fifth node D is connected to the power high potential signal line Vdd.
  • the compensation transistor T3, the first initialization transistor T4, and the second initialization transistor T7 are oxide transistors
  • the switching transistor T2, the driving transistor T1, and the second initialization transistor T2 are oxide transistors.
  • the first light emission control transistor T5 and the second light emission control transistor T6 are low temperature polysilicon transistors.
  • this embodiment provides a display panel as described in any one of the foregoing embodiments, which has the same technical effect as that of the foregoing display panel, which will not be repeated here.
  • the present application provides a display panel.
  • the display panel includes a substrate; and a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, and a fourth metal layer that are sequentially stacked on the substrate, wherein , the fourth metal layer includes a first source, a first drain, a second source and a second drain, the first source and the first drain are electrically connected to the first semiconductor layer , the second source and the second drain are electrically connected to the second semiconductor layer, the second semiconductor layer is an oxide semiconductor layer; wherein the first metal layer includes a first capacitor electrode, The second metal layer includes a second capacitor electrode, the first capacitor electrode and the second capacitor electrode form a first capacitor, and the second capacitor electrode is electrically connected to the fourth metal layer, so that low frequency Display, while reducing the power consumption of the pixel driving circuit.

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Abstract

一种显示面板，包括：衬底（10）；像素驱动电路层，包括多个像素驱动电路，每个像素驱动电路包括第一电容（Cboost）和第二电容（Cst）；其中，第一电容（Cboost）和第二电容（Cst）均有一个电容电极设置在同一金属层，从而可以实现低频显示，同时降低像素驱动电路的功耗。

Description

一种显示面板 技术领域
本申请涉及显示领域，特别涉及一种显示面板。
 背景技术
随着显示技术的发展，有机发光(OrganicLightEmittingDiode，OLED)显示装置得到越来越广泛的应用，与液晶显示器相比，OLED显示器具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点，目前，在手机、PDA、数码相机等平板显示领域，OLED显示器已经开始取代传统的液晶显示屏(LiquidCrystalDisplay，LCD)。其中，像素电路设计是OLED显示器核心技术内容，具有重要的研究意义。
在现有的7T1C电路结构中，由于像素电路中的薄膜晶体管通常由低温多晶硅(LowTemperaturePoly-silicon，LTPS)工艺形成，而采用LTPS工艺形成的薄膜晶体管的漏电流较大，因此在采用低频显示时易出现闪烁、功耗高等问题，影响显示品质。
 技术问题
本申请实施例提供一种显示面板，用以降低像素驱动电路的功耗。
 技术解决方案
为实现上述功能，本申请提供的技术方案如下：
本申请提供了一种显示面板，包括：
衬底；以及
像素驱动电路层，包括多个像素驱动电路，每个所述像素驱动电路包括第一电容和第二电容；
其中，所述像素驱动电路层包括：依次层叠设置在所述衬底上的第一半导
体层、第一金属层、第二金属层、第二半导体层、第三金属层以及第四金属层，其中，所述第四金属层包括第一源极、第一漏极、第二源极以及第二漏极，所述第一源极和所述第一漏极与所述第一半导体层电连接，所述第二源极和所述第二漏极与所述第二半导体层电连接，所述第二半导体层为氧化物半导体层；
其中，所述第一电容和所述第二电容均有一个电容电极设置在所述第二金属层。
在本申请所提供的显示面板中，所述第一金属层包括第一电容电极，所述第二金属层包括第二电容电极，或所述第二金属层包括第一电容电极，所述第三金属层包括第二电容电极；所述第一电容电极与所述第二电容电极形成所述第一电容，所述第二电容电极与所述第四金属层电连接。
在本申请所提供的显示面板中，所述显示面板还包括位于所述第二金属层和所述第二半导体层之间的第一层间介质层、位于所述第二半导体层和所述第三金属层之间的第三绝缘层以及位于所述第三金属层和所述第四金属层之间的第二层间介质层。
在本申请所提供的显示面板中，所述显示面板设置有穿过所述第二层间介质层、所述第三绝缘层以及所述第一层间介质层的第一过孔；
其中，所述第四金属层通过所述第一过孔与所述第二电容电极电连接。
在本申请所提供的显示面板中，所述显示面板设置有穿过所述第二层间介质层的第一过孔；
其中，所述第四金属层通过所述第一过孔与所述第二电容电极电连接。
在本申请所提供的显示面板中，所述显示面板还包括位于所述第一半导体层和所述第一金属层之间的第一绝缘层、及位于所述第一金属层和所述第二金属层之间的第二绝缘层；
其中，所述第一金属层还包括第一栅极和第三电容电极，所述第二金属层还包括第四电容电极，所述第三金属层还包括第三栅极，其中，所述第三电容电极和所述第四电容电极形成所述第二电容。
在本申请所提供的显示面板中，所述显示面板还包括与所述第二半导体层同层且间隔设置的第三半导体层，所述第三半导体层与所述第四金属层电连接；
其中，所述第三半导体层在所述衬底上的投影至少部分与所述第一电容电极和所述第二电容电极的重叠区域在所述衬底上的投影重叠。
在本申请所提供的显示面板中，所述第一半导体层为多晶硅半导体层，所述第三半导体层为氧化物半导体层。
在本申请所提供的显示面板中，所述显示面板还包括阵列设置的多个发光器件和驱动所述发光器件发光的像素驱动电路，所述像素驱动电路包括第一初始化晶体管、开关晶体管、驱动晶体管、补偿晶体管、第二初始化晶体管、第一发光控制晶体管、第二发光控制晶体管、所述第一电容以及所述第二电容；
其中，所述驱动晶体管的栅极连接于第一节点，所述驱动晶体管的第一端连接于第三节点，所述驱动晶体管的第二端连接于第二节点；
所述开关晶体管的栅极连接第二扫描信号，所述开关晶体管的第一端连接数据信号，所述开关晶体管的第二端连接于第二节点；
所述补偿晶体管的栅极连接第二扫描信号，所述补偿晶体管的第一端连接
于第三节点，所述补偿晶体管的第二端连接于第一节点;
所述第一初始化晶体管的栅连接第一扫描信号，所述第一初始化晶体管的第一端连接第二初始化信号，所述第一初始化晶体管的第二端连接于第一节点;
所述第一发光控制晶体管的栅极连接发光控制信号，所述第一发光控制晶体管的第一端连接于第五节点，所述第一发光控制晶体管的第二端连接于第二节点，所述第一发光控制晶体管通过第五节点与电源高电位信号线相连；
所述第二发光控制晶体管的栅极连接发光控制信号，所述第二发光控制晶体管的第一端连接于第三节点，所述第二发光控制晶体管的第二端连接于第四节点；
所述第二初始化晶体管的栅连接第二扫描信号，所述第二初始化晶体管的第一端连接于第四节点，所述第二初始化晶体管的第二端连接于第一初始化信号；
所述第一电容的第一电容电极连接于所述开关晶体管的栅极，所述第一电容的第二电容电极连接于第一节点；
所述第二电容的第三电容电极连接于第五节点，所述第二电容的第四电容电极连接于第一节点，所述第二电容通过第五节点与电源高电位信号线相连。
在本申请所提供的显示面板中，所述补偿晶体管、所述第一初始化晶体管和所述第二初始化晶体管为氧化物晶体管，所述开关晶体管、所述驱动晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管为低温多晶硅晶体管。
本申请提供一种显示面板，所述显示面板包括阵列设置的多个发光器件和驱动所述发光器件发光的像素驱动电路，所述像素驱动电路包括：
第一初始化晶体管，用于在第一扫描信号的控制下，向第一节点输入第二初始化信号；
开关晶体管，用于在第二扫描信号的控制下，向第二节点输入数据信号；
驱动晶体管，用于在第一节点和第二节点电位的控制下，驱动所述发光器件发光；
补偿晶体管，通过第一节点和第三节点与所述驱动晶体管相连，用于在第三扫描信号的控制下，补偿所述驱动晶体管的阈值电压；
第二初始化晶体管，用于在第二扫描信号的控制下，向所述发光器件阳极输入第一初始化信号；
第一发光控制晶体管，通过第二节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通电源高电位信号线流向所述驱动晶体管的电流；
第二发光控制晶体管，通过第三节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通所述驱动晶体管流向所述发光器件阳极的电流；
第一电容，耦接于第一节点和所述开关晶体管的栅极之间，用于降低第一节点的电位；
第二电容，通过第一节点与所述驱动晶体管相连，通过第四节点与电源高电位信号线相连，用于存储数据信号；
其中，所述第一电容包括相对设置的第一电容电极和第二电容电极，所述第一电容电极与所述开关晶体管的栅极电性连接，所述第二电容电极通过第一节点与所述第一初始化晶体管电性连接，其中，所述开关晶体管为低温多晶硅晶体管，所述第一初始化晶体管为氧化物晶体管。
在本申请所提供的显示面板中，所述驱动晶体管的栅极连接于第一节点，所述驱动晶体管的第一端连接于第三节点，所述驱动晶体管的第二端连接于第二节点；
所述开关晶体管的栅极连接第二扫描信号，所述开关晶体管的第一端连接数据信号，所述开关晶体管的第二端连接于第二节点；
所述补偿晶体管的栅极连接第二扫描信号，所述补偿晶体管的第一端连接
于第三节点，所述补偿晶体管的第二端连接于第一节点;
所述第一初始化晶体管的栅连接第一扫描信号，所述第一初始化晶体管的第一端连接第二初始化信号，所述第一初始化晶体管的第二端连接于第一节点;
所述第一发光控制晶体管的栅极连接发光控制信号，所述第一发光控制晶体管的第一端连接于第五节点，所述第一发光控制晶体管的第二端连接于第二节点，所述第一发光控制晶体管通过第五节点与电源高电位信号线相连；
所述第二发光控制晶体管的栅极连接发光控制信号，所述第二发光控制晶体管的第一端连接于第三节点，所述第二发光控制晶体管的第二端连接于第四节点；
所述第二初始化晶体管的栅连接第二扫描信号，所述第二初始化晶体管的第一端连接于第四节点，所述第二初始化晶体管的第二端连接于第一初始化信号；
所述第一电容的第一电容电极连接于所述开关晶体管的栅极，所述第一电容的第二电容电极连接于第一节点；
所述第二电容的第三电容电极连接于第五节点，所述第二电容的第四电容电极连接于第一节点，所述第二电容通过第五节点与电源高电位信号线相连。
在本申请所提供的显示面板中，所述补偿晶体管和所述第二初始化晶体管为氧化物晶体管，所述驱动晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管为低温多晶硅晶体管。
在本申请所提供的显示面板中，所述显示面板还包括：
衬底；以及
像素驱动电路层，包括多个像素驱动电路，每个所述像素驱动电路包括第一电容和第二电容；
其中，所述像素驱动电路层包括：依次层叠设置在所述衬底上的第一半导
体层、第一金属层、第二金属层、第二半导体层、第三金属层以及第四金属层，其中，所述第四金属层包括第一源极、第一漏极、第二源极以及第二漏极，所述第一源极和所述第一漏极与所述第一半导体层电连接，所述第二源极和所述第二漏极与所述第二半导体层电连接，所述第二半导体层为氧化物半导体层；
其中，所述第一电容和所述第二电容均有一个电容电极设置在所述第二金属层。
在本申请所提供的显示面板中，所述第一金属层包括第一电容电极，所述第二金属层包括第二电容电极，或所述第二金属层包括第一电容电极，所述第三金属层包括第二电容电极；所述第一电容电极与所述第二电容电极形成所述第一电容，所述第二电容电极与所述第四金属层电连接。
在本申请所提供的显示面板中，所述显示面板还包括位于所述第二金属层和所述第二半导体层之间的第一层间介质层、位于所述第二半导体层和所述第三金属层之间的第三绝缘层以及位于所述第三金属层和所述第四金属层之间的第二层间介质层。
在本申请所提供的显示面板中，所述显示面板设置有穿过所述第二层间介质层、所述第三绝缘层以及所述第一层间介质层的第一过孔；
其中，所述第四金属层通过所述第一过孔与所述第二电容电极电连接。
在本申请所提供的显示面板中，所述显示面板设置有穿过所述第二层间介质层的第一过孔；
其中，所述第四金属层通过所述第一过孔与所述第二电容电极电连接。
在本申请所提供的显示面板中，所述显示面板还包括位于所述第一半导体层和所述第一金属层之间的第二绝缘层、及位于所述第一金属层和所述第二金属层之间的第三绝缘层；
其中，所述第一金属层还包括第一栅极和第三电容电极，所述第二金属层还包括第四电容电极，所述第三金属层还包括第三栅极，其中，所述第三电容电极和所述第四电容电极形成所述第二电容。
在本申请所提供的显示面板中，所述显示面板还包括与所述第二半导体层同层且间隔设置的第三半导体层，所述第三半导体层与所述第四金属层电连接；
其中，所述第三半导体层在所述衬底上的投影至少部分与所述第一电容电极和所述第二电容电极的重叠区域在所述衬底上的投影重叠。
 有益效果
本申请的有益效果：本申请提出一种7T2C电路结构，通过在衬底上依次层叠设置第一半导体层、第一金属层、第二金属层、第二半导体层、第三金属层以及第四金属层，其中，所述第四金属层包括第一源极、第一漏极、第二源极以及第二漏极，所述第一源极和所述第一漏极与所述第一半导体层电连接，所述第二源极和所述第二漏极与所述第二半导体层电连接，所述第二半导体层为氧化物半导体层；其中，所述第一金属层包括第一电容电极，所述第二金属层包括第二电容电极，或所述第二金属层包括第一电容电极，所述第三金属层包括第二电容电极；所述第一电容电极与所述第二电容电极形成第一电容，所述第二电容电极与所述第四金属层电连接，从而使显示面板实现低频显示，且具有稳定的显示效果；同时，降低所述像素驱动电路的功耗，避免高频显示下显示面板暗态效果不佳的问题。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为现有技术中显示面板的像素驱动电路的结构示意图；
图2为现有技术中显示面板的结构示意图；
图3为现有技术中显示面板的各膜层的平面叠加结构示意图；
图4为本申请实施例所提供的显示面板的第一种结构示意图；
图5为本申请实施例所提供的显示面板的像素驱动电路的结构示意图；
图6为本申请实施例所提供的显示面板的第一种各膜层的平面叠加结构示意图；
图7为本申请实施例所提供的显示面板的第一金属层的第一种平面结构示意图；
图8为本申请实施例所提供的显示面板的第二金属层的第一种平面结构示意图；
图9为本申请实施例所提供的显示面板的第二半导体层和第三半导体层的第一种平面结构示意图；
图10为本申请实施例所提供的显示面板的第三金属层的第一种平面结构示意图；
图11为本申请实施例所提供的显示面板的第四金属层的第一种平面结构示意图；
图12为本申请实施例所提供的显示面板的第五金属层的第一种平面结构示意图；
图13为本申请实施例所提供的显示面板的第二种结构示意图；
图14为本申请实施例所提供的显示面板的第二种各膜层的平面叠加结构示意图；
图15为本申请实施例所提供的显示面板的第一金属层的第二种平面结构示意图；
图16为本申请实施例所提供的显示面板的第二金属层的第二种平面结构示意图；
图17为本申请实施例所提供的显示面板的第二半导体层和第三半导体层的第二种平面结构示意图；
图18为本申请实施例所提供的显示面板的第三金属层的第二种平面结构示意图。
 本发明的实施方式
本申请提供一种显示面板，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
请结合图1-图3，在现有的7T1C电路结构中，所述显示面板包括自下而上层叠设置的衬底10、第一半导体层20、第一金属层30、第二金属层40、第二半导体层51、第三金属层60、第四金属层70以及第五金属层80。
其中，所述第一金属层图案化形成所述第一栅极31和第三电容电极（图中未画出），所述第二金属层图案化形成所述第四电容电极41，所述第三金属层图案化形成所述第三栅极61，所述第四金属层70图案化形成分别与所述第一半导体层20电连接的第一源极71和第一漏极72、及分别与所述第二半导体层51电连接的第二源极73和第二漏极74。
其中，所述第三电容电极和所述第四电容电极41形成存储电容Cst。
在现有技术中，像素电路中的薄膜晶体管通常低温多晶硅(LowTemperaturePoly-Silicon，LTPS)工艺形成，而采用LTPS工艺形成的薄膜晶体管的漏电流较大，因此在采用低频显示时易出现闪烁、功耗高等问题，影响显示品质。基于此，本申请实施例提供了一种显示面板，用以降低像素驱动电路的功耗，从而稳定显示面板的显示效果。
现结合具体实施例对本申请的技术方案进行描述。
实施例一
请结合图4、图6、图8以及图10，其中，图4为本申请实施例所提供的显示面板的第一种结构示意图；图6为本申请实施例所提供的显示面板的第一种各膜层的平面叠加结构示意图；图8为本申请实施例所提供的显示面板的第二金属层的第一种平面结构示意图；图10为本申请实施例所提供的显示面板的第三金属层的第一种平面结构示意图。
本实施例提供一种显示面板，所述显示面板包括衬底10；以及像素驱动电路层（图中未标记），包括多个像素驱动电路（图中未标记），每个所述像素驱动电路包括第一电容Cboost和第二电容Cst。
其中，所述像素驱动电路层包括：依次层叠设置在所述衬底10上的第一半导体层20、第一金属层30、第二金属层40、第二半导体层51、第三金属层60以及第四金属层70，其中，所述第四金属层70包括第一源极71、第一漏极72、第二源极73以及第二漏极74，所述第一源极71和所述第一漏极72与所述第一半导体层20电连接，所述第二源极73和所述第二漏极74与所述第二半导体层51电连接，所述第二半导体层51为氧化物半导体层。
其中，所述第一金属层30包括第一电容电极32，所述第二金属层40包括第二电容电极42，或所述第二金属层40包括第一电容电极32，所述第三金属层60包括第二电容电极42；所述第一电容电极32和所述第二电容电极42形成第一电容Cboost，所述第二电容电极42与所述第四金属层70电连接。
进一步地，在本实施例中，所述第一金属层30包括第一电容电极32，所述第二金属层40包括第二电容电极42，所述第一电容电极32和所述第二电容电极42形成所述第一电容Cboost，所述第二电极层43与所述第二漏极74电性连接。
可以理解的是，所述第二电极层43与所述第二漏极74电性连接仅用于举例说明，本实施例对此不做限制。
请结合图4、图6、图7以及图8，在本实施例中，所述第一金属层30还包括第一栅极31和第三电容电极（图中未标出），所述第二金属层40还包括第四电容电极41，所述第三金属层60还包括第三栅极61，其中，所述第三电容电极和所述第四电容电极41形成所述第二电容Cst。
需要说明的是，在本实施例中，所述第一栅极31和所述第三电容电极可以由同一金属块形成，它们处于同一金属块的不同区域。
所述显示面板还包括位于所述第二金属层40和所述第二半导体层51之间的第一层间介质层110、位于所述第二半导体层51和所述第三金属层60之间的第三绝缘层120以及位于所述第三金属层60和所述第四金属层70之间的第二层间介质层130。
具体地，所述显示面板包括自下而上层叠设置的所述衬底10、所述第一半导体层20、第一绝缘层90、第一栅极31、第二绝缘层100、第四电容电极41、第一层间介质层110、所述第二半导体层51、所述第三绝缘层120、第三栅极61、第二层间介质层130、所述第四金属层70、钝化层140、第一平坦层150以及所述第五金属层80。
需要说明的是，在本实施例中，所述衬底10可以包括刚性衬底或柔性衬底，当衬底10为刚性衬底时，材料可以是金属或玻璃，当衬底10为柔性衬底时，材料可以包括丙烯酸树脂、甲基丙烯酸树脂、聚异戊二烯、乙烯基树脂、环氧基树脂、聚氨酯基树脂、纤维素树脂、硅氧烷树脂、聚酰亚胺基树脂、聚酰胺基树脂中的至少一种。本申请对衬底10的材料不做限制。
进一步地，所述衬底10为柔性衬底，包括层叠设置的第一柔性衬底、阻隔层、第二柔性衬底以及缓冲层，其中第一柔性衬底和第二柔性衬底的材料可以包括聚酰亚胺、聚对苯二甲酸乙二醇酯、聚萘二甲酸乙二醇酯、聚碳酸酯、聚芳酯以及聚醚砜中的至少一种，阻隔层的材料通常为氧化硅(SiOx)，缓冲层可以包括无机材料，如氮化硅或氧化硅中的至少一种，用来防止衬底10下方的外界杂质渗入至上层的晶体管中，以及改善衬底10与上方膜层间的结合强度。
在本实施例中，所述第一半导体层20的材料包括但不限于多晶硅，所述第二半导体层51的材料包括但不限于氧化物，所述第一半导体层20形成各低温多晶硅晶体管的多晶硅有源层，所述第二半导体层51形成各氧化物晶体管的氧化物有源层，所述第一半导体层20和所述第二半导体层51通过所述第二源极73电连接。
在本实施例中，所述第一金属层30、所述第二金属层40以及所述第三金属层60的材料均可包括钼(Mo)、铝(Al)、铂(Pt)、钯(Pd)、银(Ag)、镁(Mg)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、钙(Ca)、钛(Ti)、钽(Ta)和钨(W)中的至少一种金属。
所述第一栅极31和所述第一电容电极32位于同一膜层，可以在同一工序中制作，所述第四电容电极41和所述第二电容电极42位于同一膜层，也可以在同一工序中制作，两者均能最大化的减少对所述显示面板厚度的影响。
在本实施例中，所述第一绝缘层90、所述第二绝缘层100以及所述第三绝缘层120的材料包括但不限于氧化硅；所述第一层间介质层110和所述第二层间介质层130的材料包括氮化硅和氧化硅中的至少一种。
此外，所述显示面板还可以包括位于所述第五金属层80上方的第一平坦层150、第二平坦层160、阳极180、像素定义层170、发光功能层190和支撑隔垫柱200。
请结合图4、图6、图8以及图10，在本实施例中，所述显示面板设置有穿过所述第二层间介质层130、所述第三绝缘层120以及所述第一层间介质层110的第一过孔1；其中，所述第四金属层70通过所述第一过孔1与所述第二电容电极42电连接。
进一步地，在本实施例中，所述第二源极73或所述第二漏极74穿过所述第一过孔1与所述第二电极层43电性连接，可以理解的是，本实施例对此不做进一步限制。
请结合图4、图6以及图9，所述显示面板还包括与所述第二半导体层51同层且间隔设置的第三半导体层52，所述第三半导体层52与所述第四金属层70电连接；其中，所述第三半导体层52在所述衬底10上的投影至少部分与所述第一电容电极32和所述第二电容电极42的重叠区域在所述衬底10上的投影重叠。
具体地，所述第三半导体层52通过所述第二源极73或所述第二漏极74与所述第二半导体层51电连接，可以理解的是，本实施例对此不做进一步限制。
在本实施例中，所述第三半导体层52的材料包括氧化物，所述第三半导体层52和所述第二半导体层51由同一氧化物形成。
进一步地，请结合图4、图6、图9以及图10，在本实施例中，所述显示面板设置有穿过所述第二层间介质层130和所述第三绝缘层120的第二过孔2；其中，所述第四金属层70通过所述第二过孔2与所述第三半导体层52电性连接。
进一步地，在本实施例中，所述第二源极73或所述第二漏极74穿过所述第二过孔2与所述第三半导体层52电性连接，可以理解的是，本实施例对此不做进一步限制。
本实施例通过在所述第二电极层43上制备所述第三半导体层52，使得构成所述第一电容Cboost的所述第二电极层43具备立体结构，因此可使得电容器结构在同等芯片面积下，增加了电容表面积，从而提升了所述第一电容Cboos的电容值，即提供了小尺寸大容量的电容器结构。
请结合图3~图12，在本实施例中，所述显示面板还包括阵列设置的多个发光器件D1和驱动所述发光器件D1发光的像素驱动电路，所述像素驱动电路包括：
第一初始化晶体管T4、开关晶体管T2、驱动晶体管T1、补偿晶体管T3、第二初始化晶体管T7、第一发光控制晶体管T5、第二发光控制晶体管T6、所述第一电容Cboost以及所述第二电容Cst。
其中，所述驱动晶体管T1的栅极连接于第一节点Q（N）（M），所述驱动晶体管T1的第一端连接于第三节点B，所述驱动晶体管T1的第二端连接于第二节点A。
所述开关晶体管T2的栅极连接第二扫描信号Scan2，所述开关晶体管T2的第一端连接数据信号Data，所述开关晶体管T2的第二端连接于第二节点A。
所述补偿晶体管T3的栅极连接第二扫描信号Scan2，所述补偿晶体管T3的第一端连接于第三节点B，所述补偿晶体管T3的第二端连接于第一节点Q（N）（M）。
所述第一初始化晶体管T4的栅连接第一扫描信号Scan1，所述第一初始化晶体管T4的第一端连接第二初始化信号VI2，所述第一初始化晶体管T4的第二端连接于第一节点Q（N）（M）。
所述第一发光控制晶体管T5的栅极连接发光控制信号EM，所述第一发光控制晶体管T5的第一端连接于第五节点D，所述第一发光控制晶体管T5的第二端连接于第二节点A，所述第一发光控制晶体管T5通过第五节点D与电源高电位信号线Vdd相连。
所述第二发光控制晶体管T6的栅极连接发光控制信号EM，所述第二发光控制晶体管T6的第一端连接于第三节点B，所述第二发光控制晶体管T6的第二端连接于第四节点C。
所述第二初始化晶体管T7的栅连接第二扫描信号Scan2，所述第二初始化晶体管T7的第一端连接于第四节点C，所述第二初始化晶体管T7的第二端连接于第一初始化信号VI。
所述第一电容Cboost的第一电容电极32连接于所述开关晶体管T2的栅极，所述第一电容Cboost的第二电容电极42连接于第一节点Q（N）（M）。
所述第二电容Cst的第三电容电极连接于第五节点D，所述第二电容Cst的第四电容电极41连接于第一节点Q（N）（M），所述第二电容Cst通过第五节点D与电源高电位信号线Vdd相连。
进一步地，在本实施例中，所述补偿晶体管T3、所述第一初始化晶体管T4和所述第二初始化晶体管T7为氧化物晶体管，所述开关晶体管T2、所述驱动晶体管T1、所述第一发光控制晶体管T5和所述第二发光控制晶体管T6为低温多晶硅晶体管。
请结合图4、图6、图7、图8、图9、图10以及图11，在本实施例中，所述补偿晶体管T3包括层叠设置于所述衬底10上的所述第四电容电极41、所述第一层间介质层110、所述第二半导体层51、所述第三绝缘层120、所述第三栅极61、所述第二层间介质层130以及所述第四金属层70；所述显示面板内还设置有穿过所述第二层间介质层130和所述第三绝缘层120的第三过孔3，所述第四金属层70穿过所述第三过孔3与所述第二半导体层51电连接；其中，所述第一过孔1到所述补偿晶体管T3的所述第二半导体层51的距离与所述第三过孔3到所述补偿晶体管T3的所述第二半导体层51的距离相等，从而可以明显提升所述补偿晶体管T3的电学性能，当所述补偿晶体管T3开启时，能够更加稳定的工作。
本实施例通过在衬底10上依次层叠设置第一半导体层20、第一金属层30、
第二金属层40、第二半导体层51、第三金属层60以及第四金属层70，其中，所述第四金属层70包括第一源极71、第一漏极72、第二源极73以及第二漏极74，所述第一源极71和所述第一漏极72与所述第一半导体层20电连接，所述第二源极73和所述第二漏极74与所述第二半导体层51电连接，所述第二半导体层51为氧化物半导体层；其中，所述第一金属层30包括第一电容电极32，所述第二金属层40包括第二电容电极42；所述第一电容电极32与所述第二电容电极42形成第一电容Cboost，所述第二电容电极42与所述第四金属层70电连接，从而使显示面板实现低频显示，且具有稳定的显示效果；同时降低所述像素驱动电路的功耗，避免高频显示下显示面板暗态效果不佳的问题。
请参阅图13，本申请实施例所提供的显示面板的第二种结构示意图。
在本实施例中，所述显示面板的第二种结构示意图与上述实施例一所提供的所述显示面板的第一种结构示意图相似/相同，具体请参照上述实施例一中关于所述显示面板的第一种结构示意图的描述，此处不再赘述，两者的区别仅在于：
在本实施例中，所述第二金属层40包括第一电容电极32，所述第三金属层60包括第二电容电极42；所述第一电容电极32和所述第二电容电极42形成第一电容Cboost，所述第二电容电极42与所述第四金属层70电连接。
进一步地，所述第二电极层43与所述第二漏极74电性连接。
在本实施例中，所述第一金属层30还包括第一栅极31，所述第二金属层40还包括第四电容电极41，所述第三金属层60还包括第三栅极61。
本实施例通过在所述显示面板内，设置有相对的第一电容电极32和第二电极层43，所述第一电容电极32与所述第四电容电极41同层设置，所述第二电极层43与所述第三栅极61同层设置，所述第一电容电极32和所述第二电极层43形成所述第一电容Cboost，从而使显示面板实现低频显示，且具有稳定的显示效果。
请结合图13、图14以及图18，在本实施例中，所述显示面板设置有穿过所述第二层间介质层130的第一过孔1；其中，所述第四金属层70通过所述第一过孔1与所述第二电容电极42电连接。
进一步地，在本实施例中，所述第二源极73或所述第二漏极74穿过所述第一过孔1与所述第二电极层43电性连接，可以理解的是，本实施例对此不做进一步限制。
请结合图13、图14以及图17，在本实施例中，本实施例通过在所述第二电极层43上制备所述第三半导体层52，使得构成所述第一电容Cboost的所述第一电容电极32具备立体结构，因此可使得电容器结构在同等芯片面积下，增加了电容表面积，从而提升了所述第一电容Cboost的电容值，即提供了小尺寸大容量的电容器结构。
进一步地，请结合图13、图14以及图17，在本实施例中，所述显示面板设置有穿过所述第二层间介质层130的第二过孔2；其中，所述第四金属层70通过所述第二过孔2与所述第三半导体层52电性连接。
进一步地，在本实施例中，所述第二源极73或所述第二漏极74穿过所述第二过孔2与所述第三半导体层52电性连接，可以理解的是，本实施例对此不做进一步限制。
请结合图13、图14、图15以及图16，在本实施例中，所述第一金属层30还包括第一栅极31和第三电容电极（图中未标出），所述第二金属层40还包括第四电容电极41，所述第三金属层60还包括第三栅极61，其中，所述第三电容电极和所述第四电容电极41形成所述第二电容Cst。
需要说明的是，在本实施例中，所述第一栅极31和所述第三电容电极可以由同一金属块形成，它们处于同一金属块的不同区域。
实施例二
请结合图4和图5，本申请实施例提供一种显示面板，所述显示面板包括阵列设置的多个发光器件和驱动所述发光器件D1发光的像素驱动电路，所述像素驱动电路包括：
第一初始化晶体管T4，用于在第一扫描信号Scan1的控制下，向第一节点Q（N）（M）输入第二初始化信号VI2。
开关晶体管T2，用于在第二扫描信号Scan2的控制下，向第二节点A输入数据信号Data。
驱动晶体管T1，用于在第一节点Q（N）（M）和第二节点A电位的控制下，驱动所述发光器件D1发光。
补偿晶体管T3，通过第一节点Q（N）（M）和第三节点B与所述驱动晶体管T1相连，用于在第三扫描信号Scan2的控制下，补偿所述驱动晶体管T1的阈值电压；
第二初始化晶体管T7，用于在第二扫描信号Scan2的控制下，向所述发光器件D1阳极输入第一初始化信号VI1。
第一发光控制晶体管T5，通过第二节点A与所述驱动晶体管T1相连，用于在发光控制信号EM的控制下，导通电源高电位信号线流向所述驱动晶体管T1的电流。
第二发光控制晶体管T6，通过第三节点B与所述驱动晶体管T1相连，用于在发光控制信号EM的控制下，导通所述驱动晶体管T1流向所述发光器件D1阳极的电流；
第一电容Cboost，耦接于第一节点Q（N）（M）和所述开关晶体管T2的栅极之间，用于降低第一节点Q（N）（M）的电位。
第二电容Cst，通过第一节点Q（N）（M）与所述驱动晶体管T1相连，通过第四节点C与电源高电位信号线Vdd相连，用于存储数据信号。
其中，所述第一电容Cboost包括相对设置的第一电容电极32和第二电容电极42，所述第一电容电极32与所述开关晶体管T2的栅极电性连接，所述第二电容电极42通过第一节点Q（N）（M）与所述第一初始化晶体管T4电性连接，其中，所述开关晶体管T2为低温多晶硅晶体管，所述第一初始化晶体管T4为氧化物晶体管。
在本实施例中，所述驱动晶体管T1的栅极连接于第一节点Q（N）（M），所述驱动晶体管T1的第一端连接于第三节点B，所述驱动晶体管T1的第二端连接于第二节点A。
所述开关晶体管T2的栅极连接第二扫描信号Scan2，所述开关晶体管T2的第一端连接数据信号Data，所述开关晶体管T2的第二端连接于第二节点A。
所述补偿晶体管T3的栅极连接第二扫描信号Scan2，所述补偿晶体管T3的第一端连接于第三节点B，所述补偿晶体管T3的第二端连接于第一节点Q（N）（M）。
所述第一初始化晶体管T4的栅连接第一扫描信号Scan1，所述第一初始化晶体管T4的第一端连接第二初始化信号VI2，所述第一初始化晶体管T4的第二端连接于第一节点Q（N）（M）。
所述第一发光控制晶体管T5的栅极连接发光控制信号EM，所述第一发光控制晶体管T5的第一端连接于第五节点D，所述第一发光控制晶体管T5的第二端连接于第二节点A，所述第一发光控制晶体管T5通过第五节点D与电源高电位信号线Vdd相连。
所述第二发光控制晶体管T6的栅极连接发光控制信号EM，所述第二发光控制晶体管T6的第一端连接于第三节点B，所述第二发光控制晶体管T6的第二端连接于第四节点C。
所述第二初始化晶体管T7的栅连接第二扫描信号Scan2，所述第二初始化晶体管T7的第一端连接于第四节点C，所述第二初始化晶体管T7的第二端连接于第一初始化信号VI。
所述第一电容Cboost的第一电容电极32连接于所述开关晶体管T2的栅极，所述第一电容Cboost的第二电容电极42连接于第一节点Q（N）（M）。
所述第二电容Cst的第三电容电极连接于第五节点D，所述第二电容Cst的第四电容电极41连接于第一节点Q（N）（M），所述第二电容Cst通过第五节点D与电源高电位信号线Vdd相连。
进一步地，在本实施例中，所述补偿晶体管T3、所述第一初始化晶体管T4和所述第二初始化晶体管T7为氧化物晶体管，所述开关晶体管T2、所述驱动晶体管T1、所述第一发光控制晶体管T5和所述第二发光控制晶体管T6为低温多晶硅晶体管。
进一步地，本实施例提供一种如前述任一实施例所述的显示面板，具有与前述显示面板相同的技术效果，在此不再赘述。
综上所述，本申请提供一种显示面板。所述显示面板包括衬底；以及依次层叠设置在所述衬底上的第一半导体层、第一金属层、第二金属层、第二半导体层、第三金属层以及第四金属层，其中，所述第四金属层包括第一源极、第一漏极、第二源极以及第二漏极，所述第一源极和所述第一漏极与所述第一半导体层电连接，所述第二源极和所述第二漏极与所述第二半导体层电连接，所述第二半导体层为氧化物半导体层；其中，所述第一金属层包括第一电容电极，所述第二金属层包括第二电容电极，所述第一电容电极与所述第二电容电极形成第一电容，所述第二电容电极与所述第四金属层电连接，从而可以实现低频显示，同时降低像素驱动电路的功耗。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种显示面板，其中，包括：
    衬底；以及
    像素驱动电路层，包括多个像素驱动电路，每个所述像素驱动电路包括第一电容和第二电容；
    其中，所述像素驱动电路层包括：依次层叠设置在所述衬底上的第一半导
    体层、第一金属层、第二金属层、第二半导体层、第三金属层以及第四金属层，其中，所述第四金属层包括第一源极、第一漏极、第二源极以及第二漏极，所述第一源极和所述第一漏极与所述第一半导体层电连接，所述第二源极和所述第二漏极与所述第二半导体层电连接，所述第二半导体层为氧化物半导体层；
    其中，所述第一电容和所述第二电容均有一个电容电极设置在所述第二金属层。
  2. 如权利要求1所述的显示面板，其中，所述第一金属层包括第一电容电极，所述第二金属层包括第二电容电极，或所述第二金属层包括第一电容电极，所述第三金属层包括第二电容电极；所述第一电容电极与所述第二电容电极形成所述第一电容，所述第二电容电极与所述第四金属层电连接。
  3. 如权利要求2所述的显示面板，其中，所述显示面板还包括位于所述第二金属层和所述第二半导体层之间的第一层间介质层、位于所述第二半导体层和所述第三金属层之间的第三绝缘层以及位于所述第三金属层和所述第四金属层之间的第二层间介质层。
  4. 如权利要求3所述的显示面板，其中，所述显示面板设置有穿过所述第二层间介质层、所述第三绝缘层以及所述第一层间介质层的第一过孔；
    其中，所述第四金属层通过所述第一过孔与所述第二电容电极电连接。
  5. 如权利要求3所述的显示面板，其中，所述显示面板设置有穿过所述第二层间介质层的第一过孔；
    其中，所述第四金属层通过所述第一过孔与所述第二电容电极电连接。
  6. 如权利要求3所述的显示面板，其中，所述显示面板还包括位于所述第一半导体层和所述第一金属层之间的第一绝缘层、及位于所述第一金属层和所述第二金属层之间的第二绝缘层；
    其中，所述第一金属层还包括第一栅极和第三电容电极，所述第二金属层还包括第四电容电极，所述第三金属层还包括第三栅极，其中，所述第三电容电极和所述第四电容电极形成所述第二电容。
  7. 如权利要求2所述的显示面板，其中，所述显示面板还包括与所述第二半导体层同层且间隔设置的第三半导体层，所述第三半导体层与所述第四金属层电连接；
    其中，所述第三半导体层在所述衬底上的投影至少部分与所述第一电容电极和所述第二电容电极的重叠区域在所述衬底上的投影重叠。
  8. 如权利要求7所述的显示面板，其中，所述第一半导体层为多晶硅半导体层，所述第三半导体层为氧化物半导体层。
  9. 如权利要求1任一项所述的显示面板，其中，所述显示面板还包括阵列设置的多个发光器件和驱动所述发光器件发光的像素驱动电路，所述像素驱动电路包括第一初始化晶体管、开关晶体管、驱动晶体管、补偿晶体管、第二初始化晶体管、第一发光控制晶体管、第二发光控制晶体管、所述第一电容以及所述第二电容；
    其中，所述驱动晶体管的栅极连接于第一节点，所述驱动晶体管的第一端连接于第三节点，所述驱动晶体管的第二端连接于第二节点；
    所述开关晶体管的栅极连接第二扫描信号，所述开关晶体管的第一端连接数据信号，所述开关晶体管的第二端连接于第二节点；
    所述补偿晶体管的栅极连接第二扫描信号，所述补偿晶体管的第一端连接
    于第三节点，所述补偿晶体管的第二端连接于第一节点;
    所述第一初始化晶体管的栅连接第一扫描信号，所述第一初始化晶体管的第一端连接第二初始化信号，所述第一初始化晶体管的第二端连接于第一节点;
    所述第一发光控制晶体管的栅极连接发光控制信号，所述第一发光控制晶体管的第一端连接于第五节点，所述第一发光控制晶体管的第二端连接于第二节点，所述第一发光控制晶体管通过第五节点与电源高电位信号线相连；
    所述第二发光控制晶体管的栅极连接发光控制信号，所述第二发光控制晶体管的第一端连接于第三节点，所述第二发光控制晶体管的第二端连接于第四节点；
    所述第二初始化晶体管的栅连接第二扫描信号，所述第二初始化晶体管的第一端连接于第四节点，所述第二初始化晶体管的第二端连接于第一初始化信号；
    所述第一电容的第一电容电极连接于所述开关晶体管的栅极，所述第一电容的第二电容电极连接于第一节点；
    所述第二电容的第三电容电极连接于第五节点，所述第二电容的第四电容电极连接于第一节点，所述第二电容通过第五节点与电源高电位信号线相连。
  10. 如权利要求9所述的显示面板，其中，所述补偿晶体管、所述第一初始化晶体管和所述第二初始化晶体管为氧化物晶体管，所述开关晶体管、所述驱动晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管为低温多晶硅晶体管。
  11. 一种显示面板，其中，所述显示面板包括阵列设置的多个发光器件和驱动所述发光器件发光的像素驱动电路，所述像素驱动电路包括：
    第一初始化晶体管，用于在第一扫描信号的控制下，向第一节点输入第二初始化信号；
    开关晶体管，用于在第二扫描信号的控制下，向第二节点输入数据信号；
    驱动晶体管，用于在第一节点和第二节点电位的控制下，驱动所述发光器件发光；
    补偿晶体管，通过第一节点和第三节点与所述驱动晶体管相连，用于在第三扫描信号的控制下，补偿所述驱动晶体管的阈值电压；
    第二初始化晶体管，用于在第二扫描信号的控制下，向所述发光器件阳极输入第一初始化信号；
    第一发光控制晶体管，通过第二节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通电源高电位信号线流向所述驱动晶体管的电流；
    第二发光控制晶体管，通过第三节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通所述驱动晶体管流向所述发光器件阳极的电流；
    第一电容，耦接于第一节点和所述开关晶体管的栅极之间，用于降低第一节点的电位；
    第二电容，通过第一节点与所述驱动晶体管相连，通过第四节点与电源高电位信号线相连，用于存储数据信号；
    其中，所述第一电容包括相对设置的第一电容电极和第二电容电极，所述第一电容电极与所述开关晶体管的栅极电性连接，所述第二电容电极通过第一节点与所述第一初始化晶体管电性连接，其中，所述开关晶体管为低温多晶硅晶体管，所述第一初始化晶体管为氧化物晶体管。
  12. 如权利要求11所述的显示面板，其中，所述驱动晶体管的栅极连接于第一节点，所述驱动晶体管的第一端连接于第三节点，所述驱动晶体管的第二端连接于第二节点；
    所述开关晶体管的栅极连接第二扫描信号，所述开关晶体管的第一端连接数据信号，所述开关晶体管的第二端连接于第二节点；
    所述补偿晶体管的栅极连接第二扫描信号，所述补偿晶体管的第一端连接
    于第三节点，所述补偿晶体管的第二端连接于第一节点;
    所述第一初始化晶体管的栅连接第一扫描信号，所述第一初始化晶体管的第一端连接第二初始化信号，所述第一初始化晶体管的第二端连接于第一节点;
    所述第一发光控制晶体管的栅极连接发光控制信号，所述第一发光控制晶体管的第一端连接于第五节点，所述第一发光控制晶体管的第二端连接于第二节点，所述第一发光控制晶体管通过第五节点与电源高电位信号线相连；
    所述第二发光控制晶体管的栅极连接发光控制信号，所述第二发光控制晶体管的第一端连接于第三节点，所述第二发光控制晶体管的第二端连接于第四节点；
    所述第二初始化晶体管的栅连接第二扫描信号，所述第二初始化晶体管的第一端连接于第四节点，所述第二初始化晶体管的第二端连接于第一初始化信号；
    所述第一电容的第一电容电极连接于所述开关晶体管的栅极，所述第一电容的第二电容电极连接于第一节点；
    所述第二电容的第三电容电极连接于第五节点，所述第二电容的第四电容电极连接于第一节点，所述第二电容通过第五节点与电源高电位信号线相连。
  13. 如权利要求12所述的显示面板，其特征在于，所述补偿晶体管和所述
    第二初始化晶体管为氧化物晶体管，所述驱动晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管为低温多晶硅晶体管。
  14. 如权利要求11所述的显示面板，其中，所述显示面板还包括：
    衬底；以及
    像素驱动电路层，包括多个像素驱动电路，每个所述像素驱动电路包括第一电容和第二电容；
    其中，所述像素驱动电路层包括：依次层叠设置在所述衬底上的第一半导
    体层、第一金属层、第二金属层、第二半导体层、第三金属层以及第四金属层，其中，所述第四金属层包括第一源极、第一漏极、第二源极以及第二漏极，所述第一源极和所述第一漏极与所述第一半导体层电连接，所述第二源极和所述第二漏极与所述第二半导体层电连接，所述第二半导体层为氧化物半导体层；
    其中，所述第一电容和所述第二电容均有一个电容电极设置在所述第二金属层。
  15. 如权利要求14所述的显示面板，其中，所述第一金属层包括第一电容电极，所述第二金属层包括第二电容电极，或所述第二金属层包括第一电容电极，所述第三金属层包括第二电容电极；所述第一电容电极与所述第二电容电极形成所述第一电容，所述第二电容电极与所述第四金属层电连接。
  16. 如权利要求15所述的显示面板，其中，所述显示面板还包括位于所述第二金属层和所述第二半导体层之间的第一层间介质层、位于所述第二半导体层和所述第三金属层之间的第三绝缘层以及位于所述第三金属层和所述第四金属层之间的第二层间介质层。
  17. 如权利要求16所述的显示面板，其中，所述显示面板设置有穿过所述第二层间介质层、所述第三绝缘层以及所述第一层间介质层的第一过孔；
    其中，所述第四金属层通过所述第一过孔与所述第二电容电极电连接。
  18. 如权利要求16所述的显示面板，其中，所述显示面板设置有穿过所述第二层间介质层的第一过孔；
    其中，所述第四金属层通过所述第一过孔与所述第二电容电极电连接。
  19. 如权利要求16所述的显示面板，其中，所述显示面板还包括位于所述第一半导体层和所述第一金属层之间的第二绝缘层、及位于所述第一金属层和所述第二金属层之间的第三绝缘层；
    其中，所述第一金属层还包括第一栅极和第三电容电极，所述第二金属层还包括第四电容电极，所述第三金属层还包括第三栅极，其中，所述第三电容电极和所述第四电容电极形成所述第二电容。
  20. 如权利要求15所述的显示面板，其中，所述显示面板还包括与所述第二半导体层同层且间隔设置的第三半导体层，所述第三半导体层与所述第四金属层电连接；
    其中，所述第三半导体层在所述衬底上的投影至少部分与所述第一电容电极和所述第二电容电极的重叠区域在所述衬底上的投影重叠。
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