WO2022239376A1 - 研磨条件決定用相関関係式の作成方法 - Google Patents
研磨条件決定用相関関係式の作成方法 Download PDFInfo
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- WO2022239376A1 WO2022239376A1 PCT/JP2022/008115 JP2022008115W WO2022239376A1 WO 2022239376 A1 WO2022239376 A1 WO 2022239376A1 JP 2022008115 W JP2022008115 W JP 2022008115W WO 2022239376 A1 WO2022239376 A1 WO 2022239376A1
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- 238000005498 polishing Methods 0.000 title claims abstract description 372
- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 claims abstract description 85
- 238000009826 distribution Methods 0.000 claims abstract description 57
- 238000012546 transfer Methods 0.000 claims abstract description 21
- 238000004458 analytical method Methods 0.000 claims abstract description 20
- 238000005259 measurement Methods 0.000 claims abstract description 13
- 239000002002 slurry Substances 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 238000010219 correlation analysis Methods 0.000 claims description 10
- 235000012431 wafers Nutrition 0.000 description 129
- 239000012528 membrane Substances 0.000 description 11
- 239000003795 chemical substances by application Substances 0.000 description 6
- 230000007246 mechanism Effects 0.000 description 5
- 230000004907 flux Effects 0.000 description 4
- 238000003825 pressing Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000006061 abrasive grain Substances 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 238000004227 thermal cracking Methods 0.000 description 1
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Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/005—Control means for lapping machines or devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B49/00—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation
- B24B49/14—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation taking regard of the temperature during grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
Definitions
- the present invention relates to a method of creating a correlation equation for determining polishing conditions, a method of determining polishing conditions, and a method of manufacturing a semiconductor wafer.
- the manufacturing process of semiconductor wafers includes a polishing process (see, for example, Japanese Patent Application Laid-Open No. 2018-186118 (the full description of which is specifically incorporated herein as disclosure)).
- the semiconductor wafer is polished under predetermined polishing conditions.
- the polishing conditions to be determined usually include a plurality of items. In the past, many trials and errors had to be repeated to determine these items.
- an object of one aspect of the present invention is to provide a new means that makes it possible to determine polishing conditions for semiconductor wafers without much trial and error.
- One aspect of the present invention is Polishing a semiconductor wafer under a plurality of polishing conditions including a plurality of polishing parameters, and acquiring by actual measurement information on the in-plane polishing amount distribution of the semiconductor wafer in polishing under the plurality of polishing conditions;
- a semiconductor wafer is polished under polishing conditions including a plurality of polishing parameters, and in-plane temperature distribution information during polishing of the semiconductor wafer in polishing under the plurality of polishing conditions is acquired by actual measurement, or the plurality of polishing parameters is included.
- the above correlation formula 3 is a correlation formula used for determining polishing conditions in actual polishing of a semiconductor wafer.
- a method for creating a correlation equation for determining polishing conditions hereinafter also referred to as a "method for creating a relational expression"
- the correlational expression (correlational expression 3) used for determining the polishing conditions in the actual polishing of the semiconductor wafer can be created by performing the various steps described above. . That is, the above correlation equation 3 can be determined without much trial and error. Furthermore, the following conjecture does not limit the present invention, but the correlation formula 3 determined in this way is based on the information obtained by the actual measurement and / or the information created by the heat transfer analysis as described above, The inventor of the present invention speculates that the correlation formula determined in consideration of the degree of influence of various polishing parameters can be expected to contribute to the determination of polishing conditions under which a semiconductor wafer can be polished with high precision.
- the temperature distribution parameter can be the difference (Tmax ⁇ Tmin) between the maximum in-plane temperature Tmax and the minimum in-plane temperature Tmin.
- the in-plane polishing amount distribution parameter can be the difference (Qmax-Qmin) between the maximum in-plane polishing amount Qmax and the minimum in-plane polishing amount Qmin.
- the polishing parameters can be selected from the group consisting of polishing time ⁇ , polishing slurry flow rate f, polishing pressure P, and surface plate/polishing head rotation speed ⁇ .
- One aspect of the present invention is creating a correlation equation for determining polishing conditions by the method of creating a relational expression; setting a target value or target range for the in-plane polishing amount distribution of the semiconductor wafer to be polished; and determining polishing conditions that are expected to achieve the set target value or target range by the above correlation formula;
- a method for determining polishing conditions including Regarding.
- One aspect of the present invention is Determining polishing conditions by the method for determining polishing conditions; and Polishing a semiconductor wafer under the determined polishing conditions; A method of manufacturing a semiconductor wafer, comprising Regarding.
- the semiconductor wafer can be a silicon wafer.
- FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor wafer polishing apparatus (single-sided polishing apparatus);
- FIG. FIG. 2 is a schematic cross-sectional view of a polishing head 10 of the polishing apparatus shown in FIG. 1;
- the correlation formula 3 finally created by the above relational formula creation method is a correlation formula used to determine the polishing conditions in the actual polishing of the semiconductor wafer.
- actual polishing means polishing performed in the process of manufacturing semiconductor wafers to be shipped as products.
- semiconductor wafers manufactured through such actual polishing are not limited to semiconductor wafers that are actually shipped as products and distributed in the market. It may also be a semiconductor wafer to be processed. Polishing methods for polishing the surface of a semiconductor wafer include single-sided polishing for polishing one side of the wafer and double-sided polishing for polishing both sides of the wafer.
- the polishing head and the surface plate are rotated while pressing the surface to be polished of the wafer held by the polishing head against the polishing pad attached to the surface plate, thereby polishing the surface to be polished of the wafer. and the polishing pad are brought into sliding contact with each other.
- a polishing agent between the surface to be polished and the polishing pad, which are in sliding contact with each other one surface of the wafer (the surface to be polished) can be polished.
- the correlation formula created by the above relational formula creation method can be used to determine the polishing conditions for single-side polishing as the actual polishing of the semiconductor wafer.
- FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor wafer polishing apparatus (single-sided polishing apparatus).
- the semiconductor wafer polishing apparatus 30 shown in FIG. 1 rotates the polishing head 10 and the surface plate 22 by rotating mechanisms (not shown), and polishes the surface of the semiconductor wafer (also simply referred to as "wafer") W to be polished. and the polishing pad 21 stuck on the surface plate 22 are brought into sliding contact.
- a polishing agent 41 discharged from the polishing agent supply mechanism 40 is supplied between the surface to be polished of the wafer W and the polishing pad 21, and the surface to be polished of the wafer W is polished.
- the polishing agent a polishing slurry commonly used in CMP (chemical mechanical polishing) can be used.
- FIG. 2 is a schematic cross-sectional view of the polishing head 10 of the polishing apparatus shown in FIG.
- a rubber chuck method is used as a method of pressing the wafer held by the polishing head against the polishing pad.
- the polishing head 10 shown in FIG. 2 is a rubber chuck type polishing head.
- air or the like is introduced into the space behind the membrane to inflate the membrane so that the wafer can be pressed via the back pad positioned below the membrane.
- the polishing head 10 has a head body 11 and a rigid ring 12 connected thereto.
- a lower surface of the rigid ring 12 is covered with a membrane 14 .
- a back pad 15 is attached to the lower surface of the membrane 14 .
- a space 17 is formed behind the membrane 14 by closing the opening of the rigid ring 12 with the intermediate plate 16 and the membrane 14 .
- a gas such as air is introduced into the space 17 from the gas introduction path 18 to inflate the membrane 14 , thereby pressing the wafer W held at the opening of the retainer ring 13 via the back pad 15 . can.
- the pressed wafer W is pressed against the polishing pad 21 bonded on the surface plate 22 .
- the surface to be polished w1 of the wafer W and the polishing pad 21 are brought into sliding contact by rotating the polishing head 10 and the platen 22 by rotating mechanisms (not shown).
- the polishing target surface w1 of the wafer W can be polished.
- An object to be polished with polishing conditions determined using the correlation formula determined by the above relational formula determination method is a semiconductor wafer, for example, a silicon wafer (preferably a single crystal silicon wafer).
- a silicon wafer can be produced by the following method. A silicon single crystal ingot is pulled up by the Czochralski method, and the produced ingot is cut to obtain a block. The resulting block is sliced into wafers. A silicon wafer can be produced by subjecting this wafer to various processes. Examples of the processing include chamfering, flattening (lapping, grinding, polishing), and the like. Polishing in which polishing conditions are determined using the correlation formula determined by the above-described relational formula determination method includes, for example, finish polishing, which is the final step of wafer processing described above.
- the semiconductor wafer is polished under a plurality of polishing conditions including a plurality of polishing parameters, and the in-plane polishing amount distribution information of the semiconductor wafer in the polishing under the plurality of polishing conditions is obtained by actual measurement. That is, the wafer is actually polished, and the amount of polishing at each in-plane portion of the polished wafer surface is actually measured.
- Wafers to be polished under various polishing conditions can be, for example, wafers cut from the same ingot and processed to have the same wafer diameter and the same thickness. However, it is not limited to this.
- the polishing parameters can be various numerical values that make up the polishing conditions.
- Examples of the plurality of polishing parameters include polishing time ⁇ , polishing slurry flow rate f, polishing pressure P, and surface plate/polishing head rotation speed ⁇ .
- Units for various polishing parameters are not particularly limited, and may be units that are commonly used for these parameters. Assuming that the rotating speed of the surface plate is ⁇ 1 and the rotating speed of the polishing head is ⁇ 2, in a normal semiconductor wafer polishing apparatus, ⁇ 1 and ⁇ 2 can be set independently, and can be set to the same value or different values. can do.
- silicon wafers were polished under various polishing conditions shown in Table 1 using the semiconductor wafer polishing apparatus shown in FIG.
- the wafers polished under various polishing conditions are wafers cut from the same silicon single crystal ingot and processed to have the same wafer diameter (300 mm in diameter) and the same thickness (775 ⁇ m in thickness).
- the wafer thickness was measured at multiple points in the plane of the polished surface of each wafer.
- the wafer thickness can be measured by any known non-contact or contact thickness measurement method. By subtracting the thickness at each point after polishing from the thickness of the wafer before polishing, the polishing amount was calculated for the plurality of points.
- a design value at the time of wafer manufacturing may be used, or a measured value at an arbitrary point or an arithmetic average of measured values at arbitrary plural points on the wafer before polishing may be used.
- the maximum value of the polishing amount calculated for each wafer polished under each polishing condition be the maximum in-plane polishing amount Qmax
- the minimum value be the minimum in-plane polishing amount Qmin
- the difference between them Qmax-Qmin
- Table 1 shows ⁇ Q obtained as ⁇ Q obtained in this way is an example of in-plane polishing amount distribution information.
- the units of various polishing parameters are arbitrary units.
- the polishing pressure P is the surface pressure applied to the surface of the wafer to be polished, and is a calculated value obtained by pressure calculation (finite element method) using ABAQUS manufactured by Dassault Systèmes. Note that ⁇ T in Table 1 will be described later.
- ⁇ Acquisition or creation of in-plane temperature distribution information during polishing> a semiconductor wafer is polished under polishing conditions including a plurality of polishing parameters, and in-plane temperature distribution information during polishing of the semiconductor wafer in polishing under these plurality of polishing conditions is obtained by actual measurement, or 2.
- a semiconductor wafer is polished under polishing conditions including a plurality of polishing parameters, and in-plane temperature distribution information during polishing of the semiconductor wafer in polishing under these polishing conditions is acquired by actual measurement. That is, the wafer is actually polished, and information about the temperature of each in-plane portion of the wafer surface during polishing is acquired by actual measurement.
- the temperature actually measured here can be the temperature of the position near the surface of the wafer being polished or the temperature itself of the surface of the wafer being polished. Normally, it is not easy to measure the surface temperature itself of the wafer surface being polished in sliding contact with the polishing pad. Therefore, the temperature actually measured here is preferably the temperature at a position near the surface to be polished of the wafer being polished.
- the semiconductor wafer polishing apparatus shown in FIG. can be employed as in-plane temperature distribution information during wafer polishing.
- thermocouple wire with a wireless device is inserted at multiple points between the membrane and the back pad before polishing is started.
- temperature can be measured.
- the temperatures at the above multiple locations are continuously measured.
- ⁇ T thus obtained is an example of in-plane temperature distribution information during polishing.
- the above example is an example in which in-plane temperature distribution information during polishing is acquired during polishing for acquiring in-plane polishing amount distribution information.
- the above relational expression determination method is not limited to this example.
- polishing may be performed separately from the polishing for obtaining the in-plane polishing amount distribution information, and the temperature may be measured during the polishing for obtaining the in-plane temperature distribution information during polishing.
- the plurality of polishing conditions for performing polishing for obtaining the in-plane polishing amount distribution information may be the same as the plurality of polishing conditions for obtaining the in-plane temperature distribution information during polishing. More than one or all of them may be different polishing conditions.
- the in-plane temperature distribution information during polishing of a semiconductor wafer in polishing under polishing conditions including a plurality of polishing parameters can be created by heat transfer analysis.
- a heat transfer analysis model a model that solves a heat conduction equation using general-purpose finite element method (FEM) analysis software Abaqus can be adopted.
- FEM finite element method
- the dynamic friction coefficient ⁇ used for frictional heat generation (heat flux boundary condition that expresses frictional heat flux) and slurry heat removal (heat flux boundary condition that expresses heat flux for slurry cooling and uses the Newton cooling law)
- the heat transfer coefficient h was taken as an experimental parameter.
- These are functions of the distance r from the wafer center and the polishing parameters (polishing time ⁇ , polishing pressure P, platen/polishing head rotation speed ⁇ , slurry flow rate f).
- the units of values of the polishing parameters are arbitrary units. The functions thus determined by the above model are shown below.
- the in-plane temperature distribution information during polishing of a semiconductor wafer in polishing under polishing conditions including a plurality of polishing parameters can also be created by heat transfer analysis without the need for actual measurement.
- ⁇ T which is the difference (Tmax ⁇ Tmin) between the maximum in-plane temperature Tmax and the minimum in-plane temperature Tmin, can be calculated from the prediction result.
- ⁇ T thus obtained is an example of in-plane temperature distribution information during polishing.
- ⁇ T shown in Table 1 is a value obtained by calculating ⁇ T when polishing a silicon wafer under various polishing conditions shown in Table 1 using the semiconductor wafer polishing apparatus shown in FIG. 1 to obtain ⁇ Q using the above heat transfer analysis model. .
- the above example is an example in which a heat transfer analysis model is applied to the polishing conditions for acquiring the in-plane polishing amount distribution information.
- the above relational expression determination method is not limited to this example.
- the plurality of polishing conditions for performing polishing for acquiring in-plane polishing amount distribution information may be the same as the plurality of polishing conditions for creating in-plane temperature distribution information during polishing by heat transfer analysis, or , one or more or all of which may be different polishing conditions.
- Correlation formula 1 is a correlation formula between the in-plane temperature distribution parameter of the semiconductor wafer and a plurality of polishing parameters, and can be created based on the in-plane temperature distribution information during polishing obtained or created above.
- ⁇ T is the difference between the maximum in-plane temperature Tmax and the minimum in-plane temperature Tmin, and can be obtained as described above.
- Equation 1 is the polishing time
- f the polishing slurry flow rate
- P the polishing pressure
- ⁇ the rotation speed of the surface plate/polishing head
- X 1 , X 2 , X 3 , X 4 and X 5 are constants determined by correlation analysis. , which is a positive or negative value.
- Correlation formula 2 is a correlation formula between the in-plane polishing amount distribution parameter of the semiconductor wafer and a plurality of polishing parameters, and can be created based on the in-plane polishing amount distribution information obtained above.
- ⁇ Q is the difference between the maximum in-plane polishing amount Qmax and the minimum in-plane polishing amount Qmin, and can be obtained as described above.
- Correlation formula 3 is a correlation formula used for determining polishing conditions in actual polishing of a semiconductor wafer, and can be created based on correlation formulas 1 and 2.
- the correlation formula 1 is the above formula 1
- the correlation formula 2 is the above formula 2
- X 1 to X 5 , Y 1 to Y 5 , ⁇ , f, P, and ⁇ have the same meanings as above.
- Correlation Equation 3 can be Equation 3 above.
- Equation 3 can be derived from Equations (1) and (2) above as Equation (3) below.
- Formula (3): ⁇ Q ( ⁇ 0.59+0.16 ⁇ +0.49P+0.53 ⁇ 0.006f) ⁇ (146.46 ⁇ 74.82 ⁇ 86.82P ⁇ 19.62 ⁇ 9.76f)
- One aspect of the present invention is creating a correlation equation for determining polishing conditions by the method of creating a relational expression; setting a target value or target range for the in-plane polishing amount distribution of the semiconductor wafer to be polished; and determining polishing conditions that are expected to achieve the set target value or target range by the above correlation formula; A method for determining polishing conditions, including Regarding.
- the creation of the correlation formula for determining the polishing conditions in the method for determining the polishing conditions is as described above.
- the above-described correlation formula 3 is the correlation formula for determining polishing conditions.
- Correlation formula 3 can be a correlation formula including ⁇ Q, and a specific example thereof is formula 3 described above.
- the target value or target range of ⁇ Q can be set as the target value or target range of the in-plane polishing amount distribution of the semiconductor wafer to be polished.
- Such a target value or target range can be arbitrarily set in consideration of the flatness desired for the product wafer.
- the polishing conditions (specifically, various polishing specific values of parameters) can be determined as polishing conditions that are expected to achieve a set target value or target range.
- Values that are slightly different from the above values, where A is the target value or a value within the target range, can be, for example, a value of "A x 0.90 to 1.10", and "A x 0.95 to It can also be a value of 1.05".
- one or more of the following items can be considered as constraints when determining the polishing conditions.
- Constraint A In order to prevent an increase in slurry cost, the slurry flow rate f is set to a predetermined value or less. For example, in the embodiment shown in Table 1, it is 1.00 or less. Also, in order to supply sufficient abrasive grains for polishing, the slurry flow rate f is set to a predetermined value or more. For example, in the embodiment shown in Table 1, it is 0.50 or more.
- Constraint B The polishing time ⁇ is set to a predetermined value or less in order to prevent an increase in throughput. For example, in the embodiment shown in Table 1, it is 1.00 or less.
- Constraint C In order to prevent damage to the members of the polishing head, the polishing pressure P is set to a predetermined value or less. For example, in the embodiment shown in Table 1, it is 2.00 or less.
- Constraint D In order to prevent condensation of slurry components, deterioration of the polishing pad, and thermal cracking of the platen, the maximum temperature of the surface to be polished of the wafer being polished or in the vicinity thereof (hereinafter simply referred to as described as "maximum value of temperature”) is set to a predetermined value T or less.
- the details of the temperature at or near the surface to be polished of the wafer during polishing are as described above.
- Formula (4): Tmax 17.04+0.76 ⁇ +7.31P+7.88 ⁇ 0.52f
- Constraint E In order to prevent the wafer from falling off during polishing, the surface plate/polishing head rotation speed ⁇ is set to a predetermined value or less. For example, in the embodiment shown in Table 1, it is 1.50 or less.
- polishing conditions can be determined, for example, as follows. (i) After setting the target value of ⁇ Q, the slurry flow rate f is determined within a range that satisfies the constraint condition A. (ii) Next, the surface plate/polishing head rotation speed ⁇ is determined within a range that satisfies the constraint condition E.
- the polishing time ⁇ is determined within a range that satisfies the constraint B.
- the polishing pressure P is determined within a range that satisfies the constraint condition C as the target value or a value close to the target value set by ⁇ Q.
- the polishing pressure P is suitable as the last determined value because it is relatively easy to control.
- the polishing conditions for the semiconductor wafer can be determined according to the correlation formula 3 without much trial and error, as described above.
- One aspect of the present invention is Determining polishing conditions by the method for determining polishing conditions; and Polishing a semiconductor wafer under the determined polishing conditions; A method of manufacturing a semiconductor wafer, comprising Regarding.
- polishing under the determined polishing conditions can be performed, for example, in a single-sided polishing apparatus.
- the above-described semiconductor wafer polishing apparatus shown in FIG. 1 is an example of a single-sided polishing apparatus.
- the polishing head 10 and the platen 22 are each rotated by a rotating mechanism (not shown), the polishing target surface of the wafer W and the platen 22 are bonded together. It is brought into sliding contact with the pad 21 .
- a polishing agent 41 discharged from the polishing agent supply mechanism 40 is supplied between the surface to be polished of the wafer W and the polishing pad 21, and the surface to be polished of the wafer W is polished.
- polishing slurry that is normally used for CMP (Chemical Mechanical Polishing) can be used.
- CMP Chemical Mechanical Polishing
- the method for manufacturing the semiconductor wafer known techniques relating to the method for manufacturing a semiconductor wafer having a polished surface can be applied, except that the polishing conditions are determined as described above.
- the wafer to be polished can be, for example, a silicon wafer (preferably a monocrystalline silicon wafer).
- silicon wafers can be made by the methods described above. Polishing performed under the polishing conditions determined as described above can be, for example, finish polishing, which is the final step of wafer processing.
- One aspect of the present invention is useful in the technical field of semiconductor wafers such as silicon wafers.
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Abstract
Description
複数の研磨パラメータを含む複数の研磨条件によって半導体ウェーハの研磨を行い、かかる複数の研磨条件での研磨における半導体ウェーハの面内研磨量分布情報を実測によって取得すること、
複数の研磨パラメータを含む研磨条件によって半導体ウェーハの研磨を行い、かかる複数の研磨条件での研磨における半導体ウェーハの研磨時面内温度分布情報を実測によって取得するか、または、複数の研磨パラメータを含む研磨条件での研磨における半導体ウェーハの研磨時面内温度分布情報を伝熱解析によって作成すること、
上記研磨時面内温度分布情報に基づき、半導体ウェーハの面内温度分布パラメータと複数の研磨パラメータとの相関関係式1を作成すること、
上記面内研磨量分布情報に基づき、半導体ウェーハの面内研磨量分布パラメータと複数の研磨パラメータとの相関関係式2を作成すること、
上記相関関係式1と上記相関関係式2とに基づき、半導体ウェーハの面内研磨量分布パラメータと複数の研磨パラメータとの相関関係式3を作成すること、
を含み、
上記相関関係式3は、半導体ウェーハの実研磨における研磨条件を決定するために使用される相関関係式である、
研磨条件決定用相関関係式の作成方法(以下、「関係式作成方法」とも記載する。)、
に関する。
上記相関関係式1は、
ΔT=X1+X2τ+X3P+X4ω+X5f
であることができる。ΔTは面内最高温度Tmaxと面内最低温度Tminとの差、τは研磨時間、fは研磨スラリー流量、Pは研磨圧力、ωは定盤・研磨ヘッド回転数であり、X1、X2、X3、X4およびX5は相関分析によって決定された定数である。
上記相関関係式2は、
ΔQ/ΔT=Y1+Y2τ+Y3P+Y4ω+Y5f
であることができる。ΔQは面内研磨量最大値Qmaxと面内研磨量最小値Qminとの差、τは研磨時間、fは研磨スラリー流量、Pは研磨圧力、ωは定盤・研磨ヘッド回転数であり、Y1、Y2、Y3、Y4およびY5は相関分析によって決定された定数である。
上記相関関係式3は、
ΔQ=(X1+X2τ+X3P+X4ω+X5f)×(Y1+Y2τ+Y3P+Y4ω+Y5f)
であることができる。
上記関係式作成方法によって研磨条件決定用相関関係式を作成すること、
研磨対象半導体ウェーハの面内研磨量分布の目標値または目標範囲を設定すること、および
設定された目標値または目標範囲を達成可能と予測される研磨条件を上記相関関係式によって決定すること、
を含む、研磨条件の決定方法、
に関する。
上記研磨条件の決定方法によって研磨条件を決定すること、および
決定された研磨条件によって半導体ウェーハの研磨を行うこと、
を含む、半導体ウェーハの製造方法、
に関する。
以下、上記関係式作成方法について、更に詳細に説明する。
図1は、半導体ウェーハ研磨装置(片面研磨装置)の一例を示す概略断面図である。図1に示す半導体ウェーハ研磨装置30は、研磨ヘッド10および定盤22を、それぞれ回転機構(図示せず)により回転させながら、半導体ウェーハ(単に「ウェーハ」とも記載する。)Wの研磨対象表面と定盤22上に貼り合わされた研磨パッド21とを摺接させる。研磨剤供給機構40から排出される研磨剤41が、ウェーハWの研磨対象表面と研磨パッド21との間に供給され、ウェーハWの研磨対象表面が研磨される。研磨剤としては、CMP(chemical Mechanical Polishing)に通常使用される研磨スラリーを用いることができる。
上記関係式決定方法により決定された相関関係式を使用して研磨条件が決定されて研磨される対象は、半導体ウェーハであり、例えばシリコンウェーハ(好ましくは単結晶シリコンウェーハ)であることができる。例えば、シリコンウェーハは、以下の方法により作製できる。チョクラルスキー法によりシリコン単結晶インゴットを引き上げ、作製されたインゴットをカットしてブロックを得る。得られたブロックをスライスしてウェーハとする。このウェーハに各種加工を施すことにより、シリコンウェーハを作製することができる。上記加工としては、面取り加工、平坦化加工(ラップ、研削、研磨)等を挙げることができる。上記関係式決定方法により決定された相関関係式を使用して研磨条件が決定される研磨としては、例えば、上記のウェーハ加工の最終工程である仕上げ研磨を挙げることができる。
上記関係式作成方法では、複数の研磨パラメータを含む複数の研磨条件によって半導体ウェーハの研磨を行い、これら複数の研磨条件での研磨における半導体ウェーハの面内研磨量分布情報を実測によって取得する。即ち、ウェーハの研磨を実際に行い、研磨されたウェーハ表面の面内各部における研磨量を実測する。各種研磨条件で研磨されるウェーハは、例えば、同じインゴットから切り出されたウェーハであって、かつ同じウェーハ径および同じ厚みに加工されたウェーハであることができる。ただし、これに限定されるものではない。研磨パラメータは、研磨条件を構成する各種数値であることができる。上記の複数の研磨パラメータとしては、例えば、研磨時間τ、研磨スラリー流量f、研磨圧力Pおよび定盤・研磨ヘッド回転数ωを挙げることができる。各種研磨パラメータの単位は、特に限定されず、それらパラメータについて通常採用され得る単位であることができる。定盤の回転数をω1とし、研磨ヘッドの回転数をω2とすると、通常の半導体ウェーハ研磨装置において、ω1とω2は、それぞれ独立に設定可能であって、同じ値にも異なる値にも設定することができる。本発明および本明細書において、「定盤・研磨ヘッド回転数ω」とは、ω1=ω2の場合の定盤の回転数かつ研磨ヘッドの回転数をいうものとする。
上記関係式作成方法では、複数の研磨パラメータを含む研磨条件によって半導体ウェーハの研磨を行い、これら複数の研磨条件での研磨における半導体ウェーハの研磨時面内温度分布情報を実測によって取得するか、または、複数の研磨パラメータを含む研磨条件での研磨における半導体ウェーハの研磨時面内温度分布情報を伝熱解析によって作成する。
例えば、伝熱解析モデルとして、汎用有限要素法(FEM)解析ソフトAbaqusにより熱伝導方程式を解くモデルを採用することができる。このような伝熱解析モデルを用いると、通常測定が容易ではない研磨中のウェーハ表面の温度を予測できる。
上記モデルでは、摩擦発熱(摩擦熱流束を表現する熱流束境界条件)に用いる動摩擦係数μ、スラリー抜熱(スラリー冷却の熱流束を表現し、Newton冷却則を使用した熱流束境界条件)に用いる熱伝達率hを、実験パラメータとした。これらはウェーハ中心からの距離r、研磨パラメータ(研磨時間τ,研磨圧力P、定盤・研磨ヘッド回転数ω、スラリー流量f)の関数となる。ここでは、研磨パラメータの値の単位は、任意単位としている。こうして上記モデルにより決定された関数を以下に示す。
相関関係式1は、半導体ウェーハの面内温度分布パラメータと複数の研磨パラメータとの相関関係式であって、上記で取得または作成された研磨時面内温度分布情報に基づいて作成することができる。例えば、相関関係式1は、「式1:ΔT=X1+X2τ+X3P+X4ω+X5f」であることができる。ここで、ΔTは、面内最高温度Tmaxと面内最低温度Tminとの差であり、先に記載したように求めることができる。τは研磨時間、fは研磨スラリー流量、Pは研磨圧力、ωは定盤・研磨ヘッド回転数であり、X1、X2、X3、X4およびX5は相関分析によって決定された定数であり、正または負の値である。相関分析の手法は公知である。
一例として、表1に示した実施形態では、式1は、以下の式(1)として求められる(R2=0.89)。
式(1):
ΔT=max(T(r,t=τ,P,ω,f))-min(T(r,t=τ,P,ω,f))
=-0.59+0.16τ+0.49P+0.53ω-0.006f
相関関係式2は、半導体ウェーハの面内研磨量分布パラメータと複数の研磨パラメータとの相関関係式であって、上記で取得された面内研磨量分布情報に基づいて作成することができる。例えば、相関関係式2は、「式2:ΔQ/ΔT=Y1+Y2τ+Y3P+Y4ω+Y5f」であることができる。ここで、ΔQは、面内研磨量最大値Qmaxと面内研磨量最小値Qminとの差であり、先に記載したように求めることができる。τは研磨時間、fは研磨スラリー流量、Pは研磨圧力、ωは定盤・研磨ヘッド回転数であり、Y1、Y2、Y3、Y4およびY5は相関分析によって決定された定数であり、正または負の値である。一例として、表1に示した実施形態では、式2は、以下の式(2)として求められる(R2=0.91)。
式(2):
ΔQ/ΔT=ΔQ(τ,P,ω,f)/ΔT(τ,P,ω,f)
=146.46-74.82τ-86.82P-19.62ω-9.76f
相関関係式3は、半導体ウェーハの実研磨における研磨条件を決定するために使用される相関関係式であって、相関関係式1と相関関係式2とに基づいて作成することができる。例えば、相関関係式1が上記式1であり、相関関係式2が上記式2の場合、式1と式2から「式3:ΔQ=(X1+X2τ+X3P+X4ω+X5f)×(Y1+Y2τ+Y3P+Y4ω+Y5f)」を導出できる。式3中、X1~X5、Y1~Y5、τ、f、P、ωは上記と同義である。例えば、相関関係式3は、上記式3であることができる。一例として、表1に示した実施形態では、式3は、上記の式(1)および式(2)から、以下の式(3)として導出できる。
式(3):
ΔQ=(-0.59+0.16τ+0.49P+0.53ω-0.006f)×(146.46-74.82τ-86.82P-19.62ω-9.76f)
本発明の一態様は、
上記関係式作成方法によって研磨条件決定用相関関係式を作成すること、
研磨対象半導体ウェーハの面内研磨量分布の目標値または目標範囲を設定すること、および
設定された目標値または目標範囲を達成可能と予測される研磨条件を上記相関関係式によって決定すること、
を含む、研磨条件の決定方法、
に関する。
式(4):
Tmax=17.04+0.76τ+7.31P+7.88ω-0.52f
研磨条件は、例えば、以下のように決定することができる。
(i)ΔQの目標値を設定した後、制約条件Aを満たす範囲内でスラリー流量fを決定する。
(ii)次いで、制約条件Eを満たす範囲内で定盤・研磨ヘッド回転数ωを決定する。
(iii)その後、制約条件Bを満たす範囲内で研磨時間τを決定する。
(iv)上記(i)~(iii)においてスラリー流量f、定盤・研磨ヘッド回転数ωおよび研磨時間τが決定された後、決定された各種値を式(3)に代入し、式(3)においてΔQが設定した目標値または目標値に近い値となる値として、制約条件Cを満たす範囲内で研磨圧力Pを決定する。式(3)を構成する各種変数(τ、P、ωおよびf)の中で、研磨圧力Pは、制御が比較的容易なため最後に決定される値として適している。
表2中、制約条件の判定の欄に「OK」と記載されていることは、同表中の左隣の値が表1に示す実施形態について記載した上記制約条件を満たす範囲内であることを示す。なお、表2に示す研磨条件は例示であって、これら以外にも式(3)が成立する研磨条件は各種あり得る。
本発明の一態様は、
上記研磨条件の決定方法によって研磨条件を決定すること、および
決定された研磨条件によって半導体ウェーハの研磨を行うこと、
を含む、半導体ウェーハの製造方法、
に関する。
Claims (10)
- 複数の研磨パラメータを含む複数の研磨条件によって半導体ウェーハの研磨を行い、該複数の研磨条件での研磨における半導体ウェーハの面内研磨量分布情報を実測によって取得すること、
複数の研磨パラメータを含む研磨条件によって半導体ウェーハの研磨を行い、該複数の研磨条件での研磨における半導体ウェーハの研磨時面内温度分布情報を実測によって取得するか、または、複数の研磨パラメータを含む研磨条件での研磨における半導体ウェーハの研磨時面内温度分布情報を伝熱解析によって作成すること、
前記研磨時面内温度分布情報に基づき、半導体ウェーハの面内温度分布パラメータと複数の研磨パラメータとの相関関係式1を作成すること、
前記面内研磨量分布情報に基づき、半導体ウェーハの面内研磨量分布パラメータと複数の研磨パラメータとの相関関係式2を作成すること、
前記相関関係式1と前記相関関係式2とに基づき、半導体ウェーハの面内研磨量分布パラメータと複数の研磨パラメータとの相関関係式3を作成すること、
を含み、
前記相関関係式3は、半導体ウェーハの実研磨における研磨条件を決定するために使用される相関関係式である、
研磨条件決定用相関関係式の作成方法。 - 前記面内温度分布パラメータは、面内最高温度Tmaxと面内最低温度Tminとの差(Tmax-Tmin)である、請求項1に記載の作成方法。
- 前記面内研磨量分布パラメータは、面内研磨量最大値Qmaxと面内研磨量最小値Qminとの差(Qmax-Qmin)である、請求項1または2に記載の作成方法。
- 前記研磨パラメータは、研磨時間τ、研磨スラリー流量f、研磨圧力Pおよび定盤・研磨ヘッド回転数ωからなる群から選択される、請求項1~3のいずれか1項に記載の作成方法。
- 前記相関関係式1は、
ΔT=X1+X2τ+X3P+X4ω+X5f
であり、
ΔTは面内最高温度Tmaxと面内最低温度Tminとの差、τは研磨時間、fは研磨スラリー流量、Pは研磨圧力、ωは定盤・研磨ヘッド回転数であり、X1、X2、X3、X4およびX5は相関分析によって決定された定数である、請求項1~4のいずれか1項に記載の作成方法。 - 前記相関関係式2は、
ΔQ/ΔT=Y1+Y2τ+Y3P+Y4ω+Y5f
であり、
ΔQは面内研磨量最大値Qmaxと面内研磨量最小値Qminとの差、τは研磨時間、fは研磨スラリー流量、Pは研磨圧力、ωは定盤・研磨ヘッド回転数であり、Y1、Y2、Y3、Y4およびY5は相関分析によって決定された定数である、請求項5に記載の作成方法。 - 前記相関関係式3は、
ΔQ=(X1+X2τ+X3P+X4ω+X5f)×(Y1+Y2τ+Y3P+Y4ω+Y5f)
である、請求項6に記載の作成方法。 - 請求項1~7のいずれか1項に記載の作成方法によって研磨条件決定用相関関係式を作成すること、
研磨対象半導体ウェーハの面内研磨量分布の目標値または目標範囲を設定すること、および
設定された目標値または目標範囲を達成可能と予測される研磨条件を前記相関関係式によって決定すること、
を含む、研磨条件の決定方法。 - 請求項8に記載の決定方法によって研磨条件を決定すること、および
決定された研磨条件によって半導体ウェーハの研磨を行うこと、
を含む、半導体ウェーハの製造方法。 - 前記半導体ウェーハはシリコンウェーハである、請求項9に記載の製造方法。
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