WO2022227431A1 - 一种阵列基板及显示面板 - Google Patents
一种阵列基板及显示面板 Download PDFInfo
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- WO2022227431A1 WO2022227431A1 PCT/CN2021/125509 CN2021125509W WO2022227431A1 WO 2022227431 A1 WO2022227431 A1 WO 2022227431A1 CN 2021125509 W CN2021125509 W CN 2021125509W WO 2022227431 A1 WO2022227431 A1 WO 2022227431A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 88
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Definitions
- the present application relates to the field of display technology, and in particular, to an array substrate and a display panel.
- LCD display has occupied a dominant position in the display industry, and products using ADS (advanced extra-dimensional field conversion technology) structure have the advantages of wide viewing angle, high response speed block and high contrast ratio and become the mainstream display mode ;
- ADS advanced extra-dimensional field conversion technology
- the driving of the product will face difficulties, it is necessary to use 2G2D (2 Gate lines are driven at the same time, 2
- 2G2D Gate lines are driven at the same time, 2
- the pixel It is necessary to increase the gate signal line parallel to the data line to transmit signals to the gate line, and the transmittance drop will be more obvious. Therefore, how to improve the light transmittance of high-resolution full-screen products is an urgent problem to be solved.
- the present application provides an array substrate and a display panel.
- data lines in a pair of data lines pass through corresponding sub-pixel regions, and light-shielding bars are arranged between the sub-pixel regions in the row direction to shield light, thereby effectively increasing the The light effect area of the sub-pixel area is improved, and the light transmittance is improved.
- An array substrate comprising:
- the substrate has a display area, and the display area includes a plurality of sub-pixel areas distributed in an array;
- a scan line is arranged on the substrate, and the scan line is located between the two rows of the sub-pixel regions and extends in the row direction. Two adjacent scan lines form a scan line group, and any two scan lines form a scan line group. In the scan line groups, the scan lines in one scan line group and the scan lines in the other scan line group are different from each other;
- the scan signal lines extend along the column direction, the scan signal lines are located between two adjacent sub-pixel area columns, and one of the scan signal lines is only connected to two of the scan line groups Scan line electrical connection;
- each of the data line pairs includes two data lines spaced apart and arranged in parallel, the data lines extend along the column direction, and the sub-pixel columns are one with the data line pairs A corresponding setting, in the sub-pixel column and the data line pair corresponding to each other, the two data lines in the data line pair pass through the corresponding sub-pixel area along the column direction;
- a thin film transistor which is electrically connected to the scan line and electrically connected to the data line;
- the pixel electrode is located in the sub-pixel region and is electrically connected to the thin film transistor, and the pixel electrode is orthographically projected on the base substrate with the corresponding two data lines on the base Orthographic overlay settings on the bottom;
- a light shielding bar is arranged between every two adjacent sub-pixel regions.
- a display area is included on the substrate, a wiring area is arranged on the peripheral side of the display area, a plurality of sub-pixel areas distributed in an array are arranged in the display area, and the plurality of sub-pixel areas are distributed in rows and columns, and there are mutually perpendicular rows on the substrate.
- the scan lines are arranged on the substrate, and the scan lines extend along the row direction, a plurality of scan lines are arranged and distributed in sequence along the column direction, and the scan lines are located between two adjacent rows of sub-pixel regions , wherein each two adjacent scan lines form a scan line group, and the two scan lines in each scan line group are different from the scan lines in other scan line groups;
- the substrate is also provided with scan signal lines, A plurality of scan signal lines extend along the column direction, the scan signal lines can be arranged between two adjacent sub-pixel area columns, and one scan signal line only corresponds to two scan lines in one scan line group, and is connected with the two scan lines in one scan line group. The corresponding two scan lines are electrically connected.
- the scan line signal lines can be evenly distributed on the substrate, and each scan signal line is electrically connected to the corresponding two scan lines for providing electrical signals to the scan signal lines.
- the two scan lines can be provided with electrical signals at the same time, and the two scan lines can be driven at the same time, and the scan signal lines extend along the column direction, and the drive circuit of the scan lines can be placed in the substrate along the column direction.
- One side of the substrate is introduced, thereby reducing the frame width of the other three sides of the substrate; a plurality of data line pairs are arranged on the substrate, each data line pair includes two data lines arranged at intervals, and the data lines are extended along the column direction, and Arranged and distributed along the row direction, the data line pairs are arranged in a one-to-one correspondence with the sub-pixel area columns. In the corresponding data line pairs and sub-pixel area columns, the two data lines in the data pair are located in the corresponding sub-pixel along the column direction.
- the data lines in the display area can be divided into two parts, one part is opposite to the sub-pixel area along the column direction, and the other part is opposite to the interval between two adjacent sub-pixel areas, wherein each The part corresponding to the sub-pixel area in the data lines overlaps with the sub-pixel area; wherein, a pixel electrode is arranged in the sub-pixel area, and the pixel electrode and the two data lines in the data line pair are also overlapped and arranged in the sub-pixel area.
- a light-shielding bar is arranged between every two adjacent sub-pixel areas, and the light-shielding bar is used for Covering the interval between two adjacent sub-pixels in two row directions, avoiding light leakage, and avoiding color mixing; wherein, compared with the prior art, the two data lines in the data line pair are arranged on both sides of the sub-pixel area , that is, two data lines are arranged in the interval between two adjacent sub-pixel regions in the row direction. To avoid the risk of short circuit, a certain distance is required between these two data lines, and two sub-pixels will be increased.
- the separation distance between the regions increases the width of the light-shielding regions arranged along the column direction. These light-shielding regions have no light effect, occupying the light effect area of the sub-pixel area and reducing the light effect area of the sub-pixel area.
- the data lines run through the sub-pixels, and the light-shielding bars extend along the column direction between adjacent sub-pixel regions. In the column direction, the light-shielding bars can avoid sub-pixels.
- the color mixing between the pixel areas, and the width of the shading strip along the row direction can be reduced, which greatly reduces the shading width between the two sub-pixel areas in the row direction, and can effectively increase the light effect area of the sub-pixel area.
- the light transmittance of the sub-pixel region in the above-mentioned array substrate can be greatly improved compared with the pixel structure in the prior art.
- the above-mentioned array substrate is applied to high-resolution full-screen products, which can effectively solve the problem of high-resolution
- the problem of low light transmittance of high-resolution full-screen products is improved, and the light transmittance of high-resolution full-screen products is improved.
- the data lines in the data line pairs pass through the corresponding sub-pixel regions, and the light-shielding bars are arranged between the sub-pixel regions in the row direction to shield the light, which effectively increases the light effect area of the sub-pixel regions and improves the performance of the sub-pixel regions. light transmittance.
- an organic insulating layer is provided between the data line and the pixel electrode for isolation.
- the array substrate further includes a common electrode corresponding to the pixel electrode, and a common electrode line electrically connected to the common electrode.
- the common electrode is located on a side of the data line away from the substrate, and the pixel electrode is located on a side of the common electrode away from the data line; the organic insulating layer is located on the data line between the common electrode and the common electrode; a passivation layer is arranged between the common electrode and the pixel electrode for isolation.
- the light-shielding strip is a metal light-shielding strip, and the metal light-shielding strip is electrically connected to the common electrode line.
- the shading strips and the scanning lines are prepared in the same layer.
- the thin film transistor includes a gate electrode, a gate insulating layer, an active layer, an insulating layer, and source and drain electrodes electrically connected to the active layer, which are stacked in sequence;
- the gate electrode and the scan line are prepared in the same layer; the source and drain electrodes are arranged in the same layer as the data line.
- some scan signal lines are not electrically connected to the scan lines, and some of the scan signal lines are electrically connected to the common electrode line.
- the scanning signal lines and the data lines are prepared in the same layer.
- the pixel electrode includes a plurality of electrode strips arranged at intervals and connected in sequence.
- the array substrate further includes a light shielding layer disposed along the row direction and corresponding to the scan lines for shielding light.
- the present application also provides a display panel including any one of the array substrates provided by the above technical solutions.
- FIG. 1 is a schematic partial structure diagram of an array substrate according to an embodiment of the present application.
- FIG. 2 is a schematic structural diagram of a sub-pixel in an array substrate according to an embodiment of the present application
- FIG. 3 is a schematic structural diagram of a sub-pixel in an array substrate according to an embodiment of the present application.
- Icon 1-sub-pixel area; 2-scanning line; 3-scanning signal line; 4-data line pair; 5-thin film transistor; 6-pixel electrode; 7-shading bar; 8-common electrode; 9-common electrode line ; 10-shading layer; 41-data line; 61-electrode strip.
- an embodiment of the present application provides an array substrate, comprising: a substrate, the substrate has a display area, and the display area includes a plurality of sub-pixel areas 1 distributed in an array; a scan line 2 is disposed on the substrate, and the scan line 2 is located in two rows of sub-pixel areas between and extending in the row direction, two adjacent scan lines form a scan line group, and in any two scan line groups, the scan lines in one scan line group and the scan lines in the other scan line group are mutually Different from each other, that is, multiple scan lines are divided into multiple scan line groups, two scan lines in each scan line group are adjacent, and scan lines in two adjacent scan line groups are not shared The scan lines in the two scan line groups are different scan lines from each other; the scan signal line 3, the scan signal line 3 extends along the column direction, and the scan signal line 3 is located
- the two data lines 41 in the data line pair are in the corresponding sub-pixel columns in the column direction. Pass through the pixel area 1; thin film transistor 5, the thin film transistor 5 is electrically connected to the scan line 2 and electrically connected to the data line 4; pixel electrode 6, the pixel electrode 6 is located in the sub-pixel area 1 and is electrically connected to the thin film transistor 5 connected, the orthographic projection of the pixel electrode 6 on the substrate is overlapped with the orthographic projection of the corresponding two data lines 41 on the substrate; along the row direction, a light shielding strip 7 is provided between each adjacent two sub-pixel regions .
- the above-mentioned array substrate includes a substrate and scan lines, scan signal lines, data lines, thin film transistors, and pixel electrodes arranged on the substrate.
- the substrate includes a display area, and a wiring area is arranged on the peripheral side of the display area.
- a plurality of sub-pixel regions distributed in an array a plurality of sub-pixel regions are distributed in rows and columns, and there are mutually perpendicular row and column directions on the substrate; wherein, the scan lines are arranged on the substrate, and the scan lines extend along the row direction, and the plurality of scan lines Arranged and distributed in sequence along the column direction, and the scan lines are located between two adjacent rows of sub-pixel regions, wherein every two adjacent scan lines form a scan line group, and a plurality of scan lines form a plurality of scan line groups , the two scan lines in each scan line group are different from the scan lines in other scan line groups; the substrate is also provided with scan signal lines, and a plurality of scan signal lines extend along the column direction, and the scan signal lines can be set at Between two adjacent two sub-pixel area columns, and one scan signal line only corresponds to two scan lines in one scan line group, and is electrically connected with the corresponding two scan lines, specifically, the scan line signal The lines can be evenly distributed on the substrate, and each scan signal line is
- the data lines extend along the column direction and are arranged and distributed along the row direction.
- a corresponding setting, in the corresponding data line pair and sub-pixel area column the two data lines in the data pair pass through the corresponding sub-pixel area along the column direction, and the data line in the display area can be divided into two part, along the column direction, one part is opposite to the sub-pixel area, and the other part is opposite to the interval between two adjacent sub-pixel areas, wherein the part corresponding to the sub-pixel area in each data line intersects the sub-pixel area.
- a pixel electrode is arranged, and the pixel electrode and the two data lines in the data line pair are also arranged to overlap.
- the light effect area here refers to the area in the sub-pixel area that can effectively transmit light
- a light-shielding strip is provided between every two adjacent sub-pixel areas , the shading strip is used to cover the interval between two adjacent sub-pixels in the two row directions, avoid light leakage, and avoid color mixing; wherein, compared with the prior art, the two data lines in the data line pair are arranged in the sub-pixels. Two data lines are arranged on both sides of the pixel area, that is, in the interval between two adjacent sub-pixel areas in the row direction.
- the data lines run through the sub-pixels, and the light-shielding bars extend along the column direction and are arranged between adjacent sub-pixel areas.
- the shading strip can avoid color mixing between the sub-pixel areas, and the width of the shading strip along the row direction can be reduced, which greatly reduces the shading width between the two sub-pixel areas in the row direction. Effectively increase the light effect area of the sub-pixel area and improve the light transmittance.
- the light transmittance of the sub-pixel area in the above-mentioned array substrate can be greatly improved compared with the pixel structure in the prior art.
- the above-mentioned array substrate is applied to high-resolution Among the high-resolution full-screen products, it can effectively solve the problem of low light transmittance of high-resolution full-screen products, and improve the light transmittance of high-resolution full-screen products.
- the data lines in the data line pairs pass through the corresponding sub-pixel regions, and the light-shielding bars are arranged between the sub-pixel regions in the row direction to shield the light, which effectively increases the light effect area of the sub-pixel regions and improves the performance of the sub-pixel regions. light transmittance.
- an organic insulating layer is provided between the data line and the pixel electrode for isolation.
- an organic insulating layer is arranged between the data line and the pixel electrode to be insulated from each other, and the layer thickness of the organic insulating layer can be based on actual needs. Appropriately thickening can weaken or even avoid the electric field between the data line and the pixel electrode, prevent the voltage pull on the pixel electrode when the voltage of the data line jumps, avoid bad signal crosstalk, and avoid affecting the display effect, which can help ensure normal display effect. .
- the above-mentioned array substrate further includes a common electrode 8 corresponding to the pixel electrode, and a common electrode line 9 electrically connected to the common electrode 8 .
- the common electrode line provides a stable voltage to the common electrode to ensure normal display function. .
- the common electrode is disposed on the substrate, the common electrode is located on the side of the data line away from the substrate, and the pixel electrode is located on the side of the common electrode away from the data line; the organic insulating layer is located between the data line and the common electrode; the common electrode and the pixel A passivation layer is provided between the electrodes for isolation. That is, along the stacking direction of the layer structure on the substrate, the common electrode is located between the data line and the pixel electrode, and an organic insulating layer is provided between the common electrode and the data line for isolation, and there is passivation between the common electrode and the pixel electrode.
- the common electrode is located between the data line and the pixel electrode, which can effectively shield the electric field between the data line and the pixel electrode, and prevent the pixel electrode from being pulled when the voltage of the data line jumps, resulting in poor signal crosstalk; it can effectively To ensure the normal display of the sub-pixels, and the common electrode is arranged between the data line and the pixel electrode to shield the electric field between the two, the thickness of the organic insulating layer between the data line and the common electrode can be appropriately set to be smaller, so that the The insulating effect is sufficient, and there is no need to rely on the organic insulating layer to shield the electric field between the data line and the pixel electrode, which can help reduce the thickness of the display panel and facilitate the thinning design of the display panel.
- the light-shielding strips are metal light-shielding strips, and the metal light-shielding strips are electrically connected to the common electrode lines.
- the light-shielding strips and the common electrode lines can be connected through via holes, which can make the common electrical signal uniformity of the common electrodes on the substrate better.
- the above-mentioned light shielding strips can be prepared in the same layer as the scanning lines, that is, the light shielding strips and the scanning lines can be formed by patterning in the same metal layer, which can save the preparation process and simplify the preparation process.
- the thin film transistor includes a gate electrode, a gate insulating layer, an active layer, an insulating layer, and source and drain electrodes electrically connected to the active layer that are stacked in sequence; the gate electrode may be connected to the scan line.
- the same layer is prepared; the source and drain electrodes can be arranged in the same layer as the data line, and the drain electrode of the thin film transistor is electrically connected to the pixel electrode through the via hole.
- the same scanning signal line corresponds to only one scanning line group.
- the number of scan signal lines should be at least half of the number of scan lines, that is, to make the number of scan signal lines exactly correspond to the number of scan lines, so that two scan lines can be sent to the two scan lines at the same time.
- Electric signal driving alternatively, the number of scan signal lines may be more than the number of scan line groups. In addition to being electrically connected to scan lines, some scan signal lines will be idle.
- the idle scan signal lines are not electrically connected to the scan lines, and this part of the idle scan signal lines can be electrically connected to the common electrode lines, which can further improve the uniformity of the common electrical signals of the common electrodes of the display panel;
- the number of scan signal lines is more than the number of scan line groups, for example, when the number of scan signal lines is more than multiple times the number of scan line groups, two or three scan signal lines can be set to correspond to one scan line group. That is, two or three scan signal lines are respectively connected to the same scan line group, and two or three scan signal lines simultaneously provide scan signals to one scan line group, which can effectively reduce the resistance value.
- a scan signal line can be set between two adjacent pixel units, wherein, it is necessary to ensure that one scan signal line corresponds to one scan line group and is electrically connected, and is not connected to the scan line.
- the connected scan signal lines may be connected to the common electrode lines.
- one scan signal line only corresponds to one scan line group, which means that the same scan signal line can only correspond to one scan line group, but only one scan signal line is limited to be connected to only one scan line group, but , a scan line group can be connected to more than two different scan signal lines at the same time, when the number of scan signal lines is too large, two different scan signal lines can be connected to the same scan line group respectively, two different scan signal lines at the same time Provide scan signals to the same scan line group, and one scan line group may correspond to multiple scan signal lines.
- the pixel unit is a pixel structure of 7680 ⁇ 4320 in the row direction ⁇ column direction, wherein, in the row direction, each row is set to 7680 pixel unit, each pixel unit is 3 sub-pixels arranged along the row direction, and in the column direction, each column is provided with 4320 pixel units;
- one scanning signal line can be provided on one side of each column of pixel units, and one scanning signal line can be provided for each pixel unit, and the scanning signal lines can be evenly arranged on the display panel, which is beneficial to improve the consistency of the pixel aperture ratio, then there are 7680 7680 is three times of 2160 and there are still 1200 scan signal lines. Therefore, three scan signal lines can be set to be connected to two scan lines in the same scan line group, wherein each scan signal line is connected to two scan lines in the scan line group. All scan lines are connected, that is, three scan signal lines provide scan signals to two scan lines in a scan line group at the same time, and the extra 1200 scan signal lines can be electrically connected to the common electrode lines.
- the scanning signal lines and the data lines are prepared in the same layer, and the scanning signal lines can be connected to the scanning lines through vias to achieve electrical connection, and the same metal layer is used for patterning to form the scanning signal lines and the data lines at the same time, saving one sheet mask, reducing the preparation process.
- the scanning signal line can also be prepared in a different layer from the data line, that is, the scanning signal line and the data line are divided into two layers of metal layers, and are prepared by using different masks. For the preparation of the scanning signal line, this embodiment does not do limited.
- the separation distance between the two data lines in is set to be greater than or equal to 5 ⁇ m, specifically, the separation distance between the two data lines here refers to the distance between the adjacent sides of the two data lines;
- the separation distance between two data lines in the pair of data lines is set to be greater than or equal to 5 ⁇ m, which can effectively avoid the problem of poor short circuit.
- the separation distance between the two data lines and the thickness of the data lines, Materials and other factors are related, as long as no short circuit occurs between two adjacent data lines, the distance between the two data lines in the data line pair can be set to 6 ⁇ m, 7 ⁇ m, 7.5 ⁇ m, 8 ⁇ m, 9 ⁇ m or Other values are not limited in this implementation.
- the spacing distance between two adjacent data lines belonging to different data line pairs in two adjacent data line pairs is also greater than or equal to 7 ⁇ m.
- the distance between two adjacent data lines belonging to different data line pairs will definitely be relatively large, greater than 7 ⁇ m, which generally does not cause short circuit problems.
- the above-mentioned array substrate further includes a light-shielding layer 10 arranged along the row direction and corresponding to the scan lines for light-shielding.
- the light-shielding layer here forms a light-shielding black matrix, and along the row direction of the substrate, a light-shielding layer 10 is arranged The layer blocks the scan line and the light leakage area between the scan line and the sub-pixel area, which can effectively avoid color mixing.
- the pixel electrode 6 can be set as a plurality of electrode strips 61 arranged at intervals and connected in sequence, wherein the plurality of electrode strips 61 are arranged side by side at intervals. Arrangement, from the arrangement direction of the plurality of electrode strips, the same end of a part of the electrode strips are connected in turn, the other end of the other part of the electrode strips are connected in sequence, and both ends of the electrode strip located in the middle part are connected, so that the two parts of the electrode strips are electrically connected. Up, a "horse"-shaped pixel electrode is formed, as shown in FIG. 2 , which can effectively improve the light transmittance of the pixel. It should be noted that the same ends of a plurality of electrode strips in the pixel electrode are connected in sequence to form a comb-shaped pixel electrode, as shown in FIG.
- the shape structure is not limited in this embodiment.
- This embodiment also provides a display panel including any of the array substrates provided in the foregoing embodiments.
- the display panel in this embodiment is an ADS display panel.
- the light effect area of the sub-pixel area is increased, which effectively improves the light transmittance.
- the light transmittance of the display panel in this embodiment can be effectively increased by more than 26%.
- the transmittance is also increased by more than 20%, which effectively solves the problem of the current high-resolution full-screen products.
- the problem of low transmittance improves the light transmittance of high-resolution full-screen products.
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Abstract
本申请涉及显示技术领域,公开了一种阵列基板及显示面板,该阵列基板包括:基板以及设于基板上的扫描线、扫描信号线、数据线对、薄膜晶体管、像素电极,基板具有显示区,显示区包括阵列分布的子像素区;两条相邻的扫描线构成一个扫描线组,扫描信号线沿列方向延伸,一条扫描信号线仅与一个扫描线组中的两个扫描线电性连接;每个数据线对包括两条数据线,子像素列与数据线对一一对应设置,数据线对中的两条数据线沿列方向在对应的子像素区内穿过;沿行方向,每相邻的两个子像素区之间设置有遮光条。该阵列基板中,数据线在对应的子像素区中穿行,行方向上的子像素区之间设置遮光条进行遮光,有效增大了子像素区的光效区,提高光透过率。
Description
相关申请的交叉引用
本申请要求在2021年4月29日提交中国专利局、申请号为202110474950.8、申请名称为“一种阵列基板及显示面板”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
本申请涉及显示技术领域,特别涉及一种阵列基板及显示面板。
随着显示技术的不断发展,LCD显示已经占据了显示行业的主导地位,而采用ADS(高级超维场转换技术)结构的产品具有宽视角、响应速度块和对比度高等优点成为了主流的显示模式;对于目前的全面屏产品负载大于常规产品,尤其是要达到超高分辨率级别,如8K级别,12K级别,产品的驱动将面临困难,就需要采用2G2D(2个Gate走线同时驱动、2个Data走线同时驱动)的像素架构来进行像素的驱动了,不过对于超高分辨率的产品,由于分辨率高,像素尺寸小,本身透过率较低,如果做成全面屏产品,像素中需要增加与数据线平行的Gate信号线给Gate走线传输信号,透过率下降会更加明显,因此,如何提声高分辨率的全面屏产品的光透过率是目前亟需解决的问题。
发明内容
本申请提供了一种阵列基板及显示面板,该阵列基板中,数据线对中的数据线在对应的子像素区中穿行,行方向上的子像素区之间设置遮光条进行遮光,有效增大了子像素区的光效区,提高光透过率。
为达到上述目的,本申请提供以下技术方案:
一种阵列基板,包括:
基板,所述基板具有显示区,显示区包括阵列分布的多个子像素区;
扫描线,设置于所述基板上,且所述扫描线位于两行所述子像素区之间并沿行方向延伸,两条相邻的所述扫描线构成一个扫描线组,且任意两个所述扫描线组中,其中一个扫描线组中的扫描线与另一个扫描线组中的扫描线彼此互不相同;
扫描信号线,所述扫描信号线沿列方向延伸,所述扫描信号线位于相邻的两个子像素区列之间,且一条所述扫描信号线仅与一个所述扫描线组中的两条扫描线电性连接;
数据线对,设置于所述基板上,每个所述数据线对包括两条间隔且并行设置的数据线,所述数据线沿列方向延伸,所述子像素列与所述数据线对一一对应设置,在相互对应的子像素列与数据线对中,所述数据线对中的两条数据线沿列方向在对应的子像素区内穿过;
薄膜晶体管,所述薄膜晶体管与所述扫描线电性连接且与所述数据线电性连接;
像素电极,所述像素电极位于所述子像素区内且与所述薄膜晶体管电性连接,所述像素电极在所述衬底基板上正投影与对应的两条所述数据线在所述衬底上的正投影交叠设置;
沿行方向,每相邻的两个子像素区之间设置有遮光条。
上述阵列基板中,在基板上包括显示区,在显示区的周侧设置有布线区,显示区内具有阵列分布的多个子像素区,多个子像素区行列分布,在基板上有相互垂直的行方向和列方向;其中,扫描线设置在基板上,并且扫描线沿着行方向延伸,多个扫描线沿着列方向依次间隔排列分布,且扫描线位于相邻的两行子像素区之间,其中,每两条相邻的扫描线构成一个扫描线组,每个扫描线组中的两个扫描线与其它扫描线组中的扫描线均不相同;基板上还设置有扫描信号线,多条扫描信号线沿列方向延伸,扫描信号线可以设置在两个相邻的两个子像素区列之间,并且,一条扫描信号线仅对应一个扫描线组中的两条扫描线,并与对应的两个扫描线电性连接,具体地,扫描线信号 线可以均匀分布在基板上,每个扫描信号线与相对应的两个扫描线电性连接,用于给扫描信号线提供电信号,即在扫描线进行扫描时,可以同时给两个扫描线提供电信号,同时驱动两个扫描线,且扫描信号线沿列方向延伸,可以将扫描线的驱动电路在基板中沿列方向上的一边引入,进而减小基板的其它三边的边框宽度;在基板上设置多个数据线对,每个数据线对包括两条间隔设置的数据线,数据线沿着列方向延伸设置,并且沿着行方向排列分布,数据线对与子像素区列一一对应设置,在相互对应的数据线对和子像素区列中,数据对中的两条数据线沿着列方向在对应的子像素区内穿过,在显示区内的数据线可以划分为两部分,沿着列方向,一部分与子像素区相对,另一部分与两个相邻的子像素区之间的间隔相对,其中,每条数据线中与子像素区对应的部位与子像素区交叠;其中,在子像素区内设置有像素电极,像素电极与数据线对中的两个数据线也交叠设置,在子像素区内,除了数据线遮挡的区域,其它区域都是光效区,并且,沿着行方向排列的子像素区中,每相邻的两个子像素区之间设置有遮光条,遮光条用于遮盖两个行方向上的两个相邻子像素之间的间隔,避免漏光,并且避免混色;其中,相比于现有技术,数据线对中的两个数据线设置在子像素区的两侧,也就是在行方向上相邻的两个子像素区之间的间隔内设置有两个数据线,这两个数据线之间为避免短路风险,需要间隔一定的距离,则会增大两个子像素区之间的间隔距离,增大了沿着列方向布置的遮光区的宽度,这些遮光区都没有光效,挤占了子像素区的光效区,使子像素区的光效区缩减,而本实施例中,数据线在子像素内穿行,遮光条沿着列方向延伸设置在相邻的子像素区之间,在列方向上,遮光条可以避免子像素区之间的混色,并且遮光条的沿着行方向上的宽度可以缩减,极大的减小了行方向两个子像素区之间的遮光宽度,可以有效增大子像素区的光效区,提高光透过率,上述阵列基板中的子像素区的透光率较现有技术中像素结构可以有较大提升,上述阵列基板应用于高分辨率的全面屏产品中,可以有效解决高分辨率的全面屏产品的光透过率低的问题,提升高分辨率的全面屏产品的光透过率。
因此,上述阵列基板中,数据线对中的数据线在对应的子像素区中穿行,行方向上的子像素区之间设置遮光条进行遮光,有效增大了子像素区的光效区,提高光透过率。
可选地,所述数据线与所述像素电极之间设置有有机绝缘层以隔绝。
可选地,所述阵列基板还包括与所述像素电极对应的公共电极、以及与所述公共电极电连接的公共电极线。
可选地,所述公共电极位于所述数据线背离所述基板的一侧,且所述像素电极位于所述公共电极背离所述数据线的一侧;所述有机绝缘层位于所述数据线与所述公共电极之间;所述公共电极与所述像素电极之间设置有钝化层以隔绝。
可选地,所述遮光条为金属遮光条,且所述金属遮光条与所述公共电极线电性连接。
可选地,所述遮光条与所述扫描线同层制备。
可选地,所述薄膜晶体管包括依次层叠设置的栅极、栅绝缘层、有源层、绝缘层和与所述有源层电性连接的源、漏电极;
其中,所述栅极与所述扫描线同层制备;所述源、漏电极与所述数据线同层设置。
可选地,所述扫描信号线中,部分扫描信号线与所述扫描线无电性连接,且所述部分扫描信号线与所述公共电极线电性连接。
可选地,所述扫描信号线与所述数据线同层制备。
可选地,所述像素电极包括多个间隔设置且依次连接的电极条。
可选地,所述阵列基板还包括沿所述行方向设置并与扫描线对应以用于遮光的遮光层。
本申请还提供了一种显示面板,包括如上述技术方案提供的任意一种阵列基板。
图1为本申请实施例提供的一种阵列基板的局部结构示意图;
图2为本申请实施例提供的一种阵列基板中的子像素的结构示意图;
图3为本申请实施例提供的一种阵列基板中的子像素的结构示意图。
图标:1-子像素区;2-扫描线;3-扫描信号线;4-数据线对;5-薄膜晶体管;6-像素电极;7-遮光条;8-公共电极;9-公共电极线;10-遮光层;41-数据线;61-电极条。
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。
如图1和图2所示,其中,图1中,以下行方向如图1中A方向所示,列方向如图1中B方向所示。本申请实施例提供了一种阵列基板,包括:基板,基板具有显示区,显示区包括阵列分布的多个子像素区1;扫描线2,设置于基板上,扫描线2位于两行子像素区之间并沿行方向延伸,两条相邻的扫描线构成一个扫描线组,且任意两个扫描线组中,其中一个扫描线组中的扫描线与另一个扫描线组中的扫描线彼此互不相同,也就是,多个扫描线划分为多个扫描线组,每个扫描线组中的两个扫描线是相邻的,并且两个相邻的扫描线组中的扫描线没有共用的扫描线,两个扫描线组中的扫描线是彼此不同的扫描线;扫描信号线3,扫描信号线3沿列方向延伸,扫描信号线3位于相邻的两个子像素区列之间,且一条扫描信号线3仅与一个扫描线组中的两条扫描线2电性连接;数据线对4,设置于基板上,每个数据线对4包括两条间隔且并行设置数据线41,数据线41沿列方向延伸,子像素列与数据线对一一对应设置,在相互对应的子像素列与数据线对中,数据线对中的两条数据线41沿列方向在对应的子像素区1内穿过;薄膜晶体管5,薄膜晶体管5 与扫描线2电性连接且与数据线4电性连接;像素电极6,像素电极6位于子像素区1内且与薄膜晶体管5电性连接,像素电极6在衬底基板上正投影与对应的两条数据线41在衬底上的正投影交叠设置;沿行方向,每相邻的两个子像素区之间设置有遮光条7。
上述阵列基板中,包括基板以及设于基板上的扫描线、扫描信号线、数据线、薄膜晶体管、像素电极,基板上包括显示区,在显示区的周侧设置有布线区,显示区内具有阵列分布的多个子像素区,多个子像素区行列分布,在基板上有相互垂直的行方向和列方向;其中,扫描线设置在基板上,并且扫描线沿着行方向延伸,多个扫描线沿着列方向依次间隔排列分布,且扫描线位于相邻的两行子像素区之间,其中,每两条相邻的扫描线构成一个扫描线组,多个扫描线形成多个扫描线组,每个扫描线组中的两个扫描线与其它扫描线组中的扫描线均不相同;基板上还设置有扫描信号线,多条扫描信号线沿列方向延伸,扫描信号线可以设置在两个相邻的两个子像素区列之间,并且,一条扫描信号线仅对应一个扫描线组中的两条扫描线,并与对应的两个扫描线电性连接,具体地,扫描线信号线可以均匀分布在基板上,每个扫描信号线与相对应的两个扫描线电性连接,用于给扫描信号线提供电信号,即在扫描线进行扫描时,可以同时给两个扫描线提供电信号,同时驱动两个扫描线,且扫描信号线沿列方向延伸,可以将扫描线的驱动电路在基板中沿列方向上的一边引入,进而减小基板的其它三边的边框宽度;在基板上设置多个数据线对,每个数据线对包括两条间隔设置的数据线,数据线沿着列方向延伸设置,并且沿着行方向排列分布,数据线对与子像素区列一一对应设置,在相互对应的数据线对和子像素区列中,数据对中的两条数据线沿着列方向在对应的子像素区内穿过,在显示区内的数据线可以划分为两部分,沿着列方向,一部分与子像素区相对,另一部分与两个相邻的子像素区之间的间隔相对,其中,每条数据线中与子像素区对应的部位与子像素区交叠;其中,在子像素区内设置有像素电极,像素电极与数据线对中的两个数据线也交叠设置,在子像素区内,除了数据线遮挡的区域,其它区域都是光效区, 其中,这里的光效区,是指子像素区中可以有效透光的区域,并且,沿着行方向排列的子像素区中,每相邻的两个子像素区之间设置有遮光条,遮光条用于遮盖两个行方向上的两个相邻子像素之间的间隔,避免漏光,并且避免混色;其中,相比于现有技术,数据线对中的两个数据线设置在子像素区的两侧,也就是在行方向上相邻的两个子像素区之间的间隔内设置有两个数据线,这两个数据线之间为避免短路风险,需要间隔一定的距离,则会增大两个子像素区之间的间隔距离,增大了沿着列方向布置的遮光区的宽度,这些遮光区都没有光效,挤占了子像素区的光效区,使子像素区的光效区缩减,而本实施例中,数据线在子像素内穿行,遮光条沿着列方向延伸设置在相邻的子像素区之间,在列方向上,遮光条可以避免子像素区之间的混色,并且遮光条的沿着行方向上的宽度可以缩减,极大的减小了行方向两个子像素区之间的遮光宽度,可以有效增大子像素区的光效区,提高光透过率,上述阵列基板中的子像素区的透光率较现有技术中像素结构可以有较大的提升,上述阵列基板应用于高分辨率的全面屏产品中,可以有效解决高分辨率的全面屏产品的光透过率低的问题,提升高分辨率的全面屏产品的光透过率。
因此,上述阵列基板中,数据线对中的数据线在对应的子像素区中穿行,行方向上的子像素区之间设置遮光条进行遮光,有效增大了子像素区的光效区,提高光透过率。
具体地,上述阵列基板中,数据线与像素电极之间设置有有机绝缘层以隔绝。在基板上的层结构设置上,在数据线与像素电极的层结构叠置方向上,数据线和像素电极之间设置有机绝缘层进行彼此绝缘,并且,有机绝缘层的层厚度可以根据实际需求适当加厚,可以减弱甚至避免数据线与像素电极之间的电场,防止数据线电压跳变时对像素电极产生电压拉动,避免发生信号串扰不良,避免影响显示效果,可以有利于保证正常显示效果。
具体地,如图1所示,上述阵列基板还包括与像素电极对应的公共电极8、以及与公共电极8电连接的公共电极线9,公共电极线给公共电极提供稳定电压,保证正常显示功能。
具体地,公共电极设置在基板上,公共电极位于数据线背离基板的一侧,且像素电极位于公共电极背离数据线的一侧;有机绝缘层位于数据线与公共电极之间;公共电极与像素电极之间设置有钝化层以隔绝。也就是,沿着基板上的层结构叠置方向,公共电极位于数据线与像素电极之间,并且公共电极与数据线之间设置有机绝缘层进行隔绝,公共电极与像素电极之间有钝化层进行隔绝,公共电极位于数据线与像素电极之间,可以有效的屏蔽数据线与像素电极之间的电场,防止数据线电压跳变时对像素电极产生电压拉动,出现信号串扰不良;可以有效保证子像素正常显示,并且公共电极设置在数据线与像素电极之间来屏蔽两者之间的电场,则数据线与公共电极之间的有机绝缘的层厚度可以适当的设置小一点,起到绝缘作用就可以,不需要依靠有机绝缘层屏蔽数据线和像素电极之间的电场了,可以有利于减小显示面板的厚度,有利于显示面板轻薄化设计。
具体地,上述遮光条为金属遮光条,且金属遮光条与公共电极线电性连接。遮光条与公共电极线可以通过过孔连接,可以使基板上的公共电极的公共电信号均一性更好。
具体地,上述遮光条可以与扫描线同层制备,也就是遮光条和扫描线可以在同一金属层中通过图形化处理时制备形成,可以节省制备工序,简化制备流程。
具体地,上述阵列基板中,薄膜晶体管包括依次层叠设置的栅极、栅绝缘层、有源层、绝缘层和与有源层电性连接的源、漏电极;其中,栅极可以与扫描线同层制备;源、漏电极可以与数据线同层设置,并且,薄膜晶体管的漏极通过过孔与像素电极电性连接。
具体地,上述阵列基板中,对于扫描信号线的数量以及与扫描线组的对应设置关系,扫描信号线设置多条,一般对于扫描信号线的设置,同一条扫描信号线仅对应一个扫描线组中的两条扫描线设置,从数量设置上来说,扫描信号线的数量至少设置扫描线数量的一半,也就是使扫描信号线的数量正好与扫描线的数量对应,实现同时给两个扫描线电信号驱动;或者,也可以 设置扫描信号线的数量可以多于扫描线组的数量,多个扫描信号线中除了与扫描线电性连接之外,还会有一部分扫描信号线闲置,这一部分闲置的扫描信号线与扫描线无电性连接,可以将这部分闲置的扫描信号线与公共电极线电性连接,可以进一步提升显示面板的公共电极的公共电信号的均一性;也或者,在设置扫描信号线的数量多于扫描线组的数量过多时,比如,扫描信号线的数量比扫描线组的数量的多倍以上时,可以设置两条或三条扫描信号线对应一个扫描线组,也就是,两条或三条扫描信号线各自连接到同一个扫描线组,两条或三条扫描信号线同时给一个扫描线组提供扫描信号,可以有效减小阻值。
其中,为了保证像素开口率一致性,可以在相邻的两个像素单元之间设置一条扫描信号线,其中,要保证一条扫描信号线与一个扫描线组对应并且电性连接,没有与扫描线连接的扫描信号线可以连接到公共电极线。需要说明的是,上述一条扫描信号线仅与一个扫描线组对应,指的是,同一条扫描信号线只能对应一个扫描线组,只是限定一条扫描信号线只连接到一个扫描线组,但是,一个扫描线组可以同时连接两个以上不同的扫描信号线,当扫描信号线数量过多时,可以两个不同的扫描信号线分别连接到同一个扫描线组,两个不同的扫描信号线同时给同一个扫描线组提供扫描信号,一个扫描线组可以对应多个扫描信号线。
具体地,为便于说明扫描信号线的数量和分布设置,以下以8K分辨率,像素单元是行方向×列方向为7680×4320的像素结构来说明,其中,行方向上,每一行设置为7680个像素单元,每个像素单元是沿行方向排列的3个子像素,列方向上,每一列设置4320个像素单元;
对于以上8K分辨率的像素结构,可以有2160个扫描线组,则可以只设置2160条扫描信号线,扫描信号线与扫描线组一一对应设置;
或者,可以每列像素单元的一侧设置一条扫描信号线,每个像素单元配一条扫描信号线,在显示面板上均匀设置扫描信号线,有利于提高像素开口率的一致性,则就有7680条扫描信号线,7680为2160的三倍还余1200,所 以,可以设置三条扫描信号线连接到同一个扫描线组的两个扫描线,其中,每一个扫描信号线与扫描线组中的两个扫描线都连接,也就是,有三条扫描信号线同时给一个扫描线组中的两个扫描线提供扫描信号,多余的1200条扫描信号线可以电连接到公共电极线。
具体地,扫描信号线与数据线同层制备,并且扫描信号线可以与扫描线通过过孔连接以实现电连接,利用同一金属层进行图形化处理同时形成扫描信号线和数据线,节约一张mask,减少制备工序。需要说明的是,扫描信号线也可以与数据线非同层制备,也就是扫描信号线与数据线分两层金属层,利用不同的mask制备,对于扫描信号线的制备,本实施例不做局限。
具体地,为了避免数据对中的两个数据线的距离过近而导致短路,将每个数据线对中的两个数据线之间需要有一定的间隔距离,具体地,每个数据线对中的两个数据线之间的间隔距离设置为大于等于5μm,具体地,该处两个数据线之间的间隔距离是指该两个数据线彼此相邻的侧边之间距离;将每个所述数据线对中的两个数据线之间的间隔距离设置为大于等于5μm,可以有效避免发生短路不良的问题,具体地,两个数据线之间的间隔距离和数据线的厚度、材料等因素有关系,只要保证两个相邻的数据线之间不会发生短路,数据线对中的两个数据线之间的间隔距离设置可以为6μm、7μm、7.5μm、8μm、9μm或者其它数值,本实施不做局限。
需要说明的是,根据本实施例中数据线的设置,相邻的两个数据线对中,属于不同数据线对的两个相邻的数据线之间的间隔距离也是大于等于7μm的,由于根据本实施例中的像素结构设置,在结构布置时,属于不同数据线对的两个相邻的数据线之间的间隔距离肯定会比较大,会大于7μm,一般不会带来短路问题。
具体地,如图1所示,上述阵列基板还包括沿行方向设置并与扫描线对应以用于遮光的遮光层10,这里的遮光层形成遮光黑矩阵,沿着基板的行方向上,设置遮光层遮挡扫描线以及扫描线与子像素区之间的漏光区域,可以有效避免混色。
具体地,如图2和图3所示,为了进一步增大光透过率,可以将像素电极6设置为多个间隔设置且依次连接的电极条61,其中,多个电极条61依次间隔并排设置,从多个电极条的排列方向上,一部分电极条的同一端依次连接,另一部分电极条的另一端依次连接,位于中间部位的电极条两端均连接,以使两部分电极条电连接起来,形成一“马”字型像素电极,如图2所示,可以有效提升像素的光透过率。需要说明的是,像素电极中的多个电极条的同一端依次练连接,可以形成梳子形状的像素电极,如图3所示,或者,多个电极条也可以是其它连接方式,形成其它的形状结构,本实施例不做局限。
本实施例还提供了一种显示面板,包括如上述实施例提供的任意一种阵列基板。本实施例中的显示面板为ADS显示面板,显示面板中的像素结构中,子像素区的光效区增大,有效提升了光透过率,其中,相比于现有技术中ADS显示面板,本实施例中的显示面板光透过率可以有效提升大于26%,另外,相比于现有的IPS显示面板,透过率提升也大于20%,有效解决了目前高分辨率全面屏产品透过率较低的问题,提升高分辨率的全面屏产品的光透过率。
显然,本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样,倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内,则本申请也意图包含这些改动和变型在内。
Claims (12)
- 一种阵列基板,其中,包括:基板,所述基板具有显示区,显示区包括阵列分布的多个子像素区;扫描线,设置于所述基板上,且所述扫描线位于相邻的两行所述子像素区之间并沿行方向延伸,两条相邻的所述扫描线构成一个扫描线组,且任意两个所述扫描线组中,其中一个扫描线组中的扫描线与另一个扫描线组中的扫描线彼此互不相同;扫描信号线,所述扫描信号线沿列方向延伸,所述扫描信号线位于相邻的两个子像素区列之间,且一条所述扫描信号线仅与一个所述扫描线组中的两条扫描线电性连接;数据线对,设置于所述基板上,每个所述数据线对包括两条间隔且并行设置的数据线,所述数据线沿列方向延伸,所述子像素列与所述数据线对一一对应设置,在相互对应的子像素列与数据线对中,所述数据线对中的两条数据线沿列方向在对应的子像素区内穿过;薄膜晶体管,所述薄膜晶体管与所述扫描线电性连接且与所述数据线电性连接;像素电极,所述像素电极位于所述子像素区内且与所述薄膜晶体管电性连接,所述像素电极在所述衬底基板上正投影与对应的两条所述数据线在所述衬底上的正投影交叠设置;沿行方向,每相邻的两个子像素区之间设置有遮光条。
- 根据权利要求1所述的阵列基板,其中,所述数据线与所述像素电极之间设置有有机绝缘层以隔绝。
- 根据权利要求2所述的阵列基板,其中,还包括与所述像素电极对应的公共电极、以及与所述公共电极电连接的公共电极线。
- 根据权利要求3所述的阵列基板,其中,所述公共电极位于所述数据线背离所述基板的一侧,且所述像素电极位于所述公共电极背离所述数据线 的一侧;所述有机绝缘层位于所述数据线与所述公共电极之间;所述公共电极与所述像素电极之间设置有钝化层以隔绝。
- 根据权利要求3所述的阵列基板,其中,所述遮光条为金属遮光条,且所述金属遮光条与所述公共电极线电性连接。
- 根据权利要求5所述的阵列基板,其中,所述遮光条与所述扫描线同层制备。
- 根据权利要求1所述的阵列基板,其中,所述薄膜晶体管包括依次层叠设置的栅极、栅绝缘层、有源层、绝缘层和与所述有源层电性连接的源、漏电极;其中,所述栅极与所述扫描线同层制备;所述源、漏电极与所述数据线同层设置。
- 根据权利要求3所述的阵列基板,其中,所述扫描信号线中,部分扫描信号线与所述扫描线无电性连接,且所述部分扫描信号线与所述公共电极线电性连接。
- 根据权利要求1所述的阵列基板,其中,所述扫描信号线与所述数据线同层制备。
- 根据权利要求1所述的阵列基板,其中,所述像素电极包括多个间隔设置且依次连接的电极条。
- 根据权利要求1-10任一项所述的阵列基板,其中,还包括沿所述行方向设置并与扫描线对应以用于遮光的遮光层。
- 一种显示面板,其中,包括如权利要求1-11任一项所述的阵列基板。
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