WO2022227343A1 - 晶体管结构、半导体结构及其制备方法 - Google Patents

晶体管结构、半导体结构及其制备方法 Download PDF

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Publication number
WO2022227343A1
WO2022227343A1 PCT/CN2021/113004 CN2021113004W WO2022227343A1 WO 2022227343 A1 WO2022227343 A1 WO 2022227343A1 CN 2021113004 W CN2021113004 W CN 2021113004W WO 2022227343 A1 WO2022227343 A1 WO 2022227343A1
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layer
channel layer
electrode
gate
source electrode
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PCT/CN2021/113004
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English (en)
French (fr)
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薛晖
许文涛
沈宇桐
朴仁镐
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长鑫存储技术有限公司
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Priority to EP21938807.1A priority Critical patent/EP4170701A4/en
Priority to US17/844,061 priority patent/US20220352361A1/en
Publication of WO2022227343A1 publication Critical patent/WO2022227343A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present application relates to, but is not limited to, a transistor structure, a semiconductor structure and a preparation method thereof.
  • DRAM Dynamic Random Access Memory
  • LDD lightly doped drain region
  • NBTI negative bias temperature instability
  • Embodiments of the present application provide a method for preparing a transistor structure, including:
  • the channel layer comprising a two-dimensional layered transition metal material layer
  • a gate dielectric layer on the upper surface of the substrate, the gate dielectric layer covering the channel layer, the source electrode and the drain electrode;
  • a gate is formed on the upper surface of the gate dielectric layer, and the gate is at least directly above the channel layer.
  • Embodiments of the present application also provide a method for preparing a semiconductor structure, including:
  • Two transistor structures are prepared by using the method for preparing a transistor structure as described in the above-mentioned embodiment, which are respectively denoted as a first transistor structure and a second transistor structure; the material of the source electrode and the material of the drain electrode of the first transistor structure The material includes palladium, and the material of the source electrode and the material of the drain electrode of the second transistor structure both include titanium.
  • Embodiments of the present application further provide a transistor structure, including: a gate electrode, a gate dielectric layer, a source electrode, a drain electrode and a channel layer; wherein,
  • the gate dielectric layer is located under the gate; the source electrode and the drain electrode are located under the gate dielectric layer; the channel layer is located under the gate dielectric layer and located at the source Between the electrode and the drain, the channel layer includes a two-dimensional layered transition metal material layer.
  • Embodiments of the present application also provide a semiconductor structure, including:
  • the two transistor structures described in the above embodiments on the substrate are respectively denoted as a first transistor structure and a second transistor structure; the material of the source electrode and the material of the drain electrode of the first transistor structure are both Including palladium, the material of the source electrode and the material of the drain electrode of the second transistor structure both include titanium.
  • FIG. 1 is a flowchart of a method for fabricating a transistor structure provided in an embodiment of the present application.
  • FIGS. 10 and 11 are also transistor structures provided in another embodiment of the present application. Schematic diagram of the structure.
  • FIG. 12 is a flowchart of a method for fabricating a semiconductor structure provided in another embodiment of the present application.
  • FIGS. 23 and 24 are schematic top-view structural diagrams of layouts obtained by each step in the method for fabricating a semiconductor structure provided in an embodiment of the present application; wherein, FIGS. 23 and 24 are also a semiconductor structure provided in another embodiment of the present application. Schematic diagram of the structure.
  • the present application provides a method for preparing a transistor structure, and the method for preparing a transistor structure includes the following steps:
  • the short channel effect can be suppressed without additional doping, the threshold voltage can be reduced, and the saturation current and the reliability of the device can be improved; At the same time, since the step of ion implantation is omitted, the use of the mask can be reduced, the number of process steps can be reduced, and the cost can be reduced.
  • step S11 referring to S11 in FIG. 1 and FIGS. 2 to 3 , a substrate 10 is provided.
  • the substrate 10 may include a substrate 101 and a dielectric layer 102 located on the upper surface of the substrate 101 ; specifically, the substrate 10 may include but is not limited to a silicon substrate, and the dielectric layer 102 may include, but is not limited to, an oxide layer, such as Silicon oxide layer.
  • a channel layer 11 is formed on the upper surface of the substrate 10 , and the channel layer 11 includes a two-dimensional layered transition metal material layer.
  • step S12 may include the following steps:
  • FIG. 2 is a schematic top view of the structure obtained in step S121
  • FIG. 3 is a schematic view along the lines of FIG. 2
  • FIGS. 4 and 5 are schematic top views of the structure obtained in step S122
  • FIG. 5 is Schematic diagram of the cross-sectional structure along the AA direction in FIG. 4 ; specifically, the two-dimensional layered transition metal material film layer 111 may be patterned by, but not limited to, a photolithography etching process.
  • the two-dimensional layered transition metal material layer may include a tungsten selenide layer, that is, the channel layer 11 may include a tungsten selenide layer.
  • the thickness of the two-dimensional layered transition metal material layer is less than 1 nm, that is, the thickness of the channel layer 11 may be less than 1 nm, for example, may be 0.9 nm, 0.5 nm, or 0.1 nm.
  • step S13 please refer to step S13 in FIG. 1 and FIGS. 6 to 7 , wherein FIG. 6 is a schematic top view of the structure obtained in step S13 , and FIG. 7 is a schematic cross-sectional structure along the AA direction in FIG. 6 .
  • a source electrode 12 and a drain electrode 13 are respectively formed on opposite sides of the channel layer 11 .
  • a palladium layer may be formed on the opposite sides of the channel layer 11 as the source electrode 12 and the drain electrode 13 , that is, the material of the source electrode 12 and the material of the drain electrode 13 both include palladium; in this case, the gate electrode is subsequently formed After the dielectric layer and the gate are formed, a PMOS transistor structure can be formed.
  • titanium layers may be formed on opposite sides of the channel layer 11 as the source electrode 12 and the drain electrode 13 , that is, the material of the source electrode 12 and the material of the drain electrode 13 both include titanium; After the gate dielectric layer and the gate are formed, an NMOS transistor structure can be formed.
  • the channel layer 11 is a two-dimensional layered transition metal material layer, no ion implantation is required, and a PMOS transistor structure or an NMOS transistor structure can be formed by contacting metals with different work functions (eg, the above-mentioned palladium or titanium).
  • step S14 please refer to step S14 in FIG. 1 and FIGS. 8 to 9 , wherein FIG. 8 is a schematic top view of the structure obtained in step S14 , and FIG. 9 is a schematic cross-sectional structure along the AA direction in FIG. 8 .
  • a gate dielectric layer 14 is formed on the upper surface of the bottom 10 , and the gate dielectric layer 14 covers the channel layer 11 , the source electrode 12 and the drain electrode 13 .
  • the gate dielectric layer 14 may be formed using, but not limited to, a deposition process.
  • a high-k dielectric layer may be formed on the upper surface of the substrate 10 as the gate dielectric layer 14 , and the gate dielectric layer 14 may include, but is not limited to, a hafnium oxide layer.
  • the thickness of the gate dielectric layer 14 may be 5 nm ⁇ 10 nm, and specifically, the thickness of the gate dielectric layer 14 may be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm.
  • step S15 please refer to step S15 in FIG. 1 and FIGS. 10 to 11 , wherein FIG. 10 is a schematic top view of the structure obtained in step S15 , and FIG. 11 is a schematic cross-sectional structure along the AA direction in FIG. 10 .
  • a gate electrode 15 is formed on the upper surface of the polar dielectric layer 14 , and the gate electrode 14 is at least directly above the channel layer 11 .
  • the gate electrode 15 may include, but is not limited to, a graphene gate electrode; specifically, a single-layer graphene may be used as the gate electrode 15 by wet transfer.
  • a graphene gate electrode specifically, a single-layer graphene may be used as the gate electrode 15 by wet transfer.
  • Using graphene as the gate 15 can avoid the use of a metal gate, thereby avoiding the contamination of the dielectric layer caused by the metal gate and the electrical influence of the device caused by high temperature annealing.
  • step S15 it may further include:
  • the gate electrode may include, but is not limited to, a metal electrode.
  • the metal material layer may be patterned by a photolithography etching process to obtain a metal electrode; A patterned mask layer for the electrode is then deposited to form a metal electrode based on the patterned mask layer.
  • Metal electrodes may include, but are not limited to, aluminum electrodes, copper electrodes, nickel electrodes, or tin electrodes, among others.
  • the transistor structure includes: a gate electrode 15 , a gate dielectric layer 14 , a source electrode 12 , a drain electrode 13 and a channel layer 11 ; wherein the gate dielectric layer 11 ;
  • the layer 14 is located under the gate electrode 15; the source electrode 12 and the drain electrode 13 are located under the gate dielectric layer 14; the channel layer 11 is located under the gate dielectric layer 14, and is located between the source electrode 12 and the drain electrode 13, the channel layer 11 includes a two-dimensional layered transition metal material layer.
  • the short channel effect can be suppressed without additional doping, the threshold voltage can be reduced, the saturation current and the reliability of the device can be improved;
  • the step of ion implantation is omitted, the use of the mask can be reduced, the number of process steps can be reduced, and the cost can be reduced.
  • the transistor structure in this embodiment can be obtained by using the manufacturing method of the transistor structure shown in FIGS. 1 to 12 .
  • the transistor structure is formed on the substrate 10, and the substrate 10 may include a substrate 101 and a dielectric layer 102 on the upper surface of the substrate 101; It may include, but is not limited to, oxide layers, such as silicon oxide layers.
  • the two-dimensional layered transition metal material layer may include a tungsten selenide layer, that is, the channel layer 11 may include a tungsten selenide layer.
  • the thickness of the two-dimensional layered transition metal material layer is less than 1 nm, that is, the thickness of the channel layer 11 may be less than 1 nm, for example, may be 0.9 nm, 0.5 nm, or 0.1 nm.
  • the transistor structure may include a PMOS transistor structure, and the material of the source electrode 12 and the material of the drain electrode 13 both include palladium.
  • the transistor structure may include an NMOS transistor structure, and the material of the source electrode 12 and the material of the drain electrode 13 both include titanium.
  • the channel layer 11 is a two-dimensional layered transition metal material layer, no ion implantation is required, and a PMOS transistor structure or an NMOS transistor structure can be formed by contacting metals with different work functions (eg, the above-mentioned palladium or titanium).
  • the gate dielectric layer 14 may include a high-k dielectric layer, such as a hafnium oxide layer.
  • the thickness of the gate dielectric layer 14 may be 5 nm ⁇ 10 nm, and specifically, the thickness of the gate dielectric layer 14 may be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm.
  • the gate electrode 15 may include, but is not limited to, a graphene gate electrode; specifically, a single-layer graphene may be used as the gate electrode 15 by wet transfer.
  • a graphene gate electrode specifically, a single-layer graphene may be used as the gate electrode 15 by wet transfer.
  • Using graphene as the gate 15 can avoid the use of a metal gate, thereby avoiding the contamination of the dielectric layer caused by the metal gate and the electrical influence of the device caused by high temperature annealing.
  • the transistor structure may also include a gate electrode (not shown) located on the upper surface of the gate 15 .
  • the metal electrodes may include, but are not limited to, aluminum electrodes, copper electrodes, nickel electrodes, tin electrodes, and the like.
  • the present application also provides a method for preparing a semiconductor structure, and the method for preparing a semiconductor structure includes:
  • Two of the transistor structures are prepared by using the method for preparing a transistor structure as described in any of the above solutions, which are respectively denoted as a first transistor structure and a second transistor structure; the material of the source electrode and the drain electrode of the first transistor structure
  • the material of the second transistor structure includes palladium, and the material of the source electrode and the drain electrode of the second transistor structure include titanium.
  • fabricating two of the transistor structures includes:
  • a gate dielectric layer is formed on the upper surface of the substrate, and the gate dielectric layer covers the first channel layer, the second channel layer, the first source, and the first a drain, the second source and the second drain;
  • the first channel layer, the first source electrode, the first drain electrode, the gate dielectric layer and the gate electrode together constitute the first transistor structure
  • the second channel The layer, the second source electrode, the second drain electrode, the gate dielectric layer and the gate electrode together constitute the second transistor structure
  • the short channel effect can be suppressed without additional doping, the threshold voltage can be reduced, and the saturation current and the reliability of the device can be improved;
  • the step of ion implantation is omitted, the use of the mask can be reduced, the number of process steps can be reduced, and the cost can be reduced.
  • step S21 referring to S21 in FIG. 12 and FIGS. 13 to 14 , the substrate 10 is provided.
  • the substrate 10 may include a substrate 101 and a dielectric layer 102 located on the upper surface of the substrate 101 ; specifically, the substrate 10 may include but is not limited to a silicon substrate, and the dielectric layer 102 may include, but is not limited to, an oxide layer, such as Silicon oxide layer.
  • step S22 please refer to step S22 in FIG. 12 and FIGS. 13 to 16 , the first channel layer 112 and the second channel layer 113 arranged at intervals are formed on the upper surface of the substrate 10 .
  • Both the layer 112 and the second channel layer 113 include two-dimensional layered transition metal material layers.
  • step S22 may include:
  • FIG. 13 is a schematic top view of the structure obtained in step S221
  • FIG. 14 is a view along the lines of FIG. 13
  • step S222 patterning the two-dimensional layered transition metal material film layer 111 to obtain the first channel layer 112 and the second channel layer 113 , as shown in FIG. 15 and FIG. 16 , wherein FIG. 15 is the result obtained in step S222 16 is a schematic diagram of a cross-sectional structure along the AA direction in FIG. 15; specifically, the two-dimensional layered transition metal material film layer 111 can be patterned by but not limited to a photolithography etching process.
  • the two-dimensional layered transition metal material layer may include a tungsten selenide layer, that is, both the first channel layer 112 and the second channel layer 113 may include a tungsten selenide layer.
  • the thickness of the two-dimensional layered transition metal material layer is less than 1 nm, that is, the thickness of the first channel layer 112 and the thickness of the second channel layer 113 may be less than 1 nm, for example, may be 0.9 nm, 0.5 nm or 0.1 nm nm and so on.
  • step S23 please refer to step S23 in FIG. 12 and FIGS. 17 to 18, wherein FIG. 17 is a schematic top view of the structure obtained in step S23, and FIG. 18 is a schematic cross-sectional structure along the AA direction in FIG. 17;
  • a first source electrode 121 is formed on a side of the channel layer 112 away from the second channel layer 113
  • a first drain electrode 131 is formed on the side of the first channel layer 112 adjacent to the second channel layer 113 .
  • Both the electrode 121 and the first drain electrode 131 are in contact with the first channel layer 112 ; the material of the first source electrode 112 and the material of the first drain electrode 113 both include palladium.
  • step S23 may include:
  • the first patterned mask layer 16 is formed on the surface of the substrate 10 , the first patterned mask layer 16 at least covers the second channel layer 113 ; specifically, the first patterned mask layer 16 may include but not only Limited to patterned photoresist layers;
  • S233 remove the first patterned mask layer 16 ; specifically, when the first patterned mask layer 16 is a patterned photoresist layer, an ashing process may be used to remove the first patterned mask layer 16 .
  • step S24 please refer to step S24 in FIG. 12 and FIGS. 19 to 20, wherein, FIG. 19 is a schematic top view of the structure obtained in step S24, and FIG. 20 is a schematic cross-sectional structure along the AA direction in FIG. 19;
  • a second source electrode 122 is formed on the side of the second channel layer 113 away from the first channel layer 112 , and a second drain electrode 132 is formed between the second channel layer 113 and the first drain electrode 131 .
  • the second source electrode 122 and the second drain electrode 132 are in contact with the second channel layer 122, and the second drain electrode 132 is in contact with the first drain electrode 131;
  • the material of the second source electrode 122 and the material of the second drain electrode 132 both include titanium .
  • step S24 may include:
  • the second patterned mask layer 17 may include, but is not limited to, a patterned photoresist layer;
  • step S25 please refer to step S25 in FIG. 12 and FIGS. 21 to 22, wherein, FIG. 21 is a schematic top view of the structure obtained in step S25, and FIG. 22 is a schematic cross-sectional structure along the AA direction in FIG. 21;
  • a gate dielectric layer 14 is formed on the upper surface of the bottom 10 , and the gate dielectric layer 14 covers the first channel layer 112 , the second channel layer 113 , the first source electrode 121 , the first drain electrode 131 , the second source electrode 122 and the The second drain 132 .
  • the gate dielectric layer 14 may be formed using, but not limited to, a deposition process.
  • a high-k dielectric layer may be formed on the upper surface of the substrate 10 as the gate dielectric layer 14 , and the gate dielectric layer 14 may include, but is not limited to, a hafnium oxide layer.
  • the thickness of the gate dielectric layer 14 may be 5 nm ⁇ 10 nm, and specifically, the thickness of the gate dielectric layer 14 may be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm.
  • step S26 please refer to step S26 in FIG. 12 and FIG. 23 to FIG. 24, wherein, FIG. 23 is a schematic top view of the structure obtained in step S25, and FIG. 24 is a schematic cross-sectional structure along the AA direction in FIG. 23; A gate 15 is formed on the upper surface of the polar dielectric layer 14 , and the gate 15 extends from right above the first channel layer 112 to right above the second channel layer 113 .
  • the gate electrode 15 may include, but is not limited to, a graphene gate electrode; specifically, a single-layer graphene may be used as the gate electrode 15 by wet transfer.
  • a graphene gate electrode specifically, a single-layer graphene may be used as the gate electrode 15 by wet transfer.
  • Using graphene as the gate 15 can avoid the use of a metal gate, thereby avoiding the contamination of the dielectric layer caused by the metal gate and the electrical influence of the device caused by high temperature annealing.
  • the width of the gate 15 may be smaller than the width of the first channel layer 112 and the width of the second channel layer 113 .
  • the gate 15 may extend to the boundary where the first channel layer 112 and the first source electrode 121 are adjacent to the boundary where the second channel layer 113 and the second source electrode 131 are adjacent.
  • step S26 it may further include:
  • the gate electrode may include, but is not limited to, a metal electrode.
  • the metal material layer may be patterned by a photolithography etching process to obtain a metal electrode; A patterned mask layer for the electrode is then deposited to form a metal electrode based on the patterned mask layer.
  • Metal electrodes may include, but are not limited to, aluminum electrodes, copper electrodes, nickel electrodes, or tin electrodes, among others.
  • the present application further provides a semiconductor structure, including: a substrate 10; The second transistor structure; the material of the source electrode 12 and the material of the drain electrode 13 of the first transistor structure both include palladium, and the material of the source electrode 12 and the material of the drain electrode 13 of the second transistor structure both include titanium.
  • the transistor structure in this application uses the two-dimensional layered transition metal material layer as the channel layer, which can suppress the short channel effect without additional doping, can reduce the threshold voltage, improve the saturation current and the reliability of the device; By removing the step of ion implantation, the use of photomasks can be reduced, process steps and costs can be reduced.
  • the semiconductor structure in this embodiment can be obtained by using the manufacturing method of the semiconductor structure as shown in FIG. 12 to FIG. 24 .
  • the first transistor structure includes: a first channel layer 112, a first source electrode 121, a first drain electrode 131, a gate dielectric layer 14 and a gate electrode 15;
  • the second transistor structure includes: a second channel layer 113 , the second source electrode 122 , the second drain electrode 132 , the gate dielectric layer 14 and the gate electrode 15 .
  • the first transistor structure and the second transistor structure share the same gate dielectric layer 14 and the gate 15 .
  • the first drain 122 of the first transistor and the second drain 132 of the second transistor are located between the first channel layer 112 of the first transistor and the second channel layer 113 of the second transistor, and The first drain 122 is adjacent to the second drain 132 .

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Abstract

本申请提供一种晶体管结构、半导体结构及其制备方法，晶体管结构的制备方法包括：提供衬底；于衬底的上表面形成沟道层，沟道层包括二维层状过渡金属材料层；于沟道层相对的两侧分别形成源极及漏极；于衬底的上表面形成栅极介质层，栅极介质层覆盖沟道层、源极及漏极；于栅极介质层的上表面形成栅极，栅极至少位于沟道层的正上方。本申请中的晶体管结构的制备方法通过形成二维层状过渡金属材料层作为沟道层，无需额外掺杂即可抑制短沟道效应，可降低阈值电压，提高饱和电流及器件的可靠性；同时由于省去了离子注入的步骤，可以减少光罩使用，减少工艺步骤，降低成本。

Description

晶体管结构、半导体结构及其制备方法
本申请要求于2021年4月30日提交中国专利局，申请号为2021104838520，申请名称为“晶体管结构、半导体结构及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及但不限于一种晶体管结构、半导体结构及其制备方法。
背景技术
在DRAM(动态随机存取存储器)的制造领域中，随着尺寸不断缩小(譬如，10nm节点及以下)并追求更快的开关速度和低能耗的需求下，如何控制短沟道效应(short channel effect)变得尤为重要。传统的制造工艺一般采用掺杂技术，如通过掺杂形成halo区域或LDD(轻掺杂漏区)来减少短沟道效应；此外，源极及漏极也需要通过离子注入来形成。然而，传统掺杂手段除了需要高的制造成本外，往往也会在掺杂的同时造成器件可靠性的问题，如硼的瞬间增强扩散，pn结漏电和负偏置温度不稳定(NBTI)等。此外，当器件尺寸进一步缩小时，进行均匀有效的掺杂也变得十分困难。
发明内容
本申请的实施例提供一种晶体管结构的制备方法，包括：
提供衬底；
于所述衬底的上表面形成沟道层，所述沟道层包括二维层状过渡金属材料层；
于所述沟道层相对的两侧分别形成源极及漏极；
于所述衬底的上表面形成栅极介质层，所述栅极介质层覆盖所述沟道层、所述源极及所述漏极；
于所述栅极介质层的上表面形成栅极，所述栅极至少位于所述沟道层的正上方。
本申请的实施例还提供一种半导体结构的制备方法，包括：
采用如上述实施例中所述的晶体管结构的制备方法制备两个所述晶体管结构，分别记为第一晶体管结构及第二晶体管结构；所述第一晶体管结构的源极的材质及漏极的材质均 包括钯，所述第二晶体管结构的源极的材质及漏极的材质均包括钛。
本申请的实施例还提供一种晶体管结构，包括：栅极、栅极介质层、源极、漏极及沟道层；其中，
所述栅极介质层位于所述栅极下方；所述源极及所述漏极位于所述栅极介质层下方；所述沟道层位于所述栅极介质层下方，且位于所述源极与所述漏极之间，所述沟道层包括二维层状过渡金属材料层。
本申请的实施例还提供一种半导体结构，包括：
衬底；
两个位于所述衬底上的如上述实施例中所述的晶体管结构，分别记为第一晶体管结构及第二晶体管结构；所述第一晶体管结构的源极的材质及漏极的材质均包括钯，所述第二晶体管结构的源极的材质及漏极的材质均包括钛。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为本申请一实施例中提供的晶体管结构制备方法的流程图。
图2至图11为本申请一实施例中提供的晶体管结构的制备方法中各步骤得到的版图的俯视结构示意图；其中，图10及图11亦为本申请另一实施例中提供的晶体管结构的结构示意图。
图12为本申请另一实施例中提供的半导体结构制备方法的流程图。
图13至图24为本申请一实施例中提供的半导体结构的制备方法中各步骤得到的版图的俯视结构示意图；其中，图23及图24亦为本申请另一实施例中提供的半导体结构的结构示意图。
附图标记说明：10、衬底；101、基底；102、介质层；11、沟道层；111、二维层状过渡金属材料膜层；112、第一沟道层；113、第二沟道层；12、源极；121、第一源极；122、第二源极；13、漏极；131、第一漏极；132、第二漏极；14、栅极介质层；15、栅极；16、第一图形化掩膜层；17、第二图形化掩膜层。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在使用本文中描述的“包括”、“具有”、和“包含”的情况下，除非使用了明确的限定用语，例如“仅”、“由……组成”等，否则还可以添加另一部件。除非相反地提及，否则单数形式的术语可以包括复数形式，并不能理解为其数量为一个。
请参阅图1，本申请提供一种晶体管结构的制备方法，晶体管结构的制备方法包括如下步骤：
S11：提供衬底；
S12:于衬底的上表面形成沟道层，沟道层包括二维层状过渡金属材料层；
S13:于沟道层相对的两侧分别形成源极及漏极；
S14:于衬底的上表面形成栅极介质层，栅极介质层覆盖沟道层、源极及漏极；
S15：于栅极介质层的上表面形成栅极，栅极至少位于沟道层的正上方。
本申请中的晶体管结构的制备方法通过形成二维层状过渡金属材料层作为沟道层，无需额外掺杂即可抑制短沟道效应，可降低阈值电压，提高饱和电流及器件的可靠性；同时由于省去了离子注入的步骤，可以减少光罩使用，减少工艺步骤，降低成本。
在步骤S11中，请参阅图1中的S11及图2至图3，提供衬底10。
在一个示例中，衬底10可以包括基底101及位于基底101上表面的介质层102；具体的，衬底10可以包括但不仅限于硅衬底，介质层102可以包括但不仅限于氧化层，譬如氧化硅层。
在步骤S12中，请参阅图1中的S12步骤及图2至图5，于衬底10的上表面形成沟道层11，沟道层11包括二维层状过渡金属材料层。
在一个示例中，步骤S12可以包括如下步骤：
S121：于衬底10的上表面形成二维层状过渡金属材料膜层111，如图2及图3所示，其中，图2为步骤S121所得结构的俯视结构示意图，图3为沿图2中AA方向的截面结构示意图；具体的，可以采用但不仅限于湿法转移工艺形成二维层状过渡金属材料膜层111；
S122：对二维层状过渡金属材料膜层111进行图形化，以得到沟道层11，如图4及图5所示，其中，图4为步骤S122所得结构的俯视结构示意图，图5为沿图4中AA方向的截面结构示意图；具体的，可以采用但不仅限于光刻刻蚀工艺对二维层状过渡金属材料膜层111进行图形化。
在一个示例中，二维层状过渡金属材料层可以包括硒化钨层，即沟道层11可以包括硒化钨层。
在一个示例中，二维层状过渡金属材料层的厚度小于1nm，即沟道层11可以的厚度可以小于1nm，譬如，可以为0.9nm、0.5nm或0.1nm等等。
在步骤S13中，请参阅图1中的S13步骤及图6至图7，其中，图6为步骤S13所得结构的俯视结构示意图，图7为沿图6中AA方向的截面结构示意图，于沟道层11相对的两侧分别形成源极12及漏极13。
在一个示例中，可以在沟道层11相对的两侧形成钯层作为源极12及漏极13，即源极12的材质及漏极13的材质均包括钯；此时，在后续形成栅极介质层及栅极后，可以形成PMOS晶体管结构。
在另一个示例中，可以在沟道层11相对的两侧形成钛层作为源极12及漏极13，即源极12的材质及漏极13的材质均包括钛；此时，在后续形成栅极介质层及栅极后，可以形成NMOS晶体管结构。
由于沟道层11为二维层状过渡金属材料层，无需进行离子注入，通过与不同功函数的金属(譬如上述的钯或钛)接触即可形成PMOS晶体管结构或NMOS晶体管结构。
在步骤S14中，请参阅图1中的S14步骤及图8至图9，其中，图8为步骤S14所得结构的俯视结构示意图，图9为沿图8中AA方向的截面结构示意图，于衬底10的上表面形成栅极介质层14，栅极介质层14覆盖沟道层11、源极12及漏极13。
在一个示例中，可以采用但不仅限于沉积工艺形成栅极介质层14。
在一个示例中，可以于衬底10的上表面形成高k介质层作为栅极介质层14，栅极介质层14可以包括但不仅限于氧化铪层。
具体的，栅极介质层14的厚度可以为5nm～10nm，具体的，栅极介质层14的厚度可 以为5nm、6nm、7nm、8nm、9nm或10nm。
在步骤S15中，请参阅图1中的S15步骤及图10至图11，其中，图10为步骤S15所得结构的俯视结构示意图，图11为沿图10中AA方向的截面结构示意图，于栅极介质层14的上表面形成栅极15，栅极14至少位于沟道层11的正上方。
在一个示例中，栅极15可以包括但不仅限于石墨烯栅极；具体的，可以通过湿法转移单层石墨烯作为栅极15。采用石墨烯作为栅极15，可以避免金属栅极的使用，从而避免由于金属栅极造成的电介质层污染及高温退火时造成的器件电性影响。
在一个示例中，步骤S15之后还可以包括：
S16：于栅极15的上表面形成栅极电极(未示出)。具体的，栅极电极可以包括但不仅限于金属电极，可以采用沉积工艺形成金属材料层后，再通过光刻刻蚀工艺对金属材料层进行图形化以得到金属电极；也可以先形成定义出金属电极的图形化掩膜层，然后再基于图形化掩膜层沉积形成金属电极。金属电极可以包括但不仅限于铝电极、铜电极、镍电极或锡电极等等。
请继续参阅图10至图11，本申请还提供一种晶体管结构，晶体管结构包括：栅极15、栅极介质层14、源极12、漏极13及沟道层11；其中，栅极介质层14位于栅极15下方；源极12及漏极13位于栅极介质层14下方；沟道层11位于栅极介质层14下方，且位于源极12与漏极13之间，沟道层11包括二维层状过渡金属材料层。
本申请中的晶体管结构通过将二维层状过渡金属材料层作为沟道层11，无需额外掺杂即可抑制短沟道效应，可降低阈值电压，提高饱和电流及器件的可靠性；同时由于省去了离子注入的步骤，可以减少光罩使用，减少工艺步骤，降低成本。
具体的，本实施例中的晶体管结构可以采用图1至图12的晶体管结构的制备方法制备而得到。
在一个示例中，晶体管结构形成于衬底10上，衬底10可以包括基底101及位于基底101上表面的介质层102；具体的，衬底10可以包括但不仅限于硅衬底，介质层102可以包括但不仅限于氧化层，譬如氧化硅层。
在一个示例中，二维层状过渡金属材料层可以包括硒化钨层，即沟道层11可以包括硒化钨层。
在一个示例中，二维层状过渡金属材料层的厚度小于1nm，即沟道层11可以的厚度可以小于1nm，譬如，可以为0.9nm、0.5nm或0.1nm等等。
在其中一个示例中，晶体管结构可以包括PMOS晶体管结构，源极12的材质及漏极 13的材质均包括钯。
在另一个示例中，晶体管结构可以包括NMOS晶体管结构，源极12的材质及漏极13的材质均包括钛。
由于沟道层11为二维层状过渡金属材料层，无需进行离子注入，通过与不同功函数的金属(譬如上述的钯或钛)接触即可形成PMOS晶体管结构或NMOS晶体管结构。
在一个示例中，栅极介质层14可以包括高k介质层，譬如氧化铪层。
具体的，栅极介质层14的厚度可以为5nm～10nm，具体的，栅极介质层14的厚度可以为5nm、6nm、7nm、8nm、9nm或10nm。
在一个示例中，栅极15可以包括但不仅限于石墨烯栅极；具体的，可以通过湿法转移单层石墨烯作为栅极15。采用石墨烯作为栅极15，可以避免金属栅极的使用，从而避免由于金属栅极造成的电介质层污染及高温退火时造成的器件电性影响。
在一个示例中，晶体管结构还可以包括栅极电极(未示出)，栅极电极位于栅极15的上表面。
具体的，金属电极可以包括但不仅限于铝电极、铜电极、镍电极或锡电极等等。
本申请还提供一种半导体结构的制备方法，半导体结构的制备方法包括：
采用如上述任一方案中所述的晶体管结构的制备方法制备两个所述晶体管结构，分别记为第一晶体管结构及第二晶体管结构；所述第一晶体管结构的源极的材质及漏极的材质均包括钯，所述第二晶体管结构的源极的材质及所述漏极的材质均包括钛。
在一个示例中，请参阅图12，制备两个所述晶体管结构包括：
S21：提供衬底；
S22：于所述衬底的上表面形成间隔排布的第一沟道层及第二沟道层，所述第一沟道层及所述第二沟道层均包括二维层状过渡金属材料层；
S23：于所述第一沟道层远离所述第二沟道层的一侧形成第一源极，并于所述第一沟道层邻近所述第二沟道层的一侧形成第一漏极，所述第一源极及所述第一漏极均与所述第一沟道层相接触；所述第一源极的材质及所述第一漏极的材质均包括钯；
S24：于所述第二沟道层远离所述第一沟道层的一侧形成第二源极，并于所述第二沟道层与所述第一漏极之间形成第二漏极，所述第二源极及所述第二漏极均与所述第二沟道层相接触，且所述第二漏极与所述第一漏极相接触；所述第二源极的材质及所述第二漏极的材质均包括钛；
S25：于所述衬底的上表面形成栅极介质层，所述栅极介质层覆盖所述第一沟道层、 所述第二沟道层、所述第一源极、所述第一漏极、所述第二源极及所述第二漏极；
S26：于所述栅极介质层的上表面形成栅极，所述栅极自所述第一沟道层的正上方延伸至所述第二沟道层的正上方；
其中，所述第一沟道层、所述第一源极、所述第一漏极、所述栅极介质层及所述栅极共同构成所述第一晶体管结构，所述第二沟道层、所述第二源极、所述第二漏极、所述栅极介质层及所述栅极共同构成所述第二晶体管结构。
本申请中的半导体结构的制备方法通过形成二维层状过渡金属材料层作为沟道层，无需额外掺杂即可抑制短沟道效应，可降低阈值电压，提高饱和电流及器件的可靠性；同时由于省去了离子注入的步骤，可以减少光罩使用，减少工艺步骤，降低成本。
在步骤S21中，请参阅图12中的S21及图13至图14，提供衬底10。
在一个示例中，衬底10可以包括基底101及位于基底101上表面的介质层102；具体的，衬底10可以包括但不仅限于硅衬底，介质层102可以包括但不仅限于氧化层，譬如氧化硅层。
在步骤S22中，请参阅图12中的S22步骤及图13至图16，于衬底10的上表面形成间隔排布的第一沟道层112及第二沟道层113，第一沟道层112及所述第二沟道层113均包括二维层状过渡金属材料层。
在一个示例中，步骤S22可以包括：
S221：于衬底10的上表面形成二维层状过渡金属材料膜层111，如图13及图14所示，其中，图13为步骤S221所得结构的俯视结构示意图，图14为沿图13中AA方向的截面结构示意图；具体的，可以采用但不仅限于湿法转移工艺形成二维层状过渡金属材料膜层111；
S222：对二维层状过渡金属材料膜层111进行图形化，以得到第一沟道层112及第二沟道层113，如图15及图16所示，其中，图15为步骤S222所得结构的俯视结构示意图，图16为沿图15中AA方向的截面结构示意图；具体的，可以采用但不仅限于光刻刻蚀工艺对二维层状过渡金属材料膜层111进行图形化。
在一个示例中，二维层状过渡金属材料层可以包括硒化钨层，即第一沟道层112及第二沟道层113均可以包括硒化钨层。
在一个示例中，二维层状过渡金属材料层的厚度小于1nm，即第一沟道层112及第二沟道层113的厚度均可以小于1nm，譬如，可以为0.9nm、0.5nm或0.1nm等等。
在步骤S23中，请参阅图12中的S23步骤及图17至图18，其中，图17为步骤S23 所得结构的俯视结构示意图，图18为沿图17中AA方向的截面结构示意图；于第一沟道层112远离第二沟道层113的一侧形成第一源极121，并于第一沟道层112邻近第二沟道层113的一侧形成第一漏极131，第一源极121及第一漏极131均与第一沟道层112相接触；第一源极112的材质及第一漏极113的材质均包括钯。
在一个示例中，步骤S23可以包括：
S231：于衬底10的表面形成第一图形化掩膜层16，第一图形化掩膜层16至少覆盖第二沟道层113；具体的，第一图形化掩膜层16可以包括但不仅限于图形化光刻胶层；
S232：基于第一图形化掩膜层16于衬底10的表面形成第一源极121及第一漏极131；
S233：去除第一图形化掩膜层16；具体的，当第一图形化掩膜层16为图形化光刻胶层时，可以采用灰化工艺去除第一图形化掩膜层16。
在步骤S24中，请参阅图12中的S24步骤及图19至图20，其中，图19为步骤S24所得结构的俯视结构示意图，图20为沿图19中AA方向的截面结构示意图；于第二沟道层113远离第一沟道层112的一侧形成第二源极122，并于第二沟道层113与第一漏极131之间形成第二漏极132，第二源极122及第二漏极132均与第二沟道层122相接触，且第二漏极132与第一漏极131相接触；第二源极122的材质及第二漏极132的材质均包括钛。
在一个示例中，步骤S24可以包括：
S241：于衬底10的表面形成第二图形化掩膜层17，第二图形化掩膜层17至少覆盖第一沟道层112、第一源极121及第一漏极131；具体的，第二图形化掩膜层17可以包括但不仅限于图形化光刻胶层；
S242：基于第二图形化掩膜层17于衬底10的表面形成第二源极122及第二漏极132；
S243：去除第二图形化掩膜层17；具体的，当第二图形化掩膜层17为图形化光刻胶层时，可以采用灰化工艺去除第二图形化掩膜层17。
在步骤S25中，请参阅图12中的S25步骤及图21至图22，其中，图21为步骤S25所得结构的俯视结构示意图，图22为沿图21中AA方向的截面结构示意图；于衬底10的上表面形成栅极介质层14，栅极介质层14覆盖第一沟道层112、第二沟道层113、第一源极121、第一漏极131、第二源极122及第二漏极132。
在一个示例中，可以采用但不仅限于沉积工艺形成栅极介质层14。
在一个示例中，可以于衬底10的上表面形成高k介质层作为栅极介质层14，栅极介质层14可以包括但不仅限于氧化铪层。
具体的，栅极介质层14的厚度可以为5nm～10nm，具体的，栅极介质层14的厚度可 以为5nm、6nm、7nm、8nm、9nm或10nm。
在步骤S26中，请参阅图12中的S26步骤及图23至图24，其中，图23为步骤S25所得结构的俯视结构示意图，图24为沿图23中AA方向的截面结构示意图；于栅极介质层14的上表面形成栅极15，栅极15自第一沟道层112的正上方延伸至第二沟道层113的正上方。
在一个示例中，栅极15可以包括但不仅限于石墨烯栅极；具体的，可以通过湿法转移单层石墨烯作为栅极15。采用石墨烯作为栅极15，可以避免金属栅极的使用，从而避免由于金属栅极造成的电介质层污染及高温退火时造成的器件电性影响。
在一个示例中，栅极15的宽度可以小于第一沟道层112的宽度及第二沟道层113的宽度。栅极15可以与第一沟道层112与第一源极121相邻接的边界延伸至第二沟道层113与第二源极131相邻接的边界。
在一个示例中，步骤S26之后还可以包括：
S27：于栅极15的上表面形成栅极电极(未示出)。具体的，栅极电极可以包括但不仅限于金属电极，可以采用沉积工艺形成金属材料层后，再通过光刻刻蚀工艺对金属材料层进行图形化以得到金属电极；也可以先形成定义出金属电极的图形化掩膜层，然后再基于图形化掩膜层沉积形成金属电极。金属电极可以包括但不仅限于铝电极、铜电极、镍电极或锡电极等等。
请继续参阅图23至图24，本申请还提供一种半导体结构，包括：衬底10；两个位于衬底10上的如上述任一方案中的晶体管结构，分别记为第一晶体管结构及第二晶体管结构；第一晶体管结构的源极12的材质及漏极13的材质均包括钯，所述第二晶体管结构的源极12的材质及漏极13的材质均包括钛。
本申请中的晶体管结构通过将二维层状过渡金属材料层作为沟道层，无需额外掺杂即可抑制短沟道效应，可降低阈值电压，提高饱和电流及器件的可靠性；同时由于省去了离子注入的步骤，可以减少光罩使用，减少工艺步骤，降低成本。
具体的，本实施例中的半导体结构可以采用如图12至图24的半导体结构的制备方法制备而得到。
更具体的，第一晶体管结构包括：第一沟道层112、第一源极121、第一漏极131、栅极介质层14及栅极15；第二晶体管结构包括：第二沟道层113、第二源极122、第二漏极132、栅极介质层14及栅极15。第一晶体管结构与第二晶体管结构共用同一层栅极介质层14且共用栅极15。
在一个示例中，第一晶体管的第一漏极122及第二晶体管的第二漏极132位于第一晶体管的第一沟道层112与第二晶体管的第二沟道层113之间，且第一漏极122与第二漏极132相邻接。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种晶体管结构的制备方法，包括：
    提供衬底；
    于所述衬底的上表面形成沟道层，所述沟道层包括二维层状过渡金属材料层；
    于所述沟道层相对的两侧分别形成源极及漏极；
    于所述衬底的上表面形成栅极介质层，所述栅极介质层覆盖所述沟道层、所述源极及所述漏极；
    于所述栅极介质层的上表面形成栅极，所述栅极至少位于所述沟道层的正上方。
  2. 根据权利要求1所述的晶体管结构的制备方法，其中，所述二维层状过渡金属材料层包括硒化钨层；所述二维层状过渡金属材料层的厚度小于1nm。
  3. 根据权利要求1所述的晶体管结构的制备方法，其中，所述源极的材质及所述漏极的材质均包括钯或所述源极的材质及所述漏极的材质均包括钛。
  4. 根据权利要求1所述的晶体管结构的制备方法，还包括：在所述于所述栅极介质层的上表面形成栅极之后，于所述栅极的上表面形成栅极电极。
  5. 根据权利要求1所述的晶体管结构的制备方法，其中，于所述衬底的上表面形成高k介质层作为所述栅极介质层；于所述栅极介质层的上表面形成石墨烯层作为所述栅极。
  6. 一种半导体结构的制备方法，包括：
    采用如权利要求1至5中任一项所述的晶体管结构的制备方法制备两个所述晶体管结构，分别记为第一晶体管结构及第二晶体管结构；所述第一晶体管结构的源极的材质及漏极的材质均包括钯，所述第二晶体管结构的源极的材质及漏极的材质均包括钛。
  7. 根据权利要求6所述的半导体结构的制备方法，其中，所述采用如权利要求1至5中任一项所述的晶体管结构的制备方法制备两个所述晶体管结构包括：
    提供衬底；
    于所述衬底的上表面形成间隔排布的第一沟道层及第二沟道层，所述第一沟道层及所述第二沟道层均包括二维层状过渡金属材料层；
    于所述第一沟道层远离所述第二沟道层的一侧形成第一源极，并于所述第一沟道层邻近所述第二沟道层的一侧形成第一漏极，所述第一源极及所述第一漏极均与所述第一沟道层相接触；所述第一源极的材质及所述第一漏极的材质均包括钯；
    于所述第二沟道层远离所述第一沟道层的一侧形成第二源极，并于所述第二沟道层与 所述第一漏极之间形成第二漏极，所述第二源极及所述第二漏极均与所述第二沟道层相接触，且所述第二漏极与所述第一漏极相接触；所述第二源极的材质及所述第二漏极的材质均包括钛；
    于所述衬底的上表面形成栅极介质层，所述栅极介质层覆盖所述第一沟道层、所述第二沟道层、所述第一源极、所述第一漏极、所述第二源极及所述第二漏极；
    于所述栅极介质层的上表面形成栅极，所述栅极自所述第一沟道层的正上方延伸至所述第二沟道层的正上方；
    其中，所述第一沟道层、所述第一源极、所述第一漏极、所述栅极介质层及所述栅极共同构成所述第一晶体管结构，所述第二沟道层、所述第二源极、所述第二漏极、所述栅极介质层及所述栅极共同构成所述第二晶体管结构。
  8. 根据权利要求7所述的半导体结构的制备方法，其中，所述于所述衬底的上表面形成间隔排布的第一沟道层及第二沟道层包括：
    于所述衬底的表面形成二维层状过渡金属材料膜层；
    对所述二维层状过渡金属材料膜层进行图形化，以得到所述第一沟道层及所述第二沟道层。
  9. 根据权利要求7所述的半导体结构的制备方法，其中，所述于所述第一沟道层远离所述第二沟道层的一侧形成第一源极，并于所述第一沟道层邻近所述第二沟道层的一侧形成第一漏极包括：
    于所述衬底的表面形成第一图形化掩膜层，所述第一图形化掩膜层至少覆盖所述第二沟道层；
    基于所述第一图形化掩膜层于所述衬底的表面形成所述第一源极及所述第一漏极；
    去除所述第一图形化掩膜层。
  10. 根据权利要求7所述的半导体结构的制备方法，其中，所述于所述第二沟道层远离所述第一沟道层的一侧形成第二源极，并于所述第二沟道层与所述第一漏极之间形成第二漏极包括：
    于所述衬底的表面形成第二图形化掩膜层，所述第二图形化掩膜层至少覆盖所述第一沟道层、所述第一源极及所述第一漏极；
    基于所述第二图形化掩膜层于所述衬底的表面形成第二源极及所述第二漏极；
    去除所述第二图形化掩膜层。
  11. 一种晶体管结构，包括：栅极、栅极介质层、源极、漏极及沟道层；其中，
    所述栅极介质层位于所述栅极下方；所述源极及所述漏极位于所述栅极介质层下方；所述沟道层位于所述栅极介质层下方，且位于所述源极与所述漏极之间，所述沟道层包括二维层状过渡金属材料层。
  12. 根据权利要求11所述的晶体管结构，其中，所述栅极包括石墨烯栅极；所述栅极介质层包括高k介质层。
  13. 根据权利要求11所述的晶体管结构，其中，所述二维层状过渡金属材料层包括硒化钨层，所述沟道层的厚度小于1nm。
  14. 根据权利要求11所述的晶体管结构，其中，所述源极的材质及所述漏极的材质均包括钯或所述源极的材质及所述漏极的材质均包括钛。
  15. 根据权利要求11至14中任一项所述的晶体管结构，还包括栅极电极，所述栅极电极位于所述栅极的上表面。
  16. 一种半导体结构，包括：
    衬底；
    两个位于所述衬底上的如权利要求11至15中任一项所述的晶体管结构，分别记为第一晶体管结构及第二晶体管结构；所述第一晶体管结构的源极的材质及漏极的材质均包括钯，所述第二晶体管结构的源极的材质及漏极的材质均包括钛。
  17. 根据权利要求16所述的半导体结构，其中，所述第一晶体管的漏极及所述第二晶体管的漏极位于所述第一晶体管的沟道层与所述第二晶体管的沟道层之间，且相邻接。
  18. 根据权利要求16所述的半导体结构，其中，所述第一晶体管与所述第二晶体管共用所述栅极。
PCT/CN2021/113004 2021-04-30 2021-08-17 晶体管结构、半导体结构及其制备方法 WO2022227343A1 (zh)

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