WO2022227338A1 - 半导体结构的制备方法 - Google Patents

半导体结构的制备方法 Download PDF

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Publication number
WO2022227338A1
WO2022227338A1 PCT/CN2021/111890 CN2021111890W WO2022227338A1 WO 2022227338 A1 WO2022227338 A1 WO 2022227338A1 CN 2021111890 W CN2021111890 W CN 2021111890W WO 2022227338 A1 WO2022227338 A1 WO 2022227338A1
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layer
transistor
oxide layer
semiconductor structure
region
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PCT/CN2021/111890
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English (en)
French (fr)
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白杰
尤康
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长鑫存储技术有限公司
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Priority to EP21935429.7A priority Critical patent/EP4120333A4/en
Priority to US17/651,577 priority patent/US20220352175A1/en
Publication of WO2022227338A1 publication Critical patent/WO2022227338A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, and in particular, to a method for preparing a semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • the DRAM device includes a substrate on which a peripheral area, a core area and a plurality of array areas are arranged, wherein the core area surrounds the outer periphery of the array area, and the peripheral area surrounds the outer periphery of the core area.
  • Memory cells are arranged in the array area, and each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to a word line (WL for short), the drain is connected to the bit line, and the source is connected to the capacitor.
  • the peripheral area is provided with a drive circuit, a clock circuit, and the like.
  • the core region includes a P-type transistor and an N-type transistor, and a SiGe layer is embedded in the channel region of the P-type transistor to improve carrier mobility, thereby improving the storage performance of the DRAM device.
  • the above-mentioned preparation method of the DRAM device causes great damage to the SiGe layer, which affects the storage performance of the DRAM device.
  • the present application provides a preparation method of a semiconductor structure, which can reduce the damage to the epitaxial layer of the preparation method of the semiconductor structure and improve the storage performance of the semiconductor structure.
  • the present application provides a method for preparing a semiconductor structure, comprising:
  • a substrate is provided; the substrate includes an array area and a non-array area, the non-array area surrounds the outer periphery of the array area, and the non-array area includes a first transistor area and a second transistor area.
  • a mask layer is formed on the substrate.
  • the mask layer on the non-array area is removed.
  • a first oxide layer is formed on the non-array region.
  • the first oxide layer on the first transistor region is removed to expose a top surface on the first transistor region.
  • An epitaxial layer is formed on the exposed top surface of the first transistor region.
  • the first oxide layer on the second transistor region is removed.
  • a second oxide layer is formed on both the second transistor region and the epitaxial layer.
  • the structural layer in the array area can be protected to prevent the structural layer in the array area from being damaged, and the mask layer on the non-array area can be exposed by removing the mask layer.
  • the substrate of the non-array area by forming a first oxide layer on the substrate surface of the non-array area, can be used as a barrier layer or insulating layer for the structure on the non-array area, and by removing the first oxide layer on the first transistor area, it can be The substrate of the first transistor region is exposed.
  • the first oxide layer can also function as a mask to facilitate the formation of an epitaxial layer on the exposed substrate surface of the first transistor region.
  • the substrate of the second transistor region By removing the first oxide layer on the second transistor region layer, the substrate of the second transistor region can be exposed, so that the second oxide layer can be formed on the surface of the substrate of the second transistor region.
  • the above preparation method the formation of the epitaxial layer is arranged after the formation of the first oxide layer, on the one hand, the first oxide layer can be used.
  • the oxide layer acts as a mask to inhibit the growth of the epitaxial layer on other substrates other than the first transistor region.
  • wet etching to remove the damage to the epitaxial layer of the mask layer is avoided, and the formation of the epitaxial layer is delayed. , avoids setting the epitaxial layer prematurely, reduces the damage to the epitaxial layer due to excessive cleaning processes, reduces the damage to the epitaxial layer in the preparation method of the semiconductor structure, and improves the storage performance of the semiconductor structure.
  • FIG. 1 is a schematic structural diagram of a device of the related art after the hard mask layer of the PMOS in the core region is removed during the preparation process;
  • FIG. 2 is a schematic structural diagram of a device of the related art after the deposition of the SiGe layer of the PMOS in the core region during the preparation process;
  • FIG. 3 is a schematic structural diagram of the device of the related art after the hard mask layer is removed during the preparation process
  • FIG. 4 is a schematic structural diagram of a device of the related art after the deposition of a thick gate oxide layer during the preparation process
  • FIG. 5 is a schematic structural diagram of the device of the related art after the thick gate oxide layer in the core region is removed during the preparation process;
  • FIG. 6 is a schematic structural diagram of a device of the related art after the deposition of a thin gate oxide layer during the preparation process
  • FIG. 7 is a schematic flowchart of a method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • FIG. 8 is a schematic flowchart of a work function adjustment process of a method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram after the formation of a mask layer in the method for preparing a semiconductor structure provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram after the mask layer is removed in the preparation method of the semiconductor structure provided by the embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of the semiconductor structure after the formation of the first oxide layer in the method for preparing the semiconductor structure provided by the embodiment of the present application;
  • FIG. 13 is a schematic structural diagram of the first oxide layer in the first transistor region after removal of the first oxide layer in the method for fabricating the semiconductor structure provided by the embodiment of the present application;
  • FIG. 14 is a schematic structural diagram of a semiconductor structure after an epitaxial layer is formed in the method for preparing a semiconductor structure provided by an embodiment of the present application;
  • 15 is a schematic structural diagram after the first oxide layer on the second transistor region is removed in the preparation method of the semiconductor structure provided by the embodiment of the application;
  • FIG. 16 is a schematic structural diagram after the formation of the second oxide layer in the preparation method of the semiconductor structure provided by the embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of a first mask layer in a method for preparing a semiconductor structure provided by an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of a second mask layer in the method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • DRAM Dynamic Random Access Memory
  • the DRAM device includes a substrate on which a peripheral area, a core area and a plurality of array areas are arranged, wherein the core area surrounds the outer periphery of the array area, and the peripheral area surrounds the outer periphery of the core area.
  • Memory cells are arranged in the array area, and each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to a word line (WL for short), the drain is connected to the bit line, and the source is connected to the capacitor.
  • the peripheral area is provided with a drive circuit, a clock circuit, and the like.
  • the core region includes a P-type transistor and an N-type transistor, and a SiGe layer is usually embedded in the channel region of the P-type transistor to improve carrier mobility, thereby improving the storage performance of the DRAM device.
  • FIG. 1 is a schematic structural diagram of a device of the related art after the hard mask layer of the PMOS in the core region is removed during the fabrication process.
  • FIG. 2 is a schematic structural diagram of a device of the related art after the deposition of the SiGe layer of the PMOS in the core region during the fabrication process.
  • FIG. 3 is a schematic structural diagram of a device of the related art after the hard mask layer is removed during the fabrication process.
  • FIG. 4 is a schematic structural diagram of a device of the related art after a thick gate oxide layer is deposited during the fabrication process.
  • FIG. 5 is a schematic structural diagram of the device of the related art after the thick gate oxide layer in the core region is removed during the fabrication process.
  • FIG. 6 is a schematic structural diagram of a device of the related art after a thin gate oxide layer is deposited during the fabrication process.
  • the following method when fabricating devices in the core region, the following method is usually used: first, remove the hard mask layer 5 on the core region PMOS2 to expose the top surface on the core region PMOS2 .
  • a SiGe layer 6 is then deposited on the top surface of the core region PMOS2.
  • the hard mask layer 5 on the core region NMOS1, the peripheral region PMOS4 and the peripheral region NMOS3 is removed by wet etching, exposing the top surfaces of the core region NMOS1, the peripheral region PMOS4 and the peripheral region NMOS3.
  • a thick gate oxide layer 7 is deposited on the core region PMOS2, the core region NMOS1, the peripheral region PMOS4 and the peripheral region NMOS3.
  • the thick gate oxide layer 7 on the core region PMOS2 and the core region NMOS1 is removed.
  • a thin gate oxide layer 8 is deposited on the core region PMOS2 and the core region NMOS1.
  • the above-mentioned preparation method will cause damage to the SiGe layer 6 when the hard mask layer 5 is removed by wet etching after the SiGe layer 6 is deposited, and the SiGe layer 6 is repeatedly contacted with the cleaning process in the subsequent preparation, so that the SiGe layer is 6
  • the damage is relatively large, thereby affecting the storage performance of the DRAM device.
  • the structural layer in the array area can be protected, the structural layer in the array area can be prevented from being damaged, and the mask on the non-array area can be removed.
  • the substrate of the non-array area can be exposed, by forming a first oxide layer on the substrate surface of the non-array area, it can be used as a barrier layer or insulating layer for the structure on the non-array area, by removing the first transistor area on the first transistor area
  • the oxide layer can expose the substrate of the first transistor region.
  • the first oxide layer can also function as a mask to facilitate the formation of an epitaxial layer on the exposed substrate surface of the first transistor region.
  • the first oxide layer can expose the substrate of the second transistor region, so as to facilitate the formation of the second oxide layer on the surface of the substrate in the second transistor region, the above preparation method, the formation of the epitaxial layer is arranged after the formation of the first oxide layer, on the one hand
  • the first oxide layer can be used as a mask to inhibit the growth of the epitaxial layer on other substrates other than the first transistor region.
  • wet etching to remove the damage to the epitaxial layer of the mask layer is avoided.
  • the forming step is delayed to avoid setting the epitaxial layer prematurely, reducing the damage to the epitaxial layer due to excessive cleaning processes, reducing the damage to the epitaxial layer in the preparation method of the semiconductor structure, and improving the storage performance of the semiconductor structure.
  • FIG. 7 is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present application.
  • FIG. 8 is a schematic flowchart of a work function adjustment process of a method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 10 is a schematic view of the structure after the mask layer is formed in the method for fabricating the semiconductor structure provided by the embodiment of the present application.
  • FIG. 11 is a schematic view of the structure after the mask layer is removed in the method for fabricating the semiconductor structure provided by the embodiment of the present application.
  • FIG. 10 is a schematic view of the structure after the mask layer is formed in the method for fabricating the semiconductor structure provided by the embodiment of the present application.
  • FIG. 12 is a schematic view of the structure after the formation of the first oxide layer in the method for fabricating the semiconductor structure provided by the embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of the first oxide layer in the first transistor region after removing the first oxide layer in the method for fabricating the semiconductor structure provided by the embodiment of the present application.
  • FIG. 14 is a schematic view of the structure after the formation of the epitaxial layer in the method for fabricating the semiconductor structure provided by the embodiment of the present application.
  • FIG. 15 is a schematic view of the structure after the first oxide layer on the second transistor region is removed in the method for fabricating the semiconductor structure provided by the embodiment of the present application.
  • FIG. 16 is a schematic view of the structure after the formation of the second oxide layer in the method for fabricating the semiconductor structure provided by the embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of a mask layer in a method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of a second mask layer in the method for fabricating a semiconductor structure provided by an embodiment of the present application. Referring to FIGS. 7-18 , embodiments of the present application provide a method for fabricating a semiconductor structure.
  • the preparation method of the semiconductor structure specifically includes:
  • the substrate 10 includes an array area 11 and a non-array area, the non-array area surrounds the outer periphery of the array area 11 , and the non-array area includes a first transistor area 14 and a second transistor area 15 .
  • the material of the substrate 10 may be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound or silicon-on-insulator (Silicon-On-Insulator, SOI for short), etc., or known to those skilled in the art Other materials, the substrate 10 can provide a support base for the structural layers on the substrate 10 .
  • the substrate 10 is a Si substrate.
  • FIG. 9 is only a partial structural schematic diagram of the semiconductor structure 100 , and does not represent the entire structure of the semiconductor structure 100 .
  • a plurality of array regions 11 may be arranged in an array on the substrate 10 . Between adjacent array areas 11 is the core area 12, and the periphery of the core area 12 is the peripheral area 13.
  • the array area 11 is provided with memory cells
  • the core area 12 is provided with sense amplifiers, etc.
  • the peripheral area 13 is provided with peripheral circuits, drivers circuits and clock circuits, etc.
  • the peripheral region 13 may further include a third transistor region 16 and a fourth transistor region 17, and the third transistor region 16 and the fourth transistor region 17 may be specifically used to form a driving circuit, a clock circuit, and the like.
  • S2 forming a mask layer on the substrate.
  • the mask layer 20 on the substrate 10 the structure layer of the array region 11 can be protected to prevent the structure layer of the array region 11 from being damaged.
  • the oxide layer can block the intrusion of dirty substances into the surface of the substrate 10 to play a blocking role, and on the other hand, it also has an insulating function, so that the first oxide layer 30 can As a barrier or insulating layer for structures on non-array regions.
  • S6 An epitaxial layer is formed on the exposed top surface of the first transistor region. In this way, a structure layer with higher carrier mobility can be formed on the substrate 10 .
  • the specific structure after each step can be referred to as shown in FIGS. 10-16 .
  • the formation of the epitaxial layer 40 is arranged after the formation of the first oxide layer 30.
  • the first oxide layer 30 can be used as a mask.
  • the use of wet etching to remove the damage to the epitaxial layer 40 of the mask layer 20 is avoided.
  • the formation step of the epitaxial layer 40 is delayed to avoid setting the epitaxial layer 40 prematurely, reducing the excessive cleaning process.
  • the damage to the epitaxial layer 40 reduces the damage to the epitaxial layer 40 in the manufacturing method of the semiconductor structure, and improves the storage performance of the semiconductor structure 100 .
  • the step of providing the substrate may include: forming sequentially arranged source regions, channel regions and drain regions in the first transistor region by ion implantation.
  • ion implantation is the doping process of choice for circuits with high density and small feature size.
  • the doping structure can be formed on the substrate 10 through an ion implantation process.
  • a mask can be used to protect the substrate 10 in the channel region, and doping can be formed on the substrate 10 in the source region and the drain region. structure to form source and drain regions.
  • the non-array area includes a core area 12 and a peripheral area 13 .
  • the core area 12 is located at the periphery of the array area 11
  • the peripheral area 13 is located at the periphery of the core area 12 .
  • Both the first transistor region 14 and the second transistor region 15 are located within the core region 12 .
  • Such arrangement can facilitate the arrangement of sense amplifiers, driving circuits, clock circuits, etc., which is helpful for reducing the feature size of the semiconductor structure 100 .
  • the step of removing the first oxide layer on the first transistor region to expose the top surface in the first transistor region may include: removing the channel in the first transistor region the first oxide layer on the area.
  • grooves can be formed on the top surface of the channel region and the surface of the substrate 10 is exposed to facilitate the epitaxial growth of the epitaxial layer 40;
  • the top surface of the pole region forms a masking effect.
  • the step of forming an epitaxial layer on the exposed top surface of the first transistor region may include: forming the epitaxial layer by selective epitaxial growth.
  • epitaxial technology can epitaxially grow high-resistance epitaxial layers on low-resistance substrates, or epitaxially grow low-resistance epitaxial layers on high-resistance substrates, and can also be combined with mask technology for epitaxial growth in designated areas. It can create conditions for the preparation of devices with special structures.
  • the compatibility between the materials of the epitaxial layer 40 and the substrate 10 should be considered first. Among them, the crystal structure, melting point, vapor pressure, thermal expansion coefficient, etc. have a great influence on the quality of the epitaxial layer 40, and secondly, consideration must be given to the quality of the epitaxial layer 40.
  • the contamination of the substrate 10 to the epitaxial layer 40 is a problem.
  • the similarity of the thermal expansion coefficients of the substrate 10 and the epitaxial layer 40 is one of the important factors for obtaining a good hetero-epitaxial layer 40. If the difference is large, a large stress will be generated at the interface when the temperature changes, so that the epitaxial layer 40 Defects increase, even warping, which affects the performance and thermal stability of materials and semiconductor mechanisms.
  • the epitaxial layer 40 is SiGe.
  • the main epitaxial growth methods include but are not limited to Gas Source Molecular Beam Epitaxy (GSMBE for short), Solid Source Molecular Beam Epitaxy (SSMBE for short) and Ultrahigh Vacuum Chemical Vapor Deposition (Ultrahigh Vacuum Chemical Vapor Deposition). Chemical Vapor Deposition, referred to as UHV/CVD).
  • GSMBE and UHV/CVD are similar, both use gas as the growth source, and the main difference is the gas pressure in the epitaxial growth chamber. The gas pressure is higher for UHV/CVD growth and lower for GSMBE growth.
  • UHV/CVD and GSMBE have obvious advantages in the growth of SiGe materials. For example, no high-temperature evaporation source furnace is required, and the vacuum of the growth chamber does not need to be destroyed when changing the source, so the purity of the growth chamber can be guaranteed for a long time, which is conducive to growth.
  • the high-quality material can be selectively epitaxial on the patterned substrate 10. Since the reaction gas is alkanes, which contains H, it can also effectively suppress the segregation of Ge.
  • the Ge source is generally GeH 4 . There are two main silicon sources, SiH 4 and Si 2 H 6 . In particular, on the Si substrate, Si 2 H 6 has a higher reaction than SiH 4 The adsorption probability and lower reaction energy are beneficial to realize low temperature growth and it is easier to grow high-quality SiGe materials with Si 2 H 6 .
  • the material of the epitaxial layer 40 includes silicon and germanium, and the content of germanium ranges from 5% to 50%, and the remaining elements can be all silicon. Specifically, the content of germanium can be 5%, 10%, 17%, 25% %, 38%, 44%, 55%, etc. In this way, since the carrier mobility of SiGe is significantly higher than that of Si, the carrier mobility of the epitaxial layer can be improved, so that the current transfer rate of the MOS tube is high.
  • the content of germanium is not limited in the embodiments of the present application, and the user can select within the above range according to the actual situation.
  • the Si substrate must first be processed to obtain a clean surface.
  • the purpose of solution treatment is to form a thin and clean SiO 2 protective layer on the surface of Si to prevent the contamination of the Si surface before the substrate 10 enters the pretreatment chamber, and the substrate 10 after the above treatment is sent to the pretreatment chamber , degassed at 300 °C for a few hours, then sent to the growth chamber, increased the temperature to 850 °C for deoxidation for 10 min, decreased the temperature to 650 °C after deoxidation, and adjusted the Si 2 H 6 and GeH 4 sources according to composition x The ratio of Si 1-x Ge x with composition x is grown into the growth chamber.
  • the parameters of the cleaning process of the substrate 10 and the preparation process of SiGe can be
  • the thickness of the epitaxial layer 40 ranges from 3 nm to 10 nm, and the thickness may specifically be 3 nm, 5 nm, 7 nm, 8 nm, or 10 nm.
  • the thickness of the epitaxial layer 40 is within the above range, on the one hand, it can ensure high carrier mobility of the MOS tube and good work performance, on the other hand, it can make the feature size of the semiconductor structure 100 as small as possible.
  • the embodiment of the present application does not limit the thickness of the epitaxial layer 40 , and the user can select it within the above range according to the actual situation.
  • the step of removing the first oxide layer on the second transistor region may include: removing the first oxide layer on the second transistor region to expose the top surface of the second transistor region . This may facilitate deposition of the second oxide layer 50 on the top surface of the second transistor region 15 .
  • the thickness of the first oxide layer 30 is greater than the thickness of the second oxide layer 50 .
  • the first oxide layer 30 can reduce the gate leakage current, and the second oxide layer 50 can be more easily turned on or turned on, so that the two have different functions when applied to different MOS transistors.
  • the thickness of the first oxide layer 30 ranges from 4 nm to 8 nm, and the specific thickness may be 4 nm, 6 nm, 7 nm, or 8 nm.
  • the thickness of the second oxide layer 50 ranges from 0.5 nm to 2 nm, and the specific thickness may be 0.5 nm, 1 nm, 1.5 nm, or 2 nm. Setting the thicknesses of the first oxide layer 30 and the second oxide layer 50 within the above ranges ensures that the MOS transistor can reduce gate leakage current or be more easily turned on, and on the other hand, can make the feature size of the semiconductor structure 100 as small as possible.
  • the materials of the first oxide layer 30 and the second oxide layer 50 are the same.
  • the first oxide layer 30 and the second oxide layer 50 are both silicon dioxide, and silicon dioxide is an insulating material , silicon dioxide can be used to treat the surface of the Si substrate, as a doping barrier layer, a surface insulating layer, and as an insulating part in the device.
  • silicon dioxide can act as a contamination barrier, which can block the intrusion of dirty substances in the environment into the surface of the sensitive substrate 10 .
  • its hardness can not only prevent the surface of the substrate 10 from being scratched during the manufacturing process, but also enhance the durability of the substrate 10 during the production process.
  • the mask layer 20 can be one layer.
  • the material of the mask layer 20 can be silicon dioxide. On the one hand, it can prevent dirty substances in the environment from invading the surface of the sensitive substrate 10, and on the other hand On the one hand, the higher hardness can prevent the surface of the substrate 10 from being scratched during the manufacturing process.
  • the mask layer 20 may also include sub-mask layers provided in multiple layers. As shown in FIG. 17 , the material of the mask layer 20 includes silicon oxide and silicon nitride, and specifically includes two silicon dioxide layers 21 and one silicon nitride layer 22 , and the silicon nitride layer 22 is located on the two silicon dioxide layers.
  • silicon nitride is a strong mask material that helps protect the array region 11 .
  • the silicon dioxide layer 21 is arranged between the silicon nitride layer 22 and the Si substrate because the stress of the silicon nitride layer 22 is large, and the silicon dioxide layer 21 can be used as a buffer to avoid the stress between the silicon nitride layer 22 and the Si substrate. It is easy to fall off due to matching.
  • the first type of mask layer 20 is a multilayer
  • the second type of mask layer 20 is one layer.
  • the method further includes:
  • a work function adjustment layer is formed on the second oxide layer.
  • the second oxide layer and the work function adjustment layer are thermally annealed, and the second oxide layer forms a gate oxide layer.
  • a gate oxide layer may be provided on the second oxide layer 50, and the work function adjustment layer is located on the gate oxide layer, so that the work function diffusion particles can be diffused to the gate oxide layer and the second oxide layer.
  • the work function at the interface between the gate oxide layer and the second oxide layer 50 is adjusted by using the work function diffusion particles in the work function adjustment layer.
  • the work function diffusing particles may include chloride ions or lanthanum ions.
  • the step of removing the work function adjustment layer it also includes:
  • a first transistor structure is formed on the surface of the first transistor region, and the first transistor structure is a P-type transistor.
  • a second transistor structure is formed on the surface of the second transistor region, and the second transistor structure is an N-type transistor.
  • PMOS transistors and NMOS transistors can be formed in the core region 12 , and the feature size of the semiconductor structure 100 can be reduced.
  • the materials of the gate oxide layers of the first transistor structure and the second transistor structure include one or more of silicon-doped lanthanum oxide, silicon-doped hafnium oxide, and silicon-doped zirconium oxide.
  • the gate oxide layer can reduce the quantum tunneling effect of the gate dielectric layer, thereby reducing the gate leakage current of the transistor formed in the semiconductor structure 100 and the problem of high power consumption caused by it.
  • the material of the gate layers of the first transistor structure and the second transistor structure may include titanium, cobalt, aluminum, or tungsten.
  • the gate layer includes the above-mentioned materials to form a metal gate layer.
  • the metal gate layer can reduce the threshold voltage drift of the existing polysilicon gate, the polysilicon depletion effect, the excessive gate resistance and the pinning of the Fermi level, thereby improving the stability of the semiconductor structure 100 and improving the semiconductor structure. performance of the transistor formed in 100.
  • the semiconductor structure 100 can be prepared by the above-mentioned preparation method.
  • the semiconductor structure 100 can be a memory, and specifically can include an array area 11 , and a plurality of array areas 11 can be Arrays are arranged on the substrate 10 , between adjacent array regions 11 is a core region 12 , and the periphery of the core region 12 is a peripheral region 13 .
  • the core area 12 is provided with sense amplifiers and the like, and the peripheral area 13 is provided with peripheral circuits, driving circuits, clock circuits, and the like.
  • memory cells are provided in the array area 11, and the memory cells include capacitors and transistors. Among them, the capacitor is used to store data, and the transistor can control the access of the capacitor to the data.
  • the formation of the epitaxial layer 40 is arranged after the formation of the first oxide layer 30.
  • the first oxide layer 30 can be used as a mask, and on the other hand, wet etching is avoided to remove the mask.
  • the damage of the film layer 20 to the epitaxial layer 40, in addition, the formation step of the epitaxial layer 40 is delayed, so as to avoid setting the epitaxial layer 40 prematurely, reducing the damage to the epitaxial layer 40 due to excessive cleaning processes, and reducing the preparation method of the semiconductor structure.
  • the damage to the epitaxial layer 40 improves the memory performance of the semiconductor structure 100 .

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Abstract

本申请提供一种半导体结构的制备方法，涉及半导体制造技术领域，以解决目前的DRAM器件的制作方法对SiGe层损伤较大的技术问题。该半导体结构的制备方法包括：提供基底；在基底上形成掩膜层；去除非阵列区上的掩膜层；在非阵列区上形成第一氧化层；去除第一晶体管区上的第一氧化层，以暴露出位于第一晶体管区的顶表面；在暴露出的第一晶体管区的顶表面上形成外延层；去除第二晶体管区上的第一氧化层；在第二晶体管区上，以及外延层上均形成第二氧化层。本申请能够降低半导体结构的制作方法对外延层的损伤，提高了半导体结构的存储性能。

Description

半导体结构的制备方法
本申请要求于2021年4月28日提交中国专利局、申请号为202110469981.4、申请名称为“半导体结构的制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种半导体结构的制备方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。
DRAM器件包括基底，基底上设置有***区、核心区和多个阵列区，其中，核心区包围在阵列区的外周，***区包围在核心区的外周。阵列区内设置有存储单元，每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线(Word Line，简称为WL)相连、漏极与位线相连、源极与电容器相连。***区设置有驱动电路、时钟电路等。核心区内包括P型晶体管和N型晶体管，在P型晶体管的沟道区中嵌入SiGe层来提高载流子迁移率，从而提高DRAM器件的存储性能。
然而，上述的DRAM器件的制备方法对SiGe层的损伤较大，影响DRAM器件的存储性能。
发明内容
为了解决背景技术中提到的至少一个问题，本申请提供一种半导体结构 的制备方法，能够降低半导体结构的制备方法对外延层的损伤，提高了半导体结构的存储性能。
为了实现上述目的，本申请提供一种半导体结构的制备方法，包括：
提供基底；所述基底包括阵列区和非阵列区，所述非阵列区围绕在所述阵列区的外周，所述非阵列区包括第一晶体管区和第二晶体管区。
在所述基底上形成掩膜层。
去除所述非阵列区上的所述掩膜层。
在所述非阵列区上形成第一氧化层。
去除所述第一晶体管区上的所述第一氧化层，以暴露出位于所述第一晶体管区的顶表面。
在暴露出的所述第一晶体管区的顶表面上形成外延层。
去除所述第二晶体管区上的所述第一氧化层。
在所述第二晶体管区上，以及所述外延层上均形成第二氧化层。
本申请提供的半导体结构的制备方法，通过在基底上形成掩膜层，可以对阵列区的结构层进行保护，防止阵列区的结构层受到损伤，去除非阵列区上的掩膜层，可以露出非阵列区的基底，通过在非阵列区的基底表面上形成第一氧化层，可以作为非阵列区上的结构的阻挡层或绝缘层，通过去除第一晶体管区上的第一氧化层，可以使第一晶体管区的基底暴露，此外，第一氧化层还可以起掩膜的作用，便于在暴露出的第一晶体管区的基底表面形成外延层，通过去除第二晶体管区上的第一氧化层，可以露出第二晶体管区的基底，便于在第二晶体管区的基底表面形成第二氧化层，上述制备方法，将外延层的形成设置在形成第一氧化层后，一方面可以利用第一氧化层起掩膜作用，抑制第一晶体管区以外的其他基底上生长外延层，另一方面避免了采用湿法刻蚀去除掩膜层对外延层的损伤，此外将外延层的形成步骤延后，避免过早设置外延层，减少了过多的清洗制程对外延层的损伤，降低了半导体结构的制备方法对外延层的损伤，提高了半导体结构的存储性能。
本申请的构造以及它的其他申请目的及有益效果将会通过结合附图而对优选实施例的描述而更加明显易懂。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作以简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术的器件在制备过程中核心区PMOS的硬掩膜层去除后的结构示意图；
图2为相关技术的器件在制备过程中核心区PMOS的SiGe层沉积后的结构示意图；
图3为相关技术的器件在制备过程中硬掩膜层去除后的结构示意图；
图4为相关技术的器件在制备过程中厚栅氧化物层沉积后的结构示意图；
图5为相关技术的器件在制备过程中核心区的厚栅氧化物层去除后的结构示意图；
图6为相关技术的器件在制备过程中薄栅氧化层沉积后的结构示意图；
图7为本申请实施例提供的半导体结构的制备方法的流程示意图；
图8为本申请实施例提供的半导体结构的制备方法的功函数调节过程的流程示意图；
图9为本申请实施例提供的半导体结构的结构示意图；
图10为本申请实施例提供的半导体结构的制备方法中掩膜层形成后的结构示意图；
图11为本申请实施例提供的半导体结构的制备方法中掩膜层去除后的结构示意图；
图12为本申请实施例提供的半导体结构的制备方法中第一氧化层形成后的结构示意图；
图13为本申请实施例提供的半导体结构的制备方法中第一晶体管区的第一氧化层去除后的结构示意图；
图14为本申请实施例提供的半导体结构的制备方法中外延层形成后的结构示意图；
图15为本申请实施例提供的半导体结构的制备方法中第二晶体管区 上的第一氧化层去除后的结构示意图；
图16为本申请实施例提供的半导体结构的制备方法中第二氧化层形成后的结构示意图；
图17为本申请实施例提供的半导体结构的制备方法中第一种掩膜层的结构示意图；
图18为本申请实施例提供的半导体结构的制备方法中第二种掩膜层的结构示意图。
附图标记说明：
1-核心区NMOS；2-核心区PMOS；3-***区NMOS；4-***区PMOS；5-硬掩膜层；6-SiGe层；7-厚栅氧化物层；8-薄栅氧化物层；100-半导体结构；10-基底；11-阵列区；12-核心区；13-***区；14-第一晶体管区；15-第二晶体管区；16-第三晶体管区；17-第四晶体管区；20-掩膜层；21-二氧化硅层；22-氮化硅层；30-第一氧化层；40-外延层；50-第二氧化层。
具体实施方式
在半导体制造技术领域，动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。DRAM器件包括基底，基底上设置有***区、核心区和多个阵列区，其中，核心区包围在阵列区的外周，***区包围在核心区的外周。阵列区内设置有存储单元，每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线(Word Line，简称为WL)相连、漏极与位线相连、源极与电容器相连。***区设置有驱动电路、时钟电路等。核心区内包括P型晶体管和N型晶体管，通常在P型晶体管的沟道区中嵌入SiGe层来提高载流子迁移率，从而提高DRAM器件的存储性能。
具体的，图1为相关技术的器件在制备过程中核心区PMOS的硬掩膜层去除后的结构示意图。图2为相关技术的器件在制备过程中核心区PMOS的SiGe层沉积后的结构示意图。图3为相关技术的器件在制备过程中硬掩膜层去除后的结构示意图。图4为相关技术的器件在制备过程中厚栅氧化物层沉积后的结构示意图。图5为相关技术的器件在制备过程中 核心区的厚栅氧化物层去除后的结构示意图。图6为相关技术的器件在制备过程中薄栅氧化层沉积后的结构示意图。
参照图1-图6所示，相关技术在制备核心区的器件时，通常按照如下方法：首先去除核心区PMOS2上的硬掩膜层5，暴露出核心区PMOS2上的顶表面。然后在核心区PMOS2的顶表面上沉积SiGe层6。然后采用湿法刻蚀去除核心区NMOS1、***区PMOS4以及***区NMOS3上的硬掩膜层5，暴露出核心区NMOS1、***区PMOS4以及***区NMOS3的顶表面。接着在核心区PMOS2、核心区NMOS1、***区PMOS4以及***区NMOS3上沉积厚栅氧化物层7。接着去除核心区PMOS2和核心区NMOS1上的厚栅氧化物层7。最后在核心区PMOS2和核心区NMOS1上沉积薄栅氧化物层8。
然而，上述的制备方法在沉积SiGe层6后，采用湿法刻蚀去除硬掩膜层5时会对SiGe层6造成损伤，并且SiGe层6在后续制备中多次接触清洗制程，使SiGe层6损伤较大，从而影响DRAM器件的存储性能。
有鉴于此，本申请提供的半导体结构的制备方法，通过在基底上形成掩膜层，可以对阵列区的结构层进行保护，防止阵列区的结构层受到损伤，去除非阵列区上的掩膜层，可以露出非阵列区的基底，通过在非阵列区的基底表面上形成第一氧化层，可以作为非阵列区上的结构的阻挡层或绝缘层，通过去除第一晶体管区上的第一氧化层，可以使第一晶体管区的基底暴露，此外，第一氧化层还可以起掩膜的作用，便于在暴露出的第一晶体管区的基底表面形成外延层，通过去除第二晶体管区上的第一氧化层，可以露出第二晶体管区的基底，便于在第二晶体管区的基底表面形成第二氧化层，上述制备方法，将外延层的形成设置在形成第一氧化层后，一方面可以利用第一氧化层起掩膜作用，抑制第一晶体管区以外的其他基底上生长外延层，另一方面避免了采用湿法刻蚀去除掩膜层对外延层的损伤，此外将外延层的形成步骤延后，避免过早设置外延层，减少了过多的清洗制程对外延层的损伤，降低了半导体结构的制备方法对外延层的损伤，提高了半导体结构的存储性能。
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请的优选实施例中的附图，对本申请实施例中的技术方案进行更加详细的描述。 在附图中，自始至终相同或类似的标号表示相同或类似的部件或具有相同或类似功能的部件。所描述的实施例是本申请一部分实施例，而不是全部的实施例。下面通过参考附图描述的实施例是示例性的，旨在用于解释本申请，而不能理解为对本申请的限制。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。下面结合附图对本申请的实施例进行详细说明。
图7为本申请实施例提供的半导体结构的制备方法的流程示意图。图8为本申请实施例提供的半导体结构的制备方法的功函数调节过程的流程示意图。图9为本申请实施例提供的半导体结构的结构示意图。图10为本申请实施例提供的半导体结构的制备方法中掩膜层形成后的结构示意图。图11为本申请实施例提供的半导体结构的制备方法中掩膜层去除后的结构示意图。图12为本申请实施例提供的半导体结构的制备方法中第一氧化层形成后的结构示意图。图13为本申请实施例提供的半导体结构的制备方法中第一晶体管区的第一氧化层去除后的结构示意图。图14为本申请实施例提供的半导体结构的制备方法中外延层形成后的结构示意图。图15为本申请实施例提供的半导体结构的制备方法中第二晶体管区上的第一氧化层去除后的结构示意图。图16为本申请实施例提供的半导体结构的制备方法中第二氧化层形成后的结构示意图。图17为本申请实施例提供的半导体结构的制备方法中掩膜层的结构示意图。图18为本申请实施例提供的半导体结构的制备方法中第二种掩膜层的结构示意图。参照图7-图18所示，本申请实施例提供了一种半导体结构的制备方法。
如图7所示，该半导体结构的制备方法，具体包括：
S1：提供基底。基底10包括阵列区11和非阵列区，非阵列区围绕在阵列区11的外周，非阵列区包括第一晶体管区14和第二晶体管区15。
需要说明的是，该基底10的材料可以是单晶硅、多晶硅、无定型硅、锗硅化合物或绝缘体上硅(Silicon-On-Insulator，简称为SOI)等，或者本领域技术人员已知的其他材料，该基底10可以为基底10上的结构层提供支撑基础。在本实施例中，基底10为Si基底。
该半导体结构100如图9所示，需要说明的是，图9只是半导体结构100的部分结构示意图，并不表示半导体结构100的全部结构，多个阵列 区11可以在基底10上阵列排布，相邻阵列区11之间为核心区12，核心区12的***为***区13，一般的，阵列区11设置有存储单元，核心区12设置有感应放大器等，***区13有***电路、驱动电路和时钟电路等。此外，***区13还可以有第三晶体管区16和第四晶体管区17，第三晶体管区16和第四晶体管区17具体可以用于形成驱动电路、时钟电路等。
S2：在基底上形成掩膜层。通过在基底10上形成掩膜层20，可以对阵列区11的结构层进行保护，防止阵列区11的结构层受到损伤。
S3：去除非阵列区上的掩膜层。这样可以露出非阵列区的基底10，便于形成第一氧化层30。
S4：在非阵列区上形成第一氧化层。通过在非阵列区的基底10表面上形成第一氧化层30，由于氧化物层一方面可以阻挡脏物质侵入基底10表面起阻挡作用，另一方面还具有绝缘作用，这样第一氧化层30可以作为非阵列区上的结构的阻挡层或绝缘层。
S5：去除第一晶体管区上的第一氧化层，以暴露出位于第一晶体管区的顶表面。通过去除第一晶体管区14上的第一氧化层30，可以使第一晶体管区14的基底10暴露，此外，第一氧化层30还可以起掩膜的作用，抑制第一晶体管区14以外的其他基底10上生长外延层40，便于在暴露出的第一晶体管区14的基底10表面形成外延层40。
S6：在暴露出的第一晶体管区的顶表面上形成外延层。这样可以在基底10上形成较高载流子迁移率的结构层。
S7：去除第二晶体管区上的第一氧化层。这样可以露出第二晶体管区15的基底10，便于在第二晶体管区15的基底10表面形成第二氧化层50。
S8：在第二晶体管区上，以及外延层上均形成第二氧化层。
具体每一步骤后的结构可以参照图10-图16所示，上述制备方法，将外延层40的形成设置在形成第一氧化层30后，一方面可以利用第一氧化层30起掩膜作用，另一方面避免了采用湿法刻蚀去除掩膜层20对外延层40的损伤，此外将外延层40的形成步骤延后，避免过早设置外延层40，减少了过多的清洗制程对外延层40的损伤，降低了半导体结构的制备方法对外延层40的损伤，提高了半导体结构100的存储性能。
在一种可以实现的实施方式中，在提供基底的步骤中，可以包括：通 过离子注入，在位于第一晶体管区内形成依次排布的源极区、沟道区和漏极区。离子注入具有好的可控性且没有侧向扩散，是高密度、小特征尺寸电路的首选掺杂工艺。具体可以通过离子注入的工艺在基底10上形成掺杂结构，在执行离子注入工艺时，可以通过一道掩膜保护沟道区的基底10，在源极区和漏极区的基底10形成掺杂结构，从而形成源极区和漏极区。
具体的，非阵列区包括核心区12和***区13，核心区12位于阵列区11的***，***区13位于核心区12的***。第一晶体管区14和第二晶体管区15均位于核心区12内。通过这样排布可以便于设置感应放大器、驱动电路、时钟电路等，有助于减小半导体结构100的特征尺寸。
在一种可以实现的实施方式中，去除第一晶体管区上的第一氧化层，以暴露出位于第一晶体管区的顶表面的步骤中，可以包括：去除位于第一晶体管区内的沟道区上的第一氧化层。这样一方面可以在沟道区的顶表面形成凹槽并且使基底10表面露出，便于外延生长外延层40，另一方面可以使第一氧化层30在第一晶体管区14的源极区和漏极区的顶表面形成掩膜作用。
在一种可以实现的实施方式中，在暴露出的第一晶体管区的顶表面上形成外延层步骤中，可以包括：外延层通过选择性外延生长形成。
需要说明的是，外延技术可以在低阻衬底上外延生长高阻外延层，或在高阻衬底上外延生长低阻外延层，还可以与掩膜技术结合在指定的区域进行外延生长，可以为结构特殊的器件的制备创造条件。在进行外延时，首先应考虑外延层40和基底10材料之间的相容性，其中，晶体结构、熔点、蒸汽压、热膨胀系数等对外延层40的质量影响很大，其次还必须考虑基底10对外延层40的沾污问题。另一方面，基底10和外延层40的热膨胀系数相近是得到优良异质外延层40的重要因素之一，如果相差较大，在温度变化时会在界面附件产生较大应力，使外延层40缺陷增多，甚至翘曲，从而影响材料和半导体机构的性能和热稳定性。
具体的，在本申请实施例中，外延层40为SiGe。主要的外延生长方法包括但不限于气体源分子束外延(Gas Source Molecular Beam Epitaxy，简称GSMBE)、固体源分子束外延(Solid Source Molecular Beam Epitaxy， 简称SSMBE)和超高真空化学气相沉积(Ultrahigh Vacuum Chemical Vapor Deposition，简称UHV/CVD)。其中，GSMBE和UHV/CVD方法相近，都是用气体作为生长源，主要差别是外延时生长室的气压不同。UHV/CVD生长时气压比较高，而GSMBE生长时气压要低一些。在生长SiGe材料方面UHV/CVD和GSMBE与SSMBE相比有明显的优势，例如不需要高温蒸发源炉，更换源时不需要破坏生长室的真空，因而可以长期保证生长室的纯净，有利于生长高质量材料，可以在图形基底10上进行选择外延，由于反应气体为烷类，其中含有H，它还可以有效地抑制Ge的偏析。用UHV/CVD和GSMBE生长SiGe时Ge源一般用GeH 4，硅源主要有两种SiH 4和Si 2H 6，特别的，在Si基底上，Si 2H 6比SiH 4有更高的反应吸附几率和更低的反应能，有利于实现低温生长并且用Si 2H 6更易于生长出高质量的SiGe材料。
具体的，外延层40的材料包括硅和锗，且锗的含量范围为5％～50％，其余元素可以全部为硅，具体的，锗的含量可以是5％、10％、17％、25％、38％、44％、55％等。这样由于SiGe的载流子迁移率显著高于Si的载流子迁移率，可以提高外延层的载流子迁移率，使MOS管的电流传递速率高。本申请实施例对锗的含量不作限制，用户可以根据实际在上述范围内进行选择。
需要说明的是，在生长时，首先要对Si基底进行处理以获得洁净的表面。作为一种可实现的实施方式，一般可先采用硅外延清洗基底10的方法来处理，将基底10处理干净，最后用HCL：H 2O 2：H 2O＝1:2:7溶液或其他溶液处理，其目的是要在Si的表面上形成一层薄而清洁的SiO 2保护层，防止基底10进入预处理室前Si表面的沾污，把经过上述处理的基底10送入预处理室，在300℃下除气几小时，然后送入生长室，将温度提高到850℃下脱氧10分钟，脱氧后把温度降到650℃，并按组分x调整Si 2H 6和GeH 4源的比例通入生长室生长组分为x的Si 1-xGe x。在实际制备过程中，该基底10的清洗过程以及SiGe的制备过程的参数可以根据需要调整，本实施例对此并不加以限制。
具体的，外延层40的厚度范围为3nm～10nm，厚度具体可以是3nm、5nm、7nm、8nm、10nm。外延层40的厚度位于上述范围内，一方面可以 保证MOS管的载流子迁移率高，工作性能好，另一方面可以使半导体结构100的特征尺寸尽量小。本申请实施例对外延层40的厚度不作限制，用户可以根据实际在上述范围内进行选择。
在一种可以实现的实施方式中，去除第二晶体管区上的第一氧化层的步骤中，可以包括：去除第二晶体管区上的第一氧化层，暴露出位于第二晶体管区的顶表面。这样可以便于在第二晶体管区15的顶表面上沉积第二氧化层50。
具体的，第一氧化层30的厚度大于第二氧化层50的厚度。这样使第一氧化层30可以减少栅极漏电流，使第二氧化层50可以更易开启或更易导通，使二者分别应用在不同的MOS管上具有不同的作用。
具体的，第一氧化层30的厚度范围为4nm-8nm，具体厚度可以是4nm、6nm、7nm、8nm。在一种可以实现的实施方式中，第二氧化层50的厚度范围为0.5nm-2nm，具体厚度可以是0.5nm、1nm、1.5nm、2nm。将第一氧化层30和第二氧化层50的厚度设置在上述范围内，一方面保证MOS管可以减少栅极漏电流或更易开启，另一方面可以使半导体结构100的特征尺寸尽量小。
具体的，第一氧化层30和第二氧化层50的材料相同，在本申请实施例中，第一氧化层30和第二氧化层50均为二氧化硅，二氧化硅是一种绝缘材料，二氧化硅可以用来处理Si基底的表面，做掺杂阻挡层、表面绝缘层，以及作为器件中的绝缘部分。
需要说明的是，二氧化硅密度非常高，非常硬，因此二氧化硅可以作为污染阻挡层，它可以阻挡环境中脏物质侵入敏感的基底10表面。同时，它的硬度既可以防止基底10表面在制备过程中被划伤，同时又增强基底10在生产流程过程中的耐用性。
具体的，掩膜层20可以为一层，当掩膜层20为一层时，掩膜层20的材料可以是二氧化硅，一方面可以阻挡环境中脏物质侵入敏感的基底10表面，另一方面较高的硬度可以防止基底10表面在制备过程中被划伤。掩膜层20也可以包括多层叠设的子掩膜层。如图17所示，掩膜层20的材料包括氧化硅和氮化硅，具体包括两层二氧化硅层21和一层氮化硅层22，氮化硅层22位于两层二氧化硅层21之间，氮化硅是坚固的掩膜材料， 有助于保护阵列区11。氮化硅层22和Si基底之间设置设置二氧化硅层21是因为氮化硅层22的应力交大，二氧化硅层21可以作为缓冲，避免氮化硅层22和Si基底应力之间不匹配而导致易脱落。具体如图17所示，第一种掩膜层20为多层，如图18，第二种掩膜层20为一层。
在一种可以实现的实施方式中，如图2所示，在第二晶体管区上，以及外延层上均形成第二氧化层的步骤之后，还包括：
S9：在第二氧化层上形成功函数调节层。
S10：热退火处理第二氧化层和功函数调节层，第二氧化层形成栅极氧化物层。
S11：去除功函数调节层。
需要说明的是，第二氧化层50上可以设置有栅极氧化物层，功函数调节层位于栅极氧化物层之上，这样可以使功函数扩散粒子扩散到栅极氧化物层和第二氧化层50之间的界面处，利用功函数调节层中的功函数扩散粒子调节栅极氧化物层和第二氧化层50之间的界面处的功函数。功函数扩散粒子可以包括氯离子或镧离子。
具体的，去除功函数调节层的步骤之后，还包括：
在第一晶体管区表面形成第一晶体管结构，第一晶体管结构为P型晶体管。
在第二晶体管区表面形成第二晶体管结构，第二晶体管结构为N型晶体管。
这样可以在核心区12形成PMOS管和NMOS管，并且降低半导体结构100的特征尺寸。
具体的，第一晶体管结构和第二晶体管结构的栅极氧化物层的材料包括掺硅氧化镧、掺硅氧化铪和掺硅氧化锆中的一种或多种。该栅极氧化物层可以减少栅介质层的量子隧穿效应，从而减低半导体结构100中所形成的晶体管的栅极漏电流及其引起的高功耗的问题。
此外，第一晶体管结构和第二晶体管结构的栅极层的材料可以包括钛、钴、铝或钨。栅极层包括上述材料可以形成金属栅极层。金属栅极层可以减少现有多晶硅栅极的阈值电压漂移，多晶硅耗尽效应、过高的栅电阻以及费米能级的钉扎的现象，从而可以提高半导体结构100的稳定性，提升 半导体结构100中所形成的晶体管的性能。
在上述的基础上，本实施例还提供一种半导体结构，该半导体结构100可以采用上述的制备方法制备而成，半导体结构100可以是存储器，具体可以包括阵列区11，多个阵列区11可以在基底10上阵列排布，相邻阵列区11之间为核心区12，核心区12的***为***区13。核心区12设置有感应放大器等，***区13有***电路、驱动电路和时钟电路等。一般的，阵列区11内设置有存储单元，存储单元包括电容器和晶体管。其中，电容器用于存储数据，而晶体管可以控制电容器对数据的存取。
本申请提供的半导体结构100，将外延层40的形成设置在形成第一氧化层30后，一方面可以利用第一氧化层30起掩膜作用，另一方面避免了采用湿法刻蚀去除掩膜层20对外延层40的损伤，此外将外延层40的形成步骤延后，避免过早设置外延层40，减少了过多的清洗制程对外延层40的损伤，降低了半导体结构的制备方法对外延层40的损伤，提高了半导体结构100的存储性能。
描述中，需要理解的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应作广义理解，例如，可以使固定连接，也可以是通过中间媒介间接相连，可以是两个元件内部的连通或者两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。术语“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或者位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或者暗示所指的装置或者元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。在本申请的描述中，“多个”的含义是两个或两个以上，除非是另有精确具体地规定。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过 程、方法、***、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构的制备方法，包括：
    提供基底；所述基底包括阵列区和非阵列区，所述非阵列区围绕在所述阵列区的外周，所述非阵列区包括第一晶体管区和第二晶体管区；
    在所述基底上形成掩膜层；
    去除所述非阵列区上的所述掩膜层；
    在所述非阵列区上形成第一氧化层；
    去除所述第一晶体管区上的所述第一氧化层，以暴露出位于所述第一晶体管区的顶表面；
    在暴露出的所述第一晶体管区的顶表面上形成外延层；
    去除所述第二晶体管区上的所述第一氧化层；
    在所述第二晶体管区上，以及所述外延层上均形成第二氧化层。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，所述提供基底的步骤中，包括：
    通过离子注入，在位于所述第一晶体管区内形成依次排布的源极区、沟道区和漏极区。
  3. 根据权利要求2所述的半导体结构的制备方法，其中，所述非阵列区包括核心区和***区，所述核心区位于所述阵列区的***，所述***区位于所述核心区的***；
    所述第一晶体管区和所述第二晶体管区均位于所述核心区内。
  4. 根据权利要求2所述的半导体结构的制备方法，其中，所述去除所述第一晶体管区上的所述第一氧化层，以暴露出位于所述第一晶体管区的顶表面的步骤中，包括：
    去除位于所述第一晶体管区内的所述沟道区上的所述第一氧化层。
  5. 根据权利要求1-4中任一项所述的半导体结构的制备方法，其中，所述在暴露出的所述第一晶体管区的顶表面上形成外延层步骤中，包括：
    所述外延层通过选择性外延生长形成。
  6. 根据权利要求1-4中任一项所述的半导体结构的制备方法，其中，所述外延层的材料包括硅和锗，且锗的含量范围为5％～50％。
  7. 根据权利要求1-4中任一项所述的半导体结构的制备方法，其中，所述外延层的厚度范围为3nm～10nm。
  8. 根据权利要求3所述的半导体结构的制备方法，其中，所述去除所述第二晶体管区上的所述第一氧化层的步骤中，包括：
    去除所述第二晶体管区上的所述第一氧化层，暴露出位于所述第二晶体管区的顶表面。
  9. 根据权利要求1-4中任一项所述的半导体结构的制备方法，其中，所述第一氧化层的厚度大于所述第二氧化层的厚度。
  10. 根据权利要求9所述的半导体结构的制备方法，其中，所述第一氧化层的厚度范围为4nm-8nm；
    和/或，所述第二氧化层的厚度范围为0.5nm-2nm。
  11. 根据权利要求1-4中任一项所述的半导体结构的制备方法，其中，所述第一氧化层和所述第二氧化层的材料相同。
  12. 根据权利要求1-4中任一项所述的半导体结构的制备方法，其中，所述掩膜层为一层，或，所述掩膜层包括多层叠设的子掩膜层；
    和/或，所述掩膜层的材料包括氧化硅和氮化硅。
  13. 根据权利要求1-4中任一项所述的半导体结构的制备方法，其中，所述在所述第二晶体管区上，以及所述外延层上均形成所述第二氧化层的步骤之后，还包括：
    在所述第二氧化层上形成功函数调节层；
    热退火处理所述第二氧化层和所述功函数调节层，所述第二氧化层形成栅极氧化物层；
    去除所述功函数调节层。
  14. 根据权利要求13所述的半导体结构的制备方法，其中，所述去除所述功函数调节层的步骤之后，还包括：
    在所述第一晶体管区表面形成第一晶体管结构，所述第一晶体管结构为P型晶体管；
    在所述第二晶体管区表面形成第二晶体管结构，所述第二晶体管结构为N型晶体管。
  15. 根据权利要求14所述的半导体结构的制备方法，其中，所述第 一晶体管结构和所述第二晶体管结构的栅极氧化物层的材料包括掺硅氧化镧、掺硅氧化铪和掺硅氧化锆中的一种或多种；
    和/或，所述第一晶体管结构和所述第二晶体管结构的栅极层的材料包括钛、钴、铝或钨。
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JP2000133729A (ja) * 1998-10-23 2000-05-12 Stmicroelectronics Srl 非サリサイド処理不揮発性メモリセル、非サリサイド処理高電圧トランジスタ、及びサリサイド処理接合低電圧トランジスタを含む電子デバイスの製法および電子デバイス
JP2001339070A (ja) * 2000-05-30 2001-12-07 Toshiba Corp Ｔｆｔアレイおよびその製造方法
CN1905160A (zh) * 2005-07-14 2007-01-31 秦蒙达股份公司 集成半导体结构的制造方法及相应的集成半导体结构
CN112599593A (zh) * 2020-12-11 2021-04-02 上海交通大学 一种基于石墨烯的场效应晶体管的制备***及制备方法

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Publication number Priority date Publication date Assignee Title
JP2000133729A (ja) * 1998-10-23 2000-05-12 Stmicroelectronics Srl 非サリサイド処理不揮発性メモリセル、非サリサイド処理高電圧トランジスタ、及びサリサイド処理接合低電圧トランジスタを含む電子デバイスの製法および電子デバイス
JP2001339070A (ja) * 2000-05-30 2001-12-07 Toshiba Corp Ｔｆｔアレイおよびその製造方法
CN1905160A (zh) * 2005-07-14 2007-01-31 秦蒙达股份公司 集成半导体结构的制造方法及相应的集成半导体结构
CN112599593A (zh) * 2020-12-11 2021-04-02 上海交通大学 一种基于石墨烯的场效应晶体管的制备***及制备方法

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