WO2022226973A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022226973A1
WO2022226973A1 PCT/CN2021/091379 CN2021091379W WO2022226973A1 WO 2022226973 A1 WO2022226973 A1 WO 2022226973A1 CN 2021091379 W CN2021091379 W CN 2021091379W WO 2022226973 A1 WO2022226973 A1 WO 2022226973A1
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WO
WIPO (PCT)
Prior art keywords
metal layer
display panel
area
layer
pixel circuit
Prior art date
Application number
PCT/CN2021/091379
Other languages
English (en)
French (fr)
Other versions
WO2022226973A9 (zh
Inventor
蔡建畅
龙跃
王琦伟
徐元杰
黄耀
孙开鹏
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/763,803 priority Critical patent/US20240057387A1/en
Priority to PCT/CN2021/091379 priority patent/WO2022226973A1/zh
Priority to CN202180001002.0A priority patent/CN115552510A/zh
Priority to EP21938448.4A priority patent/EP4202905A4/en
Publication of WO2022226973A1 publication Critical patent/WO2022226973A1/zh
Publication of WO2022226973A9 publication Critical patent/WO2022226973A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/13—Active-matrix OLED [AMOLED] displays comprising photosensors that control luminance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • OLED display panels have been widely used due to their advantages of self-luminescence, low driving voltage, and fast response speed.
  • An OLED display panel generally includes: a plurality of pixel units, and each pixel unit includes a light-emitting element and a pixel circuit coupled to the light-emitting element.
  • the present disclosure provides a display panel and a display device, and the technical solutions are as follows:
  • a display panel comprising:
  • a base substrate having a first display area, a second display area and a peripheral area, the second display area at least partially surrounds the first display area, and the peripheral area at least partially surrounds the second display area;
  • a plurality of second pixel circuits and a plurality of second light-emitting elements are located in the second display area, at least one second pixel circuit in the plurality of second pixel circuits and at least one of the plurality of second light-emitting elements a second light-emitting element is coupled;
  • At least one first connection line is located in the peripheral area, the second display area and the first display area, and at least one first pixel circuit in the plurality of first pixel circuits is connected to the plurality of first pixel circuits. At least one first light-emitting element in a light-emitting element is coupled through the first connection trace;
  • At least one compensation capacitor is located in the peripheral region, the compensation capacitor includes an overlapping first metal layer and a second metal layer, the first metal layer is coupled to the target node, and the second metal layer is connected to a power supply terminal is coupled, and the target node is a node where the first pixel circuit is coupled with the first connecting line.
  • the capacitance value of the compensation capacitor corresponding to each of the first pixel circuits is negatively correlated with the length of the coupled first connection line.
  • the overlapping area of the two overlapping metal layers is negatively correlated with the length of the coupled first connection line.
  • the display panel includes: a plurality of pixel circuit groups, each of the pixel circuit groups including: at least two of the first pixel circuits;
  • the capacitance values of the compensation capacitors corresponding to each of the pixel circuit groups are the same, and the capacitance values of the compensation capacitors corresponding to different pixel circuit groups are different.
  • the plurality of pixel circuit groups include: a first sub-pixel circuit group, a second sub-pixel circuit group and a third sub-pixel circuit group that are sequentially spaced along the pixel row direction;
  • each compensation capacitor corresponding to the first sub-pixel circuit group is smaller than the capacitance value of each compensation capacitor corresponding to the second sub-pixel circuit group, and each compensation capacitor corresponding to the second sub-pixel circuit group The capacitance value of is greater than the capacitance value of each compensation capacitor corresponding to the third sub-pixel circuit group.
  • the peripheral area includes: a first area and a second area arranged along a pixel column direction, and the second area is close to the second display area relative to the first area;
  • each of the first pixel circuits is located in the first area, and each of the compensation capacitors is located in the second area.
  • the display panel includes a plurality of the compensation capacitors, the second metal layers included in each of the compensation capacitors have an integrated structure, and the first metal layers included in each of the compensation capacitors are arranged at intervals along the pixel row direction. .
  • the at least one compensation capacitor includes a plurality of first group compensation capacitors, and at least one first group compensation capacitor in the plurality of first group compensation capacitors includes an overlapping third metal layer and a fourth metal layer. layer, and in the first metal layer, the second metal layer, the third metal layer and the fourth metal layer, any two metal layers are located in different layers;
  • the third metal layer is coupled to the target node, and the fourth metal layer is coupled to the power terminal.
  • the at least one compensation capacitor further includes: multiple second sets of compensation capacitors and multiple third sets of compensation capacitors;
  • At least one of the plurality of first-group compensation capacitors further includes overlapping first metal layers and second metal layers, and at least one of the plurality of second-group compensation capacitors
  • the compensation capacitor further includes overlapping first metal layers and second metal layers, and at least one of the plurality of third groups of compensation capacitors further includes overlapping first metal layers and second metal layers Floor;
  • the plurality of first groups of compensation capacitors, the plurality of second groups of compensation capacitors, and the plurality of third groups of compensation capacitors are sequentially spaced along the pixel row direction, and the second group of compensation capacitors includes the first
  • the height of the metal layer along the pixel column direction is greater than the height of the first metal layer included in the third group of compensation capacitors along the pixel column direction, and greater than the height of the first metal layer included in the second group of compensation capacitors along the pixel column direction.
  • the pixel circuit in the display panel includes: an active layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer and the second source-drain metal layer;
  • the first metal layer is located in the same layer as one of the first gate metal layer and the second gate metal layer, and the second metal layer is in the same layer as the first gate metal layer and the second gate metal layer. another gate metal layer in the second gate metal layer is located in the same layer;
  • the third metal layer is located in the same layer as one of the first source-drain metal layer and the second source-drain metal layer, and the fourth metal layer and the first source-drain metal layer It is located in the same layer as another source-drain metal layer in the second source-drain metal layer.
  • the first metal layer and the first gate metal layer are located on the same layer, and the second metal layer and the second gate metal layer are located on the same layer.
  • the third metal layer and the first source-drain metal layer are located on the same layer, and the fourth metal layer and the second source-drain metal layer are located on the same layer.
  • each of the compensation capacitors includes: the overlapping first metal layer and the second metal layer, and the overlapping third metal layer and the fourth metal layer.
  • the fourth metal layer included in each of the compensation capacitors has an integrated structure, and the third metal layers included in each of the compensation capacitors are arranged at intervals along the pixel row direction.
  • the orthographic projection of the first metal layer on the base substrate and the orthographic projection of the third metal layer on the base substrate are both strip-like structures, and the strip-like structures Extends along the pixel column direction.
  • the display panel further includes:
  • At least one second connection line located in the peripheral region, the first metal layer and the third metal layer are both coupled to the target node through the second connection line.
  • the peripheral area includes: a first area, a third area and a second area arranged along the pixel column direction, and the second area is close to the second display area relative to the first area; the first metal layer and the second connection trace are coupled through a first via hole, and the third metal layer and the first metal layer are coupled through a second via hole;
  • the first via hole is located in the third area of the peripheral area, and the second via hole is located in the first area of the peripheral area.
  • the display panel further includes: a first flat layer, a second flat layer and a third flat layer arranged in sequence along the direction of the first via hole away from the base substrate;
  • the orthographic projection of the first flat layer on the base substrate covers the orthographic projection of the first via hole on the base substrate, and the second flat layer on the base substrate
  • the orthographic projection covers the orthographic projection of the first via on the base substrate
  • the orthographic projection of the third flat layer on the base substrate is the same as the orthographic projection of the first via on the base substrate
  • the orthographic projections on do not overlap.
  • the first flattening layer, the second flattening layer, and the third flattening layer are all located on a side of the second connection trace away from the base substrate.
  • the second connection wiring and the second source-drain metal layer included in the pixel circuit in the display panel are located at the same layer.
  • the display panel includes at least one compensation capacitor corresponding to the at least one first connection line one-to-one;
  • each of the compensation capacitors and a corresponding one of the first connection lines are coupled to the target node.
  • the display panel includes a plurality of the first connection wires, and at least two of the plurality of the first connection wires are located on different layers.
  • the plurality of first connection lines include at least one first-type first connection line located on the same layer, at least one second-type first connection line located on the same layer, and at least one first-type connection line located on the same layer.
  • any two types of first connection wires are located on different layers.
  • the first connecting wire is a transparent conductive wire.
  • a display device in another aspect, includes: a photosensitive sensor, and the display panel according to the above aspect;
  • the photosensitive sensor is located in the first display area of the display panel.
  • FIG. 1 is a schematic diagram of coupling between a first connecting wire and a light-emitting element provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of coupling of another first connection wire and a light-emitting element according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of still another display panel provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of still another display panel provided by an embodiment of the present disclosure.
  • FIG. 8 is a structural layout of a compensation capacitor provided by an embodiment of the present disclosure.
  • FIG. 9 is a structural layout of a part of a metal layer in a compensation capacitor provided by an embodiment of the present disclosure.
  • FIG. 10 is a structural layout of a first metal layer in a compensation capacitor provided by an embodiment of the present disclosure
  • FIG. 11 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 12 is a partial structural layout of a compensation capacitor in yet another display panel provided by an embodiment of the present disclosure.
  • FIG. 13 is a partial structural layout of a compensation capacitor in yet another display panel provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of still another display panel provided by an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of still another display panel provided by an embodiment of the present disclosure.
  • 16 is a schematic diagram of a structure including a flat layer and a via hole provided by an embodiment of the present disclosure
  • FIG. 17 is a schematic structural diagram of still another display panel provided by an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of a first connection wiring provided by an embodiment of the present disclosure.
  • FIG. 19 is a schematic structural diagram of a first type of first connection wiring provided by an embodiment of the present disclosure.
  • 20 is a schematic structural diagram of a second type of first connection wiring provided by an embodiment of the present disclosure.
  • 21 is a schematic structural diagram of a third type of first connection wiring provided by an embodiment of the present disclosure.
  • FIG. 22 is a schematic structural diagram of still another display panel provided by an embodiment of the present disclosure.
  • FIG. 23 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the existing Liu Haiping or water drop screen designs are gradually unable to meet the needs of users for a high screen-to-body ratio of display panels.
  • a series of high-PPI OLED display panels with light-transmitting display areas have emerged.
  • PPI It is a unit of resolution, the full English name is pixel per inch, which represents the number of pixels per inch of the display panel.
  • hardware such as a photosensitive sensor (such as a camera) can be arranged in the light-transmitting display area.
  • the light-transmitting display area can also be called the camera area under the screen.
  • the first display The area refers to the camera area under the screen.
  • an electroluminescence device electroluminescence, EL
  • the EL is the first light-emitting element described in the embodiment of the present disclosure.
  • the pixel circuit that drives the EL light emission in the under-screen camera area ie, the first pixel circuit described in the embodiment of the present disclosure
  • a conductive wire ie, the first connecting wire described in the embodiment of the present disclosure
  • Coupling may refer to electrical connection.
  • FIG. 1 shows a schematic diagram of a first connection trace coupled to a first light-emitting element.
  • the first connection line L1 may extend to the first light emitting element 01 via the first pixel circuit (not shown), and be coupled to the anode of the light emitting element 01 .
  • the node coupled to the first light-emitting element 01 is identified as P1
  • the first connection trace L1 also has a parasitic capacitance c0.
  • parasitic capacitance c1 There is a parasitic capacitance c1.
  • the distances between the first pixel circuits at different positions and the coupled first light-emitting elements are different, the lengths of each of the first connection lines provided in the display panel are different.
  • the magnitude of the parasitic capacitance c1 shown in FIG. 1 is different, that is, the magnitude of the capacitance at the node P1 of the different first light-emitting elements 01 is different.
  • the light-emitting brightness of different first light-emitting elements 01 is different, which affects the display effect.
  • the embodiment of the present disclosure provides a display panel including a compensation capacitor, the compensation capacitor can effectively compensate the capacitance value at the node P1, so that the uniformity of the luminous brightness of different first light-emitting elements is better, and the camera area under the screen can be reached.
  • the display effect is consistent with the display effect of other normal display areas.
  • FIG. 2 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel may include: a base substrate 00, the base substrate 00 may have a first display area A1, a second display area A2 and a peripheral area A3, the second display area A2 may at least partially surround The first display area A1, and the peripheral area A3 may at least partially surround the second display area A2.
  • the first display area A1 shown in FIG. 2 is located at the upper middle position of the base substrate 00, and the second display area A2 surrounds the first display area A1, that is, the first display area A1 is surrounded by the second display area A2 .
  • the peripheral area A3 surrounds the second display area A2, that is, the second display area A2 is surrounded by the peripheral area A3.
  • the first display area A1 may not be located at the position shown in FIG. 2 , but may be located at other positions on the base substrate 00 .
  • the first display area A1 may be located at the upper left corner or the upper right corner of the base substrate 00 .
  • FIG. 3 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure. It can be seen in conjunction with FIG. 2 and FIG. 3 that the display panel may further include: a plurality of first light-emitting elements 01 located in the first display area A1. A plurality of first pixel circuits 02 and at least one compensation capacitor 03 located in the peripheral area A3. A plurality of second pixel circuits 04 and a plurality of second light emitting elements 05 located in the second display area A2. and at least one first connecting line L1 located in the peripheral area A3, the second display area A2 and the first display area A1.
  • At least one first pixel circuit 02 in the plurality of first pixel circuits 02 and at least one first light emitting element 01 in the plurality of first light emitting elements 01 may be coupled through the first connection line L1.
  • one end of the first connection line L1 can be coupled with the first pixel circuit 02 (the coupling point is the target node P1 shown in the figure), and the other end of the first connection line L1 can be coupled with the first light emitting Element 01 is coupled.
  • the at least one first pixel circuit 02 can be used to provide a driving signal for the coupled first light-emitting element 01, so as to drive the first light-emitting element 01 to emit light.
  • At least one second pixel circuit 04 of the plurality of second pixel circuits 04 may be coupled to at least one second light emitting element 05 of the plurality of second light emitting elements 05, and the at least one second pixel circuit 04 may be used for all
  • the coupled second light-emitting element 05 provides a driving signal to drive the second light-emitting element 05 to emit light.
  • each second pixel circuit 04 is coupled to one second light emitting element 05 .
  • Each compensation capacitor 03 may be coupled to a target node P1 to realize capacitance compensation at the target node P1.
  • FIG. 4 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure. It can be seen in combination with FIG. 3 and FIG. 4 that each compensation capacitor 03 may include a first metal layer 031 and a second metal layer 032 that are overlapped.
  • the first metal layer 031 can be coupled to the target node P1, and the second metal layer 032 can be coupled to the power terminal VSS.
  • the first metal layer 031 and the second metal layer 032 are overlapped to effectively form the compensation capacitor 03 .
  • FIG. 5 shows the capacitor c2 (ie, the compensation capacitor 03 ) formed by overlapping the first metal layer 031 and the second metal layer 032 ) optional circuit structure. Comparing FIG. 1 and FIG. 5 , it can be seen that a capacitor c2 is additionally added to the target node P1 in the embodiment of the present disclosure.
  • the first connection line L1 can be flexibly set based on the length of the first connection line L1.
  • the overlapping area of the metal layer 031 and the second metal layer 032, and/or the distance between the first metal layer 031 and the second metal layer 032, can achieve effective compensation for the target node P1.
  • the uniformity of the light-emitting brightness of different first light-emitting elements is better.
  • the first display area A1 may be a light-transmitting display area
  • the second display area A2 may be a non-light-transmitting display area
  • the peripheral area A3 may be a non-display area. That is, the first display area A1 described in the embodiments of the present disclosure can transmit light, and the hardware structure required for the display device such as a photosensitive sensor can be arranged in the first display area A1. This not only lays a foundation for the realization of a true full screen, but also ensures that the first display area A1 only includes the first light-emitting element 01, but does not include the first pixel circuit 02 that drives the first light-emitting element 01 to emit light. The light transmittance of the first display area A1 is good, and it is ensured that the resolution of the display panel is good.
  • the resolution of the first display area A1 may be less than or equal to the resolution of the second display area A2.
  • the area of the first display area A1 and the area of the second display area A2 may be the same, and the number of the first light-emitting elements 01 included in the first display area A1 and the number of the second light-emitting elements 05 included in the second display area A2 Also the same.
  • the area of the first display area A1 may be smaller than that of the second display area A2, and the first light-emitting element 01 included in the first display area A1 is relative to the second display area A2.
  • the number of included second light emitting elements 05 may be small.
  • the second display area A2 may also be referred to as the main display area.
  • the resolution of the first display area A1 may be greater than that of the second display area A2. That is, the area of the first display area A1 is larger than that of the second display area A2, and the first light-emitting element 01 included in the first display area A1 is larger than the second light-emitting element included in the second display area A2 05 is more in number.
  • an embodiment of the present disclosure provides a display panel, the display panel includes a first light emitting element located in a first display area, a first pixel circuit and a compensation capacitor located in a peripheral area.
  • the first pixel circuit may be coupled to the first light emitting element through a first connection wire.
  • the first metal layer in the compensation capacitor can be coupled with a target node, the second metal layer can be coupled with a power supply terminal, and the target node is a node where the first connection line and the first pixel circuit are coupled.
  • the capacitance value of the compensation capacitor 03 corresponding to each first pixel circuit 02 may be negatively correlated with the length of the coupled first connection line L1 . That is, the longer the length of the first connection line L1, the smaller the capacitance of the compensation capacitor 03; the shorter the length of the first connection line L1, the larger the capacitance of the compensation capacitor 03.
  • the compensation capacitor 03 corresponding to the first pixel circuit 02 refers to the compensation capacitor 03 coupled to the target node P1 in the first pixel circuit 02 .
  • the length of the first connecting line L1 is generally positively related to the existing parasitic capacitance. That is, the longer the length of the first connection line L1, the larger the capacitance of the parasitic capacitance on the first connection line L1, the longer the length of the first connection line L1, the greater the parasitic capacitance on the first connection line L1
  • the capacitance value is smaller.
  • the capacitance value of the corresponding compensation capacitor 03 should be smaller, that is, less compensation can be made.
  • the corresponding compensation capacitor 03 should have a larger capacitance value, that is, more compensation can be achieved.
  • the capacitance value of the compensation capacitor 03 corresponding to the first pixel circuit 02 to be negatively correlated with the length of the coupled first connection line L1
  • different first connection lines L1 coupled to different first connection lines L1 can be
  • the brightness of the light-emitting elements 01 should be the same as possible, so as to ensure better uniformity of the light-emitting brightness of each first light-emitting element 01 .
  • the display effect of the display panel can be effectively improved.
  • the compensation capacitor 03 corresponding to each first pixel circuit 02 can be set to have two overlapping metal layers.
  • the overlapping area is negatively related to the length of the coupled first connection line L1.
  • the compensation capacitor 03 includes the overlapping first metal layer 031 and the second metal layer 032 . If the length of the first connection trace L1 is longer, the overlapping area of the first metal layer 031 and the second metal layer 032 can be set to be smaller. On the contrary, if the length of the first connection line L1 is short, the overlapping area of the first metal layer 031 and the second metal layer 032 can be set to be large. For a structure including other overlapping metal layers, the principle of setting is the same, and details are not described in subsequent embodiments.
  • the display panel may further include: a plurality of pixel circuit groups, and each pixel circuit group may include at least two first pixel circuits 02 .
  • the capacitance values of the compensation capacitors 03 corresponding to each pixel circuit group may be the same, and the capacitance values of the compensation capacitors 03 corresponding to different pixel circuit groups may be different.
  • a plurality of pixel circuit groups may include a first sub-pixel circuit group Z11 , a second sub-pixel circuit group Z12 and a third sub-pixel circuit group Z13 which are sequentially spaced along the pixel row direction X1 . That is, the second sub-pixel circuit group Z12 is closer to the first display area A1 than the first sub-pixel circuit group Z11 and the third sub-pixel circuit group Z13.
  • the distance between each of the first pixel circuits 02 included in the second sub-pixel circuit group Z12 and the first light-emitting element 01 is closer than that of the first sub-pixel circuit group Z11 and the third sub-pixel circuit group Z13 , the first connecting lines L1 for coupling the first pixel circuits 02 to the first light-emitting elements 01 are shorter. Therefore, continuing to refer to FIG. 6 and FIG.
  • each compensation capacitor 03 corresponding to the first sub-pixel circuit group Z11 is smaller than the capacitance value of each compensation capacitor 03 corresponding to the second sub-pixel circuit group Z12
  • the second The capacitance value of each compensation capacitor 03 corresponding to the sub-pixel circuit group Z12 may be greater than the capacitance value of each compensation capacitor 03 corresponding to the third sub-pixel circuit group Z13. That is, along the direction in which the second sub-pixel circuit group Z12 approaches the first sub-pixel circuit group Z11, and along the direction in which the second sub-pixel circuit group Z12 approaches the third sub-pixel circuit group Z13, the compensation capacitor O3 that needs to be set The capacitance values are decreasing.
  • FIGS. 6 and 7 both take the overlapping area of the first metal layer 031 and the second metal layer 032 as an example to illustrate the capacitance values of the compensation capacitors 03 corresponding to different pixel circuit groups.
  • 6 is by setting the second metal layer 032 as a "convex" shape structure, and setting the heights of the first metal layers 031 corresponding to different pixel circuit groups are the same, so that the compensation capacitors 03 corresponding to different pixel circuit groups Z1 are The overlapping areas of the first metal layer 031 and the second metal layer 032 are different.
  • FIG. 7 shows that the heights of the first metal layers 031 corresponding to different pixel circuit groups Z1 are different, and the second metal layer 032 is set to have a rectangular structure, so that the first metal layers 031 in the compensation capacitors 03 corresponding to different pixel circuit groups Z1 The overlapping area with the second metal layer 032 is different.
  • FIG. 6 nor FIG. 7 shows the specific structure of each pixel circuit group Z1, and neither shows the first light-emitting element 01 included in the first display area A1.
  • the overlapping area of the two metal layers can be changed by flexibly adjusting the structure of any one of the two overlapping metal layers.
  • the display panel may include at least one compensation capacitor 03 corresponding to at least one first connection line L1 one-to-one, and each compensation capacitor 03 corresponds to one first connection line L1 is coupled to the target node P1. That is, each of the first connection lines L1 in the display panel is correspondingly provided with a compensation capacitor 03 .
  • FIG. 8 is a schematic structural diagram of still another display panel provided by an embodiment of the present disclosure.
  • the at least one compensation capacitor 03 included in the display panel may include a plurality of first group compensation capacitors 03A.
  • FIG. 8 does not show the specific structure of each pixel circuit group, and does not show the first light-emitting element 01 included in the first display area A1.
  • FIG. 9 is a schematic structural diagram of still another display panel provided by an embodiment of the present disclosure.
  • at least one first-group compensation capacitor 03A may include overlapping third metal layers 033 and fourth metal layers 034 .
  • the third metal layer 033 may be coupled to the target node P1, and the fourth metal layer 034 may be coupled to the power supply terminal VSS.
  • the third metal layer 033 and the fourth metal layer 034 overlap to effectively form a compensation capacitor 03 .
  • each first group of compensation capacitors 03A shown in FIG. 9 includes overlapping third metal layers 033 and fourth metal layers 034, and further includes overlapping first metal layers 031 and second metal layers 032.
  • the at least one compensation capacitor 03 may further include a plurality of second group compensation capacitors 03B and a plurality of third group compensation capacitors 03C.
  • At least one first group of compensation capacitors 03A may further include overlapping first metal layers 031 and second metal layers 032 .
  • At least one second set of compensation capacitors 03B may include overlapping first metal layers 031 and second metal layers 032 , and overlapping third metal layers 033 and fourth metal layers 034 .
  • At least one third group of compensation capacitors 03C may include overlapping first metal layers 031 and second metal layers 032 , and overlapping third metal layers 033 and fourth metal layers 034 . It should be noted that FIG. 9 only shows the optional structure of the first group of compensation capacitors 03A.
  • the plurality of first group of compensation capacitors 03A may correspond to the first sub-pixel circuit group Z11
  • the plurality of second groups of compensation capacitors 03B may correspond to the second sub-pixel circuit group Z12.
  • the plurality of third groups of compensation capacitors O3C may correspond to the third sub-pixel circuit group Z13.
  • the height of the first metal layer 031 along the pixel column direction X2 represents the overlapping area of the first metal layer 031 and the second metal layer 032, it can be seen with reference to FIG. 7 and FIG. 10 that the second set of compensation capacitors 03B
  • the height of the included first metal layer 031 along the pixel column direction X2 may be greater than the height of the first metal layer 031 included in the third set of compensation capacitors 03C along the pixel column direction X2, and may be greater than the height of the first metal layer 031 included in the first set of compensation capacitors 03A.
  • each compensation capacitor 03 in at least part of the compensation capacitors 03 may be composed of overlapping first metal layers 031 and second metal layers 032. form.
  • at least a portion of each of the compensation capacitors 03 may be formed of a third metal layer 033 and a fourth metal layer 034 that may overlap.
  • each compensation capacitor 03 in at least a part of the compensation capacitors 03 may be formed by the overlapping first metal layer 031 and the second metal layer 032, and by the overlapping third metal layer 033 and the fourth metal layer 034 form. That is, each compensation capacitor 03 may include two kinds of capacitors.
  • each compensation capacitor 03 includes: overlapping first metal layer 031 and second metal layer 032 , and overlapping third metal layer 033 and fourth metal layer 034. That is, each compensation capacitor 03 may include two types of capacitors formed by four metal layers. By setting a larger number of compensation capacitors 03, the effective compensation for the capacitance value of the target node P1 can be further realized.
  • the number of metal layers included in the compensation capacitor 03 can also be adjusted according to the length of the first connecting line L1 to set the capacitance value of the compensation capacitor 03 .
  • the compensation capacitor 03 can be set to include only overlapping the first metal layer 031 and the second metal layer 032.
  • the target node P1 in the embodiment of the present disclosure is additionally provided with a capacitor c3 .
  • any two of the first metal layer 031 , the second metal layer 032 , the third metal layer 033 and the fourth metal layer 034 included in the compensation capacitor 03 may be on different layers. Located on different layers may refer to being located on different layers.
  • the pixel circuit in the display panel may include: an active layer P-Si, a first gate metal layer GATE1 , a second gate metal layer GATE1 , and a second gate electrode which are sequentially arranged in a direction away from the base substrate 00 .
  • the buffer layer BUFFER located between the active layer P-Si and the base substrate 00, the first gate insulating layer GI1 located between the active layer P-Si and the first gate metal layer GATE1, located in the first gate metal a second gate insulating layer GI2 between the layer GATE1 and the second gate metal layer GATE2, an interlayer ILD between the second gate metal layer GATE2 and the first source-drain metal layer SD1, and a first source-drain layer A passivation layer PVX between the metal layer SD1 and the second source-drain metal layer SD2.
  • the first source-drain metal layer SD1 is coupled to the active layer P-Si.
  • the first metal layer 031 may be located in the same layer as one of the first gate metal layer GATE1 and the second gate metal layer GATE2, and the second metal layer 032 may It is located in the same layer as another gate metal layer in the first gate metal layer GATE1 and the second gate metal layer GATE2.
  • the third metal layer 033 may be located on the same layer as one of the first source-drain metal layer SD1 and the second source-drain metal layer SD2, and the fourth metal layer 034 may be the same as the first source-drain metal layer SD1 and the second source-drain metal layer SD2. Another source-drain metal layer in the source-drain metal layer SD2 is located in the same layer.
  • each compensation capacitor 03 may include: a capacitor formed by overlapping the first gate metal layer GATE1 and the second gate metal layer GATE2, and overlapping the first source-drain metal layer SD1 and the second source-drain metal layer SD2 another capacitor formed.
  • Being located in the same layer may refer to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through one patterning process.
  • one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, a plurality of elements, components, structures and/or sections located on the "same layer" are composed of the same material and formed by the same patterning process.
  • the metal layer included in the compensation capacitor 03 is located in the same layer as the metal layer in the pixel circuit, the process can be simplified and the cost can be saved.
  • a metal layer independent of the pixel circuit may also be provided to form the compensation capacitor described in the above embodiments.
  • FIG. 12 shows a partial structural layout of a compensation capacitor in a display panel
  • FIG. 13 shows another structural layout of a compensation capacitor in a display panel.
  • each compensation capacitor 03 may have an integrated structure. That is, each compensation capacitor 03 may share one second metal layer 032 .
  • the fourth metal layer 034 included in each compensation capacitor 03 may also have an integrated structure. That is, each compensation capacitor 03 may share one fourth metal layer 034 .
  • the second metal layer 032 and the fourth metal layer 034 can be coupled to the power terminal VSS through the same via hole K0 . Because the second metal layer 032 and the fourth metal layer 034 are coupled to the power supply terminal VSS, by only providing one second metal layer 032 and/or only one fourth metal layer 034, the premise of ensuring effective compensation can be achieved. Therefore, the structure is simplified, the cost is saved, and the narrow frame design of the display panel is facilitated.
  • the second metal layers 032 included in each compensation capacitor 03 may also be independent of each other and arranged at intervals.
  • the fourth metal layers 034 included in each compensation capacitor 03 may also be independent of each other and arranged at intervals. This embodiment of the present disclosure does not limit this.
  • the 13 also shows two signal lines 11 and 12 coupled to the clock signal terminal in the pixel circuit, the two signal lines 11 and 12 are generally located between the compensation capacitor 03 and the plurality of first pixel circuits 02 .
  • the first metal layers 031 included in each compensation capacitor 03 may be arranged at intervals along the pixel row direction X1. That is, the first metal layers 031 included in each compensation capacitor 03 may be independent of each other.
  • the third metal layers 033 included in each compensation capacitor 03 may also be arranged at intervals along the pixel row direction X1. That is, the third metal layers 033 included in each compensation capacitor 03 may also be independent of each other.
  • the orthographic projection of the first metal layer 031 on the base substrate 00 and the orthographic projection of the third metal layer 033 on the base substrate 00 may be All have a strip structure.
  • the strip structure can extend along the pixel column direction X2 and be coupled to the target node P1.
  • first metal layer 031 and the third metal layer 033 may not overlap, and the first metal layer 031 and the third metal layer 033 may also have other shapes, such as an ellipse.
  • the display panel may further include: at least one second connection line L2 located in the peripheral area A3 .
  • Both the first metal layer 031 and the third metal layer 033 may be coupled to the target node P1 through the second connection line L2.
  • the first metal layer 031 and the second connection trace L2 may be coupled through the first via K1, and the third metal layer 033 and the first metal layer 031 may be coupled through the second The via hole K2 is coupled.
  • the third metal layer 033 can also be coupled to the second connection trace L2 through the first via hole K1, and the first metal layer 031 and the third metal layer 033 through the second via hole K2. coupled. That is, in the embodiment of the present disclosure, one target metal layer among the first metal layer 031 and the third metal layer 033 may be set to be directly coupled to the second connection trace L2, and another target metal layer other than the target metal layer may be set. The metal layer is directly coupled to the target metal layer.
  • first metal layer 031 and the second connection trace L2 may be coupled through the first via K1
  • another part of the third metal layer 033 may be coupled to the second connection trace through the first via K1 L2 coupling.
  • each of the second connection lines L2 included in the display panel may be located at the same layer as the second source-drain metal layer SD2 included in the pixel circuit. In this way, the structure can be simplified and the cost can be saved.
  • FIG. 15 shows a partial area structure layout of a display panel. 12, 14 and 15, it can be seen that in each compensation capacitor 03, the first metal layer 031 and the third metal layer 033 can be coupled to one end of the second connecting line L2 through a first via K1 , the other end of the second connecting line L2 is coupled to the target node P1. 12, 14 and 15, it can be seen that each of the first vias K1 can be arranged at intervals along the pixel row direction X1, and each of the second vias K2 can also be arranged at intervals along the pixel row direction X1. .
  • the display panel may further include: a first flat layer PLN1 , a first flat layer PLN1 , a The second flattening layer PLN2 and the third flattening layer PLN3.
  • the orthographic projection of the first flat layer PLN1 on the base substrate 00 may cover the orthographic projection of the first via hole K1 on the base substrate 00, and the orthographic projection of the second flat layer PLN2 on the base substrate 00 may cover the orthographic projection of the second flat layer PLN2 on the base substrate 00.
  • An orthographic projection of the via hole K1 on the base substrate 00 , and the orthographic projection of the third flat layer PLN3 on the base substrate 00 may not overlap with the orthographic projection of the first via hole K1 on the base substrate 00 .
  • the first flattening layer PLN1 , the second flattening layer PLN2 and the third flattening layer PLN3 may all be located on the side of the second connection line L2 away from the base substrate 00 .
  • FIG. 17 is a schematic structural diagram of still another display panel provided by an embodiment of the present disclosure.
  • the peripheral area A3 may include: a first area A31 and a second area A32 arranged along the pixel column direction X2, and the second area A32 is close to the second display area relative to the first area A31 A2.
  • each first pixel circuit 02 in the display panel may be located in the second area A32, and each compensation capacitor 03 in the display panel may be. Located in the first area A31.
  • this arrangement can facilitate the coupling of the first pixel circuit 02 and the first light-emitting element 01 , reduce the length of the first connection line L1 as much as possible, save wiring costs and simplify wiring.
  • the plurality of first pixel circuits 02 and the compensation capacitors 03 shown therein can actually be considered to be located on the side of the upper frame of the display panel.
  • the first via hole K1 described in the above embodiment may be located in the third area A33 of the peripheral area A3
  • the third area A33 may be located in the third area A33 of the peripheral area A3
  • the second via hole K2 described in the above embodiment may be located in the first area A31 of the peripheral area A3.
  • the first connecting wire L1 described in the embodiment of the present disclosure may be a transparent conductive wire.
  • the first connection line L1 may be made of transparent materials such as indium tin oxide (ITO) or indium gallium zinc oxide (IGZO). If the first connection wire L1 is made of ITO material, the first connection wire L1 may also be called an ITO wire.
  • the display panel may generally include a plurality of first connection lines L1, and at least two of the plurality of first connection lines L1 may be located in different layers.
  • FIG. 18 is a schematic structural diagram of a display panel including a first connection line L1 provided by an embodiment of the present disclosure.
  • the plurality of first connection wires L1 may include at least one first type of first connection wire L1_1 at the same layer, at least one second type of first connection wire L1_2 at the same layer, and at least one first type of connection wire L1_2 at the same layer.
  • any two types of first connection wires L1 may be located at different layers. In this way, wiring can be facilitated.
  • the first type of first connection trace L1_1 may be located on the same layer as the metal layer M1
  • the second type of first connection trace L1_2 may be located at the same layer as the metal layer M2
  • the third type of first connection trace L1_2 may be located at the same layer as the metal layer M2.
  • the first connection line L1_3 may be located at the same layer as the metal layer M3.
  • the metal layers M1 to M3 may be located on the same layer as the metal layers in the display panel, or may also be separately and additionally provided metal layers.
  • the first display area A1 may be divided into three areas according to the pixel column direction and/or the pixel row direction.
  • each of the first light emitting elements 01 in one area can be coupled to the first pixel circuit 02 through the first type of first connection wires L1_1.
  • Each of the first light emitting elements 01 in one area may be coupled to the first pixel circuit 02 through the second type of first connection wires L1_2.
  • Each of the first light emitting elements 01 in one area may be coupled to the first pixel circuit 02 through the third type of first connection wires L1_3.
  • FIG. 22 shows a partial area layout of the overall structure of a display panel. Referring to FIG. 22 , it can be further seen that the via hole through which the compensation capacitor O3 is coupled with the second connecting line L2 is located in the third area A33 of the peripheral area A3 .
  • an embodiment of the present disclosure provides a display panel including a first light emitting element located in a first display area, a first pixel circuit and a compensation capacitor located in a peripheral area.
  • the first pixel circuit may be coupled to the first light emitting element through a first connection wire.
  • the first metal layer in the compensation capacitor can be coupled to a target node, the second metal layer can be coupled to a power terminal, and the target node is a node where the first connection line and the first pixel circuit are coupled.
  • FIG. 23 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the display device may include: a photosensitive sensor 10 , and a display panel 000 as shown in the above figures.
  • the photosensitive sensor 10 may be located in the first display area A1 of the display panel 000 .
  • the first display area A1 may be a rectangle as shown in FIG. 23 , and the area of the orthographic projection of the photosensitive sensor 10 on the base substrate 00 may be less than or equal to the area of the inscribed circle of the first display area A1 . That is, the size of the area where the photosensitive sensor 10 is located may be smaller than or equal to the size of the inscribed circle of the first display area A1. For example, referring to FIG. 23 , referring to FIG.
  • the size of the area where the photosensitive sensor 10 is located is equal to the size of the inscribed circle Y0 of the first display area A1, that is, the shape of the area where the photosensitive sensor 10 is located may be a circle, Correspondingly, the area where the photosensitive sensor 10 is located may also be referred to as a light-transmitting hole.
  • the first display area A1 may also have other shapes than rectangles, such as circles.
  • the display device may be any of: an OLED display device, an active-matrix organic light-emitting diode (active-matrix organic light-emitting diode, AMOLED) display device, a mobile phone, a tablet computer, a flexible display device, a television, and a display. Products or parts with display capabilities.
  • an OLED display device an active-matrix organic light-emitting diode (active-matrix organic light-emitting diode, AMOLED) display device
  • AMOLED active-matrix organic light-emitting diode

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Abstract

本公开提供了一种显示面板及显示装置，属于显示技术领域。其中，该显示面板包括位于第一显示区的第一发光元件，以及位于周边区的第一像素电路和补偿电容。该第一像素电路可以通过第一连接走线与第一发光元件耦接。该补偿电容中的第一金属层可以与目标节点耦接，第二金属层可以与电源端耦接，该目标节点为第一连接走线和第一像素电路耦接的节点。如此，可以实现对第一连接走线上的寄生电容的有效补偿，确保第一显示区中各个第一发光元件的发光亮度均一性较好。进而，可以使得显示面板的显示效果较好。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种显示面板及显示装置。
背景技术
有机发光二极管(organic light-emitting diode，OLED)显示面板由于具有自发光，驱动电压低，以及响应速度快等优点而得到了广泛的应用。OLED显示面板一般包括：多个像素单元，每个像素单元包括发光元件以及与该发光元件耦接的像素电路。
发明内容
本公开提供了一种显示面板及显示装置，所述技术方案如下：
一方面，提供了一种显示面板，所述显示面板包括：
衬底基板，具有第一显示区、第二显示区和周边区，所述第二显示区至少部分围绕所述第一显示区，所述周边区至少部分围绕所述第二显示区；
多个第一发光元件，位于所述第一显示区；
多个第一像素电路，位于所述周边区；
多个第二像素电路和多个第二发光元件，位于所述第二显示区，所述多个第二像素电路中的至少一个第二像素电路与所述多个第二发光元件中的至少一个第二发光元件耦接；
至少一条第一连接走线，位于所述周边区、所述第二显示区和所述第一显示区，所述多个第一像素电路中的至少一个第一像素电路与所述多个第一发光元件中的至少一个第一发光元件通过所述第一连接走线耦接；
至少一个补偿电容，位于所述周边区，所述补偿电容包括存在交叠的第一金属层和第二金属层，所述第一金属层与目标节点耦接，所述第二金属层与电源端耦接，所述目标节点为所述第一像素电路与所述第一连接走线耦接的节点。
可选的，各个所述第一像素电路对应的补偿电容的容值与所耦接的第一连 接走线的长度负相关。
可选的，各个所述第一像素电路对应的补偿电容中，存在交叠的两个金属层的交叠面积与所耦接的第一连接走线的长度负相关。
可选的，所述显示面板包括：多个像素电路组，每个所述像素电路组包括：至少两个所述第一像素电路；
其中，每个所述像素电路组对应的各个补偿电容的容值相同，且不同的所述像素电路组对应的补偿电容的容值不同。
可选的，所述多个像素电路组包括：沿像素行方向依次间隔排布的第一子像素电路组、第二子像素电路组和第三子像素电路组；
其中，所述第一子像素电路组对应的各个补偿电容的容值小于所述第二子像素电路组对应的各个补偿电容的容值，且所述第二子像素电路组对应的各个补偿电容的容值大于所述第三子像素电路组对应的各个补偿电容的容值。
可选的，所述周边区包括：沿像素列方向排布的第一区域和第二区域，且所述第二区域相对于所述第一区域靠近所述第二显示区；
其中，各个所述第一像素电路位于所述第一区域，各个所述补偿电容位于所述第二区域。
可选的，所述显示面板包括多个所述补偿电容，各个所述补偿电容包括的第二金属层为一体结构，且各个所述补偿电容包括的第一金属层沿像素行方向间隔排布。
可选的，所述至少一个补偿电容包括多个第一组补偿电容，所述多个第一组补偿电容中的至少一个第一组补偿电容包括存在交叠的第三金属层和第四金属层，且所述第一金属层、所述第二金属层、所述第三金属层和所述第四金属层中，任意两个金属层位于异层；
其中，所述第三金属层与所述目标节点耦接，所述第四金属层与所述电源端耦接。
可选的，所述至少一个补偿电容还包括：多个第二组补偿电容和多个第三组补偿电容；
所述多个第一组补偿电容中的至少一个第一组补偿电容还包括存在交叠的第一金属层和第二金属层，所述多个第二组补偿电容中的至少一个第二组补偿电容还包括存在交叠的第一金属层和第二金属层，所述多个第三组补偿电容中 的至少一个第三组补偿电容还包括存在交叠的第一金属层和第二金属层；
其中，所述多个第一组补偿电容、所述多个第二组补偿电容和所述多个第三组补偿电容沿像素行方向依次间隔排布，且第二组补偿电容包括的第一金属层沿像素列方向的高度，大于第三组补偿电容包括的第一金属层沿像素列方向的高度，且大于第二组补偿电容包括的第一金属层沿像素列方向的高度。
可选的，所述显示面板中的像素电路包括：沿远离所述衬底基板的方向依次排布的有源层，第一栅金属层，第二栅金属层，第一源漏金属层和第二源漏金属层；
其中，所述第一金属层与所述第一栅金属层和所述第二栅金属层中的一个栅金属层位于同层，所述第二金属层与所述第一栅金属层和所述第二栅金属层中的另一个栅金属层位于同层；
所述第三金属层与所述第一源漏金属层和所述第二源漏金属层中的一个源漏金属层位于同层，所述第四金属层与所述第一源漏金属层和所述第二源漏金属层中的另一个源漏金属层位于同层。
可选的，所述第一金属层与所述第一栅金属层位于同层，所述第二金属层与所述第二栅金属层位于同层。
可选的，所述第三金属层与所述第一源漏金属层位于同层，所述第四金属层与所述第二源漏金属层位于同层。
可选的，每个所述补偿电容均包括：存在交叠的所述第一金属层和所述第二金属层，以及存在交叠的所述第三金属层和所述第四金属层。
可选的，各个所述补偿电容包括的第四金属层为一体结构，且各个所述补偿电容包括的第三金属层沿像素行方向间隔排布。
可选的，所述第一金属层在所述衬底基板上的正投影，以及所述第三金属层在所述衬底基板上的正投影均呈条状结构，且所述条状结构沿像素列方向延伸。
可选的，所述显示面板还包括：
位于所述周边区的至少一条第二连接走线，所述第一金属层和所述第三金属层均通过所述第二连接走线与所述目标节点耦接。
可选的，所述周边区包括：沿像素列方向排布的第一区域、第三区域和第二区域，且所述第二区域相对于所述第一区域靠近所述第二显示区；所述第一 金属层和所述第二连接走线通过第一过孔耦接，所述第三金属层和所述第一金属层通过第二过孔耦接；
其中，所述第一过孔位于所述周边区的第三区域，所述第二过孔位于所述周边区的第一区域。
可选的，所述显示面板还包括：沿所述第一过孔远离所述衬底基板的方向依次排布的第一平坦层、第二平坦层和第三平坦层；
其中，所述第一平坦层在所述衬底基板上的正投影覆盖所述第一过孔在所述衬底基板上的正投影，所述第二平坦层在所述衬底基板上的正投影覆盖所述第一过孔在所述衬底基板上的正投影，且所述第三平坦层在所述衬底基板上的正投影与所述第一过孔在所述衬底基板上的正投影不重叠。
可选的，所述第一平坦层、所述第二平坦层和所述第三平坦层均位于所述第二连接走线远离所述衬底基板的一侧。
可选的，所述第二连接走线与所述显示面板中像素电路包括的第二源漏金属层位于同层。
可选的，所述显示面板包括与所述至少一条第一连接走线一一对应的至少一个补偿电容；
其中，每个所述补偿电容与对应的一条所述第一连接走线耦接于目标节点。
可选的，所述显示面板包括多条所述第一连接走线，且多条所述第一连接走线中至少两条第一连接走线位于异层。
可选的，所述多条第一连接走线包括至少一条位于同层的第一类第一连接走线，至少一条位于同层的第二类第一连接走线，以及至少一条位于同层的第三类第一连接走线；
并且，所述第一类第一连接走线、所述第二类第一连接走线和所述第三类第一连接走线中，任意两类第一连接走线位于异层。
可选的，所述第一连接走线为透明导电线。
另一方面，提供了一种显示装置，其中，所述显示装置包括：感光传感器，以及如上述方面所述的显示面板；
其中，所述感光传感器位于所述显示面板的第一显示区内。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种第一连接走线与发光元件的耦接示意图；
图2是本公开实施例提供的一种显示面板的结构示意图；
图3是本公开实施例提供的另一种显示面板的结构示意图；
图4是本公开实施例提供的又一种显示面板的结构示意图；
图5是本公开实施例提供的另一种第一连接走线与发光元件的耦接示意图；
图6是本公开实施例提供的再一种显示面板的结构示意图；
图7是本公开实施例提供的再一种显示面板的结构示意图；
图8是本公开实施例提供的一种补偿电容的结构版图；
图9是本公开实施例提供的一种补偿电容中部分金属层的结构版图；
图10是本公开实施例提供的一种补偿电容中第一金属层的结构版图；
图11是本公开实施例提供的一种像素电路的结构示意图；
图12是本公开实施例提供的再一种显示面板中补偿电容的部分结构版图；
图13是本公开实施例提供的再一种显示面板中补偿电容的部分结构版图；
图14是本公开实施例提供的再一种显示面板的结构示意图；
图15是本公开实施例提供的再一种显示面板的结构示意图；
图16是本公开实施例提供的一种包括平坦层和过孔的结构示意图；
图17是本公开实施例提供的再一种显示面板的结构示意图；
图18是本公开实施例提供的一种第一连接走线的结构示意图；
图19是本公开实施例提供的一种第一类第一连接走线的结构示意图；
图20是本公开实施例提供的一种第二类第一连接走线的结构示意图；
图21是本公开实施例提供的一种第三类第一连接走线的结构示意图；
图22是本公开实施例提供的再一种显示面板的结构示意图；
图23是本公开实施例提供的一种显示装置的结构示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开作进一步地详细描述。
随着显示技术的发展，现有的刘海屏或水滴屏设计均逐渐不能满足用户对显示面板高屏占比的需求，一系列具有透光显示区的高PPI的OLED显示面板应运而生，PPI为分辨率的单位，英文全称为pixel per inch，代表显示面板每英寸包括的像素数量。该类显示面板中，可以将感光传感器(如，摄像头)等硬件设置于透光显示区，如此，透光显示区也可以称为屏下摄像头区域，在本公开实施例中，用第一显示区指代该屏下摄像头区域。
在本公开实施例中，屏下摄像头区域仅保留电致发光器件(electroluminesc ence，EL)，该EL即为本公开实施例记载的第一发光元件。驱动该屏下摄像头区域内的EL发光的像素电路(即，本公开实施例记载的第一像素电路)位于围绕屏下摄像头区域的周边区，如显示面板的上边框。然后，再采用导电线(即，本公开实施例记载的第一连接走线)耦接第一像素电路和第一发光元件，从而实现对第一发光元件的可靠驱动。耦接可以是指电连接。
例如，图1示出了第一连接走线耦接第一发光元件的示意图。参考图1可以看出，第一连接走线L1可以经第一像素电路(未示出)延伸至第一发光元件01，并与发光元件01的阳极耦接。假设将耦接至第一发光元件01的节点标识为P1，则参考图1可以看出，P1节点和第一发光元件01的阴极之间存在寄生电容c0，且第一连接走线L1上也存在寄生电容c1。
经测试，因不同位置处的第一像素电路与所耦接的第一发光元件的距离不同，故显示面板中所设置的各条第一连接走线的长度不同。由此，导致上述图1所示的寄生电容c1的大小不同，即不同第一发光元件01的节点P1处的容值的大小不同。进而导致不同第一发光元件01的发光亮度不同，影响显示效果。
本公开实施例提供了一种包括补偿电容的显示面板，该补偿电容可以实现对节点P1处容值的有效补偿，使得不同第一发光元件的发光亮度的均一性较好，达到屏下摄像头区域的显示效果与其他正常显示区域的显示效果一致的目的。
图2是本公开实施例提供的一种显示面板的结构示意图。如图2所示，该显示面板可以包括：衬底基板00，该衬底基板00可以具有第一显示区A1、第 二显示区A2和周边区A3，该第二显示区A2可以至少部分围绕第一显示区A1，且该周边区A3可以至少部分围绕该第二显示区A2。
例如，图2示出的第一显示区A1位于衬底基板00的上方中间位置处，第二显示区A2围绕该第一显示区A1，即该第一显示区A1被第二显示区A2包围。且周边区A3围绕该第二显示区A2，即该第二显示区A2被周边区A3包围。
当然，在一些实施例中，该第一显示区A1也可以不位于图2所示的位置，而位于衬底基板00上的其他位置。如，结合图2，该第一显示区A1可以位于衬底基板00的左上角位置或右上角位置处。
图3是本公开实施例提供的另一种显示面板的结构示意图。结合图2和图3可以看出，该显示面板还可以包括：位于第一显示区A1的多个第一发光元件01。位于周边区A3的多个第一像素电路02和至少一个补偿电容03。位于第二显示区A2的多个第二像素电路04和多个第二发光元件05。以及位于周边区A3、第二显示区A2和第一显示区A1的至少一条第一连接走线L1。
其中，多个第一像素电路02中的至少一个第一像素电路02与多个第一发光元件01中的至少一个第一发光元件01可以通过第一连接走线L1耦接。即参考图3，第一连接走线L1的一端可以与第一像素电路02耦接(耦接点为图中所示的目标节点P1)，第一连接走线L1的另一端可以与第一发光元件01耦接。如此，即实现了第一像素电路02与第一发光元件01的有效耦接。该至少一个第一像素电路02可以用于为所耦接的第一发光元件01提供驱动信号，从而驱动该第一发光元件01发光。多个第二像素电路04中的至少一个第二像素电路04可以与多个第二发光元件05中的至少一个第二发光元件05耦接，该至少一个第二像素电路04可以用于为所耦接的第二发光元件05提供驱动信号，从而驱动该第二发光元件05发光。例如，图3所示的显示面板中，每个第二像素电路04均与一个第二发光元件05耦接。每个补偿电容03可以与一个目标节点P1耦接，以实现对目标节点P1处的容值补偿。
可选的，图4是本公开实施例提供的又一种显示面板的结构示意图。结合图3和图4可以看出，每个补偿电容03可以包括存在交叠的第一金属层031和第二金属层032。其中，该第一金属层031可以与目标节点P1耦接，该第二金属层032可以与电源端VSS耦接。由此，第一金属层031和第二金属层032交叠即可以有效形成补偿电容03。
示例的，在图1所示结构基础上，结合图4所示的补偿电容03，图5示出了第一金属层031和第二金属层032交叠形成的电容c2(即，补偿电容03)的可选电路结构。对比图1和图5可以看出，本公开实施例的目标节点P1处还额外增加有电容c2。
此外，基于电容容值的计算公式“C＝εS/d，ε为极板(即，用于形成补偿电容的金属层)间介质的介电常数，S为极板间交叠面积，d为极板间的距离”，以及第一连接走线L1的长度与寄生电容的容值正相关等原理可知：在本公开实施例中，能够基于第一连接走线L1的长度，灵活设置第一金属层031和第二金属层032的交叠面积，和/或，第一金属层031和第二金属层032的距离，以达到对目标节点P1的有效补偿。使得不同第一发光元件的发光亮度的均一性较好。
可选的，该第一显示区A1可以为透光显示区，该第二显示区A2可以为非透光显示区，该周边区A3可以为非显示区。即，本公开实施例记载的第一显示区A1可透光，可以将感光传感器等显示装置所需硬件结构设置于第一显示区A1。如此，不仅为真全面屏的实现奠定了基础，且因第一显示区A1内仅包括第一发光元件01，而不包括驱动第一发光元件01发光的第一像素电路02，故还确保了第一显示区A1的透光率较好，以及确保了显示面板的分辨率较好。
可选的，该第一显示区A1的分辨率可以小于等于第二显示区A2的分辨率。例如，第一显示区A1的面积与第二显示区A2的面积可以相同，且第一显示区A1所包括的第一发光元件01与第二显示区A2所包括的第二发光元件05的数量也相同。或者，如图2和图3所示，第一显示区A1的面积可以小于第二显示区A2的面积，且第一显示区A1所包括的第一发光元件01相对于第二显示区A2所包括的第二发光元件05的数量可以较少。如此，第二显示区A2也可以称为主显示区。或者，第一显示区A1的分辨率可以大于第二显示区A2的分辨率。即，该第一显示区A1的面积相对于第二显示区A2的面积较大，且第一显示区A1所包括的第一发光元件01相对于第二显示区A2所包括的第二发光元件05的数量较多。
综上所述，本公开实施例提供了一种显示面板，该显示面板包括位于第一显示区的第一发光元件，以及位于周边区的第一像素电路和补偿电容。该第一像素电路可以通过第一连接走线与第一发光元件耦接。该补偿电容中的第一金属层可以与目标节点耦接，第二金属层可以与电源端耦接，该目标节点为第一 连接走线和第一像素电路耦接的节点。如此，可以实现对第一连接走线上的寄生电容的有效补偿，确保第一显示区中各个第一发光元件的发光亮度均一性较好。进而，可以使得显示面板的显示效果较好。
在本公开实施例中，各个第一像素电路02对应的补偿电容03的容值可以与所耦接的第一连接走线L1的长度负相关。即，第一连接走线L1的长度越长，补偿电容03的容值越小；第一连接走线L1的长度越短，补偿电容03的容值越大。其中，第一像素电路02对应的补偿电容03是指：第一像素电路02中的目标节点P1所耦接的补偿电容03。
因第一连接走线L1的长度与存在的寄生电容一般正相关。即第一连接走线L1的长度越长，第一连接走线L1上的寄生电容的容值则越大，第一连接走线L1的长度越长，第一连接走线L1上的寄生电容的容值则越小。且，针对寄生电容较大的第一连接走线L1，对应的补偿电容03的容值应该越小，即可以补偿的较少。反之，寄生电容较小的第一连接走线L1，对应的补偿电容03的容值应该较大，即可以补偿的较多。故，通过设置第一像素电路02对应的补偿电容03的容值可以与所耦接的第一连接走线L1的长度负相关，可以使得耦接至不同第一连接走线L1的不同第一发光元件01的亮度尽可能相同，确保各个第一发光元件01的发光亮度的均一性较好。进而，可以有效改善显示面板的显示效果。
可选的，基于上述实施例记载的电容容值的计算公式可知，在本公开实施例中，可以通过设置各个第一像素电路02对应的补偿电容03中，存在交叠的两个金属层的交叠面积与所耦接的第一连接走线L1的长度负相关。
如，参考图4，假设补偿电容03包括存在交叠的第一金属层031和第二金属层032。若第一连接走线L1的长度较长，则可以设置第一金属层031和第二金属层032的交叠面积较小。反之，若第一连接走线L1的长度较短，则可以设置第一金属层031和第二金属层032的交叠面积较大。对于包括其他存在交叠的金属层的结构，设置原理同理，后续实施例不再赘述。
可选的，在本公开实施例中，结合图3，显示面板还可以包括：多个像素电路组，每个像素电路组可以包括至少两个第一像素电路02。
其中，每个像素电路组对应的各个补偿电容03的容值可以相同，且不同的像素电路组对应的补偿电容03的容值可以不同。
例如，参考图6和图7，假设多个像素电路组可以包括沿像素行方向X1依次间隔排布的第一子像素电路组Z11、第二子像素电路组Z12和第三子像素电路组Z13。即，第二子像素电路组Z12相对于第一子像素电路组Z11和第三子像素电路组Z13而言，更靠近第一显示区A1。则可以确定，第二子像素电路组Z12相对于第一子像素电路组Z11和第三子像素电路组Z13而言，所包括的各个第一像素电路02与第一发光元件01的距离更近，各个第一像素电路02与第一发光元件01耦接用的第一连接走线L1更短。故，继续参考图6和图7可以看出，第一子像素电路组Z11对应的各个补偿电容03的容值小于第二子像素电路组Z12对应的各个补偿电容03的容值，且第二子像素电路组Z12对应的各个补偿电容03的容值可以大于第三子像素电路组Z13对应的各个补偿电容03的容值。即，沿第二子像素电路组Z12向第一子像素电路组Z11靠近的方向，以及沿第二子像素电路组Z12向第三子像素电路组Z13靠近的方向，所需设置的补偿电容03的容值均递减。
需要说明的是，图6和图7均以第一金属层031和第二金属层032的交叠面积为例，示出不同像素电路组对应的补偿电容03的容值。且，图6是通过设置第二金属层032为“凸”字形结构，且设置不同像素电路组对应的第一金属层031的高度均相同，以使得不同像素电路组Z1对应的补偿电容03中第一金属层031和第二金属层032的交叠面积不同。图7是通过设置不同像素电路组Z1对应的第一金属层031的高度不同，且设置第二金属层032为矩形结构，以使得不同像素电路组Z1对应的补偿电容03中第一金属层031和第二金属层032的交叠面积不同。此外，图6和图7均未示出各像素电路组Z1的具体结构，且均未示出第一显示区A1内包括的第一发光元件01。
结合图6和图7可以确定，在本公开实施例中，可以通过灵活调整存在交叠的两个金属层中任一金属层的结构，以改变两个金属层的交叠面积。
可选的，在本公开实施例中，显示面板可以包括与至少一条第一连接走线L1一一对应的至少一个补偿电容03，且每个补偿电容03与对应的一条第一连接走线L1耦接于目标节点P1。即，显示面板中的每条第一连接走线L1均对应设置有一个补偿电容03。
可选的，图8是本公开实施例提供的再一种显示面板的结构示意图。如图8所示，该显示面板包括的至少一个补偿电容03可以包括多个第一组补偿电容 03A。图8未示出各像素电路组的具体结构，且未示出第一显示区A1内包括的第一发光元件01。
图9是本公开实施例提供的再一种显示面板的结构示意图。如图9所示，括多个第一组补偿电容03A中，至少一个第一组补偿电容03A可以包括存在交叠的第三金属层033和第四金属层034。其中，第三金属层033可以与目标节点P1耦接，第四金属层034可以与电源端VSS耦接。由此，第三金属层033和第四金属层034交叠即可以再有效形成一个补偿电容03。
例如，图9所示的每个第一组补偿电容03A均包括存在交叠的第三金属层033和第四金属层034，且还包括存在交叠的第一金属层031和第二金属层032。
此外，继续参考图8可以看出，至少一个补偿电容03还可以包括多个第二组补偿电容03B和多个第三组补偿电容03C。
其中，至少一个第一组补偿电容03A还可以包括存在交叠的第一金属层031和第二金属层032。至少一个第二组补偿电容03B可以包括存在交叠的第一金属层031和第二金属层032，以及存在交叠的第三金属层033和第四金属层034。至少一个第三组补偿电容03C可以包括存在交叠的第一金属层031和第二金属层032，以及存在交叠的第三金属层033和第四金属层034。需要说明的是，图9仅示出了第一组补偿电容03A的可选结构。
可选的，结合图8可以看出，该多个第一组补偿电容03A可以与第一子像素电路组Z11对应，该多个第二组补偿电容03B可以与第二子像素电路组Z12对应，该多个第三组补偿电容03C可以与第三子像素电路组Z13对应。
如此，若以第一金属层031沿像素列方向X2的高度代表第一金属层031与第二金属层032的交叠面积，则参考图7和图10可以看出，第二组补偿电容03B包括的第一金属层031沿像素列方向X2的高度，可以大于第三组补偿电容03C包括的第一金属层031沿像素列方向X2的高度，且可以大于第一组补偿电容03A包括的第一金属层031沿像素列方向X2的高度。即，沿第二组补偿电容03B向第一组补偿电容03A靠近的方向，以及沿第二组补偿电容03B向第三组补偿电容03C靠近的方向，第一金属层031的高度均递减。
可选的，结合上述实施例可知，显示面板包括的多个补偿电容03中，至少部分补偿电容03中的每个补偿电容03可以由存在交叠的第一金属层031和第二金属层032形成。或者，至少部分补偿电容03中的每个补偿电容03可以由 存在交叠的第三金属层033和第四金属层034形成。或者，至少部分补偿电容03中的每个补偿电容03可以由存在交叠的第一金属层031和第二金属层032形成，且由存在交叠的第三金属层033和第四金属层034形成。即，每个补偿电容03可以包括两种电容。
例如，结合图9所示的显示面板，每个补偿电容03均包括：存在交叠的第一金属层031和第二金属层032，以及存在交叠的第三金属层033和第四金属层034。即每个补偿电容03均可以包括由四层金属层形成的两种电容。通过设置较多数量的补偿电容03，可以进一步实现对目标节点P1的容值的有效补偿。
基于此还可以确定，还可以根据第一连接走线L1的长度来调整补偿电容03包括的金属层数量，以设置补偿电容03的容值。且基于第一连接走线L1的长度与补偿电容03负相关的关系，以及电容并联容值增大的原理可知，第一连接走线L1的长度越长，可以设置补偿电容03仅包括交叠的第一金属层031和第二金属层032。第一连接走线L1的长度越短，可以设置补偿电容03包括存在交叠的第一金属层031和第二金属层032，以及存在交叠的第三金属层033和第四金属层034。
示例的，在图1所示结构基础上，结合图9所示的补偿电容03，图5还示出了第三金属层033和第四金属层034交叠形成的电容c3(即，补偿电容03)的可选电路结构。即，对比图1和图5可以看出，本公开实施例的目标节点P1处还额外增加有电容c3。
可选的，结合上述实施例可知，在本公开实施例中，补偿电容03包括的第一金属层031、第二金属层032、第三金属层033和第四金属层034中，任意两个金属层可以位于异层。位于异层可以是指位于不同层。
可选的，参考图11所示结构可知，显示面板中的像素电路可以包括：沿远离衬底基板00的方向依次排布的有源层P-Si、第一栅金属层GATE1、第二栅金属层GATE2、第一源漏金属层SD1和第二源漏金属层SD2。以及，位于有源层P-Si和衬底基板00之间的缓冲层BUFFER，位于有源层P-Si和第一栅金属层GATE1之间的第一栅绝缘层GI1，位于第一栅金属层GATE1和第二栅金属层GATE2之间的第二栅绝缘层GI2，位于第二栅金属层GATE2和第一源漏金属层SD1之间的层间介定层ILD，以及位于第一源漏金属层SD1和第二源漏金属层SD2之间的钝化层PVX。第一源漏金属层SD1与有源层P-Si耦接。
在本公开实施例中，每个补偿电容03中，第一金属层031可以与第一栅金属层GATE1和第二栅金属层GATE2中的一个栅金属层位于同层，第二金属层032可以与第一栅金属层GATE1和第二栅金属层GATE2中的另一个栅金属层位于同层。第三金属层033可以与第一源漏金属层SD1和第二源漏金属层SD2中的一个源漏金属层位于同层，第四金属层034可以与第一源漏金属层SD1和第二源漏金属层SD2中的另一个源漏金属层位于同层。
例如，参考图9可以看出，在本公开实施例中，第一金属层031可以与第一栅金属层GATE1位于同层，第二金属层032可以与第二栅金属层GATE2位于同层。第三金属层033可以与第一源漏金属层SD1位于同层，第四金属层034可以与第二源漏金属层SD2位于同层。换言之，每个补偿电容03可以包括：由第一栅金属层GATE1和第二栅金属层GATE2交叠形成的一个电容，以及由第一源漏金属层SD1和第二源漏金属层SD2交叠形成的另一个电容。
位于同层可以是指：采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。即，位于“同层”的多个元件、部件、结构和/或部分由相同的材料构成，并通过同一次构图工艺形成。
通过设置补偿电容03包括的金属层与像素电路中的金属层位于同层，可以简化工艺，节省成本。当然，在一些实施例中，也可以设置独立于像素电路的金属层来形成上述实施例记载的补偿电容。
以图9所示结构为例，图12示出了一种显示面板中补偿电容的部分结构版图，图13示出了一种显示面板中补偿电容的另一部分结构版图。
可选的，参考图9、图12和图13可以看出，在本公开实施例中，各个补偿电容03包括的第二金属层032可以为一体结构。即，各个补偿电容03可以共用一个第二金属层032。各个补偿电容03包括的第四金属层034也可以为一体结构。即，各个补偿电容03可以共用一个第四金属层034。
并且，参考图13还可以看出，第二金属层032和第四金属层034可以通过同一个转接孔K0与电源端VSS耦接。因该第二金属层032和第四金属层034是与电源端VSS耦接，故通过仅设置一个第二金属层032和/或仅设置一个第四金属层034，可以在确保有效补偿的前提下，简化结构，节省成本，且有利于显 示面板的窄边框设计。
当然，在一些实施例中，各个补偿电容03包括的第二金属层032也可以互相独立，且间隔排布。各个补偿电容03包括的第四金属层034也可以互相独立，且间隔排布。本公开实施例对此不做限定。
其中，图13还示出了像素电路中耦接时钟信号端的两条信号线l1和l2，该两条信号线l1和l2一般位于补偿电容03与多个第一像素电路02之间。
可选的，结合图12和图13可以看出，各个补偿电容03包括的第一金属层031可以沿像素行方向X1间隔排布。即，各个补偿电容03包括的第一金属层031可以相互独立。各个补偿电容03包括的第三金属层033也可以沿像素行方向X1间隔排布。即，各个补偿电容03包括的第三金属层033也可以相互独立。
并且，结合图9和图12还可以看出，在本公开实施例中，第一金属层031在衬底基板00上的正投影和第三金属层033在衬底基板00上的正投影可以均呈条状结构。且该条状结构可以沿像素列方向X2延伸，并耦接至目标节点P1。
当然，在一些实施例中，第一金属层031和第三金属层033也可以不存在交叠，且第一金属层031和第三金属层033也可以呈其他形状，如椭圆。
可选的，继续参考图12和图14示出的再一种显示面板的结构可以看出，该显示面板还可以包括：位于周边区A3的至少一条第二连接走线L2。第一金属层031和第三金属层033均可以通过第二连接走线L2与目标节点P1耦接。
示例的，结合图12和图14可以看出，第一金属层031和第二连接走线L2可以通过第一过孔K1耦接，第三金属层033和第一金属层031可以通过第二过孔K2耦接。当然，在一些实施例中，也可以是第三金属层033通过第一过孔K1与第二连接走线L2耦接，第一金属层031再通过第二过孔K2与第三金属层033耦接。即，在本公开实施例中，可以设置第一金属层031和第三金属层033中的一个目标金属层与第二连接走线L2直接耦接，再设置除目标金属层之外的另一金属层与该目标金属层直接耦接。即，对于除目标金属层之外的另一金属层而言，其与第二连接走线L2可以是间接耦接。在一些实施例中，也可以是一部分第一金属层031和第二连接走线L2通过第一过孔K1耦接，另一部分第三金属层033通过第一过孔K1与第二连接走线L2耦接。
可选的，结合图9，显示面板包括的各条第二连接走线L2可以与像素电路包括的第二源漏金属层SD2可以位于同层。如此，可以简化结构，节省成本。
以图14所示结构为例，图15示出了一种显示面板的部分区域结构版图。结合图12、图14和图15可以看出，每个补偿电容03中，第一金属层031和第三金属层033可以通过一个第一过孔K1耦接至第二连接走线L2的一端，第二连接走线L2的另一端再耦接至目标节点P1。且，结合图12、图14和图15可以看出，各个第一过孔K1可以沿像素行方向X1依次间隔排布，且各个第二过孔K2也可以沿像素行方向X1依次间隔排布。
可选的，参考图16所示的显示面板可知，在本公开实施例中，显示面板还可以包括：沿第一过孔K1远离衬底基板00的方向依次排布的第一平坦层PLN1、第二平坦层PLN2和第三平坦层PLN3。
其中，第一平坦层PLN1在衬底基板00上的正投影可以覆盖第一过孔K1在衬底基板00上的正投影，第二平坦层PLN2在衬底基板00上的正投影可以覆盖第一过孔K1在衬底基板00上的正投影，且第三平坦层PLN3在衬底基板00上的正投影可以与第一过孔K1在衬底基板00上的正投影不重叠。
可选的，继续参考图16可以看出，第一平坦层PLN1、第二平坦层PLN2和第三平坦层PLN3可以均位于第二连接走线L2远离衬底基板00的一侧。
如此，相对于第一平坦层PLN1、第二平坦层PLN2和第三平坦层PLN3均覆盖第一过孔K1的现有技术而言，可以避免因第一平坦层PLN1、第二平坦层PLN2和第三平坦层PLN3的层叠段差较大而导致走线断裂的问题。
图17是本公开实施例提供的再一种显示面板的结构示意图。结合图14和图17可以看出，周边区A3可以包括：沿像素列方向X2排布的第一区域A31和第二区域A32，且第二区域A32相对于第一区域A31靠近第二显示区A2。
可选的，在将周边区A3划分为第一区域A31和第二区域A32的前提下，显示面板中的各个第一像素电路02可以位于第二区域A32，显示面板中的各个补偿电容03可以位于第一区域A31。
结合图14和图17可知，如此设置，可以便于第一像素电路02与第一发光元件01耦接，可以尽可能的减小第一连接走线L1的长度，节省布线成本且简化布线。结合图17所示结构可知，其示出的多个第一像素电路02和补偿电容03其实可以认为是位于显示面板的上边框一侧。
此外，在图17所示结构前提下，再参考图12和14还可以看出，上述实施例记载的第一过孔K1可以位于周边区A3的第三区域A33，该第三区域A33可 以位于周边区A3的第一区域A31和第二区域A32之间。上述实施例记载的第二过孔K2可以位于周边区A3的第一区域A31中。
可选的，为进一步确保第一显示区A1的透光率较好，本公开实施例记载的第一连接走线L1可以为透明导电线。例如，该第一连接走线L1可以由氧化铟锡(indium tin oxide，ITO)或铟镓锌氧化物(indium gallium zinc oxide，IGZO)等透明材料制成。若该第一连接走线L1由ITO材料制成，则该第一连接走线L1也可以称为ITO走线。
可选的，结合上述附图可以看出，显示面板一般可以包括多条第一连接走线L1，且多条第一连接走线L1中至少两条第一连接走线L1可以位于异层。
例如，图18是本公开实施例提供的一种包括第一连接走线L1的显示面板结构示意图。如图17所示，多条第一连接走线L1可以包括至少一条位于同层的第一类第一连接走线L1_1，至少一条位于同层的第二类第一连接走线L1_2，以及至少一条位于同层的第三类第一连接走线L1_3。结合图18可以进一步确定，不同第一连接走线L1的长度一般不同。
其中，第一类第一连接走线L1_1、第二类第一连接走线L1_2和第三类第一连接走线L1_3中，任意两类第一连接走线L1可以位于异层。如此，可以便于布线。例如，参考图19至图21看出，第一类第一连接走线L1_1可以与金属层M1位于同层，第二类第一连接走线L1_2可以与金属层M2位于同层，第三类第一连接走线L1_3可以与金属层M3位于同层。
可选的，该金属层M1至金属层M3可以与显示面板中的金属层位于同层，或者，也可以为单独额外设置的金属层。
可选的，可以将第一显示区A1按像素列方向和/或像素行方向划分为三个区域。其中，一个区域内的各个第一发光元件01可以通过第一类第一连接走线L1_1耦接至第一像素电路02。一个区域内的各个第一发光元件01可以通过第二类第一连接走线L1_2耦接至第一像素电路02。一个区域内的各个第一发光元件01可以通过第三类第一连接走线L1_3耦接至第一像素电路02。
可选的，以上述实施例记载的显示面板为例，图22示出了一种显示面板的整体结构的部分区域版图。参考图22可以进一步看出，补偿电容03与第二连接走线L2耦接的过孔位于周边区A3的第三区域A33。
综上所述，本公开实施例提供了一种显示面板，该显示面板包括位于第一 显示区的第一发光元件，以及位于周边区的第一像素电路和补偿电容。该第一像素电路可以通过第一连接走线与第一发光元件耦接。该补偿电容中的第一金属层可以与目标节点耦接，第二金属层可以与电源端耦接，该目标节点为第一连接走线和第一像素电路耦接的节点。如此，可以实现对第一连接走线上的寄生电容的有效补偿，确保第一显示区中各个第一发光元件的发光亮度均一性较好。进而，可以使得显示面板的显示效果较好。
图23是本公开实施例提供的一种显示装置的结构示意图。如图23所示，该显示装置可以包括：感光传感器10，以及如上述附图所示的显示面板000。其中，该感光传感器10可以位于显示面板000的第一显示区A1内。
可选的，该第一显示区A1可以为图23所示的矩形，感光传感器10在衬底基板00上的正投影的面积可以小于等于第一显示区A1的内切圆的面积。即，感光传感器10所处区域的尺寸可以小于或等于该第一显示区A1的内切圆的尺寸。例如，结合图23，其示出的显示面板中，感光传感器10所处区域的尺寸等于第一显示区A1的内切圆Y0的尺寸，即该感光传感器10所在区域的形状可以为圆形，相应的，该感光传感器10所在区域也可以称为透光孔。当然，在一些实施例中，第一显示区A1也可以为除矩形之外的其他形状，如圆形。
可选的，该显示装置可以为：OLED显示装置、有源矩阵有机发光二极管(active-matrix organic light-emitting diode，AMOLED)显示装置、手机、平板电脑、柔性显示装置、电视机和显示器等任何具有显示功能的产品或部件。
本公开的实施方式部分使用的术语仅用于对本公开的实施例进行解释，而非旨在限定本公开。除非另作定义，本公开的实施方式使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。
本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”、“第三”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“上”、“下”、“左”、 “右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。
在本文中提及的“和/或”，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的显示基板和显示装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (25)

  1. 一种显示面板，所述显示面板包括：
    衬底基板，具有第一显示区、第二显示区和周边区，所述第二显示区至少部分围绕所述第一显示区，所述周边区至少部分围绕所述第二显示区；
    多个第一发光元件，位于所述第一显示区；
    多个第一像素电路，位于所述周边区；
    多个第二像素电路和多个第二发光元件，位于所述第二显示区，所述多个第二像素电路中的至少一个第二像素电路与所述多个第二发光元件中的至少一个第二发光元件耦接；
    至少一条第一连接走线，位于所述周边区、所述第二显示区和所述第一显示区，所述多个第一像素电路中的至少一个第一像素电路与所述多个第一发光元件中的至少一个第一发光元件通过所述第一连接走线耦接；
    至少一个补偿电容，位于所述周边区，所述补偿电容包括存在交叠的第一金属层和第二金属层，所述第一金属层与目标节点耦接，所述第二金属层与电源端耦接，所述目标节点为所述第一像素电路与所述第一连接走线耦接的节点。
  2. 根据权利要求1所述的显示面板，其中，各个所述第一像素电路对应的补偿电容的容值与所耦接的第一连接走线的长度负相关。
  3. 根据权利要求2所述的显示面板，其中，各个所述第一像素电路对应的补偿电容中，存在交叠的两个金属层的交叠面积与所耦接的第一连接走线的长度负相关。
  4. 根据权利要求1至3任一所述的显示面板，其中，所述显示面板包括：多个像素电路组，每个所述像素电路组包括：至少两个所述第一像素电路；
    其中，每个所述像素电路组对应的各个补偿电容的容值相同，且不同的所述像素电路组对应的补偿电容的容值不同。
  5. 根据权利要求4所述的显示面板，其中，所述多个像素电路组包括：沿像 素行方向依次间隔排布的第一子像素电路组、第二子像素电路组和第三子像素电路组；
    其中，所述第一子像素电路组对应的各个补偿电容的容值小于所述第二子像素电路组对应的各个补偿电容的容值，且所述第二子像素电路组对应的各个补偿电容的容值大于所述第三子像素电路组对应的各个补偿电容的容值。
  6. 根据权利要求1至5任一所述的显示面板，其中，所述周边区包括：沿像素列方向排布的第一区域和第二区域，且所述第二区域相对于所述第一区域靠近所述第二显示区；
    其中，各个所述第一像素电路位于所述第一区域，各个所述补偿电容位于所述第二区域。
  7. 根据权利要求1至6任一所述的显示面板，其中，所述显示面板包括多个所述补偿电容，各个所述补偿电容包括的第二金属层为一体结构，且各个所述补偿电容包括的第一金属层沿像素行方向间隔排布。
  8. 根据权利要求1至7任一所述的显示面板，其中，所述至少一个补偿电容包括多个第一组补偿电容，所述多个第一组补偿电容中的至少一个第一组补偿电容包括存在交叠的第三金属层和第四金属层，且所述第一金属层、所述第二金属层、所述第三金属层和所述第四金属层中，任意两个金属层位于异层；
    其中，所述第三金属层与所述目标节点耦接，所述第四金属层与所述电源端耦接。
  9. 根据权利要求8所述的显示面板，其中，所述至少一个补偿电容还包括：多个第二组补偿电容和多个第三组补偿电容；
    所述多个第一组补偿电容中的至少一个第一组补偿电容还包括存在交叠的第一金属层和第二金属层，所述多个第二组补偿电容中的至少一个第二组补偿电容还包括存在交叠的第一金属层和第二金属层，所述多个第三组补偿电容中的至少一个第三组补偿电容还包括存在交叠的第一金属层和第二金属层；
    其中，所述多个第一组补偿电容、所述多个第二组补偿电容和所述多个第 三组补偿电容沿像素行方向依次间隔排布，且第二组补偿电容包括的第一金属层沿像素列方向的高度，大于第三组补偿电容包括的第一金属层沿像素列方向的高度，且大于第二组补偿电容包括的第一金属层沿像素列方向的高度。
  10. 根据权利要求8所述的显示面板，其中，所述显示面板中的像素电路包括：沿远离所述衬底基板的方向依次排布的有源层，第一栅金属层，第二栅金属层，第一源漏金属层和第二源漏金属层；
    其中，所述第一金属层与所述第一栅金属层和所述第二栅金属层中的一个栅金属层位于同层，所述第二金属层与所述第一栅金属层和所述第二栅金属层中的另一个栅金属层位于同层；
    所述第三金属层与所述第一源漏金属层和所述第二源漏金属层中的一个源漏金属层位于同层，所述第四金属层与所述第一源漏金属层和所述第二源漏金属层中的另一个源漏金属层位于同层。
  11. 根据权利要求10所述的显示面板，其中，所述第一金属层与所述第一栅金属层位于同层，所述第二金属层与所述第二栅金属层位于同层。
  12. 根据权利要求10所述的显示面板，其中，所述第三金属层与所述第一源漏金属层位于同层，所述第四金属层与所述第二源漏金属层位于同层。
  13. 根据权利要求8至12任一所述的显示面板，其中，每个所述补偿电容均包括：存在交叠的所述第一金属层和所述第二金属层，以及存在交叠的所述第三金属层和所述第四金属层。
  14. 根据权利要求8至13任一所述的显示面板，其中，各个所述补偿电容包括的第四金属层为一体结构，且各个所述补偿电容包括的第三金属层沿像素行方向间隔排布。
  15. 根据权利要求8至14任一所述的显示面板，其中，所述第一金属层在所述衬底基板上的正投影，以及所述第三金属层在所述衬底基板上的正投影均呈 条状结构，且所述条状结构沿像素列方向延伸。
  16. 根据权利要求8至15任一所述的显示面板，其中，所述显示面板还包括：
    位于所述周边区的至少一条第二连接走线，所述第一金属层和所述第三金属层均通过所述第二连接走线与所述目标节点耦接。
  17. 根据权利要求16所述的显示面板，其中，所述周边区包括：沿像素列方向排布的第一区域、第三区域和第二区域，且所述第二区域相对于所述第一区域靠近所述第二显示区；所述第一金属层和所述第二连接走线通过第一过孔耦接，所述第三金属层和所述第一金属层通过第二过孔耦接；
    其中，所述第一过孔位于所述周边区的第三区域，所述第二过孔位于所述周边区的第一区域。
  18. 根据权利要求17所述的显示面板，其中，所述显示面板还包括：沿所述第一过孔远离所述衬底基板的方向依次排布的第一平坦层、第二平坦层和第三平坦层；
    其中，所述第一平坦层在所述衬底基板上的正投影覆盖所述第一过孔在所述衬底基板上的正投影，所述第二平坦层在所述衬底基板上的正投影覆盖所述第一过孔在所述衬底基板上的正投影，且所述第三平坦层在所述衬底基板上的正投影与所述第一过孔在所述衬底基板上的正投影不重叠。
  19. 根据权利要求18所述的显示面板，其中，所述第一平坦层、所述第二平坦层和所述第三平坦层均位于所述第二连接走线远离所述衬底基板的一侧。
  20. 根据权利要求16至19任一所述的显示面板，其中，所述第二连接走线与所述显示面板中像素电路包括的第二源漏金属层位于同层。
  21. 根据权利要求1至20任一所述的显示面板，其中，所述显示面板包括与所述至少一条第一连接走线一一对应的至少一个补偿电容；
    其中，每个所述补偿电容与对应的一条所述第一连接走线耦接于目标节点。
  22. 根据权利要求1至21任一所述的显示面板，其中，所述显示面板包括多条所述第一连接走线，且多条所述第一连接走线中至少两条第一连接走线位于异层。
  23. 根据权利要求22所述的显示面板，其中，所述多条第一连接走线包括至少一条位于同层的第一类第一连接走线，至少一条位于同层的第二类第一连接走线，以及至少一条位于同层的第三类第一连接走线；
    并且，所述第一类第一连接走线、所述第二类第一连接走线和所述第三类第一连接走线中，任意两类第一连接走线位于异层。
  24. 根据权利要求1至23任一所述的显示面板，其中，所述第一连接走线为透明导电线。
  25. 一种显示装置，其中，所述显示装置包括：感光传感器，以及如权利要求1至24任一所述的显示面板；
    其中，所述感光传感器位于所述显示面板的第一显示区内。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120026146A1 (en) * 2010-08-02 2012-02-02 Samsung Mobile Display Co., Ltd. Pixel and organic light emitting display device using the same
CN107481669A (zh) * 2017-09-08 2017-12-15 武汉天马微电子有限公司 一种显示面板及显示装置
CN107705756A (zh) * 2017-11-22 2018-02-16 武汉天马微电子有限公司 一种显示面板及显示装置
CN108538907A (zh) * 2018-06-28 2018-09-14 武汉天马微电子有限公司 有机发光显示面板和有机发光显示装置
CN108877622A (zh) * 2018-06-28 2018-11-23 武汉天马微电子有限公司 异形显示面板和显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070078522A (ko) * 2006-01-27 2007-08-01 삼성전자주식회사 표시 장치 및 액정 표시 장치
KR102438782B1 (ko) * 2015-11-26 2022-09-01 엘지디스플레이 주식회사 표시장치와 이의 제조방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120026146A1 (en) * 2010-08-02 2012-02-02 Samsung Mobile Display Co., Ltd. Pixel and organic light emitting display device using the same
CN107481669A (zh) * 2017-09-08 2017-12-15 武汉天马微电子有限公司 一种显示面板及显示装置
CN107705756A (zh) * 2017-11-22 2018-02-16 武汉天马微电子有限公司 一种显示面板及显示装置
CN108538907A (zh) * 2018-06-28 2018-09-14 武汉天马微电子有限公司 有机发光显示面板和有机发光显示装置
CN108877622A (zh) * 2018-06-28 2018-11-23 武汉天马微电子有限公司 异形显示面板和显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4202905A4 *

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