WO2021017094A1 - 一种阵列基板及 oled 显示装置 - Google Patents

一种阵列基板及 oled 显示装置 Download PDF

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Publication number
WO2021017094A1
WO2021017094A1 PCT/CN2019/103908 CN2019103908W WO2021017094A1 WO 2021017094 A1 WO2021017094 A1 WO 2021017094A1 CN 2019103908 W CN2019103908 W CN 2019103908W WO 2021017094 A1 WO2021017094 A1 WO 2021017094A1
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Prior art keywords
layer
metal layer
array substrate
signal line
insulating layer
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PCT/CN2019/103908
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English (en)
French (fr)
Inventor
徐品全
王威
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武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/619,480 priority Critical patent/US10916613B1/en
Publication of WO2021017094A1 publication Critical patent/WO2021017094A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate and an OLED display device.
  • OLED Organic Light Emitting Diode
  • OLED is a current-driven device, when current flows through the OLED, the OLED emits light, and the brightness of the light is determined by the current flowing through the OLED itself.
  • Most existing ICs Integrated Circuits, integrated circuits
  • the prior art OLED pixel drive circuit is usually 7T1C (7 transistors 1
  • the capacitance that is, the structure of seven thin film transistors plus a storage capacitor) circuit to convert voltage into current, and control the pixel circuit through the 7T1C circuit.
  • the array substrate includes a substrate substrate 111, a barrier layer (M/B) 112, a buffer layer (Buffer) 113, an active layer (Act) 114, a first gate insulating layer (GI1) 115, a First gate layer (GE1) 116, a second gate insulating layer (GI2) 117, a second gate layer (GE2) 118, a dielectric insulating layer (ILD) 119, a first source/drain layer (SD1) 120, a passivation layer (PV) 121, a first flat layer (PLN1) 122, a second source/drain layer (SD2) 123, and a second flat layer (PLN2) 124.
  • the display panel using the array substrate further includes: an anode (ANO) 125, a pixel defined layer (PDL) 126, and a photoresist layer (Photo Spacer, referred to as PS)127.
  • ANO anode
  • PDL pixel defined layer
  • PS photoresist layer
  • the active layer 114, the first gate layer 116, and the first source/drain electrode 120 are used to form the 7T1C circuit of the array substrate.
  • the first gate layer 116 is used as the bottom plate of the storage capacitor, and the second gate layer 118 is used as the top plate of the storage capacitor.
  • the first gate layer 116 and the second gate are directly used.
  • the second gate insulating layer 117 in the overlapping area of the layer 118 serves as the dielectric insulating layer of the storage capacitor, thereby forming the storage capacitor of the 7T1C circuit to drive the driver TFT of the 7T1C circuit.
  • An inorganic insulating layer is deposited on the second gate layer 118 as the dielectric insulating layer 119, and then a layer of the first source/drain layer 120 is deposited and patterned to form the source of the thin film transistor /Drain and data line; a layer of the first flat layer 122 is coated on the first source/drain layer 120, and then a layer of the second source/drain is deposited The electrode layer 123 is patterned to form a power signal line (Power Line); a layer of the second flat layer 124 is coated on the second source/drain layer 123, and then a layer of anode metal (PE) is deposited and performed The anode 125 is formed by patterning.
  • Power Line power signal line
  • PE anode metal
  • the existing array substrate has the problem of uneven display of the picture caused by IR drop (IR-Drop) when displaying in the display area (AA), and has the risk of manufacturing process.
  • IR-Drop IR drop
  • the purpose of this application is to provide an array substrate and an OLED display device for the problems existing in the prior art, which can reduce the IR voltage drop, improve the uniformity of the picture display, and can also reduce the coupling storage capacitance between the traces, and A larger storage capacitor can be formed.
  • the present application provides an array substrate including a plurality of sub-pixels, each of the sub-pixels includes a driving thin film transistor and a storage capacitor; the sub-pixels in two adjacent columns are arranged in a mirror symmetry structure;
  • the array substrate further includes: a first metal layer, the first metal layer constituting the gate electrode and the scan driving line of the driving thin film transistor; a second metal layer, the second metal layer constituting the driving thin film transistor The source/drain electrodes, the data signal line, the reset signal line, and the first plate of the storage capacitor, wherein the first metal layer and the second metal layer include an inorganic insulating layer and a layer Organic insulating layer; and a third metal layer, the third metal layer constitutes the power signal line and the second plate of the storage capacitor, wherein the second metal layer and the third metal layer include An inorganic insulating layer and an organic insulating layer.
  • the present application also provides an array substrate including a plurality of sub-pixels, each of the sub-pixels includes a driving thin film transistor and a storage capacitor; the array substrate further includes: a first metal layer, The first metal layer constitutes the gate electrode and scan driving line of the driving thin film transistor; a second metal layer constitutes the source/drain electrode, data signal line, and reset signal line of the driving thin film transistor And the first plate of the storage capacitor; and a third metal layer, the third metal layer constituting the power signal line and the second plate of the storage capacitor.
  • the present application also provides an OLED display device, the OLED display device includes an OLED display panel, the OLED display panel includes an array substrate, the array substrate includes a plurality of sub-pixels, each of the sub-pixels
  • the pixel includes a driving thin film transistor and a storage capacitor;
  • the array substrate further includes: a first metal layer, the first metal layer constituting the gate electrode and scan driving line of the driving thin film transistor; and a second metal layer,
  • the second metal layer constitutes the source/drain electrodes of the driving thin film transistor, the data signal line, the reset signal line, and the first plate of the storage capacitor; and a third metal layer, the third metal layer constitutes The power signal line and the second plate of the storage capacitor.
  • the metal wiring of the array substrate of this application adopts a three-layer metal structure design, which can facilitate the design of larger PPI circuits; by providing an inorganic insulating layer and an organic insulating layer between the two metal layers, two layers of wiring can be reduced The coupling effect between the storage capacitors; by exposing all or part of the organic insulating layer at the area where the second plate of the storage capacitor is formed, a larger storage capacitor can be formed; the third metal layer itself can form a mesh structure in the Reduce the IR pressure drop without increasing the mask and improve the uniformity of the picture display.
  • this application adopts a mirror symmetrical structure.
  • the reset signal line and the first via, the power signal line and the second via, and the reset signal line and the power signal line extend in the same direction, about half of the power supply can be saved.
  • the signal lines, reset signal lines and vias provide space for the improvement of PPI and facilitate the realization of high PPI panel design.
  • FIG. 1 is a schematic diagram of a layered structure of an existing array substrate
  • FIG. 2 is a schematic diagram of a layered structure of an embodiment of an array substrate of the present application.
  • FIG. 3 is a schematic diagram of a pixel structure of an embodiment of an array substrate of the present application.
  • the "on” or “under” of the first feature of the second feature may include the first and second features in direct contact, or may include the first and second features Not in direct contact but through other features between them.
  • “above”, “above” and “above” the second feature of the first feature include the first feature being directly above and obliquely above the second feature, or it simply means that the level of the first feature is higher than the second feature.
  • the “below”, “below” and “below” the first feature of the second feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • the array substrate of the present application includes a plurality of sub-pixels, each of the sub-pixels includes a driver TFT and a storage capacitor; the array substrate further includes: a first metal layer (GE1), the first The metal layer constitutes the gate electrode (Gate) and the scan line (Scan line) of the driving thin film transistor; a second metal layer (SD1), and the second metal layer constitutes the source/drain electrode ( S/D), a data signal line (Data line), a reset signal line (VI line, used to reset the storage capacitor and anode) and the first plate of the storage capacitor; a third metal layer (SD2), the The third metal layer constitutes a power signal line (Power (Vdd) Line or Power (VSS) Line) and the second plate of the storage capacitor.
  • the second metal layer and the third metal layer are used to make the two electrode plates of the storage capacitor, and only the gate electrode and the scan driving line for driving the thin film transistor are made on the first metal layer, which can facilitate the larger pixel density (Pixels Per Inch, PPI) circuit design.
  • an inorganic insulating layer and an organic insulating layer are included between the first metal layer and the second metal layer to reduce the coupling effect between the two layers of wiring.
  • an inorganic insulating layer and an organic insulating layer are included between the second metal layer and the third metal layer; more preferably, between the first plate and the second plate of the storage capacitor
  • the organic insulating layer is exposed through an exposure process, leaving only the inorganic insulating layer, so that a larger storage capacitor can be formed.
  • a halftone mask process can also be used to partially expose the organic insulating layer to achieve the purpose of reducing the thickness of the dielectric insulating layer corresponding to the storage capacitor area and increasing the storage capacitor, while ensuring the thickness of the organic insulating layer in other areas Not affected.
  • the third metal layer forms a mesh structure, and this structure design can reduce the IR pressure drop without adding a mask.
  • the sub-pixels in two adjacent columns are arranged in a mirror symmetrical structure.
  • the sub-pixels in two adjacent columns share one reset signal line and at least one first via, or share one power signal line and at least one second via.
  • the reset signal line and the power signal line extend in the same direction (that is, parallel).
  • the improved layout structure of the present application can save about half of the power signal lines, reset signal lines, and vias, thereby providing space for improvement of PPI and facilitating the realization of high PPI panel design.
  • the metal wiring adopts the GE1/SD1/SD2 three-layer structure design.
  • GE1 constitutes the gate electrode and scan driving line of the driving thin film transistor
  • SD1 constitutes the source/drain electrode, data signal line and reset signal line of the driving thin film transistor.
  • SD2 constitutes the power signal line and the second plate of the storage capacitor; at the same time, SD2 itself forms a mesh structure, which can facilitate the design of larger PPI circuits without adding a mask. Reduce IR pressure drop and improve the uniformity of screen display. By disposing an inorganic insulating layer and an organic insulating layer between the two metal layers, the coupling effect between the two layers of wiring can be reduced.
  • the organic insulating layer is fully or partially exposed to form a larger storage capacitor.
  • Mirror symmetrical structure is adopted.
  • the array substrate of the present application includes a plurality of sub-pixels, and each of the sub-pixels includes a driver TFT and a storage capacitor.
  • the array substrate of the present application also includes: a substrate substrate 211, a barrier layer (M/B) 212, a buffer layer (Buffer) 213, and an active layer (active layer) sequentially disposed on the substrate substrate 211 214, a first gate insulating layer (GI1) 215, a first metal layer (GE1) 216, a passivation layer (PV) 217, an organic dielectric insulating layer (OILD) 218, a second metal layer (SD1) ) 219, a second gate insulating layer (GI2) 220, a first flat layer (PLN1) 221, a third metal layer (SD2) 222, and a second flat layer (PLN2) 223.
  • the substrate substrate 211 may be a glass (Glass) substrate or an organic substrate made of a colorless and transparent polyimide (PI) material.
  • the first metal layer 216 constitutes a gate electrode (Gate) 2161 and a scan line (Scan line) 2162 of the driving thin film transistor.
  • the passivation layer 217 is an inorganic insulating layer covering the first metal layer 216; the organic dielectric insulating layer 218 is an organic insulating layer and is disposed on the passivation layer 217. That is, the first metal layer 216 and the second metal layer 219 include an inorganic insulating layer and an organic insulating layer, which can reduce the coupling effect between the two layers of wiring.
  • the second metal layer 219 constitutes a source/drain electrode (S/D) 2191 of the driving thin film transistor, a first reset signal line (VI line) 2192, a data signal line (Data line) 2193, and the The first plate 2194 of the storage capacitor.
  • the second gate insulating layer 220 is an inorganic insulating layer covering the second metal layer 219; the first flat layer 221 is an organic insulating layer and is disposed on the second gate insulating layer 220.
  • the third metal layer 222 constitutes a power signal line (Power (Vdd) Line or Power (VSS) Line) 2221 and the second plate 2222 of the storage capacitor.
  • the thickness of the first flat layer 221 can be reduced by an exposure process at the area where the second plate 2222 of the storage capacitor is formed, thereby reducing the thickness of the dielectric insulating layer of the storage capacitor, which can form a larger
  • the storage capacitor can ensure that the thickness of the organic insulating layer in other areas is not affected.
  • the second flat layer 223 (organic insulating layer) covers the third metal layer 222, and then an anode metal (PE) is deposited and patterned to form the anode 224.
  • PE anode metal
  • the second gate insulating layer 220 there is an inorganic insulating layer (the second gate insulating layer 220) and a layer between the data signal line 2193 on the second metal layer 219 and the power signal line 2221 on the third metal layer 222.
  • the organic insulating layer (the first flat layer 221) can reduce the coupling capacitance between the data signal line 2193 and the power signal line 2221.
  • the third metal layer 222 forms a mesh structure, and this structure design can reduce the IR voltage drop and improve the uniformity of the image display without increasing the mask.
  • the second metal layer 219 and the third metal layer 222 are used to fabricate the first plate and the second plate of the storage capacitor, respectively, and only the gate of the driving thin film transistor is formed on the first metal layer 216. Electrodes and scan driving lines can facilitate the design of larger PPI circuits. At the same time, an inorganic insulating layer and an organic insulating layer are included between the two metal layers, which can reduce the coupling effect between the two layers of wiring. The exposure process is used to reduce the thickness of the dielectric insulating layer in the storage capacitor area, thereby achieving the purpose of increasing the storage capacitor.
  • a groove 2211 is provided on the first flat layer 221 at a position corresponding to the first plate 2194 of the storage capacitor, and the second plate 2222 of the storage capacitor is formed on Inside the groove 2211. That is, the dielectric insulating layer of the storage capacitor is composed of the first flat layer 221 remaining under the trench 2211 (there may be no remaining) and the second gate insulating layer 220.
  • the depth of the trench 2211 can be adjusted by a partial exposure process of the first flat layer 221 through a halftone mask process. Therefore, the size of the storage capacitor can be adjusted by the overlapping area of the first electrode plate and the second electrode plate and the depth of the trench 2211.
  • the display panel using the array substrate of the present application is an OLED display panel, and the OLED display panel further includes a fourth metal layer 224 sequentially disposed on the second flat layer 223 of the array substrate.
  • An OLED light-emitting unit (not shown in the figure), a Pixel Defined Layer (PDL) 225, and a photoresist layer (Photo Spacer, PS) 226.
  • the fourth metal layer 224 constitutes an anode (ANO) 2241 and a second reset signal line 2242.
  • a plurality of through holes are formed on the second gate insulating layer 220 and the first flat layer 221, and the through holes are deposited with the third
  • the material of the metal layer 222 is the same metal material.
  • the anode 2241 is electrically connected to the source/drain electrode 2191 of the second metal layer 219 through a through hole; the second reset signal line 2242 is connected to the source/drain electrode 2191 through another through hole.
  • the first reset signal line 2192 of the second metal layer 219 is electrically connected.
  • the OLED display panel of the present application may also include other components, such as a cathode (Cathode) and a TFE encapsulation layer, etc., which will not be omitted here. Repeat.
  • CNT1 is the contact hole between the active layer and the second metal layer (Poly-SD1), namely the first via hole
  • CNT2 is the second metal layer and the second metal layer (Poly-SD1).
  • the contact hole of the three metal layer (SD1-SD2) is the second via hole
  • CNT3 is the contact hole of the third metal layer and the anode (SD2-PE), that is, the third via hole.
  • the array substrate includes a scan drive line (marked as scan in the figure), a light-emitting signal drive line (marked as EM in the figure) and a data signal line (marked as data in the figure), and the scan drive line (scan), light-emitting A pixel portion formed by a signal driving line (EM) and a data signal line (data) and a plurality of sub-pixels provided in the pixel portion.
  • the sub-pixel is a 7T1C circuit, including 7 thin film transistors (M1 to M7) and a storage capacitor (Cst), where the thin film transistor M1 is a driver TFT.
  • the sub-pixels in two adjacent columns are arranged in a mirror symmetrical structure.
  • the 7T1C of the sub-pixel n and the sub-pixel n+1 are mirror-symmetrical
  • the 7T1C of the sub-pixel n+1 and the sub-pixel n+2 are mirror-symmetrical.
  • the sub-pixels in two adjacent columns share a reset signal line (marked as VI in the figure) and the first via CNT1, or share a power signal line (marked as VDD in the figure) and the second Via CNT2.
  • the common reset signal line VI(n, n+1) and the first via CNT1 of the sub-pixel n and the sub-pixel n+1, the sub-pixel n+1 and the sub-pixel n+2 share the power supply signal line VDD(n+ 1, n+2) and the second via CNT2.
  • the improved layout structure of the present application can save about half of the power signal lines, reset signal lines, and vias, thereby providing space for improvement of PPI and facilitating the realization of high PPI panel design.
  • the application also provides an OLED display device, the OLED display device includes an OLED display panel, and the OLED display panel includes the above-mentioned array substrate of the application.
  • the metal wiring of the array substrate adopts the GE1/SD1/SD2 three-layer structure design.
  • GE1 constitutes the gate electrode and scan driving line of the driving thin film transistor
  • SD1 constitutes the source/drain electrode and data signal line of the driving thin film transistor.
  • the reset signal line and the first plate of the storage capacitor, SD2 constitutes the power signal line and the second plate of the storage capacitor; at the same time, SD2 itself forms a mesh structure, which facilitates the design of larger PPI circuits, and can be used without adding light In the case of the hood, the IR pressure drop is reduced, and the uniformity of the screen display is improved.
  • the subject of this application can be manufactured and used in industry and has industrial applicability.

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Abstract

一种阵列基板及OLED显示装置，阵列基板的金属走线采用三层金属结构（GE1/SD1/SD2）设计，通过在两层金属层之间设置一层无机绝缘层和一层有机绝缘层，可以减少两层走线之间的耦合效应；通过将形成存储电容的第二极板的区域处的有机绝缘层全部或部分曝光，可以形成较大存储电容；通过第三金属层（222）自身形成网状结构的构造，可以在不增加光罩的情况下降低IR压降，提高画面显示均匀度。

Description

一种阵列基板及OLED显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及OLED显示装置。
 背景技术
近年来OLED(Organic Light Emitting Diode，有机发光二极管)显示技术的快速发展，推动曲面和柔性显示产品迅速进入市场，相关领域技术更新也是日新月异。OLED是指利用有机半导体材料和发光材料在电场驱动下，通过载流子注入和复合导致发光的二极管。OLED显示装置由于重量轻、自发光、广视角、驱动电压低、发光效率高、功耗低、响应速度快等优点，应用范围越来越广泛。
OLED是电流驱动器件，当有电流流经时OLED发光，且发光亮度由流经OLED自身的电流决定。大部分已有的IC (Integrated Circuit，集成电路)都只传输电压信号，故OLED的像素驱动电路需要完成将电压信号转变为电流信号的任务。现有技术中的OLED像素驱动电路通常为7T1C(7 transistors 1 capacitance，即七个薄膜晶体管加一个存储电容的结构)电路，以将电压变换为电流，并通过7T1C电路进行像素电流(Pixel circuit)的控制。
 技术问题
参考图1，现有的阵列基板的层状结构示意图。所述阵列基板包括一基板衬底111，一阻挡层(M/B)112，一缓冲层(Buffer)113，一有源层(Act)114，一第一栅绝缘层(GI1)115，一第一栅极层(GE1)116，一第二栅绝缘层(GI2)117，一第二栅极层(GE2)118，一介电绝缘层(ILD)119，一第一源/漏极层(SD1)120，一钝化层(PV)121，一第一平坦层(PLN1)122，一第二源/漏极层(SD2)123，以及一第二平坦层(PLN2)124。采用所述阵列基板的显示面板还包括：依次设于所述第二平坦层124上的一阳极(ANO)125，一像素定义层(Pixel Defined Layer，简称PDL)126以及一光阻层 (Photo Spacer，简称PS)127。
由图1可以看出，在现有的阵列基板设计中，采用所述有源层114、所述第一栅极层116以及所述第一源/漏电极120构成所述阵列基板的7T1C电路的薄膜晶体管(TFT)。采用所述第一栅极层116作为存储电容的下极板、所述第二栅极层118作为存储电容的上极板，直接采用所述第一栅极层116与所述第二栅极层118重叠区域的所述第二栅绝缘层117作为存储电容的介电绝缘层，从而形成7T1C电路的存储电容，以进行7T1C电路的驱动薄膜晶体管(Driver TFT)的驱动。在所述第二栅极层118上方沉积的一层无机绝缘层作为所述介电绝缘层119，然后沉积一层所述第一源/漏极层120并图案化形成所述薄膜晶体管的源/漏极以及数据信号线(Data line)；在所述第一源/漏极层120上方涂布(coater)一层所述第一平坦层122，然后沉积一层所述第二源/漏极层123并图案化形成电源信号线(Power Line)；在所述第二源/漏极层123上方涂布一层所述第二平坦层124，然后沉积一层阳极金属(PE)并进行图案化形成所述阳极125。
现有的阵列基板在显示区(AA)显示时存在IR压降(IR-Drop)导致的画面显示不均问题，并存在制程风险。另外，现有的阵列基板，数据信号线与电源信号线之间会存在耦合(couple)电容，同时两栅极层重叠区域的绝缘层厚度受限，无法形成较大存储电容。
 技术解决方案
本申请的目的在于，针对现有技术存在的问题，提供一种阵列基板及OLED显示装置，可以降低IR压降，提高画面显示均匀度，还可以减小走线之间的耦合存储电容，并可以形成较大存储电容。
为实现上述目的，本申请提供了一种阵列基板，包括多个子像素，每一所述子像素包括一驱动薄膜晶体管以及一存储电容；相邻两列所述子像素采用镜像对称结构设置；所述阵列基板还包括：一第一金属层，所述第一金属层构成所述驱动薄膜晶体管的栅电极和扫描驱动线；一第二金属层，所述第二金属层构成所述驱动薄膜晶体管的源/漏电极、数据信号线、复位信号线以及所述存储电容的第一极板，其中，所述第一金属层与所述第二金属层之间包括一层无机绝缘层和一层有机绝缘层；以及一第三金属层，所述第三金属层构成电源信号线以及所述存储电容的第二极板，其中，所述第二金属层与所述第三金属层之间包括一层无机绝缘层和一层有机绝缘层。
为实现上述目的，本申请还提供了一种阵列基板，包括多个子像素，每一所述子像素包括一驱动薄膜晶体管以及一存储电容；所述阵列基板还包括：一第一金属层，所述第一金属层构成所述驱动薄膜晶体管的栅电极和扫描驱动线；一第二金属层，所述第二金属层构成所述驱动薄膜晶体管的源/漏电极、数据信号线、复位信号线以及所述存储电容的第一极板；以及一第三金属层，所述第三金属层构成电源信号线以及所述存储电容的第二极板。
为实现上述目的，本申请还提供了一种OLED显示装置，所述OLED显示装置包括OLED显示面板，所述OLED显示面板包括一阵列基板，所述阵列基板包括多个子像素，每一所述子像素包括一驱动薄膜晶体管以及一存储电容；所述阵列基板还包括：一第一金属层，所述第一金属层构成所述驱动薄膜晶体管的栅电极和扫描驱动线；一第二金属层，所述第二金属层构成所述驱动薄膜晶体管的源/漏电极、数据信号线、复位信号线以及所述存储电容的第一极板；以及一第三金属层，所述第三金属层构成电源信号线以及所述存储电容的第二极板。
 有益效果
本申请阵列基板的金属走线采用三层金属结构设计，可便于更大PPI电路设计；通过在两层金属层之间设置一层无机绝缘层和一层有机绝缘层，可以减少两层走线之间的耦合效应；通过将形成存储电容的第二极板的区域处的有机绝缘层全部或部分曝光，可以形成较大存储电容；通过第三金属层自身形成网状结构的构造，可以在不增加光罩的情况下降低IR压降，提高画面显示均匀度。同时，本申请采用镜像对称结构设置，通过共用复位信号线及第一过孔及电源信号线及第二过孔，以及复位信号线和电源信号线沿相同方向延伸，可以省去一半左右的电源信号线、复位信号线走线以及过孔，从而为PPI的提高提供了空间，利于实现高PPI面板设计。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为现有的阵列基板的层状结构示意图；
图2为本申请阵列基板一实施例的层状结构示意图；
图3为本申请阵列基板一实施例的像素结构示意图。
 本发明的实施方式
下面详细描述本申请的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本申请阵列基板，包括多个子像素，每一所述子像素包括一驱动薄膜晶体管(Driver TFT)以及一存储电容；所述阵列基板还包括：一第一金属层(GE1)，所述第一金属层构成所述驱动薄膜晶体管的栅电极(Gate)和扫描驱动线(Scan line)；一第二金属层(SD1)，所述第二金属层构成所述驱动薄膜晶体管的源/漏电极(S/D)、数据信号线(Data line)、复位信号线(VI line，用于复位存储电容和阳极)以及所述存储电容的第一极板；一第三金属层(SD2)，所述第三金属层构成电源信号线(Power(Vdd) Line或 Power(VSS) Line)以及所述存储电容的第二极板。采用第二金属层与第三金属层制作存储电容的两极板，第一金属层上只制作驱动薄膜晶体管的栅电极以及扫描驱动线，可便于更大像素密度(Pixels Per Inch ，简称PPI)电路设计。
优选的，所述第一金属层与所述第二金属层之间包括一层无机绝缘层和一层有机绝缘层，以减少两层走线之间的耦合效应。
优选的，所述第二金属层与所述第三金属层之间包括一层无机绝缘层和一层有机绝缘层；更优选的，所述存储电容的第一极板与第二极板之间仅设有一层所述无机绝缘层作为所述存储电容的介电层。在第二金属层上的数据信号线上方存在两层绝缘层(一层无机绝缘层和一层有机绝缘层)，以减小数据信号线与电源信号线的耦合电容。而在形成存储电容的第二极板的区域处，通过曝光制程曝光有机绝缘层，只留下无机绝缘层，从而可以形成较大存储电容。也可以采用半色调(halftone)掩膜工艺对有机绝缘层进行部分曝光制程，达到存储电容区域对应的介电绝缘层厚度减薄、存储电容增大的目的，同时可保证其它区域有机绝缘层厚度不受影响。
优选的，所述第三金属层形成网状(Mesh)结构，此种结构设计在不增加光罩的情况下可以降低IR压降。
优选的，相邻两列所述子像素采用镜像(Mirror)对称结构设置。优选的，相邻两列所述子像素共用一条复位信号线及至少一第一过孔，或共用一条电源信号线及至少一第二过孔。优选的，所述复位信号线和所述电源信号线沿相同方向延伸(即平行)。相对于现有的7T1C布局结构，本申请改进的布局结构可以省去一半左右的电源信号线、复位信号线走线以及过孔，从而为PPI的提高提供了空间，利于实现高PPI面板设计。
本申请阵列基板，金属走线采用GE1/SD1/SD2三层结构设计，GE1构成驱动薄膜晶体管的栅电极以及扫描驱动线，SD1构成驱动薄膜晶体管的源/漏电极、数据信号线、复位信号线以及存储电容的第一极板，SD2构成电源信号线以及存储电容的第二极板；同时SD2自身形成网状结构的构造，可便于更大PPI电路设计，可以在不增加光罩的情况下降低IR压降，提高画面显示均匀度。通过在两层金属层之间设置一层无机绝缘层和一层有机绝缘层，可以减少两层走线之间的耦合效应。而在形成存储电容的第二极板的区域处，有机绝缘层被全部或部分曝光，可以形成较大存储电容。采用镜像对称结构设置，通过共用复位信号线及第一过孔及电源信号线及第二过孔，以及复位信号线和电源信号线沿相同方向延伸，可以省去一半左右的电源信号线、复位信号线走线以及过孔，从而为PPI的提高提供了空间，利于实现高PPI面板设计。
参考图2，本申请阵列基板一实施例的层状结构示意图。本申请阵列基板包括多个子像素，每一所述子像素包括一驱动薄膜晶体管(Driver TFT)以及一存储电容。本申请阵列基板还包括：一基板衬底211，依次设于所述基板衬底211上的一阻挡层(M/B)212、一缓冲层(Buffer)213、一有源层(active layer)214、一第一栅绝缘层(GI1)215、一第一金属层(GE1)216、一钝化层(PV)217、一有机介电绝缘层(OILD)218、一第二金属层(SD1)219、一第二栅绝缘层(GI2)220、一第一平坦层(PLN1)221、一第三金属层(SD2)222以及一第二平坦层(PLN2)223。所述基板衬底211可以采用玻璃(Glass)基板或采用无色透明聚酰亚胺(PI)材料制备的有机基板。
具体的，所述第一金属层216构成所述驱动薄膜晶体管的栅电极(Gate)2161和扫描驱动线(Scan line)2162。所述钝化层217为无机绝缘层，覆盖所述第一金属层216；所述有机介电绝缘层218为有机绝缘层，设于所述钝化层217上。也即，所述第一金属层216与所述第二金属层219之间包括一层无机绝缘层和一层有机绝缘层，可以减少两层走线之间的耦合效应。
具体的，所述第二金属层219构成所述驱动薄膜晶体管的源/漏电极(S/D)2191、第一复位信号线(VI line)2192、数据信号线(Data line)2193以及所述存储电容的第一极板2194。所述第二栅绝缘层220为无机绝缘层，覆盖所述第二金属层219；所述第一平坦层221为有机绝缘层，设于所述第二栅绝缘层220上。
具体的，所述第三金属层222构成电源信号线(Power(Vdd) Line或 Power(VSS) Line)2221以及所述存储电容的第二极板2222。可以在形成所述存储电容的第二极板2222的区域处，通过曝光制程减薄所述第一平坦层221厚度，从而减薄所述存储电容的介电绝缘层的厚度，可以形成较大存储电容，同时可保证其它区域有机绝缘层厚度不受影响。所述第二平坦层223(有机绝缘层)覆盖所述第三金属层222，之后沉积阳极金属(PE)并进行图案化，形成所述阳极224。也即，在第二金属层219上的数据信号线2193与所述第三金属层222上的电源信号线2221之间存在一层无机绝缘层(所述第二栅绝缘层220)和一层有机绝缘层(所述第一平坦层221)，可以减小所述数据信号线2193与所述电源信号线2221的耦合电容。优选的，所述第三金属层222形成网状(Mesh)结构，此种结构设计在不增加光罩的情况下可以降低IR压降，提高画面显示均匀度。
采用所述第二金属层219与所述第三金属层222分别制作所述存储电容的第一极板、第二极板，所述第一金属层216上只制作所述驱动薄膜晶体管的栅电极以及扫描驱动线，可便于更大PPI电路设计。同时，两层金属层之间包括一层无机绝缘层和一层有机绝缘层，可以减少两层走线之间的耦合效应。而采用曝光制程减薄存储电容区域介电绝缘层厚度减薄，达到存储电容增大的目的。
优选的，在本实施例中，所述第一平坦层221上与所述存储电容的第一极板2194对应的位置处设有一沟槽2211，所述存储电容的第二极板2222形成于所述沟槽2211内。也即，所述存储电容的介电绝缘层由沟槽2211下方剩余的第一平坦层221(也可以没有剩余)和第二栅绝缘层220组成。所述沟槽2211深度可以通过半色调(halftone)掩膜工艺对第一平坦层221进行部分曝光制程进行调整。从而，所述存储电容的大小可以通过第一极板、第二极板重叠区域面积及沟槽2211的深度进行调整。
在本实施例中，采用本申请阵列基板的显示面板为OLED显示面板，所述OLED显示面板还包括依次设于所述阵列基板的所述第二平坦层223上的一第四金属层224，一OLED发光单元(未示于图中)及一像素定义层(Pixel Defined Layer，简称PDL)225，以及一光阻层((Photo Spacer，简称PS)226。具体的，所述第四金属层224构成一阳极(ANO)2241以及第二复位信号线2242。所述第二栅绝缘层220与所述第一平坦层221上形成有多个通孔，通孔内沉积有与所述第三金属层222的材料相同的金属材料。所述阳极2241通过一通孔与所述第二金属层219的所述源/漏电极2191电连接；所述第二复位信号线2242通过另一通孔与所述第二金属层219的所述第一复位信号线2192电连接。需要说明的是，本申请OLED显示面板还可以包括其它组件，例如，阴极(Cathode)以及TFE封装层等，在此不再赘述。
参考图3，本申请阵列基板一实施例的像素结构示意图，图中CNT1为有源层与第二金属层(Poly-SD1)的接触孔即第一过孔，CNT2为第二金属层与第三金属层(SD1-SD2)的接触孔即第二过孔，CNT3为第三金属层与阳极(SD2-PE)的接触孔即第三过孔。所述阵列基板包括扫描驱动线(图中标记为scan)、发光信号驱动线(图中标记为EM)与数据信号线(图中标记为data)，由所述扫描驱动线(scan)、发光信号驱动线(EM)与数据信号线(data)形成的像素部分以及设置在所述像素部分中的多个子像素。所述子像素为7T1C电路，包括7个薄膜晶体管(M1~ M7)以及1个存储电容(Cst)，其中薄膜晶体管M1为驱动薄膜晶体管(Driver TFT)。
由图3可以看出，相邻两列所述子像素采用镜像(Mirror)对称结构设置。如图3中子像素n和子像素n+1的7T1C呈镜像对称，子像素n+1和子像素n+2的7T1C呈镜像对称。
由图3可以看出，相邻两列所述子像素共用一条复位信号线(图中标记为VI)及第一过孔CNT1，或共用一条电源信号线(图中标记为VDD)及第二过孔CNT2。如图3中子像素n和子像素n+1的共用复位信号线VI(n, n+1)和第一过孔CNT1，子像素n+1和子像素n+2共用电源信号线VDD(n+1, n+2)和第二过孔CNT2。
由图3可以看出，复位信号线(VI)和电源信号线(VDD)沿相同方向延伸(即平行)。
相对于现有的7T1C布局结构，本申请改进的布局结构可以省去一半左右的电源信号线、复位信号线走线以及过孔，从而为PPI的提高提供了空间，利于实现高PPI面板设计。
基于同一申请构思，本申请还提供了一种OLED显示装置，所述OLED显示装置包括OLED显示面板，所述OLED显示面板包括本申请上述的阵列基板。
本申请OLED显示装置，阵列基板的金属走线采用GE1/SD1/SD2三层结构设计，GE1构成驱动薄膜晶体管的栅电极以及扫描驱动线，SD1构成驱动薄膜晶体管的源/漏电极、数据信号线、复位信号线以及存储电容的第一极板，SD2构成电源信号线以及存储电容的第二极板；同时SD2自身形成网状结构的构造，可便于更大PPI电路设计，可以在不增加光罩的情况下降低IR压降，提高画面显示均匀度。通过在两层金属层之间设置一层无机绝缘层和一层有机绝缘层，可以减少两层走线之间的耦合效应。而在形成存储电容的第二极板的区域处，有机绝缘层全部或部分曝光，可以形成较大存储电容。采用镜像对称结构设置，通过共用复位信号线及第一过孔及电源信号线及第二过孔，以及复位信号线和电源信号线沿相同方向延伸，可以省去一半左右的电源信号线、复位信号线走线以及过孔，从而为PPI的提高提供了空间，利于实现高PPI面板设计。
 工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (20)

  1. 一种阵列基板，包括多个子像素，每一所述子像素包括一驱动薄膜晶体管以及一存储电容；其中，相邻两列所述子像素采用镜像对称结构设置；所述阵列基板还包括：一第一金属层，所述第一金属层构成所述驱动薄膜晶体管的栅电极和扫描驱动线；一第二金属层，所述第二金属层构成所述驱动薄膜晶体管的源/漏电极、数据信号线、复位信号线以及所述存储电容的第一极板，并且其中，所述第一金属层与所述第二金属层之间包括一层无机绝缘层和一层有机绝缘层；以及一第三金属层，所述第三金属层构成电源信号线以及所述存储电容的第二极板，并且其中，所述第二金属层与所述第三金属层之间包括一层无机绝缘层和一层有机绝缘层。
  2. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括：一基板衬底；依次设于所述基板衬底上的一阻挡层、一缓冲层、一有源层、一第一栅绝缘层和所述第一金属层；依次设于所述第一金属层上的一钝化层、一有机介电绝缘层和所述第二金属层；依次设于所述第二金属层上的一第二栅绝缘层、一第一平坦层和所述第三金属层；以及覆盖所述第三金属层的一第二平坦层。
  3. 如权利要求2所述的阵列基板，其中，所述第一平坦层与所述存储电容的第一极板对应的位置处设有一沟槽，所述存储电容的第二极板形成于所述沟槽内。
  4. 如权利要求1所述的阵列基板，其中，相邻两列所述子像素共用一条复位信号线及至少一第一过孔，或共用一条电源信号线及至少一第二过孔。
  5. 如权利要求1所述的阵列基板，其中，所述复位信号线和所述电源信号线沿相同方向延伸。
  6. 一种阵列基板，包括多个子像素，每一所述子像素包括一驱动薄膜晶体管以及一存储电容；其中，所述阵列基板还包括：一第一金属层，所述第一金属层构成所述驱动薄膜晶体管的栅电极和扫描驱动线；一第二金属层，所述第二金属层构成所述驱动薄膜晶体管的源/漏电极、数据信号线、复位信号线以及所述存储电容的第一极板；以及一第三金属层，所述第三金属层构成电源信号线以及所述存储电容的第二极板。
  7. 如权利要求6所述的阵列基板，其中，所述第一金属层与所述第二金属层之间包括一层无机绝缘层和一层有机绝缘层。
  8. 如权利要求6所述的阵列基板，其中，所述第二金属层与所述第三金属层之间包括一层无机绝缘层和一层有机绝缘层，所述存储电容的第一极板与第二极板之间仅设有一层所述无机绝缘层。
  9. 如权利要求6所述的阵列基板，其中，所述第三金属层形成网状结构。
  10. 如权利要求6所述的阵列基板，其中，所述阵列基板还包括：一基板衬底；依次设于所述基板衬底上的一阻挡层、一缓冲层、一有源层、一第一栅绝缘层和所述第一金属层；依次设于所述第一金属层上的一钝化层、一有机介电绝缘层和所述第二金属层；依次设于所述第二金属层上的一第二栅绝缘层、一第一平坦层和所述第三金属层；以及覆盖所述第三金属层的一第二平坦层。
  11. 如权利要求10所述的阵列基板，其中，所述第一平坦层与所述存储电容的第一极板对应的位置处设有一沟槽，所述存储电容的第二极板形成于所述沟槽内。
  12. 如权利要求6所述的阵列基板，其中，相邻两列所述子像素采用镜像对称结构设置。
  13. 如权利要求6所述的阵列基板，其中，相邻两列所述子像素共用一条复位信号线及至少一第一过孔，或共用一条电源信号线及至少一第二过孔。
  14. 如权利要求6所述的阵列基板，其中，所述复位信号线和所述电源信号线沿相同方向延伸。
  15. 一种OLED显示装置，其中，所述OLED显示装置包括OLED显示面板，所述OLED显示面板包括一阵列基板，所述阵列基板包括多个子像素，每一所述子像素包括一驱动薄膜晶体管以及一存储电容；所述阵列基板还包括：一第一金属层，所述第一金属层构成所述驱动薄膜晶体管的栅电极和扫描驱动线；一第二金属层，所述第二金属层构成所述驱动薄膜晶体管的源/漏电极、数据信号线、复位信号线以及所述存储电容的第一极板；以及一第三金属层，所述第三金属层构成电源信号线以及所述存储电容的第二极板。
  16. 如权利要求15所述的OLED显示装置，其中，所述第一金属层与所述第二金属层之间包括一层无机绝缘层和一层有机绝缘层。
  17. 如权利要求15所述的OLED显示装置，其中，所述第二金属层与所述第三金属层之间包括一层无机绝缘层和一层有机绝缘层，所述存储电容的第一极板与第二极板之间仅设有一层所述无机绝缘层。
  18. 如权利要求15所述的OLED显示装置，其中，所述阵列基板还包括：一基板衬底；依次设于所述基板衬底上的一阻挡层、一缓冲层、一有源层、一第一栅绝缘层和所述第一金属层；依次设于所述第一金属层上的一钝化层、一有机介电绝缘层和所述第二金属层；依次设于所述第二金属层上的一第二栅绝缘层、一第一平坦层和所述第三金属层；以及覆盖所述第三金属层的一第二平坦层。
  19. 如权利要求18所述的OLED显示装置，其中，所述第一平坦层与所述存储电容的第一极板对应的位置处设有一沟槽，所述存储电容的第二极板形成于所述沟槽内。
  20. 如权利要求18所述的OLED显示装置，其中，相邻两列所述子像素采用镜像对称结构设置。
PCT/CN2019/103908 2019-07-26 2019-09-02 一种阵列基板及 oled 显示装置 WO2021017094A1 (zh)

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