WO2022213587A1 - 一种高线性度的相位插值电路 - Google Patents

一种高线性度的相位插值电路 Download PDF

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Publication number
WO2022213587A1
WO2022213587A1 PCT/CN2021/128288 CN2021128288W WO2022213587A1 WO 2022213587 A1 WO2022213587 A1 WO 2022213587A1 CN 2021128288 W CN2021128288 W CN 2021128288W WO 2022213587 A1 WO2022213587 A1 WO 2022213587A1
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Prior art keywords
phase interpolation
nmos transistor
circuit
output
drain
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PCT/CN2021/128288
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English (en)
French (fr)
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马锡昆
谢宜政
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无锡中微亿芯有限公司
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Priority to US17/643,840 priority Critical patent/US11791827B2/en
Publication of WO2022213587A1 publication Critical patent/WO2022213587A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals

Definitions

  • the invention relates to the field of phase interpolation circuits, in particular to a phase interpolation circuit with high linearity.
  • timing margin In the high-speed interface chip, when data is input, a clock at the center of the data is required to sample it, so as to perform subsequent data processing. With the different working conditions, the location of the data center is also changing, which requires that the phase of the sampling clock can have a corresponding adjustment range, or the clock needs to achieve fine phase adjustment, so as to obtain more timing margin for the system ( timing margin).
  • Phase Interpolation is a common technology to achieve fine phase adjustment.
  • DDR phase Interpolation
  • it When applied to parallel interfaces such as DDR, it often cooperates with DLL to perform phase interpolation on adjacent phase clocks generated by DLL to obtain more refined polyphase. clock output.
  • DDR clock data recovery block
  • CDR clock data recovery block
  • DLL/PLL often completes coarse phase adjustment, such as outputting 0°, 45°, 90°, 135°, 180°, 225°, 270°, 315° phase clock, while PI completes fine phase adjustment, such as PI according to the input
  • PI completes fine phase adjustment, such as PI according to the input
  • the 225° and 270° clocks generate additional 5-phase clocks between 225° and 270°, thereby improving the phase adjustment accuracy.
  • the principle of phase interpolation can also be used.
  • phase interpolation circuits are shown in Figure 1.
  • IN1 and IN2 are the input two-phase clocks
  • PI_CELL is the basic interpolation circuit.
  • N is the length of the phase interpolation, which determines the number of phases to be output.
  • S1 ⁇ SN and G1 ⁇ GN are switches, which control the weights of IN1 and IN2, thereby determining whether the phase of the output OUT is close to IN1 or IN2.
  • the capacitors C0/C1/C2 are used to adjust the slew rate of the input signal, so that IN1/IN2 is The relationship of overlapping clocks, so as to output smoothly.
  • Linearity is an important indicator of phase interpolation, which determines the minimum adjustment accuracy. Due to the nonlinear behavior of the MOS tube, the output phase of the phase interpolation circuit shown in Figure 1 cannot show a uniform distribution, as shown in Figure 2, D1, D2 , D3, and D4 are not exactly equal. In order to improve the adjustment accuracy, the current common practice is to increase the length N of phase interpolation to compensate for the lack of linearity, but this method will sacrifice chip area and power consumption.
  • phase interpolation circuit In order to improve the adjustment accuracy of the existing phase interpolation circuit, a common practice is to increase the length N of the phase interpolation to compensate for the lack of linearity, but this method will sacrifice chip area and power consumption.
  • phase interpolation circuit with high linearity includes:
  • a first parallel circuit composed of M phase interpolation units and a second parallel circuit composed of N phase interpolation units the input terminal of the first parallel circuit is connected to the first clock input terminal and grounded through the first capacitor, and the output of the first parallel circuit The terminal is connected to the clock output terminal, the input terminal of the second parallel circuit is connected to the second clock input terminal and is grounded through the second capacitor, the output terminal of the second parallel circuit is connected to the clock output terminal, and the clock output terminal is also grounded through the zeroth capacitor;
  • the clock output terminal outputs several output clock signals with different phases
  • the circuit parameters of each phase interpolation unit correspond to their respective target output weights, and the target output weights of each phase interpolation unit are determined by iteration to minimize the output delay difference of the phase interpolation circuit.
  • the output delay difference indicates that the phase interpolation circuit passes The phase difference between all output clock signals with different phases output by the clock output terminal.
  • a further technical solution is that the target output weights of each phase interpolation unit with the smallest output delay difference of the phase interpolation circuit form a target weight combination of the phase interpolation circuit, and the phase interpolation circuit corresponds to at least two different target weight combinations.
  • the output delay difference degree is determined by at least one of the variance, standard deviation and typical value difference of the phase delay between the output clock signals, and the typical value difference is the difference between the two typical values.
  • the typical value is any one of the extreme value, average value and median value in the phase delay.
  • a further technical solution is that a control switch is connected in series on the branch where each phase interpolation unit is located, or a control switch is connected in series on the branch where some phase interpolation units are located; each control switch is controlled by an independent control signal, or there are at least two control switches. Each control switch is controlled by the same control signal.
  • each phase interpolation unit is respectively connected with a control switch in series
  • each branch in the first parallel circuit and each branch in the second parallel circuit are in one-to-one correspondence
  • the two control switches on the two branches with the corresponding relationship are simultaneously controlled by the signal itself of the same control signal and its inverse signal, and the states are opposite.
  • each phase interpolation unit includes a basic interpolation circuit and a weight adjustment circuit, the basic interpolation circuits in all phase interpolation units are the same, and the circuit parameters of the weight adjustment circuits in different phase interpolation units correspond to the phase.
  • the target output weight of the interpolation unit is that each phase interpolation unit includes a basic interpolation circuit and a weight adjustment circuit, the basic interpolation circuits in all phase interpolation units are the same, and the circuit parameters of the weight adjustment circuits in different phase interpolation units correspond to the phase.
  • the basic interpolation circuit includes a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, and the source of the first PMOS tube is connected to the power supply terminal, and the drain is connected to the second PMOS tube.
  • the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and serves as the output terminal of the phase interpolation unit
  • the source of the second NMOS transistor is connected to the drain of the first NMOS transistor
  • the The source is connected to the ground terminal
  • the gate of the first PMOS transistor and the gate of the first NMOS transistor are both connected to the input terminal of the phase interpolation unit
  • the gate of the second NMOS transistor is connected to the first switch signal
  • the gate of the second PMOS transistor A second switch signal is connected, and the first switch signal and the second switch signal are a pair of signals with opposite polarities;
  • the weight adjustment circuit is connected to the source of the second PMOS transistor and the source of the second NMOS transistor.
  • the drain of the first PMOS transistor is directly connected to the source of the second PMOS transistor, and the source of the second NMOS transistor is directly connected to the drain of the first NMOS transistor;
  • the weight adjustment circuit includes a third PMOS tube and a third NMOS tube, the source of the third PMOS tube is connected to the power supply terminal, the drain is connected to the common terminal of the first PMOS tube and the second PMOS tube, and the source of the third NMOS tube is grounded The drain is connected to the common terminal of the first NMOS transistor and the second NMOS transistor, and the gate of the third PMOS transistor and the gate of the third NMOS transistor are both connected to the input end of the phase interpolation unit.
  • the weight adjustment circuit includes a fourth PMOS transistor and a fourth NMOS transistor.
  • the drain of the first PMOS transistor is connected to the source of the second PMOS transistor through the fourth PMOS transistor, and the second PMOS transistor is connected to the source of the second PMOS transistor.
  • the source of the NMOS transistor is connected to the drain of the first NMOS transistor through the fourth NMOS transistor: the source of the fourth PMOS transistor is connected to the drain of the first PMOS transistor, the drain is connected to the source of the second PMOS transistor, and the gate is connected to ground The source of the fourth NMOS transistor is connected to the drain of the first NMOS transistor, the drain is connected to the source of the second NMOS transistor, and the gate is connected to the power supply terminal.
  • phase interpolation unit adopts a differential transmission mode
  • the input end of the phase interpolation unit includes a first differential input end and a second differential input end
  • the output end of the phase interpolation unit includes a first differential output end and a second differential input end.
  • the basic interpolation circuit includes a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube.
  • the source of the fifth NMOS tube is connected to the ground terminal, and the drain is connected to the source of the sixth NMOS tube and the source of the seventh NMOS tube.
  • the gate of the fifth NMOS transistor is connected to the bias voltage, the drain of the sixth NMOS transistor and the drain of the seventh NMOS transistor are connected to the power supply terminal through the load circuit, the gate of the sixth NMOS transistor is connected to the first differential input terminal, and the seventh NMOS transistor is connected to the first differential input terminal.
  • the gate of the tube is connected to the second differential input terminal, the drain of the seventh NMOS tube is used as the first differential output terminal, and the drain of the sixth NMOS tube is used as the second differential output terminal;
  • the weight adjustment circuit includes an eighth NMOS transistor and a ninth NMOS transistor.
  • the source of the eighth NMOS transistor is connected to the source of the second NMOS transistor, the drain is connected to the drain of the second NMOS transistor, and the gate is connected to the first differential input terminal.
  • the source of the ninth NMOS transistor is connected to the source of the seventh NMOS transistor, the drain is connected to the drain of the seventh NMOS transistor, and the gate is connected to the second differential input terminal.
  • the present application discloses a phase interpolation circuit with high linearity.
  • the phase interpolation circuit adds nonlinearity through the circuit parameters of the phase interpolation unit on each phase interpolation branch to compensate the nonlinearity existing in the MOS tube itself.
  • the target output weight of the interpolation branch can effectively improve the linearity of the phase interpolation circuit, and the implementation method is simple, which avoids the difficulty of implementing complex compensation techniques, does not need to increase the length of phase interpolation, and does not sacrifice area and power consumption.
  • the weight adjustment circuit can be embedded in the existing basic interpolation circuit to form the phase interpolation unit of the present application, which is beneficial to layout implementation.
  • FIG. 1 is a circuit configuration diagram of a conventional phase interpolation circuit.
  • FIG. 2 is a schematic diagram of an output clock signal of the phase interpolation circuit of FIG. 1 .
  • FIG. 3 is a circuit configuration diagram of the phase interpolation circuit of the present application.
  • FIG. 4 is a circuit diagram of an implementation of the phase interpolation unit in the present application.
  • FIG. 5 is another implementation circuit diagram of the phase interpolation unit in the present application.
  • FIG. 6 is another implementation circuit diagram of the phase interpolation unit in the present application.
  • the present application discloses a phase interpolation circuit with high linearity.
  • the phase interpolation circuit includes a first parallel circuit composed of M phase interpolation units and a second parallel circuit composed of N phase interpolation units.
  • the input of each phase interpolation unit is The terminal in is connected to the input terminal of the parallel circuit, and the output terminal is connected to the output terminal of the parallel circuit.
  • the input terminal of the first parallel circuit is connected to the first clock input terminal IN1 and grounded through the first capacitor C1 , and the output terminal of the first parallel circuit is connected to the clock output terminal OUT.
  • the input end of the second parallel circuit is connected to the second clock input end IN2 and grounded through the second capacitor C2, the output end of the second parallel circuit is connected to the clock output end OUT, and the clock output end OUT is also grounded through the zeroth capacitor C0, and the capacitor C0/ C1/C2 are used to adjust the slew rate of the input signal.
  • the clock output terminal OUT can output several output clock signals with different phases.
  • the on-off of the branch is controlled by controlling the on-off of the control switch connected in series with the phase interpolation unit.
  • a control switch is connected in series on the branch where each phase interpolation unit is located, so that each phase interpolation The branch where the unit is located can be individually controlled on/off, or, a control switch is connected in series on the branch where some phase interpolation units are located, so that the branch with the control switch can be controlled on/off, and the remaining branches are turned on by default.
  • each control switch is controlled by an independent control signal, or at least two control switches are controlled by the same control signal, including directly using the same control signal to control multiple control switches or using the same control signal. and its inverse signal to control multiple control switches.
  • each phase interpolation unit is connected in series with a control switch, that is, a symmetrical structure as shown in Figure 3 is formed.
  • each control switch can be independently controlled by its own control signal, but more commonly, each branch in the first parallel circuit is in a one-to-one correspondence with each branch in the second parallel circuit , and the two control switches on the two branches with a corresponding relationship are simultaneously controlled by the signal itself of the same control signal and its inverse signal, and the states are opposite.
  • the present application adjusts and redesigns each phase interpolation unit in the phase interpolation circuit.
  • the circuit parameters of each phase interpolation unit correspond to the respective target output weights.
  • the target output weights corresponding to the phase interpolation unit CELL1 are all T1_1, then the phase interpolation unit is represented as CELL1 (T1_1) in the figure, and the target output weights corresponding to the phase interpolation unit CELL2 are T2_1.
  • the interpolation unit is denoted as CELL2 (T2_1), and so on.
  • phase interpolation unit Different circuit parameters of the phase interpolation unit can be realized by different sizes of internal devices, and the target output weights corresponding to different phase interpolation units are the same or different. More specifically, if a symmetrical structure and control method are adopted, the two phase interpolation units on the same link can be set to the same target output weight, for example, T1_1 and T2_1 are equal.
  • the target output weight of each phase interpolation unit is determined iteratively and makes the output delay difference minimum, and the output delay difference represents the phase difference between all the output clock signals with different phases output by the phase interpolation circuit through the clock output terminal OUT. .
  • the output delay difference degree represents the difference degree among D1 , D2 , D3 and D4 . The smaller the output delay difference, the better the linearity of the phase interpolation circuit.
  • 1 and 0 indicate the state of S1 ⁇ S4, 1 indicates that the switch is closed, 0 indicates that the switch is open, 1111 indicates that S4 ⁇ S1 are closed, 1110 indicates that S4 ⁇ S2 are closed, S1 is open, and so on, and G4 ⁇ The corresponding positions of G1 and S4 ⁇ S1 are inverted.
  • the output weight of the phase interpolation unit completes the traversal adjustment of the ith phase interpolation unit, and determines the output delay difference corresponding to each adjustment. In this way, the traversal adjustment of each phase interpolation unit is completed in sequence, and the output weight of each phase interpolation unit when the corresponding output delay difference is the smallest is taken as the target output weight of each phase interpolation unit.
  • the predetermined range of the output weight of the phase interpolation unit during adjustment is usually determined by the range of circuit parameters achievable by the circuit structure, which can be considered as a predetermined range.
  • the output weight of any one of the phase interpolation units can be selected for adjustment each time.
  • the final target output weight of each phase interpolation unit may be different. Therefore, in this application, if the target output weights of each phase interpolation unit with the smallest output delay difference are defined to constitute a target weight combination of the phase interpolation circuit, the phase interpolation unit corresponds to at least two different target weight combinations.
  • one of the optimal target weight combinations can be selected for application, and the optimal target weight combination can be one of the best circuit performances, for example, the total circuit parameters of all corresponding phase interpolation units are the smallest.
  • the output delay difference degree in this application can be measured in various ways, and the output delay difference degree in this application is measured by at least one of the variance, standard deviation and typical value difference of all phase delays between the output clock signals
  • the typical value difference is the difference between two typical values, and the typical value is any one of the extreme value, average value and median value of all phase delays.
  • the output delay difference degree in this application is determined by the typical value difference determined by the extreme value of all phase delays and the average value AVE, and the extreme value includes the maximum value MAX and N of all phase delays.
  • the minimum value MIN in the phase delay, the output delay difference is:
  • TARGET max((MAX-AVE), (AVE-MIN));
  • the output delay difference is the maximum value between the difference between the maximum value and the average value and the difference between the minimum value and the average value.
  • each phase interpolation unit includes a basic interpolation circuit and a weight adjustment circuit
  • the basic interpolation circuits in all phase interpolation units are the same
  • the circuit parameters of the weight adjustment circuits in different phase interpolation units correspond to the phase interpolation The output weight of the unit.
  • the basic interpolation circuit can adopt the circuit structure of the existing basic interpolation circuit PI_CELL in FIG.
  • phase interpolation unit in this application is improved by adding a weight adjustment circuit on the basis of the existing PI_CELL, so it can be directly Using the existing conventional PI_CELL circuit, and each phase interpolation unit can use the same PI_CELL circuit, it is only necessary to combine the weight adjustment circuit of different circuit parameters, which can reduce the difficulty of circuit design.
  • phase interpolation unit in this application has a variety of different circuit implementations, which can be mainly divided into two categories:
  • the phase interpolation unit adopts the single-ended transmission mode.
  • the basic interpolation circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1 and a second NMOS transistor N2.
  • the source of a PMOS transistor P1 is connected to the power supply terminal VCC
  • the drain is connected to the source of the second PMOS transistor P2
  • the drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2 and serves as the output terminal of the phase interpolation unit That is, the clock output terminal OUT.
  • the source of the second NMOS transistor N2 is connected to the drain of the first NMOS transistor N1, the source of the first NMOS transistor N1 is connected to the ground terminal VSS, the gate of the first PMOS transistor P1 and the gate of the first NMOS transistor N1 are both
  • the input terminal in of the phase interpolation unit is connected, the gate of the second NMOS transistor N2 is connected to the first switch signal, the gate of the second PMOS transistor P2 is connected to the second switch signal, and the first switch signal and the second switch signal are a pair of poles Sexually opposite signals.
  • the weight adjustment circuit is connected to the source of the second PMOS transistor P2 and the source of the second NMOS transistor N2.
  • the drain of the first PMOS transistor P1 is directly connected to the source of the second PMOS transistor P2, and the source of the second NMOS transistor N2 is directly connected to the first NMOS transistor N1. drain.
  • the weight adjustment circuit includes a third PMOS transistor P3 and a third NMOS transistor N3, the source of the third PMOS transistor P3 is connected to the power supply terminal VCC, the drain is connected to the common terminal of the first PMOS transistor P1 and the second PMOS transistor P2, and the third PMOS transistor P3 is connected to the power supply terminal VCC.
  • the source of the NMOS transistor N3 is grounded, the drain is connected to the common terminal of the first NMOS transistor N1 and the second NMOS transistor N2, the gate of the third PMOS transistor P3 and the gate of the third NMOS transistor N3 are both connected to the input of the phase interpolation unit end in.
  • the size of P3 and N3 corresponds to the target output weight of the phase interpolation unit where they are located.
  • the weight adjustment circuit includes a fourth PMOS transistor P4 and a fourth NMOS transistor N4 .
  • the drain of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P2 through the fourth PMOS transistor P4, and the source of the second NMOS transistor N2 is connected to the first NMOS transistor N1 through the fourth NMOS transistor N4.
  • the drain and drain of the first NMOS transistor N1 are connected to the source and the gate of the second NMOS transistor N2 are connected to the power supply terminal VCC. Then the size of P4 and N4 corresponds to the target output weight of the phase interpolation unit where they are located.
  • the phase interpolation unit adopts the differential transmission mode.
  • the input end of the phase interpolation unit includes a first differential input end VIN and a second differential input end VIP
  • the output end of the phase interpolation unit includes the first differential output. terminal VON and the second differential output terminal VOP.
  • the basic interpolation circuit includes a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a seventh NMOS transistor N7.
  • the source of the fifth NMOS transistor N5 is connected to the ground terminal VSS, and the drain is connected to the source of the sixth NMOS transistor N6 and the seventh NMOS.
  • the source of the transistor N7, the gate of the fifth NMOS transistor N5 is connected to the bias voltage VB, the drain of the sixth NMOS transistor N6 and the drain of the seventh NMOS transistor N7 are connected to the power supply terminal VCC through the load circuit, and the load circuit is set as required , for example, as shown in Figure 6, it can be realized by connecting resistors R1 and R2 of N6 and N7.
  • the gate of the sixth NMOS transistor N6 is connected to the first differential input terminal VIN
  • the gate of the seventh NMOS transistor N7 is connected to the second differential input terminal VIP
  • the drain of the seventh NMOS transistor N7 is used as the first differential output terminal VON
  • the sixth NMOS transistor N7 is used as the first differential output terminal VON.
  • the drain of the NMOS transistor N6 serves as the second differential output terminal VOP.
  • the weight adjustment circuit includes an eighth NMOS transistor N8 and a ninth NMOS transistor N9, the source of the eighth NMOS transistor N8 is connected to the source of the second NMOS transistor N2, the drain is connected to the drain of the second NMOS transistor N2, and the gate is connected to The first differential input terminal VIN, the source of the ninth NMOS transistor N9 is connected to the source of the seventh NMOS transistor N7, the drain is connected to the drain of the seventh NMOS transistor N7, and the gate is connected to the second differential input terminal VIP. Then the size of N8 and N9 corresponds to the target output weight of the phase interpolation unit where they are located.

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Abstract

一种高线性度的相位插值电路，涉及相位插值电路领域，该相位插值电路中各个相位插值单元的电路参数对应于各自的目标输出权重，各个相位插值单元的目标输出权重通过迭代确定且使得该相位插值电路的所有输出时钟信号之间的相位差异度最小；该相位插值电路通过各个相位插值单元的电路参数来人为加入非线性，以补偿MOS管本身存在的非线性，可以有效提升相位插值电路的线性度，实现方式简单，避免了复杂补偿技术的实现难度，不需要增加相位插值长度，不牺牲面积和功耗。

Description

一种高线性度的相位插值电路 技术领域
本发明涉及相位插值电路领域，尤其是一种高线性度的相位插值电路。
 背景技术
在高速接口芯片中，当数据输入后，需要一个处于数据中心位置的时钟对其进行采样，从而进行后续的数据处理。而随着工作条件的不同，数据中心位置也在变化，这就要求采样时钟的相位可以有对应的调节范围，或者说时钟需要实现精细的相位调节，从而为***获得更多的时序余量(timing margin)。
相位插值(PI, Phase Interpolation)是实现精细相位调节的常用技术，应用于并行接口如DDR时,它往往与DLL配合，对DLL生成的相临相位时钟进行相位插值，得到更为精细的多相位时钟输出。应用于串行接口时，它可以作为时钟数据恢复模块(CDR)的一部分，对PLL生成的相临相位时钟进行相位插值，得到更为精细的多相位时钟输出。DLL/PLL往往完成相位的粗调，比如输出0°、45°、90°、135°、180°、225°、270°、315°相位时钟，而PI则完成相位细调，比如PI根据输入的225°与270°时钟生成额外的位于225°与270°之间的5相位时钟，从而提高相位的调节精度。最后，当数据需要进行相位调节时，也可以采用相位插值的原理实现。
目前常用的相位插值电路如图1所示，IN1和IN2是输入的两相位时钟，PI_CELL是基本插值电路，图中一共有2N个完全相同的基本插值电路，N为相位插值的长度，其决定了输出的相位数量。S1~SN以及G1~GN均为开关，控制IN1与IN2的权重，从而决定输出OUT的相位是靠近IN1还是IN2，电容C0/C1/C2用来调节输入信号的摆率，使IN1/IN2为交叠时钟的关系，这样才能平滑地输出。
线性度是相位插值的重要指标，其决定了最小调节精度，由于MOS管行为的非线性，图1所示相位插值电路的输出相位并不能呈现出均匀分布，如图2所示，D1、D2、D3、D4并不能完全相等。为了提高调节精度，目前常用的做法是增加相位插值的长度N来补偿线性度的不足，但这种做法会牺牲芯片面积和功耗。
 技术问题
现有的相位插值电路为了提高调节精度，常用的做法是增加相位插值的长度N来补偿线性度的不足，但这种做法会牺牲芯片面积和功耗。
 技术解决方案
本发明人针对上述问题及技术需求，提出了一种高线性度的相位插值电路，本发明的技术方案如下：
一种高线性度的相位插值电路，该相位插值电路包括：
M个相位插值单元组成的第一并联电路以及N个相位插值单元组成的第二并联电路，第一并联电路的输入端连接第一时钟输入端并通过第一电容接地，第一并联电路的输出端连接时钟输出端，第二并联电路的输入端连接第二时钟输入端并通过第二电容接地，第二并联电路的输出端连接时钟输出端，时钟输出端还通过第零电容接地；
通过控制第一并联电路和第二并联电路中各个相位插值单元所在支路的通断使得时钟输出端输出若干个相位不同的输出时钟信号；
每个相位插值单元的电路参数对应于各自的目标输出权重，各个相位插值单元的目标输出权重通过迭代确定且使得相位插值电路的输出延时差异度最小，输出延时差异度表示相位插值电路通过时钟输出端输出的所有相位不同的输出时钟信号之间的相位差异度。
其进一步的技术方案为，使得相位插值电路的输出延时差异度最小的各个相位插值单元的目标输出权重构成相位插值电路的一个目标权重组合，相位插值电路对应至少两种不同的目标权重组合。
其进一步的技术方案为，初始化各个相位插值单元的输出权重相等并确定对应的输出延时差异度，在保持其余的M+N-1个相位插值单元的输出权重不变的情况下、在预定范围内依次调节第i个相位插值单元的输出权重完成对第i个相位插值单元的遍历调节，并确定每次调节对应的输出延时差异度；依次完成对每个相位插值单元的遍历调节，将对应的输出延时差异度最小时的各个相位插值单元的输出权重作为各个相位插值单元的目标输出权重。
其进一步的技术方案为，输出延时差异度通过输出时钟信号之间的相位延时的方差、标准差和典型值差值中的至少一种方式确定，典型值差值是两个典型值之间的差值，典型值是相位延时中的极值、平均值和中位值中的任意一种。
其进一步的技术方案为，每个相位插值单元所在支路上均串联有控制开关，或者，部分相位插值单元所在支路上串联有控制开关；各个控制开关分别通过独立的控制信号控制，或者存在至少两个控制开关由同一个控制信号控制。
其进一步的技术方案为，M=N且每个相位插值单元分别与一个控制开关串联，第一并联电路中的每条支路与第二并联电路中的每条支路分别一一对应，且存在对应关系的两条支路上的两个控制开关通过同一个控制信号的信号本身及其反相信号同时控制、状态相反。
其进一步的技术方案为，每个相位插值单元分别包括基本插值电路和权重调节电路，所有相位插值单元中的基本插值电路均相同，不同的相位插值单元中的权重调节电路的电路参数对应于相位插值单元的目标输出权重。
其进一步的技术方案为，基本插值电路包括第一PMOS管、第二PMOS管、第一NMOS管和第二NMOS管，第一PMOS管的源极连接电源端、漏极连接至第二PMOS管的源极，第二PMOS管的漏极连接第二NMOS管的漏极并作为相位插值单元的输出端，第二NMOS管的源极连接至第一NMOS管的漏极，第一NMOS管的源极连接接地端，第一PMOS管的栅极以及第一NMOS管的栅极均连接相位插值单元的输入端，第二NMOS管的栅极连接第一开关信号，第二PMOS管的栅极连接第二开关信号，第一开关信号和第二开关信号是一对极性相反的信号；权重调节电路连接至第二PMOS管的源极以及第二NMOS管的源极。
其进一步的技术方案为，在基本插值电路中，第一PMOS管的漏极直接连接第二PMOS管的源极，第二NMOS管的源极直接连接第一NMOS管的漏极；
则权重调节电路包括第三PMOS管和第三NMOS管，第三PMOS管的源极连接电源端、漏极连接第一PMOS管和第二PMOS管的公共端，第三NMOS管的源极接地、漏极连接第一NMOS管和第二NMOS管的公共端，第三PMOS管的栅极和第三NMOS管的栅极均连接相位插值单元的输入端。
其进一步的技术方案为，权重调节电路包括第四PMOS管和第四NMOS管，在基本插值电路中，第一PMOS管的漏极通过第四PMOS管连接第二PMOS管的源极，第二NMOS管的源极通过第四NMOS管连接第一NMOS管的漏极：第四PMOS管的源极连接第一PMOS管的漏极、漏极连接第二PMOS管的源极、栅极连接接地端，第四NMOS管的源极连接第一NMOS管的漏极、漏极连接第二NMOS管的源极、栅极连接电源端。
其进一步的技术方案为，相位插值单元采用差分传输方式，则相位插值单元的输入端包括第一差分输入端和第二差分输入端，相位插值单元的输出端包括第一差分输出端和第二差分输出端；
基本插值电路包括第五NMOS管、第六NMOS管和第七NMOS管，第五NMOS管的源极连接接地端、漏极连接第六NMOS管的源极以及第七NMOS管的源极，第五NMOS管的栅极连接偏置电压，第六NMOS管的漏极以及第七NMOS管的漏极通过负载电路连接电源端，第六NMOS管的栅极连接第一差分输入端，第七NMOS管的栅极连接第二差分输入端，第七NMOS管的漏极作为第一差分输出端，第六NMOS管的漏极作为第二差分输出端；
则权重调节电路包括第八NMOS管和第九NMOS管，第八NMOS管的源极连接第二NMOS管的源极、漏极连接第二NMOS管的漏极、栅极连接第一差分输入端，第九NMOS管的源极连接第七NMOS管的源极、漏极连接第七NMOS管的漏极、栅极连接第二差分输入端。
 有益效果
本申请公开了一种高线性度的相位插值电路，该相位插值电路通过各个相位插值支路上的相位插值单元的电路参数来加入非线性，以补偿MOS管本身存在的非线性，通过设计各个相位插值支路的目标输出权重可以有效提升相位插值电路的线性度，实现方式简单，避免了复杂补偿技术的实现难度，不需要增加相位插值长度，不牺牲面积和功耗。且权重调节电路可以内嵌在现有的基本插值电路中构成本申请的相位插值单元，有利于版图实现。
 附图说明
图1是现有的相位插值电路的电路结构图。
图2是图1的相位插值电路的输出时钟信号示意图。
图3是本申请的相位插值电路的电路结构图。
图4是本申请中的相位插值单元的一种实现电路图。
图5是本申请中的相位插值单元的另一种实现电路图。
图6是本申请中的相位插值单元的另一种实现电路图。
 本发明的实施方式
下面结合附图对本发明的具体实施方式做进一步说明。
本申请公开了一种高线性度的相位插值电路，该相位插值电路包括M个相位插值单元组成的第一并联电路以及N个相位插值单元组成的第二并联电路，每个相位插值单元的输入端in连接至所在并联电路的输入端、输出端连接至所在并联电路的输出端。如图1所示，第一并联电路的输入端连接第一时钟输入端IN1并通过第一电容C1接地，第一并联电路的输出端连接时钟输出端OUT。第二并联电路的输入端连接第二时钟输入端IN2并通过第二电容C2接地，第二并联电路的输出端连接时钟输出端OUT，时钟输出端OUT还通过第零电容C0接地，电容C0/C1/C2用来调节输入信号的摆率。
通过控制第一并联电路和第二并联电路中各个相位插值单元所在支路的通断可以使得时钟输出端OUT输出若干个相位不同的输出时钟信号。较为常规的，通过控制与相位插值单元串联的控制开关的通断来控制所在支路的通断，可选的，每个相位插值单元所在支路上均串联有控制开关、从而使得每个相位插值单元所在支路都可以单独控制通断，或者，部分相位插值单元所在支路上串联有控制开关、从而使得有控制开关的支路可以控制通断、其余支路默认导通。而在控制通断时，各个控制开关分别通过独立的控制信号控制，或者存在至少两个控制开关由同一个控制信号控制，包括直接利用同一个控制信号控制多个控制开关或者利用同一个控制信号及其反相信号控制多个控制开关。
考虑到便于电路调控和版图设计，更为常用的结构是：M=N且每个相位插值单元分别与一个控制开关串联，也即形成如图3这种对称式结构。基于这种对称式结构，各个控制开关可以通过各自的控制信号独立控制，但更为常用的，第一并联电路中的每条支路与第二并联电路中的每条支路分别一一对应，且存在对应关系的两条支路上的两个控制开关通过同一个控制信号的信号本身及其反相信号同时控制、状态相反。比如在图3中，存在对应关系的两条支路上的S1和G1通断状态相反，存在对应关系的两条支路上的S2和G2通断状态相反，存在对应关系的两条支路上的S3和G3通断状态相反，其余类似，从而形成一种结构对称且控制对称的电路。
不管是否采用对称式结构，也不管是否采用对称式控制方式，本申请的主体设计是相同的：本申请对相位插值电路中的各个相位插值单元进行了调整与重新设计，在本申请的相位插值电路中，各个相位插值单元的电路参数对应于各自的目标输出权重。在图3中，相位插值单元CELL1对应的目标输出权重均为T1_1，则图上对相位插值单元表示为CELL1（T1_1），相位插值单元CELL2对应的目标输出权重均为T2_1，则图上对相位插值单元表示为CELL2（T2_1），其他以此类推。
相位插值单元的不同电路参数可以通过内部器件的不同尺寸来实现，不同相位插值单元对应的目标输出权重相同或者不同。较为特殊的，若采用对称式的结构和控制方式，则可以将同一链路上的两个相位插值单元设置为相同的目标输出权重，比如T1_1与T2_1相等。
各个相位插值单元的目标输出权重通过迭代确定且使得输出延时差异度最小，输出延时差异度表示相位插值电路通过时钟输出端OUT所输出的所有相位不同的输出时钟信号之间的相位差异度。假设所输出的5个输出时钟信号如图2所示，则输出延时差异度表示D1、D2、D3和D4之间的差异度。输出延时差异度越小，则相位插值电路的线性度越好。
现有常规的相位插值电路中所有基本插值电路PI_CELL都是相同的，也即可以认为图1所示的常规电路中所有PI_CELL具有相同的输出权重，由于MOS管的非线性，由图2可以看出D1和D4较小，而D2和D3较大，导致相位插值电路的线性度较低。本申请做如下考虑：
以1和0表示S1~S4的状态，1表示开关闭合、0表示开关断开，1111表示S4~S1均闭合，1110表示S4~S2均闭合、S1断开，其他以此类推，而G4~G1与S4~S1对应位置反相。在图1中，在假设同一链路上的两个PI_CELL的权重相等的基础上，定义IN1（1111）表示有4个权重分别为T1/T2/T3/T4的基本插值电路使得输出时钟信号趋向于IN1，IN2（0000）表示没有任何权重分别为T1/T2/T3/T4的基本插值电路使得输出时钟信号趋向于IN2，于是，图2中最左侧趋向于IN1的输出时钟信号可以表示为IN1(1111)+IN2（0000），下一个输出时钟信号可以表示为IN1(1110)+IN2(0001)，以此类推，图1中T1=T2=T3=T4，由于IN1(1110)+IN2(0001)中IN2(0001)太弱，因此导致D1较小，因此可以考虑增大T1以使D1增加。同理，对于D2过大，可以通过减小T2即减弱IN2(0011)。但是改变一个参数比如T1时，不仅会使D1增加，同时也会影响D2、D3和D4，因此本申请通过迭代确定各个目标输出权重。
确定各个相位插值单元对应的目标输出权重的过程如下：
初始化各个相位插值单元的输出权重相等并确定对应的输出延时差异度，在保持其余的M+N-1个相位插值单元的输出权重不变的情况下、在预定范围内依次调节第i个相位插值单元的输出权重完成对第i个相位插值单元的遍历调节，并确定每次调节对应的输出延时差异度。通过这种方式，依次完成对每个相位插值单元的遍历调节，将对应的输出延时差异度最小时的各个相位插值单元的输出权重作为各个相位插值单元的目标输出权重。
其中，相位插值单元的输出权重在调节时的预定范围通常由电路结构可实现的电路参数的范围决定，可以认为是一个预先确定的范围。在上述过程，每次可以选定任意一个相位插值单元的输出权重进行调节，当选定调节的顺序不同时，可能导致最终而定的各个相位插值单元的目标输出权重不同。因此在本申请中，若定义使得输出延时差异度最小的各个相位插值单元的目标输出权重构成相位插值电路的一个目标权重组合，该相位插值单元对应至少两种不同的目标权重组合。实际可以选择其中最优的一个目标权重组合进行应用，最优的一个目标权重组合可以是其中一项电路性能最优，比如对应的所有相位插值单元的总的电路参数最小。
本申请中的输出延时差异度可以通过多种方式衡量，本申请中的输出延时差异度通过输出时钟信号之间的所有相位延时的方差、标准差和典型值差值中的至少一种方式确定，典型值差值是两个典型值之间的差值，典型值是所有相位延时中的极值、平均值和中位值中的任意一种。
较为典型的，本申请中的输出延时差异度通过所有相位延时中的极值和平均值AVE所确定的典型值差值确定，极值包括所有相位延时中的最大值MAX以及N个相位延时中的最小值MIN，则输出延时差异度为：
TARGET=max（（MAX-AVE），（AVE-MIN））；
也即输出延时差异度为最大值与平均值的差值以及最小值与平均值的差值之间的最大值。
在本申请中，每个相位插值单元分别包括基本插值电路和权重调节电路，所有相位插值单元中的基本插值电路均相同，不同的相位插值单元中的权重调节电路的电路参数对应于所在相位插值单元的输出权重。基本插值电路可以采用图1中的现有的基本插值电路PI_CELL的电路结构，也即可以认为本申请中的相位插值单元是在现有的PI_CELL的基础上增加权重调节电路改进得到，因此可以直接使用现有常规的PI_CELL电路，而且各个相位插值单元都可以使用相同的PI_CELL电路，只需结合不同电路参数的权重调节电路即可，这种做法可以减少电路设计难度。
本申请中的相位插值单元具有多种不同的电路实现方式，主要可以分为两大类：
第一类，相位插值单元采用单端传输方式，如图4和5所示，基本插值电路包括第一PMOS管P1、第二PMOS管P2、第一NMOS管N1和第二NMOS管N2，第一PMOS管P1的源极连接电源端VCC、漏极连接至第二PMOS管P2的源极，第二PMOS管P2的漏极连接第二NMOS管N2的漏极并作为相位插值单元的输出端也即时钟输出端OUT。第二NMOS管N2的源极连接至第一NMOS管N1的漏极，第一NMOS管N1的源极连接接地端VSS，第一PMOS管P1的栅极以及第一NMOS管N1的栅极均连接相位插值单元的输入端in，第二NMOS管N2的栅极连接第一开关信号，第二PMOS管P2的栅极连接第二开关信号，第一开关信号和第二开关信号是一对极性相反的信号。权重调节电路连接至第二PMOS管P2的源极以及第二NMOS管N2的源极。
基于这种架构，具体的可以有如下两种电路结构：
（1）、如图4所示，在基本插值电路中，第一PMOS管P1的漏极直接连接第二PMOS管P2的源极，第二NMOS管N2的源极直接连接第一NMOS管N1的漏极。
则权重调节电路包括第三PMOS管P3和第三NMOS管N3，第三PMOS管P3的源极连接电源端VCC、漏极连接第一PMOS管P1和第二PMOS管P2的公共端，第三NMOS管N3的源极接地、漏极连接第一NMOS管N1和第二NMOS管N2的公共端，第三PMOS管P3的栅极和第三NMOS管N3的栅极均连接相位插值单元的输入端in。则P3和N3的尺寸对应于所在相位插值单元的目标输出权重。
（2）、如图5所示，权重调节电路包括第四PMOS管P4和第四NMOS管N4。在基本插值电路中，第一PMOS管P1的漏极通过第四PMOS管P4连接第二PMOS管P2的源极，第二NMOS管N2的源极通过第四NMOS管N4连接第一NMOS管N1的漏极：第四PMOS管P4的源极连接第一PMOS管P1的漏极、漏极连接第二PMOS管P2的源极、栅极连接接地端VSS，第四NMOS管N4的源极连接第一NMOS管N1的漏极、漏极连接第二NMOS管N2的源极、栅极连接电源端VCC。则P4和N4的尺寸对应于所在相位插值单元的目标输出权重。
第二类，相位插值单元采用差分传输方式，如图6所示，相位插值单元的输入端包括第一差分输入端VIN和第二差分输入端VIP，相位插值单元的输出端包括第一差分输出端VON和第二差分输出端VOP。
基本插值电路包括第五NMOS管N5、第六NMOS管N6和第七NMOS管N7，第五NMOS管N5的源极连接接地端VSS、漏极连接第六NMOS管N6的源极以及第七NMOS管N7的源极，第五NMOS管N5的栅极连接偏置电压VB，第六NMOS管N6的漏极以及第七NMOS管N7的漏极通过负载电路连接电源端VCC，负载电路根据需要设置，比如可以如图6所示，通过连接N6和N7的电阻R1和R2实现。第六NMOS管N6的栅极连接第一差分输入端VIN，第七NMOS管N7的栅极连接第二差分输入端VIP，第七NMOS管N7的漏极作为第一差分输出端VON，第六NMOS管N6的漏极作为第二差分输出端VOP。
则权重调节电路包括第八NMOS管N8和第九NMOS管N9，第八NMOS管N8的源极连接第二NMOS管N2的源极、漏极连接第二NMOS管N2的漏极、栅极连接第一差分输入端VIN，第九NMOS管N9的源极连接第七NMOS管N7的源极、漏极连接第七NMOS管N7的漏极、栅极连接第二差分输入端VIP。则N8和N9的尺寸对应于所在相位插值单元的目标输出权重。
以上所述的仅是本申请的优选实施方式，本发明不限于以上实施例。可以理解，本领域技术人员在不脱离本发明的精神和构思的前提下直接导出或联想到的其他改进和变化，均应认为包含在本发明的保护范围之内。

Claims (10)

  1. 一种高线性度的相位插值电路，其特征在于，所述相位插值电路包括：
    M个相位插值单元组成的第一并联电路以及N个相位插值单元组成的第二并联电路，所述第一并联电路的输入端连接第一时钟输入端并通过第一电容接地，所述第一并联电路的输出端连接时钟输出端，所述第二并联电路的输入端连接第二时钟输入端并通过第二电容接地，所述第二并联电路的输出端连接所述时钟输出端，所述时钟输出端还通过第零电容接地；
    通过控制所述第一并联电路和所述第二并联电路中各个相位插值单元所在支路的通断使得所述时钟输出端输出若干个相位不同的输出时钟信号；
    每个相位插值单元的电路参数对应于各自的目标输出权重，各个相位插值单元的目标输出权重通过迭代确定且使得所述相位插值电路的输出延时差异度最小，所述输出延时差异度表示所述相位插值电路通过所述时钟输出端输出的所有相位不同的输出时钟信号之间的相位差异度。
  2. 根据权利要求1所述的相位插值电路，其特征在于，
    使得所述相位插值电路的输出延时差异度最小的各个相位插值单元的目标输出权重构成所述相位插值电路的一个目标权重组合，所述相位插值电路对应至少两种不同的目标权重组合。
  3. 根据权利要求1所述的相位插值电路，其特征在于，
    初始化各个相位插值单元的输出权重相等并确定对应的输出延时差异度，在保持其余的M+N-1个相位插值单元的输出权重不变的情况下、在预定范围内依次调节第i个相位插值单元的输出权重完成对第i个相位插值单元的遍历调节，并确定每次调节对应的输出延时差异度；依次完成对每个相位插值单元的遍历调节，将对应的输出延时差异度最小时的各个相位插值单元的输出权重作为各个相位插值单元的目标输出权重。
  4. 根据权利要求1所述的相位插值电路，其特征在于，
    每个相位插值单元所在支路上均串联有控制开关，或者，部分相位插值单元所在支路上串联有控制开关；各个控制开关分别通过独立的控制信号控制，或者存在至少两个控制开关由同一个控制信号控制。
  5. 根据权利要求4所述的相位插值电路，其特征在于，
    M=N且每个相位插值单元分别与一个控制开关串联，所述第一并联电路中的每条支路与所述第二并联电路中的每条支路分别一一对应，且存在对应关系的两条支路上的两个控制开关通过同一个控制信号的信号本身及其反相信号同时控制、状态相反。
  6. 根据权利要求1-5任一所述的相位插值电路，其特征在于，
    每个相位插值单元分别包括基本插值电路和权重调节电路，所有相位插值单元中的基本插值电路均相同，不同的相位插值单元中的权重调节电路的电路参数对应于所述相位插值单元的目标输出权重。
  7. 根据权利要求6所述的相位插值电路，其特征在于，
    所述基本插值电路包括第一PMOS管、第二PMOS管、第一NMOS管和第二NMOS管，所述第一PMOS管的源极连接电源端、漏极连接至所述第二PMOS管的源极，所述第二PMOS管的漏极连接所述第二NMOS管的漏极并作为所述相位插值单元的输出端，所述第二NMOS管的源极连接至所述第一NMOS管的漏极，所述第一NMOS管的源极连接接地端，所述第一PMOS管的栅极以及所述第一NMOS管的栅极均连接所述相位插值单元的输入端，所述第二NMOS管的栅极连接第一开关信号，所述第二PMOS管的栅极连接第二开关信号，所述第一开关信号和所述第二开关信号是一对极性相反的信号；所述权重调节电路连接至所述第二PMOS管的源极以及所述第二NMOS管的源极。
  8. 根据权利要求7所述的相位插值电路，其特征在于，在所述基本插值电路中，所述第一PMOS管的漏极直接连接所述第二PMOS管的源极，所述第二NMOS管的源极直接连接所述第一NMOS管的漏极；
    则所述权重调节电路包括第三PMOS管和第三NMOS管，所述第三PMOS管的源极连接所述电源端、漏极连接所述第一PMOS管和第二PMOS管的公共端，所述第三NMOS管的源极接地、漏极连接所述第一NMOS管和第二NMOS管的公共端，所述第三PMOS管的栅极和所述第三NMOS管的栅极均连接所述相位插值单元的输入端。
  9. 根据权利要求7所述的相位插值电路，其特征在于，所述权重调节电路包括第四PMOS管和第四NMOS管，在所述基本插值电路中，所述第一PMOS管的漏极通过所述第四PMOS管连接所述第二PMOS管的源极，所述第二NMOS管的源极通过所述第四NMOS管连接所述第一NMOS管的漏极：所述第四PMOS管的源极连接所述第一PMOS管的漏极、漏极连接所述第二PMOS管的源极、栅极连接所述接地端，所述第四NMOS管的源极连接所述第一NMOS管的漏极、漏极连接所述第二NMOS管的源极、栅极连接所述电源端。
  10. 根据权利要求6所述的相位插值电路，其特征在于，
    所述相位插值单元采用差分传输方式，则所述相位插值单元的输入端包括第一差分输入端和第二差分输入端，所述相位插值单元的输出端包括第一差分输出端和第二差分输出端；
    所述基本插值电路包括第五NMOS管、第六NMOS管和第七NMOS管，所述第五NMOS管的源极连接接地端、漏极连接所述第六NMOS管的源极以及所述第七NMOS管的源极，所述第五NMOS管的栅极连接偏置电压，所述第六NMOS管的漏极以及所述第七NMOS管的漏极通过负载电路连接电源端，所述第六NMOS管的栅极连接第一差分输入端，所述第七NMOS管的栅极连接第二差分输入端，所述第七NMOS管的漏极作为所述第一差分输出端，所述第六NMOS管的漏极作为所述第二差分输出端；
    则所述权重调节电路包括第八NMOS管和第九NMOS管，所述第八NMOS管的源极连接所述第二NMOS管的源极、漏极连接所述第二NMOS管的漏极、栅极连接所述第一差分输入端，所述第九NMOS管的源极连接所述第七NMOS管的源极、漏极连接所述第七NMOS管的漏极、栅极连接所述第二差分输入端。
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