WO2022202795A1 - Metal plate, laminate, and insulated circuit board - Google Patents

Metal plate, laminate, and insulated circuit board Download PDF

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Publication number
WO2022202795A1
WO2022202795A1 PCT/JP2022/013103 JP2022013103W WO2022202795A1 WO 2022202795 A1 WO2022202795 A1 WO 2022202795A1 JP 2022013103 W JP2022013103 W JP 2022013103W WO 2022202795 A1 WO2022202795 A1 WO 2022202795A1
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WO
WIPO (PCT)
Prior art keywords
layer
metal plate
insulating resin
plate material
resin layer
Prior art date
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PCT/JP2022/013103
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French (fr)
Japanese (ja)
Inventor
万里奈 坂巻
賢治 久保田
東洋 大橋
Original Assignee
三菱マテリアル株式会社
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Application filed by 三菱マテリアル株式会社 filed Critical 三菱マテリアル株式会社
Priority to JP2023509188A priority Critical patent/JPWO2022202795A1/ja
Publication of WO2022202795A1 publication Critical patent/WO2022202795A1/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B15/08—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate

Definitions

  • the present invention relates to a metal plate material, a laminate having a structure in which a resin member and a metal plate material are laminated, and an insulated circuit board.
  • a power module, an LED module, and a thermoelectric module have a structure in which a power semiconductor element, an LED element, and a thermoelectric element are joined to an insulating circuit board in which a circuit layer made of a conductive material is formed on one side of an insulating layer.
  • the insulating layer one using ceramics and one using insulating resin have been proposed.
  • Patent Document 1 proposes a metal base circuit board.
  • Patent Document 2 proposes a multilayer wiring board.
  • an insulating resin layer is formed on the metal board, and a circuit layer having a circuit pattern is formed on the insulating resin layer.
  • the insulating resin layer is made of epoxy resin, which is a thermosetting resin
  • the circuit layer is made of copper foil.
  • a semiconductor element is bonded onto the circuit layer, and a heat sink is provided on the opposite side of the metal substrate to the insulating resin layer, so that heat generated by the semiconductor element is transmitted to the heat sink side.
  • the structure is designed to dissipate heat by
  • the multilayer wiring board described in Patent Document 2 is manufactured by the following method.
  • the surface roughness (Ra) of the metal foil is set to 0.2 ⁇ m or more, and the wiring circuit layer is formed by etching in a circuit pattern.
  • the wiring circuit layer formed on the surface of the resin film is embedded in the surface of the soft insulating sheet while applying pressure to transfer the insulating circuit layer to the surface of the insulating sheet.
  • a plurality of insulating sheets thus obtained are laminated and collectively heat-cured.
  • the insulating resin layer and the circuit layer (metal plate) may peel off, or the insulating resin layer and the metal substrate (metallic plate) may peel off. It is necessary to secure adhesion between the insulating resin layer and the circuit layer (metal plate) and adhesion between the insulating resin layer and the metal substrate (metal plate) so as not to cause peeling of the substrate.
  • the metal base circuit board described in Patent Document 1 it is not considered to improve the adhesion between the insulating resin layer and the circuit layer and the adhesion between the insulating resin layer and the metal substrate. Occasionally, the insulating resin layer and the circuit layer (metal plate) may be separated, or the insulating resin layer and the metal substrate (metal plate) may be separated.
  • the surface roughness (Ra) of the wiring circuit layer is set to 0.2 ⁇ m or more and embedded in the insulating sheet, thereby improving the adhesion between the insulating sheet and the wiring circuit layer.
  • the surface roughness (Ra) of the wiring circuit layer is set to 0.2 ⁇ m or more, if the protrusions protruding from the circuit layer side are not uniformly and densely formed, the insulating sheet and the There was a risk that the adhesion of the film could not be ensured.
  • the present invention has been made in view of the circumstances described above, and provides a metal plate material having excellent adhesion to a laminated resin member, a laminate in which the metal plate material and the resin member are laminated, and an insulated circuit board. intended to provide
  • the inventors of the present invention conducted extensive studies, and as a result, it was confirmed that by performing pulse plating on a metal plate, it was possible to form a roughened plating layer in which a plurality of convex portions were formed. Then, the inventors have found that by reducing the residual stress of the metal plate when forming the roughened plating layer, it is possible to form the convex portions uniformly and precisely.
  • a metal plate material according to one aspect of the present invention has a plate body and a roughened plating layer formed on the outermost layer of the plate body.
  • the roughened plating layer has a convex portion that protrudes toward the opposite side of the plate body, and the KAM value is is 1.0 or more, and the area ratio of the region is 10% or less, and the Sdr (development interface area ratio) of the outermost surface of the roughening plating layer is 20% or more, or the roughening plating layer
  • the outermost surface R ratio of developed interface line length
  • the KAM (Kernel Average Misorientation) value is a value calculated by averaging the orientation difference between one pixel in a certain crystal grain and the pixels surrounding it. Since the shape of the pixel is a regular hexagon, when the degree of proximity is 1 (1st), the average value of the orientation difference with six adjacent pixels is calculated as the KAM value. However, if there is a crystal grain boundary between adjacent measurement points, it is not included in the calculation of the KAM value. By using this KAM value, it becomes possible to visualize the distribution of local misorientation, that is, strain. A region with a high KAM value is a region with a high strain introduced during processing, resulting in a high residual stress.
  • the area ratio of the region having a KAM value of 1.0 or more is 10% or less in the region of 6 ⁇ m in the thickness direction from the outermost layer of the roughened plating layer. Residual stress in the surface layer portion is kept low, and in the roughened plating layer, convex portions protruding toward the side opposite to the plate body can be uniformly and precisely formed. Further, since the Sdr (development interface area ratio) of the outermost surface of the roughened plating layer is 20% or more, or the R (development interface line length ratio) of the outermost surface of the roughening plating layer is 40% or more. , it is possible to improve the adhesion with the resin member laminated on the roughened plating layer side.
  • the convex portion includes a widened portion whose width gradually increases toward the tip end side in the projecting direction.
  • the protruding portion protruding toward the opposite side of the plate body has a widened portion whose width gradually increases toward the tip side in the protruding direction, it is laminated on the roughened plating layer side.
  • the resin member is reliably engaged with the convex portion, and it is possible to improve the adhesion with the resin member.
  • the plate body is preferably made of copper or a copper alloy.
  • the plate body since the plate body is made of copper or a copper alloy, it has excellent electrical conductivity and thermal conductivity.
  • a laminate according to an aspect of the present invention is a laminate in which a resin member is laminated on the plate surface of the above-described metal plate material, and at a joint interface between the resin member and the metal plate material, the metal plate material The resin member is engaged with the convex portion.
  • the resin member is laminated on the plate surface (roughened plating layer) of the metal plate material on which the protrusions are formed, and at the joint interface between the resin member and the metal plate material, the Since the convex portion of the metal plate material and the resin member are engaged with each other, it is possible to improve the adhesion between the resin member and the metal plate material.
  • the laminated body includes the metal plate material described above and a resin member laminated on the plate surface of the metal plate material on the roughened plating layer side.
  • An insulated circuit board is an insulated circuit board including an insulating resin layer and a circuit layer formed on one surface of the insulating resin layer, wherein the circuit layer comprises the above-described
  • the insulating resin layer is formed by bonding a metal plate material to one surface of the insulating resin layer, and the insulating resin layer is formed on the convex portion of the metal plate material at the bonding interface between the insulating resin layer and the circuit layer. characterized by being engaged.
  • the circuit layer is formed by bonding the plate surface (roughened plating layer) of the metal plate on which the protrusions are formed to one surface of the insulating resin layer.
  • the insulating resin layer is engaged with the convex portion of the circuit layer (copper member), so that the adhesion between the circuit layer and the insulating resin layer is improved.
  • An insulated circuit board comprises an insulating resin layer, a circuit layer formed on one surface of the insulating resin layer, a metal substrate formed on the other surface of the insulating resin layer, , wherein one or both of the circuit layer and the metal substrate are formed by bonding the metal plate material described above to the surface of the insulating resin layer, and the insulating resin
  • the insulating resin layer is engaged with the convex portion of the metal plate at one or both of the bonding interface between the layer and the circuit layer and the bonding interface between the insulating resin layer and the metal substrate. It is characterized by
  • the insulated circuit board having this configuration, by bonding the plate surface (roughened plating layer) of the metal plate on which the protrusions are formed to the surface of the insulating resin layer, one or both of the circuit layer and the metal substrate is formed. At one or both of the bonding interface between the insulating resin layer and the circuit layer and the bonding interface between the insulating resin layer and the metal substrate, the insulating resin layer is formed on the convex portion of the metal plate material. engaged. Therefore, the adhesion between the circuit layer and the insulating resin layer or the adhesion between the metal substrate and the insulating resin layer can be improved.
  • FIG. 1 is a schematic explanatory diagram of a power module provided with an insulated circuit board according to an embodiment of the present invention
  • FIG. FIG. 2 is an explanatory diagram of the metal plate material according to the embodiment of the present invention, and more specifically, an observation photograph of the vicinity of the surface.
  • FIG. 2 is an explanatory diagram of the metal plate material according to the embodiment of the present invention, and more specifically, a schematic diagram of an engaging projection.
  • 1 is a flowchart showing a method for manufacturing an insulated circuit board according to an embodiment of the present invention
  • FIG. FIG. 4 is a schematic explanatory view of a method for manufacturing the insulated circuit board shown in FIG. 3
  • FIG. 1 is a schematic illustration of a testing apparatus for evaluating the insulation (withstand voltage) of an insulated circuit board in Examples.
  • FIG. 1 shows an insulated circuit board 10 and a power module 1 using the insulated circuit board 10 according to an embodiment of the present invention.
  • the insulating circuit board 10 according to this embodiment includes an insulating resin layer 12, a circuit layer 13 formed on one surface of the insulating resin layer 12, and a metal substrate 11 formed on the other surface of the insulating resin layer 12. , provided. Both the circuit layer 13 and the metal substrate 11 are formed by bonding the metal plate material 30 according to this embodiment to the surface of the insulating resin layer 12 .
  • the insulating resin layer 12 is an example of a resin member, and it can also be said that the insulating circuit board 10 according to this embodiment is a laminate according to this embodiment.
  • the laminate according to this embodiment includes the metal plate material 30 according to this embodiment and a resin member, and the resin member is laminated on the plate surface (roughened plating layer) of the metal plate material 30 . In other words, the metal plate material 30 is bonded to the surface of the resin member.
  • the power module 1 shown in FIG. 1 includes an insulating circuit board 10, a semiconductor element 3 bonded to one surface (upper surface in FIG. 1) of the insulating circuit board 10 via a first solder layer 2, and an insulating circuit board. 10 (lower side in FIG. 1) and a heat sink 41 bonded via a second solder layer 42 .
  • the semiconductor element 3 is made of a semiconductor material such as Si.
  • the first solder layer 2 that joins the insulating circuit board 10 and the semiconductor element 3 is made of, for example, a Sn--Ag-based, Sn--Cu-based, Sn--In-based, or Sn--Ag--Cu-based solder material (so-called lead-free solder). material).
  • the heat sink 41 is for dissipating heat from the insulating circuit board 10 side.
  • the heat sink 41 is made of copper, a copper alloy, aluminum, an aluminum alloy, or the like, which has good thermal conductivity.
  • the radiator plate is made of oxygen-free copper.
  • the thickness of the heat sink 41 is set within a range of 3 mm or more and 10 mm or less.
  • the insulating circuit board 10 and the heat sink 41 are bonded via the second solder layer 42 .
  • the second solder layer 42 can have the same configuration as the first solder layer 2 described above.
  • the insulating circuit board 10 of the present embodiment includes a metal substrate 11, an insulating resin layer 12 formed on one surface (upper surface in FIG. 1) of the metal substrate 11, and an insulating resin and a circuit layer 13 formed on one surface of the layer 12 (upper surface in FIG. 1).
  • the metal substrate 11 has the effect of improving the heat dissipation characteristics by spreading the heat generated in the semiconductor element 3 mounted on the insulated circuit substrate 10 in the plane direction. Therefore, the metal substrate 11 is made of a metal with excellent thermal conductivity, such as copper or a copper alloy, aluminum or an aluminum alloy. In this embodiment, it is made of a rolled sheet of oxygen-free copper. The thickness of the metal substrate 11 is set within a range of 0.05 mm or more and 3 mm or less, and is set to 2.0 mm in this embodiment.
  • the insulating resin layer 12 prevents electrical connection between the circuit layer 13 and the metal substrate 11, and is made of an insulating thermosetting resin.
  • a thermosetting resin containing a filler is used in order to ensure the strength of the insulating resin layer 12 and to ensure thermal conductivity.
  • alumina, boron nitride, aluminum nitride, or the like can be used as the filler.
  • an epoxy resin, a polyimide resin, etc. can be used as a thermosetting resin.
  • the insulating resin layer 12 is made of an epoxy resin containing boron nitride as a filler.
  • the thickness of the insulating resin layer 12 is set within a range of 20 ⁇ m or more and 250 ⁇ m or less, and is set to 150 ⁇ m in this embodiment.
  • the circuit layer 13 has a circuit pattern formed by bonding a metal plate material 30 according to the present embodiment to one surface (upper surface in FIG. 4) of the insulating resin layer 12 . Specifically, one surface of the insulating resin layer 12 and the surface of the metal plate member 30 on the roughened plating layer 35 side are joined together. Alternatively, a circuit pattern may be first formed on the metal plate material 30 and then the metal plate material 30 having the circuit pattern formed thereon may be bonded to one surface of the insulating resin layer 12 . A circuit pattern is formed on the circuit layer 13, and one surface (upper surface in FIG. 1) of the circuit layer 13 serves as a mounting surface on which the semiconductor element 3 is mounted.
  • the thickness of the circuit layer 13 is set within a range of 0.3 mm or more and 3 mm or less, and is set to 0.5 mm in this embodiment.
  • the metal plate material 30 of this embodiment which becomes the circuit layer 13 described above, will be described with reference to FIGS. 2A and 2B.
  • the metal plate material 30 of the present embodiment is made of a metal having excellent electrical conductivity and thermal conductivity. In the present embodiment, it is made of copper or a copper alloy, specifically oxygen-free copper. It is configured. As shown in FIG. 2A, the metal plate material 30 of this embodiment includes a plate body 31 and a roughened plating layer 35 formed on the outermost layer of the plate body 31 .
  • the roughened plating layer 35 is formed with convex portions 36 that protrude toward the side opposite to the plate body 31 (upper side in FIG. 2B).
  • the convex portion 36 preferably includes a widened portion 36a whose width gradually increases toward the tip side in the projecting direction.
  • the KAM value is 1.0 or more when the area of the copper portion in the region of 6 ⁇ m in the thickness direction from the outermost layer of the roughened plating layer 35 is 100%.
  • the area ratio of a certain region is set to 10% or less.
  • the Sdr (developed interface area ratio) of the outermost surface of the roughened plating layer 35 is 20% or more, or the R (developed interface line length ratio) of the outermost surface of the roughened plating layer 35 is 40% or more. .
  • the protrusions 36 of the circuit layer 13 (metal plate material 30) and the insulating resin layer 12 are engaged at the bonding interface between the insulating resin layer 12 and the circuit layer 13.
  • the circuit layer 13 (metal plate material 30) and the insulating resin layer 12 are embedded in each other.
  • the metal substrate 11 is formed by joining the metal plate material 30 of this embodiment to the other surface (lower surface in FIG. 4) of the insulating resin layer 12 . Specifically, the other surface of the insulating resin layer 12 and the surface of the metal plate member 30 on the roughened plating layer 35 side are joined together. Also at the joint interface between the insulating resin layer 12 and the metal substrate 11, the convex portion of the metal substrate 11 (metal plate material 30) and the insulating resin layer 12 are engaged, and the metal substrate 11 (metal plate material 30) and the insulating resin are engaged.
  • the layer 12 and the layer 12 have a structure in which they enter each other.
  • the area ratio of the region having a KAM value of 1.0 or more, the outermost surface of the roughened plating layer 35 The reason why Sdr (ratio of developed interface area) and R (ratio of developed interface line length) of the outermost surface of the roughened plating layer 35 are defined as described above will be explained.
  • the KAM (Kernel Average Misorientation) value measured by the EBSD method evaluates the local orientation difference, that is, the strain distribution. and the residual stress is high.
  • the area ratio of the region having a KAM value of 1.0 or more in the region of 6 ⁇ m in the thickness direction from the outermost layer of the roughened plating layer 35 is low, the region with high strain is small. Residual stress is sufficiently reduced, and it becomes possible to form convex portions 36 uniformly and precisely in the roughened plating layer 35 . Therefore, in the metal plate material 30 of the present embodiment, the area ratio of a region having a KAM value of 1.0 or more in a region of 6 ⁇ m in the thickness direction from the outermost layer of the roughened plating layer 35 is limited to 10% or less. ing.
  • the area ratio of a region having a KAM value of 1.0 or more in a region of 6 ⁇ m in the thickness direction from the outermost layer of the roughened plating layer 35 is preferably 5% or less, and is preferably 3% or less. More preferred.
  • the lower limit of the above area ratio is not particularly limited, and is most preferably 0%.
  • the top of the most protruding convex portion 36 is the "outermost layer of the roughened plating layer 35"
  • the area of the metal portion in the region of 6 ⁇ m in the thickness direction from here is 100%
  • the KAM value is The area ratio of the region that is 1.0 or more is calculated.
  • Sdr expansion interface area ratio
  • Sdr expansion interface area ratio
  • the Sdr (development interface area ratio) of the outermost surface of the roughened plating layer 35 is specified to be 20% or more.
  • the Sdr (spread interface area ratio) of the outermost surface of the roughened plating layer 35 is preferably 40% or more, more preferably 65% or more.
  • Sdr (spread interface area ratio) is measured by the following method.
  • a 129 ⁇ m ⁇ 129 ⁇ m range of the surface of the roughened plating layer 35 of the metal plate material 30 is observed using a 100 ⁇ objective lens of a laser microscope. Perform processing to remove sample tilt and noise. The obtained image is analyzed, and Sdr (ratio of developed interface area) is calculated by the above formula. Normally, Sdr (development interface area ratio) is measured on the metal plate material 30 before being joined to the insulating resin layer (resin member) 12 .
  • the circuit layer 13 and the metal substrate 11 of the insulating circuit board (laminate) 10 are the metal plate material 30 and the metal plate material 30 is bonded to the insulating resin layer (resin member) 12, the insulating circuit board (laminate) ) 10 is measured by the following method.
  • the insulating resin layer (resin member) 12 is removed by dissolving the insulating resin layer (resin member) 12 with an organic solvent or the like, or by baking the insulating circuit board (laminate) 10 . In this way, the bonding interface (the surface of the roughened plating layer 35 of the metal plate material 30) between the metal plate material 30 and the insulating resin layer (resin member) 12 is exposed. Then, the surface is observed using a laser microscope as described above. The obtained image is analyzed, and Sdr (ratio of developed interface area) is calculated by the above formula.
  • R development interface line length ratio
  • L1 the length of the cross-sectional curve projected onto the X axis (projected length) is L0
  • R is expressed by the following equation.
  • the thickness direction of the roughening plating layer in a cross section be the Y-axis, and let the direction orthogonal to the Y-axis be the X-axis.
  • the R ⁇ (L 1 /L 0 )-1 ⁇ x 100 (%)
  • the R (development interface line length ratio) of the outermost surface of the roughening plating layer 35 is specified to be 40% or more.
  • R (development interface line length ratio) is preferably 100% or more, more preferably 150% or more. Although there is no particular upper limit for R (development interface line length ratio), it is practically 1000% or less.
  • R (ratio of developed interface line length) is measured by the following method. A section parallel to the longitudinal direction of the metal plate member 30 and a section perpendicular to the longitudinal direction of the metal plate member 30 are prepared.
  • R development interface line length ratio
  • the average value of R (developed interface line length ratio) in a cross section parallel to the longitudinal direction of the metal plate material 30 and R (developed interface line length ratio) in a cross section perpendicular to the longitudinal direction of the metal plate material 30 is calculated.
  • 30 of the roughened plating layer 35 is defined as R (ratio of developed interface line length).
  • the insulating circuit board (laminate) ) 10 is measured by the following method. A section parallel to the longitudinal direction of the insulating circuit board (laminate) 10 and a section perpendicular to the longitudinal direction of the insulating circuit board (laminate) 10 are prepared. Each cross section is observed with a scanning electron microscope at a magnification of 1000 times. In the cross section, a cross-sectional curve of the roughened plating layer 35 at the bonding interface between the metal plate material 30 and the insulating resin layer (resin member) 12 is specified.
  • R development interface line length ratio
  • the outline of the metal piece that is independent of the metal plate material 30 and that exists in the insulating resin layer (resin member) 12 and the outline of the resin piece that is independent of the insulating resin layer (resin member) 12 and exists in the metal plate material 30 are shown in cross section. It is not included in the line length (L 1 ) of the curve.
  • the metal plate material 30 (circuit layer 13 and metal substrate 11) in the insulating circuit board (laminate) 10 The R (development interface line length ratio) of the metal substrate 11) can be easily measured.
  • the metal substrate 11 is not provided with a metal plate material 30, but the metal substrate 11 is the metal plate material 30, and includes a plate main body 31 and a roughened surface formed on the outermost layer of the plate main body 31. and a plating layer 35 .
  • Stress reduction step S01 First, in the metal plate material 30 that becomes the circuit layer 13, the residual stress in the vicinity of the surface of the plate body 31 (the surface on which the roughened plating layer 35 is formed) is reduced. Similarly, the residual stress in the vicinity of the surface of the metal substrate 11 (the surface on which the roughened plating layer 35 is formed) is reduced.
  • a method for reducing residual stress is not particularly limited, but chemical polishing, heat treatment, direct current electroplating, etc., can be applied, for example.
  • a chemical polishing liquid for example, a mixture of sulfuric acid and hydrogen peroxide
  • a chemical polishing liquid for example, a mixture of sulfuric acid and hydrogen peroxide
  • the residual stress in the vicinity of the surface of the plate body 31 is reduced, for example, by holding at a temperature of 400° C. or higher and 600° C. or lower for 1 hour or more and 2 hours or less.
  • DC electroplating for example, the surface of the plate body 31 is subjected to electrolytic degreasing treatment and pickling treatment, and then a film of 6 ⁇ m or more is formed at high temperature and low current density. After that, the residual stress in the vicinity of the surface of the plate body 31 is reduced by leaving it at room temperature for several days or performing heat treatment at 150° C. for 1 hour.
  • a roughening plated layer 35 is formed on the surface of the plate body 31 in which the surface residual stress is reduced.
  • the roughening plated layer 35 is also formed on the metal substrate 11 .
  • This roughening plated layer 35 is formed as follows. Electroplating is applied to the joint surfaces of the plate body 31 (and the metal substrate 11).
  • 3,3′-dithiobis(1-propanesulfonic acid) disodium is added to a copper sulfate bath containing copper sulfate (CuSO 4 ) and sulfuric acid (H 2 SO 4 ) as main components as an electrolytic plating solution.
  • CuSO 4 copper sulfate
  • H 2 SO 4 sulfuric acid
  • the temperature of the plating bath is preferably within the range of 25° C. or higher and 35° C. or lower.
  • the electroplating treatment is first performed by a DC electroplating method, and then performed by a PR (Periodic Reverse) pulse electroplating method.
  • the current density is set within the range of 1 A/dm 2 or more and 20 A/dm 2 or less
  • the application time is set within the range of 10 seconds or more and 120 seconds or less.
  • the PR pulse electroplating method is a method of performing electroplating by applying current while periodically reversing the direction of the current. For example, a positive electrolysis of 1 A/dm 2 or more and 30 A/dm 2 or less (anodic electrolysis using the plate body 31 (and the metal substrate 11) as an anode) is 1 ms or more and 1000 ms or less, and a negative electrolysis of 1 A/dm 2 or more and 30 A/dm 2 or less. Electrolysis (negative electrolysis using the plate body 31 (and the metal substrate 11) as the negative electrode) is repeated for 1 ms or more and 1000 ms or less. As a result, the dissolution of the surface of the plate body 31 (and the metal substrate 11) and the deposition of copper are repeated, and the roughened plating layer 35 is formed.
  • the number of protrusions 36 in the roughening plating layer 35 can be adjusted depending on the surface properties of the plate body 31 (and the metal substrate 11) forming the roughened plating layer 35 and various plating conditions (pulse application time, pulse waveform (precipitation amount/dissolution amount ratio), pulse frequency),
  • the number of protrusions 36 in the roughening plating layer 35 can be adjusted.
  • the size of the protrusions 36 can be increased by lengthening the pulse application time or by adjusting the deposition/dissolution ratio of the pulse waveform.
  • the pulse frequency the number of protrusions 36 can be increased.
  • a resin composition 22 containing boron nitride as a filler, an epoxy resin as a thermosetting resin, and a curing agent is provided on one surface (upper surface in FIG. 4) of the metal substrate 11 .
  • the resin composition 22 is formed in a sheet shape.
  • a metal plate material 30 to be the circuit layer 13 is arranged on one surface (upper surface in FIG. 4) of the resin composition 22 .
  • the resin composition 22 is laminated so as to be in direct contact with the surfaces of the metal substrate 11 and the metal plate material 30 on which the roughened plating layer 35 is formed.
  • thermocompression bonding step S04 Next, the laminated metal substrate 11, the resin composition 22, and the metal plate material 30 are heated while being pressed in the lamination direction to cure the resin composition 22 and form the insulating resin layer 12.
  • the insulating resin layer 12 and the insulating resin layer 12 and the metal plate material 30 are joined.
  • the conditions of this thermocompression bonding step S04 are as follows: heating temperature in the range of 100° C. or more and 400° C. or less, holding time at the heating temperature in the range of 30 minutes or more and 90 minutes or less, and pressure in the stacking direction of 1 MPa or more and 100 MPa or less. is preferably within the range of
  • circuit pattern forming step S05 Next, the metal plate material 30 joined to the insulating resin layer 12 is etched to form a circuit pattern, and the circuit layer 13 is obtained.
  • the insulating circuit board 10 of the present embodiment is manufactured.
  • a heat sink 41 is joined to the other surface of the metal substrate 11 of the insulated circuit substrate 10 .
  • the metal substrate 11 and the heat sink 41 are joined together via a solder material.
  • semiconductor element bonding step S07 the semiconductor element 3 is bonded to the circuit layer 13 of the insulating circuit board 10 .
  • the circuit layer 13 and the semiconductor element 3 are joined via a solder material.
  • the KAM value is Since the area ratio of the region of 1.0 or more is set to 10% or less, the residual stress of the surface layer is kept low, and the roughened plating layer 35 protrudes toward the side opposite to the plate body 31.
  • the protrusions 36 can be formed uniformly and densely. Then, the Sdr (developed interface area ratio) of the outermost surface of the roughened plating layer 35 is 20% or more, or the R (developed interface line length ratio) of the outermost surface of the roughened plating layer 35 is 40% or more.
  • the protrusions 36 are formed uniformly and densely, and the protrusions 36 are engaged with the insulating resin layer 12 laminated on the roughened plating layer 35 side, thereby forming the circuit layer 13 (metal plate material 30). and the insulating resin layer 12, and the adhesiveness between the metal substrate 11 (metal plate material 30) and the insulating resin layer 12 can be improved.
  • the convex portion 36 protruding toward the opposite side of the plate body 31 includes a widened portion 36a whose width gradually increases toward the tip side in the direction of protrusion,
  • the insulating resin layer 12 laminated on the roughened plated layer 35 side is reliably engaged with the protrusions 36 , and the adhesion between the circuit layer 13 (metal plate material 30 ) and the insulating resin layer 12 and the metal substrate 11 It is possible to further improve the adhesion between (the metal plate material 30) and the insulating resin layer 12.
  • the plate body 31 is made of copper or a copper alloy, it is possible to form the circuit layer 13 (metal plate material 30) with excellent electrical conductivity and thermal conductivity.
  • the present invention is not limited to this, and can be modified as appropriate without departing from the technical requirements of the invention.
  • the insulating circuit board is manufactured by the manufacturing method of the insulating circuit board shown in FIGS. 3 and 4, but it is not limited to this.
  • the metal plate material 30 forming the circuit layer 13 has been described as being made of oxygen-free copper, but is not limited to this, and may be made of other copper or copper alloy. It may be made of other metal such as aluminum or aluminum alloy. Furthermore, it may have a structure in which a plurality of metals are laminated.
  • the metal substrate 11 is described as being made of oxygen-free copper, but is not limited to this, and may be made of other copper or copper alloy. Alternatively, it may be made of other metals such as aluminum or an aluminum alloy. Furthermore, it may have a structure in which a plurality of metals are laminated.
  • Metal substrate 11 may be a heat sink. That is, the heat sink may be directly bonded to the other surface of the insulating resin layer 12 .
  • a power module is configured by mounting a semiconductor element on an insulated circuit board, but it is not limited to this.
  • an LED module may be configured by mounting an LED element on the circuit layer of the insulating circuit board, or a thermoelectric module may be configured by mounting a thermoelectric element on the circuit layer of the insulating circuit board.
  • both the circuit layer 13 and the metal substrate 11 are described as being formed by bonding the metal plate material 30 according to the present embodiment to the surface of the insulating resin layer 12, but the present invention is not limited to this. never If either one of the circuit layer 13 and the metal substrate 11 is formed by bonding the metal plate material 30 according to the present embodiment to the surface of the insulating resin layer 12, the effects described in the present embodiment can be obtained. . In particular, when the metal substrate 11 is the metal plate material 30 according to the present embodiment, it is easier to obtain the effects described in the present embodiment than when the circuit layer 13 is the metal plate material 30 according to the present embodiment. .
  • a metal substrate (40 mm ⁇ 40 mm ⁇ 2 mm thick) made of a rolled sheet of oxygen-free copper and a metal plate material (40 mm ⁇ 40 mm ⁇ 0.5 mm thickness) to be the circuit layer are prepared, and the insulating resin of these metal substrates and metal plate materials
  • a stress reduction step is performed as shown in Table 1 on the surface to be bonded to the layer, and then a roughened plating layer is formed by the DC electroplating method and the PR pulse electroplating method described in the above embodiment. formed.
  • Table 1 shows the plating conditions.
  • the application time of PR pulse electrolysis in Table 1 is the total application time of the pulse current.
  • a sheet material (40 mm ⁇ 40 mm ⁇ 0.15 mm thick) of a resin composition containing an epoxy resin containing boron nitride as a filler was placed on the surface of the metal substrate on which the roughened plating layer was formed. Further, a metal plate material to be a circuit layer was laminated on one surface of the resin composition sheet material so that the surface on which the roughened plating layer was formed faced the resin composition sheet material side.
  • the metal substrate, the sheet material of the resin composition, and the metal plate material laminated as described above are heated while being pressed in the stacking direction, and the resin composition is cured to form an insulating resin layer, and the metal substrate and the insulating resin are formed.
  • the layer, and the insulating resin layer and the metal plate were joined to obtain an insulated circuit board.
  • the pressure in the stacking direction was 10 MPa
  • the heating temperature was 180° C.
  • the holding time at the heating temperature was 60 minutes.
  • the metal plate material and the insulated circuit board thus obtained were evaluated for the following items.
  • the surface perpendicular to the rolling width direction of the metal plate material, that is, the TD surface (Transverse direction) and the surface perpendicular to the rolling direction, that is, the RD surface (Rolling direction) are used as observation surfaces, with an EBSD measurement device and OIM analysis software, KAM values were measured as follows.
  • the observation surface was mechanically polished using water-resistant abrasive paper.
  • cross-sectional ion processing was performed using a cross-sectional ion processing device (IM-4000 manufactured by Hitachi High-Tech Co., Ltd.).
  • IM-4000 manufactured by Hitachi High-Tech Co., Ltd.
  • EBSD detector TSL/EDAX Hikari
  • the electron beam acceleration voltage is 15 kV
  • the measurement interval is 0.1 ⁇ m steps
  • the plating surface is observed on the observation surface.
  • the EBSD pattern was measured over a range of 7 ⁇ m wide perpendicular to the plated surface and 30 ⁇ m wide parallel to the plating surface.
  • the orientation difference of each crystal grain is analyzed using analysis software (EDAX/TSL OIM Data Analysis ver.7), and the boundary where the orientation difference between adjacent pixels is 5° or more is regarded as a grain boundary. , the KAM value near the plating surface (width 11 ⁇ m) was obtained.
  • the IQ value (Image Quality value) in this measurement is 600 or less in order to remove the area that is not the copper plating part generated due to the unevenness of the roughened plating layer surface from the data in the measurement range. Measurement points are excluded.
  • the IQ value is a relative index that indicates the clarity of the EBSD pattern, but it varies greatly depending on the measurement conditions, detector, substance, and condition of the sample observation surface. After confirming that the range was excluded, I adjusted the IQ value.
  • the contour of the metal piece independent from the metal plate and present in the insulating resin layer and the contour of the resin piece independent from the insulating resin layer and present in the metal plate are removed.
  • the obtained image was analyzed, and the developed interface line length ratio R was calculated.
  • the average value of the developed interface line length ratio R in the cross section parallel to the longitudinal direction of the insulating circuit board and the developed interface line length ratio R in the cross section perpendicular to the longitudinal direction of the insulating circuit board is calculated as the developed interface of the roughening plating layer.
  • a line length ratio R was used.
  • the insulated circuit board described above was placed in a thermo-hygrostat (85° C. temperature, 85% humidity) and held for 3 days. After that, it was placed in a heating furnace and subjected to reflow treatment at 290° C. for 10 minutes.
  • the partial discharge inception voltage and dielectric breakdown voltage (dielectric withstand voltage) of the circuit layer and the insulating resin layer were evaluated as follows. As shown in FIG. 5, the metal substrate 11 was placed on the base plate 61, the probes 62 were brought into contact with the circuit layer 13, and the partial discharge was evaluated.
  • the test atmosphere was Fluorinert (tm) FC-770 manufactured by 3M. Then, the voltage was increased with a step profile (retention time: 60 seconds) in steps of 0.5 kV, and the voltage at which the average discharge charge amount was 5 pC or more was defined as the partial discharge inception voltage. The voltage at which dielectric breakdown occurred (the voltage at which the leakage current became 10 mA or more) was taken as the dielectric breakdown voltage. Table 2 shows the evaluation results. Partial discharge starts due to small peeling voids, and dielectric breakdown occurs when a voltage above a certain level is applied. The partial discharge inception voltage is the value resulting from small flaking.
  • Comparative Examples 1 to 5 the DC electroplating method was performed without reducing the residual stress of the plate body, and then the PR pulse electroplating method was performed to form a roughened plating layer.
  • the area ratio of the region having a KAM value of 1.0 or more in the region of 6 ⁇ m in the thickness direction from the outermost layer of the roughened plating layer exceeded 10%, and the Sdr (developed interface area ratio) was less than 20%.
  • the partial discharge inception voltage after moisture absorption reflow was low, and the adhesion between the circuit layer (metal substrate) and the insulating resin layer was insufficient.
  • Examples 1 to 12 of the present invention the residual stress of the plate body was reduced by chemical polishing, DC electroplating was performed, and then PR pulse electroplating was performed to form a roughened plating layer.
  • the area ratio of the region where the KAM value is 1.0 or more in the region of 6 ⁇ m in the thickness direction from the outermost layer of the roughened plating layer is 10% or less, and the Sdr (development interface) of the outermost surface of the roughened plating layer area ratio) was 20% or more.
  • the partial discharge inception voltage after moisture absorption reflow was high, and the circuit layer (metal substrate) and the insulating resin layer were sufficiently adhered.
  • the metal plate material of this embodiment has excellent adhesion to laminated resin members. Therefore, the laminate and the insulating circuit board in which the metal plate material and the resin member are laminated according to the present embodiment are suitably applied to power modules, LED modules, and thermoelectric modules.

Abstract

This metal plate (30) comprises a plate body (31), and a roughened plating layer (35) formed on the outermost layer of the plate body (31). A protuberance (36) projecting away from the plate body (31) is formed on the roughened plating layer (35). The area ratio of a region having a KAM value of 1.0 or greater in a region extending 6 µm in the thickness direction from the outermost layer of the roughened plating layer (35) is 10% or less, and either the developed interfacial area ratio (Sdr) of the outermost surface of the roughened plating layer (35) is 20% or greater, or the R (developed interfacial linear length ratio) of the outermost surface of the roughened plating layer (35) is 40% or greater.

Description

金属板材、積層体、および、絶縁回路基板Metal sheets, laminates, and insulated circuit boards
　この発明は、金属板材、樹脂部材と金属板材が積層された構造の積層体、および、絶縁回路基板に関するものである。
　本願は、２０２１年３月２６日に、日本に出願された特願２０２１－０５３４４９号に基づき優先権を主張し、その内容をここに援用する。 TECHNICAL FIELD The present invention relates to a metal plate material, a laminate having a structure in which a resin member and a metal plate material are laminated, and an insulated circuit board.
This application claims priority based on Japanese Patent Application No. 2021-053449 filed in Japan on March 26, 2021, the content of which is incorporated herein.
　パワーモジュール、ＬＥＤモジュールおよび熱電モジュールにおいては、絶縁層の一方の面に導電材料からなる回路層を形成した絶縁回路基板に、パワー半導体素子、ＬＥＤ素子および熱電素子が接合された構造とされている。なお、絶縁層としては、セラミックスを用いたものや絶縁樹脂を用いたものが提案されている。
　ここで、絶縁樹脂層を備えた絶縁回路基板として、例えば特許文献１には、金属ベース回路基板が提案されている。また、特許文献２には、多層配線基板が提案されている。 A power module, an LED module, and a thermoelectric module have a structure in which a power semiconductor element, an LED element, and a thermoelectric element are joined to an insulating circuit board in which a circuit layer made of a conductive material is formed on one side of an insulating layer. . As the insulating layer, one using ceramics and one using insulating resin have been proposed.
Here, as an insulating circuit board having an insulating resin layer, for example, Patent Document 1 proposes a metal base circuit board. Further, Patent Document 2 proposes a multilayer wiring board.
　特許文献１に記載された金属ベース回路基板においては、金属基板上に絶縁樹脂層が形成され、この絶縁樹脂層上に回路パターンを有する回路層が形成されている。ここで、絶縁樹脂層は、熱硬化型樹脂であるエポキシ樹脂で構成されており、回路層は、銅箔で構成されている。
　この金属ベース回路基板においては、回路層上に半導体素子が接合され、金属基板の絶縁樹脂層とは反対側の面にヒートシンクが配設されており、半導体素子で発生した熱をヒートシンク側に伝達して放熱する構造とされている。 In the metal-based circuit board disclosed in Patent Document 1, an insulating resin layer is formed on the metal board, and a circuit layer having a circuit pattern is formed on the insulating resin layer. Here, the insulating resin layer is made of epoxy resin, which is a thermosetting resin, and the circuit layer is made of copper foil.
In this metal base circuit board, a semiconductor element is bonded onto the circuit layer, and a heat sink is provided on the opposite side of the metal substrate to the insulating resin layer, so that heat generated by the semiconductor element is transmitted to the heat sink side. The structure is designed to dissipate heat by
　また、特許文献２に記載された多層配線基板は、以下の方法によって製造されている。樹脂フィルムに接着した金属箔に対してエッチング処理することで金属箔の表面粗さ（Ｒａ）を０．２μｍ以上とし、さらに回路パターン状にエッチング処理して配線回路層を形成する。樹脂フィルムの表面に形成された配線回路層を、軟質の絶縁シートの表面に圧力を加えながら埋設し、絶縁回路層を絶縁シートの表面に転写させる。このようにして得られた複数の絶縁シートを積層して一括して加熱硬化する。 Also, the multilayer wiring board described in Patent Document 2 is manufactured by the following method. By etching the metal foil adhered to the resin film, the surface roughness (Ra) of the metal foil is set to 0.2 μm or more, and the wiring circuit layer is formed by etching in a circuit pattern. The wiring circuit layer formed on the surface of the resin film is embedded in the surface of the soft insulating sheet while applying pressure to transfer the insulating circuit layer to the surface of the insulating sheet. A plurality of insulating sheets thus obtained are laminated and collectively heat-cured.
　ところで、絶縁樹脂層に金属板等を接合して回路層を形成した構造の絶縁回路基板においては、使用時に、絶縁樹脂層と回路層（金属板）の剥離や絶縁樹脂層と金属基板（金属板）の剥離が生じないように、絶縁樹脂層と回路層（金属板）の密着性や絶縁樹脂層と金属基板（金属板）の密着性を確保する必要がある。
　ここで、特許文献１に記載された金属ベース回路基板においては、絶縁樹脂層と回路層との密着性や絶縁樹脂層と金属基板との密着性を向上させることは考慮されておらず、使用時に、絶縁樹脂層と回路層（金属板）の剥離や絶縁樹脂層と金属基板（金属板）の剥離が生じるおそれがあった。 By the way, in an insulated circuit board having a structure in which a circuit layer is formed by bonding a metal plate or the like to an insulating resin layer, during use, the insulating resin layer and the circuit layer (metal plate) may peel off, or the insulating resin layer and the metal substrate (metallic plate) may peel off. It is necessary to secure adhesion between the insulating resin layer and the circuit layer (metal plate) and adhesion between the insulating resin layer and the metal substrate (metal plate) so as not to cause peeling of the substrate.
Here, in the metal base circuit board described in Patent Document 1, it is not considered to improve the adhesion between the insulating resin layer and the circuit layer and the adhesion between the insulating resin layer and the metal substrate. Occasionally, the insulating resin layer and the circuit layer (metal plate) may be separated, or the insulating resin layer and the metal substrate (metal plate) may be separated.
　一方、特許文献２に記載された多層配線基板においては、配線回路層の表面粗さ（Ｒａ）を０．２μｍ以上として絶縁シートに埋設させることで、絶縁シートと配線回路層との密着性の向上を図っている。
　ここで、配線回路層の表面粗さ（Ｒａ）を０．２μｍ以上とした場合であっても、回路層側から突出する凸部が均一かつ緻密に形成されていない場合には、絶縁シートとの密着性が確保できないおそれがあった。 On the other hand, in the multilayer wiring board described in Patent Document 2, the surface roughness (Ra) of the wiring circuit layer is set to 0.2 μm or more and embedded in the insulating sheet, thereby improving the adhesion between the insulating sheet and the wiring circuit layer. We are trying to improve.
Here, even when the surface roughness (Ra) of the wiring circuit layer is set to 0.2 μm or more, if the protrusions protruding from the circuit layer side are not uniformly and densely formed, the insulating sheet and the There was a risk that the adhesion of the film could not be ensured.
特開２０１５－２０７６６６号公報JP 2015-207666 A 特開２０００－０７７８５０号公報JP-A-2000-077850
　この発明は、前述した事情に鑑みてなされたものであって、積層した樹脂部材との密着性に優れる金属板材、この金属板材と樹脂部材とが積層された積層体、および、絶縁回路基板を提供することを目的とする。 The present invention has been made in view of the circumstances described above, and provides a metal plate material having excellent adhesion to a laminated resin member, a laminate in which the metal plate material and the resin member are laminated, and an insulated circuit board. intended to provide
　前述の課題を解決するために、本発明者らが鋭意検討した結果、金属板にパルスめっきを行うことにより、複数の凸部を形成した粗化めっき層を形成できることが確認された。そして、この粗化めっき層を形成する際に、金属板の残留応力を低減することで、凸部を均一かつ緻密に形成することが可能となるとの知見を得た。 In order to solve the above-mentioned problems, the inventors of the present invention conducted extensive studies, and as a result, it was confirmed that by performing pulse plating on a metal plate, it was possible to form a roughened plating layer in which a plurality of convex portions were formed. Then, the inventors have found that by reducing the residual stress of the metal plate when forming the roughened plating layer, it is possible to form the convex portions uniformly and precisely.
　本発明は、上述の知見を基になされたものであって、本発明の一態様に係る金属板材は、板本体と、この板本体の最表層に形成された粗化めっき層と、を有し、前記粗化めっき層には、前記板本体とは反対側に向けて突出する凸部が形成されており、前記粗化めっき層の最表層から厚さ方向に６μｍの領域において、ＫＡＭ値が１．０以上である領域の面積率が１０％以下とされており、前記粗化めっき層の最表面のＳｄｒ（展開界面面積率）が２０％以上であるか、または前記粗化めっき層の最表面のＲ（展開界面線長率）が４０％以上であることを特徴としている。 The present invention was made based on the above findings, and a metal plate material according to one aspect of the present invention has a plate body and a roughened plating layer formed on the outermost layer of the plate body. Then, the roughened plating layer has a convex portion that protrudes toward the opposite side of the plate body, and the KAM value is is 1.0 or more, and the area ratio of the region is 10% or less, and the Sdr (development interface area ratio) of the outermost surface of the roughening plating layer is 20% or more, or the roughening plating layer The outermost surface R (ratio of developed interface line length) is 40% or more.
　なお、ＫＡＭ（Ｋｅｒｎｅｌ Ａｖｅｒａｇｅ Ｍｉｓｏｒｉｅｎｔａｔｉｏｎ）値は、ある結晶粒内の１つのピクセルとそれを取り囲むピクセル間との方位差を平均値化することで算出される値である。ピクセルの形状は正六角形のため、近接次数を１とする場合（１ｓｔ）、隣接する六つのピクセルとの方位差の平均値がＫＡＭ値として算出される。ただし隣接する測定点との間に結晶粒界がある場合はＫＡＭ値の計算には含まれない。
　このＫＡＭ値を用いることで、局所的な方位差、すなわち、ひずみの分布を可視化することが可能となる。このＫＡＭ値が高い領域は、加工時に導入されたひずみが高い領域であり、残留応力が高くなる。 The KAM (Kernel Average Misorientation) value is a value calculated by averaging the orientation difference between one pixel in a certain crystal grain and the pixels surrounding it. Since the shape of the pixel is a regular hexagon, when the degree of proximity is 1 (1st), the average value of the orientation difference with six adjacent pixels is calculated as the KAM value. However, if there is a crystal grain boundary between adjacent measurement points, it is not included in the calculation of the KAM value.
By using this KAM value, it becomes possible to visualize the distribution of local misorientation, that is, strain. A region with a high KAM value is a region with a high strain introduced during processing, resulting in a high residual stress.
　この構成の金属板材によれば、前記粗化めっき層の最表層から厚さ方向に６μｍの領域において、ＫＡＭ値が１．０以上である領域の面積率が１０％以下とされているので、表層部分の残留応力が低く抑えられおり、粗化めっき層において、板本体とは反対側に向けて突出する凸部を均一かつ緻密に形成することができる。
　そして、前記粗化めっき層の最表面のＳｄｒ（展開界面面積率）が２０％以上でるか、または前記粗化めっき層の最表面のＲ（展開界面線長率）が４０％以上であるので、この粗化めっき層側に積層した樹脂部材との密着性を向上させることが可能となる。 According to the metal plate material having this configuration, the area ratio of the region having a KAM value of 1.0 or more is 10% or less in the region of 6 μm in the thickness direction from the outermost layer of the roughened plating layer. Residual stress in the surface layer portion is kept low, and in the roughened plating layer, convex portions protruding toward the side opposite to the plate body can be uniformly and precisely formed.
Further, since the Sdr (development interface area ratio) of the outermost surface of the roughened plating layer is 20% or more, or the R (development interface line length ratio) of the outermost surface of the roughening plating layer is 40% or more. , it is possible to improve the adhesion with the resin member laminated on the roughened plating layer side.
　ここで、本発明の一態様に係る金属板材においては、前記凸部は、突出方向の先端側に向かうにしたがい漸次幅が広くなる拡幅部を備えていることが好ましい。
　この場合、前記板本体とは反対側に向けて突出する凸部が、突出方向の先端側に向かうにしたがい漸次幅が広くなる拡幅部を備えているので、前記粗化めっき層側に積層した樹脂部材が凸部と確実に係合されることになり、樹脂部材との密着性を向上させることが可能となる。 Here, in the metal plate material according to the aspect of the present invention, it is preferable that the convex portion includes a widened portion whose width gradually increases toward the tip end side in the projecting direction.
In this case, since the protruding portion protruding toward the opposite side of the plate body has a widened portion whose width gradually increases toward the tip side in the protruding direction, it is laminated on the roughened plating layer side. The resin member is reliably engaged with the convex portion, and it is possible to improve the adhesion with the resin member.
　また、本発明の一態様に係る金属板材においては、板本体が銅又は銅合金で構成されていることが好ましい。
　この場合、板本体が銅又は銅合金で構成されているので、電気伝導性および熱伝導性に優れている。 Moreover, in the metal plate material according to one aspect of the present invention, the plate body is preferably made of copper or a copper alloy.
In this case, since the plate body is made of copper or a copper alloy, it has excellent electrical conductivity and thermal conductivity.
　本発明の一態様に係る積層体は、上述の金属板材の板面に、樹脂部材が積層された積層体であって、前記樹脂部材と前記金属板材との接合界面においては、前記金属板材の前記凸部に前記樹脂部材が係合していることを特徴としている。 A laminate according to an aspect of the present invention is a laminate in which a resin member is laminated on the plate surface of the above-described metal plate material, and at a joint interface between the resin member and the metal plate material, the metal plate material The resin member is engaged with the convex portion.
　この構成の積層体によれば、凸部が形成された金属板材の板面（粗化めっき層）に樹脂部材が積層されており、前記樹脂部材と前記金属板材との接合界面においては、前記金属板材の前記凸部と前記樹脂部材とが係合していることから、樹脂部材と金属板材との密着性を向上させることができる。
　なお、積層体は、上述の金属板材と、前記金属板材の粗化めっき層側の板面に積層された樹脂部材を有すると言うこともできる。 According to the laminated body having this configuration, the resin member is laminated on the plate surface (roughened plating layer) of the metal plate material on which the protrusions are formed, and at the joint interface between the resin member and the metal plate material, the Since the convex portion of the metal plate material and the resin member are engaged with each other, it is possible to improve the adhesion between the resin member and the metal plate material.
In addition, it can also be said that the laminated body includes the metal plate material described above and a resin member laminated on the plate surface of the metal plate material on the roughened plating layer side.
　本発明の一態様に係る絶縁回路基板は、絶縁樹脂層と、前記絶縁樹脂層の一方の面に形成された回路層と、を備えた絶縁回路基板であって、前記回路層は、上述の金属板材を、前記絶縁樹脂層の一方の面に接合することにより形成されており、前記絶縁樹脂層と前記回路層との接合界面においては、前記金属板材の前記凸部に前記絶縁樹脂層が係合していることを特徴としている。 An insulated circuit board according to an aspect of the present invention is an insulated circuit board including an insulating resin layer and a circuit layer formed on one surface of the insulating resin layer, wherein the circuit layer comprises the above-described The insulating resin layer is formed by bonding a metal plate material to one surface of the insulating resin layer, and the insulating resin layer is formed on the convex portion of the metal plate material at the bonding interface between the insulating resin layer and the circuit layer. characterized by being engaged.
　この構成の絶縁回路基板によれば、凸部が形成された金属板材の板面（粗化めっき層）を絶縁樹脂層の一方の面に接合することにより回路層が形成されており、前記絶縁樹脂層と前記回路層との接合界面においては、前記回路層（銅部材）の前記凸部に前記絶縁樹脂層が係合していることから、回路層と絶縁樹脂層との密着性を向上させることができる。 According to the insulating circuit board having this configuration, the circuit layer is formed by bonding the plate surface (roughened plating layer) of the metal plate on which the protrusions are formed to one surface of the insulating resin layer. At the joint interface between the resin layer and the circuit layer, the insulating resin layer is engaged with the convex portion of the circuit layer (copper member), so that the adhesion between the circuit layer and the insulating resin layer is improved. can be made
　本発明の他の態様に係る絶縁回路基板は、絶縁樹脂層と、前記絶縁樹脂層の一方の面に形成された回路層と、前記絶縁樹脂層の他方の面に形成された金属基板と、を備えた絶縁回路基板であって、前記回路層及び前記金属基板のいずれか一方又は両方は、上述の金属板材を、前記絶縁樹脂層の面に接合することにより形成されており、前記絶縁樹脂層と前記回路層との接合界面、及び前記絶縁樹脂層と前記金属基板との接合界面のうち、いずれか一方又は両方においては、前記金属板材の前記凸部に前記絶縁樹脂層が係合していることを特徴としている。 An insulated circuit board according to another aspect of the present invention comprises an insulating resin layer, a circuit layer formed on one surface of the insulating resin layer, a metal substrate formed on the other surface of the insulating resin layer, , wherein one or both of the circuit layer and the metal substrate are formed by bonding the metal plate material described above to the surface of the insulating resin layer, and the insulating resin The insulating resin layer is engaged with the convex portion of the metal plate at one or both of the bonding interface between the layer and the circuit layer and the bonding interface between the insulating resin layer and the metal substrate. It is characterized by
　この構成の絶縁回路基板によれば、凸部が形成された金属板材の板面（粗化めっき層）を絶縁樹脂層の面に接合することにより、回路層及び金属基板のいずれか一方又は両方が形成されている。前記絶縁樹脂層と前記回路層との接合界面、及び前記絶縁樹脂層と前記金属基板との接合界面のうち、いずれか一方又は両方においては、前記金属板材の前記凸部に前記絶縁樹脂層が係合している。このため、回路層と絶縁樹脂層との密着性又は金属基板と絶縁樹脂層との密着性を向上させることができる。 According to the insulated circuit board having this configuration, by bonding the plate surface (roughened plating layer) of the metal plate on which the protrusions are formed to the surface of the insulating resin layer, one or both of the circuit layer and the metal substrate is formed. At one or both of the bonding interface between the insulating resin layer and the circuit layer and the bonding interface between the insulating resin layer and the metal substrate, the insulating resin layer is formed on the convex portion of the metal plate material. engaged. Therefore, the adhesion between the circuit layer and the insulating resin layer or the adhesion between the metal substrate and the insulating resin layer can be improved.
　本発明の一態様及び他の態様によれば、積層した樹脂部材との密着性に優れる金属板材、この金属板材と樹脂部材とが積層された積層体、および、絶縁回路基板を提供することが可能となる。 According to one aspect and another aspect of the present invention, it is possible to provide a metal plate material having excellent adhesion to a laminated resin member, a laminate in which the metal plate material and the resin member are laminated, and an insulated circuit board. It becomes possible.
本発明の実施形態に係る絶縁回路基板を備えたパワーモジュールの概略説明図である。1 is a schematic explanatory diagram of a power module provided with an insulated circuit board according to an embodiment of the present invention; FIG. 本発明の実施形態に係る金属板材の説明図であり、詳細には表面近傍の観察写真である。FIG. 2 is an explanatory diagram of the metal plate material according to the embodiment of the present invention, and more specifically, an observation photograph of the vicinity of the surface. 本発明の実施形態に係る金属板材の説明図であり、詳細には係合凸部の模式図である。FIG. 2 is an explanatory diagram of the metal plate material according to the embodiment of the present invention, and more specifically, a schematic diagram of an engaging projection. 本発明の実施形態に係る絶縁回路基板の製造方法を示すフロー図である。1 is a flowchart showing a method for manufacturing an insulated circuit board according to an embodiment of the present invention; FIG. 図３に示す絶縁回路基板の製造方法の概略説明図である。FIG. 4 is a schematic explanatory view of a method for manufacturing the insulated circuit board shown in FIG. 3; 実施例において絶縁回路基板の絶縁性（絶縁耐圧）を評価する試験装置の概略説明図である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic illustration of a testing apparatus for evaluating the insulation (withstand voltage) of an insulated circuit board in Examples.
　以下に、本発明の実施形態である金属板材、積層体、および、絶縁回路基板について、添付した図面を参照して説明する。
　図１に、本発明の実施形態である絶縁回路基板１０およびこの絶縁回路基板１０を用いたパワーモジュール１を示す。
　本実施形態に係る絶縁回路基板１０は、絶縁樹脂層１２と、絶縁樹脂層１２の一方の面に形成された回路層１３と、絶縁樹脂層１２の他方の面に形成された金属基板１１と、を備える。回路層１３と金属基板１１の両者は、本実施形態に係る金属板材３０を絶縁樹脂層１２の面に接合することにより形成されている。
　絶縁樹脂層１２は、樹脂部材の一例であり、本実施形態に係る絶縁回路基板１０は、本実施形態に係る積層体であると言うこともできる。本実施形態に係る積層体は、本実施形態に係る金属板材３０と、樹脂部材を有し、金属板材３０の板面（粗化めっき層）に、樹脂部材が積層されている。言い換えると、金属板材３０は、樹脂部材の面に接合している。 EMBODIMENT OF THE INVENTION Below, the metal plate material, laminated body, and insulated circuit board which are embodiment of this invention are demonstrated with reference to attached drawings.
FIG. 1 shows an insulated circuit board 10 and a power module 1 using the insulated circuit board 10 according to an embodiment of the present invention.
The insulating circuit board 10 according to this embodiment includes an insulating resin layer 12, a circuit layer 13 formed on one surface of the insulating resin layer 12, and a metal substrate 11 formed on the other surface of the insulating resin layer 12. , provided. Both the circuit layer 13 and the metal substrate 11 are formed by bonding the metal plate material 30 according to this embodiment to the surface of the insulating resin layer 12 .
The insulating resin layer 12 is an example of a resin member, and it can also be said that the insulating circuit board 10 according to this embodiment is a laminate according to this embodiment. The laminate according to this embodiment includes the metal plate material 30 according to this embodiment and a resin member, and the resin member is laminated on the plate surface (roughened plating layer) of the metal plate material 30 . In other words, the metal plate material 30 is bonded to the surface of the resin member.
　図１に示すパワーモジュール１は、絶縁回路基板１０と、この絶縁回路基板１０の一方の面（図１において上面）に第１はんだ層２を介して接合された半導体素子３と、絶縁回路基板１０の他方側（図１において下側）に第２はんだ層４２を介して接合されたヒートシンク４１と、を備えている。 The power module 1 shown in FIG. 1 includes an insulating circuit board 10, a semiconductor element 3 bonded to one surface (upper surface in FIG. 1) of the insulating circuit board 10 via a first solder layer 2, and an insulating circuit board. 10 (lower side in FIG. 1) and a heat sink 41 bonded via a second solder layer 42 .
　半導体素子３は、Ｓｉ等の半導体材料で構成されている。絶縁回路基板１０と半導体素子３とを接合する第１はんだ層２は、例えばＳｎ－Ａｇ系、Ｓｎ－Ｃｕ系、Ｓｎ－Ｉｎ系、若しくはＳｎ－Ａｇ－Ｃｕ系のはんだ材（いわゆる鉛フリーはんだ材）とされている。 The semiconductor element 3 is made of a semiconductor material such as Si. The first solder layer 2 that joins the insulating circuit board 10 and the semiconductor element 3 is made of, for example, a Sn--Ag-based, Sn--Cu-based, Sn--In-based, or Sn--Ag--Cu-based solder material (so-called lead-free solder). material).
　ヒートシンク４１は、絶縁回路基板１０側の熱を放散するためのものである。ヒートシンク４１は、熱伝導性が良好な銅又は銅合金、アルミニウム又はアルミニウム合金等で構成されている。本実施形態においては、無酸素銅からなる放熱板とされている。なお、ヒートシンク４１の厚さは、３ｍｍ以上１０ｍｍ以下の範囲内に設定されている。
　ここで、絶縁回路基板１０とヒートシンク４１とは、第２はんだ層４２を介して接合されている。この第２はんだ層４２は、上述の第１はんだ層２と同様の構成とすることができる。 The heat sink 41 is for dissipating heat from the insulating circuit board 10 side. The heat sink 41 is made of copper, a copper alloy, aluminum, an aluminum alloy, or the like, which has good thermal conductivity. In this embodiment, the radiator plate is made of oxygen-free copper. The thickness of the heat sink 41 is set within a range of 3 mm or more and 10 mm or less.
Here, the insulating circuit board 10 and the heat sink 41 are bonded via the second solder layer 42 . The second solder layer 42 can have the same configuration as the first solder layer 2 described above.
　そして、本実施形態である絶縁回路基板１０は、図１に示すように、金属基板１１と、金属基板１１の一方の面（図１において上面）に形成された絶縁樹脂層１２と、絶縁樹脂層１２の一方の面（図１において上面）に形成された回路層１３と、を備えている。 As shown in FIG. 1, the insulating circuit board 10 of the present embodiment includes a metal substrate 11, an insulating resin layer 12 formed on one surface (upper surface in FIG. 1) of the metal substrate 11, and an insulating resin and a circuit layer 13 formed on one surface of the layer 12 (upper surface in FIG. 1).
　金属基板１１は、絶縁回路基板１０に搭載された半導体素子３において発生した熱を面方向に拡げることによって、放熱特性を向上させる作用を有する。このため、金属基板１１は、熱伝導性に優れた金属、例えば銅又は銅合金、アルミニウム又はアルミニウム合金で構成されている。本実施形態では、無酸素銅の圧延板で構成されている。また、金属基板１１の厚さは、０．０５ｍｍ以上３ｍｍ以下の範囲内に設定されており、本実施形態では、２．０ｍｍに設定されている。 The metal substrate 11 has the effect of improving the heat dissipation characteristics by spreading the heat generated in the semiconductor element 3 mounted on the insulated circuit substrate 10 in the plane direction. Therefore, the metal substrate 11 is made of a metal with excellent thermal conductivity, such as copper or a copper alloy, aluminum or an aluminum alloy. In this embodiment, it is made of a rolled sheet of oxygen-free copper. The thickness of the metal substrate 11 is set within a range of 0.05 mm or more and 3 mm or less, and is set to 2.0 mm in this embodiment.
　絶縁樹脂層１２は、回路層１３と金属基板１１との間の電気的接続を防止するものであり、絶縁性を有する熱硬化型樹脂で構成されている。
　本実施形態では、絶縁樹脂層１２の強度を確保するとともに、熱伝導性を確保するために、フィラーを含有する熱硬化型樹脂が用いられている。ここで、フィラーとしては、例えばアルミナ、窒化ホウ素、窒化アルミニウム等を用いることができる。また、熱硬化型樹脂としては、エポキシ樹脂、ポリイミド樹脂等を用いることができる。本実施形態では、絶縁樹脂層１２は、フィラーとして窒化ホウ素を含有するエポキシ樹脂で構成されている。また、絶縁樹脂層１２の厚さは、２０μｍ以上２５０μｍ以下の範囲内とされており、本実施形態では、１５０μｍとされている。 The insulating resin layer 12 prevents electrical connection between the circuit layer 13 and the metal substrate 11, and is made of an insulating thermosetting resin.
In this embodiment, a thermosetting resin containing a filler is used in order to ensure the strength of the insulating resin layer 12 and to ensure thermal conductivity. Here, for example, alumina, boron nitride, aluminum nitride, or the like can be used as the filler. Moreover, an epoxy resin, a polyimide resin, etc. can be used as a thermosetting resin. In this embodiment, the insulating resin layer 12 is made of an epoxy resin containing boron nitride as a filler. Further, the thickness of the insulating resin layer 12 is set within a range of 20 μm or more and 250 μm or less, and is set to 150 μm in this embodiment.
　回路層１３は、図４に示すように、絶縁樹脂層１２の一方の面（図４において上面）に、本実施形態である金属板材３０が接合され、回路パターンが形成されている。詳細には、絶縁樹脂層１２の一方の面と、金属板材３０の粗化めっき層３５側の面とが接合されている。なお、まず金属板材３０に回路パターンを形成し、次いで回路パターンが形成された金属板材３０を絶縁樹脂層１２の一方の面に接合してもよい。
　この回路層１３においては、回路パターンが形成されており、その一方の面（図１において上面）が、半導体素子３が搭載される搭載面とされている。ここで、回路層１３の厚さは０．３ｍｍ以上３ｍｍ以下の範囲内に設定されており、本実施形態では０．５ｍｍに設定されている。 As shown in FIG. 4, the circuit layer 13 has a circuit pattern formed by bonding a metal plate material 30 according to the present embodiment to one surface (upper surface in FIG. 4) of the insulating resin layer 12 . Specifically, one surface of the insulating resin layer 12 and the surface of the metal plate member 30 on the roughened plating layer 35 side are joined together. Alternatively, a circuit pattern may be first formed on the metal plate material 30 and then the metal plate material 30 having the circuit pattern formed thereon may be bonded to one surface of the insulating resin layer 12 .
A circuit pattern is formed on the circuit layer 13, and one surface (upper surface in FIG. 1) of the circuit layer 13 serves as a mounting surface on which the semiconductor element 3 is mounted. Here, the thickness of the circuit layer 13 is set within a range of 0.3 mm or more and 3 mm or less, and is set to 0.5 mm in this embodiment.
　ここで、上述の回路層１３となる本実施形態の金属板材３０について、図２Ａ、図２Ｂを参照して説明する。
　本実施形態である金属板材３０は、電気伝導性および熱伝導性に優れた金属で構成されており、本実施形態では、銅又は銅合金で構成されており、具体的には無酸素銅で構成されている。
　そして、本実施形態である金属板材３０においては、図２Ａに示すように、板本体３１と、この板本体３１の最表層に形成された粗化めっき層３５と、を備えている。 Here, the metal plate material 30 of this embodiment, which becomes the circuit layer 13 described above, will be described with reference to FIGS. 2A and 2B.
The metal plate material 30 of the present embodiment is made of a metal having excellent electrical conductivity and thermal conductivity. In the present embodiment, it is made of copper or a copper alloy, specifically oxygen-free copper. It is configured.
As shown in FIG. 2A, the metal plate material 30 of this embodiment includes a plate body 31 and a roughened plating layer 35 formed on the outermost layer of the plate body 31 .
　この粗化めっき層３５には、図２Ｂに示すように、板本体３１とは反対側（図２Ｂにおいて上側）に向けて突出する凸部３６が形成されている。
　なお、本実施形態では、凸部３６として、図２Ｂに示すように、突出方向の先端側に向かうにしたがい漸次幅が広くなる拡幅部３６ａを備えているものが存在していることが好ましい。 As shown in FIG. 2B, the roughened plating layer 35 is formed with convex portions 36 that protrude toward the side opposite to the plate body 31 (upper side in FIG. 2B).
In the present embodiment, as shown in FIG. 2B, the convex portion 36 preferably includes a widened portion 36a whose width gradually increases toward the tip side in the projecting direction.
　そして、本実施形態である金属板材３０においては、粗化めっき層３５の最表層から厚さ方向に６μｍの領域における銅部分の面積を１００％とした場合に、ＫＡＭ値が１．０以上である領域の面積率が１０％以下とされている。
　また、粗化めっき層３５の最表面のＳｄｒ（展開界面面積率）が２０％以上であるか、または粗化めっき層３５の最表面のＲ（展開界面線長率）が４０％以上である。 In the metal plate material 30 of the present embodiment, the KAM value is 1.0 or more when the area of the copper portion in the region of 6 μm in the thickness direction from the outermost layer of the roughened plating layer 35 is 100%. The area ratio of a certain region is set to 10% or less.
Further, the Sdr (developed interface area ratio) of the outermost surface of the roughened plating layer 35 is 20% or more, or the R (developed interface line length ratio) of the outermost surface of the roughened plating layer 35 is 40% or more. .
　そして、本実施形態である絶縁回路基板１０は、絶縁樹脂層１２と回路層１３との接合界面において、回路層１３（金属板材３０）の凸部３６と絶縁樹脂層１２とが係合しており、回路層１３（金属板材３０）と絶縁樹脂層１２とが互いに入り込んだ構造とされている。 In the insulating circuit board 10 of the present embodiment, the protrusions 36 of the circuit layer 13 (metal plate material 30) and the insulating resin layer 12 are engaged at the bonding interface between the insulating resin layer 12 and the circuit layer 13. In this structure, the circuit layer 13 (metal plate material 30) and the insulating resin layer 12 are embedded in each other.
　なお、本実施形態では、金属基板１１は、絶縁樹脂層１２の他方の面（図４において下面）に、本実施形態である金属板材３０が接合されることにより形成されている。詳細には、絶縁樹脂層１２の他方の面と、金属板材３０の粗化めっき層３５側の面とが接合されている。絶縁樹脂層１２と金属基板１１との接合界面においても、金属基板１１（金属板材３０）の凸部と絶縁樹脂層１２とが係合しており、金属基板１１（金属板材３０）と絶縁樹脂層１２とが互いに入り込んだ構造とされている。 In this embodiment, the metal substrate 11 is formed by joining the metal plate material 30 of this embodiment to the other surface (lower surface in FIG. 4) of the insulating resin layer 12 . Specifically, the other surface of the insulating resin layer 12 and the surface of the metal plate member 30 on the roughened plating layer 35 side are joined together. Also at the joint interface between the insulating resin layer 12 and the metal substrate 11, the convex portion of the metal substrate 11 (metal plate material 30) and the insulating resin layer 12 are engaged, and the metal substrate 11 (metal plate material 30) and the insulating resin are engaged. The layer 12 and the layer 12 have a structure in which they enter each other.
　以下に、本実施形態である絶縁回路基板１０の回路層１３及び金属基板１１を構成する金属板材３０において、ＫＡＭ値が１．０以上である領域の面積率、粗化めっき層３５の最表面のＳｄｒ（展開界面面積率）、粗化めっき層３５の最表面のＲ（展開界面線長率）を、上述のように規定した理由について説明する。 Below, in the metal plate material 30 constituting the circuit layer 13 and the metal substrate 11 of the insulated circuit board 10 of this embodiment, the area ratio of the region having a KAM value of 1.0 or more, the outermost surface of the roughened plating layer 35 The reason why Sdr (ratio of developed interface area) and R (ratio of developed interface line length) of the outermost surface of the roughened plating layer 35 are defined as described above will be explained.
（ＫＡＭ値が１．０以上である領域の面積率）
　ＥＢＳＤ法により測定されるＫＡＭ（Ｋｅｒｎｅｌ Ａｖｅｒａｇｅ Ｍｉｓｏｒｉｅｎｔａｔｉｏｎ）値は、局所的な方位差、すなわち、ひずみの分布を評価したものであり、このＫＡＭ値が高い領域は、加工時に導入されたひずみが高い領域であり、残留応力が高くなる。 (Area ratio of regions with a KAM value of 1.0 or more)
The KAM (Kernel Average Misorientation) value measured by the EBSD method evaluates the local orientation difference, that is, the strain distribution. and the residual stress is high.
　本実施形態の金属板材３０においては、粗化めっき層３５の最表層から厚さ方向に６μｍの領域におけるＫＡＭ値が１．０以上である領域の面積率が低いと、ひずみが高い領域が少なく残留応力が十分に低減されていることになり、粗化めっき層３５において、均一かつ緻密に凸部３６を形成することが可能となる。
　このため、本実施形態の金属板材３０においては、粗化めっき層３５の最表層から厚さ方向に６μｍの領域におけるＫＡＭ値が１．０以上である領域の面積率を１０％以下に制限している。 In the metal plate material 30 of the present embodiment, when the area ratio of the region having a KAM value of 1.0 or more in the region of 6 μm in the thickness direction from the outermost layer of the roughened plating layer 35 is low, the region with high strain is small. Residual stress is sufficiently reduced, and it becomes possible to form convex portions 36 uniformly and precisely in the roughened plating layer 35 .
Therefore, in the metal plate material 30 of the present embodiment, the area ratio of a region having a KAM value of 1.0 or more in a region of 6 μm in the thickness direction from the outermost layer of the roughened plating layer 35 is limited to 10% or less. ing.
　なお、粗化めっき層３５の最表層から厚さ方向に６μｍの領域におけるＫＡＭ値が１．０以上である領域の面積率は、５％以下であることが好ましく、３％以下であることがさらに好ましい。上述の面積率の下限には、特に制限はなく、０％であることが最も好ましい。
　ここで、観察視野において、最も突出した凸部３６の頂部が「粗化めっき層３５の最表層」となり、ここから厚さ方向に６μｍの領域の金属部分の面積を１００％とし、ＫＡＭ値が１．０以上である領域の面積率を算出することになる。 In addition, the area ratio of a region having a KAM value of 1.0 or more in a region of 6 μm in the thickness direction from the outermost layer of the roughened plating layer 35 is preferably 5% or less, and is preferably 3% or less. More preferred. The lower limit of the above area ratio is not particularly limited, and is most preferably 0%.
Here, in the observation field, the top of the most protruding convex portion 36 is the "outermost layer of the roughened plating layer 35", and the area of the metal portion in the region of 6 μm in the thickness direction from here is 100%, and the KAM value is The area ratio of the region that is 1.0 or more is calculated.
（粗化めっき層３５の最表面のＳｄｒ）
　Ｓｄｒ（展開界面面積率）は、凹凸による表面積の増加割合を示す指標である。金属板材３０と平行な平面をＸＹ平面とし、凹凸の輪郭曲面の表面積をＡ１とし、表面をＸＹ平面に投影したときの表面積（投影面積）をＡ０とすると、Ｓｄｒは以下の式で表される。
　Ｓｄｒ＝｛（Ａ１／Ａ０）－１｝×１００（％）
　Ｓｄｒが大きいと、凸部（表面の形状）が緻密で起伏が大きいことになる。
　このため、本実施形態の金属板材３０においては、粗化めっき層３５の最表面のＳｄｒ（展開界面面積率）を２０％以上に規定している。
　なお、粗化めっき層３５の最表面のＳｄｒ（展開界面面積率）は、４０％以上であることが好ましく、６５％以上であることがさらに好ましい。粗化めっき層３５の最表面のＳｄｒ（展開界面面積率）の上限に特に制限はないが、測定方法に鑑みて現実的には１５０％以下となる。
　Ｓｄｒ（展開界面面積率）は、以下の方法によって測定される。金属板材３０の粗化めっき層３５の表面のうち、１２９μｍ×１２９μｍの範囲を、レーザ顕微鏡の１００倍の対物レンズを使用して観察する。サンプルの傾き、ノイズを除去する処理を行う。得られた画像を解析し、上述の式によりＳｄｒ（展開界面面積率）を算出する。
　通常、Ｓｄｒ（展開界面面積率）は、絶縁樹脂層（樹脂部材）１２に接合される前の金属板材３０にて測定される。
　絶縁回路基板（積層体）１０の回路層１３や金属基板１１が金属板材３０であり、金属板材３０が絶縁樹脂層（樹脂部材）１２に接合された状態である場合、絶縁回路基板（積層体）１０における金属板材３０（回路層１３や金属基板１１）のＳｄｒ（展開界面面積率）は、以下の方法により測定される。有機溶媒などにより絶縁樹脂層（樹脂部材）１２を溶解するか、又は絶縁回路基板（積層体）１０を焼成することにより、絶縁樹脂層（樹脂部材）１２を除去する。このようにして、金属板材３０と絶縁樹脂層（樹脂部材）１２の接合界面（金属板材３０の粗化めっき層３５の表面）を露出させる。そして、上述したようにレーザ顕微鏡を用いて表面を観察する。得られた画像を解析し、上述の式によりＳｄｒ（展開界面面積率）を算出する。 (Sdr on the outermost surface of the roughened plating layer 35)
Sdr (expansion interface area ratio) is an index showing the rate of increase in surface area due to unevenness. Assuming that the plane parallel to the metal plate 30 is the XY plane, the surface area of the contour curved surface of the unevenness is A1, and the surface area (projected area) when the surface is projected onto the XY plane is A0, Sdr is expressed by the following equation. be done.
Sdr={(A 1 /A 0 )−1}×100 (%)
When the Sdr is large, the projections (surface shape) are dense and have large undulations.
For this reason, in the metal plate material 30 of the present embodiment, the Sdr (development interface area ratio) of the outermost surface of the roughened plating layer 35 is specified to be 20% or more.
The Sdr (spread interface area ratio) of the outermost surface of the roughened plating layer 35 is preferably 40% or more, more preferably 65% or more. Although there is no particular upper limit for the Sdr (development interface area ratio) of the outermost surface of the roughened plating layer 35, it is practically 150% or less in view of the measurement method.
Sdr (spread interface area ratio) is measured by the following method. A 129 μm×129 μm range of the surface of the roughened plating layer 35 of the metal plate material 30 is observed using a 100× objective lens of a laser microscope. Perform processing to remove sample tilt and noise. The obtained image is analyzed, and Sdr (ratio of developed interface area) is calculated by the above formula.
Normally, Sdr (development interface area ratio) is measured on the metal plate material 30 before being joined to the insulating resin layer (resin member) 12 .
When the circuit layer 13 and the metal substrate 11 of the insulating circuit board (laminate) 10 are the metal plate material 30 and the metal plate material 30 is bonded to the insulating resin layer (resin member) 12, the insulating circuit board (laminate) ) 10 is measured by the following method. The insulating resin layer (resin member) 12 is removed by dissolving the insulating resin layer (resin member) 12 with an organic solvent or the like, or by baking the insulating circuit board (laminate) 10 . In this way, the bonding interface (the surface of the roughened plating layer 35 of the metal plate material 30) between the metal plate material 30 and the insulating resin layer (resin member) 12 is exposed. Then, the surface is observed using a laser microscope as described above. The obtained image is analyzed, and Sdr (ratio of developed interface area) is calculated by the above formula.
（粗化めっき層３５の最表面のＲ）
　粗化めっき層３５の断面における表面の曲線を断面曲線とすると、Ｒ（展開界面線長率）は、凹凸による断面曲線の線長の増加割合を示す指標である。断面曲線の線長をＬ１とし、断面曲線をＸ軸に投影したときの長さ（投影長さ）をＬ０とすると、Ｒは以下の式で表される。なお、断面における粗化めっき層の厚み方向をＹ軸とし、Ｙ軸と直交する方向をＸ軸とする。
　Ｒ＝｛（Ｌ１／Ｌ０）－１｝×１００（％）
　Ｒが大きいと、凸部（表面の形状）が緻密で起伏が大きいことになる。
　このため、本実施形態の金属板材３０においては、粗化めっき層３５の最表面のＲ（展開界面線長率）を４０％以上に規定している。Ｒ（展開界面線長率）は、１００％以上が好ましく、１５０％以上が更に好ましい。Ｒ（展開界面線長率）の上限に特に制限はないが、現実的には１０００％以下となる。
　Ｒ（展開界面線長率）は、以下の方法によって測定される。金属板材３０の長手方向に平行な断面と、金属板材３０の長手方向に直行する方向の断面を用意する。それぞれの断面のうち、断面曲線の１１５μｍの範囲を、走査型電子顕微鏡を用いて１０００倍の倍率で観察する。得られた画像を解析し、上述の式によりＲ（展開界面線長率）を算出する。金属板材３０の長手方向に平行な断面におけるＲ（展開界面線長率）と、金属板材３０の長手方向に直行する方向の断面におけるＲ（展開界面線長率）の平均値を、その金属板材３０の粗化めっき層３５のＲ（展開界面線長率）とする。
　絶縁回路基板（積層体）１０の回路層１３や金属基板１１が金属板材３０であり、金属板材３０が絶縁樹脂層（樹脂部材）１２に接合された状態である場合、絶縁回路基板（積層体）１０における金属板材３０（回路層１３や金属基板１１）のＲ（展開界面線長率）は、以下の方法により測定される。絶縁回路基板（積層体）１０の長手方向に平行な断面と、絶縁回路基板（積層体）１０の長手方向に直行する方向の断面を用意する。それぞれの断面を走査型電子顕微鏡を用いて１０００倍の倍率で観察する。断面において、金属板材３０と絶縁樹脂層（樹脂部材）１２との接合界面における粗化めっき層３５の断面曲線を特定する。断面曲線の１１５μｍの範囲を観察する。得られた画像を解析し、上述の式によりＲ（展開界面線長率）を算出する。絶縁回路基板（積層体）１０の長手方向に平行な断面におけるＲ（展開界面線長率）と、絶縁回路基板（積層体）１０の長手方向に直行する方向の断面におけるＲ（展開界面線長率）の平均値を、その金属板材３０の粗化めっき層３５のＲ（展開界面線長率）とする。
　なお、金属板材３０から独立し絶縁樹脂層（樹脂部材）１２中に存在する金属片の輪郭や絶縁樹脂層（樹脂部材）１２から独立し金属板材３０中に存在する樹脂片の輪郭は、断面曲線の線長（Ｌ１）に含めない。
　絶縁回路基板（積層体）１０における金属板材３０（回路層１３や金属基板１１）のＳｄｒ（展開界面面積率）に比べて、絶縁回路基板（積層体）１０における金属板材３０（回路層１３や金属基板１１）のＲ（展開界面線長率）は、簡便に測定できる。 (R of the outermost surface of the roughened plating layer 35)
Assuming that the surface curve in the cross section of the roughened plating layer 35 is a cross-sectional curve, R (development interface line length ratio) is an index indicating the rate of increase in line length of the cross-sectional curve due to unevenness. Assuming that the length of the cross - sectional curve is L1 and the length of the cross-sectional curve projected onto the X axis (projected length) is L0 , R is expressed by the following equation. In addition, let the thickness direction of the roughening plating layer in a cross section be the Y-axis, and let the direction orthogonal to the Y-axis be the X-axis.
R = {(L 1 /L 0 )-1} x 100 (%)
When the R is large, the projections (shape of the surface) are dense and have large undulations.
For this reason, in the metal plate material 30 of the present embodiment, the R (development interface line length ratio) of the outermost surface of the roughening plating layer 35 is specified to be 40% or more. R (development interface line length ratio) is preferably 100% or more, more preferably 150% or more. Although there is no particular upper limit for R (development interface line length ratio), it is practically 1000% or less.
R (ratio of developed interface line length) is measured by the following method. A section parallel to the longitudinal direction of the metal plate member 30 and a section perpendicular to the longitudinal direction of the metal plate member 30 are prepared. In each cross section, a 115 μm range of the cross-sectional curve is observed using a scanning electron microscope at a magnification of 1000 times. The obtained image is analyzed, and R (development interface line length ratio) is calculated by the above formula. The average value of R (developed interface line length ratio) in a cross section parallel to the longitudinal direction of the metal plate material 30 and R (developed interface line length ratio) in a cross section perpendicular to the longitudinal direction of the metal plate material 30 is calculated. 30 of the roughened plating layer 35 is defined as R (ratio of developed interface line length).
When the circuit layer 13 and the metal substrate 11 of the insulating circuit board (laminate) 10 are the metal plate material 30 and the metal plate material 30 is bonded to the insulating resin layer (resin member) 12, the insulating circuit board (laminate) ) 10 is measured by the following method. A section parallel to the longitudinal direction of the insulating circuit board (laminate) 10 and a section perpendicular to the longitudinal direction of the insulating circuit board (laminate) 10 are prepared. Each cross section is observed with a scanning electron microscope at a magnification of 1000 times. In the cross section, a cross-sectional curve of the roughened plating layer 35 at the bonding interface between the metal plate material 30 and the insulating resin layer (resin member) 12 is specified. Observe the 115 μm range of the cross-sectional curve. The obtained image is analyzed, and R (development interface line length ratio) is calculated by the above formula. R (development interface line length ratio) in a cross section parallel to the longitudinal direction of the insulating circuit board (laminate) 10 and R (development interface line length) in a cross section perpendicular to the longitudinal direction of the insulating circuit board (laminate) 10 rate) is taken as the R (developed interface line length rate) of the roughened plating layer 35 of the metal plate material 30 .
Note that the outline of the metal piece that is independent of the metal plate material 30 and that exists in the insulating resin layer (resin member) 12 and the outline of the resin piece that is independent of the insulating resin layer (resin member) 12 and exists in the metal plate material 30 are shown in cross section. It is not included in the line length (L 1 ) of the curve.
Compared to the Sdr (development interface area ratio) of the metal plate material 30 (circuit layer 13 and metal substrate 11) in the insulating circuit board (laminate) 10, the metal plate material 30 (circuit layer 13 and metal substrate 11) in the insulating circuit board (laminate) 10 The R (development interface line length ratio) of the metal substrate 11) can be easily measured.
　次に、本実施形態である絶縁回路基板１０の製造方法について、図３および図４を参照して説明する。
　なお、図４では、金属基板１１に金属板材の符号３０が付されていないが、金属基板１１は、金属板材３０であり、板本体３１と、板本体３１の最表層に形成された粗化めっき層３５と、を有する。 Next, a method for manufacturing the insulating circuit board 10 according to the present embodiment will be described with reference to FIGS. 3 and 4. FIG.
In FIG. 4, the metal substrate 11 is not provided with a metal plate material 30, but the metal substrate 11 is the metal plate material 30, and includes a plate main body 31 and a roughened surface formed on the outermost layer of the plate main body 31. and a plating layer 35 .
（応力低減工程Ｓ０１）
　まず、回路層１３となる金属板材３０において、板本体３１の表面（粗化めっき層３５を形成する面）近傍の残留応力を低減する。同様に、金属基板１１の表面（粗化めっき層３５を形成する面）近傍の残留応力を低減する。
　残留応力の低減方法に特に制限はないが、例えば、化学研磨、熱処理、直流電解めっき等を適用することができる。 (Stress reduction step S01)
First, in the metal plate material 30 that becomes the circuit layer 13, the residual stress in the vicinity of the surface of the plate body 31 (the surface on which the roughened plating layer 35 is formed) is reduced. Similarly, the residual stress in the vicinity of the surface of the metal substrate 11 (the surface on which the roughened plating layer 35 is formed) is reduced.
A method for reducing residual stress is not particularly limited, but chemical polishing, heat treatment, direct current electroplating, etc., can be applied, for example.
　化学研磨においては、例えば、化学研磨液（例えば、硫酸と過酸化水素の混合液）を使用して、板本体３１の表面を除去することで、板本体３１の表面近傍の残留応力を低減する。
　熱処理においては、例えば、４００℃以上６００℃以下の温度で１時間以上２時間以下保持することで、板本体３１の表面近傍の残留応力を低減する。
　直流電解めっきにおいては、例えば、板本体３１の表面を電解脱脂処理、酸洗処理し、次いで、高温かつ低電流密度にて６μｍ以上成膜する。その後、常温で数日置く、もしくは、１５０℃×１時間の熱処理を行うことで、板本体３１の表面近傍の残留応力を低減する。 In chemical polishing, for example, a chemical polishing liquid (for example, a mixture of sulfuric acid and hydrogen peroxide) is used to remove the surface of the plate body 31, thereby reducing the residual stress in the vicinity of the surface of the plate body 31. .
In the heat treatment, the residual stress in the vicinity of the surface of the plate body 31 is reduced, for example, by holding at a temperature of 400° C. or higher and 600° C. or lower for 1 hour or more and 2 hours or less.
In DC electroplating, for example, the surface of the plate body 31 is subjected to electrolytic degreasing treatment and pickling treatment, and then a film of 6 μm or more is formed at high temperature and low current density. After that, the residual stress in the vicinity of the surface of the plate body 31 is reduced by leaving it at room temperature for several days or performing heat treatment at 150° C. for 1 hour.
（表面粗化工程Ｓ０２）
　次に、表面の残留応力を低減した板本体３１の表面に粗化めっき層３５を形成する。本実施形態では、金属基板１１にも粗化めっき層３５を形成する。この粗化めっき層３５は、以下のようにして形成される。
　板本体３１（および金属基板１１）の接合面に電解めっき処理を施す。本実施形態では、電解めっき液として硫酸銅（ＣｕＳＯ４）および硫酸（Ｈ２ＳＯ４）を主成分とした硫酸銅浴に、３，３’－ジチオビス（１－プロパンスルホン酸）２ナトリウムを添加した水溶液からなる電解液を用いることが好ましい。また、めっき浴の温度は例えば２５℃以上３５℃以下の範囲内とすることが好ましい。 (Surface roughening step S02)
Next, a roughening plated layer 35 is formed on the surface of the plate body 31 in which the surface residual stress is reduced. In this embodiment, the roughening plated layer 35 is also formed on the metal substrate 11 . This roughening plated layer 35 is formed as follows.
Electroplating is applied to the joint surfaces of the plate body 31 (and the metal substrate 11). In this embodiment, 3,3′-dithiobis(1-propanesulfonic acid) disodium is added to a copper sulfate bath containing copper sulfate (CuSO 4 ) and sulfuric acid (H 2 SO 4 ) as main components as an electrolytic plating solution. It is preferable to use an electrolytic solution consisting of an aqueous solution obtained by Also, the temperature of the plating bath is preferably within the range of 25° C. or higher and 35° C. or lower.
　そして、電解めっき処理としては、まず、直流電解めっき法で実施し、その後、ＰＲ（Ｐｅｒｉｏｄｉｃ　Ｒｅｖｅｒｓｅ）パルス電解めっき法で実施する。
　直流電解めっき法においては、電流密度を１Ａ／ｄｍ２以上２０Ａ／ｄｍ２以下の範囲内、印加時間を１０秒以上１２０秒以下の範囲内とする。
　この直流電解めっきを実施することにより、板本体３１の表面に位置する表層結晶粒が粗大な場合でも、後述するＰＲパルス電解めっきによって、凸部３６を十分に形成することが可能となる。
　特に、応力低減工程Ｓ０１において、化学研磨や熱処理を実施した場合には、表層結晶粒が粗大化し易いため、直流電解めっきを実施することが好ましい。 Then, the electroplating treatment is first performed by a DC electroplating method, and then performed by a PR (Periodic Reverse) pulse electroplating method.
In the DC electroplating method, the current density is set within the range of 1 A/dm 2 or more and 20 A/dm 2 or less, and the application time is set within the range of 10 seconds or more and 120 seconds or less.
By carrying out this DC electroplating, even if the surface layer crystal grains located on the surface of the plate body 31 are coarse, it is possible to sufficiently form the protrusions 36 by PR pulse electroplating, which will be described later.
In particular, when chemical polishing or heat treatment is performed in the stress reduction step S01, surface layer crystal grains tend to coarsen, so DC electroplating is preferably performed.
　ＰＲパルス電解めっき法は、電流の方向を周期的に反転させながら通電して電解めっきする方法である。例えば、１Ａ／ｄｍ２以上３０Ａ／ｄｍ２以下の正電解（板本体３１（および金属基板１１）を陽極とする陽極電解）を１ｍｓ以上１０００ｍｓ以下、１Ａ／ｄｍ２以上３０Ａ／ｄｍ２以下の負電解（板本体３１（および金属基板１１）を負極とする負極電解）を１ｍｓ以上１０００ｍｓ以下として、これを繰り返す。これにより、板本体３１（および金属基板１１）の表面の溶解と銅の析出とが繰り返し実施され、粗化めっき層３５が形成されることになる。 The PR pulse electroplating method is a method of performing electroplating by applying current while periodically reversing the direction of the current. For example, a positive electrolysis of 1 A/dm 2 or more and 30 A/dm 2 or less (anodic electrolysis using the plate body 31 (and the metal substrate 11) as an anode) is 1 ms or more and 1000 ms or less, and a negative electrolysis of 1 A/dm 2 or more and 30 A/dm 2 or less. Electrolysis (negative electrolysis using the plate body 31 (and the metal substrate 11) as the negative electrode) is repeated for 1 ms or more and 1000 ms or less. As a result, the dissolution of the surface of the plate body 31 (and the metal substrate 11) and the deposition of copper are repeated, and the roughened plating layer 35 is formed.
　ここで、粗化めっき層３５を形成する板本体３１（および金属基板１１）の表面性状、および、各種めっき条件（パルス印加時間、パルス波形（析出量／溶解量比）、パルス周波数）によって、粗化めっき層３５における凸部３６の個数を調整することができる。
　例えば、パルス印加時間を長くするか、パルス波形として析出量／溶解量比を調整すると、凸部３６の大きさを大きくさせることができる。パルス周波数を調整すると、凸部３６の個数を増加させることができる。 Here, depending on the surface properties of the plate body 31 (and the metal substrate 11) forming the roughened plating layer 35 and various plating conditions (pulse application time, pulse waveform (precipitation amount/dissolution amount ratio), pulse frequency), The number of protrusions 36 in the roughening plating layer 35 can be adjusted.
For example, the size of the protrusions 36 can be increased by lengthening the pulse application time or by adjusting the deposition/dissolution ratio of the pulse waveform. By adjusting the pulse frequency, the number of protrusions 36 can be increased.
（積層工程Ｓ０３）
　次に、金属基板１１の一方の面（図４において上面）に、フィラーとしての窒化ホウ素と熱硬化型樹脂としてのエポキシ樹脂と硬化剤とを含有する樹脂組成物２２を配設する。なお、本実施形態では、樹脂組成物２２は、シート状に形成されている。
　また、この樹脂組成物２２の一方の面（図４において上面）に、回路層１３となる金属板材３０を配設する。
　なお、樹脂組成物２２は、金属基板１１および金属板材３０の粗化めっき層３５が形成された面に直接接するように積層される。 (Lamination step S03)
Next, a resin composition 22 containing boron nitride as a filler, an epoxy resin as a thermosetting resin, and a curing agent is provided on one surface (upper surface in FIG. 4) of the metal substrate 11 . In addition, in this embodiment, the resin composition 22 is formed in a sheet shape.
Also, a metal plate material 30 to be the circuit layer 13 is arranged on one surface (upper surface in FIG. 4) of the resin composition 22 .
The resin composition 22 is laminated so as to be in direct contact with the surfaces of the metal substrate 11 and the metal plate material 30 on which the roughened plating layer 35 is formed.
（熱圧着工程Ｓ０４）
　次に、積層した金属基板１１、樹脂組成物２２、金属板材３０を、積層方向に加圧しながら加熱して、樹脂組成物２２を硬化させて絶縁樹脂層１２を形成するとともに、金属基板１１と絶縁樹脂層１２、絶縁樹脂層１２と金属板材３０を接合する。
　この熱圧着工程Ｓ０４の条件は、加熱温度を１００℃以上４００℃以下の範囲内、加熱温度での保持時間を３０分以上９０分以下の範囲内、積層方向の加圧圧力を１ＭＰａ以上１００ＭＰａ以下の範囲内とすることが好ましい。 (Thermal compression step S04)
Next, the laminated metal substrate 11, the resin composition 22, and the metal plate material 30 are heated while being pressed in the lamination direction to cure the resin composition 22 and form the insulating resin layer 12. The insulating resin layer 12 and the insulating resin layer 12 and the metal plate material 30 are joined.
The conditions of this thermocompression bonding step S04 are as follows: heating temperature in the range of 100° C. or more and 400° C. or less, holding time at the heating temperature in the range of 30 minutes or more and 90 minutes or less, and pressure in the stacking direction of 1 MPa or more and 100 MPa or less. is preferably within the range of
（回路パターン形成工程Ｓ０５）
　次に、絶縁樹脂層１２に接合された金属板材３０に対してエッチング処理を行い、回路パターンを形成し、回路層１３を得る。 (Circuit pattern forming step S05)
Next, the metal plate material 30 joined to the insulating resin layer 12 is etched to form a circuit pattern, and the circuit layer 13 is obtained.
　以上のようにして、本実施形態である絶縁回路基板１０が製造される。 As described above, the insulating circuit board 10 of the present embodiment is manufactured.
（ヒートシンク接合工程Ｓ０６）
　次に、この絶縁回路基板１０の金属基板１１の他方の面にヒートシンク４１を接合する。本実施形態では、金属基板１１とヒートシンク４１とを、はんだ材を介して接合している。 (Heat-sink bonding step S06)
Next, a heat sink 41 is joined to the other surface of the metal substrate 11 of the insulated circuit substrate 10 . In this embodiment, the metal substrate 11 and the heat sink 41 are joined together via a solder material.
（半導体素子接合工程Ｓ０７）
　そして、絶縁回路基板１０の回路層１３に半導体素子３を接合する。本実施形態では、回路層１３と半導体素子３とを、はんだ材を介して接合している。
　以上の工程により、図１に示すパワーモジュール１が製造される。 (Semiconductor element bonding step S07)
Then, the semiconductor element 3 is bonded to the circuit layer 13 of the insulating circuit board 10 . In this embodiment, the circuit layer 13 and the semiconductor element 3 are joined via a solder material.
Through the steps described above, the power module 1 shown in FIG. 1 is manufactured.
　以上のような構成とされた本実施形態に係る金属板材３０および絶縁回路基板１０（積層体）によれば、粗化めっき層３５の最表層から厚さ方向に６μｍの領域において、ＫＡＭ値が１．０以上である領域の面積率が１０％以下とされているので、表層の残留応力が低く抑えられており、粗化めっき層３５において、板本体３１とは反対側に向けて突出する凸部３６を均一かつ緻密に形成することができる。
　そして、粗化めっき層３５の最表面のＳｄｒ（展開界面面積率）が２０％以上であるか、または粗化めっき層３５の最表面のＲ（展開界面線長率）が４０％以上であるので、凸部３６が均一かつ緻密に形成されており、粗化めっき層３５側に積層した絶縁樹脂層１２と上述の凸部３６とが係合することにより、回路層１３（金属板材３０）と絶縁樹脂層１２との密着性、及び金属基板１１（金属板材３０）と絶縁樹脂層１２との密着性を向上させることが可能となる。 According to the metal plate material 30 and the insulating circuit board 10 (laminate) according to the present embodiment configured as described above, the KAM value is Since the area ratio of the region of 1.0 or more is set to 10% or less, the residual stress of the surface layer is kept low, and the roughened plating layer 35 protrudes toward the side opposite to the plate body 31. The protrusions 36 can be formed uniformly and densely.
Then, the Sdr (developed interface area ratio) of the outermost surface of the roughened plating layer 35 is 20% or more, or the R (developed interface line length ratio) of the outermost surface of the roughened plating layer 35 is 40% or more. Therefore, the protrusions 36 are formed uniformly and densely, and the protrusions 36 are engaged with the insulating resin layer 12 laminated on the roughened plating layer 35 side, thereby forming the circuit layer 13 (metal plate material 30). and the insulating resin layer 12, and the adhesiveness between the metal substrate 11 (metal plate material 30) and the insulating resin layer 12 can be improved.
　本実施形態において、板本体３１とは反対側に向けて突出する凸部３６が、突出方向の先端側に向かうにしたがい漸次幅が広くなる拡幅部３６ａを備えているものを含む場合には、粗化めっき層３５側に積層した絶縁樹脂層１２が凸部３６と確実に係合されることになり、回路層１３（金属板材３０）と絶縁樹脂層１２との密着性、及び金属基板１１（金属板材３０）と絶縁樹脂層１２との密着性をさらに向上させることが可能となる。 In this embodiment, if the convex portion 36 protruding toward the opposite side of the plate body 31 includes a widened portion 36a whose width gradually increases toward the tip side in the direction of protrusion, The insulating resin layer 12 laminated on the roughened plated layer 35 side is reliably engaged with the protrusions 36 , and the adhesion between the circuit layer 13 (metal plate material 30 ) and the insulating resin layer 12 and the metal substrate 11 It is possible to further improve the adhesion between (the metal plate material 30) and the insulating resin layer 12.
　また、本実施形態においては、板本体３１が銅又は銅合金で構成されているので、電気伝導性および熱伝導性に優れた回路層１３（金属板材３０）を形成することができる。 In addition, in the present embodiment, since the plate body 31 is made of copper or a copper alloy, it is possible to form the circuit layer 13 (metal plate material 30) with excellent electrical conductivity and thermal conductivity.
　以上、本発明の実施形態について説明したが、本発明はこれに限定されることはなく、その発明の技術的要件を逸脱しない範囲で適宜変更可能である。
　本実施形態においては、図３および図４に示す絶縁回路基板の製造方法によって絶縁回路基板を製造するものとして説明したが、これに限定されることはない。 Although the embodiment of the present invention has been described above, the present invention is not limited to this, and can be modified as appropriate without departing from the technical requirements of the invention.
In the present embodiment, the insulating circuit board is manufactured by the manufacturing method of the insulating circuit board shown in FIGS. 3 and 4, but it is not limited to this.
　また、本実施形態においては、回路層１３を形成する金属板材３０として、無酸素銅で構成されたものとして説明したが、これに限定されることはなく、他の銅又は銅合金で構成されたものであってもよいし、アルミニウム又はアルミニウム合金等の他の金属で構成されたものであってもよい。さらに、複数の金属が積層された構造のものであってもよい。 Further, in the present embodiment, the metal plate material 30 forming the circuit layer 13 has been described as being made of oxygen-free copper, but is not limited to this, and may be made of other copper or copper alloy. It may be made of other metal such as aluminum or aluminum alloy. Furthermore, it may have a structure in which a plurality of metals are laminated.
　さらに、本実施形態においては、金属基板１１を、無酸素銅で構成されたものとして説明したが、これに限定されることはなく、他の銅又は銅合金で構成されたものであってもよいし、アルミニウム又はアルミニウム合金等の他の金属で構成されたものであってもよい。さらに、複数の金属が積層された構造のものであってもよい。
　金属基板１１は、ヒートシンクであってもよい。すなわち、ヒートシンクが直接絶縁樹脂層１２の他方の面に接合されてもよい。 Furthermore, in the present embodiment, the metal substrate 11 is described as being made of oxygen-free copper, but is not limited to this, and may be made of other copper or copper alloy. Alternatively, it may be made of other metals such as aluminum or an aluminum alloy. Furthermore, it may have a structure in which a plurality of metals are laminated.
Metal substrate 11 may be a heat sink. That is, the heat sink may be directly bonded to the other surface of the insulating resin layer 12 .
　また、本実施形態では、絶縁回路基板に半導体素子を搭載してパワーモジュールを構成するものとして説明したが、これに限定されることはない。例えば、絶縁回路基板の回路層にＬＥＤ素子を搭載してＬＥＤモジュールを構成してもよいし、絶縁回路基板の回路層に熱電素子を搭載して熱電モジュールを構成してもよい。 Also, in the present embodiment, a power module is configured by mounting a semiconductor element on an insulated circuit board, but it is not limited to this. For example, an LED module may be configured by mounting an LED element on the circuit layer of the insulating circuit board, or a thermoelectric module may be configured by mounting a thermoelectric element on the circuit layer of the insulating circuit board.
　本実施形態では、回路層１３と金属基板１１の両者が、本実施形態に係る金属板材３０を絶縁樹脂層１２の面に接合することにより形成されているものとして説明したが、これに限定されることはない。回路層１３と金属基板１１のいずれか一方が、本実施形態に係る金属板材３０を絶縁樹脂層１２の面に接合することにより形成されていれば、本実施形態に記載の作用効果が得られる。特に、回路層１３が本実施形態に係る金属板材３０である場合よりも、金属基板１１が本実施形態に係る金属板材３０である場合の方が、本実施形態に記載の作用効果を得やすい。 In the present embodiment, both the circuit layer 13 and the metal substrate 11 are described as being formed by bonding the metal plate material 30 according to the present embodiment to the surface of the insulating resin layer 12, but the present invention is not limited to this. never If either one of the circuit layer 13 and the metal substrate 11 is formed by bonding the metal plate material 30 according to the present embodiment to the surface of the insulating resin layer 12, the effects described in the present embodiment can be obtained. . In particular, when the metal substrate 11 is the metal plate material 30 according to the present embodiment, it is easier to obtain the effects described in the present embodiment than when the circuit layer 13 is the metal plate material 30 according to the present embodiment. .
　以下に、本発明の効果を確認すべく行った確認実験の結果について説明する。 The results of confirmation experiments conducted to confirm the effects of the present invention are described below.
　無酸素銅の圧延板からなる金属基板（４０ｍｍ×４０ｍｍ×厚さ２ｍｍ）および回路層となる金属板材（４０ｍｍ×４０ｍｍ×厚さ０．５ｍｍ）を準備し、これら金属基板および金属板材の絶縁樹脂層との接合面となる面に対して、表１に示すように応力低減工程を実施し、その後、上述の実施形態に記載した直流電解めっき法およびＰＲパルス電解めっき法によって粗化めっき層を形成した。なお、めっき条件を表１に示す。表１のＰＲパルス電解の印加時間は、パルス電流の合計印加時間である。 A metal substrate (40 mm × 40 mm × 2 mm thick) made of a rolled sheet of oxygen-free copper and a metal plate material (40 mm × 40 mm × 0.5 mm thickness) to be the circuit layer are prepared, and the insulating resin of these metal substrates and metal plate materials A stress reduction step is performed as shown in Table 1 on the surface to be bonded to the layer, and then a roughened plating layer is formed by the DC electroplating method and the PR pulse electroplating method described in the above embodiment. formed. Table 1 shows the plating conditions. The application time of PR pulse electrolysis in Table 1 is the total application time of the pulse current.
　そして、金属基板の粗化めっき層が形成された面に、フィラーとして窒化ホウ素を含むエポキシ樹脂を含有する樹脂組成物のシート材（４０ｍｍ×４０ｍｍ×厚さ０．１５ｍｍ）を配置した。
　また、この樹脂組成物のシート材の一方の面に、回路層となる金属板材を、粗化めっき層が形成された面が樹脂組成物のシート材側を向くように、積層した。 Then, a sheet material (40 mm×40 mm×0.15 mm thick) of a resin composition containing an epoxy resin containing boron nitride as a filler was placed on the surface of the metal substrate on which the roughened plating layer was formed.
Further, a metal plate material to be a circuit layer was laminated on one surface of the resin composition sheet material so that the surface on which the roughened plating layer was formed faced the resin composition sheet material side.
　上述のように積層した金属基板と樹脂組成物のシート材と金属板材とを、積層方向に加圧しながら加熱し、樹脂組成物を硬化させて絶縁樹脂層を形成するとともに、金属基板と絶縁樹脂層、および、絶縁樹脂層と金属板材を接合し、絶縁回路基板を得た。なお、積層方向の加圧圧力は１０ＭＰａ、加熱温度は１８０℃、加熱温度での保持時間は６０分とした。
　以上のようにして、得られた金属板材および絶縁回路基板について、以下の項目についてそれぞれ評価した。 The metal substrate, the sheet material of the resin composition, and the metal plate material laminated as described above are heated while being pressed in the stacking direction, and the resin composition is cured to form an insulating resin layer, and the metal substrate and the insulating resin are formed. The layer, and the insulating resin layer and the metal plate were joined to obtain an insulated circuit board. The pressure in the stacking direction was 10 MPa, the heating temperature was 180° C., and the holding time at the heating temperature was 60 minutes.
The metal plate material and the insulated circuit board thus obtained were evaluated for the following items.
（ＫＡＭ値が１．０以上である領域の面積率）
　金属板材の圧延の幅方向に対して垂直な面、すなわちＴＤ面(Ｔｒａｎｓｖｅｒｓｅ ｄｉｒｅｃｔｉｏｎ）および圧延方向に垂直な面、すなわちＲＤ面（Ｒｏｌｌｉｎｇ　ｄｉｒｅｃｔｉｏｎ）を観察面として、ＥＢＳＤ測定装置及びＯＩＭ解析ソフトによって、次のようにＫＡＭ値を測定した。 (Area ratio of regions with a KAM value of 1.0 or more)
The surface perpendicular to the rolling width direction of the metal plate material, that is, the TD surface (Transverse direction) and the surface perpendicular to the rolling direction, that is, the RD surface (Rolling direction) are used as observation surfaces, with an EBSD measurement device and OIM analysis software, KAM values were measured as follows.
　耐水研磨紙を用いて観察面の機械研磨を行った。次いで、断面イオン加工装置（日立ハイテク社製ＩＭ－４０００）を用いて、断面イオン加工を行った。そして走査型電子顕微鏡（Carl Zeiss社製　ULTRA55）に搭載されたＥＢＳＤ検出器（TSL/EDAX社製 Hikari）を用いて電子線の加速電圧１５ｋＶ、測定間隔０．１μｍステップで、観察面においてめっき表面に垂直に幅７μｍ、めっき表面と平行に幅３０μｍの範囲以上でＥＢＳＤパターンを測定した。解析ソフト（ＥＤＡＸ／ＴＳＬ社製ＯＩＭ Ｄａｔａ Ａｎａｌｙｓｉｓ ｖｅｒ．７）を用いて各結晶粒の方位差の解析を行い、隣接するピクセル間の方位差が５°以上である境界を結晶粒界とみなして、めっき表面付近（幅１１μｍ）のＫＡＭ値を求めた。 The observation surface was mechanically polished using water-resistant abrasive paper. Next, cross-sectional ion processing was performed using a cross-sectional ion processing device (IM-4000 manufactured by Hitachi High-Tech Co., Ltd.). Then, using an EBSD detector (TSL/EDAX Hikari) mounted on a scanning electron microscope (Carl Zeiss ULTRA55), the electron beam acceleration voltage is 15 kV, the measurement interval is 0.1 μm steps, and the plating surface is observed on the observation surface. The EBSD pattern was measured over a range of 7 μm wide perpendicular to the plated surface and 30 μm wide parallel to the plating surface. The orientation difference of each crystal grain is analyzed using analysis software (EDAX/TSL OIM Data Analysis ver.7), and the boundary where the orientation difference between adjacent pixels is 5° or more is regarded as a grain boundary. , the KAM value near the plating surface (width 11 μm) was obtained.
　ＫＡＭ値の算出の際、粗化めっき層表面の凹凸に伴い生じた銅めっき部ではない領域を測定範囲のデータから除去するために、本測定ではＩＱ値（Ｉｍａｇｅ　Ｑｕａｌｉｔｙ値）が６００以下である測定点を除いた。ＩＱ値はＥＢＳＤパターンの明瞭さを示す相対指標であるが、測定条件や検出器、物質、試料観察面の状態などによって大きく変化するため、走査型電子顕微鏡画像と対比しながら銅めっき部ではない範囲を除けているか確認して、ＩＱ値を調整した。 When calculating the KAM value, the IQ value (Image Quality value) in this measurement is 600 or less in order to remove the area that is not the copper plating part generated due to the unevenness of the roughened plating layer surface from the data in the measurement range. Measurement points are excluded. The IQ value is a relative index that indicates the clarity of the EBSD pattern, but it varies greatly depending on the measurement conditions, detector, substance, and condition of the sample observation surface. After confirming that the range was excluded, I adjusted the IQ value.
（粗化めっき層の最表面のＳｄｒ）
　絶縁樹脂層に接合される前の金属板材の粗化めっき層の表面を、レーザ顕微鏡（オリンパス社製ＯＬＳ５０００）の１００倍の対物レンズを用いて、１２９μｍ×１２９μｍの測定範囲で観察した。サンプルの傾き、ノイズを除去する処理を行い、得られた画像を解析し、実施形態に記載された方法で金属板材の粗化めっき層の展開界面面積率Ｓｄｒを算出した。 (Sdr on the outermost surface of the roughened plating layer)
The surface of the roughened plating layer of the metal plate before being joined to the insulating resin layer was observed in a measurement range of 129 μm×129 μm using a 100× objective lens of a laser microscope (OLS5000 manufactured by Olympus). The tilt of the sample and processing for removing noise were performed, the obtained image was analyzed, and the developed interface area ratio Sdr of the roughened plating layer of the metal plate material was calculated by the method described in the embodiment.
（粗化めっき層の最表面のＲ）
　絶縁回路基板の長手方向に平行な断面と、絶縁回路基板の長手方向に直行する方向の断面を用意した。耐水研磨紙を用いて断面の機械研磨を行った。次いで、断面イオン加工装置（日立ハイテク社製ＩＭ－４０００）を用いて、断面イオン加工を行った。それぞれの断面を走査型電子顕微鏡を用いて１０００倍の倍率で観察した。断面において、金属板材と絶縁樹脂層との接合界面における粗化めっき層の断面曲線を特定した。断面曲線の１１５μｍの範囲を観察した。ここで、金属板材から独立し絶縁樹脂層中に存在する金属片の輪郭や絶縁樹脂層から独立し金属板材中に存在する樹脂片の輪郭は除去した。得られた画像を解析し、展開界面線長率Ｒを算出した。絶縁回路基板の長手方向に平行な断面における展開界面線長率Ｒと、絶縁回路基板の長手方向に直行する方向の断面における展開界面線長率Ｒの平均値を、粗化めっき層の展開界面線長率Ｒとした。 (R of the outermost surface of the roughened plating layer)
A section parallel to the longitudinal direction of the insulating circuit board and a section perpendicular to the longitudinal direction of the insulating circuit board were prepared. The cross section was mechanically polished using waterproof abrasive paper. Next, cross-sectional ion processing was performed using a cross-sectional ion processing device (IM-4000 manufactured by Hitachi High-Tech Co., Ltd.). Each cross section was observed with a scanning electron microscope at a magnification of 1000 times. In the cross section, the cross-sectional curve of the roughened plating layer at the bonding interface between the metal plate material and the insulating resin layer was specified. A 115 μm range of cross-sectional curves was observed. Here, the contour of the metal piece independent from the metal plate and present in the insulating resin layer and the contour of the resin piece independent from the insulating resin layer and present in the metal plate are removed. The obtained image was analyzed, and the developed interface line length ratio R was calculated. The average value of the developed interface line length ratio R in the cross section parallel to the longitudinal direction of the insulating circuit board and the developed interface line length ratio R in the cross section perpendicular to the longitudinal direction of the insulating circuit board is calculated as the developed interface of the roughening plating layer. A line length ratio R was used.
（吸湿リフロー後の部分放電開始電圧と絶縁耐圧）
　上述の絶縁回路基板を、恒温恒湿槽（温度８５℃、湿度８５％）に入れ、３日間保持した。その後、加熱炉内に装入し、２９０℃で１０分間のリフロー処理を実施した。
　リフロー処理後の絶縁回路基板において、回路層と絶縁樹脂層の部分放電開始電圧と絶縁破壊電圧（絶縁耐圧）について以下のようにして評価した。
　図５に示すように、金属基板１１をベース板６１の上に載置し、回路層１３の上にプローブ６２を接触させ、部分放電を評価した。測定装置として、三菱電線株式会社製の部分放電試験機を用いた。なお、試験雰囲気として、３Ｍ社製フロリナート（ｔｍ）ＦＣ－７７０中で実施した。
　そして、電圧を０．５ｋＶごとのステッププロファイル（保持時間６０秒）で昇圧し、平均放電電荷量が５ｐＣ以上となる電圧を部分放電開始電圧とした。また絶縁破壊が生じた電圧（漏れ電流が１０ｍＡ以上となった電圧）を絶縁破壊電圧とした。評価結果を表２に示す。
　小さな剥離のボイドによる部分的な放電が開始し、一定以上の電圧が加わると絶縁破壊になる。部分放電開始電圧は、小さな剥離に起因する値である。 (Partial discharge inception voltage and dielectric strength after moisture absorption reflow)
The insulated circuit board described above was placed in a thermo-hygrostat (85° C. temperature, 85% humidity) and held for 3 days. After that, it was placed in a heating furnace and subjected to reflow treatment at 290° C. for 10 minutes.
In the insulated circuit board after the reflow treatment, the partial discharge inception voltage and dielectric breakdown voltage (dielectric withstand voltage) of the circuit layer and the insulating resin layer were evaluated as follows.
As shown in FIG. 5, the metal substrate 11 was placed on the base plate 61, the probes 62 were brought into contact with the circuit layer 13, and the partial discharge was evaluated. A partial discharge tester manufactured by Mitsubishi Cable Co., Ltd. was used as a measuring device. The test atmosphere was Fluorinert (tm) FC-770 manufactured by 3M.
Then, the voltage was increased with a step profile (retention time: 60 seconds) in steps of 0.5 kV, and the voltage at which the average discharge charge amount was 5 pC or more was defined as the partial discharge inception voltage. The voltage at which dielectric breakdown occurred (the voltage at which the leakage current became 10 mA or more) was taken as the dielectric breakdown voltage. Table 2 shows the evaluation results.
Partial discharge starts due to small peeling voids, and dielectric breakdown occurs when a voltage above a certain level is applied. The partial discharge inception voltage is the value resulting from small flaking.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　比較例１～５においては、板本体の残留応力を低減せずに、直流電解めっき法を実施し、次いでＰＲパルス電解めっき法を実施し、粗化めっき層を形成した。その結果、粗化めっき層の最表層から厚さ方向に６μｍの領域におけるＫＡＭ値が１．０以上である領域の面積率が１０％を超えており、粗化めっき層の最表面のＳｄｒ（展開界面面積率）が２０％未満となった。これらの比較例１～５においては、吸湿リフロー後の部分放電開始電圧が低く、回路層（金属基板）と絶縁樹脂層との密着性が不十分であった。 In Comparative Examples 1 to 5, the DC electroplating method was performed without reducing the residual stress of the plate body, and then the PR pulse electroplating method was performed to form a roughened plating layer. As a result, the area ratio of the region having a KAM value of 1.0 or more in the region of 6 μm in the thickness direction from the outermost layer of the roughened plating layer exceeded 10%, and the Sdr ( developed interface area ratio) was less than 20%. In Comparative Examples 1 to 5, the partial discharge inception voltage after moisture absorption reflow was low, and the adhesion between the circuit layer (metal substrate) and the insulating resin layer was insufficient.
　本発明例１～１２においては、化学研磨によって板本体の残留応力を低減し、直流電解めっき法を実施し、次いでＰＲパルス電解めっき法を実施し、粗化めっき層を形成した。その結果、粗化めっき層の最表層から厚さ方向に６μｍの領域におけるＫＡＭ値が１．０以上である領域の面積率が１０％以下となり、粗化めっき層の最表面のＳｄｒ（展開界面面積率）が２０％以上となった。これらの本発明例１～１２においては、吸湿リフロー後の部分放電開始電圧が高く、回路層（金属基板）と絶縁樹脂層とが十分に密着していた。 In Examples 1 to 12 of the present invention, the residual stress of the plate body was reduced by chemical polishing, DC electroplating was performed, and then PR pulse electroplating was performed to form a roughened plating layer. As a result, the area ratio of the region where the KAM value is 1.0 or more in the region of 6 μm in the thickness direction from the outermost layer of the roughened plating layer is 10% or less, and the Sdr (development interface) of the outermost surface of the roughened plating layer area ratio) was 20% or more. In Examples 1 to 12 of the present invention, the partial discharge inception voltage after moisture absorption reflow was high, and the circuit layer (metal substrate) and the insulating resin layer were sufficiently adhered.
　以上の実験結果から、本発明例によれば、積層した樹脂部材との密着性に優れる金属板材、この金属板材と樹脂部材とが積層された積層体、および、絶縁回路基板を提供可能であることが確認された。 From the above experimental results, according to the example of the present invention, it is possible to provide a metal plate material having excellent adhesion to a laminated resin member, a laminate in which the metal plate material and the resin member are laminated, and an insulated circuit board. was confirmed.
　本実施形態の金属板材は、積層した樹脂部材との密着性に優れる。このため、本実施形態の金属板材と樹脂部材が積層された積層体や絶縁回路基板は、パワーモジュール、ＬＥＤモジュールおよび熱電モジュールに好適に適用される。 The metal plate material of this embodiment has excellent adhesion to laminated resin members. Therefore, the laminate and the insulating circuit board in which the metal plate material and the resin member are laminated according to the present embodiment are suitably applied to power modules, LED modules, and thermoelectric modules.
１０　絶縁回路基板（積層体）
１１　金属基板
１２　絶縁樹脂層（樹脂部材）
１３　回路層
３０　金属板材
３１　板本体
３５　粗化めっき層
３６　凸部
３６ａ　拡幅部 10 Insulated circuit board (laminate)
11 metal substrate 12 insulating resin layer (resin member)
13 Circuit layer 30 Metal plate material 31 Plate main body 35 Rough plating layer 36 Convex portion 36a Widened portion

Claims (6)

  1. 　板本体と、この板本体の最表層に形成された粗化めっき層と、を有し、
    　前記粗化めっき層には、前記板本体とは反対側に向けて突出する凸部が形成されており、
    　前記粗化めっき層の最表層から厚さ方向に６μｍの領域において、ＫＡＭ値が１．０以上である領域の面積率が１０％以下とされており、
    　前記粗化めっき層の最表面のＳｄｒ（展開界面面積率）が２０％以上であるか、または前記粗化めっき層の最表面のＲ（展開界面線長率）が４０％以上であることを特徴とする金属板材。     Having a plate body and a roughened plating layer formed on the outermost layer of the plate body,
    The roughened plating layer is formed with a convex portion that protrudes toward the side opposite to the plate body,
    In a region of 6 μm in the thickness direction from the outermost layer of the roughened plating layer, the area ratio of the region having a KAM value of 1.0 or more is 10% or less,
    Sdr (developed interface area ratio) of the outermost surface of the roughened plating layer is 20% or more, or R (developed interface line length ratio) of the outermost surface of the roughened plating layer is 40% or more. A metal plate material characterized by:
  2. 　前記凸部は、突出方向の先端側に向かうにしたがい漸次幅が広くなる拡幅部を備えていることを特徴とする請求項１に記載の金属板材。 The metal plate material according to claim 1, wherein the convex portion has a widened portion whose width gradually increases toward the tip side in the projecting direction.
  3. 　前記板本体が、銅又は銅合金で構成されていることを特徴とする請求項１又は請求項２に記載の金属板材。 The metal plate material according to claim 1 or claim 2, wherein the plate body is made of copper or a copper alloy.
  4. 　請求項１から請求項３のいずれか一項に記載の金属板材の板面に、樹脂部材が積層された積層体であって、
    　前記樹脂部材と前記金属板材との接合界面においては、前記金属板材の前記凸部に前記樹脂部材が係合していることを特徴とする積層体。     A laminate in which a resin member is laminated on the plate surface of the metal plate material according to any one of claims 1 to 3,
    A laminated body, wherein the resin member is engaged with the convex portion of the metal plate at a joint interface between the resin member and the metal plate.
  5. 　絶縁樹脂層と、前記絶縁樹脂層の一方の面に形成された回路層と、を備えた絶縁回路基板であって、
    　前記回路層は、請求項１から請求項３のいずれか一項に記載の金属板材を、前記絶縁樹脂層の一方の面に接合することにより形成されており、
    　前記絶縁樹脂層と前記回路層との接合界面においては、前記金属板材の前記凸部に前記絶縁樹脂層が係合していることを特徴とする絶縁回路基板。     An insulated circuit board comprising an insulating resin layer and a circuit layer formed on one surface of the insulating resin layer,
    The circuit layer is formed by bonding the metal plate material according to any one of claims 1 to 3 to one surface of the insulating resin layer,
    An insulated circuit board, wherein the insulated resin layer is engaged with the convex portion of the metal plate material at the bonding interface between the insulated resin layer and the circuit layer.
  6. 　絶縁樹脂層と、前記絶縁樹脂層の一方の面に形成された回路層と、前記絶縁樹脂層の他方の面に形成された金属基板と、を備えた絶縁回路基板であって、
    　前記回路層及び前記金属基板のいずれか一方又は両方は、請求項１から請求項３のいずれか一項に記載の金属板材を、前記絶縁樹脂層の面に接合することにより形成されており、
    　前記絶縁樹脂層と前記回路層との接合界面、及び前記絶縁樹脂層と前記金属基板との接合界面のうち、いずれか一方又は両方においては、前記金属板材の前記凸部に前記絶縁樹脂層が係合していることを特徴とする絶縁回路基板。     An insulated circuit board comprising an insulating resin layer, a circuit layer formed on one surface of the insulating resin layer, and a metal substrate formed on the other surface of the insulating resin layer,
    Either one or both of the circuit layer and the metal substrate are formed by bonding the metal plate material according to any one of claims 1 to 3 to the surface of the insulating resin layer,
    At one or both of the bonding interface between the insulating resin layer and the circuit layer and the bonding interface between the insulating resin layer and the metal substrate, the insulating resin layer is formed on the convex portion of the metal plate material. An insulated circuit board characterized by being engaged.
PCT/JP2022/013103 2021-03-26 2022-03-22 Metal plate, laminate, and insulated circuit board WO2022202795A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001073171A (en) * 1999-09-06 2001-03-21 Mitsui Mining & Smelting Co Ltd Face-regulated electrolytic copper foil, its production and its use
JP2020163650A (en) * 2019-03-29 2020-10-08 三菱マテリアル株式会社 Joined body, and insulation circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001073171A (en) * 1999-09-06 2001-03-21 Mitsui Mining & Smelting Co Ltd Face-regulated electrolytic copper foil, its production and its use
JP2020163650A (en) * 2019-03-29 2020-10-08 三菱マテリアル株式会社 Joined body, and insulation circuit board

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