WO2022199189A1 - Gate drive module, method for generating gate control signal, and display apparatus - Google Patents

Gate drive module, method for generating gate control signal, and display apparatus Download PDF

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Publication number
WO2022199189A1
WO2022199189A1 PCT/CN2021/142900 CN2021142900W WO2022199189A1 WO 2022199189 A1 WO2022199189 A1 WO 2022199189A1 CN 2021142900 W CN2021142900 W CN 2021142900W WO 2022199189 A1 WO2022199189 A1 WO 2022199189A1
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WIPO (PCT)
Prior art keywords
buffer
shift
control signal
output
circuit
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PCT/CN2021/142900
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French (fr)
Chinese (zh)
Inventor
彭格格
余思慧
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重庆惠科金渝光电科技有限公司
惠科股份有限公司
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Publication of WO2022199189A1 publication Critical patent/WO2022199189A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present application relates to the field of display technology, and in particular, to a gate driving module, a method for generating a gate control signal, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display
  • the main driving principle of TFT-LCD is that the system motherboard connects the R/G/B compression signal, control signal and power supply to the connector on the printed circuit board through wires, and the data passes through the timing controller (Timing Controller, TCON) on the printed circuit board. ) after processing, connect with the display area through the source-level thin film driver chip (Source-Chip on Film, S-COF) and the gate thin film driver chip (Gate-Chip on Film, G-COF), so that the liquid crystal display can obtain the required power and signal.
  • TCON Timing Controller
  • the gate driver chip mainly accepts the control signal of TCON. With this control signal, it outputs the low level (VGL) and the high level (VGH) that drive the display panel through the level shifter.
  • VGH is the control signal.
  • the voltage at which the TFT is turned on, and VGL is the voltage that controls the turn-off of the TFT.
  • the output VGH and VGL are connected to the inside of the panel through the output buffer. Multiple level shifters corresponding to the gate lines inside the display panel are required, but this setting occupies The area of the gate driving chip is too large and the cost is high.
  • the purpose of the present application is to provide a gate driving module, a method for generating a gate control signal and a display device, which saves the area of the gate driving chip, simplifies the internal circuit design of the gate driving chip, and reduces the size of the gate driving chip. cost.
  • the present application discloses a gate driving module.
  • the gate driving module includes a first input terminal for receiving a first control signal, a second input terminal for receiving a clock signal, and a logic control signal generated by receiving the first control signal and the clock signal.
  • the buffer circuit simultaneously receives the first control signal output from the level conversion circuit and the clock signal output from the second input terminal;
  • the gate driving module includes a gate line coupled to the shift output buffer circuit; wherein,
  • the shift output buffer circuit includes a plurality of cascaded shift buffers, each of the shift output buffer units generates a gate control signal according to the second control signal and the corresponding clock signal and outputs it to the shift output buffer. the gate line.
  • the present application also discloses a method for generating a gate control signal, comprising the steps of:
  • the gate control signal of the first gate line is shifted step by step, and the gate control signal of the Nth gate line is respectively generated and output to the corresponding Nth gate line in the display panel;
  • N is a natural number greater than or equal to 2; the low level and high level of the second control signal are preset low level and high level for driving the display panel.
  • the present application also discloses a display device, the display device includes a display panel, and a gate driving module drivingly connected to the display panel, the gate driving module includes a first input terminal for receiving a first control signal, a clock receiving a second input end of the signal, a logic control circuit for receiving the first control signal and the clock signal to generate a logic control signal, a level conversion circuit, and a shift output buffer circuit for receiving the clock signal; the input end of the logic control circuit is connected to the a first input terminal and a second input terminal are coupled, and the logic control circuit generates a logic control signal by receiving the first control signal input from the first input terminal and the clock signal input from the second input terminal; The input end of the level conversion circuit is coupled to the output end of the logic control circuit, and the logic control signal is level-converted to generate a second control signal; the shift output buffer circuit is connected to the second control signal.
  • the input end and the output end of the level shift circuit are coupled, and the shift buffer circuit simultaneously receives the first control signal output by the level shift circuit and the clock signal output by the second input end; gate driving The module includes a gate line coupled to the shift output buffer circuit; wherein the shift output buffer circuit includes a plurality of cascaded shift buffers, each of the shift output buffer units according to the first The two control signals and the corresponding clock signal generate gate control signals and output them to the gate lines.
  • the gate driving module of the present application first generates the second control signal by passing the first control signal through the level conversion circuit, and the second control signal passes through the shift buffer.
  • the circuit then generates multiple gate control signals corresponding to the gate lines; because the level shift is performed first and then the shift is performed, multiple level shifters corresponding to the internal gate lines of the display panel are not required, and it is only necessary to set
  • One level converter can achieve the above effects, which greatly saves the area of the gate driving chip, simplifies the internal circuit design of the gate driving chip, and reduces the cost of the gate driving chip.
  • FIG. 1 is a schematic structural diagram of a gate driving module according to an embodiment of the present application
  • FIG. 2 is a schematic circuit diagram of a gate driving module according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of timing waveforms according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a circuit of a gate driving module according to another embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a method for generating a gate control signal according to another embodiment of the present application.
  • first and second are for descriptive purposes only, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features.
  • a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • the term “comprising” and any variations thereof are intended to cover non-exclusive inclusion.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements.
  • a gate driving module 100 of a display panel includes a first input terminal 110 for receiving a first control signal, a clock receiving The second input terminal 120 of the signal, the logic control circuit 130 that receives the first control signal input from the first input terminal 110 and the clock signal input from the second input terminal 120 to generate a logic control signal, and the level The conversion circuit 140 and the shift output buffer circuit 150 receiving the clock signal input from the second input terminal 120 ; specifically, the input terminal of the logic control circuit 130 and the first input terminal 110 and the second input terminal 120 coupled, the logic control circuit 130 receives the first control signal input from the first input terminal 110 and the clock signal input from the second input terminal 120 to generate a logic control signal; the level conversion circuit The input end of 140 is coupled to the output end of the logic control circuit 130, and the logic control signal is level-converted to generate a second control signal; the shift output buffer circuit 150 is connected to the second input end 120 and the output terminal of the level
  • the shift output buffer circuit 150 includes a plurality of cascaded shift buffers 160; the input end of the level shift circuit 140 is coupled to the output end of the logic control circuit 130, and the level shift circuit 130
  • the circuit 140 performs level conversion of the logic control signal to generate a second control signal, and outputs it to the shift output buffer circuit 150; the low level and high level of the second control signal are preset to drive the The low level and the high level of the display panel, the shift output buffer circuit 150 respectively generates the gate control signal corresponding to the gate line in the display panel through the second control signal and the clock signal, because the power is performed first
  • the level conversion is shifted, there is no need for multiple level shifters corresponding to the gate lines inside the display panel, which greatly reduces the number of level shift circuits, saves the components required for the gate drive module, and reduces the The chip area is reduced, thereby reducing the chip cost of the gate drive module.
  • the low level and high level for driving the display panel are mainly obtained by conversion by the level conversion circuit.
  • the level conversion circuit includes a high-level signal receiving end and a low-level signal receiving end, respectively. After receiving the high level signal and the low level signal, the level conversion circuit performs level conversion on the logic control signal according to the high level signal and the low level signal to generate a second control signal.
  • the level shift circuit includes a level shifter, and the level shifter converts the logic control signal output by the first flip-flop into a second control signal and outputs it to the shift output buffer circuit.
  • the shift output buffer circuit 150 includes a plurality of cascaded shift buffers 160, and the first shift buffer 160 of the shift output buffer circuit directly outputs the second control signal as a gate control signal to the corresponding first gate line in the display panel; specifically, the first shift buffer 160 of the shift output buffer circuit includes a buffer 161, and the input end of the buffer 162 is directly The output terminal of the level conversion circuit 140 is connected, and the output terminal of the buffer 162 outputs the gate control signal corresponding to the first gate line in the display panel, and the first one of the shift The output terminal of the buffer 160 is directly connected to the input terminal of the second shift buffer 160 .
  • the internal structure of the shift buffer 160 cascaded with the first shift buffer is the same.
  • N shift buffers as an example (the N is a natural number greater than or equal to 2)
  • the Nth The control terminals of the shift buffers 160 are connected to the second input terminal 120 ; the input terminals of the Nth shift buffers 160 are connected to the output terminals of the N-1th shift buffer 160 ,
  • the output terminal of the Nth shift buffer 160 outputs the gate control signal corresponding to the Nth gate line in the display panel 200 , and the output terminal of the Nth shift buffer is connected to The input terminal of the N+1th said shift buffer.
  • the cascaded shift buffers 160 can realize the function of shifting, and generate and output gate control signals corresponding to the gate lines in the display panel according to the corresponding clock signal and the second control signal. After the gate control signal is output to the display panel, the N+1th shift buffer generates the N+1th gate control signal according to the Nth gate control signal and the corresponding N+1th clock signal and outputs it to the display panel. Display panel.
  • the Nth shift buffer 160 includes a flip-flop 161 and a buffer 162; the buffer in the Nth shift buffer The same buffer as the first said shift buffer can be used.
  • the buffers in the first shift buffer to the buffers in the Nth shift buffer are sequentially the first buffer (Output buffer 1)...the Nth buffer (Output buffer n), the control end of the flip-flop 161 of the Nth shift buffer 160 is connected to the second input end 120; the control end of the flip-flop 161 of the Nth shift buffer 161
  • the output end is connected to the input end of the buffer (Output buffer n) of the Nth shift buffer; the output end of the buffer of the Nth shift buffer 160 outputs and the display panel
  • the gate control signal of the corresponding Nth gate line in the Nth shift buffer 160, and the output end of the buffer of the Nth shift buffer 160 is connected to the N+1th shift buffer.
  • the Nth shift buffer further includes a voltage stabilizing circuit, and the voltage stabilizing circuit includes a capacitor; the voltage stabilizing circuit is connected to the current shift buffer.
  • N is a natural number greater than or equal to 1, and each of the shift buffers includes a capacitor. The setting of the capacitor can help the shift buffer maintain the previous output voltage.
  • the logic control circuit 130 may be a first flip-flop 131, the first flip-flop 131 is a rising edge flip-flop, and the control end of the first flip-flop 131 is connected to the The second input terminal 120, the input terminal of the first flip-flop 131 is connected to the first input terminal 110, the output terminal of the first flip-flop 131 is connected to the input terminal of the level conversion circuit 140, and the first flip-flop 131 is connected to the input terminal of the level conversion circuit 140.
  • the output terminal of a flip-flop 131 outputs the logic control signal to the level conversion circuit 140; the flip-flop in the Nth shift buffer can be selected from the same flip-flop as the first flip-flop 131, As shown in FIG. 2 , the buffers in the first flip-flop 131 to the N-th shift buffer are sequentially designated as the first flip-flop ( D1 ) . . . the N-th flip-flop (Dn).
  • the level converter 141 converts the input terminal voltage into a required voltage for output according to the first control signal (such as the frame start signal STV); output buffer1, output buffer2, output buffer3...output buffer n is a buffer
  • the controller 162 is capable of not only outputting the second control signal, but also amplifying the output.
  • D1, D2, D3, ..., Dn are rising edge flip-flops 161, whose function is to assign the logic potential of the D terminal to Q when the control terminal CLK terminal receives the rising edge of the signal;
  • CLK1, CLK2...CLKn Provide the first, second, third...nth control signal for the timing control chip;
  • C1, C2, C3...Cn are the stabilizing capacitors output by the buffer.
  • the D1 flip-flop input is a square wave signal as shown in Figure 2, the low level
  • the square wave signal (the first control signal) with the high level of 0V to 3.3V is converted into the square wave signal (the second control signal) from VGL to VGH through the level shifter 141, and the square wave signal passes through the shift output buffer.
  • a gate control signal is generated and input into the display panel to drive the TFT to be turned on and off.
  • the waveform of the gate control signal Output 1 corresponding to the first gate line is shown in FIG. 3 .
  • the D2 flip-flop When the rising edge of CLK2 comes, the D2 flip-flop outputs the input gate-output1 to the output buffer2, thereby outputting the gate-output 2 waveform.
  • gate-output n When gate-output n is output normally, gate-output1, gate-output2, ..., gate-output n-1 can output normally more stably because of the function of its voltage-stabilizing capacitor.
  • the gate drive module can start to work normally.
  • the complexity of the internal circuit of the gate drive module is simplified, and n-1 level converters and bidirectional shift register modules are saved, saving The area of the gate driving chip where the gate driving module is located, thereby saving the cost of manufacturing the gate driving chip.
  • the first control signal can be a frame start signal (STV), but is not limited to being a frame start signal, and can also be an ordinary AC signal, as long as the gate control signal can be activated time.
  • the first control signal may be output by a timing control chip (TCON) in the display panel, but in the future with different circuit structures, the AC signal or STV signal here may not be limited to output by the timing control chip.
  • TCON timing control chip
  • the first shift buffer 160 directly converts the first The two control signals are output as gate control signals to the corresponding first gate line in the display panel, and the output end of the first shift buffer 160 is directly connected to the second shift buffer. input.
  • the Nth (N is a natural number greater than or equal to 2) the shift buffer 160 includes a flip-flop 170, and the control terminal of the flip-flop of the Nth shift buffer is connected to the second input terminal;
  • the input segments of the flip-flops 170 of the N shift buffers 160 are connected to the outputs of the flip-flops of the N-1th shift buffer;
  • the Nth shift buffer The output terminal of the flip-flop 170 of 160 outputs a gate control signal corresponding to the Nth gate line in the display panel, and the Nth flip-flop 170 of the shift buffer 160 outputs a gate control signal.
  • the output terminal is connected to the input terminal of the flip-flop 170 of the N+1th shift buffer 160 .
  • the level converter performs level conversion on the logic control signal to generate a second control signal, and outputs it to the shift output buffer unit; the shift output buffer unit passes the second control signal and the The clock signals respectively generate gate control signals corresponding to the gate lines in the display panel, and no buffers are needed for amplification, so that the number of buffers can also be saved.
  • a method for generating a gate control signal corresponding to the above gate driving module including the steps of:
  • S1 receive the first control signal and the clock signal, and generate a logic control signal
  • S3 generate a gate control signal of the first gate line according to the second control signal and the clock signal, and output it to the corresponding first gate line in the display panel;
  • the low level and high level of the second control signal are preset low level and high level for driving the display panel.
  • the present application further discloses a display device 300 .
  • the display device 300 includes a display panel 200 , and at least one drive connected to the display panel is as described above.
  • the gate driving module 100 , the gate driving modules 100 jointly generate gate control signals and output them to the corresponding gate lines 210 in the display panel 200 .
  • the panel of the present application can be a TN panel (the full name is Twisted Nematic, that is, a twisted nematic panel), an IPS panel (In-Plane Switching, plane switching), a VA panel (Multi-domain Vertica Alignment, multi-quadrant vertical alignment technology), Of course, other types of panels may also be used, as applicable.
  • TN panel the full name is Twisted Nematic, that is, a twisted nematic panel
  • IPS panel In-Plane Switching, plane switching
  • VA panel Multi-domain Vertica Alignment, multi-quadrant vertical alignment technology

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  • Computer Hardware Design (AREA)
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Abstract

A gate drive module (100), comprising a logic control circuit (130), which receives a first control signal and a clock signal to generate a logic control signal, a level conversion circuit (140), and a shift output buffer circuit (150), which receives the clock signal, wherein the level conversion circuit (140) performs level conversion on the logic control signal to generate a second control signal, and outputs the second control signal to the shift output buffer circuit (150); and the shift output buffer circuit (150) respectively generates, by means of the second control signal and the clock signal, a gate control signal corresponding to a gate line (210) in a display panel (200).

Description

栅极驱动模块、栅极控制信号的生成方法和显示装置Gate driving module, method for generating gate control signal, and display device
本申请要求于2021年3月22日提交中国专利局、申请号为202110301058X、申请名称为“一种栅极驱动模块、栅极控制信号的生成方法和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims the priority of the Chinese patent application filed on March 22, 2021, with the application number 202110301058X, and the application title is "A gate driver module, a method for generating gate control signals, and a display device", The entire contents of which are incorporated herein by reference.
技术领域technical field
本申请涉及显示技术领域，尤其涉及一种栅极驱动模块、栅极控制信号的生成方法和显示装置。The present application relates to the field of display technology, and in particular, to a gate driving module, a method for generating a gate control signal, and a display device.
背景技术Background technique
这里的陈述仅提供与本申请有关的背景信息,而不必然地构成现有技术。The statements herein merely provide background information related to the present application and do not necessarily constitute prior art.
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)是当前平板显示的主要品种之一，已经成为了现代IT、视讯产品中重要的显示平台。TFT-LCD主要驱动原理，***主板将R/G/B压缩信号、控制信号及电源通过线材与印刷电路板上的连接器相连接，数据经过印刷电路板上的时序控制器(Timing Controller，TCON)处理后，通过源级薄膜驱动芯片(Source-Chip on Film，S-COF)和栅极薄膜驱动芯片(Gate-Chip on Film，G-COF)与显示区连接，从而使得液晶显示器获得所需的电源、信号。TFT-LCD (Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display) is one of the main varieties of current flat panel display, and has become an important display platform in modern IT and video products. The main driving principle of TFT-LCD is that the system motherboard connects the R/G/B compression signal, control signal and power supply to the connector on the printed circuit board through wires, and the data passes through the timing controller (Timing Controller, TCON) on the printed circuit board. ) after processing, connect with the display area through the source-level thin film driver chip (Source-Chip on Film, S-COF) and the gate thin film driver chip (Gate-Chip on Film, G-COF), so that the liquid crystal display can obtain the required power and signal.
目前栅极驱动芯片主要接受TCON的控制信号，配合这个控制信号，经过电平移位器(level shift)输出驱动所述显示面板的低电平(VGL)和高电平(VGH)，VGH是控制TFT打开的电压，VGL是控制TFT关闭的电压，输出的VGH和VGL经过输出缓冲器连接到面板内部，需要多个与显示面板内部栅极线一一对应的电平转换器，但如此设置占用栅极驱动芯片的面积过大，且成本较高。At present, the gate driver chip mainly accepts the control signal of TCON. With this control signal, it outputs the low level (VGL) and the high level (VGH) that drive the display panel through the level shifter. VGH is the control signal. The voltage at which the TFT is turned on, and VGL is the voltage that controls the turn-off of the TFT. The output VGH and VGL are connected to the inside of the panel through the output buffer. Multiple level shifters corresponding to the gate lines inside the display panel are required, but this setting occupies The area of the gate driving chip is too large and the cost is high.
发明内容SUMMARY OF THE INVENTION
本申请的目的是提供一种栅极驱动模块、栅极控制信号的生成方法和显示装置，节省栅极驱动芯片面积，而且还简化了栅极驱动芯片内部电路设计，也可以降低栅极驱动芯片成本。The purpose of the present application is to provide a gate driving module, a method for generating a gate control signal and a display device, which saves the area of the gate driving chip, simplifies the internal circuit design of the gate driving chip, and reduces the size of the gate driving chip. cost.
本申请公开了一种栅极驱动模块，所述栅极驱动模块包括接收第一控制信号的第一输入端、接收时钟信号的第二输入端、接收第一控制信号和时钟信号生成逻辑控制信号的逻辑控制电路、电平转换电路以及接收时钟信号的移位输出缓冲电路；所述逻辑控制电路的输入端与所述第一输入端以及第二输入端耦接，所述逻辑控制电路接收所述第一输入端输入的所述 第一控制信号和所述第二输入端输入的所述时钟信号生成逻辑控制信号；所述电平转换电路的输入端与所述逻辑控制电路的输出端耦接，将所述逻辑控制信号进行电平转换生成第二控制信号；所述移位输出缓冲电路，与所述第二输入端以及所述电平转换电路的输出端耦接，所述移位缓冲电路同时接收所述电平转换电路输出的第一控制信号和所述第二输入端输出的时钟信号；栅极驱动模块包括与所述移位输出缓冲电路耦接的栅极线；其中，所述移位输出缓冲电路包括多个级联的移位缓冲器，每个所述移位输出缓冲单元根据所述第二控制信号以及对应的所述时钟信号生成栅极控制信号并输出至所述栅极线。The present application discloses a gate driving module. The gate driving module includes a first input terminal for receiving a first control signal, a second input terminal for receiving a clock signal, and a logic control signal generated by receiving the first control signal and the clock signal. A logic control circuit, a level conversion circuit and a shift output buffer circuit for receiving a clock signal; the input end of the logic control circuit is coupled to the first input end and the second input end, and the logic control circuit receives the The first control signal input from the first input terminal and the clock signal input from the second input terminal generate a logic control signal; the input terminal of the level conversion circuit is coupled to the output terminal of the logic control circuit Then, perform level conversion on the logic control signal to generate a second control signal; the shift output buffer circuit is coupled with the second input terminal and the output terminal of the level conversion circuit, and the shift output buffer circuit is coupled with the second input terminal and the output terminal of the level conversion circuit. The buffer circuit simultaneously receives the first control signal output from the level conversion circuit and the clock signal output from the second input terminal; the gate driving module includes a gate line coupled to the shift output buffer circuit; wherein, The shift output buffer circuit includes a plurality of cascaded shift buffers, each of the shift output buffer units generates a gate control signal according to the second control signal and the corresponding clock signal and outputs it to the shift output buffer. the gate line.
本申请还公开了一种栅极控制信号的生成方法，包括步骤：The present application also discloses a method for generating a gate control signal, comprising the steps of:
接收第一控制信号和时钟信号，生成逻辑控制信号；receiving a first control signal and a clock signal to generate a logic control signal;
将所述逻辑控制信号进行电平转换生成第二控制信号；performing level conversion on the logic control signal to generate a second control signal;
根据第二控制信号和时钟信号，生成第1条栅极线的栅极控制信号，并输出至所述显示面板内的对应的第1条栅极线；以及generating a gate control signal of the first gate line according to the second control signal and the clock signal, and outputting it to the corresponding first gate line in the display panel; and
根据第1条栅极线的栅极控制信号逐级移位，分别生成第N条栅极线的栅极控制信号，并输出至所述显示面板内的对应的第N条栅极线；According to the gate control signal of the first gate line, the gate control signal is shifted step by step, and the gate control signal of the Nth gate line is respectively generated and output to the corresponding Nth gate line in the display panel;
其中，N为大于等于2的自然数；所述第二控制信号的低电平和高电平为预设的驱动所述显示面板的低电平和高电平。Wherein, N is a natural number greater than or equal to 2; the low level and high level of the second control signal are preset low level and high level for driving the display panel.
本申请还公开了显示装置，所述显示装置包括显示面板，以及与所述显示面板驱动连接的栅极驱动模块，所述栅极驱动模块包括接收第一控制信号的第一输入端、接收时钟信号的第二输入端、接收第一控制信号和时钟信号生成逻辑控制信号的逻辑控制电路、电平转换电路以及接收时钟信号的移位输出缓冲电路；所述逻辑控制电路的输入端与所述第一输入端以及第二输入端耦接，所述逻辑控制电路接收所述第一输入端输入的所述第一控制信号和所述第二输入端输入的所述时钟信号生成逻辑控制信号；所述电平转换电路的输入端与所述逻辑控制电路的输出端耦接，将所述逻辑控制信号进行电平转换生成第二控制信号；所述移位输出缓冲电路，与所述第二输入端以及所述电平转换电路的输出端耦接，所述移位缓冲电路同时接收所述电平转换电路输出的第一控制信号和所述第二输入端输出的时钟信号；栅极驱动模块包括与所述移位输出缓冲电路耦接的栅极线；其中，所述移位输出缓冲电路包括多个级联的移位缓冲器，每个所述移位输出缓冲单元根据所述第二控制信号以及对应的所述时钟信号生成栅极控制信号并输出至所述栅极线。The present application also discloses a display device, the display device includes a display panel, and a gate driving module drivingly connected to the display panel, the gate driving module includes a first input terminal for receiving a first control signal, a clock receiving a second input end of the signal, a logic control circuit for receiving the first control signal and the clock signal to generate a logic control signal, a level conversion circuit, and a shift output buffer circuit for receiving the clock signal; the input end of the logic control circuit is connected to the a first input terminal and a second input terminal are coupled, and the logic control circuit generates a logic control signal by receiving the first control signal input from the first input terminal and the clock signal input from the second input terminal; The input end of the level conversion circuit is coupled to the output end of the logic control circuit, and the logic control signal is level-converted to generate a second control signal; the shift output buffer circuit is connected to the second control signal. The input end and the output end of the level shift circuit are coupled, and the shift buffer circuit simultaneously receives the first control signal output by the level shift circuit and the clock signal output by the second input end; gate driving The module includes a gate line coupled to the shift output buffer circuit; wherein the shift output buffer circuit includes a plurality of cascaded shift buffers, each of the shift output buffer units according to the first The two control signals and the corresponding clock signal generate gate control signals and output them to the gate lines.
相对于之前先移位后进行电平转换的方案来说，本申请的栅极驱动模块先将第一控制信号通过电平转换电路生成第二控制信号，所述第二控制信号通过移位缓冲电路再生成多个与栅极线对应的栅极控制信号；因为先进行电平转换后再移位，不需要多个与显示面板内部栅极线一一对应的电平转换器，只需要设置一个电平转换器即可实现上述效果，大大节省了栅 极驱动芯片面积，而且还简化了栅极驱动芯片内部电路设计，降低栅极驱动芯片成本。Compared with the previous scheme of first shifting and then performing level conversion, the gate driving module of the present application first generates the second control signal by passing the first control signal through the level conversion circuit, and the second control signal passes through the shift buffer. The circuit then generates multiple gate control signals corresponding to the gate lines; because the level shift is performed first and then the shift is performed, multiple level shifters corresponding to the internal gate lines of the display panel are not required, and it is only necessary to set One level converter can achieve the above effects, which greatly saves the area of the gate driving chip, simplifies the internal circuit design of the gate driving chip, and reduces the cost of the gate driving chip.
附图说明Description of drawings
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, constitute a part of the specification, illustrate embodiments of the application, and together with the description, serve to explain the principles of the application. Obviously, the drawings in the following description are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort. In the attached image:
图1是本申请的一实施例的一种栅极驱动模块的结构示意图；FIG. 1 is a schematic structural diagram of a gate driving module according to an embodiment of the present application;
图2是本申请的一实施例的一种栅极驱动模块的电路示意图；FIG. 2 is a schematic circuit diagram of a gate driving module according to an embodiment of the present application;
图3是本申请的一实施例的时序波形示意图；3 is a schematic diagram of timing waveforms according to an embodiment of the present application;
图4是本申请的另一实施例的一种栅极驱动模块的电路的示意图；4 is a schematic diagram of a circuit of a gate driving module according to another embodiment of the present application;
图5是本申请的另一实施例的栅极控制信号的生成方法的流程示意图。FIG. 5 is a schematic flowchart of a method for generating a gate control signal according to another embodiment of the present application.
具体实施方式Detailed ways
这里所公开的具体结构和功能细节仅仅是代表性的，并且是描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。Specific structural and functional details disclosed herein are merely representative and for purposes of describing example embodiments of the present application. The application may, however, be embodied in many alternative forms and should not be construed as limited only to the embodiments set forth herein.
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。In the description of this application, it should be understood that the terms "center", "lateral", "top", "bottom", "left", "right", "vertical", "horizontal", "top", The orientation or positional relationship indicated by "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying the indicated device. Or elements must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as a limitation of the present application. In addition, the terms "first" and "second" are for descriptive purposes only, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature. In the description of this application, unless stated otherwise, "plurality" means two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood in specific situations.
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文 明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the exemplary embodiments. As used herein, the singular forms "a", "an" and "an" are intended to include the plural unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and/or "comprising" as used herein specify the presence of stated features, integers, steps, operations, units and/or components, but do not preclude the presence or addition of one or more Other features, integers, steps, operations, units, components and/or combinations thereof.
下面结合附图和实施例对本申请作进一步说明。The present application will be further described below with reference to the accompanying drawings and embodiments.
如图1和图2所示，作为本申请的一实施例，公开了一种显示面板的栅极驱动模块100，栅极驱动模块100包括接收第一控制信号的第一输入端110、接收时钟信号的第二输入端120、接收所述第一输入端110输入的所述第一控制信号和所述第二输入端120输入的所述时钟信号生成逻辑控制信号的逻辑控制电路130、电平转换电路140以及接收所述第二输入端120输入的时钟信号的移位输出缓冲电路150；具体的，所述逻辑控制电路130的输入端与所述第一输入端110以及第二输入端120耦接，所述逻辑控制电路130接收所述第一输入端110输入的所述第一控制信号和所述第二输入端120输入的所述时钟信号生成逻辑控制信号；所述电平转换电路140的输入端与所述逻辑控制电路130的输出端耦接，将所述逻辑控制信号进行电平转换生成第二控制信号；所述移位输出缓冲电路150，与所述第二输入端120以及所述电平转换电路140的输出端耦接，所述移位缓冲电路150同时接收所述电平转换电路140输出的第一控制信号和所述第二输入端120输出的时钟信号；栅极驱动模块100包括与所述移位输出缓冲电路150耦接的栅极线210。As shown in FIG. 1 and FIG. 2 , as an embodiment of the present application, a gate driving module 100 of a display panel is disclosed. The gate driving module 100 includes a first input terminal 110 for receiving a first control signal, a clock receiving The second input terminal 120 of the signal, the logic control circuit 130 that receives the first control signal input from the first input terminal 110 and the clock signal input from the second input terminal 120 to generate a logic control signal, and the level The conversion circuit 140 and the shift output buffer circuit 150 receiving the clock signal input from the second input terminal 120 ; specifically, the input terminal of the logic control circuit 130 and the first input terminal 110 and the second input terminal 120 coupled, the logic control circuit 130 receives the first control signal input from the first input terminal 110 and the clock signal input from the second input terminal 120 to generate a logic control signal; the level conversion circuit The input end of 140 is coupled to the output end of the logic control circuit 130, and the logic control signal is level-converted to generate a second control signal; the shift output buffer circuit 150 is connected to the second input end 120 and the output terminal of the level conversion circuit 140 is coupled, the shift buffer circuit 150 simultaneously receives the first control signal output by the level conversion circuit 140 and the clock signal output by the second input terminal 120; The pole driving module 100 includes a gate line 210 coupled to the shift output buffer circuit 150 .
其中，所述移位输出缓冲电路150包括多个级联的移位缓冲器160；所述电平转换电路140的输入端与所述逻辑控制电路130的输出端耦接，所述电平转换电路140将所述逻辑控制信号进行电平转换生成第二控制信号，并输出至所述移位输出缓冲电路150；所述第二控制信号的低电平和高电平为预设的驱动所述显示面板的低电平和高电平，所述移位输出缓冲电路150通过所述第二控制信号和所述时钟信号分别生成与显示面板内栅极线对应的栅极控制信号，因为先进行电平转换后再移位，不需要多个与显示面板内部栅极线一一对应的电平转换器，大大减少了电平转换电路的数量，节省了栅极驱动模块所需的元器件，减小了芯片面积，从而降低栅极驱动模块的芯片成本。The shift output buffer circuit 150 includes a plurality of cascaded shift buffers 160; the input end of the level shift circuit 140 is coupled to the output end of the logic control circuit 130, and the level shift circuit 130 The circuit 140 performs level conversion of the logic control signal to generate a second control signal, and outputs it to the shift output buffer circuit 150; the low level and high level of the second control signal are preset to drive the The low level and the high level of the display panel, the shift output buffer circuit 150 respectively generates the gate control signal corresponding to the gate line in the display panel through the second control signal and the clock signal, because the power is performed first After the level conversion is shifted, there is no need for multiple level shifters corresponding to the gate lines inside the display panel, which greatly reduces the number of level shift circuits, saves the components required for the gate drive module, and reduces the The chip area is reduced, thereby reducing the chip cost of the gate drive module.
本申请要得到驱动所述显示面板的低电平和高电平主要靠所述电平转换电路进行转换得到，所述电平转换电路包括高电平信号接收端和低电平信号接收端，分别接收高电平信号和低电平信号，所述电平转换电路根据高电平信号和低电平信号，将所述逻辑控制信号进行电平转换生成第二控制信号。所述电平转换电路包括电平转换器，电平转换器将第一触发器输出的逻辑控制信号转换为第二控制信号输出至移位输出缓冲电路。In the present application, the low level and high level for driving the display panel are mainly obtained by conversion by the level conversion circuit. The level conversion circuit includes a high-level signal receiving end and a low-level signal receiving end, respectively. After receiving the high level signal and the low level signal, the level conversion circuit performs level conversion on the logic control signal according to the high level signal and the low level signal to generate a second control signal. The level shift circuit includes a level shifter, and the level shifter converts the logic control signal output by the first flip-flop into a second control signal and outputs it to the shift output buffer circuit.
所述移位输出缓冲电路150包括多个级联的移位缓冲器160，所述移位输出缓冲电路的第1个所述移位缓冲器160直接将第二控制信号作为栅极控制信号输出至所述显示面板内的 对应的第1条栅极线；具体的，所述移位输出缓冲电路第1个所述移位缓冲器160包括缓冲器161，所述缓冲器162的输入端直接连接所述电平转换电路140的输出端，所述缓冲器162的输出端输出与所述显示面板内的对应的第1条栅极线的栅极控制信号，且第1个所述移位缓冲器160的输出端直接连接第2个所述移位缓冲器160的输入端。The shift output buffer circuit 150 includes a plurality of cascaded shift buffers 160, and the first shift buffer 160 of the shift output buffer circuit directly outputs the second control signal as a gate control signal to the corresponding first gate line in the display panel; specifically, the first shift buffer 160 of the shift output buffer circuit includes a buffer 161, and the input end of the buffer 162 is directly The output terminal of the level conversion circuit 140 is connected, and the output terminal of the buffer 162 outputs the gate control signal corresponding to the first gate line in the display panel, and the first one of the shift The output terminal of the buffer 160 is directly connected to the input terminal of the second shift buffer 160 .
之后与第一个所述移位缓冲器级联的移位缓冲器160的内部结构是相同的，以N个移位缓冲器为例(所述的N为大于等于2的自然数)，第N个所述移位缓冲器160的控制端连接所述第二输入端120；第N个所述移位缓冲器160的输入端连接第N-1个所述移位缓冲器160的输出端，第N个所述移位缓冲器160的输出端输出与所述显示面板200内的对应的第N条栅极线的栅极控制信号，且第N个所述移位缓冲器的输出端连接第N+1个所述移位缓冲器的输入端。级联的移位缓冲器160可以实现移位的功能，根据对应的时钟信号和第二控制信号生成与所述显示面板内栅极线对应的栅极控制信号并输出，当生成的第N个栅极控制信号输出到显示面板后，第N+1个移位缓冲器根据第N个栅极控制信号和对应的第N+1个的时钟信号生成第N+1个栅极控制信号输出到显示面板。Afterwards, the internal structure of the shift buffer 160 cascaded with the first shift buffer is the same. Taking N shift buffers as an example (the N is a natural number greater than or equal to 2), the Nth The control terminals of the shift buffers 160 are connected to the second input terminal 120 ; the input terminals of the Nth shift buffers 160 are connected to the output terminals of the N-1th shift buffer 160 , The output terminal of the Nth shift buffer 160 outputs the gate control signal corresponding to the Nth gate line in the display panel 200 , and the output terminal of the Nth shift buffer is connected to The input terminal of the N+1th said shift buffer. The cascaded shift buffers 160 can realize the function of shifting, and generate and output gate control signals corresponding to the gate lines in the display panel according to the corresponding clock signal and the second control signal. After the gate control signal is output to the display panel, the N+1th shift buffer generates the N+1th gate control signal according to the Nth gate control signal and the corresponding N+1th clock signal and outputs it to the display panel. Display panel.
与第1个所述移位缓冲器160的具体电路不同的是，第N个所述移位缓冲器160包括触发器161以及缓冲器162；第N个所述移位缓冲器里的缓冲器可采用与所述第1个所述移位缓冲器一样的缓冲器。图2中，第1个所述移位缓冲器里的缓冲器至第N个所述移位缓冲器里的缓冲器依次为第一个缓冲器(Output buffer 1)……第N个缓冲器(Output buffer n)，第N个所述移位缓冲器160的所述触发器161的控制端连接所述第二输入端120；第N个所述移位缓冲器的所述触发器161的输出端连接第N个所述移位缓冲器的所述缓冲器(Output buffer n)的输入端；第N个所述移位缓冲器160的所述缓冲器的输出端输出与所述显示面板内的对应的第N条栅极线的栅极控制信号，且第N个所述移位缓冲器160的所述缓冲器的输出端连接所述第N+1个所述移位缓冲器的所述触发器的输入端；第N个所述移位缓冲器的所述触发器的输入端连接所述第N-1个所述移位缓冲器的所述触发器161的输出端。Different from the specific circuit of the first shift buffer 160, the Nth shift buffer 160 includes a flip-flop 161 and a buffer 162; the buffer in the Nth shift buffer The same buffer as the first said shift buffer can be used. In FIG. 2, the buffers in the first shift buffer to the buffers in the Nth shift buffer are sequentially the first buffer (Output buffer 1)...the Nth buffer (Output buffer n), the control end of the flip-flop 161 of the Nth shift buffer 160 is connected to the second input end 120; the control end of the flip-flop 161 of the Nth shift buffer 161 The output end is connected to the input end of the buffer (Output buffer n) of the Nth shift buffer; the output end of the buffer of the Nth shift buffer 160 outputs and the display panel The gate control signal of the corresponding Nth gate line in the Nth shift buffer 160, and the output end of the buffer of the Nth shift buffer 160 is connected to the N+1th shift buffer. The input terminal of the flip-flop; the input terminal of the flip-flop of the Nth shift buffer is connected to the output terminal of the flip-flop 161 of the N-1th shift buffer.
为了保证移位缓冲器输出的电压的稳定性，第N个所述移位缓冲器还包括稳压电路，所述稳压电路包括电容；所述稳压电路连接在当前的所述移位缓冲器的输出端与地线之间，N为大于等于1的自然数，每个所述移位缓冲器内都包括一个电容。电容的设置可以帮助移位缓冲器维持之前的输出电压。In order to ensure the stability of the voltage output by the shift buffer, the Nth shift buffer further includes a voltage stabilizing circuit, and the voltage stabilizing circuit includes a capacitor; the voltage stabilizing circuit is connected to the current shift buffer. Between the output end of the device and the ground line, N is a natural number greater than or equal to 1, and each of the shift buffers includes a capacitor. The setting of the capacitor can help the shift buffer maintain the previous output voltage.
在上述的栅极驱动模块100中，所述逻辑控制电路130可以为第一触发器131，所述第一触发器131为上升沿触发器，所述第一触发器131的控制端连接所述第二输入端120，所述第一触发器131的输入端连接所述第一输入端110，所述第一触发器131的输出端连接所述电平转换电路140的输入端，所述第一触发器131的输出端输出所述逻辑控制信号至所述电平转换电路140；第N个所述移位缓冲器里的触发器可选用与所述第一触发器131一样的 触发器，如图2所示，第一触发器131至第N个所述移位缓冲器里的缓冲器依次标示为第一触发器(D1)……第N触发器器(Dn)。In the above gate driving module 100, the logic control circuit 130 may be a first flip-flop 131, the first flip-flop 131 is a rising edge flip-flop, and the control end of the first flip-flop 131 is connected to the The second input terminal 120, the input terminal of the first flip-flop 131 is connected to the first input terminal 110, the output terminal of the first flip-flop 131 is connected to the input terminal of the level conversion circuit 140, and the first flip-flop 131 is connected to the input terminal of the level conversion circuit 140. The output terminal of a flip-flop 131 outputs the logic control signal to the level conversion circuit 140; the flip-flop in the Nth shift buffer can be selected from the same flip-flop as the first flip-flop 131, As shown in FIG. 2 , the buffers in the first flip-flop 131 to the N-th shift buffer are sequentially designated as the first flip-flop ( D1 ) . . . the N-th flip-flop (Dn).
现参照图2的电路示意图和图3的时序波形示意图，对本方案进行进一步说明。其中所述电平转换器141，根据第一控制信号(如帧起始信号STV)将输入端电压转换成所需的电压进行输出；output buffer1、output buffer2、output buffer3……output buffer n是缓冲器162，其不仅能够输出第二控制信号，还有放大输出能力。D1、D2、D3、……、Dn为上升沿触发器161，其功能为当其控制端CLK端接收到讯号上升沿的时候，将其D端的逻辑电位赋值给Q；CLK1、CLK2……CLKn为时序控制芯片提供第一个、第二个、第三个……第n个的控制讯号；C1、C2、C3……Cn是缓冲器输出的稳压电容。The present solution will now be further described with reference to the schematic circuit diagram of FIG. 2 and the schematic diagram of timing waveforms of FIG. 3 . The level converter 141 converts the input terminal voltage into a required voltage for output according to the first control signal (such as the frame start signal STV); output buffer1, output buffer2, output buffer3...output buffer n is a buffer The controller 162 is capable of not only outputting the second control signal, but also amplifying the output. D1, D2, D3, ..., Dn are rising edge flip-flops 161, whose function is to assign the logic potential of the D terminal to Q when the control terminal CLK terminal receives the rising edge of the signal; CLK1, CLK2...CLKn Provide the first, second, third...nth control signal for the timing control chip; C1, C2, C3...Cn are the stabilizing capacitors output by the buffer.
设第一控制信号(STV信号)的起始状态为低电平L，当D1触发器接收到CLK1为上升沿时，D1触发器输入为方波信号如图2所示的信号，低电平高电平分别为0V到3.3V的方波信号(第一控制信号)经过电平转换器141转换成VGL到VGH的方波信号(第二控制信号)，此方波信号经过移位输出缓冲电路后生成栅极控制信号输入到显示面板内部，用来驱动TFT打开和关闭。所述第一根栅极线对应的栅极控制信号Output 1的波形如图3所示。Set the initial state of the first control signal (STV signal) as low level L, when the D1 flip-flop receives the rising edge of CLK1, the D1 flip-flop input is a square wave signal as shown in Figure 2, the low level The square wave signal (the first control signal) with the high level of 0V to 3.3V is converted into the square wave signal (the second control signal) from VGL to VGH through the level shifter 141, and the square wave signal passes through the shift output buffer. After the circuit, a gate control signal is generated and input into the display panel to drive the TFT to be turned on and off. The waveform of the gate control signal Output 1 corresponding to the first gate line is shown in FIG. 3 .
当CLK2的上升沿来时，D2触发器将输入的gate-output1输出给output buffer2，从而输出gate-output 2波形。以此类推，当gate-output n正常输出时，此时gate-output1、gate-output2、……、gate-output n-1因为其稳压电容的作用可以更稳定的正常输出。此时栅极驱动模块可以开始正常工作，在实现原有功能的基础上，简化了栅极驱动模块内部电路的复杂度，省掉n-1个电平转换器和双向移位寄存器模块，节省栅极驱动模块所在的栅极驱动芯片面积，从而节省了制作栅极驱动芯片的成本。When the rising edge of CLK2 comes, the D2 flip-flop outputs the input gate-output1 to the output buffer2, thereby outputting the gate-output 2 waveform. By analogy, when gate-output n is output normally, gate-output1, gate-output2, ..., gate-output n-1 can output normally more stably because of the function of its voltage-stabilizing capacitor. At this time, the gate drive module can start to work normally. On the basis of realizing the original function, the complexity of the internal circuit of the gate drive module is simplified, and n-1 level converters and bidirectional shift register modules are saved, saving The area of the gate driving chip where the gate driving module is located, thereby saving the cost of manufacturing the gate driving chip.
需要说明的是所述第一控制信号可以为帧起始信号(STV)，但并不仅限于为帧起始信号，也可以为一个普通的交流信号，只要能提现所述栅极控制信号的启动时间即可。所述第一控制信号可以由显示面板中的时序控制芯片(TCON)输出，但未来随着电路架构不同，这里的交流信号或STV信号可以不限于为时序控制芯片输出的。It should be noted that the first control signal can be a frame start signal (STV), but is not limited to being a frame start signal, and can also be an ordinary AC signal, as long as the gate control signal can be activated time. The first control signal may be output by a timing control chip (TCON) in the display panel, but in the future with different circuit structures, the AC signal or STV signal here may not be limited to output by the timing control chip.
如图1和图2所示，作为本申请的另一实施例，公开了另一种栅极驱动模块100，与上述实施例不同的是，第1个所述移位缓冲器160直接将第二控制信号作为栅极控制信号输出与所述显示面板内的对应的第1条栅极线，第1个所述移位缓冲器160的输出端直接连接第2个所述移位缓冲器的输入端。As shown in FIG. 1 and FIG. 2 , as another embodiment of the present application, another gate driving module 100 is disclosed. Different from the above embodiment, the first shift buffer 160 directly converts the first The two control signals are output as gate control signals to the corresponding first gate line in the display panel, and the output end of the first shift buffer 160 is directly connected to the second shift buffer. input.
第N(N为大于等于2的自然数)个所述移位缓冲器160包括触发器170，第N个所述移位缓冲器的所述触发器的控制端连接所述第二输入端；第N个所述移位缓冲器160的所述触发器170的输入段连接所述第N-1个所述移位缓冲器的所述触发器的输出端；第N个所述移位缓冲器160的所述触发器170的输出端输出与所述显示面板内的对应的第N条栅极线的 栅极控制信号，且第N个所述移位缓冲器160的所述触发器170的输出端连接所述第N+1个所述移位缓冲器160的所述触发器170的输入端。The Nth (N is a natural number greater than or equal to 2) the shift buffer 160 includes a flip-flop 170, and the control terminal of the flip-flop of the Nth shift buffer is connected to the second input terminal; The input segments of the flip-flops 170 of the N shift buffers 160 are connected to the outputs of the flip-flops of the N-1th shift buffer; the Nth shift buffer The output terminal of the flip-flop 170 of 160 outputs a gate control signal corresponding to the Nth gate line in the display panel, and the Nth flip-flop 170 of the shift buffer 160 outputs a gate control signal. The output terminal is connected to the input terminal of the flip-flop 170 of the N+1th shift buffer 160 .
对应的，电平转换器将所述逻辑控制信号进行电平转换生成第二控制信号，并输出至所述移位输出缓冲单元；所述移位输出缓冲单元通过所述第二控制信号和所述时钟信号分别生成与所述显示面板内栅极线对应的栅极控制信号，不需要缓冲器进行放大，如此还可以节省缓冲器的数量。Correspondingly, the level converter performs level conversion on the logic control signal to generate a second control signal, and outputs it to the shift output buffer unit; the shift output buffer unit passes the second control signal and the The clock signals respectively generate gate control signals corresponding to the gate lines in the display panel, and no buffers are needed for amplification, so that the number of buffers can also be saved.
如图4所示，作为本申请的另一实施例，公开了一种与上述栅极驱动模块对应的栅极控制信号的生成方法，包括步骤：As shown in FIG. 4 , as another embodiment of the present application, a method for generating a gate control signal corresponding to the above gate driving module is disclosed, including the steps of:
S1：接收第一控制信号和时钟信号，生成逻辑控制信号；S1: receive the first control signal and the clock signal, and generate a logic control signal;
S2：将所述逻辑控制信号进行电平转换生成第二控制信号；S2: perform level conversion on the logic control signal to generate a second control signal;
S3：根据第二控制信号和时钟信号，生成第1条栅极线的栅极控制信号，并输出至所述显示面板内的对应的第1条栅极线；S3: generate a gate control signal of the first gate line according to the second control signal and the clock signal, and output it to the corresponding first gate line in the display panel;
S4：根据第1条栅极线的栅极控制信号逐级移位，分别生成第N条栅极线的栅极控制信号，并输出至所述显示面板内的对应的第N条栅极线；S4: Shifting step by step according to the gate control signal of the first gate line, respectively generating the gate control signal of the Nth gate line, and outputting it to the corresponding Nth gate line in the display panel ;
其中，所述第二控制信号的低电平和高电平为预设的驱动所述显示面板的低电平和高电平。Wherein, the low level and high level of the second control signal are preset low level and high level for driving the display panel.
如图5所示，作为本申请的另一实施例，本申请还公开了一种显示装置300，所述显示装置300包括显示面板200，以及与所述显示面板驱动连接的至少一个如上所述的栅极驱动模块100，所述栅极驱动模块100共同生成栅极控制信号，并输出至所述显示面板200内的对应的栅极线210。As shown in FIG. 5 , as another embodiment of the present application, the present application further discloses a display device 300 . The display device 300 includes a display panel 200 , and at least one drive connected to the display panel is as described above. The gate driving module 100 , the gate driving modules 100 jointly generate gate control signals and output them to the corresponding gate lines 210 in the display panel 200 .
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。It should be noted that the limitations of the steps involved in this scheme are not considered to limit the sequence of steps without affecting the implementation of the specific scheme. The steps written in the front may be executed first. It can also be executed later, or even executed at the same time, as long as the solution can be implemented, it should be regarded as belonging to the protection scope of the present application.
本申请的面板可以是TN面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS面板(In-Plane Switching，平面转换)、VA面板(Multi-domain Vertica Alignment，多象限垂直配向技术)，当然，也可以是其他类型的面板，适用即可。The panel of the present application can be a TN panel (the full name is Twisted Nematic, that is, a twisted nematic panel), an IPS panel (In-Plane Switching, plane switching), a VA panel (Multi-domain Vertica Alignment, multi-quadrant vertical alignment technology), Of course, other types of panels may also be used, as applicable.
以上内容是结合具体的优选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。The above content is a further detailed description of the present application in conjunction with specific preferred embodiments, and it cannot be considered that the specific implementation of the present application is limited to these descriptions. For those of ordinary skill in the technical field of the present application, without departing from the concept of the present application, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present application.

Claims (19)

  1. 一种栅极驱动模块，包括：A gate drive module, comprising:
    第一输入端，接收第一控制信号；a first input end, receiving a first control signal;
    第二输入端，接收时钟信号；The second input terminal receives the clock signal;
    逻辑控制电路，所述逻辑控制电路的输入端与所述第一输入端以及第二输入端耦接，所述逻辑控制电路接收所述第一输入端输入的所述第一控制信号和所述第二输入端输入的所述时钟信号生成逻辑控制信号；a logic control circuit, the input end of the logic control circuit is coupled to the first input end and the second input end, the logic control circuit receives the first control signal input from the first input end and the The clock signal input by the second input terminal generates a logic control signal;
    电平转换电路，所述电平转换电路的输入端与所述逻辑控制电路的输出端耦接，将所述逻辑控制信号进行电平转换生成第二控制信号；a level conversion circuit, the input end of the level conversion circuit is coupled with the output end of the logic control circuit, and the logic control signal is level-converted to generate a second control signal;
    移位输出缓冲电路，与所述第二输入端以及所述电平转换电路的输出端耦接，所述移位缓冲电路同时接收所述电平转换电路输出的第一控制信号和所述第二输入端输出的时钟信号；以及a shift output buffer circuit, coupled to the second input terminal and the output terminal of the level shift circuit, the shift buffer circuit simultaneously receives the first control signal output by the level shift circuit and the first control signal output by the level shift circuit the clock signal output from the two input terminals; and
    栅极线，与所述移位输出缓冲电路耦接；a gate line, coupled to the shift output buffer circuit;
    其中，所述移位输出缓冲电路包括多个级联的移位缓冲器，每个所述移位输出缓冲单元根据所述第二控制信号以及对应的所述时钟信号生成一栅极控制信号并输出至所述栅极线。Wherein, the shift output buffer circuit includes a plurality of cascaded shift buffers, each of the shift output buffer units generates a gate control signal according to the second control signal and the corresponding clock signal, and generates a gate control signal. output to the gate line.
  2. 如权利要求1所述的一种栅极驱动模块，其中，所述移位输出缓冲电路的第1个所述移位缓冲器直接将第二控制信号作为栅极控制信号输出至所述显示面板内的对应的第1条栅极线；The gate driving module of claim 1, wherein the first shift buffer of the shift output buffer circuit directly outputs the second control signal to the display panel as a gate control signal The corresponding 1st gate line within;
    所述移位输出缓冲电路的第N个所述移位缓冲器的控制端连接所述第二输入端；第N个所述移位缓冲器的输入端连接第N-1个所述移位缓冲器的输出端，第N个所述移位缓冲器的输出端输出与所述显示面板内的对应的第N条栅极线的栅极控制信号，且第N个所述移位缓冲器的输出端连接第N+1个所述移位缓冲器的输入端；The control terminal of the Nth shift buffer of the shift output buffer circuit is connected to the second input terminal; the input terminal of the Nth shift buffer is connected to the N-1th shift buffer The output end of the buffer, the output end of the Nth shift buffer outputs a gate control signal corresponding to the Nth gate line in the display panel, and the Nth shift buffer The output terminal of is connected to the input terminal of the N+1th shift buffer;
    其中，所述的N为大于等于2的自然数。Wherein, the N is a natural number greater than or equal to 2.
  3. 如权利要求1所述的一种栅极驱动模块，其中，所述移位输出缓冲电路的第1个所述移位缓冲器直接将第二控制信号作为栅极控制信号输出与所述显示面板内的对应的第1条栅极线，第1个所述移位缓冲器的输出端直接连接第2个所述移位缓冲器的输入端；The gate driving module of claim 1, wherein the first shift buffer of the shift output buffer circuit directly outputs the second control signal as a gate control signal to the display panel For the corresponding first gate line in the first gate line, the output end of the first shift buffer is directly connected to the input end of the second shift buffer;
    所述移位输出缓冲电路的第N个所述移位缓冲器包括触发器，第N个所述移位缓冲器的所述触发器的控制端连接所述第二输入端；The Nth shift buffer of the shift output buffer circuit includes a flip-flop, and the control terminal of the flip-flop of the Nth shift buffer is connected to the second input terminal;
    第N个所述移位缓冲器的所述触发器的输入段连接所述第N-1个所述移位缓冲器的所述触发器的输出端；The input section of the flip-flop of the Nth shift buffer is connected to the output end of the flip-flop of the N-1th shift buffer;
    第N个所述移位缓冲器的所述触发器的输出端输出与所述显示面板内的对应的第N条栅 极线的栅极控制信号，且第N个所述移位缓冲器的所述触发器的输出端连接所述第N+1个所述移位缓冲器的所述触发器的输入端；The output end of the flip-flop of the Nth shift buffer outputs the gate control signal corresponding to the Nth gate line in the display panel, and the Nth shift buffer outputs the gate control signal. The output terminal of the flip-flop is connected to the input terminal of the flip-flop of the N+1th shift buffer;
    其中，所述的N为大于等于2的自然数。Wherein, the N is a natural number greater than or equal to 2.
  4. 如权利要求1所述的一种栅极驱动模块，其中，所述移位输出缓冲电路的第1个所述移位缓冲器包括缓冲器，所述缓冲器的输入端直接连接所述电平转换电路的输出端，所述缓冲器的输出端输出与所述显示面板内的对应的第1条栅极线的栅极控制信号，且第1个所述移位缓冲器的输出端直接连接第2个所述移位缓冲器的输入端；The gate driving module of claim 1, wherein the first shift buffer of the shift output buffer circuit comprises a buffer, and the input terminal of the buffer is directly connected to the level The output end of the conversion circuit, the output end of the buffer outputs the gate control signal corresponding to the first gate line in the display panel, and the output end of the first shift buffer is directly connected the input terminal of the second said shift buffer;
    所述移位输出缓冲电路的第N个所述移位缓冲器包括触发器以及缓冲器；The Nth shift buffer of the shift output buffer circuit includes a flip-flop and a buffer;
    第N个所述移位缓冲器的所述触发器的控制端连接所述第二输入端；The control end of the flip-flop of the Nth shift buffer is connected to the second input end;
    第N个所述移位缓冲器的所述触发器的输出端连接第N个所述移位缓冲器的所述缓冲器的输入端；The output end of the flip-flop of the Nth shift buffer is connected to the input end of the buffer of the Nth shift buffer;
    第N个所述移位缓冲器的所述缓冲器的输出端输出与所述显示面板内的对应的第N条栅极线的栅极控制信号，且第N个所述移位缓冲器的所述缓冲器的输出端连接所述第N+1个所述移位缓冲器的所述触发器的输入端；The output end of the buffer of the Nth shift buffer outputs the gate control signal corresponding to the Nth gate line in the display panel, and the Nth shift buffer outputs the gate control signal of the corresponding Nth gate line in the display panel. The output end of the buffer is connected to the input end of the flip-flop of the N+1th shift buffer;
    第N个所述移位缓冲器的所述触发器的输入端连接所述第N-1个所述移位缓冲器的所述触发器的输出端；The input end of the flip-flop of the Nth shift buffer is connected to the output end of the flip-flop of the N-1th shift buffer;
    其中，所述的N为大于等于2的自然数。Wherein, the N is a natural number greater than or equal to 2.
  5. 如权利要求3所述的一种栅极驱动模块，其中，每个所述移位缓冲器还包括稳压电路；所述稳压电路连接在当前的所述移位缓冲器的输出端与地线之间。The gate driving module of claim 3, wherein each of the shift buffers further comprises a voltage regulator circuit; the voltage regulator circuit is connected between the current output end of the shift buffer and the ground between the lines.
  6. 如权利要求1所述的一种栅极驱动模块，其中，所述电平转换电路包括高电平信号接收端和低电平信号接收端，分别接收高电平信号和低电平信号，所述电平转换电路根据高电平信号和低电平信号，将所述逻辑控制信号进行电平转换生成第二控制信号。The gate driving module according to claim 1, wherein the level conversion circuit comprises a high-level signal receiving end and a low-level signal receiving end, respectively receiving the high-level signal and the low-level signal, so the The level conversion circuit performs level conversion on the logic control signal according to the high-level signal and the low-level signal to generate a second control signal.
  7. 如权利要求1所述的一种栅极驱动模块，其中，所述逻辑控制电路为第一触发器，所述第一触发器为上升沿触发器，所述第一触发器的控制端连接所述第二输入端，所述第一触发器的输入端连接所述第一输入端，所述第一触发器的输出端连接所述电平转换电路的输入端，所述第一触发器的输出端输出所述逻辑控制信号至所述电平转换电路。The gate driving module of claim 1, wherein the logic control circuit is a first flip-flop, the first flip-flop is a rising edge flip-flop, and a control end of the first flip-flop is connected to the The second input terminal, the input terminal of the first flip-flop is connected to the first input terminal, the output terminal of the first flip-flop is connected to the input terminal of the level conversion circuit, and the output terminal of the first flip-flop is connected to the input terminal of the level conversion circuit. The output terminal outputs the logic control signal to the level conversion circuit.
  8. 如权利要求1所述的一种栅极驱动模块，其中，所述第一控制信号为帧起始信号。The gate driving module of claim 1, wherein the first control signal is a frame start signal.
  9. 如权利要求4所述的一种栅极驱动模块，其中，每个所述移位缓冲器还包括稳压电路；所述稳压电路一端连接在当前的所述移位缓冲器的输出端与所述触发器的输入端之间，另一端接地。The gate driving module according to claim 4, wherein each of the shift buffers further comprises a voltage regulator circuit; one end of the voltage regulator circuit is connected between the output end of the current shift buffer and the voltage regulator circuit. Between the input ends of the flip-flop, the other end is grounded.
  10. 如权利要求5所述的一种栅极驱动模块，其中，每个所述稳压单元包括一个稳压电容。The gate driving module of claim 5, wherein each of the voltage stabilization units includes a voltage stabilization capacitor.
  11. 如权利要求7所述的一种栅极驱动模块，其中，所述时钟信号的上升沿与对应的所述栅极控制的信号上升沿为同一时刻。The gate driving module according to claim 7, wherein the rising edge of the clock signal and the corresponding rising edge of the gate control signal are at the same time.
  12. 如权利要求11所述的一种栅极驱动模块，其中，当前行扫描线对应的所述栅极控制的信号下降沿与下一行扫描线对应的时钟信号的上升沿为同一时刻。11. The gate driving module of claim 11, wherein the falling edge of the gate-controlled signal corresponding to the scan line of the current row and the rising edge of the clock signal corresponding to the scan line of the next row are at the same time.
  13. 一种栅极控制信号的生成方法，包括步骤：A method for generating a gate control signal, comprising the steps of:
    接收第一控制信号和时钟信号，生成逻辑控制信号；receiving a first control signal and a clock signal to generate a logic control signal;
    将所述逻辑控制信号进行电平转换生成第二控制信号；performing level conversion on the logic control signal to generate a second control signal;
    根据第二控制信号和时钟信号，生成第1条栅极线的栅极控制信号，并输出至显示面板内的对应的第1条栅极线；以及generating a gate control signal of the first gate line according to the second control signal and the clock signal, and outputting it to the corresponding first gate line in the display panel; and
    根据第1条栅极线的栅极控制信号逐级移位，分别生成第N条栅极线的栅极控制信号，并输出至所述显示面板内的对应的第N条栅极线；According to the gate control signal of the first gate line, the gate control signal is shifted step by step, and the gate control signal of the Nth gate line is respectively generated and output to the corresponding Nth gate line in the display panel;
    其中，所述第二控制信号的低电平和高电平为预设的驱动所述显示面板的低电平和高电平。Wherein, the low level and high level of the second control signal are preset low level and high level for driving the display panel.
  14. 如权利要求13所述的一种栅极控制信号的生成方法，其中，所述显示面板与一栅极驱动模块连接，所述栅极驱动模块包括：The method for generating a gate control signal according to claim 13, wherein the display panel is connected to a gate driving module, and the gate driving module comprises:
    第一输入端，接收第一控制信号；a first input end, receiving a first control signal;
    第二输入端，接收时钟信号；The second input terminal receives the clock signal;
    逻辑控制电路，所述逻辑控制电路的输入端与所述第一输入端以及第二输入端耦接，所述逻辑控制电路接收所述第一输入端输入的所述第一控制信号和所述第二输入端输入的所述时钟信号生成逻辑控制信号；a logic control circuit, the input end of the logic control circuit is coupled to the first input end and the second input end, the logic control circuit receives the first control signal input from the first input end and the The clock signal input by the second input terminal generates a logic control signal;
    电平转换电路，所述电平转换电路的输入端与所述逻辑控制电路的输出端耦接，将所述逻辑控制信号进行电平转换生成第二控制信号；a level conversion circuit, the input end of the level conversion circuit is coupled with the output end of the logic control circuit, and the logic control signal is level-converted to generate a second control signal;
    移位输出缓冲电路，与所述第二输入端以及所述电平转换电路的输出端耦接，所述移位缓冲电路同时接收所述电平转换电路输出的第一控制信号和所述第二输入端输出的时钟信号；以及a shift output buffer circuit, coupled to the second input terminal and the output terminal of the level shift circuit, the shift buffer circuit simultaneously receives the first control signal output by the level shift circuit and the first control signal output by the level shift circuit the clock signal output from the two input terminals; and
    栅极线，与所述移位输出缓冲电路耦接；a gate line, coupled to the shift output buffer circuit;
    其中，所述移位输出缓冲电路包括多个级联的移位缓冲器，每个所述移位输出缓冲单元根据所述第二控制信号以及对应的所述时钟信号生成一栅极控制信号并输出至所述栅极线。Wherein, the shift output buffer circuit includes a plurality of cascaded shift buffers, each of the shift output buffer units generates a gate control signal according to the second control signal and the corresponding clock signal, and generates a gate control signal. output to the gate line.
  15. 如权利要求14所述的一种栅极控制信号的生成方法，其中，所述移位输出缓冲电路的第1个所述移位缓冲器直接将第二控制信号作为栅极控制信号输出与所述显示面板内的对应的第1条栅极线，第1个所述移位缓冲器的输出端直接连接第2个所述移位缓冲器的输入端；The method for generating a gate control signal according to claim 14, wherein the first shift buffer of the shift output buffer circuit directly outputs the second control signal as the gate control signal, which is the same as the gate control signal. the corresponding first gate line in the display panel, the output end of the first shift buffer is directly connected to the input end of the second shift buffer;
    所述移位输出缓冲电路的第N个所述移位缓冲器包括触发器，第N个所述移位缓冲器的所述触发器的控制端连接所述第二输入端；The Nth shift buffer of the shift output buffer circuit includes a flip-flop, and the control terminal of the flip-flop of the Nth shift buffer is connected to the second input terminal;
    第N个所述移位缓冲器的所述触发器的输入段连接所述第N-1个所述移位缓冲器的所述触发器的输出端；The input section of the flip-flop of the Nth shift buffer is connected to the output end of the flip-flop of the N-1th shift buffer;
    第N个所述移位缓冲器的所述触发器的输出端输出与所述显示面板内的对应的第N条栅极线的栅极控制信号，且第N个所述移位缓冲器的所述触发器的输出端连接所述第N+1个所述移位缓冲器的所述触发器的输入端；The output end of the flip-flop of the Nth shift buffer outputs the gate control signal corresponding to the Nth gate line in the display panel, and the Nth shift buffer outputs the gate control signal. The output terminal of the flip-flop is connected to the input terminal of the flip-flop of the N+1th shift buffer;
    其中，所述的N为大于等于2的自然数；Wherein, the N is a natural number greater than or equal to 2;
    每个所述移位缓冲器还包括稳压电路；所述稳压电路连接在当前的所述移位缓冲器的输出端与地线之间。Each of the shift buffers further includes a voltage-stabilizing circuit; the voltage-stabilizing circuit is connected between the output terminal of the current shift buffer and the ground line.
  16. 如权利要求14所述的一种栅极控制信号的生成方法，其中，所述移位输出缓冲电路的第1个所述移位缓冲器包括缓冲器，所述缓冲器的输入端直接连接所述电平转换电路的输出端，所述缓冲器的输出端输出与所述显示面板内的对应的第1条栅极线的栅极控制信号，且第1个所述移位缓冲器的输出端直接连接第2个所述移位缓冲器的输入端；The method for generating a gate control signal according to claim 14, wherein the first shift buffer of the shift output buffer circuit comprises a buffer, and the input end of the buffer is directly connected to the The output end of the level conversion circuit, the output end of the buffer outputs the gate control signal corresponding to the first gate line in the display panel, and the first output of the shift buffer The terminal is directly connected to the input terminal of the second shift buffer;
    所述移位输出缓冲电路的第N个所述移位缓冲器包括触发器以及缓冲器；The Nth shift buffer of the shift output buffer circuit includes a flip-flop and a buffer;
    第N个所述移位缓冲器的所述触发器的控制端连接所述第二输入端；The control end of the flip-flop of the Nth shift buffer is connected to the second input end;
    第N个所述移位缓冲器的所述触发器的输出端连接第N个所述移位缓冲器的所述缓冲器的输入端；The output end of the flip-flop of the Nth shift buffer is connected to the input end of the buffer of the Nth shift buffer;
    第N个所述移位缓冲器的所述缓冲器的输出端输出与所述显示面板内的对应的第N条栅极线的栅极控制信号，且第N个所述移位缓冲器的所述缓冲器的输出端连接所述第N+1个所述移位缓冲器的所述触发器的输入端；The output end of the buffer of the Nth shift buffer outputs the gate control signal corresponding to the Nth gate line in the display panel, and the Nth shift buffer outputs the gate control signal of the corresponding Nth gate line in the display panel. The output end of the buffer is connected to the input end of the flip-flop of the N+1th shift buffer;
    第N个所述移位缓冲器的所述触发器的输入端连接所述第N-1个所述移位缓冲器的所述触发器的输出端；The input end of the flip-flop of the Nth shift buffer is connected to the output end of the flip-flop of the N-1th shift buffer;
    其中，所述的N为大于等于2的自然数；Wherein, the N is a natural number greater than or equal to 2;
    每个所述移位缓冲器还包括稳压电路；所述稳压电路一端连接在当前的所述移位缓冲器的输出端与所述触发器的输入端之间，另一端接地。Each of the shift buffers further includes a voltage-stabilizing circuit; one end of the voltage-stabilizing circuit is connected between the current output end of the shift buffer and the input end of the flip-flop, and the other end is grounded.
  17. 一种显示装置，包括显示面板，以及与所述显示面板驱动连接的栅极驱动模块，所述栅极驱动模块生成栅极控制信号，并输出至所述显示面板的对应的栅极线；所述栅极驱动模块包括：A display device, comprising a display panel, and a gate driving module drivingly connected to the display panel, the gate driving module generates a gate control signal and outputs it to a corresponding gate line of the display panel; the The gate drive module includes:
    第一输入端，接收第一控制信号；a first input end, receiving a first control signal;
    第二输入端，接收时钟信号；The second input terminal receives the clock signal;
    逻辑控制电路，所述逻辑控制电路的输入端与所述第一输入端以及第二输入端耦接，所 述逻辑控制电路接收所述第一输入端输入的所述第一控制信号和所述第二输入端输入的所述时钟信号生成逻辑控制信号；a logic control circuit, the input end of the logic control circuit is coupled to the first input end and the second input end, the logic control circuit receives the first control signal input from the first input end and the The clock signal input by the second input terminal generates a logic control signal;
    电平转换电路，所述电平转换电路的输入端与所述逻辑控制电路的输出端耦接，将所述逻辑控制信号进行电平转换生成第二控制信号；a level conversion circuit, the input end of the level conversion circuit is coupled with the output end of the logic control circuit, and the logic control signal is level-converted to generate a second control signal;
    移位输出缓冲电路，与所述第二输入端以及所述电平转换电路的输出端耦接，所述移位缓冲电路同时接收所述电平转换电路输出的第一控制信号和所述第二输入端输出的时钟信号；以及a shift output buffer circuit, coupled to the second input terminal and the output terminal of the level shift circuit, the shift buffer circuit simultaneously receives the first control signal output by the level shift circuit and the first control signal output by the level shift circuit a clock signal output from the two input terminals; and
    栅极线，与所述移位输出缓冲电路耦接；a gate line, coupled to the shift output buffer circuit;
    其中，所述移位输出缓冲电路包括多个级联的移位缓冲器，每个所述移位输出缓冲单元根据所述第二控制信号以及对应的所述时钟信号生成一栅极控制信号并输出至所述栅极线。Wherein, the shift output buffer circuit includes a plurality of cascaded shift buffers, each of the shift output buffer units generates a gate control signal according to the second control signal and the corresponding clock signal, and generates a gate control signal. output to the gate line.
  18. 如权利要求17所述的一种显示装置，其中，所述移位输出缓冲电路的第1个所述移位缓冲器直接将第二控制信号作为栅极控制信号输出至所述显示面板内的对应的第1条栅极线；18. The display device of claim 17, wherein the first shift buffer of the shift output buffer circuit directly outputs the second control signal as a gate control signal to a second control signal in the display panel. The corresponding first gate line;
    所述移位输出缓冲电路的第N个所述移位缓冲器的控制端连接所述第二输入端；第N个所述移位缓冲器的输入端连接第N-1个所述移位缓冲器的输出端，第N个所述移位缓冲器的输出端输出与所述显示面板内的对应的第N条栅极线的栅极控制信号，且第N个所述移位缓冲器的输出端连接第N+1个所述移位缓冲器的输入端；The control terminal of the Nth shift buffer of the shift output buffer circuit is connected to the second input terminal; the input terminal of the Nth shift buffer is connected to the N-1th shift buffer The output end of the buffer, the output end of the Nth shift buffer outputs a gate control signal corresponding to the Nth gate line in the display panel, and the Nth shift buffer The output terminal of is connected to the input terminal of the N+1th shift buffer;
    其中，所述的N为大于等于2的自然数；Wherein, the N is a natural number greater than or equal to 2;
    所述电平转换电路包括高电平信号接收端和低电平信号接收端，分别接收高电平信号和低电平信号，所述电平转换电路根据高电平信号和低电平信号，将所述逻辑控制信号进行电平转换生成第二控制信号。The level conversion circuit includes a high-level signal receiving terminal and a low-level signal receiving terminal, which respectively receive the high-level signal and the low-level signal, and the level conversion circuit according to the high-level signal and the low-level signal, The logic control signal is level-converted to generate a second control signal.
  19. 如权利要求17所述的一种显示装置，其中，所述移位输出缓冲电路的第1个所述移位缓冲器包括缓冲器，所述缓冲器的输入端直接连接所述电平转换电路的输出端，所述缓冲器的输出端输出与所述显示面板内的对应的第1条栅极线的栅极控制信号，且第1个所述移位缓冲器的输出端直接连接第2个所述移位缓冲器的输入端；The display device of claim 17, wherein the first shift buffer of the shift output buffer circuit comprises a buffer, and the input end of the buffer is directly connected to the level conversion circuit , the output end of the buffer outputs the gate control signal corresponding to the first gate line in the display panel, and the output end of the first shift buffer is directly connected to the second an input of the shift buffer;
    所述移位输出缓冲电路的第N个所述移位缓冲器包括触发器以及缓冲器；The Nth shift buffer of the shift output buffer circuit includes a flip-flop and a buffer;
    第N个所述移位缓冲器的所述触发器的控制端连接所述第二输入端；The control end of the flip-flop of the Nth shift buffer is connected to the second input end;
    第N个所述移位缓冲器的所述触发器的输出端连接第N个所述移位缓冲器的所述缓冲器的输入端；The output end of the flip-flop of the Nth shift buffer is connected to the input end of the buffer of the Nth shift buffer;
    第N个所述移位缓冲器的所述缓冲器的输出端输出与所述显示面板内的对应的第N条栅极线的栅极控制信号，且第N个所述移位缓冲器的所述缓冲器的输出端连接所述第N+1个所述移位缓冲器的所述触发器的输入端；The output end of the buffer of the Nth shift buffer outputs the gate control signal corresponding to the Nth gate line in the display panel, and the Nth shift buffer outputs the gate control signal of the corresponding Nth gate line in the display panel. The output end of the buffer is connected to the input end of the flip-flop of the N+1th shift buffer;
    第N个所述移位缓冲器的所述触发器的输入端连接所述第N-1个所述移位缓冲器的所述触发器的输出端；The input end of the flip-flop of the Nth shift buffer is connected to the output end of the flip-flop of the N-1th shift buffer;
    其中，所述的N为大于等于2的自然数；Wherein, the N is a natural number greater than or equal to 2;
    所述逻辑控制电路为第一触发器，所述第一触发器为上升沿触发器，所述第一触发器的控制端连接所述第二输入端，所述第一触发器的输入端连接所述第一输入端，所述第一触发器的输出端连接所述电平转换电路的输入端，所述第一触发器的输出端输出所述逻辑控制信号至所述电平转换电路。The logic control circuit is a first flip-flop, the first flip-flop is a rising edge flip-flop, the control terminal of the first flip-flop is connected to the second input terminal, and the input terminal of the first flip-flop is connected to the second input terminal. The first input terminal and the output terminal of the first flip-flop are connected to the input terminal of the level conversion circuit, and the output terminal of the first flip-flop outputs the logic control signal to the level conversion circuit.
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