WO2022193570A1 - 扰码装置及扰码方法 - Google Patents
扰码装置及扰码方法 Download PDFInfo
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- WO2022193570A1 WO2022193570A1 PCT/CN2021/116888 CN2021116888W WO2022193570A1 WO 2022193570 A1 WO2022193570 A1 WO 2022193570A1 CN 2021116888 W CN2021116888 W CN 2021116888W WO 2022193570 A1 WO2022193570 A1 WO 2022193570A1
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- signal
- scrambling
- control signal
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000005070 sampling Methods 0.000 claims description 21
- 230000000694 effects Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/4408—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving video stream encryption, e.g. re-encrypting a decrypted video stream for redistribution in a home network
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
Definitions
- the present application relates to the technical field of display panel data signal control, and in particular, to a scrambling device and a scrambling method.
- the sender In order to obtain a display device with better display quality, it is necessary to better process the data signal.
- the sender In the transmission of digital signals, the sender usually needs to add a scrambler to optimize the data signal through the scrambler.
- the function of the scrambling code is to change the statistical characteristics of the digital signal and make it an approximate white noise sequence.
- the frequency of the white noise sequence is relatively scattered, which is equivalent to the relatively scattered energy of the signal, so as to achieve the purpose of reducing electromagnetic interference.
- the scrambling code sequence generated by the scrambler has a certain cycle period, and the sequences are connected in sequence to form a long-period sequence, thereby effectively improving the quality of signal data processing.
- Embodiments of the present application provide a scrambling device and a scrambling method, so as to effectively improve the inability to effectively process data of a long scrambling sequence when processing a data signal, and in the process of processing, the data signal is very difficult to process. It is easy to be subject to external electromagnetic interference, which makes the data scrambling effect unsatisfactory, which further leads to problems such as poor display quality of the display device when displaying the picture.
- a scrambling device including:
- the data acquisition module is used to acquire the original data signal of the display screen:
- the judging module is used for judging the original data signal, wherein, when the original data signal is a high-level signal, the first control signal is output, and when the original data signal is a low-level signal signal, output a second control signal, wherein the number of bits of the first control signal is different from the number of bits of the second control signal;
- first scrambling module configured to receive the first control signal and scramble the first control signal to obtain a first scrambled data signal
- the second scrambling module is configured to receive the second control signal and scramble the second control signal to obtain a second scrambled data signal;
- An output module configured to receive and output the first scrambled data signal or the second scrambled data signal.
- the judgment module includes a sampling unit and a control unit, the sampling unit is connected to the control unit, one end of the sampling unit is connected to the output end of the data acquisition module, and the sampling unit The other end is connected with the control unit.
- the control unit when the original data signal is at a high level, the control unit is turned on, and the output signal of the judgment module is transmitted to the first scrambling module;
- the control unit When the original data signal is at a low level, the control unit is closed, and the output signal of the judgment module is transmitted to the second scrambling module.
- control unit is an inversion logic gate.
- the first control signal and the second control signal include a logic digital signal and an enable data signal.
- the original data signal has a number of 8 bits.
- the first control signal and the second control signal are mutually inverse data values.
- a scrambling device including:
- the data acquisition module is used to acquire the original data signal of the display screen:
- the judging module is used for judging the original data signal, wherein, when the original data signal is a high-level signal, the first control signal is output, and when the original data signal is a low-level signal signal, output the second control signal;
- first scrambling module configured to receive the first control signal and scramble the first control signal to obtain a first scrambled data signal
- the second scrambling module is configured to receive the second control signal and scramble the second control signal to obtain a second scrambled data signal;
- An output module configured to receive and output the first scrambled data signal or the second scrambled data signal.
- the judgment module includes a sampling unit and a control unit, the sampling unit is connected to the control unit, one end of the sampling unit is connected to the output end of the data acquisition module, and the sampling unit The other end is connected with the control unit.
- the control unit when the original data signal is at a high level, the control unit is turned on, and the output signal of the judgment module is transmitted to the first scrambling module;
- the control unit When the original data signal is at a low level, the control unit is closed, and the output signal of the judgment module is transmitted to the second scrambling module.
- control unit is an inversion logic gate.
- the first control signal and the second control signal include a logic digital signal and an enable data signal.
- the original data signal has a number of 8 bits.
- the first control signal and the second control signal are mutually inverse data values.
- a scrambling method including the following steps:
- the first scrambled data signal and the second scrambled data signal are received and output.
- the first control signal is scrambled by the first scrambling module
- the second control signal is scrambled by the second scrambling module
- the first control signal includes N data bit streams
- the second control signal includes N data bit streams
- the first control signal is a high-level signal, and the first control signal is processed by the first scrambling module to obtain the ith data Bit stream
- the second control signal is a low-level signal, and the second control signal is processed by the second scrambling module to obtain the i+1 th data Bit stream
- i is an integer greater than or equal to 1;
- the first control signal is a high-level signal
- the first control signal is processed by the first scrambling module , to obtain the i-th data bit stream
- the second control signal is a low-level signal
- the second control signal passes through the second
- the scrambling module processes, and obtains the i+2 and i+3 data bit streams, where i is an integer greater than or equal to 1.
- the number of bits of the first control signal is different from the number of bits of the second control signal.
- the first control signal and the second control signal are mutually inverse data values.
- the original data signal has a number of 8 bits.
- the embodiments of the present application provide a scrambling device and a scrambling method.
- a data acquisition module acquires an original data signal of a display screen, and a judgment module receives the original data signal and judges the data signal, specifically the high and low voltages of the original data signal.
- the first control signal is output when the original data signal is a high-level signal, and the first control signal is transmitted to the first scrambling module.
- the first control signal is transmitted to the first scrambling module.
- Output the second control signal invert the second control signal, and transmit it to the second scrambling module again.
- FIG. 1 is a schematic structural diagram of a scrambling device provided by an embodiment of the present application.
- FIG. 2 is a schematic structural diagram of a judgment module provided by an embodiment of the present application.
- FIG. 3 is a scrambling method provided by an embodiment of the present application.
- first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present application, “plurality” means two or more, unless otherwise expressly and specifically defined.
- the sender in the process of digital signal transmission, the sender usually needs to add a scrambler to change the statistical characteristics of the digital signal through scrambling, and the data signal becomes an approximate white noise sequence signal.
- the embodiments of the present application provide a scrambling device and a scrambling method, which improve the scrambling performance and scrambling rate of a digital signal, and simultaneously solve the problems of unsatisfactory scrambling effect and easy external electromagnetic interference in the process of digital signal propagation, and Effectively improve system performance.
- FIG. 1 is a schematic structural diagram of a scrambling device provided by an embodiment of the present application.
- the scrambling device includes a data acquisition module 100 , a judgment module 101 , a scrambling module 102 and an output module 103 .
- the data acquisition module 100 is connected with the judgment module 101 , the judgment module 101 is connected with the scrambling module 102 , and the output module 103 is connected with the scrambling module 102 .
- the data acquisition module 100 is configured to acquire the original data signal of the display image to be transmitted, and after acquiring the original data signal of the display image, transmit the original data signal to the determination module 101 , when the determination module 101 receives the original data signal After the original data signal is transmitted, the level of the original data signal is judged, and then different enable data signals are output according to the level of the original data signal.
- the scrambling module 102 receives different enable data signals. data signals, and process different enabled data signals, finally obtain different data signals after scrambled processing, and output them.
- multiple scrambling unit modules may be set in the scrambling module 102, and the multiple scrambling unit modules may be In parallel with each other, in this embodiment of the present application, two-level cascaded scrambling unit modules are used as an example for description, and other cascaded scrambling unit modules will not be described in detail.
- the scrambling module 102 includes a first scrambling module 1021 and a second scrambling module 1022 .
- the input terminals of the first scrambling module 1021 and the second scrambling module 1022 are both connected to the judgment module 101
- the output terminals of the first scrambling module 1021 and the second scrambling module 1022 are both connected to the output module 103 .
- the data acquisition module 100 After the data acquisition module 100 acquires the original data signal of the display screen, it transmits the original data signal to the judgment module 101, and the judgment module 101 judges the original data signal.
- the acquired raw data signals may include data signals such as pixel data of the display screen.
- the data acquisition module 100 may convert the pixel data signals into corresponding digital signals and transmit them.
- the judgment module 101 receives the original data signal output from the data acquisition module 100 and judges the data signal. Specifically, when the original data signal is at a high level, the first control signal is output, and when the original data signal is at a low level data signal, the judgment module 101 outputs a second control signal.
- FIG. 2 is a schematic structural diagram of a judgment module provided by an embodiment of the present application.
- the judgment module 101 provided in this embodiment of the present application further includes a sampling unit 1011 and a control unit 1012 .
- One end of the sampling unit 1011 is connected to the input end of the judgment module 101
- the other end of the sampling unit 1011 is connected to one end of the control unit 1012
- the other end of the control unit 1012 is connected to the output end of the judgment module 101 .
- the sampling unit 1011 judges the original data signal.
- the original data signal is a high-level data signal, it outputs the first control signal; when the original data signal is a low-level data signal, it outputs the first control signal. the second control signal.
- control unit 1012 receives different control signals transmitted by the sampling unit 1011. Specifically, when the signal received by the control unit 1012 is the first control signal, the control unit 1012 controls the first control signal and makes the first control signal The control signal is only transmitted to the first scrambling module 1021 , and when the signal received by the control unit 1012 is the second control signal, the second control signal is only transmitted to the second scrambling module 1022 .
- different original data signals can be respectively transmitted to different scrambling modules to perform scramble processing and obtain better data signals.
- control unit 1012 when the control unit 1012 processes different control signals, when the control signal is the first control signal, the control unit 1012 is turned on, so that the first control signal is transmitted to the first control signal.
- the scrambling module when the control signal is the second control signal, the control unit 1012 is closed, so that the second control signal is transmitted to the second scrambling module.
- control unit 1012 may be an inversion logic gate. Specifically, when the original data signal received by the judgment module 101 is a low-level signal, the inversion logic gate first performs inversion processing on the original data signal , and obtain a second control signal, and then transmit the second control signal to the second scrambling module 1022 . Therefore, in this embodiment of the present application, the first control signal and the second control signal are mutually inverse data.
- the first control signal and the second control signal in the embodiment of the present application may include a logic digital signal and an enable data signal, the scrambling mode of the data is selected by the enable data signal, and the opening or closing of the control unit 1012 is controlled, In this way, it is ensured that different original data signals can be transmitted to the first scrambling module 1021 and the second scrambling module 1022 respectively, so as to meet the requirements of reducing signal energy and reducing electromagnetic interference to the greatest extent, the scrambling rate is increased, and the The storage space of the device is reduced, and the scrambling quality is guaranteed.
- the logic digital signal in the first control signal and the second control signal in the embodiment of the present application can select the scrambling code module corresponding to the input original data signal, that is, different pixel data are transmitted to different scrambling codes. In the module, it is finally ensured that the pixel data undergoes the corresponding scramble operation and the scrambled pixel data is obtained. Meanwhile, the high and low level lengths of the enable signal in the first control signal and the second control signal can be adjusted according to the actual scrambling process, wherein the number of bits of the first control signal and the second control signal can be the same.
- one high level corresponds to N pixel data
- one low level corresponds to M pixel data
- M and N can be set arbitrarily, which are not specifically limited in this embodiment. Therefore, the generated scrambling code sequence is closer to the white noise sequence, and the energy of each frequency band is relatively balanced, so as to effectively improve the scrambling code effect.
- the original data signal may include data information of multiple bits.
- the data information when data information of one data bit stream is transmitted, the data information is 8-bit pixel data.
- the i-th data bit stream arrives, when the control signal in the judgment module 101 judges that the pixel data is at a high level, the pixel data is transmitted to the first scrambling module 1021, and finally the i-th scrambled data bit is obtained flow.
- i+1 th data bit stream arrives, when the control signal in the judgment module 101 judges that the pixel data is at a low level, the pixel data is transmitted to the second scrambling module 1022, and finally the i th scrambled code is obtained.
- i is an integer greater than 1.
- the period of the control signal is 4. That is, the length of the high-level signal is 2 bit streams, and the length of the low-level signal is 2 bit streams.
- the pixel data signal is at a high level, and the signal is transmitted to the first scrambling module 1021 to obtain the i-th and i-th scrambled and i+1-th data bit streams.
- i+1 data bit stream data when the i+2 and i+3 data bit streams arrive, when the pixel data signal is at a low level, the signal is transmitted to the second scrambling module 1022 to obtain a scrambling code
- the i+2th and i+3th data bit streams after.
- the scrambling device in the embodiment of the present application effectively ensures the efficiency of data scrambling processing.
- FIG. 3 is a scrambling method provided by an embodiment of the present application, including the following steps:
- the data acquisition module 100 acquires the original data signal of the display screen, and transmits the original data signal to the determination module 101 , and the determination module 101 Judging the data signal: when the original data signal is a high-level signal, the first control signal is output, and when the original data signal is a low-level signal, the second control signal is output.
- S102 Receive the first control signal and the second control signal, and scramble the first control signal and the second control signal; wherein, scramble the first control signal to obtain the first control signal.
- the second control signal is scrambled
- the second control signal is inverted and then scrambled to obtain a second scrambled data signal.
- the first control signal corresponding to the high-level pixel data is scrambled by the first scrambling module 1021 and output, and the second control signal corresponding to the low-level pixel data is inverted and then passed through the second scrambling module 1022. Scrambled and output. Thereby, the pixel data can be better scrambled.
- S103 Receive the first scrambled data signal and the second scrambled data signal, and output them.
- the embodiment of the present application also provides a signal processing system, the signal processing system includes a storage medium and the scrambling device provided in the embodiment of the present application, by transmitting data signals of different levels to different scrambling devices The data signal is scrambled correspondingly in the module, thereby effectively improving the scrambling efficiency and quality of the data signal, and finally improving the display performance of the display panel.
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Abstract
本申请提供一种扰码装置及扰码方法,扰码装置包括数据获取模块、判断模块、第一加扰模块、第二加扰模块以及输出模块,通过判断模块对数据信号进行判断,并将不同的数据信号传输至对应的加扰模块内,以对数据信号进行加扰处理,并最终得到所需要的输出信号,从而有效的提高了扰码装置的扰码速率。
Description
本申请涉及显示面板数据信号控制技术领域,特别是涉及一种扰码装置及扰码方法。
随着显示面板显示技术的不断提高,人们对显示面板显示画面的质量以及效果也提出了更高的要求。
为了获得到显示质量更好的显示装置,需要对数据信号更好的进行处理。在数字信号的传输中,发送端通常要加入扰码器,通过扰码器对数据信号进行优化,扰码的作用主要是改变数字信号的统计特性使其变成近似白噪声序列。而白噪声序列的频率较为分散,相当于信号的能量较为分散,从而达到减少电磁干扰的目的。此外,扰码器生成的扰码序列具有一定循环周期,序列依次连接起来,可以形成长周期的序列,进而有效的提高了信号数据处理的质量。但是,现有技术在对数据信号进行处理时,往往存在着数据信号处理效率低,不能有效的对较长扰码序列的数据进行处理,并且在处理过程中,容易受到外界电磁干扰,数据扰码不理想等问题,进而导致画面显示的显示质量差。
综上所述,现有数字信号扰码技术中,在对数字信号进行扰码处理时,不能有效的对较长扰码序列的数据进行处理,并且在处理过程中,数据信号很容易受到外界电磁干扰,使得数据扰码效果不理想,进而导致显示装置在画面显示时的显示质量差等问题。
本申请实施例提供一种扰码装置及扰码方法,以有效的改善在对数据信号进行处理时,不能有效的对较长扰码序列的数据进行处理,并且在处理过程中,数据信号很容易受到外界电磁干扰,使得数据扰码效果不理想,进而导致显示装置在画面显示时的显示质量差等问题。
为解决上述技术问题,本申请实施例提供的技术方法如下:
本申请实施例的第一方面,提供了一种扰码装置,包括:
数据获取模块,用于获取显示画面的原始数据信号:
判断模块,所述判断模块用于对所述原始数据信号进行判断,其中,当所述原始数据信号为高电平信号时,则输出第一控制信号,当所述原始数据信号为低电平信号时,则输出第二控制信号,其中,所述第一控制信号的比特位数与所述第二控制信号的比特位数不同;
第一加扰模块,所述第一加扰模块用于接收所述第一控制信号并对所述第一控制信号扰码处理,得到第一扰码数据信号;
第二加扰模块,所述第二加扰模块用于接收所述第二控制信号并对所述第二控制信号扰码处理,得到第二扰码数据信号;以及,
输出模块,所述输出模块用于接收所述第一扰码数据信号或所述第二扰码数据信号并输出。
根据本申请一实施例,所述判断模块包括采样单元和控制单元,所述采样单元与所述控制单元连接,所述采样单元的一端与所述数据获取模块的输出端连接,所述采样单元的另一端与所述控制单元连接。
根据本申请一实施例,当所述原始数据信号为高电平时,所述控制单元打开,所述判断模块的输出信号传输至所述第一加扰模块;
当所述原始数据信号为低电平时,所述控制单元闭合,所述判断模块的输出信号传输至所述第二加扰模块。
根据本申请一实施例,所述控制单元为取反逻辑门。
根据本申请一实施例,所述第一控制信号和所述第二控制信号包括逻辑数字信号和使能数据信号。
根据本申请一实施例,所述原始数据信号具有8个比特数目。
根据本申请一实施例,所述第一控制信号与所述第二控制信号互为取反数据值。
本申请实施例的第二方面,提供了一种扰码装置,包括:
数据获取模块,用于获取显示画面的原始数据信号:
判断模块,所述判断模块用于对所述原始数据信号进行判断,其中,当所述原始数据信号为高电平信号时,则输出第一控制信号,当所述原始数据信号为低电平信号时,则输出第二控制信号;
第一加扰模块,所述第一加扰模块用于接收所述第一控制信号并对所述第一控制信号扰码处理,得到第一扰码数据信号;
第二加扰模块,所述第二加扰模块用于接收所述第二控制信号并对所述第二控制信号扰码处理,得到第二扰码数据信号;以及,
输出模块,所述输出模块用于接收所述第一扰码数据信号或所述第二扰码数据信号并输出。
根据本申请一实施例,所述判断模块包括采样单元和控制单元,所述采样单元与所述控制单元连接,所述采样单元的一端与所述数据获取模块的输出端连接,所述采样单元的另一端与所述控制单元连接。
根据本申请一实施例,当所述原始数据信号为高电平时,所述控制单元打开,所述判断模块的输出信号传输至所述第一加扰模块;
当所述原始数据信号为低电平时,所述控制单元闭合,所述判断模块的输出信号传输至所述第二加扰模块。
根据本申请一实施例,所述控制单元为取反逻辑门。
根据本申请一实施例,所述第一控制信号和所述第二控制信号包括逻辑数字信号和使能数据信号。
根据本申请一实施例,所述原始数据信号具有8个比特数目。
根据本申请一实施例,所述第一控制信号与所述第二控制信号互为取反数据值。
根据本申请实施例的第二方面,还提供一种扰码方法,包括如下步骤:
获取显示画面的原始数据信号;
对所述原始数据信号进行判断,当所述原始数据信号为高电平信号时,则输出第一控制信号,当所述原始数据信号为低电平信号时,则输出第二控制信号;
接收所述第一控制信号和所述第二控制信号,对所述第一控制信号和所述第二控制信号加扰处理;其中,对所述第一控制信号加扰处理并得到第一扰码数据信号,对所述第二控制信号加扰处理时,对所述第二控制信号取反后在进行加扰处理并得到第二扰码数据信号;
接收所述第一扰码数据信号和所述第二扰码数据信号,并输出。
根据本申请一实施例,通过第一加扰模块对所述第一控制信号进行加扰处理,通过第二加扰模块对所述第二控制信号进行加扰处理。
根据本申请一实施例,所述第一控制信号包括N个数据比特流,所述第二控制信号包括N个数据比特流;
当N=1时,当第i个数据比特流到来时,所述第一控制信号为高电平信号,所述第一控制信号经过所述第一加扰模块处理后,得到第i个数据比特流,当第i+1个数据比特流到来时,所述第二控制信号为低电平信号,所述第二控制信号经过所述第二加扰模块处理,得到第i+1个数据比特流,i为大于等于1的整数;
当N=2时,当第i个和第i+1个数据比特流到来时,所述第一控制信号为高电平信号,所述第一控制信号经过所述第一加扰模块处理后,得到第i个数据比特流,当第i+2个和第i+3个数据比特流到来时,所述第二控制信号为低电平信号,所述第二控制信号经过所述第二加扰模块处理,得到第i+2个和第i+3个数据比特流,i为大于等于1的整数。
根据本申请一实施例,所述第一控制信号的比特位数与所述第二控制信号的比特位数不同。
根据本申请一实施例,所述第一控制信号与所述第二控制信号互为取反数据值。
根据本申请一实施例,所述原始数据信号具有8个比特数目。
本申请实施例提供一种扰码装置及扰码方法,数据获取模块获取显示画面的原始数据信号,判断模块接收原始数据信号并对该数据信号进行判断,具体的对该原始数据信号的高低电平进行判断,当原始数据信号为高电平信号时,继而输出第一控制信号,并将该第一控制信号传输至第一加扰模块内,当原始数据信号为低电平信号时,继而输出第二控制信号,并将该第二控制信号取反处理,并再次传输至第二加扰模块内,通过上述处理及控制方法,从而有效地对不同的数字信号进行扰码处理,并减小了在处理的过程中外界电磁干扰的影响,使得数据的扰码效果更好,并最终有效地提高了信号的传输质量以及画面显示质量。
下面结合附图,通过对本申请的具体实施方式详细描述,将使本申请的技术方案及其它有益效果更显而易见。
图1为本申请实施例提供的一种扰码装置的结构示意图;
图2为本申请实施例提供的判断模块的结构示意图;
图3为本申请实施例提供的一种扰码方法。
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述。显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。
在本申请的描述中,需要理解的是,术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本申请和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本申请的限制。此外,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中,“多个”的含义是两个或两个以上,除非另有明确具体的限定。
随着数字信号处理技术的不断提高,在数字信号的传输过程中,发送端通常要加入扰码器,通过扰码以改变数字信号的统计特性,并数据信号变成近似白噪声序列信号。本申请实施例提供一种扰码装置及扰码方法,提高数字信号的扰码性能以及扰码速率,同时解决在数字信号传播过程中,扰码效果不理想以及容易外界电磁干扰的问题,并有效的提高***的性能。
如图1所示,图1为本申请实施例提供的一种扰码装置的结构示意图。扰码装置包括数据获取模块100、判断模块101、加扰模块102以及输出模块103。
具体的,数据获取模块100与判断模块101相连接,判断模块101与加扰模块102相连,同时输出模块103与加扰模块102相连接。本揭示实施例中,数据获取模块100用于获取待传输的显示画面的原始数据信号,获取到显示画面的原始数据信号后,并将该原始数据信号传输至判断模块101,当判断模块101接收到传输的原始数据信号后,对该原始数据信号的电平高低进行判断,进而再根据原始数据信号的高低电平输出不同的使能数据信号,此时,加扰模块102接收不同的使能数据信号,并对不同的使能数据信号进行处理,最终得到扰码处理后不同的数据信号,并进行输出。
本申请实施例中,为了有效的提高数据信号的扰码质量及扰码效果,在设置扰码模块102时,扰码模块102内可设置多个扰码单元模块,多个扰码单元模块可相互并联,本申请实施例中,以二级级联的扰码单元模块为例进行说明,其他级联的扰码单元模块不再详细赘述。
优选的,本申请实施例中加扰模块102包括第一加扰模块1021和第二加扰模块1022。第一加扰模块1021和第二加扰模块1022的输入端均与判断模块101相连,第一加扰模块1021和第二加扰模块1022的输出端均与输出模块103相连接。
当数据获取模块100获取到显示画面的原始数据信号后,并将该原始数据信号传输至判断模块101,判断模块101对该原始数据信号进行判断。具体的,获取的原始数据信号可包括显示画面的像素数据等数据信号,数据获取模块100获取到像素数据后可将该像素数据信号转换为对应的数字信号并进行传输。
判断模块101接收从数据获取模块100中输出的原始数据信号并对该数据信号进行判断。具体的,当该原始数据信号为高电平时,则输出第一控制信号,而当该原始数据信号低电平数据信号时,则通过该判断模块101输出第二控制信号。
优选的,如图2所示,图2为本申请实施例提供的判断模块的结构示意图。本申请实施例中提供的判断模块101还包括采样单元1011和控制单元1012。采样单元1011的一端与判断模块101的输入端连接,采样单元1011的另一端与控制单元1012的一端相连接,控制单元1012的另一端与判断模块101的输出端相连接。
在对数据信号进行判断时,采样单元1011对原始数据信号进行判断,当原始数据信号为高电平数据信号时,输出第一控制信号;当原始数据信号为低电平数据信号时,则输出第二控制信号。
进一步的,控制单元1012接收由采样单元1011传输的不同的控制信号,具体的,当控制单元1012接收的信号为第一控制信号时,控制单元1012控制该第一控制信号,并使该第一控制信号仅传输至第一加扰模块1021内,而当控制单元1012接收的信号为第二控制信号时,则将该第二控制信号仅传输至第二加扰模块1022内。进而使得不同的原始数据信号可分别传输至不同的加扰模块中,以对其进行加扰处理,并获得到更好的数据信号。
优选的,本申请实施例中的,控制单元1012在对不同的控制信号进行处理时,当该控制信号为第一控制信号时,该控制单元1012打开,进而使得第一控制信号传输至第一加扰模块,当该控制信号为第二控制信号时,该控制单元1012闭合,从而使得第二控制信号传输至第二加扰模块。
本申请实施例中,控制单元1012可为取反逻辑门,具体的,当判断模块101接收的原始数据信号为低电平信号时,该取反逻辑门首先对该原始数据信号进行取反处理,并得到第二控制信号,进而再将该第二控制信号传输至第二加扰模块1022内。因此,本申请实施例中,第一控制信号与第二控制信号互为取反数据。本申请实施例中的第一控制信号和第二控制信号可包括逻辑数字信号和使能数据信号,通过使能数据信号来选择该数据的扰码方式,并控制控制单元1012的打开或者闭合,进而保证不同的原始数据信号可分别传输至第一加扰模块1021和第二加扰模块1022内,进而在最大程度满足降低信号能量、减少电磁干扰的前提下,提高了扰码速率,并降低了装置的存储空间,保证了加扰的质量。
具体的,本申请实施例中的第一控制信号和第二控制信号中的逻辑数字信号可对输入的原始数据信号对应的扰码模块进行选择,即使得不同的像素数据传输至不同的扰码模块内,最终保证该像素数据经过相应的扰码操作并得到扰码后的像素数据。同时,第一控制信号和第二控制信号中的使能信号的高低电平长度是可以根据实际加扰过程进行调整的,其中,第一控制信号和第二控制信号的位数可相同。优选的,在进行调整时,一个高电平对应N个像素数据,一个低电平对应M个像素数据,其中M与N可以任意设定,本实施例中不具体进行限定。从而使得生成的扰码序列更加的接近于白噪声序列,并且使得各个频段的能量相对均衡,以有效的提高扰码效果。
原始数据信号可包括多个比特位的数据信息,本申请实施例中,在传输1个数据比特流的数据信息时,该数据信息为8bit的像素数据。当像素数据的比特流N=1时,此时,控制信号的周期为2,即高电平信号的长度为1个比特流,低电平信号的长度也为1个比特流。第i个数据比特流到来时,当判断模块101内的控制信号判断该像素数据为高电平时,像素数据被传输至第一加扰模块1021内,最终得到扰码后的第i个数据比特流。当第i+1个数据比特流到来时,当判断模块101内的控制信号判断该像素数据为低电平时,像素数据被传输至第二加扰模块1022内,最终得到扰码后的第i+1个数据比特流,i为大于1的整数。
当像素数据的比特流N=2时,此时,控制信号的周期为4。即高电平信号的长度为2个比特流,低电平信号的长度为2个比特流,在进行扰码处理时,两个高电平的像素数据传输至第一加扰模块1021内,两个低电平的像素数据传输至第二加扰模块1022内。
依次类推,即当第i个和第i+1个数据比特流到来时,像素数据信号为高电平,信号被传输至第一加扰模块1021内,得到扰码后的第i个和第i+1个数据比特流数据;当第i+2个和第i+3个数据比特流到来时,像素数据信号为低电平时,信号被传输至第二加扰模块1022内,得到扰码后的第i+2个和第i+3个数据比特流。
进而通过上述判断模块101以及加扰模块102,使得不同的像素数据被传输至不同的加扰模块内,并将加扰的数据输出。通过本申请实施例中提供的加扰方法有效的降低了扰码序列的长度,因此,本申请实施例中的加扰装置有效的保证了数据加扰处理的效率。
进一步的,本如图3所示,图3为本申请实施例提供的一种扰码方法,包括如下步骤:
S100:获取显示画面的原始数据信号。
S101:对所述原始数据信号进行判断,当所述原始数据信号为高电平信号时,则输出第一控制信号,当所述原始数据信号为低电平信号时,则输出第二控制信号。
同时结合图1中的加扰装置的结构示意图,本申请实施例中,通过数据获取模块100对显示画面的原始数据信号进行获取,并将该原始数据信号传输至判断模块101内,判断模块101对该数据信号进行判断:当所述原始数据信号为高电平信号时,则输出第一控制信号,当所述原始数据信号为低电平信号时,则输出第二控制信号。
S102:接收所述第一控制信号和所述第二控制信号,对所述第一控制信号和所述第二控制信号加扰处理;其中,对所述第一控制信号加扰处理并得到第一扰码数据信号,对所述第二控制信号加扰处理时,对所述第二控制信号取反后在进行加扰处理并得到第二扰码数据信号。
由于第一控制信号和第二控制信号的电平的高低不同,因此,在加扰过程中,分别对不同的数据信号进行不同的加扰处理。
高电平像素数据对应的第一控制信号经过第一加扰模块1021的加扰处理并输出,低电平像素数据对应的第二控制信号经过取反后,再经过第二加扰模块1022的加扰处理并输出。从而更好的对像素数据进行加扰处理。
S103:接收所述第一扰码数据信号和所述第二扰码数据信号,并输出。
进一步的,本申请实施例中还提供一种信号处理***,信号处理***中包括有存储介质以及本申请实施例中提供的加扰装置,通过将不同电平的数据信号传输至不同的加扰模块内,并对应的将该数据信号进行加扰处理,从而有效的提高数据信号的加扰效率以及质量,最终提高显示面板的显示性能。
以上对本申请实施例所提供的一种加扰装置以及加扰方法进行了详细介绍,本文中应用了具体个例对本申请的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想;本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。
Claims (20)
- 一种扰码装置,包括:数据获取模块,用于获取显示画面的原始数据信号;判断模块,所述判断模块用于对所述原始数据信号进行判断,其中,当所述原始数据信号为高电平信号时,则输出第一控制信号,当所述原始数据信号为低电平信号时,则输出第二控制信号,其中,所述第一控制信号的比特位数与所述第二控制信号的比特位数不同;第一加扰模块,所述第一加扰模块用于接收所述第一控制信号并对所述第一控制信号扰码处理,得到第一扰码数据信号;第二加扰模块,所述第二加扰模块用于接收所述第二控制信号并对所述第二控制信号扰码处理,得到第二扰码数据信号;以及,输出模块,所述输出模块用于接收所述第一扰码数据信号或所述第二扰码数据信号并输出。
- 根据权利要求1所述的扰码装置,其中所述判断模块包括采样单元和控制单元,所述采样单元与所述控制单元连接,所述采样单元的一端与所述数据获取模块的输出端连接,所述采样单元的另一端与所述控制单元连接。
- 根据权利要求2所述的扰码装置,其中当所述原始数据信号为高电平时,所述控制单元打开,所述判断模块的输出信号传输至所述第一加扰模块;当所述原始数据信号为低电平时,所述控制单元闭合,所述判断模块的输出信号传输至所述第二加扰模块。
- 根据权利要求2所述的扰码装置,其中所述控制单元为取反逻辑门。
- 根据权利要求1所述的扰码装置,其中所述第一控制信号和所述第二控制信号包括逻辑数字信号和使能数据信号。
- 根据权利要求3所述的扰码装置,其中所述原始数据信号具有8个比特数目。
- 根据权利要求1所述的扰码装置,其中所述第一控制信号与所述第二控制信号互为取反数据值。
- 一种扰码装置,包括:数据获取模块,用于获取显示画面的原始数据信号;判断模块,所述判断模块用于对所述原始数据信号进行判断,其中,当所述原始数据信号为高电平信号时,则输出第一控制信号,当所述原始数据信号为低电平信号时,则输出第二控制信号,其中,所述第一控制信号的比特位数与所述第二控制信号的比特位数不同;第一加扰模块,所述第一加扰模块用于接收所述第一控制信号并对所述第一控制信号扰码处理,得到第一扰码数据信号;第二加扰模块,所述第二加扰模块用于接收所述第二控制信号并对所述第二控制信号扰码处理,得到第二扰码数据信号;以及,输出模块,所述输出模块用于接收所述第一扰码数据信号或所述第二扰码数据信号并输出。
- 根据权利要求8所述的扰码装置,其中所述判断模块包括采样单元和控制单元,所述采样单元与所述控制单元连接,所述采样单元的一端与所述数据获取模块的输出端连接,所述采样单元的另一端与所述控制单元连接。
- 根据权利要求9所述的扰码装置,其中当所述原始数据信号为高电平时,所述控制单元打开,所述判断模块的输出信号传输至所述第一加扰模块;当所述原始数据信号为低电平时,所述控制单元闭合,所述判断模块的输出信号传输至所述第二加扰模块。
- 根据权利要求9所述的扰码装置,其中所述控制单元为取反逻辑门。
- 根据权利要求8所述的扰码装置,其中所述第一控制信号和所述第二控制信号包括逻辑数字信号和使能数据信号。
- 根据权利要求11所述的扰码装置,其中所述原始数据信号具有8个比特数目。
- 根据权利要求8所述的扰码装置,其中所述第一控制信号与所述第二控制信号互为取反数据值。
- 一种扰码方法,包括如下步骤:获取显示画面的原始数据信号;对所述原始数据信号进行判断,当所述原始数据信号为高电平信号时,则输出第一控制信号,当所述原始数据信号为低电平信号时,则输出第二控制信号;接收所述第一控制信号和所述第二控制信号,对所述第一控制信号和所述第二控制信号加扰处理;其中,对所述第一控制信号加扰处理并得到第一扰码数据信号,对所述第二控制信号加扰处理时,对所述第二控制信号取反后在进行加扰处理并得到第二扰码数据信号;接收所述第一扰码数据信号和所述第二扰码数据信号,并输出。
- 根据权利要求15所述的扰码方法,其中通过第一加扰模块对所述第一控制信号进行加扰处理,通过第二加扰模块对所述第二控制信号进行加扰处理。
- 根据权利要求16所述的扰码方法,其中所述第一控制信号包括N个数据比特流,所述第二控制信号包括N个数据比特流;当N=1时,当第i个数据比特流到来时,所述第一控制信号为高电平信号,所述第一控制信号经过所述第一加扰模块处理后,得到第i个数据比特流,当第i+1个数据比特流到来时,所述第二控制信号为低电平信号,所述第二控制信号经过所述第二加扰模块处理,得到第i+1个数据比特流,i为大于等于1的整数;当N=2时,当第i个和第i+1个数据比特流到来时,所述第一控制信号为高电平信号,所述第一控制信号经过所述第一加扰模块处理后,得到第i个数据比特流,当第i+2个和第i+3个数据比特流到来时,所述第二控制信号为低电平信号,所述第二控制信号经过所述第二加扰模块处理,得到第i+2个和第i+3个数据比特流,i为大于等于1的整数。
- 根据权利要求15所述的扰码方法,其中所述第一控制信号和所述第二控制信号包括逻辑数字信号和使能数据信号。
- 根据权利要求18所述的扰码方法,其中所述第一控制信号与所述第二控制信号互为取反数据值。
- 根据权利要求15所述的扰码方法,其中所述原始数据信号具有8个比特数目。
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