WO2022166312A1 - 阵列基板和显示装置 - Google Patents

阵列基板和显示装置 Download PDF

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Publication number
WO2022166312A1
WO2022166312A1 PCT/CN2021/131947 CN2021131947W WO2022166312A1 WO 2022166312 A1 WO2022166312 A1 WO 2022166312A1 CN 2021131947 W CN2021131947 W CN 2021131947W WO 2022166312 A1 WO2022166312 A1 WO 2022166312A1
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Prior art keywords
layer
array substrate
conductive layer
electrode plate
electrically connected
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PCT/CN2021/131947
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English (en)
French (fr)
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袁粲
李永谦
袁志东
徐攀
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US17/914,466 priority Critical patent/US20230122411A1/en
Publication of WO2022166312A1 publication Critical patent/WO2022166312A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate and a display device.
  • the second conductive layer is disposed on the side of the first conductive layer away from the gate layer, and the second electrode of the storage capacitor is disposed at least on the second conductive layer;
  • the first electrode of the storage capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is arranged on the first conductive layer, the second electrode plate is arranged on the gate layer, the The first electrode plate and the second electrode plate are electrically connected through a via hole; the second electrode plate is also electrically connected with the gate of the driving transistor;
  • the first storage capacitor, the second storage capacitor and the third storage capacitor are connected in parallel to form the storage capacitor.
  • the light shielding layer is multiplexed into the fourth electrode plate.
  • the array substrate further includes:
  • first interlayer dielectric layer disposed between the active layer and the first conductive layer, and a via hole is disposed on the first interlayer dielectric layer
  • the third electrode plate and the fourth electrode plate are connected through via holes on the buffer layer, the first interlayer dielectric layer and the second interlayer dielectric layer.
  • the scan line includes a first scan line
  • the array substrate further includes a second transistor, the gate of the second transistor is electrically connected to the first scan line, the first stage of the second transistor is electrically connected to the data line, and the second transistor is electrically connected to the data line.
  • the second stage is electrically connected to the gate of the drive transistor.
  • the scan line further includes a second scan line
  • the array substrate further includes a third transistor, the gate of the third transistor is electrically connected to the second scan line, the first stage of the third transistor is multiplexed into the second stage of the driving transistor, the The second stage of the third transistor is electrically connected to the sense line.
  • the array substrate further includes:
  • the sensing connection part is arranged on the second conductive layer, and the sensing connection part is electrically connected with the second stage of the third transistor through a via hole;
  • the via holes on the third interlayer dielectric layer and the first flat layer are formed through a one-step patterning process using a halftone mask.
  • the light-emitting unit includes a cathode layer and an anode layer disposed oppositely, and an organic light-emitting layer disposed between the cathode layer and the anode layer, and the anode layer is located on the
  • the third conductive layer is located on the side away from the base substrate, and the cathode layer is located at the side of the anode layer away from the base substrate;
  • the array substrate further includes:
  • An auxiliary cathode layer, the auxiliary cathode layer is arranged between the anode layer and the third conductive layer, and is electrically connected to the cathode layer.
  • an insulating layer arranged between the third conductive layer and the light-emitting unit, and a via hole is arranged on the insulating layer;
  • the anode layer is electrically connected to the drain of the driving transistor through at least the auxiliary cathode layer, the insulating layer, and the via hole on the second flat layer.
  • the via holes on the insulating layer and the second flat layer are formed by a one-step patterning process using a halftone mask.
  • Fig. 2 is the 3T1C circuit structure of two pixel units
  • Fig. 3 is the 3T1C circuit structure of one sub-pixel
  • FIG. 4 is a schematic structural diagram of a light-shielding layer
  • FIG. 6 is a schematic structural diagram of a gate layer
  • FIG. 8 is a schematic structural diagram of a first conductive layer
  • FIG. 9 is a schematic diagram of a via hole on the second interlayer dielectric layer
  • FIG. 12 is a schematic structural diagram of a third conductive layer
  • FIG. 14 is a schematic structural diagram of an auxiliary cathode layer
  • FIG. 2 shows a 3T1C circuit structure of two pixel units
  • FIG. 3 shows a 3T1C circuit structure of one sub-pixel.
  • the sub-pixel circuit structure includes a capacitor and three TFT transistors T1-T9.
  • all TFTs are N-type TFTs, wherein the first transistor T1 is a driving transistor, and the other transistors are switching transistors.
  • each pixel unit includes three sub-pixels, corresponding to red sub-pixels, green sub-pixels and blue sub-pixels respectively.
  • the gates 2g of the six second transistors T2 in the six sub-pixel circuit structures are commonly connected to the same first scan line 11 (G1), and the gates 3g of the six third transistors T3 are commonly connected to the same second scan line 12 (G2), the drains 3d of the six third transistors T3 are commonly connected to the same sensing line 40 (sense).
  • 400 is provided between the active layer 300 and the gate layer 500, and a first interlayer dielectric layer 600 is provided between the gate insulating layer 400 and the first conductive layer 700.
  • the first conductive layer A second interlayer dielectric layer 800 is provided between the layer 700 and the second conductive layer 900 , and a third interlayer dielectric layer 1000 is provided between the second conductive layer 900 and the third conductive layer 1200 .
  • An insulating layer is provided between the third conductive layer 1200 and the anode layer 1700 .
  • a buffer layer 200 is further disposed under the active layer 300 for protecting the base substrate 1 .
  • FIGS. 4-16 are schematic diagrams of stacking of each film layer in sequence
  • FIG. 1 is a schematic cross-sectional view along the A-A direction in FIG. 16 .
  • FIG. 4 is a schematic structural diagram of the light shielding layer 100 .
  • FIG. 5 is a schematic structural diagram of the active layer 300 .
  • the active layer 300 is used to set the channel region (1g-3g), the first stage (1s-3s) and the second stage (1d-3d) of each TFT transistor.
  • 6 is a schematic diagram of the structure of the gate layer 500, the gate layer 500 is used to set the gates (eg: 1g-3g) of the transistors in the sub-pixel driving circuit, as well as the first scan line 11 and the second scan line 12. .
  • the first scan lines 11 and the second scan lines 12 are arranged at intervals in the column direction and extend in the row direction, and are used for providing scan signals to each sub-pixel located in the same row in the row direction.
  • the first scan line 11 is located below the sub-pixel area
  • the second scan line 12 is located above the sub-pixel area.
  • the gate 1g of the driving transistor T1 is multiplexed as the second plate 52 of the storage capacitor.
  • FIG. 7 shows the via holes 91 provided on the first interlayer dielectric layer 600 .
  • the first interlayer dielectric layer is a transparent film layer, so only the positions of the via holes are shown in the figure.
  • FIG. 8 shows a schematic structural diagram of the first conductive layer 700 .
  • the first electrode plate 51 of the storage capacitor is disposed in the first conductive layer 700 , and the first electrode plate 51 and the second electrode plate 52 are electrically connected through via holes to form the first electrode Cst1 of the storage capacitor.
  • the first conductive layer 700 is also provided with a first connection part 61 , one end of the first connection part 61 is connected to the gate 1g of the driving transistor T1 , and the other end is connected to the second through the via hole provided on the first interlayer dielectric layer 600 .
  • the drain 2d of the transistor is connected to connect the gate 1g of the drive transistor T1 to the drain 2d of the second transistor.
  • the second connection portion 62 is connected to the source electrode 2s of the second transistor through a via hole provided on the first interlayer dielectric layer 600 .
  • the first conductive layer 700 is further provided with a fifth connection part 65, the fifth connection part 65 is connected to the drain 1d of the driving transistor T1 through a via hole arranged on the first interlayer dielectric layer 600, and is also The via holes on the interlayer dielectric layer 600 and the buffer layer 200 are connected to the light shielding layer 100 .
  • the projection of the first pole plate 51 and the third pole plate 53 on the base substrate 1 has overlapping, forming the first storage capacitor;
  • the projection of the second pole plate 52 and the fourth pole plate 54 have overlapping projections on the substrate substrate 1 to form the third storage capacitor;
  • the first storage capacitor, the second storage capacitor and the third storage capacitor The storage capacitor is connected in parallel to form a storage capacitor, which can improve the storage effect of the capacitor.
  • the second conductive layer 900 is further provided with a sensing connection part 68 , and the sensing connection part 68 is electrically connected to the second stage 3d of the third transistor T3 through the via hole provided on the second interlayer dielectric layer 800 .
  • Data lines 20 , power lines 30 and sensing lines 40 are disposed in the third conductive layer 1200 .
  • the sensing line 40 and the sensing connection part 68 are electrically connected through the via hole provided on the third interlayer dielectric layer 1000 , so that the second stage of the third transistor is connected with the sensing line 40 .
  • the sensing connection portion 68 in every two pixel units is connected to the sensing line 40 through a via hole disposed on the third interlayer dielectric layer 1000 . In this embodiment, the via hole is located between the two pixel units. .
  • the data line 20 is connected to the sixth connection part 66 through the via hole provided on the third interlayer dielectric layer 1000, and then connected to the source electrode 2s of the second transistor through the second connection part 62, so as to realize the application of data to the second transistor Voltage.
  • the power line 30 is connected to the seventh connection portion 67 through the via hole provided on the third interlayer dielectric layer 1000, and is further connected to the source 1s of the driving transistor T1 via the fourth connection portion, so as to apply the power supply voltage to the driving transistor T1 .
  • three sub-pixels in each pixel unit share one power supply line 30 , and each sub-pixel corresponds to its own data line 20 .
  • a first flat layer 1100 is also provided between the second conductive layer 900 and the third conductive layer 1200 , and via holes are also provided on the first flat layer 1100 , in the second conductive layer 900 and in the third conductive layer 1200 Each structure of 100 is electrically connected through the via holes in the third interlayer dielectric layer 1000 and the via holes in the first flat layer 1100 .
  • the first flat layer 1100 can increase the thickness between the third conductive layer 1200 and the gate layer 500 , which can reduce the overlap capacitance, and can also reduce the risk of short circuit and thus improve the yield.
  • FIG. 13 shows the via holes 94 provided on the first insulating layer 1300 and the second planar layer 1400 .
  • FIG. 14 shows a schematic structural diagram of the auxiliary cathode layer 1500 .
  • FIG. 15 shows a schematic structural diagram of the anode layer 1700 .
  • FIG. 16 shows a schematic structural diagram of the pixel definition layer 2000 .
  • the array substrate further includes an auxiliary cathode layer 1500, which is arranged between the anode layer 1700 and the third conductive layer 1200, and is electrically connected to the cathode layer 1900 to reduce the resistance of the cathode layer 1900, thereby reducing the IR of vss drop.
  • an auxiliary cathode layer 1500 which is arranged between the anode layer 1700 and the third conductive layer 1200, and is electrically connected to the cathode layer 1900 to reduce the resistance of the cathode layer 1900, thereby reducing the IR of vss drop.
  • a second insulating layer 1600 is disposed between the auxiliary cathode layer 1500 and the anode layer 1700 .
  • a first insulating layer 1300 and a second flat layer 1400 are arranged between the auxiliary cathode layer 1500 and the third conductive layer 1200 , and via holes 94 are arranged on the first insulating layer 1300 and the second flat layer 1400 , and the auxiliary cathode layer 1500 There are also via holes, and the anode layer 1700 is connected to the third electrode plate 53 through the via holes on the auxiliary cathode layer 1500, the first insulating layer 1300, and the second flat layer 1400, and then is connected to the driving transistor T1 via the fifth connection portion 65.
  • the auxiliary cathode layer may not be provided, and the anode layers 1700 are connected to the third electrode plate 53 through vias provided on the insulating layer, and then to the drain of the driving transistor T1 through the fifth connection portion 65 .
  • the electrode 1d is connected so that the anode layer 1700 is connected to the drain 1d of the driving transistor T1.
  • the impedance load is reduced by about 40%, and the overlap capacitance between Gate and SD3 is also reduced accordingly (the impedance load is reduced by about 15%). While the impedance load is effectively reduced, the VDD IR Drop It has also been reduced accordingly, providing technical support for large-size ultra-high PPI.
  • Step S100 a base substrate 1 is provided, and a light shielding layer 100 and a buffer layer 200 covering the light shielding layer 100 are formed on the base substrate 1 .
  • step S200 the active layer 300 , the gate insulating layer 400 and the gate layer 500 are formed on the buffer layer 200 to form the driving transistor T1 , the second transistor and the third transistor.
  • the gate 1g of the driving transistor T1 is multiplexed as the second electrode plate 52 of the storage capacitor.
  • a first interlayer dielectric layer 600 and a first conductive layer 700 are formed above the gate layer 500, so that the first conductive layer 700 contains the first electrode plate 51 of the storage capacitor, and the first electrode plate 51 and the second electrode plate 51 are formed.
  • the stages are connected through vias on the first interlayer dielectric layer 600 .
  • the first conductive layer 700 further includes a fifth connection part 65 , and the fifth connection part 65 is connected to the light shielding layer 100 through the via hole on the first interlayer dielectric layer 600 .
  • the first conductive layer 700 is further formed with a first connection portion 61 to a fifth connection portion 65.
  • the first connection portion 61 is used to connect the gate 1g of the driving transistor T1 to the drain 2d of the second transistor, and the second connection portion 62 is connected to the source electrode 2s of the second transistor through a via hole provided on the first interlayer dielectric layer 600 .
  • the third connection portion 63 is connected to the drain electrode 3d of the third transistor through the via hole provided on the first interlayer dielectric layer 600 , and the fourth connection portion is connected to the driving transistor through the via hole provided on the first interlayer dielectric layer 600 .
  • the source 1s of T1 is connected.
  • step S400 a second interlayer dielectric layer 800 and a second conductive layer 900 are formed above the first conductive layer 700, so that the second conductive layer 900 contains the third electrode plate 53 of the storage capacitor, and the third electrode plate 53 passes through the third electrode plate 53.
  • the via hole on the interlayer dielectric layer 800 is connected to the fifth connection portion 65 , and further connected to the light shielding layer 100 , and the light shielding layer 100 is multiplexed as the fourth electrode plate 54 of the storage capacitor.
  • the first electrode plate 51 and the third electrode plate 53 form the first storage capacitor
  • the first electrode plate 51 and the fourth electrode plate 54 form the second storage capacitor
  • the second electrode plate 52 and the fourth electrode plate 54 form the third storage capacitor
  • the first storage capacitor, the second storage capacitor and the third storage capacitor are connected in parallel to form a storage capacitor.
  • the second conductive layer 900 further includes a sensing connection part 68 , a sixth connection part 66 and a seventh connection part 67 , and the sensing connection part 68 is connected to the second connection part of the third transistor through the via hole on the first interlayer dielectric layer 600 . level electrical connection.
  • the sixth connection part 66 is connected to the second connection part 62 through the via hole provided on the second interlayer dielectric layer 800
  • the seventh connection part 67 is connected to the fourth connection part 67 through the via hole provided on the second interlayer dielectric layer 800 .
  • Department connection is provided.
  • Step S500 forming a third interlayer dielectric layer 1000 , a first flat layer 1100 and a third conductive layer 1200 over the second conductive layer 900 , so that the third conductive layer 1200 includes the data lines 20 , the power lines 30 and the sensing lines 40 .
  • the sensing line 40 is connected to the sensing connection portion 68 through the third interlayer dielectric layer 1000 and the via hole on the first flat layer 1100, and is further connected to the second stage of the third transistor.
  • the data line 20 is connected to the sixth connection part 66 through the via hole provided on the third interlayer dielectric layer 1000 and the first flat layer 1100 , and is further connected to the source electrode 2s of the second transistor through the second connection part 62 .
  • the power line 30 is connected to the seventh connection portion 67 through vias provided on the third interlayer dielectric layer 1000 and the first flat layer 1100 , and is further connected to the source 1s of the driving transistor T1 through the fourth connection portion.
  • a pixel defining layer 2000 with an opening area is formed, the anode layer 1700 is exposed in the opening area, an organic light emitting layer 1800 is formed in the opening area, and finally a cathode layer 1900 is formed, and the cathode layer 1900 is connected with the auxiliary cathode layer 1500 .
  • the via holes may be formed through a one-step etching process using a half-tone mask when forming the via holes on the first interlayer dielectric layer 600 and the buffer layer 200 .
  • the via hole may be formed by a half-tone mask and a one-step etching process when forming the via hole on the third interlayer dielectric layer 1000 and the first flat layer 1100 .
  • a half-tone mask may be used to form the vias through a one-step etching process.
  • step S500 when a halftone mask is used for etching, a whole-surface third interlayer dielectric layer 1000 is firstly formed by processes such as deposition, and then a whole-surface first flat layer 1100 is formed by processes such as printing. Vias with different depths are formed by using a halftone mask at the positions where vias need to be formed by a photolithography process.
  • the present disclosure also provides a display device including the array substrate in the above embodiments. Since the display device includes the above-mentioned array substrate, it has the same beneficial effects, and details are not described herein again in this disclosure.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

提供一种阵列基板和显示装置。阵列基板包括衬底基板和依次层叠设置于衬底基板上的扫描线、数据线、电源线、感测线、像素驱动电路和发光单元，阵列基板还包括栅极层、第一导电层、第二导电层、第三导电层，存储电容的第一电极至少设于第一导电层，存储电容的第二电极至少设于第二导电层；数据线、电源线、感测线设于第三导电层。能够提供较高的像素密度（PPI）。

Description

阵列基板和显示装置
交叉引用
本公开要求于2021年2月5日提交的申请号为202110162501.X名称为“阵列基板和显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种阵列基板和显示装置。
背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示技术，以其轻薄、自发光、视角广、响应速度快、亮度低、功耗低等优点，被业界公认为第三代显示技术，已广泛地被应用于高性能显示领域中。
随着对显示面板PPI(像素密度)的要求越来越高，面板上的布线压力也越来越大，既需要考虑各种线路能够紧密排布，又要尽量降低各种线路之间的互相影响，因此对布线设计提出了更高的要求。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种阵列基板和显示装置。
根据本公开的一个方面，提供一种阵列基板，包括衬底基板和依次层叠设置于所述衬底基板上的扫描线、数据线、电源线、感测线、像素驱动电路和发光单元，所述像素驱动电路包括驱动晶体管和存储电容，所述存储电容包括第一电极和第二电极，所述驱动晶体管的第一级与所述电源线电连接，第二级与所述发光单元电连接，栅极与所述存储电容的第二电极电连接；所述阵列基板包括：
栅极层，设于所述衬底基板，所述扫描线、驱动晶体管的栅极设于所述栅极层；
第一导电层，设于所述栅极层背离所述衬底基板的一侧，所述存储电容的第一电极至少设于所述第一导电层；
第二导电层，设于所述第一导电层背离所述栅极层一侧，所述存储电容的第二电极至少设于所述第二导电层；
第三导电层，设于所述第二导电层背离所述第一导电层一侧，所述数据线、电源线、感测线设于所述第三导电层。
在本公开的一种示例性实施例中，所述阵列基板还包括有源层，所述有源层设于所述衬底基板和所述栅极层之间；
所述存储电容的第一电极包括第一极板和第二极板，所述第一极板设于所述第一导电层，所述第二极板设于所述栅极层，所述第一极板和第二极板通过过孔电连接；所述第二极板还与所述驱动晶体管的栅极电连接；
所述存储电容的第二电极包括第三极板和第四极板，所述第三极板设于所述第二导电层，所述第四极板至少设于所述有源层背离所述栅极层的一侧，所述第三极板和第四极板通过过孔电连接；所述第三极板还与所述发光单元电连接；
其中，所述第一极板和第三极板在所述衬底基板的投影具有重叠，形成第一存储电容；所述第一极板和第四极板在所述衬底基板的投影具有重叠，形成第二存储电容；所述第二极板和第四极板在所述衬底基板的投影具有重叠，形成第三存储电容；
所述第一存储电容、第二存储电容和第三存储电容并联形成所述存储电容。
在本公开的一种示例性实施例中，所述驱动晶体管的栅极复用为所述第二极板。
在本公开的一种示例性实施例中，所述阵列基板还包括遮光层，所述遮光层位于所述有源层背离所述栅极层的一侧，且在所述衬底基板上的投影与所述驱动晶体管的栅极具有重叠。
在本公开的一种示例性实施例中，所述遮光层复用为所述第四极板。
在本公开的一种示例性实施例中，所述阵列基板还包括：
缓冲层，设于所述有源层和遮光层之间，所述缓冲层上设置有过孔；
第一层间介质层，设于所述有源层和第一导电层之间，所述第一层间介质层上设置有过孔；
第二层间介质层，设于所述第一导电层和第二导电层之间，所述第二层间介质层上设置有过孔；
所述第三极板和第四极板通过所述缓冲层、第一层间介质层和第二层间介质层上的过孔相连。
在本公开的一种示例性实施例中，所述缓冲层和第一层间介质层上的过孔采用半色调掩模版通过一步构图工艺形成。
在本公开的一种示例性实施例中，所述扫描线包括第一扫描线；
所述阵列基板还包括第二晶体管，所述第二晶体管的栅极电连接所述第一扫描线，所述第二晶体管的第一级电连接所述数据线，所述第二晶体管的第二级电连接所述驱动晶体管的栅极。
在本公开的一种示例性实施例中，所述扫描线还包括第二扫描线；
所述阵列基板还包括第三晶体管，所述第三晶体管的栅极电连接所述第二扫描线，所述第三晶体管的第一级复用为所述驱动晶体管的第二级，所述第三晶体管的第二级电连接所述感测线。
在本公开的一种示例性实施例中，所述阵列基板还包括：
感测连接部，所述感测连接部设于所述第二导电层，所述感测连接部与所述第三晶体管的第二级通过过孔电连接；
所述感测连接部还与所述感测线通过过孔电连接。
在本公开的一种示例性实施例中，所述第二导电层和第三导电层之间设置有第三层间介质层和第一平坦层，所述第三层间介质层和第一平坦层上设置有过孔，所述感测连接部和所述感测线通过所述第三层间介质层和第一平坦层上的过孔电连接。
在本公开的一种示例性实施例中，所述第三层间介质层和第一平坦层上的过孔采用半色调掩模版通过一步构图工艺形成。
在本公开的一种示例性实施例中，所述发光单元包括相对设置的阴极层和阳极层，以及设于所述阴极层和阳极层之间的有机发光层，所述阳极层位于所述第三导电层背离所述衬底基板的一侧，所述阴极层位于所述阳极层背离所述衬底基板的一侧；所述阵列基板还包括：
辅助阴极层，所述辅助阴极层设于所述阳极层和第三导电层之间，且与所述阴极层电连接。
在本公开的一种示例性实施例中，所述辅助阴极层上设有过孔，所述阵列基板还包括：
绝缘层，设于所述第三导电层和发光单元之间，所述绝缘层上设置有过孔；
第二平坦层，设于所述绝缘层和发光单元之间，所述第二平坦层上设置有过孔；
所述阳极层至少通过所述辅助阴极层、绝缘层、第二平坦层上的过孔与所述驱动晶体管的漏极电连接。
在本公开的一种示例性实施例中，所述绝缘层和第二平坦层上的过孔采用半色调掩模版通过一步构图工艺形成。
根据本公开的另一个方面，提供一种显示装置，包括以上所述的阵列基板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本实施方式中阵列基板的结构示意图；
图2为两个像素单元的3T1C电路结构；
图3为一个子像素的3T1C电路结构；
图4为遮光层的结构示意图；
图5为有源层的结构示意图；
图6为栅极层的结构示意图；
图7为第一层间介质层上的过孔示意图；
图8为第一导电层的结构示意图；
图9为第二层间介质层上的过孔示意图；
图10为第二导电层的结构示意图；
图11为第三层间介质层、第一平坦层上的过孔示意图；
图12为第三导电层的结构示意图；
图13为第一绝缘层和第二平坦层上的过孔示意图；
图14为辅助阴极层的结构示意图；
图15为阳极层的结构示意图；
图16为像素界定层的结构示意图。
附图标记说明：
1、衬底基板；100、遮光层；200、缓冲层；300、有源层；400、栅绝缘层；500、栅极层；600、第一层间介质层；700、第一导电层；800、第二层间介质层；900、第二导电层；1000、第三层间介质层；1100、第一平坦层；1200、第三导电层；1300、第一绝缘层；1400、第二平坦层；1500、辅助阴极层；1600、第二绝缘层；1700、阳极层；1800、有机发光层；1900、阴极层；2000、像素界定层；
11、第一扫描线；12、第二扫描线；20、数据线；30、电源线；40、感测线；51、第一极板；52、第二极板；53、第三极板；54、第四极板；61、第一连接部；62、第二连接部；63、第三连接部；64、第四连接部；65、第五连接部；66、第六连接部；67、第七连接部；68、感测连接部；
91、92、93、94、过孔。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一 个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本公开实施方式提供了一种阵列基板，参考图1，包括衬底基板1和依次层叠设置于衬底基板1上的数据线20、电源线30、感测线40、像素驱动电路和发光单元，像素驱动电路包括驱动晶体管T1和存储电容，存储电容包括第一电极和第二电极，驱动晶体管T1的第一级与电源线30电连接，第二级与发光单元电连接，栅极与存储电容的第二电极电连接。
阵列基板包括栅极层500、第一导电层700、第二导电层900和第三导电层1200。栅极层500设于衬底基板1，驱动晶体管的栅极设于栅极层500。第一导电层700设于栅极层500背离衬底基板1的一侧，存储电容的第一电极至少设于第一导电层700。第二导电层900设于第一导电层700背离栅极层500一侧，存储电容的第二电极至少设于第二导电层900。第三导电层1200设于第二导电层900背离第一导电层700一侧，数据线20、电源线30、感测线40设于第三导电层1200。
本公开在栅极层500上共设置三层导电层，第一导电层700、第二导电层900和第三导电层1200可以分别看做第一源漏极层、第二源漏极层和第三源漏极层。第一导电层700、第二导电层900用于设置存储电容，第三导电层1200用于设置数据线20、电源线30、感测线40，为信号线提供了充足的布线空间，满足驱动刷新频率的同时，可降低数据线20的电阻及电源线30的IR drop。相比将上述结构均设置在一层或两层 导电层内，大大减轻了布线空间压力，对于横向固定尺寸的显示产品而言，能够提供较高的像素PPI，尤其适用于超高像素PPI的产品。另外，本公开将扫描线和数据线20、电源线30、感测线40分开，在降低负载的基础上，也降低了层与层之间的短接机率，进而提升了产品良率。
下面对本公开实施方式的阵列基板进行详细的说明。
参考图2和图3，参考图2示出了两个像素单元的3T1C电路结构，图3示出了一个子像素的3T1C电路结构。子像素电路结构包括一个电容和三个TFT晶体管T1～T9，本实施例中，所有TFT均为N型TFT，其中第一晶体管T1为驱动晶体管，其他晶体管为开关晶体管。
电容包括第一电极Cst1和第二电极Cst2，第一电极Cst1连于节点N1，第二电极Cst2连于节点N2。驱动晶体管T1(第一晶体管)的栅极1g连于节点N1，源极1s与电源线30(vdd)连接，漏极1d连于节点N2。第二晶体管T2的栅极2g与第一扫描线11(G1)连接，源极2s与数据线20(data)连接，漏极2d连于节点N1。第三晶体管T3的栅极3g与第二扫描线12(G2)连接，源极3s连于节点N2，漏极3d与感测线40(sense)连接。
参考图2，每个像素单元包括三个子像素，分别对应红色子像素、绿色子像素和蓝色子像素。六个子像素电路结构中的六个第二晶体管T2的栅极2g共同连接于同一根第一扫描线11(G1)，六个第三晶体管T3的栅极3g共同连接于同一根第二扫描线12(G2)，六个第三晶体管T3的漏极3d共同连接于同一根感测线40(sense)。
在本实施方式中，上述各子像素的子像素驱动电路制备于一衬底基板1。结合图1，衬底基板1上由下至上依次层叠设置有源层300、栅极层500、第一导电层700、第二导电层900、第三导电层1200，第三导电层1200上还设置有发光单元，本公开中发光单元以OLED发光器件为例，包括由下至上依次层叠设置的阳极层1700、有机发光层1800、阴极层1900。两膜层之间通过绝缘材料进行绝缘，例如有源层300和栅极层500之间设置400，栅绝缘层400和第一导电层700之间设置第一层间介质层600，第一导电层700和第二导电层900之间设置第二层间介质层800，第二导电层900和第三导电层1200之间设置第三层间介质层1000。 第三导电层1200和阳极层1700之间设置有绝缘层。有源层300下方还设置有缓冲层200，用于对衬底基板1进行保护。阵列基板还包括遮光层100，遮光层100位于有源层300背离栅极层500的一侧，具***于缓冲层200和衬底基板1之间，且在衬底基板1上的投影与驱动晶体管T1的栅极具有重叠，用于防止背面的环境光对驱动晶体管T1造成影响。各子像素的OLED发光器件通过像素界定层2000进行间隔。
图4-图16依次示出了各膜层的堆叠示意图，图1为图16中A-A向的截面示意图。
图4为遮光层100的结构示意图。图5为有源层300的结构示意图。有源层300用于设置各TFT晶体管的沟道区(1g-3g)、第一级(1s-3s)和第二级(1d-3d)。参考图6为栅极层500的结构示意图，栅极层500用于设置形成子像素驱动电路中各晶体管的栅极(如：1g-3g)、以及第一扫描线11和第二扫描线12。第一扫描线11和第二扫描线12均沿列方向间隔排列且沿行方向延伸，用于向行方向上位于同一行的各子像素提供扫描信号。本实施例中，第一扫描线11位于子像素区域的下方，第二扫描线12位于子像素区域的上方。本实施例中，驱动晶体管T1的栅极1g复用为存储电容的第二极板52。
图7示出了第一层间介质层600上设置的过孔91，第一层间介质层为透明膜层，因此图中仅表示出了过孔位置。图8示出了第一导电层700的结构示意图。
第一导电层700内设置有存储电容的第一极板51，第一极板51和第二极板52通过过孔电连接，组成存储电容的第一电极Cst1。
第一导电层700内还设置有第一连接部61，第一连接部61一端与驱动晶体管T1的栅极1g连接，另一端通过设置在第一层间介质层600上的过孔与第二晶体管的漏极2d连接，以将驱动晶体管T1的栅极1g与第二晶体管的漏极2d连接。第二连接部62通过设置在第一层间介质层600上的过孔与第二晶体管的源极2s连接。
第一导电层700内还设置有第三连接部63和第四连接部64，第三连接部63通过设置在第一层间介质层600上的过孔与第三晶体管的漏极3d连接，第四连接部64通过设置在第一层间介质层600上的过孔与驱 动晶体管T1的源极1s连接。
第一导电层700内还设置有第五连接部65，第五连接部65通过设置在第一层间介质层600上的过孔与驱动晶体管T1的漏极1d连接，还通过设置在第一层间介质层600和缓冲层200上的过孔与遮光层100连接。
图9示出了第二层间介质层800上设置的过孔92。图10示出了第二导电层900的结构示意图。
第二导电层900内设置存储电容的第三极板53，本实施例中，第三极板53通过设置于第二层间介质层800上的过孔与第五连接部65连接，使得遮光层100与第三极板53连接，进而使得遮光层100可以复用为第四极板54。第三极板53和第四极板54通过过孔电连接，组成存储电容的第二电极Cst2。由于遮光层100需要复用为第四极板54，因此遮光层100需要具有导电性，其可以采用金属等导电材料制成。
上述四个极板中，第一极板51和第三极板53在衬底基板1的投影具有重叠，形成第一存储电容；第一极板51和第四极板54在衬底基板1的投影具有重叠，形成第二存储电容；第二极板52和第四极板54在衬底基板1的投影具有重叠，形成第三存储电容；第一存储电容、第二存储电容和第三存储电容并联形成存储电容，可提高电容存储效果。
第二导电层900内还设置有感测连接部68，感测连接部68通过设置在第二层间介质层800上的过孔与第三晶体管T3的第二级3d电连接，本实施方式中，每两个像素单元内的六个子像素的感测连接部68连接为一体，整体沿行方向延伸。
第二导电层900内还设置有第六连接部66和第七连接部67，第六连接部66通过设置在第二层间介质层800上的过孔与第二连接部62连接，第七连接部67通过设置在第二层间介质层800上的过孔与第四连接部64连接。
图11示出了第三层间介质层1000、第一平坦层1100上设置的过孔93。图12示出了第三导电层1200的结构示意图。
第三导电层1200内设置有数据线20、电源线30和感测线40。感测线40与感测连接部68通过设置在第三层间介质层1000上的过孔电连接， 以使第三晶体管的第二级与感测线40连接。每两个像素单元内的感测连接部68通过设置于第三层间介质层1000上的一个过孔实现与感测线40的连接，本实施例中，该过孔位于两个像素单元中间。数据线20通过设置于第三层间介质层1000上的过孔与第六连接部66连接，进而经由第二连接部62与第二晶体管的源极2s连接，以实现对第二晶体管施加数据电压。电源线30通过设置于第三层间介质层1000上的过孔与第七连接部67连接，进而经由第四连接部与驱动晶体管T1的源极1s连接，以实现对驱动晶体管T1施加电源电压。本实施方式中，每个像素单元内的三个子像素共用一条电源线30，每个子像素对应有各自的数据线20。
进一步地，第二导电层900和第三导电层1200之间还设置有第一平坦层1100，第一平坦层1100上也设置有过孔，第二导电层900内和第三导电层1200内的各结构通过第三层间介质层1000的过孔和第一平坦层1100上的过孔共同实现电连接。第一平坦层1100能够增加第三导电层1200与栅极层500之间的厚度，可降低交叠电容，也可降低短接风险进而提升良率。
需要说明的是，由于第三层间介质层1000、第一平坦层1100上的过孔位置重叠，因此图11中93所标识的过孔包括第三层间介质层1000上的六边形过孔和第一平坦层1100上的三角形过孔。第三层间介质层1000的过孔和第一平坦层1100上的过孔可以分为两步先后刻蚀形成，也可以采用半色调掩模版通过一步构图工艺形成，由此可以减少光刻次数。
图13示出了第一绝缘层1300和第二平坦层1400上设置的过孔94。图14示出了辅助阴极层1500的结构示意图。图15示出了阳极层1700的结构示意图。图16示出了像素界定层2000的结构示意图。
阵列基板还包括辅助阴极层1500，辅助阴极层1500设于阳极层1700和第三导电层1200之间，且与阴极层1900电连接，起到降低阴极层1900电阻的作用，进而降低vss的IR Drop。
辅助阴极层1500和阳极层1700之间设置有第二绝缘层1600。辅助阴极层1500和第三导电层1200之间设有第一绝缘层1300和第二平坦层1400，第一绝缘层1300和第二平坦层1400上均设置有过孔94，辅助阴 极层1500上也设有过孔，阳极层1700通过辅助阴极层1500、第一绝缘层1300、第二平坦层1400上的过孔与第三极板53连接，进而经由第五连接部65与驱动晶体管T1的漏极1d连接，使得阳极层1700与驱动晶体管T1的漏极1d连接。第二平坦层1400的设计也可降低辅助阴极层1500和第三导电层1200之间的交叠电容，也可降低短接风险进而提升良率。
在另一种实施方式中，可以不设置辅助阴极层，阳极层1700之间通过设置在绝缘层上的过孔与第三极板53连接，进而经由第五连接部65与驱动晶体管T1的漏极1d连接，使得阳极层1700与驱动晶体管T1的漏极1d连接。
本公开图1所示的阵列基板，其阻抗负载降低约40％，Gate与SD3之间的交叠电容也相应减小(阻抗负载降低约15％)，有效降低阻抗负载的同时，VDD IR Drop也相应进行了降低，为大尺寸超高PPI提供了技术支持。
下面对本公开阵列基板的制备方法进行说明，形成图1所示的阵列基板，该制备方法包括：
步骤S100，提供衬底基板1，并在衬底基板1上形成遮光层100和覆盖遮光层100的缓冲层200。
步骤S200，在缓冲层200上形成有源层300、栅绝缘层400和栅极层500，以形成驱动晶体管T1、第二晶体管、第三晶体管。其中，驱动晶体管T1的栅极1g复用为存储电容的第二极板52。
步骤S300，在栅极层500上方形成第一层间介质层600和第一导电层700，使第一导电层700包含存储电容的第一极板51，并使第一极板51和第二级板通过第一层间介质层600上的过孔连接。第一导电层700还包括第五连接部65，第五连接部65通过第一层间介质层600上的过孔与遮光层100连接。
第一导电层700内还形成有第一连接部61～第五连接部65，第一连接部61用于将驱动晶体管T1的栅极1g与第二晶体管的漏极2d连接，第二连接部62通过设置在第一层间介质层600上的过孔与第二晶体管的源极2s连接。第三连接部63通过设置在第一层间介质层600上的过孔 与第三晶体管的漏极3d连接，第四连接部通过设置在第一层间介质层600上的过孔与驱动晶体管T1的源极1s连接。第五连接部65通过设置在第一层间介质层600上的过孔与驱动晶体管T1的漏极1d连接，还通过设置在第一层间介质层600和缓冲层200上的过孔与遮光层100连接。
步骤S400，在第一导电层700上方形成第二层间介质层800和第二导电层900，使第二导电层900包含存储电容的第三极板53，并使第三极板53通过第二层间介质层800上的过孔与第五连接部65连接，进而与遮光层100连接，遮光层100复用为存储电容的第四极板54。
第一极板51和第三极板53形成第一存储电容，第一极板51和第四极板54形成第二存储电容，第二极板52和第四极板54形成第三存储电容，第一存储电容、第二存储电容和第三存储电容并联形成存储电容。
第二导电层900内还包含感测连接部68、第六连接部66和第七连接部67，感测连接部68通过第一层间介质层600上的过孔与第三晶体管的第二级电连接。第六连接部66通过设置在第二层间介质层800上的过孔与第二连接部62连接，第七连接部67通过设置在第二层间介质层800上的过孔与第四连接部连接。
步骤S500，在第二导电层900上方形成第三层间介质层1000、第一平坦层1100和第三导电层1200，使第三导电层1200包含数据线20、电源线30和感测线40。感测线40通过第三层间介质层1000、第一平坦层1100上的过孔与感测连接部68连接，进而与第三晶体管的第二级连接。数据线20通过设置于第三层间介质层1000、第一平坦层1100上的过孔与第六连接部66连接，进而经由第二连接部62与第二晶体管的源极2s连接。电源线30通过设置于第三层间介质层1000、第一平坦层1100上的过孔与第七连接部67连接，进而经由第四连接部与驱动晶体管T1的源极1s连接。
步骤S600，在第三导电层1200上方依次形成第一绝缘层1300、第二平坦层1400、辅助阴极层1500、第二绝缘层1600，并在这些膜层上形成过孔。再在第二绝缘层1600上形成发光单元，其中阳极层1700通过辅助阴极层1500、第一绝缘层1300、第二平坦层1400、第二绝缘层1600上的过孔与第三极板53连接，进而经由第五连接部65与驱动晶体 管T1的漏极1d连接，使得阳极层1700与驱动晶体管T1的漏极1d连接。
然后再形成具有开口区的像素界定层2000，开口区露出阳极层1700，并在开口区内形成有机发光层1800，最后形成阴极层1900，并使阴极层1900与辅助阴极层1500连接。
按照上述步骤逐步形成图1所示的结构过程中，共需要进行16次掩模工艺。为了减少工艺步骤，步骤S300中在第一层间介质层600和缓冲层200上形成过孔时可采用半色调掩模版通过一步刻蚀工艺形成。步骤S500中在第三层间介质层1000和第一平坦层1100上形成过孔时可采用半色调掩模版通过一步刻蚀工艺形成。步骤S600中在第一绝缘层1300和第二平坦层1400上形成过孔时可采用半色调掩模版通过一步刻蚀工艺形成。
以步骤S500为例，当采用半色调掩模版进行刻蚀时，先通过沉积等工艺形成整面的第三层间介质层1000，然后通过打印等工艺形成整面的第一平坦层1100，最后在需要形成过孔的位置通过半色调掩模版采用一道光刻工艺形成深度不同的过孔。
采用该刻蚀方式可使整个工艺只进行14次掩膜工艺，提高了制备效率，节省了掩膜板数量，降低了加工成本。当然，两个膜层上的过孔也可以分为两步先后刻蚀形成。
需要说明的是，尽管在附图中以特定顺序描述了本公开方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本公开还提供一种显示装置，包含以上实施方式中的阵列基板。由于该显示装置包括上述阵列基板，因此具有相同的有益效果，本公开在此不再赘述。
本公开对于显示装置的适用不做具体限制，其可以是电视机、笔记本电脑、平板电脑、可穿戴显示设备、手机、车载显示、导航、电子书、数码相框、广告灯箱等任何具有柔性显示功能的产品或部件。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (16)

  1. 一种阵列基板，包括衬底基板和依次层叠设置于所述衬底基板上的扫描线、数据线、电源线、感测线、像素驱动电路和发光单元，所述像素驱动电路包括驱动晶体管和存储电容，所述存储电容包括第一电极和第二电极，所述驱动晶体管的第一级与所述电源线电连接，第二级与所述发光单元电连接，栅极与所述存储电容的第二电极电连接；其中，所述阵列基板包括：
    栅极层，设于所述衬底基板，所述扫描线、驱动晶体管的栅极设于所述栅极层；
    第一导电层，设于所述栅极层背离所述衬底基板的一侧，所述存储电容的第一电极至少设于所述第一导电层；
    第二导电层，设于所述第一导电层背离所述栅极层一侧，所述存储电容的第二电极至少设于所述第二导电层；
    第三导电层，设于所述第二导电层背离所述第一导电层一侧，所述数据线、电源线、感测线设于所述第三导电层。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括有源层，所述有源层设于所述衬底基板和所述栅极层之间；
    所述存储电容的第一电极包括第一极板和第二极板，所述第一极板设于所述第一导电层，所述第二极板设于所述栅极层，所述第一极板和第二极板通过过孔电连接；所述第二极板还与所述驱动晶体管的栅极电连接；
    所述存储电容的第二电极包括第三极板和第四极板，所述第三极板设于所述第二导电层，所述第四极板至少设于所述有源层背离所述栅极层的一侧，所述第三极板和第四极板通过过孔电连接；所述第三极板还与所述发光单元电连接；
    其中，所述第一极板和第三极板在所述衬底基板的投影具有重叠，形成第一存储电容；所述第一极板和第四极板在所述衬底基板的投影具有重叠，形成第二存储电容；所述第二极板和第四极板在所述衬底基板的投影具有重叠，形成第三存储电容；
    所述第一存储电容、第二存储电容和第三存储电容并联形成所述存 储电容。
  3. 根据权利要求2所述的阵列基板，其中，所述驱动晶体管的栅极复用为所述第二极板。
  4. 根据权利要求3所述的阵列基板，其中，所述阵列基板还包括遮光层，所述遮光层位于所述有源层背离所述栅极层的一侧，且在所述衬底基板上的投影与所述驱动晶体管的栅极具有重叠。
  5. 根据权利要求4所述的阵列基板，其中，所述遮光层复用为所述第四极板。
  6. 根据权利要求5所述的阵列基板，其中，所述阵列基板还包括：
    缓冲层，设于所述有源层和遮光层之间，所述缓冲层上设置有过孔；
    第一层间介质层，设于所述有源层和第一导电层之间，所述第一层间介质层上设置有过孔；
    第二层间介质层，设于所述第一导电层和第二导电层之间，所述第二层间介质层上设置有过孔；
    所述第三极板和第四极板通过所述缓冲层、第一层间介质层和第二层间介质层上的过孔相连。
  7. 根据权利要求6所述的阵列基板，其中，所述缓冲层和第一层间介质层上的过孔采用半色调掩模版通过一步构图工艺形成。
  8. 根据权利要求5所述的阵列基板，其中，所述扫描线包括第一扫描线；
    所述阵列基板还包括第二晶体管，所述第二晶体管的栅极电连接所述第一扫描线，所述第二晶体管的第一级电连接所述数据线，所述第二晶体管的第二级电连接所述驱动晶体管的栅极。
  9. 根据权利要求8所述的阵列基板，其中，所述扫描线还包括第二扫描线；
    所述阵列基板还包括第三晶体管，所述第三晶体管的栅极电连接所述第二扫描线，所述第三晶体管的第一级复用为所述驱动晶体管的第二级，所述第三晶体管的第二级电连接所述感测线。
  10. 根据权利要求9所述的阵列基板，其中，所述阵列基板还包括：
    感测连接部，所述感测连接部设于所述第二导电层，所述感测连接 部与所述第三晶体管的第二级通过过孔电连接；
    所述感测连接部还与所述感测线通过过孔电连接。
  11. 根据权利要求5所述的阵列基板，其中，所述第二导电层和第三导电层之间设置有第三层间介质层和第一平坦层，所述第三层间介质层和第一平坦层上设置有过孔，所述感测连接部和所述感测线通过所述第三层间介质层和第一平坦层上的过孔电连接。
  12. 根据权利要求11所述的阵列基板，其中，所述第三层间介质层和第一平坦层上的过孔采用半色调掩模版通过一步构图工艺形成。
  13. 根据权利要求5所述的阵列基板，其中，所述发光单元包括相对设置的阴极层和阳极层，以及设于所述阴极层和阳极层之间的有机发光层，所述阳极层位于所述第三导电层背离所述衬底基板的一侧，所述阴极层位于所述阳极层背离所述衬底基板的一侧；所述阵列基板还包括：
    辅助阴极层，所述辅助阴极层设于所述阳极层和第三导电层之间，且与所述阴极层电连接。
  14. 根据权利要求13所述的阵列基板，其中，所述辅助阴极层上设有过孔，所述阵列基板还包括：
    绝缘层，设于所述第三导电层和发光单元之间，所述绝缘层上设置有过孔；
    第二平坦层，设于所述绝缘层和发光单元之间，所述第二平坦层上设置有过孔；
    所述阳极层至少通过所述辅助阴极层、绝缘层、第二平坦层上的过孔与所述驱动晶体管的漏极电连接。
  15. 根据权利要求14所述的阵列基板，其中，所述绝缘层和第二平坦层上的过孔采用半色调掩模版通过一步构图工艺形成。
  16. 一种显示装置，其中，包括权利要求1-15中任一项所述的阵列基板。
PCT/CN2021/131947 2021-02-05 2021-11-19 阵列基板和显示装置 WO2022166312A1 (zh)

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