WO2022115985A1

WO2022115985A1 - A novel liner confined cell structure and fabrication method with reduced programming current and thermal cross talk for 3d x-point memory

Info

Publication number: WO2022115985A1
Application number: PCT/CN2020/133051
Authority: WO
Inventors: Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2020-12-01
Filing date: 2020-12-01
Publication date: 2022-06-09
Also published as: CN112655093A; CN112655093B

Abstract

A three-dimensional memory architecture including a top cell array of memory cells, a bottom cell array of memory cells, a plurality of word lines and bit lines are coupled to the arrays. The memory cells are phase change memory (PCM) cells is modified to form a liner confined PCM material formed in the recess of a sacrificial material. Reduced contact area between the electrode and PCM cell and decreased cell material volume leads to less current required for programming the cell. The larger distance between adjacent memory cells results in less thermal cross talk. Having a smaller PCM cell size than selector size allows less of a current density requirement in the current selector (also known as a current limiter or a current steering element) in a resistive switching memory element.

Description

A NOVEL LINER CONFINED CELL STRUCTURE AND FABRICATION METHOD WITH REDUCED PROGRAMMING CURRENT AND THERMAL CROSS TALK FOR 3D X-POINT MEMORY

TECHNICAL FIELD

The present disclosure generally relates to three-dimensional electronic memories, and more particularly, to reducing programming current and thermal cross talk in adjacent memory cells.

BACKGROUND

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells.

Phase-change memory (PCM) is a non-volatile solid-state memory technology that exploits reversible, thermally-assisted switching of phase-change materials like chalcogenide compounds such as GST (Germanium-Antimony-Tellurium) , between states with different electrical resistance. The fundamental storage unit (the “cell” ) can be programmed into a number of different states, or levels, which exhibit different resistance characteristics. Programmable cell-states can be used to represent different data values, permitting storage of information.

PCM cells are programmed or erased by thermal self-heating to induce an amorphous or crystalline state to denote 1 and 0. Programming current is directly proportional to the size and cross-sectional area of the PCM cell. In single-level PCM devices, each cell can be set to one of two states, a “SET” state and a “RESET” state, permitting storage of one bit per cell. In the RESET state, which corresponds to a wholly amorphous state of the phase-change material, the electrical resistance of the cell is very high. By heating to a temperature above its crystallization point and then cooling, the phase-change material can be transformed into a low-resistance, fully-crystalline state. This low-resistance state provides the SET state of the cell. If the cell is then heated to a high temperature, above the melting point of the phase-change material, the material reverts to the fully-amorphous RESET state on rapid cooling.

Due to the nature of thermal self-heating, cross talk occurs when an adjacent cell is programmed. Crosstalk is interference between signals. Due to process-technology scaling, the spacing between adjacent interconnects shrinks. Switching on one signal, can influence another signal. This may, in the worst cases cause a change in value of another cell, or it could delay a signal transition affecting timing. This is classified as a signal integrity issue.

In addition, large programming current requirements also lend to large program voltage requirements due to IR drop (IR =voltage=current x resistance) . Reading and writing of data in PCM cells is achieved by applying appropriate voltages to the phase-change material via a pair of electrodes associated with each cell. In a write operation, the resulting programming signal causes Joule heating of the phase-change material to an appropriate temperature to induce the desired cell-state on cooling. Reading of PCM cells is performed using cell resistance as a metric for cell-state. An applied read voltage causes current to flow through the cell, this current being dependent on resistance of the cell. Measurement of the cell current therefore provides an indication of the programmed cell state. A sufficiently low read voltage is used for this resistance metric to ensure that application of the read voltage does not disturb the programmed cell state. Cell state detection can then be performed by comparing the resistance metric with predefined reference levels. Programming current (I) is typically in the order of 100-200μA. The voltage drop may be significant if the write line (WL) and bit line (BL) in the cell encounters large resistance.

Thus, there is still a need for such a memory cell that provides reduced programming current and reduced thermal cross talk.

SUMMARY

The following summary is included in order to provide a basic understanding of aspects and features of the disclosure. This summary is not an extensive overview and as such it is not intended to particularly identify key or critical elements or to delineate the scope of the disclosure. Its sole purpose is to present concepts in a summarized format.

In one aspect, a new liner confined cell structure for 3D X-Point Memory is presented allowing a reduced programming current and reduced thermal cross talk as compared to current state of the art 3D X-Point Memory cell structures. In the present new cell structure, each stack is composed of a perpendicular word line and bit line with a phase change memory (PCM) in series with an ovonic threshold switch (OTS) in between the word line and the bit line. The PCM memory cell and the OTS selection device are self-aligned to the word line and bit line. The PCM memory cell is composed of a liner confined cell in bit line direction in electrical contact with the OTS selection device.

In another aspect, a method for forming a new recessed liner confined cell structure for 3D X-Point Memory is presented allowing a reduced programming current and reduced thermal cross talk as compared to current state of the art 3D X-Point Memory cell structures. The method includes forming a cross point memory array with parallel bit lines (BL) and perpendicular word lines (WL) . A PCM memory cell in series with an ovonic threshold switch (OTS) is formed at the cross point of the WL and the BL and is self-aligned. A liner confined cell is formed by deposition of sacrificial material on the sidewall of dielectric mesa, removal of the sacrificial material and backfilling with PCM material and planarizing by chemical mechanical polishing (CMP) .

In other aspect, a 3D X-Point Memory Die architecture includes quantities of memory arrays (tiles) separated by a small space. The memory array is composed of multiple memory cells (PCM) with liner confined memory cell and ovonic threshold switch (OTS) .

In accordance with an aspect, a three-dimensional memory with a liner confined cell structure includes a word line and a bit line perpendicular to each other and coupled to at least one memory cell stack; a selector, a modified liner confined phase change memory (lcPCM) cell, a first electrode, a second electrode, and a third electrode contained within the memory cell stack; the lcPCM cell disposed between the first and the second electrodes, and the selector disposed between the second and the third electrodes; the lcPCM cell and the selector confined between the word line and the bit line, and the lcPCM is in series with the selector; a word line direction running parallel to the word line, and a bit line direction running parallel to the bit line; wherein, the lcPCM cell and the selector are self-aligned with respect to the word line and the bit line; and wherein, the lcPCM is formed in the bit line direction and in electrical contact with the selector.

In some arrangements, the lcPCM cell is disposed within a nitride liner.

In some arrangements, the lcPCM cell, the selector, and the first, the second and the third electrodes each have size dimensions relative to the word line and the bit line directions; and the lcPCM is smaller in dimensions relative to the selector for providing reduced required current to the lcPCM.

In some arrangements, the selector is an ovonic threshold switch, and the cell stack further includes an encapsulation layer to protect the lcPCM cell and the ovonic threshold switch.

In some arrangements, the three-dimensional memory includes additional memory cells in a region above or below a two-dimensional region defined by the word line.

In some arrangements, the cell stack further includes a nitride layer, a tungsten layer, an oxide layer, a gap fill layer and the first and the second electrodes are carbon electrodes.

In some arrangements, the gap fill layer contains material selected from a group consisting of cobalt based material, gallium arsenide (GaAs) , indium gallium arsenide (InGaAs) , gallium nitride (GaN) , aluminum nitride (AlN) , cadmium sulfide (CdS) , cadmium selenide (CdSe) , cadmium tellurite (CdTe) , zinc sulfide (ZnS) , lead sulfide (PbS) , and lead selenide (PbSe) , and any combination thereof.

In accordance with another aspect, a three-dimensional X-Point Memory Die architecture with a liner confined cell structure includes a plurality of top arrays or tiles of phase change memory cells; a plurality of bottom arrays or tiles of phase change memory cells; a plurality of bit lines coupled to the top array and coupled to the bottom array; a plurality of word lines, comprising a set of top cell word lines coupled to the top array and a set of bottom cell word lines coupled to the bottom array; and wherein, the top array of memory cells are each separated by a first space defined by adjacent phase change memory cell with a liner confined cell and a selector in the top array, and the bottom array of phase change memory cells are each separated by a second space defined by adjacent phase change memory cell with a liner confined cell and a selector in the bottom array.

In some arrangements, the top and the bottom word lines are coupled thereto.

In some arrangements, the top and the bottom arrays of recess liner confined cells have a reduced size as compared to a selector disposed within each respective array.

In some arrangements, the selector is an ovonic threshold switch.

In yet another aspect, a method of forming a three-dimensional memory with a recess liner confined cell structure includes forming a cross point memory array with a plurality of parallel bit lines and a plurality of perpendicular word lines; self-aligned forming a recess liner confined phase change memory (lcPCM) cell in series with an ovonic threshold switch (OTS) selection device at a cross point of the word line and the bit line; and wherein the lcPCM cell is formed by recessing a sacrificial material to form a recess and deposition of phase change memory cell material in the recess and planarization by chemical mechanical planarization (CMP) .

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects, features and advantages of the present disclosure will be further appreciated when considered with reference to the following description of exemplary embodiments and accompanying drawings, wherein like reference numerals represent like elements. In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be used for the sake of clarity.

However, the aspects of the present disclosure are not intended to be limited to the specific terms used.

Figs. 1A and 1B are isometric views of a prior multi-section and a single section of three-dimensional cross point memory, respectively.

Fig. 2A is an isometric view of a section of a three-dimensional cross point memory, and Fig. 2B is a diagram showing abbreviations for layers in the cell stack.

Figs. 3A and 3B are plan views of a section of a three-dimensional cross point memory showing deposition of a nitride layer, and Fig. 3C is a top view of Fig. 3B.

Fig. 4A is a plan view of a section of a three-dimensional cross point memory showing sacrificial material deposition followed by etching to form liner electrodes. Fig. 4B is a top view of Fig. 4A. Fig. 4C is a plan view of a section of the three-dimensional cross point memory of Fig. 4A showing recess of the sacrificial material and backfilling with PCM material. Fig. 4D is a top view of Fig. 4C.

Figs. 5A and 5B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 4A and 4B showing bottom cell double patterning with a first partial etch to etch through the top electrode and memory cell, stopping on the middle electrode to form parallel lines.

Figs. 6A and 6B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 5A and 5B showing bottom cell etch with a second partial etch to etch to form parallel bottom cell bit lines followed by encapsulation, gap filling and polishing.

Figs. 7A and 7B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 6A and 6B showing word line metal deposition.

Figs. 8A and 8B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 7A and 7B showing bottom cell word line double patterning to form parallel lines.

Figs. 9A and 9B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 8A and 8B showing encapsulation, gap filling and polishing the cell stack.

Figs. 10 is a plan view of the three-dimensional cross point memory in accordance with the embodiment of Figs. 9A and 9B showing a second stack of memory cell deposition on top of the stack shown in Fig. 9A.

Fig. 11 is a plan view of a section of an alternative embodiment of a three-dimensional cross point memory.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to “one embodiment, ” “an embodiment, ” “an example embodiment, ” “some embodiments, ” and the like, merely indicate that the embodiment described may include a particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context.

It should be readily understood that the meaning of “on, ” “above, ” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer there between, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer there between (i.e., directly on something) .

Further, spatially relative terms, such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The term “substrate” as used herein may refer to any workpiece on which formation or treatment of material layers is desired. Non-limiting examples include silicon, germanium, silica, sapphire, zinc oxide, silicon carbide, aluminum nitride, gallium nitride, Spinel, silicon on oxide, silicon carbide on oxide, glass, gallium nitride, indium nitride, aluminum nitride, glasses, combinations or alloys thereof, and other solid materials. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, including but not limited to silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

The term “horizontal” as used herein will be understood to be defined as a plane parallel to the plane or surface of the substrate, regardless of the orientation of the substrate. The term “vertical” will refer to a direction perpendicular to the horizontal as previously defined. Terms such as “above” , “below” , “bottom” , “top” , “side” (e.g. sidewall) , “higher” , “lower” , “upper” , “over” , and “under” , are defined with respect to the horizontal plane. The term “on” means there is direct contact between the elements. The term “above” will allow for intervening elements.

As used herein, a material (e.g. a dielectric material or an electrode material) will be considered to be “crystalline” if it exhibits greater than or equal to 30%crystallinity as measured by a technique such as x-ray diffraction (XRD) . Amorphous material is considered non-crystalline.

As used herein, the terms “first, ” “second, ” and other ordinals will be understood to provide differentiation only, rather than imposing any specific spatial or temporal order.

As used herein, the term “oxide” (of an element) will be understood to include additional components besides the element and oxygen, including but not limited to a dopant or alloy. As used herein, the term “nitride” (of an element) will be understood to include additional components besides the element and nitrogen, including but not limited to a dopant or alloy.

The present technology is applied in the field of three-dimensional memory. A generalized prior example of a three-dimensional (3D) memory is shown in FIG. 1A. In particular, Fig. 1A is an isometric view of a section of three-dimensional crosspoint memory. The memory includes a first layer of memory cells 5 and a second layer of memory cells 10. Between the first layer of memory cells 5 and second layer of memory cells is a number of word lines 15 extending in the X direction. Above the first layer of memory cells 5 is a number of first bit lines 20 extending along the Y direction, and below the second layer of memory cells is a number of second bit lines 25 extending along the Y direction. Further, as can be seen from the figure, the sequential structure of bit lines -memory cells -word lines -memory cells may be repeated along the Z direction to realize a stacked configuration. In any event, an individual memory cell may be accessed by selectively activating the word line and bit line corresponding to the cell.

In FIG. 1B, shown is a single section 100 of the cell structure in FIG. 1A. Shown is a top cell bit line 110 connected to a top cell stack 150. Stack 150 is composed of several layers that will be described herein in the improvement of this standard stack 150. Perpendicular to the top cell bit line 110 is top cell write line 130 and bottom cell write line 140. Connected to bottom cell write line 140 is a bottom cell stack 160. Parallel to top cell bit line 110 is bottom cell bit line 120. Bottom cell bit line 120 is coupled to the bottom cell stack 160. Like cell stack 150, cell stack 160 is also made of several layers. FIGS. 1A and 1B illustrate the general structure of a 3D X-Point Memory cell that terminology is used herein to describe the improvement. The FIG. 1A depicts the section as viewed along the Z (depth) direction. The section includes a number of word lines, e.g. word lines 130, 140, extending in the X (horizontal) direction, a number of top cell bit lines, e.g.,

bit lines

110, 120, extending along the Y (vertical) direction and corresponding to a top cell array of memory cells 150, and a number of bottom cell bit lines extending along the vertical direction and corresponding to a bottom cell array of memory cells 160. The word lines, top cell bit lines, and bottom cell bit lines are typically formed according to a 20 nm /20 nm Line /Space (L/S) pattern and are formed on a silicon substrate. Moreover, the memory may employ complementary metal-oxide semiconductor (CMOS) technology.

As stated above, issues of cross talk may occur with adjacent cells. The present disclosure address this issue and the issue of reducing current required for the memory cell. Adverting to FIG. 2A is a plan view of an exemplary three-dimensional cross point bottom cell stack. Each stack is made of several layers. The cell stacks are similar in function and composition. For the description of materials disclosed herein, similar reference numerals to common elements in various figures denote similar material and functions of the elements shown and described.

In FIG. 2A, shown is a single section 200 of the cell structure of an embodiment. Shown is a bottom cell write line 210 connected to a bottom cell stack 230. Perpendicular to the bottom cell write line 210 is a bottom cell bit line 220. Layer 201 is a nitride layer. Examples of such materials include metal nitrides such as TiN, TiAlN, TaN, BN, metal oxide nitrides such as TiON, metal silicides such as PtSi, semiconductors such as silicon or germanium (with and without doping) , reduced metal oxides such as TiOx (x<2 indicates reduction) , metals such as W, Ni, Co, or carbon based materials. Typically, deposition may be accomplished by chemical vapor deposition (CVD) . In this process, a vacuum deposition method is used to produce high quality, high performance, and solid materials. In typical CVD, the water (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit.

Layers

202a, 202b, and 206c are a-C or electrode layers. The electrodes can be formed of any convenient electrically-conductive material, typically a metallic material (e.g. a pure metal or a metal compound, alloy or other mixture) or a doped semiconductor material such as silicon. Depending on the embodiment, the electrode may be a carbon electrode or any other electrode known to one skilled in the art. Layer 203 is a modified phase change memory (PCM) cell or liner confined PCM 203. FIG. 2A shows the liner confined PCM 203 in an amorphous 203a and crystalline 203b state, respectively. Liner confined PCM 203 is confined in nitride layer 201 as shown in FIG. 2A. The PCM 203 is disposed between

electrodes

202a and 202b in the cell stack as shown in FIG. 2A. Memory cell 203 is disposed into or thereon nitride layer 201. A selector or ovonic threshold switch (OTS) 205 is also disposed between two electrodes, 202b, 202c. FIG. 2B is a diagram showing abbreviations for the various layers described herein. Moreover, while the features described are particularly advantageous for multi-level cells, these features can also be applied to advantage in single-level cells in some embodiments.

As recognized with the present technology described herein, the prior configuration as exemplified in FIGS. 1A, and 1B is inefficient in its use of memory area (or “memory real estate” ) . The configuration is susceptible to cross talk from adjacent cells causing interference with the memory cells. In addition, power requirements are dramatically increased as the number of the cells is increased due to increased need for additional memory. The disclosed new configurations provide improved memory cell density and bit line density as well as reduced cross talk and power required for the memory cell. The new configuration includes a reduced sized PCM 203, 503 in relation to the selector and/or electrodes in its respective stack. This reduced size and cross sectional area may be seen for example starting at a process shown from FIGS. 3A and 3B through to FIG. 10.

FIG. 3A illustrates a bottom cell stack deposition. Layer 301 may be a tungsten based compound, or a cobalt based compound, and functions as a conductor among other things. Depending on the embodiment, the conductor may be made of other materials that have conductive properties.

Layers

202b and 202c are a-C or electrode layers. A selector or ovonic threshold switch (OTC) 205 is disposed between electrode layers 202b and 202c. Layer 302 may be a substrate depending on the embodiment or represent the bottom bit line. In FIG. 3B, shown is a nitride layer 201 deposition covering electrode 202b. In this figure, a first etching occurs to etch through the nitride layer 201 and stops on electrode 202b to form parallel lines of

nitride layer

201a and 201b. Etching, depending on the embodiment, may be accomplished for example using hydrogen peroxide or ammonium hydroxide. Other methods known by those skilled in the art may also be utilized. In FIG. 3C, shown is a top view of the parallel lines of nitride layer 201 formed.

FIG. 4A illustrates a liner sacrificial material deposition step. Liner sacrificial material 404 is disposed between the parallel lines of

nitride layer

201a, 201b. A second etching occurs to etch the liner sacrificial material 404 to form liner

sacrificial layers

404a, 404b, 404c. Nitride material is disposed between the liner

sacrificial layers

404a, 404b, 404c to form parallel lines of

nitride layer

401a, 401b, and chemical mechanical polishing (CMP) treatment occurs, planarizing the nitride-liner sacrificial layer surface 410. FIG. 4B is a top view of the embodiment of FIG 4A, showing resultant alternating parallel lines of

nitride layer

401a, 201a, 401b, 201b and liner

sacrificial layer

404a, 404b, 404c.

FIG. 4C illustrates liner sacrificial layer recess and PCM deposition steps. Liner

sacrificial layers

404a, 404b, 404c are recessed and backfilled with PCM material to form liner confined PCM layer 403a, 403b, 403c. As shown, the liner confined PCM layers 403a, 403b, 403c are disposed between

nitride layers

401a, 201a, 401b, 201b, respectively. Chemical mechanical polishing (CMP) treatment occurs, planarizing the nitride-recess liner confined PCM layer 420. FIG. 4D is a top view of the embodiment of FIG. 4C.

FIG. 5A illustrates an electrode deposition step. As shown, an electrode layer 202a and a nitride layer 501 hard mask are produced. The electrode can be formed of any convenient electrically-conductive material, typically a metallic material (e.g. a pure metal or a metal compound, alloy or other mixture) or a doped semiconductor material such as silicon. Depending on the embodiment, the electrode layer 202a may be a carbon electrode or any other electrode known to one skilled in the art. The nitride layer 501 may be TiN, TiAlN, TaN, BN, metal oxide nitrides such as TiON, metal silicides such as PtSi, semiconductors such as silicon or germanium (with and without doping) , reduced metal oxides such as TiOx (x<2 indicates reduction) , or metals such as W, Ni, Co, or carbon based materials.

FIG. 5B illustrates bottom cell double patterning. A first partial etch occurs to etch through the top electrode 202a and nitride-liner confined PCM 203 and stops on electrode 202b to form parallel lines. Bottom cell double patterning with first etching or partial etching, depending on the embodiment, may be accomplished for example using hydrogen peroxide or ammonium hydroxide or other methods known by those skilled in the art. FIG. 5B illustrates deposition of nitride and

oxide encapsulation

510, 512 to cover

stacks

1, 2, and 3 to protect the exposed electrode and nitride-recess liner confined phase change memory cell in each stack. Encapsulation layer 510 may be composed of silicon nitride or other suitable materials.

Stacks

1, 2, and 3 may be further encapsulated with oxide layer 512 including a substrate.

FIG. 6A illustrates the second etching to etch through the remaining

electrodes

202b, 202c, ovonic thermal switch 205 and conductor 301 to form parallel bottom cell bit lines. Encapsulation layer 610

deposition covering stacks

1, 2, and 3 to protect the now exposed ovonic thermal switch 205 in each stack. After encapsulation, gap fill 601 cover the

stacks

1, 2, and 3. Gap fill may be obtained through atomic layer deposition oxide, Spin on Dielectric (SOD) or flowable chemical vapor deposition (CVD) oxide. Examples of gap fill materials, include, but are not limited to, gallium arsenide (GaAs) , indium gallium arsenide (InGaAs) , gallium nitride (GaN) , aluminum nitride (AlN) , cadmium sulfide (CdS) , cadmium selenide (CdSe) , cadmium tellurite (CdTe) , zinc sulfide (ZnS) , lead sulfide (PbS) and lead selenide (PbSe) and Cobalt based compounds and any combination thereof. FIG. 6B illustrates oxide/nitride chemical mechanical polishing (CMP) treatment to the

stacks

1, 2, and 3. The CMP treatment stops on the carbon electrode 202a as shown in FIG. 6B.

FIG. 7A illustrates a word line metal and nitride metal deposition step. Shown in the X direction, a metal layer 701 and a nitride layer 702 are produced. The metal layer 701 may be tungsten or any other conductor metal. The nitride layer 702 may be TiN, TiAlN, TaN, BN, metal oxide nitrides such as TiON, metal silicides such as PtSi, semiconductors such as silicon or germanium (with and without doping) , reduced metal oxides such as TiOx (x<2 indicates reduction) , metals such as W, Ni, Co, or carbon based materials. Typically deposition may be accomplished by chemical vapor deposition (CVD) . In this process a vacuum deposition method is used to produce high quality, high-performance, solid materials. In typical CVD, the wafer (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit. FIG. 5B is a cross section taken from stack 1 of FIG. 7A along line 7B-7B showing the various layers described in FIG. 7A in the Y direction.

FIGS. 8A and 8B illustrate bottom cell word line double patterning to form parallel bottom cell write lines perpendicular to bit lines that are in contact with the bottom cell top carbon electrode 202a. As shown in FIG. 8B, which is a cross-section of FIG. 8A in a direction 8B-8B, a first partial etch occurs to etch through the top electrode 202a, liner confined PCM 203, and stops on electrode 202b to form parallel lines. Etching, depending on the embodiment, may be accomplished for example using hydrogen peroxide or ammonium hydroxide, or by other methods known by those skilled in the art.

FIGS. 9A and 9B illustrate deposition of nitride and

oxide encapsulation

910, 912 to cover

stacks

1, 2, and 3 to protect the exposed electrode and nitride-recess liner confined phase change memory cell in each stack. Encapsulation layer 910 may be composed of silicon nitride or other suitable materials.

Stacks

1, 2, and 3 may be further encapsulated with oxide layer 912 including a substrate. Bottom cell write line etching then occurs with a second etching to etch through the remaining

electrodes

202b, 202c, ovonic thermal switch 205, and conductor 301 to form parallel bottom cell word lines. Encapsulation layer 914

deposition covering stacks

1, 2, and 3 to protect the now exposed ovonic thermal switch 205 in each stack. After encapsulation, gap fill 9 cover the

stacks

801, 802, and 803. Gap fill may be obtained through atomic layer deposition oxide, Spin on Dielectric (SOD) or flowable chemical vapor deposition (CVD) oxide. Oxide chemical mechanical polishing (CMP) is done and stopped in conductor 701, as shown in FIG. 9B. Again depending on the embodiment conductor 701 may be tungsten (W) or another conductive material

FIG. 10 illustrates a second stack of memory cell deposition and patterning with the new cell structure described herein with a recess and reduced dimension. Shown is top section 1010 and bottom section 1030 both having reduced phase change memory cells 203 relative to

electrodes

202a, 202b, 202c and selector 205. Top cell and bottom cell write lines 1020 separate the two stacks. Oxide/nitride chemical mechanical polishing (CMP) treatment to the

stacks

1001, 1002, and 1003. The CMP treatment stops on conductor 701 as shown in FIG. 9B.

FIG. 11 illustrates a single section 1100 of the cell structure of another embodiment. Shown is liner confined PCM 203 disposed within nitride liner 201. The nitride liner 201 and liner confined PCM 201 are disposed between metal electrodes 1101a and 1101b. Metal electrodes 1101a and 1101b may be tungsten or any other conductor metal. This embodiment could utilize all other elements of the embodiment described in FIGS. 2A-10.

Most of the foregoing alternative examples are not mutually exclusive, but may be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above may be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. As an example, the preceding operations do not have to be performed in the precise order described above. Rather, various steps can be handled in a different order, such as reversed, or simultaneously. Steps can also be omitted unless otherwise stated. In addition, the provision of the examples described herein, as well as clauses phrased as "such as, " "including" and the like, should not be interpreted as limiting the subject matter of the claims to the specific examples; rather, the examples are intended to illustrate only one of many possible embodiments. Further, the same reference numbers in different drawings may identify the same or similar elements.

Although the present disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

A three-dimensional memory with a liner confined cell structure, comprising:

a word line and a bit line perpendicular to each other and coupled to at least one memory cell stack;

a selector, a modified liner confined phase change memory (lcPCM) cell, a first electrode, a second electrode, and a third electrode contained within the memory cell stack;

the lcPCM cell disposed between the first and the second electrodes, and the selector disposed between the second and the third electrodes;

the lcPCM cell and the selector are confined between the word line and the bit line, and the lcPCM is in series with the selector;

a word line direction running parallel to the word line, and a bit line direction running parallel to the bit line;

wherein, the lcPCM cell and the selector are self-aligned with respect to the word line and the bit line; and

wherein, the lcPCM is formed in the bit line direction and in electrical contact with the selector.
The three-dimensional memory according to claim 1, wherein the lcPCM cell is disposed within a nitride liner.
The three-dimensional memory according to claim 1, wherein, the lcPCM cell, the selector, and the first, the second and the third electrodes each having size dimensions relative to the word line and the bit line directions; and the lcPCM is smaller in dimension relative to the selector for providing reduced required current to the lcPCM.
The three-dimensional memory according to claim 1, wherein the selector is an ovonic threshold switch, and the cell stack further includes an encapsulation layer to protect the lcPCM cell and the ovonic threshold switch.
The three-dimensional memory according to claim 1, further comprising additional memory cells in a region above or below a two-dimensional region defined by the word line.
The three-dimensional memory according to claim 1, wherein the cell stack further includes a nitride layer, a tungsten layer, an oxide layer, a gap fill layer and the first and the second electrodes are carbon electrodes.
The three-dimensional memory according to claim 6, wherein the gap fill layer contains material selected from a group consisting of cobalt based material, gallium arsenide (GaAs) , indium gallium arsenide (InGaAs) , gallium nitride (GaN) , aluminum nitride (AlN) , cadmium sulfide (CdS) , cadmium selenide (CdSe) , cadmium tellurite (CdTe) , zinc sulfide (ZnS) , lead sulfide (PbS) , and lead selenide (PbSe) , and any combination thereof.
A three-dimensional X-Point Memory Die architecture with a liner confined cell structure, comprising:

a plurality of top arrays or tiles of phase change memory cells;

a plurality of bottom arrays or tiles of phase change memory cells;

a plurality of bit lines coupled to the top array and coupled to the bottom array;

a plurality of word lines, comprising a set of top cell word lines coupled to the top array and a set of bottom cell word lines coupled to the bottom array; and

wherein, the top array of memory cells are each separated by a first space defined by adjacent phase change memory cell with a liner confined cell and a selector in the top array, and the bottom array of phase change memory cells are each separated by a second space defined by adjacent phase change memory cell with a liner confined cell and a selector in the bottom array.
The three-dimensional architecture according to claim 8, wherein the top and the bottom word lines are coupled thereto.
The three-dimensional architecture according to claim 8, wherein the top and the bottom arrays of liner confined cells have a reduced size as compared to a selector disposed within each respective array.
The three-dimensional architecture according to claim 8, wherein the selector is an ovonic threshold switch.
A method of forming a three-dimensional memory with a recess liner confined cell structure comprising:

forming a cross point memory array with a plurality of parallel bit lines and a plurality of perpendicular word lines;

self-alignedly forming a liner confined phase change memory (lcPCM) cell in series with an ovonic threshold switch (OTS) selection device at a cross point of the word line and the bit line; and

wherein, the lcPCM cell is formed by recessing a sacrificial material to form a recess and deposition of phase change memory cell material in the recess and planarization by chemical mechanical planarization (CMP) .